1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,x1e80100-gcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "clk-regmap-divider.h" 19 #include "clk-regmap-mux.h" 20 #include "clk-regmap-phy-mux.h" 21 #include "gdsc.h" 22 #include "reset.h" 23 24 enum { 25 DT_BI_TCXO, 26 DT_SLEEP_CLK, 27 DT_PCIE_3_PIPE, 28 DT_PCIE_4_PIPE, 29 DT_PCIE_5_PIPE, 30 DT_PCIE_6A_PIPE, 31 DT_PCIE_6B_PIPE, 32 DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE, 33 DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE, 34 DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE, 35 }; 36 37 enum { 38 P_BI_TCXO, 39 P_GCC_GPLL0_OUT_EVEN, 40 P_GCC_GPLL0_OUT_MAIN, 41 P_GCC_GPLL4_OUT_MAIN, 42 P_GCC_GPLL7_OUT_MAIN, 43 P_GCC_GPLL8_OUT_MAIN, 44 P_GCC_GPLL9_OUT_MAIN, 45 P_SLEEP_CLK, 46 P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 47 P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 48 P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 49 }; 50 51 static struct clk_alpha_pll gcc_gpll0 = { 52 .offset = 0x0, 53 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 54 .clkr = { 55 .enable_reg = 0x52030, 56 .enable_mask = BIT(0), 57 .hw.init = &(const struct clk_init_data) { 58 .name = "gcc_gpll0", 59 .parent_data = &(const struct clk_parent_data) { 60 .index = DT_BI_TCXO, 61 }, 62 .num_parents = 1, 63 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 64 }, 65 }, 66 }; 67 68 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 69 { 0x1, 2 }, 70 { } 71 }; 72 73 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 74 .offset = 0x0, 75 .post_div_shift = 10, 76 .post_div_table = post_div_table_gcc_gpll0_out_even, 77 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 78 .width = 4, 79 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 80 .clkr.hw.init = &(const struct clk_init_data) { 81 .name = "gcc_gpll0_out_even", 82 .parent_hws = (const struct clk_hw*[]) { 83 &gcc_gpll0.clkr.hw, 84 }, 85 .num_parents = 1, 86 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 87 }, 88 }; 89 90 static struct clk_alpha_pll gcc_gpll4 = { 91 .offset = 0x4000, 92 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 93 .clkr = { 94 .enable_reg = 0x52030, 95 .enable_mask = BIT(4), 96 .hw.init = &(const struct clk_init_data) { 97 .name = "gcc_gpll4", 98 .parent_data = &(const struct clk_parent_data) { 99 .index = DT_BI_TCXO, 100 }, 101 .num_parents = 1, 102 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 103 }, 104 }, 105 }; 106 107 static struct clk_alpha_pll gcc_gpll7 = { 108 .offset = 0x7000, 109 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 110 .clkr = { 111 .enable_reg = 0x52030, 112 .enable_mask = BIT(7), 113 .hw.init = &(const struct clk_init_data) { 114 .name = "gcc_gpll7", 115 .parent_data = &(const struct clk_parent_data) { 116 .index = DT_BI_TCXO, 117 }, 118 .num_parents = 1, 119 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 120 }, 121 }, 122 }; 123 124 static struct clk_alpha_pll gcc_gpll8 = { 125 .offset = 0x8000, 126 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 127 .clkr = { 128 .enable_reg = 0x52030, 129 .enable_mask = BIT(8), 130 .hw.init = &(const struct clk_init_data) { 131 .name = "gcc_gpll8", 132 .parent_data = &(const struct clk_parent_data) { 133 .index = DT_BI_TCXO, 134 }, 135 .num_parents = 1, 136 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 137 }, 138 }, 139 }; 140 141 static struct clk_alpha_pll gcc_gpll9 = { 142 .offset = 0x9000, 143 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 144 .clkr = { 145 .enable_reg = 0x52030, 146 .enable_mask = BIT(9), 147 .hw.init = &(const struct clk_init_data) { 148 .name = "gcc_gpll9", 149 .parent_data = &(const struct clk_parent_data) { 150 .index = DT_BI_TCXO, 151 }, 152 .num_parents = 1, 153 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 154 }, 155 }, 156 }; 157 158 static const struct parent_map gcc_parent_map_0[] = { 159 { P_BI_TCXO, 0 }, 160 { P_GCC_GPLL0_OUT_MAIN, 1 }, 161 { P_GCC_GPLL0_OUT_EVEN, 6 }, 162 }; 163 164 static const struct clk_parent_data gcc_parent_data_0[] = { 165 { .index = DT_BI_TCXO }, 166 { .hw = &gcc_gpll0.clkr.hw }, 167 { .hw = &gcc_gpll0_out_even.clkr.hw }, 168 }; 169 170 static const struct parent_map gcc_parent_map_1[] = { 171 { P_BI_TCXO, 0 }, 172 { P_SLEEP_CLK, 5 }, 173 }; 174 175 static const struct clk_parent_data gcc_parent_data_1[] = { 176 { .index = DT_BI_TCXO }, 177 { .index = DT_SLEEP_CLK }, 178 }; 179 180 static const struct parent_map gcc_parent_map_2[] = { 181 { P_BI_TCXO, 0 }, 182 { P_GCC_GPLL0_OUT_MAIN, 1 }, 183 { P_SLEEP_CLK, 5 }, 184 { P_GCC_GPLL0_OUT_EVEN, 6 }, 185 }; 186 187 static const struct clk_parent_data gcc_parent_data_2[] = { 188 { .index = DT_BI_TCXO }, 189 { .hw = &gcc_gpll0.clkr.hw }, 190 { .index = DT_SLEEP_CLK }, 191 { .hw = &gcc_gpll0_out_even.clkr.hw }, 192 }; 193 194 static const struct parent_map gcc_parent_map_3[] = { 195 { P_BI_TCXO, 0 }, 196 }; 197 198 static const struct clk_parent_data gcc_parent_data_3[] = { 199 { .index = DT_BI_TCXO }, 200 }; 201 202 static const struct parent_map gcc_parent_map_4[] = { 203 { P_BI_TCXO, 0 }, 204 { P_GCC_GPLL0_OUT_MAIN, 1 }, 205 { P_GCC_GPLL8_OUT_MAIN, 2 }, 206 { P_GCC_GPLL0_OUT_EVEN, 6 }, 207 }; 208 209 static const struct clk_parent_data gcc_parent_data_4[] = { 210 { .index = DT_BI_TCXO }, 211 { .hw = &gcc_gpll0.clkr.hw }, 212 { .hw = &gcc_gpll8.clkr.hw }, 213 { .hw = &gcc_gpll0_out_even.clkr.hw }, 214 }; 215 216 static const struct parent_map gcc_parent_map_5[] = { 217 { P_BI_TCXO, 0 }, 218 { P_GCC_GPLL0_OUT_MAIN, 1 }, 219 { P_GCC_GPLL7_OUT_MAIN, 2 }, 220 { P_SLEEP_CLK, 5 }, 221 }; 222 223 static const struct clk_parent_data gcc_parent_data_5[] = { 224 { .index = DT_BI_TCXO }, 225 { .hw = &gcc_gpll0.clkr.hw }, 226 { .hw = &gcc_gpll7.clkr.hw }, 227 { .index = DT_SLEEP_CLK }, 228 }; 229 230 static const struct parent_map gcc_parent_map_6[] = { 231 { P_BI_TCXO, 0 }, 232 { P_GCC_GPLL0_OUT_MAIN, 1 }, 233 { P_GCC_GPLL7_OUT_MAIN, 2 }, 234 }; 235 236 static const struct clk_parent_data gcc_parent_data_6[] = { 237 { .index = DT_BI_TCXO }, 238 { .hw = &gcc_gpll0.clkr.hw }, 239 { .hw = &gcc_gpll7.clkr.hw }, 240 }; 241 242 static const struct parent_map gcc_parent_map_7[] = { 243 { P_BI_TCXO, 0 }, 244 { P_GCC_GPLL0_OUT_MAIN, 1 }, 245 { P_GCC_GPLL4_OUT_MAIN, 5 }, 246 { P_GCC_GPLL0_OUT_EVEN, 6 }, 247 }; 248 249 static const struct clk_parent_data gcc_parent_data_7[] = { 250 { .index = DT_BI_TCXO }, 251 { .hw = &gcc_gpll0.clkr.hw }, 252 { .hw = &gcc_gpll4.clkr.hw }, 253 { .hw = &gcc_gpll0_out_even.clkr.hw }, 254 }; 255 256 static const struct parent_map gcc_parent_map_8[] = { 257 { P_BI_TCXO, 0 }, 258 { P_GCC_GPLL0_OUT_MAIN, 1 }, 259 { P_GCC_GPLL7_OUT_MAIN, 2 }, 260 { P_GCC_GPLL0_OUT_EVEN, 6 }, 261 }; 262 263 static const struct clk_parent_data gcc_parent_data_8[] = { 264 { .index = DT_BI_TCXO }, 265 { .hw = &gcc_gpll0.clkr.hw }, 266 { .hw = &gcc_gpll7.clkr.hw }, 267 { .hw = &gcc_gpll0_out_even.clkr.hw }, 268 }; 269 270 static const struct parent_map gcc_parent_map_9[] = { 271 { P_BI_TCXO, 0 }, 272 { P_GCC_GPLL0_OUT_MAIN, 1 }, 273 { P_GCC_GPLL9_OUT_MAIN, 2 }, 274 { P_GCC_GPLL4_OUT_MAIN, 5 }, 275 { P_GCC_GPLL0_OUT_EVEN, 6 }, 276 }; 277 278 static const struct clk_parent_data gcc_parent_data_10[] = { 279 { .index = DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE }, 280 { .index = DT_BI_TCXO }, 281 }; 282 283 static const struct parent_map gcc_parent_map_10[] = { 284 { P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 285 { P_BI_TCXO, 2 }, 286 }; 287 288 static const struct clk_parent_data gcc_parent_data_11[] = { 289 { .index = DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE }, 290 { .index = DT_BI_TCXO }, 291 }; 292 293 static const struct parent_map gcc_parent_map_11[] = { 294 { P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 295 { P_BI_TCXO, 2 }, 296 }; 297 298 static const struct clk_parent_data gcc_parent_data_12[] = { 299 { .index = DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE }, 300 { .index = DT_BI_TCXO }, 301 }; 302 303 static const struct parent_map gcc_parent_map_12[] = { 304 { P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 305 { P_BI_TCXO, 2 }, 306 }; 307 308 static const struct clk_parent_data gcc_parent_data_9[] = { 309 { .index = DT_BI_TCXO }, 310 { .hw = &gcc_gpll0.clkr.hw }, 311 { .hw = &gcc_gpll9.clkr.hw }, 312 { .hw = &gcc_gpll4.clkr.hw }, 313 { .hw = &gcc_gpll0_out_even.clkr.hw }, 314 }; 315 316 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 317 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 318 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 319 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 320 { } 321 }; 322 323 static struct clk_rcg2 gcc_gp1_clk_src = { 324 .cmd_rcgr = 0x64004, 325 .mnd_width = 16, 326 .hid_width = 5, 327 .parent_map = gcc_parent_map_2, 328 .freq_tbl = ftbl_gcc_gp1_clk_src, 329 .clkr.hw.init = &(const struct clk_init_data) { 330 .name = "gcc_gp1_clk_src", 331 .parent_data = gcc_parent_data_2, 332 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 333 .flags = CLK_SET_RATE_PARENT, 334 .ops = &clk_rcg2_shared_ops, 335 }, 336 }; 337 338 static struct clk_rcg2 gcc_gp2_clk_src = { 339 .cmd_rcgr = 0x65004, 340 .mnd_width = 16, 341 .hid_width = 5, 342 .parent_map = gcc_parent_map_2, 343 .freq_tbl = ftbl_gcc_gp1_clk_src, 344 .clkr.hw.init = &(const struct clk_init_data) { 345 .name = "gcc_gp2_clk_src", 346 .parent_data = gcc_parent_data_2, 347 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 348 .flags = CLK_SET_RATE_PARENT, 349 .ops = &clk_rcg2_shared_ops, 350 }, 351 }; 352 353 static struct clk_rcg2 gcc_gp3_clk_src = { 354 .cmd_rcgr = 0x66004, 355 .mnd_width = 16, 356 .hid_width = 5, 357 .parent_map = gcc_parent_map_2, 358 .freq_tbl = ftbl_gcc_gp1_clk_src, 359 .clkr.hw.init = &(const struct clk_init_data) { 360 .name = "gcc_gp3_clk_src", 361 .parent_data = gcc_parent_data_2, 362 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 363 .flags = CLK_SET_RATE_PARENT, 364 .ops = &clk_rcg2_shared_ops, 365 }, 366 }; 367 368 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 369 F(19200000, P_BI_TCXO, 1, 0, 0), 370 { } 371 }; 372 373 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 374 .cmd_rcgr = 0xa0180, 375 .mnd_width = 16, 376 .hid_width = 5, 377 .parent_map = gcc_parent_map_1, 378 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 379 .clkr.hw.init = &(const struct clk_init_data) { 380 .name = "gcc_pcie_0_aux_clk_src", 381 .parent_data = gcc_parent_data_1, 382 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 383 .flags = CLK_SET_RATE_PARENT, 384 .ops = &clk_rcg2_shared_ops, 385 }, 386 }; 387 388 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 389 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 390 { } 391 }; 392 393 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 394 .cmd_rcgr = 0xa0054, 395 .mnd_width = 0, 396 .hid_width = 5, 397 .parent_map = gcc_parent_map_0, 398 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 399 .clkr.hw.init = &(const struct clk_init_data) { 400 .name = "gcc_pcie_0_phy_rchng_clk_src", 401 .parent_data = gcc_parent_data_0, 402 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 403 .flags = CLK_SET_RATE_PARENT, 404 .ops = &clk_rcg2_shared_ops, 405 }, 406 }; 407 408 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 409 .cmd_rcgr = 0x2c180, 410 .mnd_width = 16, 411 .hid_width = 5, 412 .parent_map = gcc_parent_map_1, 413 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 414 .clkr.hw.init = &(const struct clk_init_data) { 415 .name = "gcc_pcie_1_aux_clk_src", 416 .parent_data = gcc_parent_data_1, 417 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 418 .flags = CLK_SET_RATE_PARENT, 419 .ops = &clk_rcg2_shared_ops, 420 }, 421 }; 422 423 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { 424 .cmd_rcgr = 0x2c054, 425 .mnd_width = 0, 426 .hid_width = 5, 427 .parent_map = gcc_parent_map_0, 428 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 429 .clkr.hw.init = &(const struct clk_init_data) { 430 .name = "gcc_pcie_1_phy_rchng_clk_src", 431 .parent_data = gcc_parent_data_0, 432 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 433 .flags = CLK_SET_RATE_PARENT, 434 .ops = &clk_rcg2_shared_ops, 435 }, 436 }; 437 438 static struct clk_rcg2 gcc_pcie_2_aux_clk_src = { 439 .cmd_rcgr = 0x13180, 440 .mnd_width = 16, 441 .hid_width = 5, 442 .parent_map = gcc_parent_map_1, 443 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 444 .clkr.hw.init = &(const struct clk_init_data) { 445 .name = "gcc_pcie_2_aux_clk_src", 446 .parent_data = gcc_parent_data_1, 447 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 448 .flags = CLK_SET_RATE_PARENT, 449 .ops = &clk_rcg2_shared_ops, 450 }, 451 }; 452 453 static struct clk_rcg2 gcc_pcie_2_phy_rchng_clk_src = { 454 .cmd_rcgr = 0x13054, 455 .mnd_width = 0, 456 .hid_width = 5, 457 .parent_map = gcc_parent_map_0, 458 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 459 .clkr.hw.init = &(const struct clk_init_data) { 460 .name = "gcc_pcie_2_phy_rchng_clk_src", 461 .parent_data = gcc_parent_data_0, 462 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 463 .flags = CLK_SET_RATE_PARENT, 464 .ops = &clk_rcg2_shared_ops, 465 }, 466 }; 467 468 static struct clk_rcg2 gcc_pcie_3_aux_clk_src = { 469 .cmd_rcgr = 0x5808c, 470 .mnd_width = 16, 471 .hid_width = 5, 472 .parent_map = gcc_parent_map_1, 473 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 474 .clkr.hw.init = &(const struct clk_init_data) { 475 .name = "gcc_pcie_3_aux_clk_src", 476 .parent_data = gcc_parent_data_1, 477 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 478 .flags = CLK_SET_RATE_PARENT, 479 .ops = &clk_rcg2_shared_ops, 480 }, 481 }; 482 483 static struct clk_rcg2 gcc_pcie_3_phy_rchng_clk_src = { 484 .cmd_rcgr = 0x58070, 485 .mnd_width = 0, 486 .hid_width = 5, 487 .parent_map = gcc_parent_map_0, 488 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 489 .clkr.hw.init = &(const struct clk_init_data) { 490 .name = "gcc_pcie_3_phy_rchng_clk_src", 491 .parent_data = gcc_parent_data_0, 492 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 493 .flags = CLK_SET_RATE_PARENT, 494 .ops = &clk_rcg2_shared_ops, 495 }, 496 }; 497 498 static struct clk_rcg2 gcc_pcie_4_aux_clk_src = { 499 .cmd_rcgr = 0x6b080, 500 .mnd_width = 16, 501 .hid_width = 5, 502 .parent_map = gcc_parent_map_1, 503 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 504 .clkr.hw.init = &(const struct clk_init_data) { 505 .name = "gcc_pcie_4_aux_clk_src", 506 .parent_data = gcc_parent_data_1, 507 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 508 .flags = CLK_SET_RATE_PARENT, 509 .ops = &clk_rcg2_shared_ops, 510 }, 511 }; 512 513 static struct clk_rcg2 gcc_pcie_4_phy_rchng_clk_src = { 514 .cmd_rcgr = 0x6b064, 515 .mnd_width = 0, 516 .hid_width = 5, 517 .parent_map = gcc_parent_map_0, 518 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 519 .clkr.hw.init = &(const struct clk_init_data) { 520 .name = "gcc_pcie_4_phy_rchng_clk_src", 521 .parent_data = gcc_parent_data_0, 522 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 523 .flags = CLK_SET_RATE_PARENT, 524 .ops = &clk_rcg2_shared_ops, 525 }, 526 }; 527 528 static struct clk_rcg2 gcc_pcie_5_aux_clk_src = { 529 .cmd_rcgr = 0x2f080, 530 .mnd_width = 16, 531 .hid_width = 5, 532 .parent_map = gcc_parent_map_1, 533 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 534 .clkr.hw.init = &(const struct clk_init_data) { 535 .name = "gcc_pcie_5_aux_clk_src", 536 .parent_data = gcc_parent_data_1, 537 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 538 .flags = CLK_SET_RATE_PARENT, 539 .ops = &clk_rcg2_shared_ops, 540 }, 541 }; 542 543 static struct clk_rcg2 gcc_pcie_5_phy_rchng_clk_src = { 544 .cmd_rcgr = 0x2f064, 545 .mnd_width = 0, 546 .hid_width = 5, 547 .parent_map = gcc_parent_map_0, 548 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 549 .clkr.hw.init = &(const struct clk_init_data) { 550 .name = "gcc_pcie_5_phy_rchng_clk_src", 551 .parent_data = gcc_parent_data_0, 552 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 553 .flags = CLK_SET_RATE_PARENT, 554 .ops = &clk_rcg2_shared_ops, 555 }, 556 }; 557 558 static struct clk_rcg2 gcc_pcie_6a_aux_clk_src = { 559 .cmd_rcgr = 0x3108c, 560 .mnd_width = 16, 561 .hid_width = 5, 562 .parent_map = gcc_parent_map_1, 563 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 564 .clkr.hw.init = &(const struct clk_init_data) { 565 .name = "gcc_pcie_6a_aux_clk_src", 566 .parent_data = gcc_parent_data_1, 567 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 568 .flags = CLK_SET_RATE_PARENT, 569 .ops = &clk_rcg2_shared_ops, 570 }, 571 }; 572 573 static struct clk_rcg2 gcc_pcie_6a_phy_rchng_clk_src = { 574 .cmd_rcgr = 0x31070, 575 .mnd_width = 0, 576 .hid_width = 5, 577 .parent_map = gcc_parent_map_0, 578 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 579 .clkr.hw.init = &(const struct clk_init_data) { 580 .name = "gcc_pcie_6a_phy_rchng_clk_src", 581 .parent_data = gcc_parent_data_0, 582 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 583 .flags = CLK_SET_RATE_PARENT, 584 .ops = &clk_rcg2_shared_ops, 585 }, 586 }; 587 588 static struct clk_rcg2 gcc_pcie_6b_aux_clk_src = { 589 .cmd_rcgr = 0x8d08c, 590 .mnd_width = 16, 591 .hid_width = 5, 592 .parent_map = gcc_parent_map_1, 593 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 594 .clkr.hw.init = &(const struct clk_init_data) { 595 .name = "gcc_pcie_6b_aux_clk_src", 596 .parent_data = gcc_parent_data_1, 597 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 598 .flags = CLK_SET_RATE_PARENT, 599 .ops = &clk_rcg2_shared_ops, 600 }, 601 }; 602 603 static struct clk_rcg2 gcc_pcie_6b_phy_rchng_clk_src = { 604 .cmd_rcgr = 0x8d070, 605 .mnd_width = 0, 606 .hid_width = 5, 607 .parent_map = gcc_parent_map_0, 608 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 609 .clkr.hw.init = &(const struct clk_init_data) { 610 .name = "gcc_pcie_6b_phy_rchng_clk_src", 611 .parent_data = gcc_parent_data_0, 612 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 613 .flags = CLK_SET_RATE_PARENT, 614 .ops = &clk_rcg2_shared_ops, 615 }, 616 }; 617 618 static struct clk_rcg2 gcc_pcie_rscc_xo_clk_src = { 619 .cmd_rcgr = 0xa400c, 620 .mnd_width = 0, 621 .hid_width = 5, 622 .parent_map = gcc_parent_map_3, 623 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 624 .clkr.hw.init = &(const struct clk_init_data) { 625 .name = "gcc_pcie_rscc_xo_clk_src", 626 .parent_data = gcc_parent_data_3, 627 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 628 .flags = CLK_SET_RATE_PARENT, 629 .ops = &clk_rcg2_shared_ops, 630 }, 631 }; 632 633 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 634 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 635 { } 636 }; 637 638 static struct clk_rcg2 gcc_pdm2_clk_src = { 639 .cmd_rcgr = 0x33010, 640 .mnd_width = 0, 641 .hid_width = 5, 642 .parent_map = gcc_parent_map_0, 643 .freq_tbl = ftbl_gcc_pdm2_clk_src, 644 .clkr.hw.init = &(const struct clk_init_data) { 645 .name = "gcc_pdm2_clk_src", 646 .parent_data = gcc_parent_data_0, 647 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 648 .flags = CLK_SET_RATE_PARENT, 649 .ops = &clk_rcg2_shared_ops, 650 }, 651 }; 652 653 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 654 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 655 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 656 F(19200000, P_BI_TCXO, 1, 0, 0), 657 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 658 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 659 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 660 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 661 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 662 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 663 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 664 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 665 { } 666 }; 667 668 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 669 .name = "gcc_qupv3_wrap0_s0_clk_src", 670 .parent_data = gcc_parent_data_0, 671 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 672 .flags = CLK_SET_RATE_PARENT, 673 .ops = &clk_rcg2_ops, 674 }; 675 676 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 677 .cmd_rcgr = 0x42010, 678 .mnd_width = 16, 679 .hid_width = 5, 680 .parent_map = gcc_parent_map_0, 681 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 682 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 683 }; 684 685 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 686 .name = "gcc_qupv3_wrap0_s1_clk_src", 687 .parent_data = gcc_parent_data_0, 688 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 689 .flags = CLK_SET_RATE_PARENT, 690 .ops = &clk_rcg2_ops, 691 }; 692 693 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 694 .cmd_rcgr = 0x42148, 695 .mnd_width = 16, 696 .hid_width = 5, 697 .parent_map = gcc_parent_map_0, 698 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 699 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 700 }; 701 702 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = { 703 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 704 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 705 F(19200000, P_BI_TCXO, 1, 0, 0), 706 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 707 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 708 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 709 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 710 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 711 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 712 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 713 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 714 { } 715 }; 716 717 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 718 .name = "gcc_qupv3_wrap0_s2_clk_src", 719 .parent_data = gcc_parent_data_0, 720 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 721 .flags = CLK_SET_RATE_PARENT, 722 .ops = &clk_rcg2_ops, 723 }; 724 725 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 726 .cmd_rcgr = 0x42288, 727 .mnd_width = 16, 728 .hid_width = 5, 729 .parent_map = gcc_parent_map_0, 730 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 731 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 732 }; 733 734 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 735 .name = "gcc_qupv3_wrap0_s3_clk_src", 736 .parent_data = gcc_parent_data_0, 737 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 738 .flags = CLK_SET_RATE_PARENT, 739 .ops = &clk_rcg2_ops, 740 }; 741 742 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 743 .cmd_rcgr = 0x423c8, 744 .mnd_width = 16, 745 .hid_width = 5, 746 .parent_map = gcc_parent_map_0, 747 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 748 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 749 }; 750 751 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s4_clk_src[] = { 752 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 753 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 754 F(19200000, P_BI_TCXO, 1, 0, 0), 755 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 756 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 757 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 758 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 759 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 760 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 761 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 762 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 763 { } 764 }; 765 766 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 767 .name = "gcc_qupv3_wrap0_s4_clk_src", 768 .parent_data = gcc_parent_data_0, 769 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 770 .flags = CLK_SET_RATE_PARENT, 771 .ops = &clk_rcg2_ops, 772 }; 773 774 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 775 .cmd_rcgr = 0x42500, 776 .mnd_width = 16, 777 .hid_width = 5, 778 .parent_map = gcc_parent_map_0, 779 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 780 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 781 }; 782 783 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 784 .name = "gcc_qupv3_wrap0_s5_clk_src", 785 .parent_data = gcc_parent_data_0, 786 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 787 .flags = CLK_SET_RATE_PARENT, 788 .ops = &clk_rcg2_ops, 789 }; 790 791 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 792 .cmd_rcgr = 0x42638, 793 .mnd_width = 16, 794 .hid_width = 5, 795 .parent_map = gcc_parent_map_0, 796 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 797 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 798 }; 799 800 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 801 .name = "gcc_qupv3_wrap0_s6_clk_src", 802 .parent_data = gcc_parent_data_0, 803 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 804 .flags = CLK_SET_RATE_PARENT, 805 .ops = &clk_rcg2_ops, 806 }; 807 808 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 809 .cmd_rcgr = 0x42770, 810 .mnd_width = 16, 811 .hid_width = 5, 812 .parent_map = gcc_parent_map_0, 813 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 814 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 815 }; 816 817 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 818 .name = "gcc_qupv3_wrap0_s7_clk_src", 819 .parent_data = gcc_parent_data_0, 820 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 821 .flags = CLK_SET_RATE_PARENT, 822 .ops = &clk_rcg2_ops, 823 }; 824 825 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 826 .cmd_rcgr = 0x428a8, 827 .mnd_width = 16, 828 .hid_width = 5, 829 .parent_map = gcc_parent_map_0, 830 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 831 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 832 }; 833 834 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 835 .name = "gcc_qupv3_wrap1_s0_clk_src", 836 .parent_data = gcc_parent_data_0, 837 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 838 .flags = CLK_SET_RATE_PARENT, 839 .ops = &clk_rcg2_ops, 840 }; 841 842 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 843 .cmd_rcgr = 0x18010, 844 .mnd_width = 16, 845 .hid_width = 5, 846 .parent_map = gcc_parent_map_0, 847 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 848 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 849 }; 850 851 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 852 .name = "gcc_qupv3_wrap1_s1_clk_src", 853 .parent_data = gcc_parent_data_0, 854 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 855 .flags = CLK_SET_RATE_PARENT, 856 .ops = &clk_rcg2_ops, 857 }; 858 859 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 860 .cmd_rcgr = 0x18148, 861 .mnd_width = 16, 862 .hid_width = 5, 863 .parent_map = gcc_parent_map_0, 864 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 865 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 866 }; 867 868 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 869 .name = "gcc_qupv3_wrap1_s2_clk_src", 870 .parent_data = gcc_parent_data_0, 871 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 872 .flags = CLK_SET_RATE_PARENT, 873 .ops = &clk_rcg2_ops, 874 }; 875 876 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 877 .cmd_rcgr = 0x18288, 878 .mnd_width = 16, 879 .hid_width = 5, 880 .parent_map = gcc_parent_map_0, 881 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 882 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 883 }; 884 885 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 886 .name = "gcc_qupv3_wrap1_s3_clk_src", 887 .parent_data = gcc_parent_data_0, 888 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 889 .flags = CLK_SET_RATE_PARENT, 890 .ops = &clk_rcg2_ops, 891 }; 892 893 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 894 .cmd_rcgr = 0x183c8, 895 .mnd_width = 16, 896 .hid_width = 5, 897 .parent_map = gcc_parent_map_0, 898 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 899 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 900 }; 901 902 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 903 .name = "gcc_qupv3_wrap1_s4_clk_src", 904 .parent_data = gcc_parent_data_0, 905 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 906 .flags = CLK_SET_RATE_PARENT, 907 .ops = &clk_rcg2_ops, 908 }; 909 910 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 911 .cmd_rcgr = 0x18500, 912 .mnd_width = 16, 913 .hid_width = 5, 914 .parent_map = gcc_parent_map_0, 915 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 916 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 917 }; 918 919 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 920 .name = "gcc_qupv3_wrap1_s5_clk_src", 921 .parent_data = gcc_parent_data_0, 922 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 923 .flags = CLK_SET_RATE_PARENT, 924 .ops = &clk_rcg2_ops, 925 }; 926 927 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 928 .cmd_rcgr = 0x18638, 929 .mnd_width = 16, 930 .hid_width = 5, 931 .parent_map = gcc_parent_map_0, 932 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 933 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 934 }; 935 936 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 937 .name = "gcc_qupv3_wrap1_s6_clk_src", 938 .parent_data = gcc_parent_data_0, 939 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 940 .flags = CLK_SET_RATE_PARENT, 941 .ops = &clk_rcg2_ops, 942 }; 943 944 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 945 .cmd_rcgr = 0x18770, 946 .mnd_width = 16, 947 .hid_width = 5, 948 .parent_map = gcc_parent_map_0, 949 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 950 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 951 }; 952 953 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 954 .name = "gcc_qupv3_wrap1_s7_clk_src", 955 .parent_data = gcc_parent_data_0, 956 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 957 .flags = CLK_SET_RATE_PARENT, 958 .ops = &clk_rcg2_ops, 959 }; 960 961 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 962 .cmd_rcgr = 0x188a8, 963 .mnd_width = 16, 964 .hid_width = 5, 965 .parent_map = gcc_parent_map_0, 966 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 967 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 968 }; 969 970 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 971 .name = "gcc_qupv3_wrap2_s0_clk_src", 972 .parent_data = gcc_parent_data_0, 973 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 974 .flags = CLK_SET_RATE_PARENT, 975 .ops = &clk_rcg2_ops, 976 }; 977 978 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 979 .cmd_rcgr = 0x1e010, 980 .mnd_width = 16, 981 .hid_width = 5, 982 .parent_map = gcc_parent_map_0, 983 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 984 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 985 }; 986 987 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 988 .name = "gcc_qupv3_wrap2_s1_clk_src", 989 .parent_data = gcc_parent_data_0, 990 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 991 .flags = CLK_SET_RATE_PARENT, 992 .ops = &clk_rcg2_ops, 993 }; 994 995 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 996 .cmd_rcgr = 0x1e148, 997 .mnd_width = 16, 998 .hid_width = 5, 999 .parent_map = gcc_parent_map_0, 1000 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1001 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 1002 }; 1003 1004 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 1005 .name = "gcc_qupv3_wrap2_s2_clk_src", 1006 .parent_data = gcc_parent_data_0, 1007 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1008 .flags = CLK_SET_RATE_PARENT, 1009 .ops = &clk_rcg2_ops, 1010 }; 1011 1012 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 1013 .cmd_rcgr = 0x1e288, 1014 .mnd_width = 16, 1015 .hid_width = 5, 1016 .parent_map = gcc_parent_map_0, 1017 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1018 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, 1019 }; 1020 1021 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 1022 .name = "gcc_qupv3_wrap2_s3_clk_src", 1023 .parent_data = gcc_parent_data_0, 1024 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1025 .flags = CLK_SET_RATE_PARENT, 1026 .ops = &clk_rcg2_ops, 1027 }; 1028 1029 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 1030 .cmd_rcgr = 0x1e3c8, 1031 .mnd_width = 16, 1032 .hid_width = 5, 1033 .parent_map = gcc_parent_map_0, 1034 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1035 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, 1036 }; 1037 1038 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 1039 .name = "gcc_qupv3_wrap2_s4_clk_src", 1040 .parent_data = gcc_parent_data_0, 1041 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1042 .flags = CLK_SET_RATE_PARENT, 1043 .ops = &clk_rcg2_ops, 1044 }; 1045 1046 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 1047 .cmd_rcgr = 0x1e500, 1048 .mnd_width = 16, 1049 .hid_width = 5, 1050 .parent_map = gcc_parent_map_0, 1051 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 1052 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 1053 }; 1054 1055 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { 1056 .name = "gcc_qupv3_wrap2_s5_clk_src", 1057 .parent_data = gcc_parent_data_0, 1058 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1059 .flags = CLK_SET_RATE_PARENT, 1060 .ops = &clk_rcg2_ops, 1061 }; 1062 1063 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { 1064 .cmd_rcgr = 0x1e638, 1065 .mnd_width = 16, 1066 .hid_width = 5, 1067 .parent_map = gcc_parent_map_0, 1068 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 1069 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, 1070 }; 1071 1072 static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = { 1073 .name = "gcc_qupv3_wrap2_s6_clk_src", 1074 .parent_data = gcc_parent_data_8, 1075 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 1076 .flags = CLK_SET_RATE_PARENT, 1077 .ops = &clk_rcg2_ops, 1078 }; 1079 1080 static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { 1081 .cmd_rcgr = 0x1e770, 1082 .mnd_width = 16, 1083 .hid_width = 5, 1084 .parent_map = gcc_parent_map_8, 1085 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 1086 .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init, 1087 }; 1088 1089 static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = { 1090 .name = "gcc_qupv3_wrap2_s7_clk_src", 1091 .parent_data = gcc_parent_data_0, 1092 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1093 .flags = CLK_SET_RATE_PARENT, 1094 .ops = &clk_rcg2_ops, 1095 }; 1096 1097 static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = { 1098 .cmd_rcgr = 0x1e8a8, 1099 .mnd_width = 16, 1100 .hid_width = 5, 1101 .parent_map = gcc_parent_map_0, 1102 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 1103 .clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init, 1104 }; 1105 1106 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1107 F(400000, P_BI_TCXO, 12, 1, 4), 1108 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1109 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 1110 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1111 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), 1112 { } 1113 }; 1114 1115 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1116 .cmd_rcgr = 0x14018, 1117 .mnd_width = 8, 1118 .hid_width = 5, 1119 .parent_map = gcc_parent_map_9, 1120 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1121 .clkr.hw.init = &(const struct clk_init_data) { 1122 .name = "gcc_sdcc2_apps_clk_src", 1123 .parent_data = gcc_parent_data_9, 1124 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 1125 .flags = CLK_SET_RATE_PARENT, 1126 .ops = &clk_rcg2_floor_ops, 1127 }, 1128 }; 1129 1130 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 1131 F(400000, P_BI_TCXO, 12, 1, 4), 1132 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1133 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1134 { } 1135 }; 1136 1137 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 1138 .cmd_rcgr = 0x16018, 1139 .mnd_width = 8, 1140 .hid_width = 5, 1141 .parent_map = gcc_parent_map_0, 1142 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 1143 .clkr.hw.init = &(const struct clk_init_data) { 1144 .name = "gcc_sdcc4_apps_clk_src", 1145 .parent_data = gcc_parent_data_0, 1146 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1147 .flags = CLK_SET_RATE_PARENT, 1148 .ops = &clk_rcg2_floor_ops, 1149 }, 1150 }; 1151 1152 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 1153 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1154 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1155 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 1156 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 1157 { } 1158 }; 1159 1160 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1161 .cmd_rcgr = 0x77030, 1162 .mnd_width = 8, 1163 .hid_width = 5, 1164 .parent_map = gcc_parent_map_0, 1165 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 1166 .clkr.hw.init = &(const struct clk_init_data) { 1167 .name = "gcc_ufs_phy_axi_clk_src", 1168 .parent_data = gcc_parent_data_0, 1169 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1170 .flags = CLK_SET_RATE_PARENT, 1171 .ops = &clk_rcg2_shared_ops, 1172 }, 1173 }; 1174 1175 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1176 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1177 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), 1178 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 1179 { } 1180 }; 1181 1182 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1183 .cmd_rcgr = 0x77080, 1184 .mnd_width = 0, 1185 .hid_width = 5, 1186 .parent_map = gcc_parent_map_7, 1187 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1188 .clkr.hw.init = &(const struct clk_init_data) { 1189 .name = "gcc_ufs_phy_ice_core_clk_src", 1190 .parent_data = gcc_parent_data_7, 1191 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 1192 .flags = CLK_SET_RATE_PARENT, 1193 .ops = &clk_rcg2_shared_ops, 1194 }, 1195 }; 1196 1197 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1198 .cmd_rcgr = 0x770b4, 1199 .mnd_width = 0, 1200 .hid_width = 5, 1201 .parent_map = gcc_parent_map_3, 1202 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1203 .clkr.hw.init = &(const struct clk_init_data) { 1204 .name = "gcc_ufs_phy_phy_aux_clk_src", 1205 .parent_data = gcc_parent_data_3, 1206 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1207 .flags = CLK_SET_RATE_PARENT, 1208 .ops = &clk_rcg2_shared_ops, 1209 }, 1210 }; 1211 1212 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { 1213 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1214 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 1215 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 1216 { } 1217 }; 1218 1219 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1220 .cmd_rcgr = 0x77098, 1221 .mnd_width = 0, 1222 .hid_width = 5, 1223 .parent_map = gcc_parent_map_0, 1224 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, 1225 .clkr.hw.init = &(const struct clk_init_data) { 1226 .name = "gcc_ufs_phy_unipro_core_clk_src", 1227 .parent_data = gcc_parent_data_0, 1228 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1229 .flags = CLK_SET_RATE_PARENT, 1230 .ops = &clk_rcg2_shared_ops, 1231 }, 1232 }; 1233 1234 static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = { 1235 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 1236 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 1237 { } 1238 }; 1239 1240 static struct clk_rcg2 gcc_usb20_master_clk_src = { 1241 .cmd_rcgr = 0x2902c, 1242 .mnd_width = 8, 1243 .hid_width = 5, 1244 .parent_map = gcc_parent_map_0, 1245 .freq_tbl = ftbl_gcc_usb20_master_clk_src, 1246 .clkr.hw.init = &(const struct clk_init_data) { 1247 .name = "gcc_usb20_master_clk_src", 1248 .parent_data = gcc_parent_data_0, 1249 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1250 .flags = CLK_SET_RATE_PARENT, 1251 .ops = &clk_rcg2_shared_ops, 1252 }, 1253 }; 1254 1255 static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = { 1256 .cmd_rcgr = 0x29158, 1257 .mnd_width = 0, 1258 .hid_width = 5, 1259 .parent_map = gcc_parent_map_0, 1260 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1261 .clkr.hw.init = &(const struct clk_init_data) { 1262 .name = "gcc_usb20_mock_utmi_clk_src", 1263 .parent_data = gcc_parent_data_0, 1264 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1265 .flags = CLK_SET_RATE_PARENT, 1266 .ops = &clk_rcg2_shared_ops, 1267 }, 1268 }; 1269 1270 static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = { 1271 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), 1272 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 1273 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1274 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 1275 { } 1276 }; 1277 1278 static struct clk_rcg2 gcc_usb30_mp_master_clk_src = { 1279 .cmd_rcgr = 0x1702c, 1280 .mnd_width = 8, 1281 .hid_width = 5, 1282 .parent_map = gcc_parent_map_0, 1283 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 1284 .clkr.hw.init = &(const struct clk_init_data) { 1285 .name = "gcc_usb30_mp_master_clk_src", 1286 .parent_data = gcc_parent_data_0, 1287 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1288 .flags = CLK_SET_RATE_PARENT, 1289 .ops = &clk_rcg2_shared_ops, 1290 }, 1291 }; 1292 1293 static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = { 1294 .cmd_rcgr = 0x17158, 1295 .mnd_width = 0, 1296 .hid_width = 5, 1297 .parent_map = gcc_parent_map_0, 1298 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1299 .clkr.hw.init = &(const struct clk_init_data) { 1300 .name = "gcc_usb30_mp_mock_utmi_clk_src", 1301 .parent_data = gcc_parent_data_0, 1302 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1303 .flags = CLK_SET_RATE_PARENT, 1304 .ops = &clk_rcg2_shared_ops, 1305 }, 1306 }; 1307 1308 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1309 .cmd_rcgr = 0x3902c, 1310 .mnd_width = 8, 1311 .hid_width = 5, 1312 .parent_map = gcc_parent_map_0, 1313 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 1314 .clkr.hw.init = &(const struct clk_init_data) { 1315 .name = "gcc_usb30_prim_master_clk_src", 1316 .parent_data = gcc_parent_data_0, 1317 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1318 .flags = CLK_SET_RATE_PARENT, 1319 .ops = &clk_rcg2_shared_ops, 1320 }, 1321 }; 1322 1323 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1324 .cmd_rcgr = 0x39044, 1325 .mnd_width = 0, 1326 .hid_width = 5, 1327 .parent_map = gcc_parent_map_0, 1328 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1329 .clkr.hw.init = &(const struct clk_init_data) { 1330 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1331 .parent_data = gcc_parent_data_0, 1332 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1333 .flags = CLK_SET_RATE_PARENT, 1334 .ops = &clk_rcg2_shared_ops, 1335 }, 1336 }; 1337 1338 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { 1339 .cmd_rcgr = 0xa102c, 1340 .mnd_width = 8, 1341 .hid_width = 5, 1342 .parent_map = gcc_parent_map_0, 1343 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 1344 .clkr.hw.init = &(const struct clk_init_data) { 1345 .name = "gcc_usb30_sec_master_clk_src", 1346 .parent_data = gcc_parent_data_0, 1347 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1348 .flags = CLK_SET_RATE_PARENT, 1349 .ops = &clk_rcg2_shared_ops, 1350 }, 1351 }; 1352 1353 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { 1354 .cmd_rcgr = 0xa1044, 1355 .mnd_width = 0, 1356 .hid_width = 5, 1357 .parent_map = gcc_parent_map_0, 1358 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1359 .clkr.hw.init = &(const struct clk_init_data) { 1360 .name = "gcc_usb30_sec_mock_utmi_clk_src", 1361 .parent_data = gcc_parent_data_0, 1362 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1363 .flags = CLK_SET_RATE_PARENT, 1364 .ops = &clk_rcg2_shared_ops, 1365 }, 1366 }; 1367 1368 static struct clk_rcg2 gcc_usb30_tert_master_clk_src = { 1369 .cmd_rcgr = 0xa202c, 1370 .mnd_width = 8, 1371 .hid_width = 5, 1372 .parent_map = gcc_parent_map_0, 1373 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 1374 .clkr.hw.init = &(const struct clk_init_data) { 1375 .name = "gcc_usb30_tert_master_clk_src", 1376 .parent_data = gcc_parent_data_0, 1377 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1378 .flags = CLK_SET_RATE_PARENT, 1379 .ops = &clk_rcg2_shared_ops, 1380 }, 1381 }; 1382 1383 static struct clk_rcg2 gcc_usb30_tert_mock_utmi_clk_src = { 1384 .cmd_rcgr = 0xa2044, 1385 .mnd_width = 0, 1386 .hid_width = 5, 1387 .parent_map = gcc_parent_map_0, 1388 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1389 .clkr.hw.init = &(const struct clk_init_data) { 1390 .name = "gcc_usb30_tert_mock_utmi_clk_src", 1391 .parent_data = gcc_parent_data_0, 1392 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1393 .flags = CLK_SET_RATE_PARENT, 1394 .ops = &clk_rcg2_shared_ops, 1395 }, 1396 }; 1397 1398 static struct clk_rcg2 gcc_usb3_mp_phy_aux_clk_src = { 1399 .cmd_rcgr = 0x172a0, 1400 .mnd_width = 0, 1401 .hid_width = 5, 1402 .parent_map = gcc_parent_map_1, 1403 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1404 .clkr.hw.init = &(const struct clk_init_data) { 1405 .name = "gcc_usb3_mp_phy_aux_clk_src", 1406 .parent_data = gcc_parent_data_1, 1407 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1408 .flags = CLK_SET_RATE_PARENT, 1409 .ops = &clk_rcg2_shared_ops, 1410 }, 1411 }; 1412 1413 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1414 .cmd_rcgr = 0x39074, 1415 .mnd_width = 0, 1416 .hid_width = 5, 1417 .parent_map = gcc_parent_map_1, 1418 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1419 .clkr.hw.init = &(const struct clk_init_data) { 1420 .name = "gcc_usb3_prim_phy_aux_clk_src", 1421 .parent_data = gcc_parent_data_1, 1422 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1423 .flags = CLK_SET_RATE_PARENT, 1424 .ops = &clk_rcg2_shared_ops, 1425 }, 1426 }; 1427 1428 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { 1429 .cmd_rcgr = 0xa1074, 1430 .mnd_width = 0, 1431 .hid_width = 5, 1432 .parent_map = gcc_parent_map_1, 1433 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1434 .clkr.hw.init = &(const struct clk_init_data) { 1435 .name = "gcc_usb3_sec_phy_aux_clk_src", 1436 .parent_data = gcc_parent_data_1, 1437 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1438 .flags = CLK_SET_RATE_PARENT, 1439 .ops = &clk_rcg2_shared_ops, 1440 }, 1441 }; 1442 1443 static struct clk_rcg2 gcc_usb3_tert_phy_aux_clk_src = { 1444 .cmd_rcgr = 0xa2074, 1445 .mnd_width = 0, 1446 .hid_width = 5, 1447 .parent_map = gcc_parent_map_1, 1448 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1449 .clkr.hw.init = &(const struct clk_init_data) { 1450 .name = "gcc_usb3_tert_phy_aux_clk_src", 1451 .parent_data = gcc_parent_data_1, 1452 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1453 .flags = CLK_SET_RATE_PARENT, 1454 .ops = &clk_rcg2_shared_ops, 1455 }, 1456 }; 1457 1458 static const struct freq_tbl ftbl_gcc_usb4_0_master_clk_src[] = { 1459 F(85714286, P_GCC_GPLL0_OUT_EVEN, 3.5, 0, 0), 1460 F(175000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0), 1461 F(350000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0), 1462 { } 1463 }; 1464 1465 static struct clk_rcg2 gcc_usb4_0_master_clk_src = { 1466 .cmd_rcgr = 0x9f024, 1467 .mnd_width = 8, 1468 .hid_width = 5, 1469 .parent_map = gcc_parent_map_4, 1470 .freq_tbl = ftbl_gcc_usb4_0_master_clk_src, 1471 .clkr.hw.init = &(const struct clk_init_data) { 1472 .name = "gcc_usb4_0_master_clk_src", 1473 .parent_data = gcc_parent_data_4, 1474 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1475 .flags = CLK_SET_RATE_PARENT, 1476 .ops = &clk_rcg2_shared_ops, 1477 }, 1478 }; 1479 1480 static const struct freq_tbl ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src[] = { 1481 F(19200000, P_BI_TCXO, 1, 0, 0), 1482 F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0), 1483 F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0), 1484 { } 1485 }; 1486 1487 static struct clk_rcg2 gcc_usb4_0_phy_pcie_pipe_clk_src = { 1488 .cmd_rcgr = 0x9f0e8, 1489 .mnd_width = 0, 1490 .hid_width = 5, 1491 .parent_map = gcc_parent_map_5, 1492 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src, 1493 .clkr.hw.init = &(const struct clk_init_data) { 1494 .name = "gcc_usb4_0_phy_pcie_pipe_clk_src", 1495 .parent_data = gcc_parent_data_5, 1496 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1497 .flags = CLK_SET_RATE_PARENT, 1498 .ops = &clk_rcg2_shared_ops, 1499 }, 1500 }; 1501 1502 static struct clk_rcg2 gcc_usb4_0_sb_if_clk_src = { 1503 .cmd_rcgr = 0x9f08c, 1504 .mnd_width = 0, 1505 .hid_width = 5, 1506 .parent_map = gcc_parent_map_3, 1507 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1508 .clkr.hw.init = &(const struct clk_init_data) { 1509 .name = "gcc_usb4_0_sb_if_clk_src", 1510 .parent_data = gcc_parent_data_3, 1511 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1512 .flags = CLK_SET_RATE_PARENT, 1513 .ops = &clk_rcg2_shared_ops, 1514 }, 1515 }; 1516 1517 static const struct freq_tbl ftbl_gcc_usb4_0_tmu_clk_src[] = { 1518 F(19200000, P_BI_TCXO, 1, 0, 0), 1519 F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0), 1520 { } 1521 }; 1522 1523 static struct clk_rcg2 gcc_usb4_0_tmu_clk_src = { 1524 .cmd_rcgr = 0x9f070, 1525 .mnd_width = 0, 1526 .hid_width = 5, 1527 .parent_map = gcc_parent_map_6, 1528 .freq_tbl = ftbl_gcc_usb4_0_tmu_clk_src, 1529 .clkr.hw.init = &(const struct clk_init_data) { 1530 .name = "gcc_usb4_0_tmu_clk_src", 1531 .parent_data = gcc_parent_data_6, 1532 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 1533 .flags = CLK_SET_RATE_PARENT, 1534 .ops = &clk_rcg2_shared_ops, 1535 }, 1536 }; 1537 1538 static struct clk_rcg2 gcc_usb4_1_master_clk_src = { 1539 .cmd_rcgr = 0x2b024, 1540 .mnd_width = 8, 1541 .hid_width = 5, 1542 .parent_map = gcc_parent_map_4, 1543 .freq_tbl = ftbl_gcc_usb4_0_master_clk_src, 1544 .clkr.hw.init = &(const struct clk_init_data) { 1545 .name = "gcc_usb4_1_master_clk_src", 1546 .parent_data = gcc_parent_data_4, 1547 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1548 .flags = CLK_SET_RATE_PARENT, 1549 .ops = &clk_rcg2_shared_ops, 1550 }, 1551 }; 1552 1553 static struct clk_rcg2 gcc_usb4_1_phy_pcie_pipe_clk_src = { 1554 .cmd_rcgr = 0x2b0e8, 1555 .mnd_width = 0, 1556 .hid_width = 5, 1557 .parent_map = gcc_parent_map_5, 1558 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src, 1559 .clkr.hw.init = &(const struct clk_init_data) { 1560 .name = "gcc_usb4_1_phy_pcie_pipe_clk_src", 1561 .parent_data = gcc_parent_data_5, 1562 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1563 .flags = CLK_SET_RATE_PARENT, 1564 .ops = &clk_rcg2_shared_ops, 1565 }, 1566 }; 1567 1568 static struct clk_rcg2 gcc_usb4_1_sb_if_clk_src = { 1569 .cmd_rcgr = 0x2b08c, 1570 .mnd_width = 0, 1571 .hid_width = 5, 1572 .parent_map = gcc_parent_map_3, 1573 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1574 .clkr.hw.init = &(const struct clk_init_data) { 1575 .name = "gcc_usb4_1_sb_if_clk_src", 1576 .parent_data = gcc_parent_data_3, 1577 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1578 .flags = CLK_SET_RATE_PARENT, 1579 .ops = &clk_rcg2_shared_ops, 1580 }, 1581 }; 1582 1583 static struct clk_rcg2 gcc_usb4_1_tmu_clk_src = { 1584 .cmd_rcgr = 0x2b070, 1585 .mnd_width = 0, 1586 .hid_width = 5, 1587 .parent_map = gcc_parent_map_6, 1588 .freq_tbl = ftbl_gcc_usb4_0_tmu_clk_src, 1589 .clkr.hw.init = &(const struct clk_init_data) { 1590 .name = "gcc_usb4_1_tmu_clk_src", 1591 .parent_data = gcc_parent_data_6, 1592 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 1593 .flags = CLK_SET_RATE_PARENT, 1594 .ops = &clk_rcg2_shared_ops, 1595 }, 1596 }; 1597 1598 static struct clk_rcg2 gcc_usb4_2_master_clk_src = { 1599 .cmd_rcgr = 0x11024, 1600 .mnd_width = 8, 1601 .hid_width = 5, 1602 .parent_map = gcc_parent_map_4, 1603 .freq_tbl = ftbl_gcc_usb4_0_master_clk_src, 1604 .clkr.hw.init = &(const struct clk_init_data) { 1605 .name = "gcc_usb4_2_master_clk_src", 1606 .parent_data = gcc_parent_data_4, 1607 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1608 .flags = CLK_SET_RATE_PARENT, 1609 .ops = &clk_rcg2_shared_ops, 1610 }, 1611 }; 1612 1613 static struct clk_rcg2 gcc_usb4_2_phy_pcie_pipe_clk_src = { 1614 .cmd_rcgr = 0x110e8, 1615 .mnd_width = 0, 1616 .hid_width = 5, 1617 .parent_map = gcc_parent_map_5, 1618 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src, 1619 .clkr.hw.init = &(const struct clk_init_data) { 1620 .name = "gcc_usb4_2_phy_pcie_pipe_clk_src", 1621 .parent_data = gcc_parent_data_5, 1622 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1623 .flags = CLK_SET_RATE_PARENT, 1624 .ops = &clk_rcg2_shared_ops, 1625 }, 1626 }; 1627 1628 static struct clk_rcg2 gcc_usb4_2_sb_if_clk_src = { 1629 .cmd_rcgr = 0x1108c, 1630 .mnd_width = 0, 1631 .hid_width = 5, 1632 .parent_map = gcc_parent_map_3, 1633 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1634 .clkr.hw.init = &(const struct clk_init_data) { 1635 .name = "gcc_usb4_2_sb_if_clk_src", 1636 .parent_data = gcc_parent_data_3, 1637 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1638 .flags = CLK_SET_RATE_PARENT, 1639 .ops = &clk_rcg2_shared_ops, 1640 }, 1641 }; 1642 1643 static struct clk_rcg2 gcc_usb4_2_tmu_clk_src = { 1644 .cmd_rcgr = 0x11070, 1645 .mnd_width = 0, 1646 .hid_width = 5, 1647 .parent_map = gcc_parent_map_6, 1648 .freq_tbl = ftbl_gcc_usb4_0_tmu_clk_src, 1649 .clkr.hw.init = &(const struct clk_init_data) { 1650 .name = "gcc_usb4_2_tmu_clk_src", 1651 .parent_data = gcc_parent_data_6, 1652 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 1653 .flags = CLK_SET_RATE_PARENT, 1654 .ops = &clk_rcg2_shared_ops, 1655 }, 1656 }; 1657 1658 static struct clk_regmap_phy_mux gcc_pcie_3_pipe_clk_src = { 1659 .reg = 0x58088, 1660 .clkr = { 1661 .hw.init = &(struct clk_init_data){ 1662 .name = "gcc_pcie_3_pipe_clk_src", 1663 .parent_data = &(const struct clk_parent_data){ 1664 .index = DT_PCIE_3_PIPE, 1665 }, 1666 .num_parents = 1, 1667 .ops = &clk_regmap_phy_mux_ops, 1668 }, 1669 }, 1670 }; 1671 1672 static struct clk_regmap_div gcc_pcie_3_pipe_div_clk_src = { 1673 .reg = 0x5806c, 1674 .shift = 0, 1675 .width = 4, 1676 .clkr.hw.init = &(const struct clk_init_data) { 1677 .name = "gcc_pcie_3_pipe_div_clk_src", 1678 .parent_hws = (const struct clk_hw*[]) { 1679 &gcc_pcie_3_pipe_clk_src.clkr.hw, 1680 }, 1681 .num_parents = 1, 1682 .ops = &clk_regmap_div_ro_ops, 1683 }, 1684 }; 1685 1686 static struct clk_regmap_phy_mux gcc_pcie_4_pipe_clk_src = { 1687 .reg = 0x6b07c, 1688 .clkr = { 1689 .hw.init = &(struct clk_init_data){ 1690 .name = "gcc_pcie_4_pipe_clk_src", 1691 .parent_data = &(const struct clk_parent_data){ 1692 .index = DT_PCIE_4_PIPE, 1693 }, 1694 .num_parents = 1, 1695 .ops = &clk_regmap_phy_mux_ops, 1696 }, 1697 }, 1698 }; 1699 1700 static struct clk_regmap_div gcc_pcie_4_pipe_div_clk_src = { 1701 .reg = 0x6b060, 1702 .shift = 0, 1703 .width = 4, 1704 .clkr.hw.init = &(const struct clk_init_data) { 1705 .name = "gcc_pcie_4_pipe_div_clk_src", 1706 .parent_hws = (const struct clk_hw*[]) { 1707 &gcc_pcie_4_pipe_clk_src.clkr.hw, 1708 }, 1709 .num_parents = 1, 1710 .ops = &clk_regmap_div_ro_ops, 1711 }, 1712 }; 1713 1714 static struct clk_regmap_phy_mux gcc_pcie_5_pipe_clk_src = { 1715 .reg = 0x2f07c, 1716 .clkr = { 1717 .hw.init = &(struct clk_init_data){ 1718 .name = "gcc_pcie_5_pipe_clk_src", 1719 .parent_data = &(const struct clk_parent_data){ 1720 .index = DT_PCIE_5_PIPE, 1721 }, 1722 .num_parents = 1, 1723 .ops = &clk_regmap_phy_mux_ops, 1724 }, 1725 }, 1726 }; 1727 1728 static struct clk_regmap_div gcc_pcie_5_pipe_div_clk_src = { 1729 .reg = 0x2f060, 1730 .shift = 0, 1731 .width = 4, 1732 .clkr.hw.init = &(const struct clk_init_data) { 1733 .name = "gcc_pcie_5_pipe_div_clk_src", 1734 .parent_hws = (const struct clk_hw*[]) { 1735 &gcc_pcie_5_pipe_clk_src.clkr.hw, 1736 }, 1737 .num_parents = 1, 1738 .ops = &clk_regmap_div_ro_ops, 1739 }, 1740 }; 1741 1742 static struct clk_regmap_phy_mux gcc_pcie_6a_pipe_clk_src = { 1743 .reg = 0x31088, 1744 .clkr = { 1745 .hw.init = &(struct clk_init_data){ 1746 .name = "gcc_pcie_6a_pipe_clk_src", 1747 .parent_data = &(const struct clk_parent_data){ 1748 .index = DT_PCIE_6A_PIPE, 1749 }, 1750 .num_parents = 1, 1751 .ops = &clk_regmap_phy_mux_ops, 1752 }, 1753 }, 1754 }; 1755 1756 static struct clk_regmap_div gcc_pcie_6a_pipe_div_clk_src = { 1757 .reg = 0x3106c, 1758 .shift = 0, 1759 .width = 4, 1760 .clkr.hw.init = &(const struct clk_init_data) { 1761 .name = "gcc_pcie_6a_pipe_div_clk_src", 1762 .parent_hws = (const struct clk_hw*[]) { 1763 &gcc_pcie_6a_pipe_clk_src.clkr.hw, 1764 }, 1765 .num_parents = 1, 1766 .ops = &clk_regmap_div_ro_ops, 1767 }, 1768 }; 1769 1770 static struct clk_regmap_phy_mux gcc_pcie_6b_pipe_clk_src = { 1771 .reg = 0x8d088, 1772 .clkr = { 1773 .hw.init = &(struct clk_init_data){ 1774 .name = "gcc_pcie_6b_pipe_clk_src", 1775 .parent_data = &(const struct clk_parent_data){ 1776 .index = DT_PCIE_6B_PIPE, 1777 }, 1778 .num_parents = 1, 1779 .ops = &clk_regmap_phy_mux_ops, 1780 }, 1781 }, 1782 }; 1783 1784 static struct clk_regmap_div gcc_pcie_6b_pipe_div_clk_src = { 1785 .reg = 0x8d06c, 1786 .shift = 0, 1787 .width = 4, 1788 .clkr.hw.init = &(const struct clk_init_data) { 1789 .name = "gcc_pcie_6b_pipe_div_clk_src", 1790 .parent_hws = (const struct clk_hw*[]) { 1791 &gcc_pcie_6b_pipe_clk_src.clkr.hw, 1792 }, 1793 .num_parents = 1, 1794 .ops = &clk_regmap_div_ro_ops, 1795 }, 1796 }; 1797 1798 static struct clk_regmap_div gcc_qupv3_wrap0_s2_div_clk_src = { 1799 .reg = 0x42284, 1800 .shift = 0, 1801 .width = 4, 1802 .clkr.hw.init = &(const struct clk_init_data) { 1803 .name = "gcc_qupv3_wrap0_s2_div_clk_src", 1804 .parent_hws = (const struct clk_hw*[]) { 1805 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 1806 }, 1807 .num_parents = 1, 1808 .flags = CLK_SET_RATE_PARENT, 1809 .ops = &clk_regmap_div_ro_ops, 1810 }, 1811 }; 1812 1813 static struct clk_regmap_div gcc_qupv3_wrap0_s3_div_clk_src = { 1814 .reg = 0x423c4, 1815 .shift = 0, 1816 .width = 4, 1817 .clkr.hw.init = &(const struct clk_init_data) { 1818 .name = "gcc_qupv3_wrap0_s3_div_clk_src", 1819 .parent_hws = (const struct clk_hw*[]) { 1820 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 1821 }, 1822 .num_parents = 1, 1823 .flags = CLK_SET_RATE_PARENT, 1824 .ops = &clk_regmap_div_ro_ops, 1825 }, 1826 }; 1827 1828 static struct clk_regmap_div gcc_qupv3_wrap1_s2_div_clk_src = { 1829 .reg = 0x18284, 1830 .shift = 0, 1831 .width = 4, 1832 .clkr.hw.init = &(const struct clk_init_data) { 1833 .name = "gcc_qupv3_wrap1_s2_div_clk_src", 1834 .parent_hws = (const struct clk_hw*[]) { 1835 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 1836 }, 1837 .num_parents = 1, 1838 .flags = CLK_SET_RATE_PARENT, 1839 .ops = &clk_regmap_div_ro_ops, 1840 }, 1841 }; 1842 1843 static struct clk_regmap_div gcc_qupv3_wrap1_s3_div_clk_src = { 1844 .reg = 0x183c4, 1845 .shift = 0, 1846 .width = 4, 1847 .clkr.hw.init = &(const struct clk_init_data) { 1848 .name = "gcc_qupv3_wrap1_s3_div_clk_src", 1849 .parent_hws = (const struct clk_hw*[]) { 1850 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 1851 }, 1852 .num_parents = 1, 1853 .flags = CLK_SET_RATE_PARENT, 1854 .ops = &clk_regmap_div_ro_ops, 1855 }, 1856 }; 1857 1858 static struct clk_regmap_div gcc_qupv3_wrap2_s2_div_clk_src = { 1859 .reg = 0x1e284, 1860 .shift = 0, 1861 .width = 4, 1862 .clkr.hw.init = &(const struct clk_init_data) { 1863 .name = "gcc_qupv3_wrap2_s2_div_clk_src", 1864 .parent_hws = (const struct clk_hw*[]) { 1865 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 1866 }, 1867 .num_parents = 1, 1868 .flags = CLK_SET_RATE_PARENT, 1869 .ops = &clk_regmap_div_ro_ops, 1870 }, 1871 }; 1872 1873 static struct clk_regmap_div gcc_qupv3_wrap2_s3_div_clk_src = { 1874 .reg = 0x1e3c4, 1875 .shift = 0, 1876 .width = 4, 1877 .clkr.hw.init = &(const struct clk_init_data) { 1878 .name = "gcc_qupv3_wrap2_s3_div_clk_src", 1879 .parent_hws = (const struct clk_hw*[]) { 1880 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 1881 }, 1882 .num_parents = 1, 1883 .flags = CLK_SET_RATE_PARENT, 1884 .ops = &clk_regmap_div_ro_ops, 1885 }, 1886 }; 1887 1888 static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src = { 1889 .reg = 0x29284, 1890 .shift = 0, 1891 .width = 4, 1892 .clkr.hw.init = &(const struct clk_init_data) { 1893 .name = "gcc_usb20_mock_utmi_postdiv_clk_src", 1894 .parent_hws = (const struct clk_hw*[]) { 1895 &gcc_usb20_mock_utmi_clk_src.clkr.hw, 1896 }, 1897 .num_parents = 1, 1898 .flags = CLK_SET_RATE_PARENT, 1899 .ops = &clk_regmap_div_ro_ops, 1900 }, 1901 }; 1902 1903 static struct clk_regmap_div gcc_usb30_mp_mock_utmi_postdiv_clk_src = { 1904 .reg = 0x17284, 1905 .shift = 0, 1906 .width = 4, 1907 .clkr.hw.init = &(const struct clk_init_data) { 1908 .name = "gcc_usb30_mp_mock_utmi_postdiv_clk_src", 1909 .parent_hws = (const struct clk_hw*[]) { 1910 &gcc_usb30_mp_mock_utmi_clk_src.clkr.hw, 1911 }, 1912 .num_parents = 1, 1913 .flags = CLK_SET_RATE_PARENT, 1914 .ops = &clk_regmap_div_ro_ops, 1915 }, 1916 }; 1917 1918 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1919 .reg = 0x3905c, 1920 .shift = 0, 1921 .width = 4, 1922 .clkr.hw.init = &(const struct clk_init_data) { 1923 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1924 .parent_hws = (const struct clk_hw*[]) { 1925 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1926 }, 1927 .num_parents = 1, 1928 .flags = CLK_SET_RATE_PARENT, 1929 .ops = &clk_regmap_div_ro_ops, 1930 }, 1931 }; 1932 1933 static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = { 1934 .reg = 0xa105c, 1935 .shift = 0, 1936 .width = 4, 1937 .clkr.hw.init = &(const struct clk_init_data) { 1938 .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src", 1939 .parent_hws = (const struct clk_hw*[]) { 1940 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, 1941 }, 1942 .num_parents = 1, 1943 .flags = CLK_SET_RATE_PARENT, 1944 .ops = &clk_regmap_div_ro_ops, 1945 }, 1946 }; 1947 1948 static struct clk_regmap_div gcc_usb30_tert_mock_utmi_postdiv_clk_src = { 1949 .reg = 0xa205c, 1950 .shift = 0, 1951 .width = 4, 1952 .clkr.hw.init = &(const struct clk_init_data) { 1953 .name = "gcc_usb30_tert_mock_utmi_postdiv_clk_src", 1954 .parent_hws = (const struct clk_hw*[]) { 1955 &gcc_usb30_tert_mock_utmi_clk_src.clkr.hw, 1956 }, 1957 .num_parents = 1, 1958 .flags = CLK_SET_RATE_PARENT, 1959 .ops = &clk_regmap_div_ro_ops, 1960 }, 1961 }; 1962 1963 static struct clk_branch gcc_aggre_noc_usb_north_axi_clk = { 1964 .halt_reg = 0x2d17c, 1965 .halt_check = BRANCH_HALT_VOTED, 1966 .hwcg_reg = 0x2d17c, 1967 .hwcg_bit = 1, 1968 .clkr = { 1969 .enable_reg = 0x2d17c, 1970 .enable_mask = BIT(0), 1971 .hw.init = &(const struct clk_init_data) { 1972 .name = "gcc_aggre_noc_usb_north_axi_clk", 1973 .ops = &clk_branch2_ops, 1974 }, 1975 }, 1976 }; 1977 1978 static struct clk_branch gcc_aggre_noc_usb_south_axi_clk = { 1979 .halt_reg = 0x2d174, 1980 .halt_check = BRANCH_HALT_VOTED, 1981 .hwcg_reg = 0x2d174, 1982 .hwcg_bit = 1, 1983 .clkr = { 1984 .enable_reg = 0x2d174, 1985 .enable_mask = BIT(0), 1986 .hw.init = &(const struct clk_init_data) { 1987 .name = "gcc_aggre_noc_usb_south_axi_clk", 1988 .ops = &clk_branch2_ops, 1989 }, 1990 }, 1991 }; 1992 1993 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1994 .halt_reg = 0x770e4, 1995 .halt_check = BRANCH_HALT_VOTED, 1996 .hwcg_reg = 0x770e4, 1997 .hwcg_bit = 1, 1998 .clkr = { 1999 .enable_reg = 0x770e4, 2000 .enable_mask = BIT(0), 2001 .hw.init = &(const struct clk_init_data) { 2002 .name = "gcc_aggre_ufs_phy_axi_clk", 2003 .parent_hws = (const struct clk_hw*[]) { 2004 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2005 }, 2006 .num_parents = 1, 2007 .flags = CLK_SET_RATE_PARENT, 2008 .ops = &clk_branch2_ops, 2009 }, 2010 }, 2011 }; 2012 2013 static struct clk_branch gcc_aggre_usb2_prim_axi_clk = { 2014 .halt_reg = 0x2928c, 2015 .halt_check = BRANCH_HALT_VOTED, 2016 .hwcg_reg = 0x2928c, 2017 .hwcg_bit = 1, 2018 .clkr = { 2019 .enable_reg = 0x2928c, 2020 .enable_mask = BIT(0), 2021 .hw.init = &(const struct clk_init_data) { 2022 .name = "gcc_aggre_usb2_prim_axi_clk", 2023 .parent_hws = (const struct clk_hw*[]) { 2024 &gcc_usb20_master_clk_src.clkr.hw, 2025 }, 2026 .num_parents = 1, 2027 .flags = CLK_SET_RATE_PARENT, 2028 .ops = &clk_branch2_ops, 2029 }, 2030 }, 2031 }; 2032 2033 static struct clk_branch gcc_aggre_usb3_mp_axi_clk = { 2034 .halt_reg = 0x173d0, 2035 .halt_check = BRANCH_HALT_VOTED, 2036 .hwcg_reg = 0x173d0, 2037 .hwcg_bit = 1, 2038 .clkr = { 2039 .enable_reg = 0x173d0, 2040 .enable_mask = BIT(0), 2041 .hw.init = &(const struct clk_init_data) { 2042 .name = "gcc_aggre_usb3_mp_axi_clk", 2043 .parent_hws = (const struct clk_hw*[]) { 2044 &gcc_usb30_mp_master_clk_src.clkr.hw, 2045 }, 2046 .num_parents = 1, 2047 .flags = CLK_SET_RATE_PARENT, 2048 .ops = &clk_branch2_ops, 2049 }, 2050 }, 2051 }; 2052 2053 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 2054 .halt_reg = 0x39090, 2055 .halt_check = BRANCH_HALT_VOTED, 2056 .hwcg_reg = 0x39090, 2057 .hwcg_bit = 1, 2058 .clkr = { 2059 .enable_reg = 0x39090, 2060 .enable_mask = BIT(0), 2061 .hw.init = &(const struct clk_init_data) { 2062 .name = "gcc_aggre_usb3_prim_axi_clk", 2063 .parent_hws = (const struct clk_hw*[]) { 2064 &gcc_usb30_prim_master_clk_src.clkr.hw, 2065 }, 2066 .num_parents = 1, 2067 .flags = CLK_SET_RATE_PARENT, 2068 .ops = &clk_branch2_ops, 2069 }, 2070 }, 2071 }; 2072 2073 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { 2074 .halt_reg = 0xa1090, 2075 .halt_check = BRANCH_HALT_VOTED, 2076 .hwcg_reg = 0xa1090, 2077 .hwcg_bit = 1, 2078 .clkr = { 2079 .enable_reg = 0xa1090, 2080 .enable_mask = BIT(0), 2081 .hw.init = &(const struct clk_init_data) { 2082 .name = "gcc_aggre_usb3_sec_axi_clk", 2083 .parent_hws = (const struct clk_hw*[]) { 2084 &gcc_usb30_sec_master_clk_src.clkr.hw, 2085 }, 2086 .num_parents = 1, 2087 .flags = CLK_SET_RATE_PARENT, 2088 .ops = &clk_branch2_ops, 2089 }, 2090 }, 2091 }; 2092 2093 static struct clk_branch gcc_aggre_usb3_tert_axi_clk = { 2094 .halt_reg = 0xa2090, 2095 .halt_check = BRANCH_HALT_VOTED, 2096 .hwcg_reg = 0xa2090, 2097 .hwcg_bit = 1, 2098 .clkr = { 2099 .enable_reg = 0xa2090, 2100 .enable_mask = BIT(0), 2101 .hw.init = &(const struct clk_init_data) { 2102 .name = "gcc_aggre_usb3_tert_axi_clk", 2103 .parent_hws = (const struct clk_hw*[]) { 2104 &gcc_usb30_tert_master_clk_src.clkr.hw, 2105 }, 2106 .num_parents = 1, 2107 .flags = CLK_SET_RATE_PARENT, 2108 .ops = &clk_branch2_ops, 2109 }, 2110 }, 2111 }; 2112 2113 static struct clk_branch gcc_aggre_usb4_0_axi_clk = { 2114 .halt_reg = 0x9f118, 2115 .halt_check = BRANCH_HALT_VOTED, 2116 .hwcg_reg = 0x9f118, 2117 .hwcg_bit = 1, 2118 .clkr = { 2119 .enable_reg = 0x9f118, 2120 .enable_mask = BIT(0), 2121 .hw.init = &(const struct clk_init_data) { 2122 .name = "gcc_aggre_usb4_0_axi_clk", 2123 .parent_hws = (const struct clk_hw*[]) { 2124 &gcc_usb4_0_master_clk_src.clkr.hw, 2125 }, 2126 .num_parents = 1, 2127 .flags = CLK_SET_RATE_PARENT, 2128 .ops = &clk_branch2_ops, 2129 }, 2130 }, 2131 }; 2132 2133 static struct clk_branch gcc_aggre_usb4_1_axi_clk = { 2134 .halt_reg = 0x2b118, 2135 .halt_check = BRANCH_HALT_VOTED, 2136 .hwcg_reg = 0x2b118, 2137 .hwcg_bit = 1, 2138 .clkr = { 2139 .enable_reg = 0x2b118, 2140 .enable_mask = BIT(0), 2141 .hw.init = &(const struct clk_init_data) { 2142 .name = "gcc_aggre_usb4_1_axi_clk", 2143 .parent_hws = (const struct clk_hw*[]) { 2144 &gcc_usb4_1_master_clk_src.clkr.hw, 2145 }, 2146 .num_parents = 1, 2147 .flags = CLK_SET_RATE_PARENT, 2148 .ops = &clk_branch2_ops, 2149 }, 2150 }, 2151 }; 2152 2153 static struct clk_branch gcc_aggre_usb4_2_axi_clk = { 2154 .halt_reg = 0x11118, 2155 .halt_check = BRANCH_HALT_VOTED, 2156 .hwcg_reg = 0x11118, 2157 .hwcg_bit = 1, 2158 .clkr = { 2159 .enable_reg = 0x11118, 2160 .enable_mask = BIT(0), 2161 .hw.init = &(const struct clk_init_data) { 2162 .name = "gcc_aggre_usb4_2_axi_clk", 2163 .parent_hws = (const struct clk_hw*[]) { 2164 &gcc_usb4_2_master_clk_src.clkr.hw, 2165 }, 2166 .num_parents = 1, 2167 .flags = CLK_SET_RATE_PARENT, 2168 .ops = &clk_branch2_ops, 2169 }, 2170 }, 2171 }; 2172 2173 static struct clk_branch gcc_aggre_usb_noc_axi_clk = { 2174 .halt_reg = 0x2d034, 2175 .halt_check = BRANCH_HALT_VOTED, 2176 .hwcg_reg = 0x2d034, 2177 .hwcg_bit = 1, 2178 .clkr = { 2179 .enable_reg = 0x2d034, 2180 .enable_mask = BIT(0), 2181 .hw.init = &(const struct clk_init_data) { 2182 .name = "gcc_aggre_usb_noc_axi_clk", 2183 .ops = &clk_branch2_ops, 2184 }, 2185 }, 2186 }; 2187 2188 static struct clk_branch gcc_av1e_ahb_clk = { 2189 .halt_reg = 0x4a004, 2190 .halt_check = BRANCH_HALT_VOTED, 2191 .hwcg_reg = 0x4a004, 2192 .hwcg_bit = 1, 2193 .clkr = { 2194 .enable_reg = 0x4a004, 2195 .enable_mask = BIT(0), 2196 .hw.init = &(const struct clk_init_data) { 2197 .name = "gcc_av1e_ahb_clk", 2198 .ops = &clk_branch2_ops, 2199 }, 2200 }, 2201 }; 2202 2203 static struct clk_branch gcc_av1e_axi_clk = { 2204 .halt_reg = 0x4a008, 2205 .halt_check = BRANCH_HALT_SKIP, 2206 .hwcg_reg = 0x4a008, 2207 .hwcg_bit = 1, 2208 .clkr = { 2209 .enable_reg = 0x4a008, 2210 .enable_mask = BIT(0), 2211 .hw.init = &(const struct clk_init_data) { 2212 .name = "gcc_av1e_axi_clk", 2213 .ops = &clk_branch2_ops, 2214 }, 2215 }, 2216 }; 2217 2218 static struct clk_branch gcc_av1e_xo_clk = { 2219 .halt_reg = 0x4a014, 2220 .halt_check = BRANCH_HALT, 2221 .clkr = { 2222 .enable_reg = 0x4a014, 2223 .enable_mask = BIT(0), 2224 .hw.init = &(const struct clk_init_data) { 2225 .name = "gcc_av1e_xo_clk", 2226 .ops = &clk_branch2_ops, 2227 }, 2228 }, 2229 }; 2230 2231 static struct clk_branch gcc_boot_rom_ahb_clk = { 2232 .halt_reg = 0x38004, 2233 .halt_check = BRANCH_HALT_VOTED, 2234 .hwcg_reg = 0x38004, 2235 .hwcg_bit = 1, 2236 .clkr = { 2237 .enable_reg = 0x52000, 2238 .enable_mask = BIT(10), 2239 .hw.init = &(const struct clk_init_data) { 2240 .name = "gcc_boot_rom_ahb_clk", 2241 .ops = &clk_branch2_ops, 2242 }, 2243 }, 2244 }; 2245 2246 static struct clk_branch gcc_camera_hf_axi_clk = { 2247 .halt_reg = 0x26010, 2248 .halt_check = BRANCH_HALT_SKIP, 2249 .hwcg_reg = 0x26010, 2250 .hwcg_bit = 1, 2251 .clkr = { 2252 .enable_reg = 0x26010, 2253 .enable_mask = BIT(0), 2254 .hw.init = &(const struct clk_init_data) { 2255 .name = "gcc_camera_hf_axi_clk", 2256 .ops = &clk_branch2_ops, 2257 }, 2258 }, 2259 }; 2260 2261 static struct clk_branch gcc_camera_sf_axi_clk = { 2262 .halt_reg = 0x2601c, 2263 .halt_check = BRANCH_HALT_SKIP, 2264 .hwcg_reg = 0x2601c, 2265 .hwcg_bit = 1, 2266 .clkr = { 2267 .enable_reg = 0x2601c, 2268 .enable_mask = BIT(0), 2269 .hw.init = &(const struct clk_init_data) { 2270 .name = "gcc_camera_sf_axi_clk", 2271 .ops = &clk_branch2_ops, 2272 }, 2273 }, 2274 }; 2275 2276 static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = { 2277 .halt_reg = 0x10028, 2278 .halt_check = BRANCH_HALT_VOTED, 2279 .hwcg_reg = 0x10028, 2280 .hwcg_bit = 1, 2281 .clkr = { 2282 .enable_reg = 0x52028, 2283 .enable_mask = BIT(20), 2284 .hw.init = &(const struct clk_init_data) { 2285 .name = "gcc_cfg_noc_pcie_anoc_ahb_clk", 2286 .ops = &clk_branch2_ops, 2287 }, 2288 }, 2289 }; 2290 2291 static struct clk_branch gcc_cfg_noc_pcie_anoc_north_ahb_clk = { 2292 .halt_reg = 0x1002c, 2293 .halt_check = BRANCH_HALT_VOTED, 2294 .hwcg_reg = 0x1002c, 2295 .hwcg_bit = 1, 2296 .clkr = { 2297 .enable_reg = 0x52028, 2298 .enable_mask = BIT(22), 2299 .hw.init = &(const struct clk_init_data) { 2300 .name = "gcc_cfg_noc_pcie_anoc_north_ahb_clk", 2301 .ops = &clk_branch2_ops, 2302 }, 2303 }, 2304 }; 2305 2306 static struct clk_branch gcc_cfg_noc_pcie_anoc_south_ahb_clk = { 2307 .halt_reg = 0x10030, 2308 .halt_check = BRANCH_HALT_VOTED, 2309 .hwcg_reg = 0x10030, 2310 .hwcg_bit = 1, 2311 .clkr = { 2312 .enable_reg = 0x52000, 2313 .enable_mask = BIT(20), 2314 .hw.init = &(const struct clk_init_data) { 2315 .name = "gcc_cfg_noc_pcie_anoc_south_ahb_clk", 2316 .ops = &clk_branch2_ops, 2317 }, 2318 }, 2319 }; 2320 2321 static struct clk_branch gcc_cfg_noc_usb2_prim_axi_clk = { 2322 .halt_reg = 0x29288, 2323 .halt_check = BRANCH_HALT_VOTED, 2324 .hwcg_reg = 0x29288, 2325 .hwcg_bit = 1, 2326 .clkr = { 2327 .enable_reg = 0x29288, 2328 .enable_mask = BIT(0), 2329 .hw.init = &(const struct clk_init_data) { 2330 .name = "gcc_cfg_noc_usb2_prim_axi_clk", 2331 .parent_hws = (const struct clk_hw*[]) { 2332 &gcc_usb20_master_clk_src.clkr.hw, 2333 }, 2334 .num_parents = 1, 2335 .flags = CLK_SET_RATE_PARENT, 2336 .ops = &clk_branch2_ops, 2337 }, 2338 }, 2339 }; 2340 2341 static struct clk_branch gcc_cfg_noc_usb3_mp_axi_clk = { 2342 .halt_reg = 0x173cc, 2343 .halt_check = BRANCH_HALT_VOTED, 2344 .hwcg_reg = 0x173cc, 2345 .hwcg_bit = 1, 2346 .clkr = { 2347 .enable_reg = 0x173cc, 2348 .enable_mask = BIT(0), 2349 .hw.init = &(const struct clk_init_data) { 2350 .name = "gcc_cfg_noc_usb3_mp_axi_clk", 2351 .parent_hws = (const struct clk_hw*[]) { 2352 &gcc_usb30_mp_master_clk_src.clkr.hw, 2353 }, 2354 .num_parents = 1, 2355 .flags = CLK_SET_RATE_PARENT, 2356 .ops = &clk_branch2_ops, 2357 }, 2358 }, 2359 }; 2360 2361 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 2362 .halt_reg = 0x3908c, 2363 .halt_check = BRANCH_HALT_VOTED, 2364 .hwcg_reg = 0x3908c, 2365 .hwcg_bit = 1, 2366 .clkr = { 2367 .enable_reg = 0x3908c, 2368 .enable_mask = BIT(0), 2369 .hw.init = &(const struct clk_init_data) { 2370 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 2371 .parent_hws = (const struct clk_hw*[]) { 2372 &gcc_usb30_prim_master_clk_src.clkr.hw, 2373 }, 2374 .num_parents = 1, 2375 .flags = CLK_SET_RATE_PARENT, 2376 .ops = &clk_branch2_ops, 2377 }, 2378 }, 2379 }; 2380 2381 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { 2382 .halt_reg = 0xa108c, 2383 .halt_check = BRANCH_HALT_VOTED, 2384 .hwcg_reg = 0xa108c, 2385 .hwcg_bit = 1, 2386 .clkr = { 2387 .enable_reg = 0xa108c, 2388 .enable_mask = BIT(0), 2389 .hw.init = &(const struct clk_init_data) { 2390 .name = "gcc_cfg_noc_usb3_sec_axi_clk", 2391 .parent_hws = (const struct clk_hw*[]) { 2392 &gcc_usb30_sec_master_clk_src.clkr.hw, 2393 }, 2394 .num_parents = 1, 2395 .flags = CLK_SET_RATE_PARENT, 2396 .ops = &clk_branch2_ops, 2397 }, 2398 }, 2399 }; 2400 2401 static struct clk_branch gcc_cfg_noc_usb3_tert_axi_clk = { 2402 .halt_reg = 0xa208c, 2403 .halt_check = BRANCH_HALT_VOTED, 2404 .hwcg_reg = 0xa208c, 2405 .hwcg_bit = 1, 2406 .clkr = { 2407 .enable_reg = 0xa208c, 2408 .enable_mask = BIT(0), 2409 .hw.init = &(const struct clk_init_data) { 2410 .name = "gcc_cfg_noc_usb3_tert_axi_clk", 2411 .parent_hws = (const struct clk_hw*[]) { 2412 &gcc_usb30_tert_master_clk_src.clkr.hw, 2413 }, 2414 .num_parents = 1, 2415 .flags = CLK_SET_RATE_PARENT, 2416 .ops = &clk_branch2_ops, 2417 }, 2418 }, 2419 }; 2420 2421 static struct clk_branch gcc_cfg_noc_usb_anoc_ahb_clk = { 2422 .halt_reg = 0x2d024, 2423 .halt_check = BRANCH_HALT_VOTED, 2424 .hwcg_reg = 0x2d024, 2425 .hwcg_bit = 1, 2426 .clkr = { 2427 .enable_reg = 0x52028, 2428 .enable_mask = BIT(21), 2429 .hw.init = &(const struct clk_init_data) { 2430 .name = "gcc_cfg_noc_usb_anoc_ahb_clk", 2431 .ops = &clk_branch2_ops, 2432 }, 2433 }, 2434 }; 2435 2436 static struct clk_branch gcc_cfg_noc_usb_anoc_north_ahb_clk = { 2437 .halt_reg = 0x2d028, 2438 .halt_check = BRANCH_HALT_VOTED, 2439 .hwcg_reg = 0x2d028, 2440 .hwcg_bit = 1, 2441 .clkr = { 2442 .enable_reg = 0x52028, 2443 .enable_mask = BIT(23), 2444 .hw.init = &(const struct clk_init_data) { 2445 .name = "gcc_cfg_noc_usb_anoc_north_ahb_clk", 2446 .ops = &clk_branch2_ops, 2447 }, 2448 }, 2449 }; 2450 2451 static struct clk_branch gcc_cfg_noc_usb_anoc_south_ahb_clk = { 2452 .halt_reg = 0x2d02c, 2453 .halt_check = BRANCH_HALT_VOTED, 2454 .hwcg_reg = 0x2d02c, 2455 .hwcg_bit = 1, 2456 .clkr = { 2457 .enable_reg = 0x52018, 2458 .enable_mask = BIT(7), 2459 .hw.init = &(const struct clk_init_data) { 2460 .name = "gcc_cfg_noc_usb_anoc_south_ahb_clk", 2461 .ops = &clk_branch2_ops, 2462 }, 2463 }, 2464 }; 2465 2466 static struct clk_branch gcc_cnoc_pcie1_tunnel_clk = { 2467 .halt_reg = 0x2c2b4, 2468 .halt_check = BRANCH_HALT_VOTED, 2469 .clkr = { 2470 .enable_reg = 0x52010, 2471 .enable_mask = BIT(30), 2472 .hw.init = &(const struct clk_init_data) { 2473 .name = "gcc_cnoc_pcie1_tunnel_clk", 2474 .ops = &clk_branch2_ops, 2475 }, 2476 }, 2477 }; 2478 2479 static struct clk_branch gcc_cnoc_pcie2_tunnel_clk = { 2480 .halt_reg = 0x132b4, 2481 .halt_check = BRANCH_HALT_VOTED, 2482 .clkr = { 2483 .enable_reg = 0x52010, 2484 .enable_mask = BIT(31), 2485 .hw.init = &(const struct clk_init_data) { 2486 .name = "gcc_cnoc_pcie2_tunnel_clk", 2487 .ops = &clk_branch2_ops, 2488 }, 2489 }, 2490 }; 2491 2492 static struct clk_branch gcc_cnoc_pcie_north_sf_axi_clk = { 2493 .halt_reg = 0x10014, 2494 .halt_check = BRANCH_HALT_VOTED, 2495 .hwcg_reg = 0x10014, 2496 .hwcg_bit = 1, 2497 .clkr = { 2498 .enable_reg = 0x52008, 2499 .enable_mask = BIT(6), 2500 .hw.init = &(const struct clk_init_data) { 2501 .name = "gcc_cnoc_pcie_north_sf_axi_clk", 2502 .ops = &clk_branch2_ops, 2503 }, 2504 }, 2505 }; 2506 2507 static struct clk_branch gcc_cnoc_pcie_south_sf_axi_clk = { 2508 .halt_reg = 0x10018, 2509 .halt_check = BRANCH_HALT_VOTED, 2510 .hwcg_reg = 0x10018, 2511 .hwcg_bit = 1, 2512 .clkr = { 2513 .enable_reg = 0x52028, 2514 .enable_mask = BIT(12), 2515 .hw.init = &(const struct clk_init_data) { 2516 .name = "gcc_cnoc_pcie_south_sf_axi_clk", 2517 .ops = &clk_branch2_ops, 2518 }, 2519 }, 2520 }; 2521 2522 static struct clk_branch gcc_cnoc_pcie_tunnel_clk = { 2523 .halt_reg = 0xa02b4, 2524 .halt_check = BRANCH_HALT_VOTED, 2525 .hwcg_reg = 0xa02b4, 2526 .hwcg_bit = 1, 2527 .clkr = { 2528 .enable_reg = 0x52010, 2529 .enable_mask = BIT(29), 2530 .hw.init = &(const struct clk_init_data) { 2531 .name = "gcc_cnoc_pcie_tunnel_clk", 2532 .ops = &clk_branch2_ops, 2533 }, 2534 }, 2535 }; 2536 2537 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 2538 .halt_reg = 0x7115c, 2539 .halt_check = BRANCH_HALT_SKIP, 2540 .hwcg_reg = 0x7115c, 2541 .hwcg_bit = 1, 2542 .clkr = { 2543 .enable_reg = 0x7115c, 2544 .enable_mask = BIT(0), 2545 .hw.init = &(const struct clk_init_data) { 2546 .name = "gcc_ddrss_gpu_axi_clk", 2547 .ops = &clk_branch2_ops, 2548 }, 2549 }, 2550 }; 2551 2552 static struct clk_branch gcc_disp_hf_axi_clk = { 2553 .halt_reg = 0x2700c, 2554 .halt_check = BRANCH_HALT_SKIP, 2555 .hwcg_reg = 0x2700c, 2556 .hwcg_bit = 1, 2557 .clkr = { 2558 .enable_reg = 0x2700c, 2559 .enable_mask = BIT(0), 2560 .hw.init = &(const struct clk_init_data) { 2561 .name = "gcc_disp_hf_axi_clk", 2562 .ops = &clk_branch2_ops, 2563 }, 2564 }, 2565 }; 2566 2567 static struct clk_branch gcc_gp1_clk = { 2568 .halt_reg = 0x64000, 2569 .halt_check = BRANCH_HALT, 2570 .clkr = { 2571 .enable_reg = 0x64000, 2572 .enable_mask = BIT(0), 2573 .hw.init = &(const struct clk_init_data) { 2574 .name = "gcc_gp1_clk", 2575 .parent_hws = (const struct clk_hw*[]) { 2576 &gcc_gp1_clk_src.clkr.hw, 2577 }, 2578 .num_parents = 1, 2579 .flags = CLK_SET_RATE_PARENT, 2580 .ops = &clk_branch2_ops, 2581 }, 2582 }, 2583 }; 2584 2585 static struct clk_branch gcc_gp2_clk = { 2586 .halt_reg = 0x65000, 2587 .halt_check = BRANCH_HALT, 2588 .clkr = { 2589 .enable_reg = 0x65000, 2590 .enable_mask = BIT(0), 2591 .hw.init = &(const struct clk_init_data) { 2592 .name = "gcc_gp2_clk", 2593 .parent_hws = (const struct clk_hw*[]) { 2594 &gcc_gp2_clk_src.clkr.hw, 2595 }, 2596 .num_parents = 1, 2597 .flags = CLK_SET_RATE_PARENT, 2598 .ops = &clk_branch2_ops, 2599 }, 2600 }, 2601 }; 2602 2603 static struct clk_branch gcc_gp3_clk = { 2604 .halt_reg = 0x66000, 2605 .halt_check = BRANCH_HALT, 2606 .clkr = { 2607 .enable_reg = 0x66000, 2608 .enable_mask = BIT(0), 2609 .hw.init = &(const struct clk_init_data) { 2610 .name = "gcc_gp3_clk", 2611 .parent_hws = (const struct clk_hw*[]) { 2612 &gcc_gp3_clk_src.clkr.hw, 2613 }, 2614 .num_parents = 1, 2615 .flags = CLK_SET_RATE_PARENT, 2616 .ops = &clk_branch2_ops, 2617 }, 2618 }, 2619 }; 2620 2621 static struct clk_branch gcc_gpu_gpll0_cph_clk_src = { 2622 .halt_check = BRANCH_HALT_DELAY, 2623 .clkr = { 2624 .enable_reg = 0x52000, 2625 .enable_mask = BIT(15), 2626 .hw.init = &(const struct clk_init_data) { 2627 .name = "gcc_gpu_gpll0_cph_clk_src", 2628 .parent_hws = (const struct clk_hw*[]) { 2629 &gcc_gpll0.clkr.hw, 2630 }, 2631 .num_parents = 1, 2632 .flags = CLK_SET_RATE_PARENT, 2633 .ops = &clk_branch2_ops, 2634 }, 2635 }, 2636 }; 2637 2638 static struct clk_branch gcc_gpu_gpll0_div_cph_clk_src = { 2639 .halt_check = BRANCH_HALT_DELAY, 2640 .clkr = { 2641 .enable_reg = 0x52000, 2642 .enable_mask = BIT(16), 2643 .hw.init = &(const struct clk_init_data) { 2644 .name = "gcc_gpu_gpll0_div_cph_clk_src", 2645 .parent_hws = (const struct clk_hw*[]) { 2646 &gcc_gpll0_out_even.clkr.hw, 2647 }, 2648 .num_parents = 1, 2649 .flags = CLK_SET_RATE_PARENT, 2650 .ops = &clk_branch2_ops, 2651 }, 2652 }, 2653 }; 2654 2655 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 2656 .halt_reg = 0x71010, 2657 .halt_check = BRANCH_HALT_VOTED, 2658 .hwcg_reg = 0x71010, 2659 .hwcg_bit = 1, 2660 .clkr = { 2661 .enable_reg = 0x71010, 2662 .enable_mask = BIT(0), 2663 .hw.init = &(const struct clk_init_data) { 2664 .name = "gcc_gpu_memnoc_gfx_clk", 2665 .ops = &clk_branch2_ops, 2666 }, 2667 }, 2668 }; 2669 2670 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 2671 .halt_reg = 0x71018, 2672 .halt_check = BRANCH_HALT, 2673 .clkr = { 2674 .enable_reg = 0x71018, 2675 .enable_mask = BIT(0), 2676 .hw.init = &(const struct clk_init_data) { 2677 .name = "gcc_gpu_snoc_dvm_gfx_clk", 2678 .ops = &clk_branch2_ops, 2679 }, 2680 }, 2681 }; 2682 2683 static struct clk_branch gcc_pcie0_phy_rchng_clk = { 2684 .halt_reg = 0xa0050, 2685 .halt_check = BRANCH_HALT_VOTED, 2686 .clkr = { 2687 .enable_reg = 0x52010, 2688 .enable_mask = BIT(26), 2689 .hw.init = &(const struct clk_init_data) { 2690 .name = "gcc_pcie0_phy_rchng_clk", 2691 .parent_hws = (const struct clk_hw*[]) { 2692 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 2693 }, 2694 .num_parents = 1, 2695 .flags = CLK_SET_RATE_PARENT, 2696 .ops = &clk_branch2_ops, 2697 }, 2698 }, 2699 }; 2700 2701 static struct clk_branch gcc_pcie1_phy_rchng_clk = { 2702 .halt_reg = 0x2c050, 2703 .halt_check = BRANCH_HALT_VOTED, 2704 .clkr = { 2705 .enable_reg = 0x52020, 2706 .enable_mask = BIT(31), 2707 .hw.init = &(const struct clk_init_data) { 2708 .name = "gcc_pcie1_phy_rchng_clk", 2709 .parent_hws = (const struct clk_hw*[]) { 2710 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, 2711 }, 2712 .num_parents = 1, 2713 .flags = CLK_SET_RATE_PARENT, 2714 .ops = &clk_branch2_ops, 2715 }, 2716 }, 2717 }; 2718 2719 static struct clk_branch gcc_pcie2_phy_rchng_clk = { 2720 .halt_reg = 0x13050, 2721 .halt_check = BRANCH_HALT_VOTED, 2722 .clkr = { 2723 .enable_reg = 0x52020, 2724 .enable_mask = BIT(24), 2725 .hw.init = &(const struct clk_init_data) { 2726 .name = "gcc_pcie2_phy_rchng_clk", 2727 .parent_hws = (const struct clk_hw*[]) { 2728 &gcc_pcie_2_phy_rchng_clk_src.clkr.hw, 2729 }, 2730 .num_parents = 1, 2731 .flags = CLK_SET_RATE_PARENT, 2732 .ops = &clk_branch2_ops, 2733 }, 2734 }, 2735 }; 2736 2737 static struct clk_branch gcc_pcie_0_aux_clk = { 2738 .halt_reg = 0xa0038, 2739 .halt_check = BRANCH_HALT_VOTED, 2740 .clkr = { 2741 .enable_reg = 0x52010, 2742 .enable_mask = BIT(24), 2743 .hw.init = &(const struct clk_init_data) { 2744 .name = "gcc_pcie_0_aux_clk", 2745 .parent_hws = (const struct clk_hw*[]) { 2746 &gcc_pcie_0_aux_clk_src.clkr.hw, 2747 }, 2748 .num_parents = 1, 2749 .flags = CLK_SET_RATE_PARENT, 2750 .ops = &clk_branch2_ops, 2751 }, 2752 }, 2753 }; 2754 2755 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 2756 .halt_reg = 0xa0034, 2757 .halt_check = BRANCH_HALT_VOTED, 2758 .hwcg_reg = 0xa0034, 2759 .hwcg_bit = 1, 2760 .clkr = { 2761 .enable_reg = 0x52010, 2762 .enable_mask = BIT(23), 2763 .hw.init = &(const struct clk_init_data) { 2764 .name = "gcc_pcie_0_cfg_ahb_clk", 2765 .ops = &clk_branch2_ops, 2766 }, 2767 }, 2768 }; 2769 2770 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 2771 .halt_reg = 0xa0028, 2772 .halt_check = BRANCH_HALT_SKIP, 2773 .hwcg_reg = 0xa0028, 2774 .hwcg_bit = 1, 2775 .clkr = { 2776 .enable_reg = 0x52010, 2777 .enable_mask = BIT(22), 2778 .hw.init = &(const struct clk_init_data) { 2779 .name = "gcc_pcie_0_mstr_axi_clk", 2780 .ops = &clk_branch2_ops, 2781 }, 2782 }, 2783 }; 2784 2785 static struct clk_branch gcc_pcie_0_pipe_clk = { 2786 .halt_reg = 0xa0044, 2787 .halt_check = BRANCH_HALT_SKIP, 2788 .clkr = { 2789 .enable_reg = 0x52010, 2790 .enable_mask = BIT(25), 2791 .hw.init = &(const struct clk_init_data) { 2792 .name = "gcc_pcie_0_pipe_clk", 2793 .ops = &clk_branch2_ops, 2794 }, 2795 }, 2796 }; 2797 2798 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 2799 .halt_reg = 0xa001c, 2800 .halt_check = BRANCH_HALT_VOTED, 2801 .hwcg_reg = 0xa001c, 2802 .hwcg_bit = 1, 2803 .clkr = { 2804 .enable_reg = 0x52010, 2805 .enable_mask = BIT(21), 2806 .hw.init = &(const struct clk_init_data) { 2807 .name = "gcc_pcie_0_slv_axi_clk", 2808 .ops = &clk_branch2_ops, 2809 }, 2810 }, 2811 }; 2812 2813 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 2814 .halt_reg = 0xa0018, 2815 .halt_check = BRANCH_HALT_VOTED, 2816 .clkr = { 2817 .enable_reg = 0x52010, 2818 .enable_mask = BIT(20), 2819 .hw.init = &(const struct clk_init_data) { 2820 .name = "gcc_pcie_0_slv_q2a_axi_clk", 2821 .ops = &clk_branch2_ops, 2822 }, 2823 }, 2824 }; 2825 2826 static struct clk_branch gcc_pcie_1_aux_clk = { 2827 .halt_reg = 0x2c038, 2828 .halt_check = BRANCH_HALT_VOTED, 2829 .clkr = { 2830 .enable_reg = 0x52020, 2831 .enable_mask = BIT(29), 2832 .hw.init = &(const struct clk_init_data) { 2833 .name = "gcc_pcie_1_aux_clk", 2834 .parent_hws = (const struct clk_hw*[]) { 2835 &gcc_pcie_1_aux_clk_src.clkr.hw, 2836 }, 2837 .num_parents = 1, 2838 .flags = CLK_SET_RATE_PARENT, 2839 .ops = &clk_branch2_ops, 2840 }, 2841 }, 2842 }; 2843 2844 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 2845 .halt_reg = 0x2c034, 2846 .halt_check = BRANCH_HALT_VOTED, 2847 .hwcg_reg = 0x2c034, 2848 .hwcg_bit = 1, 2849 .clkr = { 2850 .enable_reg = 0x52020, 2851 .enable_mask = BIT(28), 2852 .hw.init = &(const struct clk_init_data) { 2853 .name = "gcc_pcie_1_cfg_ahb_clk", 2854 .ops = &clk_branch2_ops, 2855 }, 2856 }, 2857 }; 2858 2859 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 2860 .halt_reg = 0x2c028, 2861 .halt_check = BRANCH_HALT_SKIP, 2862 .hwcg_reg = 0x2c028, 2863 .hwcg_bit = 1, 2864 .clkr = { 2865 .enable_reg = 0x52020, 2866 .enable_mask = BIT(27), 2867 .hw.init = &(const struct clk_init_data) { 2868 .name = "gcc_pcie_1_mstr_axi_clk", 2869 .ops = &clk_branch2_ops, 2870 }, 2871 }, 2872 }; 2873 2874 static struct clk_branch gcc_pcie_1_pipe_clk = { 2875 .halt_reg = 0x2c044, 2876 .halt_check = BRANCH_HALT_SKIP, 2877 .clkr = { 2878 .enable_reg = 0x52020, 2879 .enable_mask = BIT(30), 2880 .hw.init = &(const struct clk_init_data) { 2881 .name = "gcc_pcie_1_pipe_clk", 2882 .ops = &clk_branch2_ops, 2883 }, 2884 }, 2885 }; 2886 2887 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 2888 .halt_reg = 0x2c01c, 2889 .halt_check = BRANCH_HALT_VOTED, 2890 .hwcg_reg = 0x2c01c, 2891 .hwcg_bit = 1, 2892 .clkr = { 2893 .enable_reg = 0x52020, 2894 .enable_mask = BIT(26), 2895 .hw.init = &(const struct clk_init_data) { 2896 .name = "gcc_pcie_1_slv_axi_clk", 2897 .ops = &clk_branch2_ops, 2898 }, 2899 }, 2900 }; 2901 2902 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 2903 .halt_reg = 0x2c018, 2904 .halt_check = BRANCH_HALT_VOTED, 2905 .clkr = { 2906 .enable_reg = 0x52020, 2907 .enable_mask = BIT(25), 2908 .hw.init = &(const struct clk_init_data) { 2909 .name = "gcc_pcie_1_slv_q2a_axi_clk", 2910 .ops = &clk_branch2_ops, 2911 }, 2912 }, 2913 }; 2914 2915 static struct clk_branch gcc_pcie_2_aux_clk = { 2916 .halt_reg = 0x13038, 2917 .halt_check = BRANCH_HALT_VOTED, 2918 .clkr = { 2919 .enable_reg = 0x52020, 2920 .enable_mask = BIT(22), 2921 .hw.init = &(const struct clk_init_data) { 2922 .name = "gcc_pcie_2_aux_clk", 2923 .parent_hws = (const struct clk_hw*[]) { 2924 &gcc_pcie_2_aux_clk_src.clkr.hw, 2925 }, 2926 .num_parents = 1, 2927 .flags = CLK_SET_RATE_PARENT, 2928 .ops = &clk_branch2_ops, 2929 }, 2930 }, 2931 }; 2932 2933 static struct clk_branch gcc_pcie_2_cfg_ahb_clk = { 2934 .halt_reg = 0x13034, 2935 .halt_check = BRANCH_HALT_VOTED, 2936 .hwcg_reg = 0x13034, 2937 .hwcg_bit = 1, 2938 .clkr = { 2939 .enable_reg = 0x52020, 2940 .enable_mask = BIT(21), 2941 .hw.init = &(const struct clk_init_data) { 2942 .name = "gcc_pcie_2_cfg_ahb_clk", 2943 .ops = &clk_branch2_ops, 2944 }, 2945 }, 2946 }; 2947 2948 static struct clk_branch gcc_pcie_2_mstr_axi_clk = { 2949 .halt_reg = 0x13028, 2950 .halt_check = BRANCH_HALT_SKIP, 2951 .hwcg_reg = 0x13028, 2952 .hwcg_bit = 1, 2953 .clkr = { 2954 .enable_reg = 0x52020, 2955 .enable_mask = BIT(20), 2956 .hw.init = &(const struct clk_init_data) { 2957 .name = "gcc_pcie_2_mstr_axi_clk", 2958 .ops = &clk_branch2_ops, 2959 }, 2960 }, 2961 }; 2962 2963 static struct clk_branch gcc_pcie_2_pipe_clk = { 2964 .halt_reg = 0x13044, 2965 .halt_check = BRANCH_HALT_SKIP, 2966 .clkr = { 2967 .enable_reg = 0x52020, 2968 .enable_mask = BIT(23), 2969 .hw.init = &(const struct clk_init_data) { 2970 .name = "gcc_pcie_2_pipe_clk", 2971 .ops = &clk_branch2_ops, 2972 }, 2973 }, 2974 }; 2975 2976 static struct clk_branch gcc_pcie_2_slv_axi_clk = { 2977 .halt_reg = 0x1301c, 2978 .halt_check = BRANCH_HALT_VOTED, 2979 .hwcg_reg = 0x1301c, 2980 .hwcg_bit = 1, 2981 .clkr = { 2982 .enable_reg = 0x52020, 2983 .enable_mask = BIT(19), 2984 .hw.init = &(const struct clk_init_data) { 2985 .name = "gcc_pcie_2_slv_axi_clk", 2986 .ops = &clk_branch2_ops, 2987 }, 2988 }, 2989 }; 2990 2991 static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = { 2992 .halt_reg = 0x13018, 2993 .halt_check = BRANCH_HALT_VOTED, 2994 .clkr = { 2995 .enable_reg = 0x52020, 2996 .enable_mask = BIT(18), 2997 .hw.init = &(const struct clk_init_data) { 2998 .name = "gcc_pcie_2_slv_q2a_axi_clk", 2999 .ops = &clk_branch2_ops, 3000 }, 3001 }, 3002 }; 3003 3004 static struct clk_branch gcc_pcie_3_aux_clk = { 3005 .halt_reg = 0x58038, 3006 .halt_check = BRANCH_HALT_VOTED, 3007 .clkr = { 3008 .enable_reg = 0x52020, 3009 .enable_mask = BIT(1), 3010 .hw.init = &(const struct clk_init_data) { 3011 .name = "gcc_pcie_3_aux_clk", 3012 .parent_hws = (const struct clk_hw*[]) { 3013 &gcc_pcie_3_aux_clk_src.clkr.hw, 3014 }, 3015 .num_parents = 1, 3016 .flags = CLK_SET_RATE_PARENT, 3017 .ops = &clk_branch2_ops, 3018 }, 3019 }, 3020 }; 3021 3022 static struct clk_branch gcc_pcie_3_cfg_ahb_clk = { 3023 .halt_reg = 0x58034, 3024 .halt_check = BRANCH_HALT_VOTED, 3025 .hwcg_reg = 0x58034, 3026 .hwcg_bit = 1, 3027 .clkr = { 3028 .enable_reg = 0x52020, 3029 .enable_mask = BIT(0), 3030 .hw.init = &(const struct clk_init_data) { 3031 .name = "gcc_pcie_3_cfg_ahb_clk", 3032 .ops = &clk_branch2_ops, 3033 }, 3034 }, 3035 }; 3036 3037 static struct clk_branch gcc_pcie_3_mstr_axi_clk = { 3038 .halt_reg = 0x58028, 3039 .halt_check = BRANCH_HALT_SKIP, 3040 .hwcg_reg = 0x58028, 3041 .hwcg_bit = 1, 3042 .clkr = { 3043 .enable_reg = 0x52018, 3044 .enable_mask = BIT(31), 3045 .hw.init = &(const struct clk_init_data) { 3046 .name = "gcc_pcie_3_mstr_axi_clk", 3047 .ops = &clk_branch2_ops, 3048 }, 3049 }, 3050 }; 3051 3052 static struct clk_branch gcc_pcie_3_phy_aux_clk = { 3053 .halt_reg = 0x58044, 3054 .halt_check = BRANCH_HALT_VOTED, 3055 .clkr = { 3056 .enable_reg = 0x52020, 3057 .enable_mask = BIT(2), 3058 .hw.init = &(const struct clk_init_data) { 3059 .name = "gcc_pcie_3_phy_aux_clk", 3060 .ops = &clk_branch2_ops, 3061 }, 3062 }, 3063 }; 3064 3065 static struct clk_branch gcc_pcie_3_phy_rchng_clk = { 3066 .halt_reg = 0x5805c, 3067 .halt_check = BRANCH_HALT_VOTED, 3068 .clkr = { 3069 .enable_reg = 0x52020, 3070 .enable_mask = BIT(4), 3071 .hw.init = &(const struct clk_init_data) { 3072 .name = "gcc_pcie_3_phy_rchng_clk", 3073 .parent_hws = (const struct clk_hw*[]) { 3074 &gcc_pcie_3_phy_rchng_clk_src.clkr.hw, 3075 }, 3076 .num_parents = 1, 3077 .flags = CLK_SET_RATE_PARENT, 3078 .ops = &clk_branch2_ops, 3079 }, 3080 }, 3081 }; 3082 3083 static struct clk_branch gcc_pcie_3_pipe_clk = { 3084 .halt_reg = 0x58050, 3085 .halt_check = BRANCH_HALT_SKIP, 3086 .clkr = { 3087 .enable_reg = 0x52020, 3088 .enable_mask = BIT(3), 3089 .hw.init = &(const struct clk_init_data) { 3090 .name = "gcc_pcie_3_pipe_clk", 3091 .ops = &clk_branch2_ops, 3092 }, 3093 }, 3094 }; 3095 3096 static struct clk_branch gcc_pcie_3_pipediv2_clk = { 3097 .halt_reg = 0x58060, 3098 .halt_check = BRANCH_HALT_SKIP, 3099 .clkr = { 3100 .enable_reg = 0x52020, 3101 .enable_mask = BIT(5), 3102 .hw.init = &(const struct clk_init_data) { 3103 .name = "gcc_pcie_3_pipediv2_clk", 3104 .parent_hws = (const struct clk_hw*[]) { 3105 &gcc_pcie_3_pipe_div_clk_src.clkr.hw, 3106 }, 3107 .num_parents = 1, 3108 .flags = CLK_SET_RATE_PARENT, 3109 .ops = &clk_branch2_ops, 3110 }, 3111 }, 3112 }; 3113 3114 static struct clk_branch gcc_pcie_3_slv_axi_clk = { 3115 .halt_reg = 0x5801c, 3116 .halt_check = BRANCH_HALT_VOTED, 3117 .hwcg_reg = 0x5801c, 3118 .hwcg_bit = 1, 3119 .clkr = { 3120 .enable_reg = 0x52018, 3121 .enable_mask = BIT(30), 3122 .hw.init = &(const struct clk_init_data) { 3123 .name = "gcc_pcie_3_slv_axi_clk", 3124 .ops = &clk_branch2_ops, 3125 }, 3126 }, 3127 }; 3128 3129 static struct clk_branch gcc_pcie_3_slv_q2a_axi_clk = { 3130 .halt_reg = 0x58018, 3131 .halt_check = BRANCH_HALT_VOTED, 3132 .clkr = { 3133 .enable_reg = 0x52018, 3134 .enable_mask = BIT(29), 3135 .hw.init = &(const struct clk_init_data) { 3136 .name = "gcc_pcie_3_slv_q2a_axi_clk", 3137 .ops = &clk_branch2_ops, 3138 }, 3139 }, 3140 }; 3141 3142 static struct clk_branch gcc_pcie_4_aux_clk = { 3143 .halt_reg = 0x6b038, 3144 .halt_check = BRANCH_HALT_VOTED, 3145 .clkr = { 3146 .enable_reg = 0x52008, 3147 .enable_mask = BIT(3), 3148 .hw.init = &(const struct clk_init_data) { 3149 .name = "gcc_pcie_4_aux_clk", 3150 .parent_hws = (const struct clk_hw*[]) { 3151 &gcc_pcie_4_aux_clk_src.clkr.hw, 3152 }, 3153 .num_parents = 1, 3154 .flags = CLK_SET_RATE_PARENT, 3155 .ops = &clk_branch2_ops, 3156 }, 3157 }, 3158 }; 3159 3160 static struct clk_branch gcc_pcie_4_cfg_ahb_clk = { 3161 .halt_reg = 0x6b034, 3162 .halt_check = BRANCH_HALT_VOTED, 3163 .hwcg_reg = 0x6b034, 3164 .hwcg_bit = 1, 3165 .clkr = { 3166 .enable_reg = 0x52008, 3167 .enable_mask = BIT(2), 3168 .hw.init = &(const struct clk_init_data) { 3169 .name = "gcc_pcie_4_cfg_ahb_clk", 3170 .ops = &clk_branch2_ops, 3171 }, 3172 }, 3173 }; 3174 3175 static struct clk_branch gcc_pcie_4_mstr_axi_clk = { 3176 .halt_reg = 0x6b028, 3177 .halt_check = BRANCH_HALT_SKIP, 3178 .hwcg_reg = 0x6b028, 3179 .hwcg_bit = 1, 3180 .clkr = { 3181 .enable_reg = 0x52008, 3182 .enable_mask = BIT(1), 3183 .hw.init = &(const struct clk_init_data) { 3184 .name = "gcc_pcie_4_mstr_axi_clk", 3185 .ops = &clk_branch2_ops, 3186 }, 3187 }, 3188 }; 3189 3190 static struct clk_branch gcc_pcie_4_phy_rchng_clk = { 3191 .halt_reg = 0x6b050, 3192 .halt_check = BRANCH_HALT_VOTED, 3193 .clkr = { 3194 .enable_reg = 0x52000, 3195 .enable_mask = BIT(22), 3196 .hw.init = &(const struct clk_init_data) { 3197 .name = "gcc_pcie_4_phy_rchng_clk", 3198 .parent_hws = (const struct clk_hw*[]) { 3199 &gcc_pcie_4_phy_rchng_clk_src.clkr.hw, 3200 }, 3201 .num_parents = 1, 3202 .flags = CLK_SET_RATE_PARENT, 3203 .ops = &clk_branch2_ops, 3204 }, 3205 }, 3206 }; 3207 3208 static struct clk_branch gcc_pcie_4_pipe_clk = { 3209 .halt_reg = 0x6b044, 3210 .halt_check = BRANCH_HALT_SKIP, 3211 .clkr = { 3212 .enable_reg = 0x52008, 3213 .enable_mask = BIT(4), 3214 .hw.init = &(const struct clk_init_data) { 3215 .name = "gcc_pcie_4_pipe_clk", 3216 .ops = &clk_branch2_ops, 3217 }, 3218 }, 3219 }; 3220 3221 static struct clk_branch gcc_pcie_4_pipediv2_clk = { 3222 .halt_reg = 0x6b054, 3223 .halt_check = BRANCH_HALT_SKIP, 3224 .clkr = { 3225 .enable_reg = 0x52010, 3226 .enable_mask = BIT(27), 3227 .hw.init = &(const struct clk_init_data) { 3228 .name = "gcc_pcie_4_pipediv2_clk", 3229 .parent_hws = (const struct clk_hw*[]) { 3230 &gcc_pcie_4_pipe_div_clk_src.clkr.hw, 3231 }, 3232 .num_parents = 1, 3233 .flags = CLK_SET_RATE_PARENT, 3234 .ops = &clk_branch2_ops, 3235 }, 3236 }, 3237 }; 3238 3239 static struct clk_branch gcc_pcie_4_slv_axi_clk = { 3240 .halt_reg = 0x6b01c, 3241 .halt_check = BRANCH_HALT_VOTED, 3242 .hwcg_reg = 0x6b01c, 3243 .hwcg_bit = 1, 3244 .clkr = { 3245 .enable_reg = 0x52008, 3246 .enable_mask = BIT(0), 3247 .hw.init = &(const struct clk_init_data) { 3248 .name = "gcc_pcie_4_slv_axi_clk", 3249 .ops = &clk_branch2_ops, 3250 }, 3251 }, 3252 }; 3253 3254 static struct clk_branch gcc_pcie_4_slv_q2a_axi_clk = { 3255 .halt_reg = 0x6b018, 3256 .halt_check = BRANCH_HALT_VOTED, 3257 .clkr = { 3258 .enable_reg = 0x52008, 3259 .enable_mask = BIT(5), 3260 .hw.init = &(const struct clk_init_data) { 3261 .name = "gcc_pcie_4_slv_q2a_axi_clk", 3262 .ops = &clk_branch2_ops, 3263 }, 3264 }, 3265 }; 3266 3267 static struct clk_branch gcc_pcie_5_aux_clk = { 3268 .halt_reg = 0x2f038, 3269 .halt_check = BRANCH_HALT_VOTED, 3270 .clkr = { 3271 .enable_reg = 0x52018, 3272 .enable_mask = BIT(16), 3273 .hw.init = &(const struct clk_init_data) { 3274 .name = "gcc_pcie_5_aux_clk", 3275 .parent_hws = (const struct clk_hw*[]) { 3276 &gcc_pcie_5_aux_clk_src.clkr.hw, 3277 }, 3278 .num_parents = 1, 3279 .flags = CLK_SET_RATE_PARENT, 3280 .ops = &clk_branch2_ops, 3281 }, 3282 }, 3283 }; 3284 3285 static struct clk_branch gcc_pcie_5_cfg_ahb_clk = { 3286 .halt_reg = 0x2f034, 3287 .halt_check = BRANCH_HALT_VOTED, 3288 .hwcg_reg = 0x2f034, 3289 .hwcg_bit = 1, 3290 .clkr = { 3291 .enable_reg = 0x52018, 3292 .enable_mask = BIT(15), 3293 .hw.init = &(const struct clk_init_data) { 3294 .name = "gcc_pcie_5_cfg_ahb_clk", 3295 .ops = &clk_branch2_ops, 3296 }, 3297 }, 3298 }; 3299 3300 static struct clk_branch gcc_pcie_5_mstr_axi_clk = { 3301 .halt_reg = 0x2f028, 3302 .halt_check = BRANCH_HALT_SKIP, 3303 .hwcg_reg = 0x2f028, 3304 .hwcg_bit = 1, 3305 .clkr = { 3306 .enable_reg = 0x52018, 3307 .enable_mask = BIT(14), 3308 .hw.init = &(const struct clk_init_data) { 3309 .name = "gcc_pcie_5_mstr_axi_clk", 3310 .ops = &clk_branch2_ops, 3311 }, 3312 }, 3313 }; 3314 3315 static struct clk_branch gcc_pcie_5_phy_rchng_clk = { 3316 .halt_reg = 0x2f050, 3317 .halt_check = BRANCH_HALT_VOTED, 3318 .clkr = { 3319 .enable_reg = 0x52018, 3320 .enable_mask = BIT(18), 3321 .hw.init = &(const struct clk_init_data) { 3322 .name = "gcc_pcie_5_phy_rchng_clk", 3323 .parent_hws = (const struct clk_hw*[]) { 3324 &gcc_pcie_5_phy_rchng_clk_src.clkr.hw, 3325 }, 3326 .num_parents = 1, 3327 .flags = CLK_SET_RATE_PARENT, 3328 .ops = &clk_branch2_ops, 3329 }, 3330 }, 3331 }; 3332 3333 static struct clk_branch gcc_pcie_5_pipe_clk = { 3334 .halt_reg = 0x2f044, 3335 .halt_check = BRANCH_HALT_SKIP, 3336 .clkr = { 3337 .enable_reg = 0x52018, 3338 .enable_mask = BIT(17), 3339 .hw.init = &(const struct clk_init_data) { 3340 .name = "gcc_pcie_5_pipe_clk", 3341 .ops = &clk_branch2_ops, 3342 }, 3343 }, 3344 }; 3345 3346 static struct clk_branch gcc_pcie_5_pipediv2_clk = { 3347 .halt_reg = 0x2f054, 3348 .halt_check = BRANCH_HALT_SKIP, 3349 .clkr = { 3350 .enable_reg = 0x52018, 3351 .enable_mask = BIT(19), 3352 .hw.init = &(const struct clk_init_data) { 3353 .name = "gcc_pcie_5_pipediv2_clk", 3354 .parent_hws = (const struct clk_hw*[]) { 3355 &gcc_pcie_5_pipe_div_clk_src.clkr.hw, 3356 }, 3357 .num_parents = 1, 3358 .flags = CLK_SET_RATE_PARENT, 3359 .ops = &clk_branch2_ops, 3360 }, 3361 }, 3362 }; 3363 3364 static struct clk_branch gcc_pcie_5_slv_axi_clk = { 3365 .halt_reg = 0x2f01c, 3366 .halt_check = BRANCH_HALT_VOTED, 3367 .hwcg_reg = 0x2f01c, 3368 .hwcg_bit = 1, 3369 .clkr = { 3370 .enable_reg = 0x52018, 3371 .enable_mask = BIT(13), 3372 .hw.init = &(const struct clk_init_data) { 3373 .name = "gcc_pcie_5_slv_axi_clk", 3374 .ops = &clk_branch2_ops, 3375 }, 3376 }, 3377 }; 3378 3379 static struct clk_branch gcc_pcie_5_slv_q2a_axi_clk = { 3380 .halt_reg = 0x2f018, 3381 .halt_check = BRANCH_HALT_VOTED, 3382 .clkr = { 3383 .enable_reg = 0x52018, 3384 .enable_mask = BIT(12), 3385 .hw.init = &(const struct clk_init_data) { 3386 .name = "gcc_pcie_5_slv_q2a_axi_clk", 3387 .ops = &clk_branch2_ops, 3388 }, 3389 }, 3390 }; 3391 3392 static struct clk_branch gcc_pcie_6a_aux_clk = { 3393 .halt_reg = 0x31038, 3394 .halt_check = BRANCH_HALT_VOTED, 3395 .clkr = { 3396 .enable_reg = 0x52018, 3397 .enable_mask = BIT(24), 3398 .hw.init = &(const struct clk_init_data) { 3399 .name = "gcc_pcie_6a_aux_clk", 3400 .parent_hws = (const struct clk_hw*[]) { 3401 &gcc_pcie_6a_aux_clk_src.clkr.hw, 3402 }, 3403 .num_parents = 1, 3404 .flags = CLK_SET_RATE_PARENT, 3405 .ops = &clk_branch2_ops, 3406 }, 3407 }, 3408 }; 3409 3410 static struct clk_branch gcc_pcie_6a_cfg_ahb_clk = { 3411 .halt_reg = 0x31034, 3412 .halt_check = BRANCH_HALT_VOTED, 3413 .hwcg_reg = 0x31034, 3414 .hwcg_bit = 1, 3415 .clkr = { 3416 .enable_reg = 0x52018, 3417 .enable_mask = BIT(23), 3418 .hw.init = &(const struct clk_init_data) { 3419 .name = "gcc_pcie_6a_cfg_ahb_clk", 3420 .ops = &clk_branch2_ops, 3421 }, 3422 }, 3423 }; 3424 3425 static struct clk_branch gcc_pcie_6a_mstr_axi_clk = { 3426 .halt_reg = 0x31028, 3427 .halt_check = BRANCH_HALT_SKIP, 3428 .hwcg_reg = 0x31028, 3429 .hwcg_bit = 1, 3430 .clkr = { 3431 .enable_reg = 0x52018, 3432 .enable_mask = BIT(22), 3433 .hw.init = &(const struct clk_init_data) { 3434 .name = "gcc_pcie_6a_mstr_axi_clk", 3435 .ops = &clk_branch2_ops, 3436 }, 3437 }, 3438 }; 3439 3440 static struct clk_branch gcc_pcie_6a_phy_aux_clk = { 3441 .halt_reg = 0x31044, 3442 .halt_check = BRANCH_HALT_VOTED, 3443 .clkr = { 3444 .enable_reg = 0x52018, 3445 .enable_mask = BIT(25), 3446 .hw.init = &(const struct clk_init_data) { 3447 .name = "gcc_pcie_6a_phy_aux_clk", 3448 .ops = &clk_branch2_ops, 3449 }, 3450 }, 3451 }; 3452 3453 static struct clk_branch gcc_pcie_6a_phy_rchng_clk = { 3454 .halt_reg = 0x3105c, 3455 .halt_check = BRANCH_HALT_VOTED, 3456 .clkr = { 3457 .enable_reg = 0x52018, 3458 .enable_mask = BIT(27), 3459 .hw.init = &(const struct clk_init_data) { 3460 .name = "gcc_pcie_6a_phy_rchng_clk", 3461 .parent_hws = (const struct clk_hw*[]) { 3462 &gcc_pcie_6a_phy_rchng_clk_src.clkr.hw, 3463 }, 3464 .num_parents = 1, 3465 .flags = CLK_SET_RATE_PARENT, 3466 .ops = &clk_branch2_ops, 3467 }, 3468 }, 3469 }; 3470 3471 static struct clk_branch gcc_pcie_6a_pipe_clk = { 3472 .halt_reg = 0x31050, 3473 .halt_check = BRANCH_HALT_SKIP, 3474 .clkr = { 3475 .enable_reg = 0x52018, 3476 .enable_mask = BIT(26), 3477 .hw.init = &(const struct clk_init_data) { 3478 .name = "gcc_pcie_6a_pipe_clk", 3479 .ops = &clk_branch2_ops, 3480 }, 3481 }, 3482 }; 3483 3484 static struct clk_branch gcc_pcie_6a_pipediv2_clk = { 3485 .halt_reg = 0x31060, 3486 .halt_check = BRANCH_HALT_SKIP, 3487 .clkr = { 3488 .enable_reg = 0x52018, 3489 .enable_mask = BIT(28), 3490 .hw.init = &(const struct clk_init_data) { 3491 .name = "gcc_pcie_6a_pipediv2_clk", 3492 .parent_hws = (const struct clk_hw*[]) { 3493 &gcc_pcie_6a_pipe_div_clk_src.clkr.hw, 3494 }, 3495 .num_parents = 1, 3496 .flags = CLK_SET_RATE_PARENT, 3497 .ops = &clk_branch2_ops, 3498 }, 3499 }, 3500 }; 3501 3502 static struct clk_branch gcc_pcie_6a_slv_axi_clk = { 3503 .halt_reg = 0x3101c, 3504 .halt_check = BRANCH_HALT_VOTED, 3505 .hwcg_reg = 0x3101c, 3506 .hwcg_bit = 1, 3507 .clkr = { 3508 .enable_reg = 0x52018, 3509 .enable_mask = BIT(21), 3510 .hw.init = &(const struct clk_init_data) { 3511 .name = "gcc_pcie_6a_slv_axi_clk", 3512 .ops = &clk_branch2_ops, 3513 }, 3514 }, 3515 }; 3516 3517 static struct clk_branch gcc_pcie_6a_slv_q2a_axi_clk = { 3518 .halt_reg = 0x31018, 3519 .halt_check = BRANCH_HALT_VOTED, 3520 .clkr = { 3521 .enable_reg = 0x52018, 3522 .enable_mask = BIT(20), 3523 .hw.init = &(const struct clk_init_data) { 3524 .name = "gcc_pcie_6a_slv_q2a_axi_clk", 3525 .ops = &clk_branch2_ops, 3526 }, 3527 }, 3528 }; 3529 3530 static struct clk_branch gcc_pcie_6b_aux_clk = { 3531 .halt_reg = 0x8d038, 3532 .halt_check = BRANCH_HALT_VOTED, 3533 .clkr = { 3534 .enable_reg = 0x52000, 3535 .enable_mask = BIT(29), 3536 .hw.init = &(const struct clk_init_data) { 3537 .name = "gcc_pcie_6b_aux_clk", 3538 .parent_hws = (const struct clk_hw*[]) { 3539 &gcc_pcie_6b_aux_clk_src.clkr.hw, 3540 }, 3541 .num_parents = 1, 3542 .flags = CLK_SET_RATE_PARENT, 3543 .ops = &clk_branch2_ops, 3544 }, 3545 }, 3546 }; 3547 3548 static struct clk_branch gcc_pcie_6b_cfg_ahb_clk = { 3549 .halt_reg = 0x8d034, 3550 .halt_check = BRANCH_HALT_VOTED, 3551 .hwcg_reg = 0x8d034, 3552 .hwcg_bit = 1, 3553 .clkr = { 3554 .enable_reg = 0x52000, 3555 .enable_mask = BIT(28), 3556 .hw.init = &(const struct clk_init_data) { 3557 .name = "gcc_pcie_6b_cfg_ahb_clk", 3558 .ops = &clk_branch2_ops, 3559 }, 3560 }, 3561 }; 3562 3563 static struct clk_branch gcc_pcie_6b_mstr_axi_clk = { 3564 .halt_reg = 0x8d028, 3565 .halt_check = BRANCH_HALT_SKIP, 3566 .hwcg_reg = 0x8d028, 3567 .hwcg_bit = 1, 3568 .clkr = { 3569 .enable_reg = 0x52000, 3570 .enable_mask = BIT(27), 3571 .hw.init = &(const struct clk_init_data) { 3572 .name = "gcc_pcie_6b_mstr_axi_clk", 3573 .ops = &clk_branch2_ops, 3574 }, 3575 }, 3576 }; 3577 3578 static struct clk_branch gcc_pcie_6b_phy_aux_clk = { 3579 .halt_reg = 0x8d044, 3580 .halt_check = BRANCH_HALT_VOTED, 3581 .clkr = { 3582 .enable_reg = 0x52000, 3583 .enable_mask = BIT(24), 3584 .hw.init = &(const struct clk_init_data) { 3585 .name = "gcc_pcie_6b_phy_aux_clk", 3586 .ops = &clk_branch2_ops, 3587 }, 3588 }, 3589 }; 3590 3591 static struct clk_branch gcc_pcie_6b_phy_rchng_clk = { 3592 .halt_reg = 0x8d05c, 3593 .halt_check = BRANCH_HALT_VOTED, 3594 .clkr = { 3595 .enable_reg = 0x52000, 3596 .enable_mask = BIT(23), 3597 .hw.init = &(const struct clk_init_data) { 3598 .name = "gcc_pcie_6b_phy_rchng_clk", 3599 .parent_hws = (const struct clk_hw*[]) { 3600 &gcc_pcie_6b_phy_rchng_clk_src.clkr.hw, 3601 }, 3602 .num_parents = 1, 3603 .flags = CLK_SET_RATE_PARENT, 3604 .ops = &clk_branch2_ops, 3605 }, 3606 }, 3607 }; 3608 3609 static struct clk_branch gcc_pcie_6b_pipe_clk = { 3610 .halt_reg = 0x8d050, 3611 .halt_check = BRANCH_HALT_SKIP, 3612 .clkr = { 3613 .enable_reg = 0x52000, 3614 .enable_mask = BIT(30), 3615 .hw.init = &(const struct clk_init_data) { 3616 .name = "gcc_pcie_6b_pipe_clk", 3617 .ops = &clk_branch2_ops, 3618 }, 3619 }, 3620 }; 3621 3622 static struct clk_branch gcc_pcie_6b_pipediv2_clk = { 3623 .halt_reg = 0x8d060, 3624 .halt_check = BRANCH_HALT_SKIP, 3625 .clkr = { 3626 .enable_reg = 0x52010, 3627 .enable_mask = BIT(28), 3628 .hw.init = &(const struct clk_init_data) { 3629 .name = "gcc_pcie_6b_pipediv2_clk", 3630 .parent_hws = (const struct clk_hw*[]) { 3631 &gcc_pcie_6b_pipe_div_clk_src.clkr.hw, 3632 }, 3633 .num_parents = 1, 3634 .flags = CLK_SET_RATE_PARENT, 3635 .ops = &clk_branch2_ops, 3636 }, 3637 }, 3638 }; 3639 3640 static struct clk_branch gcc_pcie_6b_slv_axi_clk = { 3641 .halt_reg = 0x8d01c, 3642 .halt_check = BRANCH_HALT_VOTED, 3643 .hwcg_reg = 0x8d01c, 3644 .hwcg_bit = 1, 3645 .clkr = { 3646 .enable_reg = 0x52000, 3647 .enable_mask = BIT(26), 3648 .hw.init = &(const struct clk_init_data) { 3649 .name = "gcc_pcie_6b_slv_axi_clk", 3650 .ops = &clk_branch2_ops, 3651 }, 3652 }, 3653 }; 3654 3655 static struct clk_branch gcc_pcie_6b_slv_q2a_axi_clk = { 3656 .halt_reg = 0x8d018, 3657 .halt_check = BRANCH_HALT_VOTED, 3658 .clkr = { 3659 .enable_reg = 0x52000, 3660 .enable_mask = BIT(25), 3661 .hw.init = &(const struct clk_init_data) { 3662 .name = "gcc_pcie_6b_slv_q2a_axi_clk", 3663 .ops = &clk_branch2_ops, 3664 }, 3665 }, 3666 }; 3667 3668 static struct clk_branch gcc_pcie_rscc_ahb_clk = { 3669 .halt_reg = 0xa4008, 3670 .halt_check = BRANCH_HALT_VOTED, 3671 .hwcg_reg = 0xa4008, 3672 .hwcg_bit = 1, 3673 .clkr = { 3674 .enable_reg = 0x52028, 3675 .enable_mask = BIT(18), 3676 .hw.init = &(const struct clk_init_data) { 3677 .name = "gcc_pcie_rscc_ahb_clk", 3678 .ops = &clk_branch2_ops, 3679 }, 3680 }, 3681 }; 3682 3683 static struct clk_branch gcc_pcie_rscc_xo_clk = { 3684 .halt_reg = 0xa4004, 3685 .halt_check = BRANCH_HALT_VOTED, 3686 .clkr = { 3687 .enable_reg = 0x52028, 3688 .enable_mask = BIT(17), 3689 .hw.init = &(const struct clk_init_data) { 3690 .name = "gcc_pcie_rscc_xo_clk", 3691 .parent_hws = (const struct clk_hw*[]) { 3692 &gcc_pcie_rscc_xo_clk_src.clkr.hw, 3693 }, 3694 .num_parents = 1, 3695 .flags = CLK_SET_RATE_PARENT, 3696 .ops = &clk_branch2_ops, 3697 }, 3698 }, 3699 }; 3700 3701 static struct clk_branch gcc_pdm2_clk = { 3702 .halt_reg = 0x3300c, 3703 .halt_check = BRANCH_HALT, 3704 .clkr = { 3705 .enable_reg = 0x3300c, 3706 .enable_mask = BIT(0), 3707 .hw.init = &(const struct clk_init_data) { 3708 .name = "gcc_pdm2_clk", 3709 .parent_hws = (const struct clk_hw*[]) { 3710 &gcc_pdm2_clk_src.clkr.hw, 3711 }, 3712 .num_parents = 1, 3713 .flags = CLK_SET_RATE_PARENT, 3714 .ops = &clk_branch2_ops, 3715 }, 3716 }, 3717 }; 3718 3719 static struct clk_branch gcc_pdm_ahb_clk = { 3720 .halt_reg = 0x33004, 3721 .halt_check = BRANCH_HALT_VOTED, 3722 .hwcg_reg = 0x33004, 3723 .hwcg_bit = 1, 3724 .clkr = { 3725 .enable_reg = 0x33004, 3726 .enable_mask = BIT(0), 3727 .hw.init = &(const struct clk_init_data) { 3728 .name = "gcc_pdm_ahb_clk", 3729 .ops = &clk_branch2_ops, 3730 }, 3731 }, 3732 }; 3733 3734 static struct clk_branch gcc_pdm_xo4_clk = { 3735 .halt_reg = 0x33008, 3736 .halt_check = BRANCH_HALT, 3737 .clkr = { 3738 .enable_reg = 0x33008, 3739 .enable_mask = BIT(0), 3740 .hw.init = &(const struct clk_init_data) { 3741 .name = "gcc_pdm_xo4_clk", 3742 .ops = &clk_branch2_ops, 3743 }, 3744 }, 3745 }; 3746 3747 static struct clk_branch gcc_qmip_av1e_ahb_clk = { 3748 .halt_reg = 0x4a018, 3749 .halt_check = BRANCH_HALT_VOTED, 3750 .hwcg_reg = 0x4a018, 3751 .hwcg_bit = 1, 3752 .clkr = { 3753 .enable_reg = 0x4a018, 3754 .enable_mask = BIT(0), 3755 .hw.init = &(const struct clk_init_data) { 3756 .name = "gcc_qmip_av1e_ahb_clk", 3757 .ops = &clk_branch2_ops, 3758 }, 3759 }, 3760 }; 3761 3762 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 3763 .halt_reg = 0x26008, 3764 .halt_check = BRANCH_HALT_VOTED, 3765 .hwcg_reg = 0x26008, 3766 .hwcg_bit = 1, 3767 .clkr = { 3768 .enable_reg = 0x26008, 3769 .enable_mask = BIT(0), 3770 .hw.init = &(const struct clk_init_data) { 3771 .name = "gcc_qmip_camera_nrt_ahb_clk", 3772 .ops = &clk_branch2_ops, 3773 }, 3774 }, 3775 }; 3776 3777 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 3778 .halt_reg = 0x2600c, 3779 .halt_check = BRANCH_HALT_VOTED, 3780 .hwcg_reg = 0x2600c, 3781 .hwcg_bit = 1, 3782 .clkr = { 3783 .enable_reg = 0x2600c, 3784 .enable_mask = BIT(0), 3785 .hw.init = &(const struct clk_init_data) { 3786 .name = "gcc_qmip_camera_rt_ahb_clk", 3787 .ops = &clk_branch2_ops, 3788 }, 3789 }, 3790 }; 3791 3792 static struct clk_branch gcc_qmip_disp_ahb_clk = { 3793 .halt_reg = 0x27008, 3794 .halt_check = BRANCH_HALT_VOTED, 3795 .hwcg_reg = 0x27008, 3796 .hwcg_bit = 1, 3797 .clkr = { 3798 .enable_reg = 0x27008, 3799 .enable_mask = BIT(0), 3800 .hw.init = &(const struct clk_init_data) { 3801 .name = "gcc_qmip_disp_ahb_clk", 3802 .ops = &clk_branch2_ops, 3803 }, 3804 }, 3805 }; 3806 3807 static struct clk_branch gcc_qmip_gpu_ahb_clk = { 3808 .halt_reg = 0x71008, 3809 .halt_check = BRANCH_HALT_VOTED, 3810 .hwcg_reg = 0x71008, 3811 .hwcg_bit = 1, 3812 .clkr = { 3813 .enable_reg = 0x71008, 3814 .enable_mask = BIT(0), 3815 .hw.init = &(const struct clk_init_data) { 3816 .name = "gcc_qmip_gpu_ahb_clk", 3817 .ops = &clk_branch2_ops, 3818 }, 3819 }, 3820 }; 3821 3822 static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = { 3823 .halt_reg = 0x32014, 3824 .halt_check = BRANCH_HALT_VOTED, 3825 .hwcg_reg = 0x32014, 3826 .hwcg_bit = 1, 3827 .clkr = { 3828 .enable_reg = 0x32014, 3829 .enable_mask = BIT(0), 3830 .hw.init = &(const struct clk_init_data) { 3831 .name = "gcc_qmip_video_cv_cpu_ahb_clk", 3832 .ops = &clk_branch2_ops, 3833 }, 3834 }, 3835 }; 3836 3837 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 3838 .halt_reg = 0x32008, 3839 .halt_check = BRANCH_HALT_VOTED, 3840 .hwcg_reg = 0x32008, 3841 .hwcg_bit = 1, 3842 .clkr = { 3843 .enable_reg = 0x32008, 3844 .enable_mask = BIT(0), 3845 .hw.init = &(const struct clk_init_data) { 3846 .name = "gcc_qmip_video_cvp_ahb_clk", 3847 .ops = &clk_branch2_ops, 3848 }, 3849 }, 3850 }; 3851 3852 static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = { 3853 .halt_reg = 0x32010, 3854 .halt_check = BRANCH_HALT_VOTED, 3855 .hwcg_reg = 0x32010, 3856 .hwcg_bit = 1, 3857 .clkr = { 3858 .enable_reg = 0x32010, 3859 .enable_mask = BIT(0), 3860 .hw.init = &(const struct clk_init_data) { 3861 .name = "gcc_qmip_video_v_cpu_ahb_clk", 3862 .ops = &clk_branch2_ops, 3863 }, 3864 }, 3865 }; 3866 3867 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 3868 .halt_reg = 0x3200c, 3869 .halt_check = BRANCH_HALT_VOTED, 3870 .hwcg_reg = 0x3200c, 3871 .hwcg_bit = 1, 3872 .clkr = { 3873 .enable_reg = 0x3200c, 3874 .enable_mask = BIT(0), 3875 .hw.init = &(const struct clk_init_data) { 3876 .name = "gcc_qmip_video_vcodec_ahb_clk", 3877 .ops = &clk_branch2_ops, 3878 }, 3879 }, 3880 }; 3881 3882 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 3883 .halt_reg = 0x23018, 3884 .halt_check = BRANCH_HALT_VOTED, 3885 .clkr = { 3886 .enable_reg = 0x52020, 3887 .enable_mask = BIT(9), 3888 .hw.init = &(const struct clk_init_data) { 3889 .name = "gcc_qupv3_wrap0_core_2x_clk", 3890 .ops = &clk_branch2_ops, 3891 }, 3892 }, 3893 }; 3894 3895 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 3896 .halt_reg = 0x23008, 3897 .halt_check = BRANCH_HALT_VOTED, 3898 .clkr = { 3899 .enable_reg = 0x52020, 3900 .enable_mask = BIT(8), 3901 .hw.init = &(const struct clk_init_data) { 3902 .name = "gcc_qupv3_wrap0_core_clk", 3903 .ops = &clk_branch2_ops, 3904 }, 3905 }, 3906 }; 3907 3908 static struct clk_branch gcc_qupv3_wrap0_qspi_s2_clk = { 3909 .halt_reg = 0x42280, 3910 .halt_check = BRANCH_HALT_VOTED, 3911 .clkr = { 3912 .enable_reg = 0x52028, 3913 .enable_mask = BIT(2), 3914 .hw.init = &(const struct clk_init_data) { 3915 .name = "gcc_qupv3_wrap0_qspi_s2_clk", 3916 .parent_hws = (const struct clk_hw*[]) { 3917 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 3918 }, 3919 .num_parents = 1, 3920 .flags = CLK_SET_RATE_PARENT, 3921 .ops = &clk_branch2_ops, 3922 }, 3923 }, 3924 }; 3925 3926 static struct clk_branch gcc_qupv3_wrap0_qspi_s3_clk = { 3927 .halt_reg = 0x423c0, 3928 .halt_check = BRANCH_HALT_VOTED, 3929 .clkr = { 3930 .enable_reg = 0x52028, 3931 .enable_mask = BIT(3), 3932 .hw.init = &(const struct clk_init_data) { 3933 .name = "gcc_qupv3_wrap0_qspi_s3_clk", 3934 .parent_hws = (const struct clk_hw*[]) { 3935 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 3936 }, 3937 .num_parents = 1, 3938 .flags = CLK_SET_RATE_PARENT, 3939 .ops = &clk_branch2_ops, 3940 }, 3941 }, 3942 }; 3943 3944 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 3945 .halt_reg = 0x42004, 3946 .halt_check = BRANCH_HALT_VOTED, 3947 .clkr = { 3948 .enable_reg = 0x52020, 3949 .enable_mask = BIT(10), 3950 .hw.init = &(const struct clk_init_data) { 3951 .name = "gcc_qupv3_wrap0_s0_clk", 3952 .parent_hws = (const struct clk_hw*[]) { 3953 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 3954 }, 3955 .num_parents = 1, 3956 .flags = CLK_SET_RATE_PARENT, 3957 .ops = &clk_branch2_ops, 3958 }, 3959 }, 3960 }; 3961 3962 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 3963 .halt_reg = 0x4213c, 3964 .halt_check = BRANCH_HALT_VOTED, 3965 .clkr = { 3966 .enable_reg = 0x52020, 3967 .enable_mask = BIT(11), 3968 .hw.init = &(const struct clk_init_data) { 3969 .name = "gcc_qupv3_wrap0_s1_clk", 3970 .parent_hws = (const struct clk_hw*[]) { 3971 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 3972 }, 3973 .num_parents = 1, 3974 .flags = CLK_SET_RATE_PARENT, 3975 .ops = &clk_branch2_ops, 3976 }, 3977 }, 3978 }; 3979 3980 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 3981 .halt_reg = 0x42274, 3982 .halt_check = BRANCH_HALT_VOTED, 3983 .clkr = { 3984 .enable_reg = 0x52020, 3985 .enable_mask = BIT(12), 3986 .hw.init = &(const struct clk_init_data) { 3987 .name = "gcc_qupv3_wrap0_s2_clk", 3988 .parent_hws = (const struct clk_hw*[]) { 3989 &gcc_qupv3_wrap0_s2_div_clk_src.clkr.hw, 3990 }, 3991 .num_parents = 1, 3992 .flags = CLK_SET_RATE_PARENT, 3993 .ops = &clk_branch2_ops, 3994 }, 3995 }, 3996 }; 3997 3998 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 3999 .halt_reg = 0x423b4, 4000 .halt_check = BRANCH_HALT_VOTED, 4001 .clkr = { 4002 .enable_reg = 0x52020, 4003 .enable_mask = BIT(13), 4004 .hw.init = &(const struct clk_init_data) { 4005 .name = "gcc_qupv3_wrap0_s3_clk", 4006 .parent_hws = (const struct clk_hw*[]) { 4007 &gcc_qupv3_wrap0_s3_div_clk_src.clkr.hw, 4008 }, 4009 .num_parents = 1, 4010 .flags = CLK_SET_RATE_PARENT, 4011 .ops = &clk_branch2_ops, 4012 }, 4013 }, 4014 }; 4015 4016 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 4017 .halt_reg = 0x424f4, 4018 .halt_check = BRANCH_HALT_VOTED, 4019 .clkr = { 4020 .enable_reg = 0x52020, 4021 .enable_mask = BIT(14), 4022 .hw.init = &(const struct clk_init_data) { 4023 .name = "gcc_qupv3_wrap0_s4_clk", 4024 .parent_hws = (const struct clk_hw*[]) { 4025 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 4026 }, 4027 .num_parents = 1, 4028 .flags = CLK_SET_RATE_PARENT, 4029 .ops = &clk_branch2_ops, 4030 }, 4031 }, 4032 }; 4033 4034 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 4035 .halt_reg = 0x4262c, 4036 .halt_check = BRANCH_HALT_VOTED, 4037 .clkr = { 4038 .enable_reg = 0x52020, 4039 .enable_mask = BIT(15), 4040 .hw.init = &(const struct clk_init_data) { 4041 .name = "gcc_qupv3_wrap0_s5_clk", 4042 .parent_hws = (const struct clk_hw*[]) { 4043 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 4044 }, 4045 .num_parents = 1, 4046 .flags = CLK_SET_RATE_PARENT, 4047 .ops = &clk_branch2_ops, 4048 }, 4049 }, 4050 }; 4051 4052 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 4053 .halt_reg = 0x42764, 4054 .halt_check = BRANCH_HALT_VOTED, 4055 .clkr = { 4056 .enable_reg = 0x52020, 4057 .enable_mask = BIT(16), 4058 .hw.init = &(const struct clk_init_data) { 4059 .name = "gcc_qupv3_wrap0_s6_clk", 4060 .parent_hws = (const struct clk_hw*[]) { 4061 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 4062 }, 4063 .num_parents = 1, 4064 .flags = CLK_SET_RATE_PARENT, 4065 .ops = &clk_branch2_ops, 4066 }, 4067 }, 4068 }; 4069 4070 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 4071 .halt_reg = 0x4289c, 4072 .halt_check = BRANCH_HALT_VOTED, 4073 .clkr = { 4074 .enable_reg = 0x52020, 4075 .enable_mask = BIT(17), 4076 .hw.init = &(const struct clk_init_data) { 4077 .name = "gcc_qupv3_wrap0_s7_clk", 4078 .parent_hws = (const struct clk_hw*[]) { 4079 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, 4080 }, 4081 .num_parents = 1, 4082 .flags = CLK_SET_RATE_PARENT, 4083 .ops = &clk_branch2_ops, 4084 }, 4085 }, 4086 }; 4087 4088 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 4089 .halt_reg = 0x23168, 4090 .halt_check = BRANCH_HALT_VOTED, 4091 .clkr = { 4092 .enable_reg = 0x52008, 4093 .enable_mask = BIT(18), 4094 .hw.init = &(const struct clk_init_data) { 4095 .name = "gcc_qupv3_wrap1_core_2x_clk", 4096 .ops = &clk_branch2_ops, 4097 }, 4098 }, 4099 }; 4100 4101 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 4102 .halt_reg = 0x23158, 4103 .halt_check = BRANCH_HALT_VOTED, 4104 .clkr = { 4105 .enable_reg = 0x52008, 4106 .enable_mask = BIT(19), 4107 .hw.init = &(const struct clk_init_data) { 4108 .name = "gcc_qupv3_wrap1_core_clk", 4109 .ops = &clk_branch2_ops, 4110 }, 4111 }, 4112 }; 4113 4114 static struct clk_branch gcc_qupv3_wrap1_qspi_s2_clk = { 4115 .halt_reg = 0x18280, 4116 .halt_check = BRANCH_HALT_VOTED, 4117 .clkr = { 4118 .enable_reg = 0x52028, 4119 .enable_mask = BIT(4), 4120 .hw.init = &(const struct clk_init_data) { 4121 .name = "gcc_qupv3_wrap1_qspi_s2_clk", 4122 .parent_hws = (const struct clk_hw*[]) { 4123 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 4124 }, 4125 .num_parents = 1, 4126 .flags = CLK_SET_RATE_PARENT, 4127 .ops = &clk_branch2_ops, 4128 }, 4129 }, 4130 }; 4131 4132 static struct clk_branch gcc_qupv3_wrap1_qspi_s3_clk = { 4133 .halt_reg = 0x183c0, 4134 .halt_check = BRANCH_HALT_VOTED, 4135 .clkr = { 4136 .enable_reg = 0x52028, 4137 .enable_mask = BIT(5), 4138 .hw.init = &(const struct clk_init_data) { 4139 .name = "gcc_qupv3_wrap1_qspi_s3_clk", 4140 .parent_hws = (const struct clk_hw*[]) { 4141 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 4142 }, 4143 .num_parents = 1, 4144 .flags = CLK_SET_RATE_PARENT, 4145 .ops = &clk_branch2_ops, 4146 }, 4147 }, 4148 }; 4149 4150 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 4151 .halt_reg = 0x18004, 4152 .halt_check = BRANCH_HALT_VOTED, 4153 .clkr = { 4154 .enable_reg = 0x52008, 4155 .enable_mask = BIT(22), 4156 .hw.init = &(const struct clk_init_data) { 4157 .name = "gcc_qupv3_wrap1_s0_clk", 4158 .parent_hws = (const struct clk_hw*[]) { 4159 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 4160 }, 4161 .num_parents = 1, 4162 .flags = CLK_SET_RATE_PARENT, 4163 .ops = &clk_branch2_ops, 4164 }, 4165 }, 4166 }; 4167 4168 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 4169 .halt_reg = 0x1813c, 4170 .halt_check = BRANCH_HALT_VOTED, 4171 .clkr = { 4172 .enable_reg = 0x52008, 4173 .enable_mask = BIT(23), 4174 .hw.init = &(const struct clk_init_data) { 4175 .name = "gcc_qupv3_wrap1_s1_clk", 4176 .parent_hws = (const struct clk_hw*[]) { 4177 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 4178 }, 4179 .num_parents = 1, 4180 .flags = CLK_SET_RATE_PARENT, 4181 .ops = &clk_branch2_ops, 4182 }, 4183 }, 4184 }; 4185 4186 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 4187 .halt_reg = 0x18274, 4188 .halt_check = BRANCH_HALT_VOTED, 4189 .clkr = { 4190 .enable_reg = 0x52008, 4191 .enable_mask = BIT(24), 4192 .hw.init = &(const struct clk_init_data) { 4193 .name = "gcc_qupv3_wrap1_s2_clk", 4194 .parent_hws = (const struct clk_hw*[]) { 4195 &gcc_qupv3_wrap1_s2_div_clk_src.clkr.hw, 4196 }, 4197 .num_parents = 1, 4198 .flags = CLK_SET_RATE_PARENT, 4199 .ops = &clk_branch2_ops, 4200 }, 4201 }, 4202 }; 4203 4204 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 4205 .halt_reg = 0x183b4, 4206 .halt_check = BRANCH_HALT_VOTED, 4207 .clkr = { 4208 .enable_reg = 0x52008, 4209 .enable_mask = BIT(25), 4210 .hw.init = &(const struct clk_init_data) { 4211 .name = "gcc_qupv3_wrap1_s3_clk", 4212 .parent_hws = (const struct clk_hw*[]) { 4213 &gcc_qupv3_wrap1_s3_div_clk_src.clkr.hw, 4214 }, 4215 .num_parents = 1, 4216 .flags = CLK_SET_RATE_PARENT, 4217 .ops = &clk_branch2_ops, 4218 }, 4219 }, 4220 }; 4221 4222 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 4223 .halt_reg = 0x184f4, 4224 .halt_check = BRANCH_HALT_VOTED, 4225 .clkr = { 4226 .enable_reg = 0x52008, 4227 .enable_mask = BIT(26), 4228 .hw.init = &(const struct clk_init_data) { 4229 .name = "gcc_qupv3_wrap1_s4_clk", 4230 .parent_hws = (const struct clk_hw*[]) { 4231 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 4232 }, 4233 .num_parents = 1, 4234 .flags = CLK_SET_RATE_PARENT, 4235 .ops = &clk_branch2_ops, 4236 }, 4237 }, 4238 }; 4239 4240 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 4241 .halt_reg = 0x1862c, 4242 .halt_check = BRANCH_HALT_VOTED, 4243 .clkr = { 4244 .enable_reg = 0x52008, 4245 .enable_mask = BIT(27), 4246 .hw.init = &(const struct clk_init_data) { 4247 .name = "gcc_qupv3_wrap1_s5_clk", 4248 .parent_hws = (const struct clk_hw*[]) { 4249 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 4250 }, 4251 .num_parents = 1, 4252 .flags = CLK_SET_RATE_PARENT, 4253 .ops = &clk_branch2_ops, 4254 }, 4255 }, 4256 }; 4257 4258 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 4259 .halt_reg = 0x18764, 4260 .halt_check = BRANCH_HALT_VOTED, 4261 .clkr = { 4262 .enable_reg = 0x52008, 4263 .enable_mask = BIT(28), 4264 .hw.init = &(const struct clk_init_data) { 4265 .name = "gcc_qupv3_wrap1_s6_clk", 4266 .parent_hws = (const struct clk_hw*[]) { 4267 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 4268 }, 4269 .num_parents = 1, 4270 .flags = CLK_SET_RATE_PARENT, 4271 .ops = &clk_branch2_ops, 4272 }, 4273 }, 4274 }; 4275 4276 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 4277 .halt_reg = 0x1889c, 4278 .halt_check = BRANCH_HALT_VOTED, 4279 .clkr = { 4280 .enable_reg = 0x52010, 4281 .enable_mask = BIT(16), 4282 .hw.init = &(const struct clk_init_data) { 4283 .name = "gcc_qupv3_wrap1_s7_clk", 4284 .parent_hws = (const struct clk_hw*[]) { 4285 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 4286 }, 4287 .num_parents = 1, 4288 .flags = CLK_SET_RATE_PARENT, 4289 .ops = &clk_branch2_ops, 4290 }, 4291 }, 4292 }; 4293 4294 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { 4295 .halt_reg = 0x232b8, 4296 .halt_check = BRANCH_HALT_VOTED, 4297 .clkr = { 4298 .enable_reg = 0x52010, 4299 .enable_mask = BIT(3), 4300 .hw.init = &(const struct clk_init_data) { 4301 .name = "gcc_qupv3_wrap2_core_2x_clk", 4302 .ops = &clk_branch2_ops, 4303 }, 4304 }, 4305 }; 4306 4307 static struct clk_branch gcc_qupv3_wrap2_core_clk = { 4308 .halt_reg = 0x232a8, 4309 .halt_check = BRANCH_HALT_VOTED, 4310 .clkr = { 4311 .enable_reg = 0x52010, 4312 .enable_mask = BIT(0), 4313 .hw.init = &(const struct clk_init_data) { 4314 .name = "gcc_qupv3_wrap2_core_clk", 4315 .ops = &clk_branch2_ops, 4316 }, 4317 }, 4318 }; 4319 4320 static struct clk_branch gcc_qupv3_wrap2_qspi_s2_clk = { 4321 .halt_reg = 0x1e280, 4322 .halt_check = BRANCH_HALT_VOTED, 4323 .clkr = { 4324 .enable_reg = 0x52028, 4325 .enable_mask = BIT(6), 4326 .hw.init = &(const struct clk_init_data) { 4327 .name = "gcc_qupv3_wrap2_qspi_s2_clk", 4328 .parent_hws = (const struct clk_hw*[]) { 4329 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 4330 }, 4331 .num_parents = 1, 4332 .flags = CLK_SET_RATE_PARENT, 4333 .ops = &clk_branch2_ops, 4334 }, 4335 }, 4336 }; 4337 4338 static struct clk_branch gcc_qupv3_wrap2_qspi_s3_clk = { 4339 .halt_reg = 0x1e3c0, 4340 .halt_check = BRANCH_HALT_VOTED, 4341 .clkr = { 4342 .enable_reg = 0x52028, 4343 .enable_mask = BIT(7), 4344 .hw.init = &(const struct clk_init_data) { 4345 .name = "gcc_qupv3_wrap2_qspi_s3_clk", 4346 .parent_hws = (const struct clk_hw*[]) { 4347 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 4348 }, 4349 .num_parents = 1, 4350 .flags = CLK_SET_RATE_PARENT, 4351 .ops = &clk_branch2_ops, 4352 }, 4353 }, 4354 }; 4355 4356 static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 4357 .halt_reg = 0x1e004, 4358 .halt_check = BRANCH_HALT_VOTED, 4359 .clkr = { 4360 .enable_reg = 0x52010, 4361 .enable_mask = BIT(4), 4362 .hw.init = &(const struct clk_init_data) { 4363 .name = "gcc_qupv3_wrap2_s0_clk", 4364 .parent_hws = (const struct clk_hw*[]) { 4365 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 4366 }, 4367 .num_parents = 1, 4368 .flags = CLK_SET_RATE_PARENT, 4369 .ops = &clk_branch2_ops, 4370 }, 4371 }, 4372 }; 4373 4374 static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 4375 .halt_reg = 0x1e13c, 4376 .halt_check = BRANCH_HALT_VOTED, 4377 .clkr = { 4378 .enable_reg = 0x52010, 4379 .enable_mask = BIT(5), 4380 .hw.init = &(const struct clk_init_data) { 4381 .name = "gcc_qupv3_wrap2_s1_clk", 4382 .parent_hws = (const struct clk_hw*[]) { 4383 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 4384 }, 4385 .num_parents = 1, 4386 .flags = CLK_SET_RATE_PARENT, 4387 .ops = &clk_branch2_ops, 4388 }, 4389 }, 4390 }; 4391 4392 static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 4393 .halt_reg = 0x1e274, 4394 .halt_check = BRANCH_HALT_VOTED, 4395 .clkr = { 4396 .enable_reg = 0x52010, 4397 .enable_mask = BIT(6), 4398 .hw.init = &(const struct clk_init_data) { 4399 .name = "gcc_qupv3_wrap2_s2_clk", 4400 .parent_hws = (const struct clk_hw*[]) { 4401 &gcc_qupv3_wrap2_s2_div_clk_src.clkr.hw, 4402 }, 4403 .num_parents = 1, 4404 .flags = CLK_SET_RATE_PARENT, 4405 .ops = &clk_branch2_ops, 4406 }, 4407 }, 4408 }; 4409 4410 static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 4411 .halt_reg = 0x1e3b4, 4412 .halt_check = BRANCH_HALT_VOTED, 4413 .clkr = { 4414 .enable_reg = 0x52010, 4415 .enable_mask = BIT(7), 4416 .hw.init = &(const struct clk_init_data) { 4417 .name = "gcc_qupv3_wrap2_s3_clk", 4418 .parent_hws = (const struct clk_hw*[]) { 4419 &gcc_qupv3_wrap2_s3_div_clk_src.clkr.hw, 4420 }, 4421 .num_parents = 1, 4422 .flags = CLK_SET_RATE_PARENT, 4423 .ops = &clk_branch2_ops, 4424 }, 4425 }, 4426 }; 4427 4428 static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 4429 .halt_reg = 0x1e4f4, 4430 .halt_check = BRANCH_HALT_VOTED, 4431 .clkr = { 4432 .enable_reg = 0x52010, 4433 .enable_mask = BIT(8), 4434 .hw.init = &(const struct clk_init_data) { 4435 .name = "gcc_qupv3_wrap2_s4_clk", 4436 .parent_hws = (const struct clk_hw*[]) { 4437 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 4438 }, 4439 .num_parents = 1, 4440 .flags = CLK_SET_RATE_PARENT, 4441 .ops = &clk_branch2_ops, 4442 }, 4443 }, 4444 }; 4445 4446 static struct clk_branch gcc_qupv3_wrap2_s5_clk = { 4447 .halt_reg = 0x1e62c, 4448 .halt_check = BRANCH_HALT_VOTED, 4449 .clkr = { 4450 .enable_reg = 0x52010, 4451 .enable_mask = BIT(9), 4452 .hw.init = &(const struct clk_init_data) { 4453 .name = "gcc_qupv3_wrap2_s5_clk", 4454 .parent_hws = (const struct clk_hw*[]) { 4455 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, 4456 }, 4457 .num_parents = 1, 4458 .flags = CLK_SET_RATE_PARENT, 4459 .ops = &clk_branch2_ops, 4460 }, 4461 }, 4462 }; 4463 4464 static struct clk_branch gcc_qupv3_wrap2_s6_clk = { 4465 .halt_reg = 0x1e764, 4466 .halt_check = BRANCH_HALT_VOTED, 4467 .clkr = { 4468 .enable_reg = 0x52010, 4469 .enable_mask = BIT(10), 4470 .hw.init = &(const struct clk_init_data) { 4471 .name = "gcc_qupv3_wrap2_s6_clk", 4472 .parent_hws = (const struct clk_hw*[]) { 4473 &gcc_qupv3_wrap2_s6_clk_src.clkr.hw, 4474 }, 4475 .num_parents = 1, 4476 .flags = CLK_SET_RATE_PARENT, 4477 .ops = &clk_branch2_ops, 4478 }, 4479 }, 4480 }; 4481 4482 static struct clk_branch gcc_qupv3_wrap2_s7_clk = { 4483 .halt_reg = 0x1e89c, 4484 .halt_check = BRANCH_HALT_VOTED, 4485 .clkr = { 4486 .enable_reg = 0x52010, 4487 .enable_mask = BIT(17), 4488 .hw.init = &(const struct clk_init_data) { 4489 .name = "gcc_qupv3_wrap2_s7_clk", 4490 .parent_hws = (const struct clk_hw*[]) { 4491 &gcc_qupv3_wrap2_s7_clk_src.clkr.hw, 4492 }, 4493 .num_parents = 1, 4494 .flags = CLK_SET_RATE_PARENT, 4495 .ops = &clk_branch2_ops, 4496 }, 4497 }, 4498 }; 4499 4500 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 4501 .halt_reg = 0x23000, 4502 .halt_check = BRANCH_HALT_VOTED, 4503 .hwcg_reg = 0x23000, 4504 .hwcg_bit = 1, 4505 .clkr = { 4506 .enable_reg = 0x52020, 4507 .enable_mask = BIT(6), 4508 .hw.init = &(const struct clk_init_data) { 4509 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 4510 .ops = &clk_branch2_ops, 4511 }, 4512 }, 4513 }; 4514 4515 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 4516 .halt_reg = 0x23004, 4517 .halt_check = BRANCH_HALT_VOTED, 4518 .hwcg_reg = 0x23004, 4519 .hwcg_bit = 1, 4520 .clkr = { 4521 .enable_reg = 0x52020, 4522 .enable_mask = BIT(7), 4523 .hw.init = &(const struct clk_init_data) { 4524 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 4525 .ops = &clk_branch2_ops, 4526 }, 4527 }, 4528 }; 4529 4530 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 4531 .halt_reg = 0x23150, 4532 .halt_check = BRANCH_HALT_VOTED, 4533 .hwcg_reg = 0x23150, 4534 .hwcg_bit = 1, 4535 .clkr = { 4536 .enable_reg = 0x52008, 4537 .enable_mask = BIT(20), 4538 .hw.init = &(const struct clk_init_data) { 4539 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 4540 .ops = &clk_branch2_ops, 4541 }, 4542 }, 4543 }; 4544 4545 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 4546 .halt_reg = 0x23154, 4547 .halt_check = BRANCH_HALT_VOTED, 4548 .hwcg_reg = 0x23154, 4549 .hwcg_bit = 1, 4550 .clkr = { 4551 .enable_reg = 0x52008, 4552 .enable_mask = BIT(21), 4553 .hw.init = &(const struct clk_init_data) { 4554 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 4555 .ops = &clk_branch2_ops, 4556 }, 4557 }, 4558 }; 4559 4560 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 4561 .halt_reg = 0x232a0, 4562 .halt_check = BRANCH_HALT_VOTED, 4563 .hwcg_reg = 0x232a0, 4564 .hwcg_bit = 1, 4565 .clkr = { 4566 .enable_reg = 0x52010, 4567 .enable_mask = BIT(2), 4568 .hw.init = &(const struct clk_init_data) { 4569 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 4570 .ops = &clk_branch2_ops, 4571 }, 4572 }, 4573 }; 4574 4575 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 4576 .halt_reg = 0x232a4, 4577 .halt_check = BRANCH_HALT_VOTED, 4578 .hwcg_reg = 0x232a4, 4579 .hwcg_bit = 1, 4580 .clkr = { 4581 .enable_reg = 0x52010, 4582 .enable_mask = BIT(1), 4583 .hw.init = &(const struct clk_init_data) { 4584 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 4585 .ops = &clk_branch2_ops, 4586 }, 4587 }, 4588 }; 4589 4590 static struct clk_branch gcc_sdcc2_ahb_clk = { 4591 .halt_reg = 0x14010, 4592 .halt_check = BRANCH_HALT, 4593 .clkr = { 4594 .enable_reg = 0x14010, 4595 .enable_mask = BIT(0), 4596 .hw.init = &(const struct clk_init_data) { 4597 .name = "gcc_sdcc2_ahb_clk", 4598 .ops = &clk_branch2_ops, 4599 }, 4600 }, 4601 }; 4602 4603 static struct clk_branch gcc_sdcc2_apps_clk = { 4604 .halt_reg = 0x14004, 4605 .halt_check = BRANCH_HALT, 4606 .clkr = { 4607 .enable_reg = 0x14004, 4608 .enable_mask = BIT(0), 4609 .hw.init = &(const struct clk_init_data) { 4610 .name = "gcc_sdcc2_apps_clk", 4611 .parent_hws = (const struct clk_hw*[]) { 4612 &gcc_sdcc2_apps_clk_src.clkr.hw, 4613 }, 4614 .num_parents = 1, 4615 .flags = CLK_SET_RATE_PARENT, 4616 .ops = &clk_branch2_ops, 4617 }, 4618 }, 4619 }; 4620 4621 static struct clk_branch gcc_sdcc4_ahb_clk = { 4622 .halt_reg = 0x16010, 4623 .halt_check = BRANCH_HALT, 4624 .clkr = { 4625 .enable_reg = 0x16010, 4626 .enable_mask = BIT(0), 4627 .hw.init = &(const struct clk_init_data) { 4628 .name = "gcc_sdcc4_ahb_clk", 4629 .ops = &clk_branch2_ops, 4630 }, 4631 }, 4632 }; 4633 4634 static struct clk_branch gcc_sdcc4_apps_clk = { 4635 .halt_reg = 0x16004, 4636 .halt_check = BRANCH_HALT, 4637 .clkr = { 4638 .enable_reg = 0x16004, 4639 .enable_mask = BIT(0), 4640 .hw.init = &(const struct clk_init_data) { 4641 .name = "gcc_sdcc4_apps_clk", 4642 .parent_hws = (const struct clk_hw*[]) { 4643 &gcc_sdcc4_apps_clk_src.clkr.hw, 4644 }, 4645 .num_parents = 1, 4646 .flags = CLK_SET_RATE_PARENT, 4647 .ops = &clk_branch2_ops, 4648 }, 4649 }, 4650 }; 4651 4652 static struct clk_branch gcc_sys_noc_usb_axi_clk = { 4653 .halt_reg = 0x2d014, 4654 .halt_check = BRANCH_HALT_VOTED, 4655 .hwcg_reg = 0x2d014, 4656 .hwcg_bit = 1, 4657 .clkr = { 4658 .enable_reg = 0x2d014, 4659 .enable_mask = BIT(0), 4660 .hw.init = &(const struct clk_init_data) { 4661 .name = "gcc_sys_noc_usb_axi_clk", 4662 .ops = &clk_branch2_ops, 4663 }, 4664 }, 4665 }; 4666 4667 static struct clk_branch gcc_ufs_phy_ahb_clk = { 4668 .halt_reg = 0x77024, 4669 .halt_check = BRANCH_HALT_VOTED, 4670 .hwcg_reg = 0x77024, 4671 .hwcg_bit = 1, 4672 .clkr = { 4673 .enable_reg = 0x77024, 4674 .enable_mask = BIT(0), 4675 .hw.init = &(const struct clk_init_data) { 4676 .name = "gcc_ufs_phy_ahb_clk", 4677 .ops = &clk_branch2_ops, 4678 }, 4679 }, 4680 }; 4681 4682 static struct clk_branch gcc_ufs_phy_axi_clk = { 4683 .halt_reg = 0x77018, 4684 .halt_check = BRANCH_HALT_VOTED, 4685 .hwcg_reg = 0x77018, 4686 .hwcg_bit = 1, 4687 .clkr = { 4688 .enable_reg = 0x77018, 4689 .enable_mask = BIT(0), 4690 .hw.init = &(const struct clk_init_data) { 4691 .name = "gcc_ufs_phy_axi_clk", 4692 .parent_hws = (const struct clk_hw*[]) { 4693 &gcc_ufs_phy_axi_clk_src.clkr.hw, 4694 }, 4695 .num_parents = 1, 4696 .flags = CLK_SET_RATE_PARENT, 4697 .ops = &clk_branch2_ops, 4698 }, 4699 }, 4700 }; 4701 4702 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 4703 .halt_reg = 0x77074, 4704 .halt_check = BRANCH_HALT_VOTED, 4705 .hwcg_reg = 0x77074, 4706 .hwcg_bit = 1, 4707 .clkr = { 4708 .enable_reg = 0x77074, 4709 .enable_mask = BIT(0), 4710 .hw.init = &(const struct clk_init_data) { 4711 .name = "gcc_ufs_phy_ice_core_clk", 4712 .parent_hws = (const struct clk_hw*[]) { 4713 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 4714 }, 4715 .num_parents = 1, 4716 .flags = CLK_SET_RATE_PARENT, 4717 .ops = &clk_branch2_ops, 4718 }, 4719 }, 4720 }; 4721 4722 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 4723 .halt_reg = 0x770b0, 4724 .halt_check = BRANCH_HALT_VOTED, 4725 .hwcg_reg = 0x770b0, 4726 .hwcg_bit = 1, 4727 .clkr = { 4728 .enable_reg = 0x770b0, 4729 .enable_mask = BIT(0), 4730 .hw.init = &(const struct clk_init_data) { 4731 .name = "gcc_ufs_phy_phy_aux_clk", 4732 .parent_hws = (const struct clk_hw*[]) { 4733 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 4734 }, 4735 .num_parents = 1, 4736 .flags = CLK_SET_RATE_PARENT, 4737 .ops = &clk_branch2_ops, 4738 }, 4739 }, 4740 }; 4741 4742 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 4743 .halt_reg = 0x7702c, 4744 .halt_check = BRANCH_HALT, 4745 .clkr = { 4746 .enable_reg = 0x7702c, 4747 .enable_mask = BIT(0), 4748 .hw.init = &(const struct clk_init_data) { 4749 .name = "gcc_ufs_phy_rx_symbol_0_clk", 4750 .ops = &clk_branch2_ops, 4751 }, 4752 }, 4753 }; 4754 4755 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 4756 .halt_reg = 0x770cc, 4757 .halt_check = BRANCH_HALT, 4758 .clkr = { 4759 .enable_reg = 0x770cc, 4760 .enable_mask = BIT(0), 4761 .hw.init = &(const struct clk_init_data) { 4762 .name = "gcc_ufs_phy_rx_symbol_1_clk", 4763 .ops = &clk_branch2_ops, 4764 }, 4765 }, 4766 }; 4767 4768 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 4769 .halt_reg = 0x77028, 4770 .halt_check = BRANCH_HALT, 4771 .clkr = { 4772 .enable_reg = 0x77028, 4773 .enable_mask = BIT(0), 4774 .hw.init = &(const struct clk_init_data) { 4775 .name = "gcc_ufs_phy_tx_symbol_0_clk", 4776 .ops = &clk_branch2_ops, 4777 }, 4778 }, 4779 }; 4780 4781 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 4782 .halt_reg = 0x77068, 4783 .halt_check = BRANCH_HALT_VOTED, 4784 .hwcg_reg = 0x77068, 4785 .hwcg_bit = 1, 4786 .clkr = { 4787 .enable_reg = 0x77068, 4788 .enable_mask = BIT(0), 4789 .hw.init = &(const struct clk_init_data) { 4790 .name = "gcc_ufs_phy_unipro_core_clk", 4791 .parent_hws = (const struct clk_hw*[]) { 4792 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 4793 }, 4794 .num_parents = 1, 4795 .flags = CLK_SET_RATE_PARENT, 4796 .ops = &clk_branch2_ops, 4797 }, 4798 }, 4799 }; 4800 4801 static struct clk_branch gcc_usb20_master_clk = { 4802 .halt_reg = 0x29018, 4803 .halt_check = BRANCH_HALT, 4804 .clkr = { 4805 .enable_reg = 0x29018, 4806 .enable_mask = BIT(0), 4807 .hw.init = &(const struct clk_init_data) { 4808 .name = "gcc_usb20_master_clk", 4809 .parent_hws = (const struct clk_hw*[]) { 4810 &gcc_usb20_master_clk_src.clkr.hw, 4811 }, 4812 .num_parents = 1, 4813 .flags = CLK_SET_RATE_PARENT, 4814 .ops = &clk_branch2_ops, 4815 }, 4816 }, 4817 }; 4818 4819 static struct clk_branch gcc_usb20_mock_utmi_clk = { 4820 .halt_reg = 0x29028, 4821 .halt_check = BRANCH_HALT, 4822 .clkr = { 4823 .enable_reg = 0x29028, 4824 .enable_mask = BIT(0), 4825 .hw.init = &(const struct clk_init_data) { 4826 .name = "gcc_usb20_mock_utmi_clk", 4827 .parent_hws = (const struct clk_hw*[]) { 4828 &gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw, 4829 }, 4830 .num_parents = 1, 4831 .flags = CLK_SET_RATE_PARENT, 4832 .ops = &clk_branch2_ops, 4833 }, 4834 }, 4835 }; 4836 4837 static struct clk_branch gcc_usb20_sleep_clk = { 4838 .halt_reg = 0x29024, 4839 .halt_check = BRANCH_HALT, 4840 .clkr = { 4841 .enable_reg = 0x29024, 4842 .enable_mask = BIT(0), 4843 .hw.init = &(const struct clk_init_data) { 4844 .name = "gcc_usb20_sleep_clk", 4845 .ops = &clk_branch2_ops, 4846 }, 4847 }, 4848 }; 4849 4850 static struct clk_branch gcc_usb30_mp_master_clk = { 4851 .halt_reg = 0x17018, 4852 .halt_check = BRANCH_HALT, 4853 .clkr = { 4854 .enable_reg = 0x17018, 4855 .enable_mask = BIT(0), 4856 .hw.init = &(const struct clk_init_data) { 4857 .name = "gcc_usb30_mp_master_clk", 4858 .parent_hws = (const struct clk_hw*[]) { 4859 &gcc_usb30_mp_master_clk_src.clkr.hw, 4860 }, 4861 .num_parents = 1, 4862 .flags = CLK_SET_RATE_PARENT, 4863 .ops = &clk_branch2_ops, 4864 }, 4865 }, 4866 }; 4867 4868 static struct clk_branch gcc_usb30_mp_mock_utmi_clk = { 4869 .halt_reg = 0x17028, 4870 .halt_check = BRANCH_HALT, 4871 .clkr = { 4872 .enable_reg = 0x17028, 4873 .enable_mask = BIT(0), 4874 .hw.init = &(const struct clk_init_data) { 4875 .name = "gcc_usb30_mp_mock_utmi_clk", 4876 .parent_hws = (const struct clk_hw*[]) { 4877 &gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr.hw, 4878 }, 4879 .num_parents = 1, 4880 .flags = CLK_SET_RATE_PARENT, 4881 .ops = &clk_branch2_ops, 4882 }, 4883 }, 4884 }; 4885 4886 static struct clk_branch gcc_usb30_mp_sleep_clk = { 4887 .halt_reg = 0x17024, 4888 .halt_check = BRANCH_HALT, 4889 .clkr = { 4890 .enable_reg = 0x17024, 4891 .enable_mask = BIT(0), 4892 .hw.init = &(const struct clk_init_data) { 4893 .name = "gcc_usb30_mp_sleep_clk", 4894 .ops = &clk_branch2_ops, 4895 }, 4896 }, 4897 }; 4898 4899 static struct clk_branch gcc_usb30_prim_master_clk = { 4900 .halt_reg = 0x39018, 4901 .halt_check = BRANCH_HALT, 4902 .clkr = { 4903 .enable_reg = 0x39018, 4904 .enable_mask = BIT(0), 4905 .hw.init = &(const struct clk_init_data) { 4906 .name = "gcc_usb30_prim_master_clk", 4907 .parent_hws = (const struct clk_hw*[]) { 4908 &gcc_usb30_prim_master_clk_src.clkr.hw, 4909 }, 4910 .num_parents = 1, 4911 .flags = CLK_SET_RATE_PARENT, 4912 .ops = &clk_branch2_ops, 4913 }, 4914 }, 4915 }; 4916 4917 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 4918 .halt_reg = 0x39028, 4919 .halt_check = BRANCH_HALT, 4920 .clkr = { 4921 .enable_reg = 0x39028, 4922 .enable_mask = BIT(0), 4923 .hw.init = &(const struct clk_init_data) { 4924 .name = "gcc_usb30_prim_mock_utmi_clk", 4925 .parent_hws = (const struct clk_hw*[]) { 4926 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 4927 }, 4928 .num_parents = 1, 4929 .flags = CLK_SET_RATE_PARENT, 4930 .ops = &clk_branch2_ops, 4931 }, 4932 }, 4933 }; 4934 4935 static struct clk_branch gcc_usb30_prim_sleep_clk = { 4936 .halt_reg = 0x39024, 4937 .halt_check = BRANCH_HALT, 4938 .clkr = { 4939 .enable_reg = 0x39024, 4940 .enable_mask = BIT(0), 4941 .hw.init = &(const struct clk_init_data) { 4942 .name = "gcc_usb30_prim_sleep_clk", 4943 .ops = &clk_branch2_ops, 4944 }, 4945 }, 4946 }; 4947 4948 static struct clk_branch gcc_usb30_sec_master_clk = { 4949 .halt_reg = 0xa1018, 4950 .halt_check = BRANCH_HALT, 4951 .clkr = { 4952 .enable_reg = 0xa1018, 4953 .enable_mask = BIT(0), 4954 .hw.init = &(const struct clk_init_data) { 4955 .name = "gcc_usb30_sec_master_clk", 4956 .parent_hws = (const struct clk_hw*[]) { 4957 &gcc_usb30_sec_master_clk_src.clkr.hw, 4958 }, 4959 .num_parents = 1, 4960 .flags = CLK_SET_RATE_PARENT, 4961 .ops = &clk_branch2_ops, 4962 }, 4963 }, 4964 }; 4965 4966 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { 4967 .halt_reg = 0xa1028, 4968 .halt_check = BRANCH_HALT, 4969 .clkr = { 4970 .enable_reg = 0xa1028, 4971 .enable_mask = BIT(0), 4972 .hw.init = &(const struct clk_init_data) { 4973 .name = "gcc_usb30_sec_mock_utmi_clk", 4974 .parent_hws = (const struct clk_hw*[]) { 4975 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw, 4976 }, 4977 .num_parents = 1, 4978 .flags = CLK_SET_RATE_PARENT, 4979 .ops = &clk_branch2_ops, 4980 }, 4981 }, 4982 }; 4983 4984 static struct clk_branch gcc_usb30_sec_sleep_clk = { 4985 .halt_reg = 0xa1024, 4986 .halt_check = BRANCH_HALT, 4987 .clkr = { 4988 .enable_reg = 0xa1024, 4989 .enable_mask = BIT(0), 4990 .hw.init = &(const struct clk_init_data) { 4991 .name = "gcc_usb30_sec_sleep_clk", 4992 .ops = &clk_branch2_ops, 4993 }, 4994 }, 4995 }; 4996 4997 static struct clk_branch gcc_usb30_tert_master_clk = { 4998 .halt_reg = 0xa2018, 4999 .halt_check = BRANCH_HALT, 5000 .clkr = { 5001 .enable_reg = 0xa2018, 5002 .enable_mask = BIT(0), 5003 .hw.init = &(const struct clk_init_data) { 5004 .name = "gcc_usb30_tert_master_clk", 5005 .parent_hws = (const struct clk_hw*[]) { 5006 &gcc_usb30_tert_master_clk_src.clkr.hw, 5007 }, 5008 .num_parents = 1, 5009 .flags = CLK_SET_RATE_PARENT, 5010 .ops = &clk_branch2_ops, 5011 }, 5012 }, 5013 }; 5014 5015 static struct clk_branch gcc_usb30_tert_mock_utmi_clk = { 5016 .halt_reg = 0xa2028, 5017 .halt_check = BRANCH_HALT, 5018 .clkr = { 5019 .enable_reg = 0xa2028, 5020 .enable_mask = BIT(0), 5021 .hw.init = &(const struct clk_init_data) { 5022 .name = "gcc_usb30_tert_mock_utmi_clk", 5023 .parent_hws = (const struct clk_hw*[]) { 5024 &gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr.hw, 5025 }, 5026 .num_parents = 1, 5027 .flags = CLK_SET_RATE_PARENT, 5028 .ops = &clk_branch2_ops, 5029 }, 5030 }, 5031 }; 5032 5033 static struct clk_branch gcc_usb30_tert_sleep_clk = { 5034 .halt_reg = 0xa2024, 5035 .halt_check = BRANCH_HALT, 5036 .clkr = { 5037 .enable_reg = 0xa2024, 5038 .enable_mask = BIT(0), 5039 .hw.init = &(const struct clk_init_data) { 5040 .name = "gcc_usb30_tert_sleep_clk", 5041 .ops = &clk_branch2_ops, 5042 }, 5043 }, 5044 }; 5045 5046 static struct clk_branch gcc_usb3_mp_phy_aux_clk = { 5047 .halt_reg = 0x17288, 5048 .halt_check = BRANCH_HALT, 5049 .clkr = { 5050 .enable_reg = 0x17288, 5051 .enable_mask = BIT(0), 5052 .hw.init = &(const struct clk_init_data) { 5053 .name = "gcc_usb3_mp_phy_aux_clk", 5054 .parent_hws = (const struct clk_hw*[]) { 5055 &gcc_usb3_mp_phy_aux_clk_src.clkr.hw, 5056 }, 5057 .num_parents = 1, 5058 .flags = CLK_SET_RATE_PARENT, 5059 .ops = &clk_branch2_ops, 5060 }, 5061 }, 5062 }; 5063 5064 static struct clk_branch gcc_usb3_mp_phy_com_aux_clk = { 5065 .halt_reg = 0x1728c, 5066 .halt_check = BRANCH_HALT, 5067 .clkr = { 5068 .enable_reg = 0x1728c, 5069 .enable_mask = BIT(0), 5070 .hw.init = &(const struct clk_init_data) { 5071 .name = "gcc_usb3_mp_phy_com_aux_clk", 5072 .parent_hws = (const struct clk_hw*[]) { 5073 &gcc_usb3_mp_phy_aux_clk_src.clkr.hw, 5074 }, 5075 .num_parents = 1, 5076 .flags = CLK_SET_RATE_PARENT, 5077 .ops = &clk_branch2_ops, 5078 }, 5079 }, 5080 }; 5081 5082 static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = { 5083 .halt_reg = 0x17290, 5084 .halt_check = BRANCH_HALT_SKIP, 5085 .clkr = { 5086 .enable_reg = 0x17290, 5087 .enable_mask = BIT(0), 5088 .hw.init = &(const struct clk_init_data) { 5089 .name = "gcc_usb3_mp_phy_pipe_0_clk", 5090 .ops = &clk_branch2_ops, 5091 }, 5092 }, 5093 }; 5094 5095 static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = { 5096 .halt_reg = 0x17298, 5097 .halt_check = BRANCH_HALT_SKIP, 5098 .clkr = { 5099 .enable_reg = 0x17298, 5100 .enable_mask = BIT(0), 5101 .hw.init = &(const struct clk_init_data) { 5102 .name = "gcc_usb3_mp_phy_pipe_1_clk", 5103 .ops = &clk_branch2_ops, 5104 }, 5105 }, 5106 }; 5107 5108 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 5109 .halt_reg = 0x39060, 5110 .halt_check = BRANCH_HALT, 5111 .clkr = { 5112 .enable_reg = 0x39060, 5113 .enable_mask = BIT(0), 5114 .hw.init = &(const struct clk_init_data) { 5115 .name = "gcc_usb3_prim_phy_aux_clk", 5116 .parent_hws = (const struct clk_hw*[]) { 5117 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 5118 }, 5119 .num_parents = 1, 5120 .flags = CLK_SET_RATE_PARENT, 5121 .ops = &clk_branch2_ops, 5122 }, 5123 }, 5124 }; 5125 5126 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 5127 .halt_reg = 0x39064, 5128 .halt_check = BRANCH_HALT, 5129 .clkr = { 5130 .enable_reg = 0x39064, 5131 .enable_mask = BIT(0), 5132 .hw.init = &(const struct clk_init_data) { 5133 .name = "gcc_usb3_prim_phy_com_aux_clk", 5134 .parent_hws = (const struct clk_hw*[]) { 5135 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 5136 }, 5137 .num_parents = 1, 5138 .flags = CLK_SET_RATE_PARENT, 5139 .ops = &clk_branch2_ops, 5140 }, 5141 }, 5142 }; 5143 5144 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 5145 .reg = 0x3906c, 5146 .shift = 0, 5147 .width = 2, 5148 .parent_map = gcc_parent_map_10, 5149 .clkr = { 5150 .hw.init = &(struct clk_init_data){ 5151 .name = "gcc_usb3_prim_phy_pipe_clk_src", 5152 .parent_data = gcc_parent_data_10, 5153 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 5154 .ops = &clk_regmap_mux_closest_ops, 5155 }, 5156 }, 5157 }; 5158 5159 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 5160 .halt_reg = 0x39068, 5161 .halt_check = BRANCH_HALT_SKIP, 5162 .hwcg_reg = 0x39068, 5163 .hwcg_bit = 1, 5164 .clkr = { 5165 .enable_reg = 0x39068, 5166 .enable_mask = BIT(0), 5167 .hw.init = &(const struct clk_init_data) { 5168 .name = "gcc_usb3_prim_phy_pipe_clk", 5169 .parent_hws = (const struct clk_hw*[]) { 5170 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 5171 }, 5172 .num_parents = 1, 5173 .flags = CLK_SET_RATE_PARENT, 5174 .ops = &clk_branch2_ops, 5175 }, 5176 }, 5177 }; 5178 5179 static struct clk_branch gcc_usb3_sec_phy_aux_clk = { 5180 .halt_reg = 0xa1060, 5181 .halt_check = BRANCH_HALT, 5182 .clkr = { 5183 .enable_reg = 0xa1060, 5184 .enable_mask = BIT(0), 5185 .hw.init = &(const struct clk_init_data) { 5186 .name = "gcc_usb3_sec_phy_aux_clk", 5187 .parent_hws = (const struct clk_hw*[]) { 5188 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 5189 }, 5190 .num_parents = 1, 5191 .flags = CLK_SET_RATE_PARENT, 5192 .ops = &clk_branch2_ops, 5193 }, 5194 }, 5195 }; 5196 5197 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { 5198 .halt_reg = 0xa1064, 5199 .halt_check = BRANCH_HALT, 5200 .clkr = { 5201 .enable_reg = 0xa1064, 5202 .enable_mask = BIT(0), 5203 .hw.init = &(const struct clk_init_data) { 5204 .name = "gcc_usb3_sec_phy_com_aux_clk", 5205 .parent_hws = (const struct clk_hw*[]) { 5206 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 5207 }, 5208 .num_parents = 1, 5209 .flags = CLK_SET_RATE_PARENT, 5210 .ops = &clk_branch2_ops, 5211 }, 5212 }, 5213 }; 5214 5215 static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = { 5216 .reg = 0xa106c, 5217 .shift = 0, 5218 .width = 2, 5219 .parent_map = gcc_parent_map_11, 5220 .clkr = { 5221 .hw.init = &(struct clk_init_data){ 5222 .name = "gcc_usb3_sec_phy_pipe_clk_src", 5223 .parent_data = gcc_parent_data_11, 5224 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 5225 .ops = &clk_regmap_mux_closest_ops, 5226 }, 5227 }, 5228 }; 5229 5230 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { 5231 .halt_reg = 0xa1068, 5232 .halt_check = BRANCH_HALT_SKIP, 5233 .hwcg_reg = 0xa1068, 5234 .hwcg_bit = 1, 5235 .clkr = { 5236 .enable_reg = 0xa1068, 5237 .enable_mask = BIT(0), 5238 .hw.init = &(const struct clk_init_data) { 5239 .name = "gcc_usb3_sec_phy_pipe_clk", 5240 .parent_hws = (const struct clk_hw*[]) { 5241 &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw, 5242 }, 5243 .num_parents = 1, 5244 .flags = CLK_SET_RATE_PARENT, 5245 .ops = &clk_branch2_ops, 5246 }, 5247 }, 5248 }; 5249 5250 static struct clk_branch gcc_usb3_tert_phy_aux_clk = { 5251 .halt_reg = 0xa2060, 5252 .halt_check = BRANCH_HALT, 5253 .clkr = { 5254 .enable_reg = 0xa2060, 5255 .enable_mask = BIT(0), 5256 .hw.init = &(const struct clk_init_data) { 5257 .name = "gcc_usb3_tert_phy_aux_clk", 5258 .parent_hws = (const struct clk_hw*[]) { 5259 &gcc_usb3_tert_phy_aux_clk_src.clkr.hw, 5260 }, 5261 .num_parents = 1, 5262 .flags = CLK_SET_RATE_PARENT, 5263 .ops = &clk_branch2_ops, 5264 }, 5265 }, 5266 }; 5267 5268 static struct clk_branch gcc_usb3_tert_phy_com_aux_clk = { 5269 .halt_reg = 0xa2064, 5270 .halt_check = BRANCH_HALT, 5271 .clkr = { 5272 .enable_reg = 0xa2064, 5273 .enable_mask = BIT(0), 5274 .hw.init = &(const struct clk_init_data) { 5275 .name = "gcc_usb3_tert_phy_com_aux_clk", 5276 .parent_hws = (const struct clk_hw*[]) { 5277 &gcc_usb3_tert_phy_aux_clk_src.clkr.hw, 5278 }, 5279 .num_parents = 1, 5280 .flags = CLK_SET_RATE_PARENT, 5281 .ops = &clk_branch2_ops, 5282 }, 5283 }, 5284 }; 5285 5286 static struct clk_regmap_mux gcc_usb3_tert_phy_pipe_clk_src = { 5287 .reg = 0xa206c, 5288 .shift = 0, 5289 .width = 2, 5290 .parent_map = gcc_parent_map_12, 5291 .clkr = { 5292 .hw.init = &(struct clk_init_data){ 5293 .name = "gcc_usb3_tert_phy_pipe_clk_src", 5294 .parent_data = gcc_parent_data_12, 5295 .num_parents = ARRAY_SIZE(gcc_parent_data_12), 5296 .ops = &clk_regmap_mux_closest_ops, 5297 }, 5298 }, 5299 }; 5300 5301 static struct clk_branch gcc_usb3_tert_phy_pipe_clk = { 5302 .halt_reg = 0xa2068, 5303 .halt_check = BRANCH_HALT_SKIP, 5304 .hwcg_reg = 0xa2068, 5305 .hwcg_bit = 1, 5306 .clkr = { 5307 .enable_reg = 0xa2068, 5308 .enable_mask = BIT(0), 5309 .hw.init = &(const struct clk_init_data) { 5310 .name = "gcc_usb3_tert_phy_pipe_clk", 5311 .parent_hws = (const struct clk_hw*[]) { 5312 &gcc_usb3_tert_phy_pipe_clk_src.clkr.hw, 5313 }, 5314 .num_parents = 1, 5315 .flags = CLK_SET_RATE_PARENT, 5316 .ops = &clk_branch2_ops, 5317 }, 5318 }, 5319 }; 5320 5321 static struct clk_branch gcc_usb4_0_cfg_ahb_clk = { 5322 .halt_reg = 0x9f0a8, 5323 .halt_check = BRANCH_HALT_VOTED, 5324 .hwcg_reg = 0x9f0a8, 5325 .hwcg_bit = 1, 5326 .clkr = { 5327 .enable_reg = 0x9f0a8, 5328 .enable_mask = BIT(0), 5329 .hw.init = &(const struct clk_init_data) { 5330 .name = "gcc_usb4_0_cfg_ahb_clk", 5331 .ops = &clk_branch2_ops, 5332 }, 5333 }, 5334 }; 5335 5336 static struct clk_branch gcc_usb4_0_dp0_clk = { 5337 .halt_reg = 0x9f060, 5338 .halt_check = BRANCH_HALT, 5339 .clkr = { 5340 .enable_reg = 0x9f060, 5341 .enable_mask = BIT(0), 5342 .hw.init = &(const struct clk_init_data) { 5343 .name = "gcc_usb4_0_dp0_clk", 5344 .ops = &clk_branch2_ops, 5345 }, 5346 }, 5347 }; 5348 5349 static struct clk_branch gcc_usb4_0_dp1_clk = { 5350 .halt_reg = 0x9f108, 5351 .halt_check = BRANCH_HALT, 5352 .clkr = { 5353 .enable_reg = 0x9f108, 5354 .enable_mask = BIT(0), 5355 .hw.init = &(const struct clk_init_data) { 5356 .name = "gcc_usb4_0_dp1_clk", 5357 .ops = &clk_branch2_ops, 5358 }, 5359 }, 5360 }; 5361 5362 static struct clk_branch gcc_usb4_0_master_clk = { 5363 .halt_reg = 0x9f018, 5364 .halt_check = BRANCH_HALT, 5365 .clkr = { 5366 .enable_reg = 0x9f018, 5367 .enable_mask = BIT(0), 5368 .hw.init = &(const struct clk_init_data) { 5369 .name = "gcc_usb4_0_master_clk", 5370 .parent_hws = (const struct clk_hw*[]) { 5371 &gcc_usb4_0_master_clk_src.clkr.hw, 5372 }, 5373 .num_parents = 1, 5374 .flags = CLK_SET_RATE_PARENT, 5375 .ops = &clk_branch2_ops, 5376 }, 5377 }, 5378 }; 5379 5380 static struct clk_branch gcc_usb4_0_phy_p2rr2p_pipe_clk = { 5381 .halt_reg = 0x9f0d8, 5382 .halt_check = BRANCH_HALT_SKIP, 5383 .clkr = { 5384 .enable_reg = 0x9f0d8, 5385 .enable_mask = BIT(0), 5386 .hw.init = &(const struct clk_init_data) { 5387 .name = "gcc_usb4_0_phy_p2rr2p_pipe_clk", 5388 .ops = &clk_branch2_ops, 5389 }, 5390 }, 5391 }; 5392 5393 static struct clk_branch gcc_usb4_0_phy_pcie_pipe_clk = { 5394 .halt_reg = 0x9f048, 5395 .halt_check = BRANCH_HALT_SKIP, 5396 .clkr = { 5397 .enable_reg = 0x52010, 5398 .enable_mask = BIT(19), 5399 .hw.init = &(const struct clk_init_data) { 5400 .name = "gcc_usb4_0_phy_pcie_pipe_clk", 5401 .ops = &clk_branch2_ops, 5402 }, 5403 }, 5404 }; 5405 5406 static struct clk_branch gcc_usb4_0_phy_rx0_clk = { 5407 .halt_reg = 0x9f0b0, 5408 .halt_check = BRANCH_HALT, 5409 .clkr = { 5410 .enable_reg = 0x9f0b0, 5411 .enable_mask = BIT(0), 5412 .hw.init = &(const struct clk_init_data) { 5413 .name = "gcc_usb4_0_phy_rx0_clk", 5414 .ops = &clk_branch2_ops, 5415 }, 5416 }, 5417 }; 5418 5419 static struct clk_branch gcc_usb4_0_phy_rx1_clk = { 5420 .halt_reg = 0x9f0c0, 5421 .halt_check = BRANCH_HALT, 5422 .clkr = { 5423 .enable_reg = 0x9f0c0, 5424 .enable_mask = BIT(0), 5425 .hw.init = &(const struct clk_init_data) { 5426 .name = "gcc_usb4_0_phy_rx1_clk", 5427 .ops = &clk_branch2_ops, 5428 }, 5429 }, 5430 }; 5431 5432 static struct clk_branch gcc_usb4_0_phy_usb_pipe_clk = { 5433 .halt_reg = 0x9f0a4, 5434 .halt_check = BRANCH_HALT_SKIP, 5435 .hwcg_reg = 0x9f0a4, 5436 .hwcg_bit = 1, 5437 .clkr = { 5438 .enable_reg = 0x9f0a4, 5439 .enable_mask = BIT(0), 5440 .hw.init = &(const struct clk_init_data) { 5441 .name = "gcc_usb4_0_phy_usb_pipe_clk", 5442 .ops = &clk_branch2_ops, 5443 }, 5444 }, 5445 }; 5446 5447 static struct clk_branch gcc_usb4_0_sb_if_clk = { 5448 .halt_reg = 0x9f044, 5449 .halt_check = BRANCH_HALT, 5450 .clkr = { 5451 .enable_reg = 0x9f044, 5452 .enable_mask = BIT(0), 5453 .hw.init = &(const struct clk_init_data) { 5454 .name = "gcc_usb4_0_sb_if_clk", 5455 .parent_hws = (const struct clk_hw*[]) { 5456 &gcc_usb4_0_sb_if_clk_src.clkr.hw, 5457 }, 5458 .num_parents = 1, 5459 .flags = CLK_SET_RATE_PARENT, 5460 .ops = &clk_branch2_ops, 5461 }, 5462 }, 5463 }; 5464 5465 static struct clk_branch gcc_usb4_0_sys_clk = { 5466 .halt_reg = 0x9f054, 5467 .halt_check = BRANCH_HALT, 5468 .clkr = { 5469 .enable_reg = 0x9f054, 5470 .enable_mask = BIT(0), 5471 .hw.init = &(const struct clk_init_data) { 5472 .name = "gcc_usb4_0_sys_clk", 5473 .ops = &clk_branch2_ops, 5474 }, 5475 }, 5476 }; 5477 5478 static struct clk_branch gcc_usb4_0_tmu_clk = { 5479 .halt_reg = 0x9f088, 5480 .halt_check = BRANCH_HALT_VOTED, 5481 .hwcg_reg = 0x9f088, 5482 .hwcg_bit = 1, 5483 .clkr = { 5484 .enable_reg = 0x9f088, 5485 .enable_mask = BIT(0), 5486 .hw.init = &(const struct clk_init_data) { 5487 .name = "gcc_usb4_0_tmu_clk", 5488 .parent_hws = (const struct clk_hw*[]) { 5489 &gcc_usb4_0_tmu_clk_src.clkr.hw, 5490 }, 5491 .num_parents = 1, 5492 .flags = CLK_SET_RATE_PARENT, 5493 .ops = &clk_branch2_ops, 5494 }, 5495 }, 5496 }; 5497 5498 static struct clk_branch gcc_usb4_1_cfg_ahb_clk = { 5499 .halt_reg = 0x2b0a8, 5500 .halt_check = BRANCH_HALT_VOTED, 5501 .hwcg_reg = 0x2b0a8, 5502 .hwcg_bit = 1, 5503 .clkr = { 5504 .enable_reg = 0x2b0a8, 5505 .enable_mask = BIT(0), 5506 .hw.init = &(const struct clk_init_data) { 5507 .name = "gcc_usb4_1_cfg_ahb_clk", 5508 .ops = &clk_branch2_ops, 5509 }, 5510 }, 5511 }; 5512 5513 static struct clk_branch gcc_usb4_1_dp0_clk = { 5514 .halt_reg = 0x2b060, 5515 .halt_check = BRANCH_HALT, 5516 .clkr = { 5517 .enable_reg = 0x2b060, 5518 .enable_mask = BIT(0), 5519 .hw.init = &(const struct clk_init_data) { 5520 .name = "gcc_usb4_1_dp0_clk", 5521 .ops = &clk_branch2_ops, 5522 }, 5523 }, 5524 }; 5525 5526 static struct clk_branch gcc_usb4_1_dp1_clk = { 5527 .halt_reg = 0x2b108, 5528 .halt_check = BRANCH_HALT, 5529 .clkr = { 5530 .enable_reg = 0x2b108, 5531 .enable_mask = BIT(0), 5532 .hw.init = &(const struct clk_init_data) { 5533 .name = "gcc_usb4_1_dp1_clk", 5534 .ops = &clk_branch2_ops, 5535 }, 5536 }, 5537 }; 5538 5539 static struct clk_branch gcc_usb4_1_master_clk = { 5540 .halt_reg = 0x2b018, 5541 .halt_check = BRANCH_HALT, 5542 .clkr = { 5543 .enable_reg = 0x2b018, 5544 .enable_mask = BIT(0), 5545 .hw.init = &(const struct clk_init_data) { 5546 .name = "gcc_usb4_1_master_clk", 5547 .parent_hws = (const struct clk_hw*[]) { 5548 &gcc_usb4_1_master_clk_src.clkr.hw, 5549 }, 5550 .num_parents = 1, 5551 .flags = CLK_SET_RATE_PARENT, 5552 .ops = &clk_branch2_ops, 5553 }, 5554 }, 5555 }; 5556 5557 static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = { 5558 .halt_reg = 0x2b0d8, 5559 .halt_check = BRANCH_HALT_SKIP, 5560 .clkr = { 5561 .enable_reg = 0x2b0d8, 5562 .enable_mask = BIT(0), 5563 .hw.init = &(const struct clk_init_data) { 5564 .name = "gcc_usb4_1_phy_p2rr2p_pipe_clk", 5565 .ops = &clk_branch2_ops, 5566 }, 5567 }, 5568 }; 5569 5570 static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk = { 5571 .halt_reg = 0x2b048, 5572 .halt_check = BRANCH_HALT_SKIP, 5573 .clkr = { 5574 .enable_reg = 0x52028, 5575 .enable_mask = BIT(0), 5576 .hw.init = &(const struct clk_init_data) { 5577 .name = "gcc_usb4_1_phy_pcie_pipe_clk", 5578 .ops = &clk_branch2_ops, 5579 }, 5580 }, 5581 }; 5582 5583 static struct clk_branch gcc_usb4_1_phy_rx0_clk = { 5584 .halt_reg = 0x2b0b0, 5585 .halt_check = BRANCH_HALT, 5586 .clkr = { 5587 .enable_reg = 0x2b0b0, 5588 .enable_mask = BIT(0), 5589 .hw.init = &(const struct clk_init_data) { 5590 .name = "gcc_usb4_1_phy_rx0_clk", 5591 .ops = &clk_branch2_ops, 5592 }, 5593 }, 5594 }; 5595 5596 static struct clk_branch gcc_usb4_1_phy_rx1_clk = { 5597 .halt_reg = 0x2b0c0, 5598 .halt_check = BRANCH_HALT, 5599 .clkr = { 5600 .enable_reg = 0x2b0c0, 5601 .enable_mask = BIT(0), 5602 .hw.init = &(const struct clk_init_data) { 5603 .name = "gcc_usb4_1_phy_rx1_clk", 5604 .ops = &clk_branch2_ops, 5605 }, 5606 }, 5607 }; 5608 5609 static struct clk_branch gcc_usb4_1_phy_usb_pipe_clk = { 5610 .halt_reg = 0x2b0a4, 5611 .halt_check = BRANCH_HALT_SKIP, 5612 .hwcg_reg = 0x2b0a4, 5613 .hwcg_bit = 1, 5614 .clkr = { 5615 .enable_reg = 0x2b0a4, 5616 .enable_mask = BIT(0), 5617 .hw.init = &(const struct clk_init_data) { 5618 .name = "gcc_usb4_1_phy_usb_pipe_clk", 5619 .ops = &clk_branch2_ops, 5620 }, 5621 }, 5622 }; 5623 5624 static struct clk_branch gcc_usb4_1_sb_if_clk = { 5625 .halt_reg = 0x2b044, 5626 .halt_check = BRANCH_HALT, 5627 .clkr = { 5628 .enable_reg = 0x2b044, 5629 .enable_mask = BIT(0), 5630 .hw.init = &(const struct clk_init_data) { 5631 .name = "gcc_usb4_1_sb_if_clk", 5632 .parent_hws = (const struct clk_hw*[]) { 5633 &gcc_usb4_1_sb_if_clk_src.clkr.hw, 5634 }, 5635 .num_parents = 1, 5636 .flags = CLK_SET_RATE_PARENT, 5637 .ops = &clk_branch2_ops, 5638 }, 5639 }, 5640 }; 5641 5642 static struct clk_branch gcc_usb4_1_sys_clk = { 5643 .halt_reg = 0x2b054, 5644 .halt_check = BRANCH_HALT, 5645 .clkr = { 5646 .enable_reg = 0x2b054, 5647 .enable_mask = BIT(0), 5648 .hw.init = &(const struct clk_init_data) { 5649 .name = "gcc_usb4_1_sys_clk", 5650 .ops = &clk_branch2_ops, 5651 }, 5652 }, 5653 }; 5654 5655 static struct clk_branch gcc_usb4_1_tmu_clk = { 5656 .halt_reg = 0x2b088, 5657 .halt_check = BRANCH_HALT_VOTED, 5658 .hwcg_reg = 0x2b088, 5659 .hwcg_bit = 1, 5660 .clkr = { 5661 .enable_reg = 0x2b088, 5662 .enable_mask = BIT(0), 5663 .hw.init = &(const struct clk_init_data) { 5664 .name = "gcc_usb4_1_tmu_clk", 5665 .parent_hws = (const struct clk_hw*[]) { 5666 &gcc_usb4_1_tmu_clk_src.clkr.hw, 5667 }, 5668 .num_parents = 1, 5669 .flags = CLK_SET_RATE_PARENT, 5670 .ops = &clk_branch2_ops, 5671 }, 5672 }, 5673 }; 5674 5675 static struct clk_branch gcc_usb4_2_cfg_ahb_clk = { 5676 .halt_reg = 0x110a8, 5677 .halt_check = BRANCH_HALT_VOTED, 5678 .hwcg_reg = 0x110a8, 5679 .hwcg_bit = 1, 5680 .clkr = { 5681 .enable_reg = 0x110a8, 5682 .enable_mask = BIT(0), 5683 .hw.init = &(const struct clk_init_data) { 5684 .name = "gcc_usb4_2_cfg_ahb_clk", 5685 .ops = &clk_branch2_ops, 5686 }, 5687 }, 5688 }; 5689 5690 static struct clk_branch gcc_usb4_2_dp0_clk = { 5691 .halt_reg = 0x11060, 5692 .halt_check = BRANCH_HALT, 5693 .clkr = { 5694 .enable_reg = 0x11060, 5695 .enable_mask = BIT(0), 5696 .hw.init = &(const struct clk_init_data) { 5697 .name = "gcc_usb4_2_dp0_clk", 5698 .ops = &clk_branch2_ops, 5699 }, 5700 }, 5701 }; 5702 5703 static struct clk_branch gcc_usb4_2_dp1_clk = { 5704 .halt_reg = 0x11108, 5705 .halt_check = BRANCH_HALT, 5706 .clkr = { 5707 .enable_reg = 0x11108, 5708 .enable_mask = BIT(0), 5709 .hw.init = &(const struct clk_init_data) { 5710 .name = "gcc_usb4_2_dp1_clk", 5711 .ops = &clk_branch2_ops, 5712 }, 5713 }, 5714 }; 5715 5716 static struct clk_branch gcc_usb4_2_master_clk = { 5717 .halt_reg = 0x11018, 5718 .halt_check = BRANCH_HALT, 5719 .clkr = { 5720 .enable_reg = 0x11018, 5721 .enable_mask = BIT(0), 5722 .hw.init = &(const struct clk_init_data) { 5723 .name = "gcc_usb4_2_master_clk", 5724 .parent_hws = (const struct clk_hw*[]) { 5725 &gcc_usb4_2_master_clk_src.clkr.hw, 5726 }, 5727 .num_parents = 1, 5728 .flags = CLK_SET_RATE_PARENT, 5729 .ops = &clk_branch2_ops, 5730 }, 5731 }, 5732 }; 5733 5734 static struct clk_branch gcc_usb4_2_phy_p2rr2p_pipe_clk = { 5735 .halt_reg = 0x110d8, 5736 .halt_check = BRANCH_HALT_SKIP, 5737 .clkr = { 5738 .enable_reg = 0x110d8, 5739 .enable_mask = BIT(0), 5740 .hw.init = &(const struct clk_init_data) { 5741 .name = "gcc_usb4_2_phy_p2rr2p_pipe_clk", 5742 .ops = &clk_branch2_ops, 5743 }, 5744 }, 5745 }; 5746 5747 static struct clk_branch gcc_usb4_2_phy_pcie_pipe_clk = { 5748 .halt_reg = 0x11048, 5749 .halt_check = BRANCH_HALT_SKIP, 5750 .clkr = { 5751 .enable_reg = 0x52028, 5752 .enable_mask = BIT(1), 5753 .hw.init = &(const struct clk_init_data) { 5754 .name = "gcc_usb4_2_phy_pcie_pipe_clk", 5755 .ops = &clk_branch2_ops, 5756 }, 5757 }, 5758 }; 5759 5760 static struct clk_branch gcc_usb4_2_phy_rx0_clk = { 5761 .halt_reg = 0x110b0, 5762 .halt_check = BRANCH_HALT, 5763 .clkr = { 5764 .enable_reg = 0x110b0, 5765 .enable_mask = BIT(0), 5766 .hw.init = &(const struct clk_init_data) { 5767 .name = "gcc_usb4_2_phy_rx0_clk", 5768 .ops = &clk_branch2_ops, 5769 }, 5770 }, 5771 }; 5772 5773 static struct clk_branch gcc_usb4_2_phy_rx1_clk = { 5774 .halt_reg = 0x110c0, 5775 .halt_check = BRANCH_HALT, 5776 .clkr = { 5777 .enable_reg = 0x110c0, 5778 .enable_mask = BIT(0), 5779 .hw.init = &(const struct clk_init_data) { 5780 .name = "gcc_usb4_2_phy_rx1_clk", 5781 .ops = &clk_branch2_ops, 5782 }, 5783 }, 5784 }; 5785 5786 static struct clk_branch gcc_usb4_2_phy_usb_pipe_clk = { 5787 .halt_reg = 0x110a4, 5788 .halt_check = BRANCH_HALT_SKIP, 5789 .hwcg_reg = 0x110a4, 5790 .hwcg_bit = 1, 5791 .clkr = { 5792 .enable_reg = 0x110a4, 5793 .enable_mask = BIT(0), 5794 .hw.init = &(const struct clk_init_data) { 5795 .name = "gcc_usb4_2_phy_usb_pipe_clk", 5796 .ops = &clk_branch2_ops, 5797 }, 5798 }, 5799 }; 5800 5801 static struct clk_branch gcc_usb4_2_sb_if_clk = { 5802 .halt_reg = 0x11044, 5803 .halt_check = BRANCH_HALT, 5804 .clkr = { 5805 .enable_reg = 0x11044, 5806 .enable_mask = BIT(0), 5807 .hw.init = &(const struct clk_init_data) { 5808 .name = "gcc_usb4_2_sb_if_clk", 5809 .parent_hws = (const struct clk_hw*[]) { 5810 &gcc_usb4_2_sb_if_clk_src.clkr.hw, 5811 }, 5812 .num_parents = 1, 5813 .flags = CLK_SET_RATE_PARENT, 5814 .ops = &clk_branch2_ops, 5815 }, 5816 }, 5817 }; 5818 5819 static struct clk_branch gcc_usb4_2_sys_clk = { 5820 .halt_reg = 0x11054, 5821 .halt_check = BRANCH_HALT, 5822 .clkr = { 5823 .enable_reg = 0x11054, 5824 .enable_mask = BIT(0), 5825 .hw.init = &(const struct clk_init_data) { 5826 .name = "gcc_usb4_2_sys_clk", 5827 .ops = &clk_branch2_ops, 5828 }, 5829 }, 5830 }; 5831 5832 static struct clk_branch gcc_usb4_2_tmu_clk = { 5833 .halt_reg = 0x11088, 5834 .halt_check = BRANCH_HALT_VOTED, 5835 .hwcg_reg = 0x11088, 5836 .hwcg_bit = 1, 5837 .clkr = { 5838 .enable_reg = 0x11088, 5839 .enable_mask = BIT(0), 5840 .hw.init = &(const struct clk_init_data) { 5841 .name = "gcc_usb4_2_tmu_clk", 5842 .parent_hws = (const struct clk_hw*[]) { 5843 &gcc_usb4_2_tmu_clk_src.clkr.hw, 5844 }, 5845 .num_parents = 1, 5846 .flags = CLK_SET_RATE_PARENT, 5847 .ops = &clk_branch2_ops, 5848 }, 5849 }, 5850 }; 5851 5852 static struct clk_branch gcc_video_axi0_clk = { 5853 .halt_reg = 0x32018, 5854 .halt_check = BRANCH_HALT_SKIP, 5855 .hwcg_reg = 0x32018, 5856 .hwcg_bit = 1, 5857 .clkr = { 5858 .enable_reg = 0x32018, 5859 .enable_mask = BIT(0), 5860 .hw.init = &(const struct clk_init_data) { 5861 .name = "gcc_video_axi0_clk", 5862 .ops = &clk_branch2_ops, 5863 }, 5864 }, 5865 }; 5866 5867 static struct clk_branch gcc_video_axi1_clk = { 5868 .halt_reg = 0x32024, 5869 .halt_check = BRANCH_HALT_SKIP, 5870 .hwcg_reg = 0x32024, 5871 .hwcg_bit = 1, 5872 .clkr = { 5873 .enable_reg = 0x32024, 5874 .enable_mask = BIT(0), 5875 .hw.init = &(const struct clk_init_data) { 5876 .name = "gcc_video_axi1_clk", 5877 .ops = &clk_branch2_ops, 5878 }, 5879 }, 5880 }; 5881 5882 static struct gdsc gcc_pcie_0_tunnel_gdsc = { 5883 .gdscr = 0xa0004, 5884 .en_rest_wait_val = 0x2, 5885 .en_few_wait_val = 0x2, 5886 .clk_dis_wait_val = 0xf, 5887 .pd = { 5888 .name = "gcc_pcie_0_tunnel_gdsc", 5889 }, 5890 .pwrsts = PWRSTS_OFF_ON, 5891 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 5892 }; 5893 5894 static struct gdsc gcc_pcie_1_tunnel_gdsc = { 5895 .gdscr = 0x2c004, 5896 .en_rest_wait_val = 0x2, 5897 .en_few_wait_val = 0x2, 5898 .clk_dis_wait_val = 0xf, 5899 .pd = { 5900 .name = "gcc_pcie_1_tunnel_gdsc", 5901 }, 5902 .pwrsts = PWRSTS_OFF_ON, 5903 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 5904 }; 5905 5906 static struct gdsc gcc_pcie_2_tunnel_gdsc = { 5907 .gdscr = 0x13004, 5908 .en_rest_wait_val = 0x2, 5909 .en_few_wait_val = 0x2, 5910 .clk_dis_wait_val = 0xf, 5911 .pd = { 5912 .name = "gcc_pcie_2_tunnel_gdsc", 5913 }, 5914 .pwrsts = PWRSTS_OFF_ON, 5915 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 5916 }; 5917 5918 static struct gdsc gcc_pcie_3_gdsc = { 5919 .gdscr = 0x58004, 5920 .en_rest_wait_val = 0x2, 5921 .en_few_wait_val = 0x2, 5922 .clk_dis_wait_val = 0xf, 5923 .pd = { 5924 .name = "gcc_pcie_3_gdsc", 5925 }, 5926 .pwrsts = PWRSTS_OFF_ON, 5927 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 5928 }; 5929 5930 static struct gdsc gcc_pcie_3_phy_gdsc = { 5931 .gdscr = 0x3e000, 5932 .en_rest_wait_val = 0x2, 5933 .en_few_wait_val = 0x2, 5934 .clk_dis_wait_val = 0x2, 5935 .pd = { 5936 .name = "gcc_pcie_3_phy_gdsc", 5937 }, 5938 .pwrsts = PWRSTS_OFF_ON, 5939 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 5940 }; 5941 5942 static struct gdsc gcc_pcie_4_gdsc = { 5943 .gdscr = 0x6b004, 5944 .en_rest_wait_val = 0x2, 5945 .en_few_wait_val = 0x2, 5946 .clk_dis_wait_val = 0xf, 5947 .pd = { 5948 .name = "gcc_pcie_4_gdsc", 5949 }, 5950 .pwrsts = PWRSTS_OFF_ON, 5951 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 5952 }; 5953 5954 static struct gdsc gcc_pcie_4_phy_gdsc = { 5955 .gdscr = 0x6c000, 5956 .en_rest_wait_val = 0x2, 5957 .en_few_wait_val = 0x2, 5958 .clk_dis_wait_val = 0x2, 5959 .pd = { 5960 .name = "gcc_pcie_4_phy_gdsc", 5961 }, 5962 .pwrsts = PWRSTS_OFF_ON, 5963 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 5964 }; 5965 5966 static struct gdsc gcc_pcie_5_gdsc = { 5967 .gdscr = 0x2f004, 5968 .en_rest_wait_val = 0x2, 5969 .en_few_wait_val = 0x2, 5970 .clk_dis_wait_val = 0xf, 5971 .pd = { 5972 .name = "gcc_pcie_5_gdsc", 5973 }, 5974 .pwrsts = PWRSTS_OFF_ON, 5975 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 5976 }; 5977 5978 static struct gdsc gcc_pcie_5_phy_gdsc = { 5979 .gdscr = 0x30000, 5980 .en_rest_wait_val = 0x2, 5981 .en_few_wait_val = 0x2, 5982 .clk_dis_wait_val = 0x2, 5983 .pd = { 5984 .name = "gcc_pcie_5_phy_gdsc", 5985 }, 5986 .pwrsts = PWRSTS_OFF_ON, 5987 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 5988 }; 5989 5990 static struct gdsc gcc_pcie_6_phy_gdsc = { 5991 .gdscr = 0x8e000, 5992 .en_rest_wait_val = 0x2, 5993 .en_few_wait_val = 0x2, 5994 .clk_dis_wait_val = 0x2, 5995 .pd = { 5996 .name = "gcc_pcie_6_phy_gdsc", 5997 }, 5998 .pwrsts = PWRSTS_OFF_ON, 5999 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 6000 }; 6001 6002 static struct gdsc gcc_pcie_6a_gdsc = { 6003 .gdscr = 0x31004, 6004 .en_rest_wait_val = 0x2, 6005 .en_few_wait_val = 0x2, 6006 .clk_dis_wait_val = 0xf, 6007 .pd = { 6008 .name = "gcc_pcie_6a_gdsc", 6009 }, 6010 .pwrsts = PWRSTS_OFF_ON, 6011 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 6012 }; 6013 6014 static struct gdsc gcc_pcie_6b_gdsc = { 6015 .gdscr = 0x8d004, 6016 .en_rest_wait_val = 0x2, 6017 .en_few_wait_val = 0x2, 6018 .clk_dis_wait_val = 0xf, 6019 .pd = { 6020 .name = "gcc_pcie_6b_gdsc", 6021 }, 6022 .pwrsts = PWRSTS_OFF_ON, 6023 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 6024 }; 6025 6026 static struct gdsc gcc_ufs_mem_phy_gdsc = { 6027 .gdscr = 0x9e000, 6028 .en_rest_wait_val = 0x2, 6029 .en_few_wait_val = 0x2, 6030 .clk_dis_wait_val = 0x2, 6031 .pd = { 6032 .name = "gcc_ufs_mem_phy_gdsc", 6033 }, 6034 .pwrsts = PWRSTS_OFF_ON, 6035 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6036 }; 6037 6038 static struct gdsc gcc_ufs_phy_gdsc = { 6039 .gdscr = 0x77004, 6040 .en_rest_wait_val = 0x2, 6041 .en_few_wait_val = 0x2, 6042 .clk_dis_wait_val = 0xf, 6043 .pd = { 6044 .name = "gcc_ufs_phy_gdsc", 6045 }, 6046 .pwrsts = PWRSTS_OFF_ON, 6047 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6048 }; 6049 6050 static struct gdsc gcc_usb20_prim_gdsc = { 6051 .gdscr = 0x29004, 6052 .en_rest_wait_val = 0x2, 6053 .en_few_wait_val = 0x2, 6054 .clk_dis_wait_val = 0xf, 6055 .pd = { 6056 .name = "gcc_usb20_prim_gdsc", 6057 }, 6058 .pwrsts = PWRSTS_RET_ON, 6059 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6060 }; 6061 6062 static struct gdsc gcc_usb30_mp_gdsc = { 6063 .gdscr = 0x17004, 6064 .en_rest_wait_val = 0x2, 6065 .en_few_wait_val = 0x2, 6066 .clk_dis_wait_val = 0xf, 6067 .pd = { 6068 .name = "gcc_usb30_mp_gdsc", 6069 }, 6070 .pwrsts = PWRSTS_RET_ON, 6071 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6072 }; 6073 6074 static struct gdsc gcc_usb30_prim_gdsc = { 6075 .gdscr = 0x39004, 6076 .en_rest_wait_val = 0x2, 6077 .en_few_wait_val = 0x2, 6078 .clk_dis_wait_val = 0xf, 6079 .pd = { 6080 .name = "gcc_usb30_prim_gdsc", 6081 }, 6082 .pwrsts = PWRSTS_RET_ON, 6083 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6084 }; 6085 6086 static struct gdsc gcc_usb30_sec_gdsc = { 6087 .gdscr = 0xa1004, 6088 .en_rest_wait_val = 0x2, 6089 .en_few_wait_val = 0x2, 6090 .clk_dis_wait_val = 0xf, 6091 .pd = { 6092 .name = "gcc_usb30_sec_gdsc", 6093 }, 6094 .pwrsts = PWRSTS_RET_ON, 6095 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6096 }; 6097 6098 static struct gdsc gcc_usb30_tert_gdsc = { 6099 .gdscr = 0xa2004, 6100 .en_rest_wait_val = 0x2, 6101 .en_few_wait_val = 0x2, 6102 .clk_dis_wait_val = 0xf, 6103 .pd = { 6104 .name = "gcc_usb30_tert_gdsc", 6105 }, 6106 .pwrsts = PWRSTS_RET_ON, 6107 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6108 }; 6109 6110 static struct gdsc gcc_usb3_mp_ss0_phy_gdsc = { 6111 .gdscr = 0x1900c, 6112 .en_rest_wait_val = 0x2, 6113 .en_few_wait_val = 0x2, 6114 .clk_dis_wait_val = 0x2, 6115 .pd = { 6116 .name = "gcc_usb3_mp_ss0_phy_gdsc", 6117 }, 6118 .pwrsts = PWRSTS_RET_ON, 6119 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6120 }; 6121 6122 static struct gdsc gcc_usb3_mp_ss1_phy_gdsc = { 6123 .gdscr = 0x5400c, 6124 .en_rest_wait_val = 0x2, 6125 .en_few_wait_val = 0x2, 6126 .clk_dis_wait_val = 0x2, 6127 .pd = { 6128 .name = "gcc_usb3_mp_ss1_phy_gdsc", 6129 }, 6130 .pwrsts = PWRSTS_RET_ON, 6131 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6132 }; 6133 6134 static struct gdsc gcc_usb4_0_gdsc = { 6135 .gdscr = 0x9f004, 6136 .en_rest_wait_val = 0x2, 6137 .en_few_wait_val = 0x2, 6138 .clk_dis_wait_val = 0xf, 6139 .pd = { 6140 .name = "gcc_usb4_0_gdsc", 6141 }, 6142 .pwrsts = PWRSTS_OFF_ON, 6143 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6144 }; 6145 6146 static struct gdsc gcc_usb4_1_gdsc = { 6147 .gdscr = 0x2b004, 6148 .en_rest_wait_val = 0x2, 6149 .en_few_wait_val = 0x2, 6150 .clk_dis_wait_val = 0xf, 6151 .pd = { 6152 .name = "gcc_usb4_1_gdsc", 6153 }, 6154 .pwrsts = PWRSTS_OFF_ON, 6155 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6156 }; 6157 6158 static struct gdsc gcc_usb4_2_gdsc = { 6159 .gdscr = 0x11004, 6160 .en_rest_wait_val = 0x2, 6161 .en_few_wait_val = 0x2, 6162 .clk_dis_wait_val = 0xf, 6163 .pd = { 6164 .name = "gcc_usb4_2_gdsc", 6165 }, 6166 .pwrsts = PWRSTS_OFF_ON, 6167 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6168 }; 6169 6170 static struct gdsc gcc_usb_0_phy_gdsc = { 6171 .gdscr = 0x50024, 6172 .en_rest_wait_val = 0x2, 6173 .en_few_wait_val = 0x2, 6174 .clk_dis_wait_val = 0x2, 6175 .pd = { 6176 .name = "gcc_usb_0_phy_gdsc", 6177 }, 6178 .pwrsts = PWRSTS_RET_ON, 6179 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6180 }; 6181 6182 static struct gdsc gcc_usb_1_phy_gdsc = { 6183 .gdscr = 0x2a024, 6184 .en_rest_wait_val = 0x2, 6185 .en_few_wait_val = 0x2, 6186 .clk_dis_wait_val = 0x2, 6187 .pd = { 6188 .name = "gcc_usb_1_phy_gdsc", 6189 }, 6190 .pwrsts = PWRSTS_RET_ON, 6191 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6192 }; 6193 6194 static struct gdsc gcc_usb_2_phy_gdsc = { 6195 .gdscr = 0xa3024, 6196 .en_rest_wait_val = 0x2, 6197 .en_few_wait_val = 0x2, 6198 .clk_dis_wait_val = 0x2, 6199 .pd = { 6200 .name = "gcc_usb_2_phy_gdsc", 6201 }, 6202 .pwrsts = PWRSTS_RET_ON, 6203 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6204 }; 6205 6206 static struct clk_regmap *gcc_x1e80100_clocks[] = { 6207 [GCC_AGGRE_NOC_USB_NORTH_AXI_CLK] = &gcc_aggre_noc_usb_north_axi_clk.clkr, 6208 [GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK] = &gcc_aggre_noc_usb_south_axi_clk.clkr, 6209 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 6210 [GCC_AGGRE_USB2_PRIM_AXI_CLK] = &gcc_aggre_usb2_prim_axi_clk.clkr, 6211 [GCC_AGGRE_USB3_MP_AXI_CLK] = &gcc_aggre_usb3_mp_axi_clk.clkr, 6212 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 6213 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, 6214 [GCC_AGGRE_USB3_TERT_AXI_CLK] = &gcc_aggre_usb3_tert_axi_clk.clkr, 6215 [GCC_AGGRE_USB4_0_AXI_CLK] = &gcc_aggre_usb4_0_axi_clk.clkr, 6216 [GCC_AGGRE_USB4_1_AXI_CLK] = &gcc_aggre_usb4_1_axi_clk.clkr, 6217 [GCC_AGGRE_USB4_2_AXI_CLK] = &gcc_aggre_usb4_2_axi_clk.clkr, 6218 [GCC_AGGRE_USB_NOC_AXI_CLK] = &gcc_aggre_usb_noc_axi_clk.clkr, 6219 [GCC_AV1E_AHB_CLK] = &gcc_av1e_ahb_clk.clkr, 6220 [GCC_AV1E_AXI_CLK] = &gcc_av1e_axi_clk.clkr, 6221 [GCC_AV1E_XO_CLK] = &gcc_av1e_xo_clk.clkr, 6222 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 6223 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 6224 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 6225 [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr, 6226 [GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_north_ahb_clk.clkr, 6227 [GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_south_ahb_clk.clkr, 6228 [GCC_CFG_NOC_USB2_PRIM_AXI_CLK] = &gcc_cfg_noc_usb2_prim_axi_clk.clkr, 6229 [GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr, 6230 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 6231 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, 6232 [GCC_CFG_NOC_USB3_TERT_AXI_CLK] = &gcc_cfg_noc_usb3_tert_axi_clk.clkr, 6233 [GCC_CFG_NOC_USB_ANOC_AHB_CLK] = &gcc_cfg_noc_usb_anoc_ahb_clk.clkr, 6234 [GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK] = &gcc_cfg_noc_usb_anoc_north_ahb_clk.clkr, 6235 [GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK] = &gcc_cfg_noc_usb_anoc_south_ahb_clk.clkr, 6236 [GCC_CNOC_PCIE1_TUNNEL_CLK] = &gcc_cnoc_pcie1_tunnel_clk.clkr, 6237 [GCC_CNOC_PCIE2_TUNNEL_CLK] = &gcc_cnoc_pcie2_tunnel_clk.clkr, 6238 [GCC_CNOC_PCIE_NORTH_SF_AXI_CLK] = &gcc_cnoc_pcie_north_sf_axi_clk.clkr, 6239 [GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK] = &gcc_cnoc_pcie_south_sf_axi_clk.clkr, 6240 [GCC_CNOC_PCIE_TUNNEL_CLK] = &gcc_cnoc_pcie_tunnel_clk.clkr, 6241 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 6242 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 6243 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 6244 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 6245 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 6246 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 6247 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 6248 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 6249 [GCC_GPLL0] = &gcc_gpll0.clkr, 6250 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 6251 [GCC_GPLL4] = &gcc_gpll4.clkr, 6252 [GCC_GPLL7] = &gcc_gpll7.clkr, 6253 [GCC_GPLL8] = &gcc_gpll8.clkr, 6254 [GCC_GPLL9] = &gcc_gpll9.clkr, 6255 [GCC_GPU_GPLL0_CPH_CLK_SRC] = &gcc_gpu_gpll0_cph_clk_src.clkr, 6256 [GCC_GPU_GPLL0_DIV_CPH_CLK_SRC] = &gcc_gpu_gpll0_div_cph_clk_src.clkr, 6257 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 6258 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 6259 [GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr, 6260 [GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr, 6261 [GCC_PCIE2_PHY_RCHNG_CLK] = &gcc_pcie2_phy_rchng_clk.clkr, 6262 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 6263 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 6264 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 6265 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 6266 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 6267 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 6268 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 6269 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 6270 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 6271 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 6272 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 6273 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 6274 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, 6275 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 6276 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 6277 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 6278 [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr, 6279 [GCC_PCIE_2_AUX_CLK_SRC] = &gcc_pcie_2_aux_clk_src.clkr, 6280 [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr, 6281 [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr, 6282 [GCC_PCIE_2_PHY_RCHNG_CLK_SRC] = &gcc_pcie_2_phy_rchng_clk_src.clkr, 6283 [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr, 6284 [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr, 6285 [GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr, 6286 [GCC_PCIE_3_AUX_CLK] = &gcc_pcie_3_aux_clk.clkr, 6287 [GCC_PCIE_3_AUX_CLK_SRC] = &gcc_pcie_3_aux_clk_src.clkr, 6288 [GCC_PCIE_3_CFG_AHB_CLK] = &gcc_pcie_3_cfg_ahb_clk.clkr, 6289 [GCC_PCIE_3_MSTR_AXI_CLK] = &gcc_pcie_3_mstr_axi_clk.clkr, 6290 [GCC_PCIE_3_PHY_AUX_CLK] = &gcc_pcie_3_phy_aux_clk.clkr, 6291 [GCC_PCIE_3_PHY_RCHNG_CLK] = &gcc_pcie_3_phy_rchng_clk.clkr, 6292 [GCC_PCIE_3_PHY_RCHNG_CLK_SRC] = &gcc_pcie_3_phy_rchng_clk_src.clkr, 6293 [GCC_PCIE_3_PIPE_CLK] = &gcc_pcie_3_pipe_clk.clkr, 6294 [GCC_PCIE_3_PIPE_CLK_SRC] = &gcc_pcie_3_pipe_clk_src.clkr, 6295 [GCC_PCIE_3_PIPE_DIV_CLK_SRC] = &gcc_pcie_3_pipe_div_clk_src.clkr, 6296 [GCC_PCIE_3_PIPEDIV2_CLK] = &gcc_pcie_3_pipediv2_clk.clkr, 6297 [GCC_PCIE_3_SLV_AXI_CLK] = &gcc_pcie_3_slv_axi_clk.clkr, 6298 [GCC_PCIE_3_SLV_Q2A_AXI_CLK] = &gcc_pcie_3_slv_q2a_axi_clk.clkr, 6299 [GCC_PCIE_4_AUX_CLK] = &gcc_pcie_4_aux_clk.clkr, 6300 [GCC_PCIE_4_AUX_CLK_SRC] = &gcc_pcie_4_aux_clk_src.clkr, 6301 [GCC_PCIE_4_CFG_AHB_CLK] = &gcc_pcie_4_cfg_ahb_clk.clkr, 6302 [GCC_PCIE_4_MSTR_AXI_CLK] = &gcc_pcie_4_mstr_axi_clk.clkr, 6303 [GCC_PCIE_4_PHY_RCHNG_CLK] = &gcc_pcie_4_phy_rchng_clk.clkr, 6304 [GCC_PCIE_4_PHY_RCHNG_CLK_SRC] = &gcc_pcie_4_phy_rchng_clk_src.clkr, 6305 [GCC_PCIE_4_PIPE_CLK] = &gcc_pcie_4_pipe_clk.clkr, 6306 [GCC_PCIE_4_PIPE_CLK_SRC] = &gcc_pcie_4_pipe_clk_src.clkr, 6307 [GCC_PCIE_4_PIPE_DIV_CLK_SRC] = &gcc_pcie_4_pipe_div_clk_src.clkr, 6308 [GCC_PCIE_4_PIPEDIV2_CLK] = &gcc_pcie_4_pipediv2_clk.clkr, 6309 [GCC_PCIE_4_SLV_AXI_CLK] = &gcc_pcie_4_slv_axi_clk.clkr, 6310 [GCC_PCIE_4_SLV_Q2A_AXI_CLK] = &gcc_pcie_4_slv_q2a_axi_clk.clkr, 6311 [GCC_PCIE_5_AUX_CLK] = &gcc_pcie_5_aux_clk.clkr, 6312 [GCC_PCIE_5_AUX_CLK_SRC] = &gcc_pcie_5_aux_clk_src.clkr, 6313 [GCC_PCIE_5_CFG_AHB_CLK] = &gcc_pcie_5_cfg_ahb_clk.clkr, 6314 [GCC_PCIE_5_MSTR_AXI_CLK] = &gcc_pcie_5_mstr_axi_clk.clkr, 6315 [GCC_PCIE_5_PHY_RCHNG_CLK] = &gcc_pcie_5_phy_rchng_clk.clkr, 6316 [GCC_PCIE_5_PHY_RCHNG_CLK_SRC] = &gcc_pcie_5_phy_rchng_clk_src.clkr, 6317 [GCC_PCIE_5_PIPE_CLK] = &gcc_pcie_5_pipe_clk.clkr, 6318 [GCC_PCIE_5_PIPE_CLK_SRC] = &gcc_pcie_5_pipe_clk_src.clkr, 6319 [GCC_PCIE_5_PIPE_DIV_CLK_SRC] = &gcc_pcie_5_pipe_div_clk_src.clkr, 6320 [GCC_PCIE_5_PIPEDIV2_CLK] = &gcc_pcie_5_pipediv2_clk.clkr, 6321 [GCC_PCIE_5_SLV_AXI_CLK] = &gcc_pcie_5_slv_axi_clk.clkr, 6322 [GCC_PCIE_5_SLV_Q2A_AXI_CLK] = &gcc_pcie_5_slv_q2a_axi_clk.clkr, 6323 [GCC_PCIE_6A_AUX_CLK] = &gcc_pcie_6a_aux_clk.clkr, 6324 [GCC_PCIE_6A_AUX_CLK_SRC] = &gcc_pcie_6a_aux_clk_src.clkr, 6325 [GCC_PCIE_6A_CFG_AHB_CLK] = &gcc_pcie_6a_cfg_ahb_clk.clkr, 6326 [GCC_PCIE_6A_MSTR_AXI_CLK] = &gcc_pcie_6a_mstr_axi_clk.clkr, 6327 [GCC_PCIE_6A_PHY_AUX_CLK] = &gcc_pcie_6a_phy_aux_clk.clkr, 6328 [GCC_PCIE_6A_PHY_RCHNG_CLK] = &gcc_pcie_6a_phy_rchng_clk.clkr, 6329 [GCC_PCIE_6A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_6a_phy_rchng_clk_src.clkr, 6330 [GCC_PCIE_6A_PIPE_CLK] = &gcc_pcie_6a_pipe_clk.clkr, 6331 [GCC_PCIE_6A_PIPE_CLK_SRC] = &gcc_pcie_6a_pipe_clk_src.clkr, 6332 [GCC_PCIE_6A_PIPE_DIV_CLK_SRC] = &gcc_pcie_6a_pipe_div_clk_src.clkr, 6333 [GCC_PCIE_6A_PIPEDIV2_CLK] = &gcc_pcie_6a_pipediv2_clk.clkr, 6334 [GCC_PCIE_6A_SLV_AXI_CLK] = &gcc_pcie_6a_slv_axi_clk.clkr, 6335 [GCC_PCIE_6A_SLV_Q2A_AXI_CLK] = &gcc_pcie_6a_slv_q2a_axi_clk.clkr, 6336 [GCC_PCIE_6B_AUX_CLK] = &gcc_pcie_6b_aux_clk.clkr, 6337 [GCC_PCIE_6B_AUX_CLK_SRC] = &gcc_pcie_6b_aux_clk_src.clkr, 6338 [GCC_PCIE_6B_CFG_AHB_CLK] = &gcc_pcie_6b_cfg_ahb_clk.clkr, 6339 [GCC_PCIE_6B_MSTR_AXI_CLK] = &gcc_pcie_6b_mstr_axi_clk.clkr, 6340 [GCC_PCIE_6B_PHY_AUX_CLK] = &gcc_pcie_6b_phy_aux_clk.clkr, 6341 [GCC_PCIE_6B_PHY_RCHNG_CLK] = &gcc_pcie_6b_phy_rchng_clk.clkr, 6342 [GCC_PCIE_6B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_6b_phy_rchng_clk_src.clkr, 6343 [GCC_PCIE_6B_PIPE_CLK] = &gcc_pcie_6b_pipe_clk.clkr, 6344 [GCC_PCIE_6B_PIPE_CLK_SRC] = &gcc_pcie_6b_pipe_clk_src.clkr, 6345 [GCC_PCIE_6B_PIPE_DIV_CLK_SRC] = &gcc_pcie_6b_pipe_div_clk_src.clkr, 6346 [GCC_PCIE_6B_PIPEDIV2_CLK] = &gcc_pcie_6b_pipediv2_clk.clkr, 6347 [GCC_PCIE_6B_SLV_AXI_CLK] = &gcc_pcie_6b_slv_axi_clk.clkr, 6348 [GCC_PCIE_6B_SLV_Q2A_AXI_CLK] = &gcc_pcie_6b_slv_q2a_axi_clk.clkr, 6349 [GCC_PCIE_RSCC_AHB_CLK] = &gcc_pcie_rscc_ahb_clk.clkr, 6350 [GCC_PCIE_RSCC_XO_CLK] = &gcc_pcie_rscc_xo_clk.clkr, 6351 [GCC_PCIE_RSCC_XO_CLK_SRC] = &gcc_pcie_rscc_xo_clk_src.clkr, 6352 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 6353 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 6354 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 6355 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 6356 [GCC_QMIP_AV1E_AHB_CLK] = &gcc_qmip_av1e_ahb_clk.clkr, 6357 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 6358 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 6359 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 6360 [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr, 6361 [GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr, 6362 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 6363 [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr, 6364 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 6365 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 6366 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 6367 [GCC_QUPV3_WRAP0_QSPI_S2_CLK] = &gcc_qupv3_wrap0_qspi_s2_clk.clkr, 6368 [GCC_QUPV3_WRAP0_QSPI_S3_CLK] = &gcc_qupv3_wrap0_qspi_s3_clk.clkr, 6369 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 6370 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 6371 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 6372 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 6373 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 6374 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 6375 [GCC_QUPV3_WRAP0_S2_DIV_CLK_SRC] = &gcc_qupv3_wrap0_s2_div_clk_src.clkr, 6376 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 6377 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 6378 [GCC_QUPV3_WRAP0_S3_DIV_CLK_SRC] = &gcc_qupv3_wrap0_s3_div_clk_src.clkr, 6379 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 6380 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 6381 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 6382 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 6383 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 6384 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 6385 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 6386 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 6387 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 6388 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 6389 [GCC_QUPV3_WRAP1_QSPI_S2_CLK] = &gcc_qupv3_wrap1_qspi_s2_clk.clkr, 6390 [GCC_QUPV3_WRAP1_QSPI_S3_CLK] = &gcc_qupv3_wrap1_qspi_s3_clk.clkr, 6391 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 6392 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 6393 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 6394 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 6395 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 6396 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 6397 [GCC_QUPV3_WRAP1_S2_DIV_CLK_SRC] = &gcc_qupv3_wrap1_s2_div_clk_src.clkr, 6398 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 6399 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 6400 [GCC_QUPV3_WRAP1_S3_DIV_CLK_SRC] = &gcc_qupv3_wrap1_s3_div_clk_src.clkr, 6401 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 6402 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 6403 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 6404 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 6405 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 6406 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 6407 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 6408 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 6409 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, 6410 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, 6411 [GCC_QUPV3_WRAP2_QSPI_S2_CLK] = &gcc_qupv3_wrap2_qspi_s2_clk.clkr, 6412 [GCC_QUPV3_WRAP2_QSPI_S3_CLK] = &gcc_qupv3_wrap2_qspi_s3_clk.clkr, 6413 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 6414 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 6415 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 6416 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 6417 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 6418 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 6419 [GCC_QUPV3_WRAP2_S2_DIV_CLK_SRC] = &gcc_qupv3_wrap2_s2_div_clk_src.clkr, 6420 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 6421 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 6422 [GCC_QUPV3_WRAP2_S3_DIV_CLK_SRC] = &gcc_qupv3_wrap2_s3_div_clk_src.clkr, 6423 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 6424 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 6425 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, 6426 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, 6427 [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr, 6428 [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr, 6429 [GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr, 6430 [GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr, 6431 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 6432 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 6433 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 6434 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 6435 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 6436 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 6437 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 6438 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 6439 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 6440 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 6441 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 6442 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 6443 [GCC_SYS_NOC_USB_AXI_CLK] = &gcc_sys_noc_usb_axi_clk.clkr, 6444 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 6445 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 6446 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 6447 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 6448 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 6449 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 6450 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 6451 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 6452 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 6453 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 6454 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 6455 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 6456 [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr, 6457 [GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr, 6458 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr, 6459 [GCC_USB20_MOCK_UTMI_CLK_SRC] = &gcc_usb20_mock_utmi_clk_src.clkr, 6460 [GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb20_mock_utmi_postdiv_clk_src.clkr, 6461 [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr, 6462 [GCC_USB30_MP_MASTER_CLK] = &gcc_usb30_mp_master_clk.clkr, 6463 [GCC_USB30_MP_MASTER_CLK_SRC] = &gcc_usb30_mp_master_clk_src.clkr, 6464 [GCC_USB30_MP_MOCK_UTMI_CLK] = &gcc_usb30_mp_mock_utmi_clk.clkr, 6465 [GCC_USB30_MP_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mp_mock_utmi_clk_src.clkr, 6466 [GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr, 6467 [GCC_USB30_MP_SLEEP_CLK] = &gcc_usb30_mp_sleep_clk.clkr, 6468 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 6469 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 6470 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 6471 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 6472 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 6473 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 6474 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, 6475 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, 6476 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, 6477 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr, 6478 [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr, 6479 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, 6480 [GCC_USB30_TERT_MASTER_CLK] = &gcc_usb30_tert_master_clk.clkr, 6481 [GCC_USB30_TERT_MASTER_CLK_SRC] = &gcc_usb30_tert_master_clk_src.clkr, 6482 [GCC_USB30_TERT_MOCK_UTMI_CLK] = &gcc_usb30_tert_mock_utmi_clk.clkr, 6483 [GCC_USB30_TERT_MOCK_UTMI_CLK_SRC] = &gcc_usb30_tert_mock_utmi_clk_src.clkr, 6484 [GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr, 6485 [GCC_USB30_TERT_SLEEP_CLK] = &gcc_usb30_tert_sleep_clk.clkr, 6486 [GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr, 6487 [GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr, 6488 [GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr, 6489 [GCC_USB3_MP_PHY_PIPE_0_CLK] = &gcc_usb3_mp_phy_pipe_0_clk.clkr, 6490 [GCC_USB3_MP_PHY_PIPE_1_CLK] = &gcc_usb3_mp_phy_pipe_1_clk.clkr, 6491 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 6492 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 6493 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 6494 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 6495 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 6496 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, 6497 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, 6498 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, 6499 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, 6500 [GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr, 6501 [GCC_USB3_TERT_PHY_AUX_CLK] = &gcc_usb3_tert_phy_aux_clk.clkr, 6502 [GCC_USB3_TERT_PHY_AUX_CLK_SRC] = &gcc_usb3_tert_phy_aux_clk_src.clkr, 6503 [GCC_USB3_TERT_PHY_COM_AUX_CLK] = &gcc_usb3_tert_phy_com_aux_clk.clkr, 6504 [GCC_USB3_TERT_PHY_PIPE_CLK] = &gcc_usb3_tert_phy_pipe_clk.clkr, 6505 [GCC_USB3_TERT_PHY_PIPE_CLK_SRC] = &gcc_usb3_tert_phy_pipe_clk_src.clkr, 6506 [GCC_USB4_0_CFG_AHB_CLK] = &gcc_usb4_0_cfg_ahb_clk.clkr, 6507 [GCC_USB4_0_DP0_CLK] = &gcc_usb4_0_dp0_clk.clkr, 6508 [GCC_USB4_0_DP1_CLK] = &gcc_usb4_0_dp1_clk.clkr, 6509 [GCC_USB4_0_MASTER_CLK] = &gcc_usb4_0_master_clk.clkr, 6510 [GCC_USB4_0_MASTER_CLK_SRC] = &gcc_usb4_0_master_clk_src.clkr, 6511 [GCC_USB4_0_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_0_phy_p2rr2p_pipe_clk.clkr, 6512 [GCC_USB4_0_PHY_PCIE_PIPE_CLK] = &gcc_usb4_0_phy_pcie_pipe_clk.clkr, 6513 [GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_clk_src.clkr, 6514 [GCC_USB4_0_PHY_RX0_CLK] = &gcc_usb4_0_phy_rx0_clk.clkr, 6515 [GCC_USB4_0_PHY_RX1_CLK] = &gcc_usb4_0_phy_rx1_clk.clkr, 6516 [GCC_USB4_0_PHY_USB_PIPE_CLK] = &gcc_usb4_0_phy_usb_pipe_clk.clkr, 6517 [GCC_USB4_0_SB_IF_CLK] = &gcc_usb4_0_sb_if_clk.clkr, 6518 [GCC_USB4_0_SB_IF_CLK_SRC] = &gcc_usb4_0_sb_if_clk_src.clkr, 6519 [GCC_USB4_0_SYS_CLK] = &gcc_usb4_0_sys_clk.clkr, 6520 [GCC_USB4_0_TMU_CLK] = &gcc_usb4_0_tmu_clk.clkr, 6521 [GCC_USB4_0_TMU_CLK_SRC] = &gcc_usb4_0_tmu_clk_src.clkr, 6522 [GCC_USB4_1_CFG_AHB_CLK] = &gcc_usb4_1_cfg_ahb_clk.clkr, 6523 [GCC_USB4_1_DP0_CLK] = &gcc_usb4_1_dp0_clk.clkr, 6524 [GCC_USB4_1_DP1_CLK] = &gcc_usb4_1_dp1_clk.clkr, 6525 [GCC_USB4_1_MASTER_CLK] = &gcc_usb4_1_master_clk.clkr, 6526 [GCC_USB4_1_MASTER_CLK_SRC] = &gcc_usb4_1_master_clk_src.clkr, 6527 [GCC_USB4_1_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_1_phy_p2rr2p_pipe_clk.clkr, 6528 [GCC_USB4_1_PHY_PCIE_PIPE_CLK] = &gcc_usb4_1_phy_pcie_pipe_clk.clkr, 6529 [GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_clk_src.clkr, 6530 [GCC_USB4_1_PHY_RX0_CLK] = &gcc_usb4_1_phy_rx0_clk.clkr, 6531 [GCC_USB4_1_PHY_RX1_CLK] = &gcc_usb4_1_phy_rx1_clk.clkr, 6532 [GCC_USB4_1_PHY_USB_PIPE_CLK] = &gcc_usb4_1_phy_usb_pipe_clk.clkr, 6533 [GCC_USB4_1_SB_IF_CLK] = &gcc_usb4_1_sb_if_clk.clkr, 6534 [GCC_USB4_1_SB_IF_CLK_SRC] = &gcc_usb4_1_sb_if_clk_src.clkr, 6535 [GCC_USB4_1_SYS_CLK] = &gcc_usb4_1_sys_clk.clkr, 6536 [GCC_USB4_1_TMU_CLK] = &gcc_usb4_1_tmu_clk.clkr, 6537 [GCC_USB4_1_TMU_CLK_SRC] = &gcc_usb4_1_tmu_clk_src.clkr, 6538 [GCC_USB4_2_CFG_AHB_CLK] = &gcc_usb4_2_cfg_ahb_clk.clkr, 6539 [GCC_USB4_2_DP0_CLK] = &gcc_usb4_2_dp0_clk.clkr, 6540 [GCC_USB4_2_DP1_CLK] = &gcc_usb4_2_dp1_clk.clkr, 6541 [GCC_USB4_2_MASTER_CLK] = &gcc_usb4_2_master_clk.clkr, 6542 [GCC_USB4_2_MASTER_CLK_SRC] = &gcc_usb4_2_master_clk_src.clkr, 6543 [GCC_USB4_2_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_2_phy_p2rr2p_pipe_clk.clkr, 6544 [GCC_USB4_2_PHY_PCIE_PIPE_CLK] = &gcc_usb4_2_phy_pcie_pipe_clk.clkr, 6545 [GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_clk_src.clkr, 6546 [GCC_USB4_2_PHY_RX0_CLK] = &gcc_usb4_2_phy_rx0_clk.clkr, 6547 [GCC_USB4_2_PHY_RX1_CLK] = &gcc_usb4_2_phy_rx1_clk.clkr, 6548 [GCC_USB4_2_PHY_USB_PIPE_CLK] = &gcc_usb4_2_phy_usb_pipe_clk.clkr, 6549 [GCC_USB4_2_SB_IF_CLK] = &gcc_usb4_2_sb_if_clk.clkr, 6550 [GCC_USB4_2_SB_IF_CLK_SRC] = &gcc_usb4_2_sb_if_clk_src.clkr, 6551 [GCC_USB4_2_SYS_CLK] = &gcc_usb4_2_sys_clk.clkr, 6552 [GCC_USB4_2_TMU_CLK] = &gcc_usb4_2_tmu_clk.clkr, 6553 [GCC_USB4_2_TMU_CLK_SRC] = &gcc_usb4_2_tmu_clk_src.clkr, 6554 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 6555 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 6556 }; 6557 6558 static struct gdsc *gcc_x1e80100_gdscs[] = { 6559 [GCC_PCIE_0_TUNNEL_GDSC] = &gcc_pcie_0_tunnel_gdsc, 6560 [GCC_PCIE_1_TUNNEL_GDSC] = &gcc_pcie_1_tunnel_gdsc, 6561 [GCC_PCIE_2_TUNNEL_GDSC] = &gcc_pcie_2_tunnel_gdsc, 6562 [GCC_PCIE_3_GDSC] = &gcc_pcie_3_gdsc, 6563 [GCC_PCIE_3_PHY_GDSC] = &gcc_pcie_3_phy_gdsc, 6564 [GCC_PCIE_4_GDSC] = &gcc_pcie_4_gdsc, 6565 [GCC_PCIE_4_PHY_GDSC] = &gcc_pcie_4_phy_gdsc, 6566 [GCC_PCIE_5_GDSC] = &gcc_pcie_5_gdsc, 6567 [GCC_PCIE_5_PHY_GDSC] = &gcc_pcie_5_phy_gdsc, 6568 [GCC_PCIE_6_PHY_GDSC] = &gcc_pcie_6_phy_gdsc, 6569 [GCC_PCIE_6A_GDSC] = &gcc_pcie_6a_gdsc, 6570 [GCC_PCIE_6B_GDSC] = &gcc_pcie_6b_gdsc, 6571 [GCC_UFS_MEM_PHY_GDSC] = &gcc_ufs_mem_phy_gdsc, 6572 [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc, 6573 [GCC_USB20_PRIM_GDSC] = &gcc_usb20_prim_gdsc, 6574 [GCC_USB30_MP_GDSC] = &gcc_usb30_mp_gdsc, 6575 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, 6576 [GCC_USB30_SEC_GDSC] = &gcc_usb30_sec_gdsc, 6577 [GCC_USB30_TERT_GDSC] = &gcc_usb30_tert_gdsc, 6578 [GCC_USB3_MP_SS0_PHY_GDSC] = &gcc_usb3_mp_ss0_phy_gdsc, 6579 [GCC_USB3_MP_SS1_PHY_GDSC] = &gcc_usb3_mp_ss1_phy_gdsc, 6580 [GCC_USB4_0_GDSC] = &gcc_usb4_0_gdsc, 6581 [GCC_USB4_1_GDSC] = &gcc_usb4_1_gdsc, 6582 [GCC_USB4_2_GDSC] = &gcc_usb4_2_gdsc, 6583 [GCC_USB_0_PHY_GDSC] = &gcc_usb_0_phy_gdsc, 6584 [GCC_USB_1_PHY_GDSC] = &gcc_usb_1_phy_gdsc, 6585 [GCC_USB_2_PHY_GDSC] = &gcc_usb_2_phy_gdsc, 6586 }; 6587 6588 static const struct qcom_reset_map gcc_x1e80100_resets[] = { 6589 [GCC_AV1E_BCR] = { 0x4a000 }, 6590 [GCC_CAMERA_BCR] = { 0x26000 }, 6591 [GCC_DISPLAY_BCR] = { 0x27000 }, 6592 [GCC_GPU_BCR] = { 0x71000 }, 6593 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, 6594 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, 6595 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 6596 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 }, 6597 [GCC_PCIE_0_TUNNEL_BCR] = { 0xa0000 }, 6598 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 }, 6599 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 }, 6600 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, 6601 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 }, 6602 [GCC_PCIE_1_TUNNEL_BCR] = { 0x2c000 }, 6603 [GCC_PCIE_2_LINK_DOWN_BCR] = { 0xa5014 }, 6604 [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0xa5020 }, 6605 [GCC_PCIE_2_PHY_BCR] = { 0xa501c }, 6606 [GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0xa5028 }, 6607 [GCC_PCIE_2_TUNNEL_BCR] = { 0x13000 }, 6608 [GCC_PCIE_3_BCR] = { 0x58000 }, 6609 [GCC_PCIE_3_LINK_DOWN_BCR] = { 0xab014 }, 6610 [GCC_PCIE_3_NOCSR_COM_PHY_BCR] = { 0xab020 }, 6611 [GCC_PCIE_3_PHY_BCR] = { 0xab01c }, 6612 [GCC_PCIE_3_PHY_NOCSR_COM_PHY_BCR] = { 0xab024 }, 6613 [GCC_PCIE_4_BCR] = { 0x6b000 }, 6614 [GCC_PCIE_4_LINK_DOWN_BCR] = { 0xb3014 }, 6615 [GCC_PCIE_4_NOCSR_COM_PHY_BCR] = { 0xb3020 }, 6616 [GCC_PCIE_4_PHY_BCR] = { 0xb301c }, 6617 [GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] = { 0xb3028 }, 6618 [GCC_PCIE_5_BCR] = { 0x2f000 }, 6619 [GCC_PCIE_5_LINK_DOWN_BCR] = { 0xaa014 }, 6620 [GCC_PCIE_5_NOCSR_COM_PHY_BCR] = { 0xaa020 }, 6621 [GCC_PCIE_5_PHY_BCR] = { 0xaa01c }, 6622 [GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR] = { 0xaa028 }, 6623 [GCC_PCIE_6A_BCR] = { 0x31000 }, 6624 [GCC_PCIE_6A_LINK_DOWN_BCR] = { 0xac014 }, 6625 [GCC_PCIE_6A_NOCSR_COM_PHY_BCR] = { 0xac020 }, 6626 [GCC_PCIE_6A_PHY_BCR] = { 0xac01c }, 6627 [GCC_PCIE_6A_PHY_NOCSR_COM_PHY_BCR] = { 0xac024 }, 6628 [GCC_PCIE_6B_BCR] = { 0x8d000 }, 6629 [GCC_PCIE_6B_LINK_DOWN_BCR] = { 0xb5014 }, 6630 [GCC_PCIE_6B_NOCSR_COM_PHY_BCR] = { 0xb5020 }, 6631 [GCC_PCIE_6B_PHY_BCR] = { 0xb501c }, 6632 [GCC_PCIE_6B_PHY_NOCSR_COM_PHY_BCR] = { 0xb5024 }, 6633 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 6634 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c }, 6635 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, 6636 [GCC_PCIE_RSCC_BCR] = { 0xa4000 }, 6637 [GCC_PDM_BCR] = { 0x33000 }, 6638 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x42000 }, 6639 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, 6640 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, 6641 [GCC_QUSB2PHY_HS0_MP_BCR] = { 0x1200c }, 6642 [GCC_QUSB2PHY_HS1_MP_BCR] = { 0x12010 }, 6643 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 6644 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 6645 [GCC_QUSB2PHY_TERT_BCR] = { 0x12008 }, 6646 [GCC_QUSB2PHY_USB20_HS_BCR] = { 0x12014 }, 6647 [GCC_SDCC2_BCR] = { 0x14000 }, 6648 [GCC_SDCC4_BCR] = { 0x16000 }, 6649 [GCC_UFS_PHY_BCR] = { 0x77000 }, 6650 [GCC_USB20_PRIM_BCR] = { 0x29000 }, 6651 [GCC_USB30_MP_BCR] = { 0x17000 }, 6652 [GCC_USB30_PRIM_BCR] = { 0x39000 }, 6653 [GCC_USB30_SEC_BCR] = { 0xa1000 }, 6654 [GCC_USB30_TERT_BCR] = { 0xa2000 }, 6655 [GCC_USB3_MP_SS0_PHY_BCR] = { 0x19008 }, 6656 [GCC_USB3_MP_SS1_PHY_BCR] = { 0x54008 }, 6657 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 6658 [GCC_USB3_PHY_SEC_BCR] = { 0x2a000 }, 6659 [GCC_USB3_PHY_TERT_BCR] = { 0xa3000 }, 6660 [GCC_USB3_UNIPHY_MP0_BCR] = { 0x19000 }, 6661 [GCC_USB3_UNIPHY_MP1_BCR] = { 0x54000 }, 6662 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 6663 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x2a004 }, 6664 [GCC_USB3PHY_PHY_TERT_BCR] = { 0xa3004 }, 6665 [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x19004 }, 6666 [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x54004 }, 6667 [GCC_USB4_0_BCR] = { 0x9f000 }, 6668 [GCC_USB4_0_DP0_PHY_PRIM_BCR] = { 0x50010 }, 6669 [GCC_USB4_1_DP0_PHY_SEC_BCR] = { 0x2a010 }, 6670 [GCC_USB4_2_DP0_PHY_TERT_BCR] = { 0xa3010 }, 6671 [GCC_USB4_1_BCR] = { 0x2b000 }, 6672 [GCC_USB4_2_BCR] = { 0x11000 }, 6673 [GCC_USB_0_PHY_BCR] = { 0x50020 }, 6674 [GCC_USB_1_PHY_BCR] = { 0x2a020 }, 6675 [GCC_USB_2_PHY_BCR] = { 0xa3020 }, 6676 [GCC_VIDEO_BCR] = { 0x32000 }, 6677 }; 6678 6679 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 6680 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 6681 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 6682 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 6683 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 6684 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 6685 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 6686 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 6687 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 6688 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 6689 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 6690 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 6691 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 6692 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 6693 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 6694 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 6695 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 6696 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 6697 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 6698 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), 6699 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), 6700 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 6701 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), 6702 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src), 6703 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src), 6704 }; 6705 6706 static const struct regmap_config gcc_x1e80100_regmap_config = { 6707 .reg_bits = 32, 6708 .reg_stride = 4, 6709 .val_bits = 32, 6710 .max_register = 0x1f41f0, 6711 .fast_io = true, 6712 }; 6713 6714 static const struct qcom_cc_desc gcc_x1e80100_desc = { 6715 .config = &gcc_x1e80100_regmap_config, 6716 .clks = gcc_x1e80100_clocks, 6717 .num_clks = ARRAY_SIZE(gcc_x1e80100_clocks), 6718 .resets = gcc_x1e80100_resets, 6719 .num_resets = ARRAY_SIZE(gcc_x1e80100_resets), 6720 .gdscs = gcc_x1e80100_gdscs, 6721 .num_gdscs = ARRAY_SIZE(gcc_x1e80100_gdscs), 6722 }; 6723 6724 static const struct of_device_id gcc_x1e80100_match_table[] = { 6725 { .compatible = "qcom,x1e80100-gcc" }, 6726 { } 6727 }; 6728 MODULE_DEVICE_TABLE(of, gcc_x1e80100_match_table); 6729 6730 static int gcc_x1e80100_probe(struct platform_device *pdev) 6731 { 6732 struct regmap *regmap; 6733 int ret; 6734 6735 regmap = qcom_cc_map(pdev, &gcc_x1e80100_desc); 6736 if (IS_ERR(regmap)) 6737 return PTR_ERR(regmap); 6738 6739 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 6740 ARRAY_SIZE(gcc_dfs_clocks)); 6741 if (ret) 6742 return ret; 6743 6744 /* Keep some clocks always-on */ 6745 qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ 6746 qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */ 6747 qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ 6748 qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */ 6749 qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */ 6750 qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */ 6751 qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ 6752 6753 /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */ 6754 regmap_write(regmap, 0x52224, 0x0); 6755 6756 /* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks */ 6757 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); 6758 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true); 6759 6760 return qcom_cc_really_probe(&pdev->dev, &gcc_x1e80100_desc, regmap); 6761 } 6762 6763 static struct platform_driver gcc_x1e80100_driver = { 6764 .probe = gcc_x1e80100_probe, 6765 .driver = { 6766 .name = "gcc-x1e80100", 6767 .of_match_table = gcc_x1e80100_match_table, 6768 }, 6769 }; 6770 6771 static int __init gcc_x1e80100_init(void) 6772 { 6773 return platform_driver_register(&gcc_x1e80100_driver); 6774 } 6775 subsys_initcall(gcc_x1e80100_init); 6776 6777 static void __exit gcc_x1e80100_exit(void) 6778 { 6779 platform_driver_unregister(&gcc_x1e80100_driver); 6780 } 6781 module_exit(gcc_x1e80100_exit); 6782 6783 MODULE_DESCRIPTION("QTI GCC X1E80100 Driver"); 6784 MODULE_LICENSE("GPL"); 6785