1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/of_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,x1e80100-gcc.h> 12 13 #include "clk-alpha-pll.h" 14 #include "clk-branch.h" 15 #include "clk-rcg.h" 16 #include "clk-regmap.h" 17 #include "clk-regmap-divider.h" 18 #include "clk-regmap-mux.h" 19 #include "clk-regmap-phy-mux.h" 20 #include "gdsc.h" 21 #include "reset.h" 22 23 enum { 24 DT_BI_TCXO, 25 DT_SLEEP_CLK, 26 DT_PCIE_3_PIPE, 27 DT_PCIE_4_PIPE, 28 DT_PCIE_5_PIPE, 29 DT_PCIE_6A_PIPE, 30 DT_PCIE_6B_PIPE, 31 DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE, 32 DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE, 33 DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE, 34 }; 35 36 enum { 37 P_BI_TCXO, 38 P_GCC_GPLL0_OUT_EVEN, 39 P_GCC_GPLL0_OUT_MAIN, 40 P_GCC_GPLL4_OUT_MAIN, 41 P_GCC_GPLL7_OUT_MAIN, 42 P_GCC_GPLL8_OUT_MAIN, 43 P_GCC_GPLL9_OUT_MAIN, 44 P_SLEEP_CLK, 45 P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 46 P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 47 P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 48 }; 49 50 static struct clk_alpha_pll gcc_gpll0 = { 51 .offset = 0x0, 52 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 53 .clkr = { 54 .enable_reg = 0x52030, 55 .enable_mask = BIT(0), 56 .hw.init = &(const struct clk_init_data) { 57 .name = "gcc_gpll0", 58 .parent_data = &(const struct clk_parent_data) { 59 .index = DT_BI_TCXO, 60 }, 61 .num_parents = 1, 62 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 63 }, 64 }, 65 }; 66 67 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 68 { 0x1, 2 }, 69 { } 70 }; 71 72 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 73 .offset = 0x0, 74 .post_div_shift = 10, 75 .post_div_table = post_div_table_gcc_gpll0_out_even, 76 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 77 .width = 4, 78 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 79 .clkr.hw.init = &(const struct clk_init_data) { 80 .name = "gcc_gpll0_out_even", 81 .parent_hws = (const struct clk_hw*[]) { 82 &gcc_gpll0.clkr.hw, 83 }, 84 .num_parents = 1, 85 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 86 }, 87 }; 88 89 static struct clk_alpha_pll gcc_gpll4 = { 90 .offset = 0x4000, 91 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 92 .clkr = { 93 .enable_reg = 0x52030, 94 .enable_mask = BIT(4), 95 .hw.init = &(const struct clk_init_data) { 96 .name = "gcc_gpll4", 97 .parent_data = &(const struct clk_parent_data) { 98 .index = DT_BI_TCXO, 99 }, 100 .num_parents = 1, 101 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 102 }, 103 }, 104 }; 105 106 static struct clk_alpha_pll gcc_gpll7 = { 107 .offset = 0x7000, 108 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 109 .clkr = { 110 .enable_reg = 0x52030, 111 .enable_mask = BIT(7), 112 .hw.init = &(const struct clk_init_data) { 113 .name = "gcc_gpll7", 114 .parent_data = &(const struct clk_parent_data) { 115 .index = DT_BI_TCXO, 116 }, 117 .num_parents = 1, 118 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 119 }, 120 }, 121 }; 122 123 static struct clk_alpha_pll gcc_gpll8 = { 124 .offset = 0x8000, 125 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 126 .clkr = { 127 .enable_reg = 0x52030, 128 .enable_mask = BIT(8), 129 .hw.init = &(const struct clk_init_data) { 130 .name = "gcc_gpll8", 131 .parent_data = &(const struct clk_parent_data) { 132 .index = DT_BI_TCXO, 133 }, 134 .num_parents = 1, 135 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 136 }, 137 }, 138 }; 139 140 static struct clk_alpha_pll gcc_gpll9 = { 141 .offset = 0x9000, 142 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 143 .clkr = { 144 .enable_reg = 0x52030, 145 .enable_mask = BIT(9), 146 .hw.init = &(const struct clk_init_data) { 147 .name = "gcc_gpll9", 148 .parent_data = &(const struct clk_parent_data) { 149 .index = DT_BI_TCXO, 150 }, 151 .num_parents = 1, 152 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 153 }, 154 }, 155 }; 156 157 static const struct parent_map gcc_parent_map_0[] = { 158 { P_BI_TCXO, 0 }, 159 { P_GCC_GPLL0_OUT_MAIN, 1 }, 160 { P_GCC_GPLL0_OUT_EVEN, 6 }, 161 }; 162 163 static const struct clk_parent_data gcc_parent_data_0[] = { 164 { .index = DT_BI_TCXO }, 165 { .hw = &gcc_gpll0.clkr.hw }, 166 { .hw = &gcc_gpll0_out_even.clkr.hw }, 167 }; 168 169 static const struct parent_map gcc_parent_map_1[] = { 170 { P_BI_TCXO, 0 }, 171 { P_SLEEP_CLK, 5 }, 172 }; 173 174 static const struct clk_parent_data gcc_parent_data_1[] = { 175 { .index = DT_BI_TCXO }, 176 { .index = DT_SLEEP_CLK }, 177 }; 178 179 static const struct parent_map gcc_parent_map_2[] = { 180 { P_BI_TCXO, 0 }, 181 { P_GCC_GPLL0_OUT_MAIN, 1 }, 182 { P_SLEEP_CLK, 5 }, 183 { P_GCC_GPLL0_OUT_EVEN, 6 }, 184 }; 185 186 static const struct clk_parent_data gcc_parent_data_2[] = { 187 { .index = DT_BI_TCXO }, 188 { .hw = &gcc_gpll0.clkr.hw }, 189 { .index = DT_SLEEP_CLK }, 190 { .hw = &gcc_gpll0_out_even.clkr.hw }, 191 }; 192 193 static const struct parent_map gcc_parent_map_3[] = { 194 { P_BI_TCXO, 0 }, 195 }; 196 197 static const struct clk_parent_data gcc_parent_data_3[] = { 198 { .index = DT_BI_TCXO }, 199 }; 200 201 static const struct parent_map gcc_parent_map_4[] = { 202 { P_BI_TCXO, 0 }, 203 { P_GCC_GPLL0_OUT_MAIN, 1 }, 204 { P_GCC_GPLL8_OUT_MAIN, 2 }, 205 { P_GCC_GPLL0_OUT_EVEN, 6 }, 206 }; 207 208 static const struct clk_parent_data gcc_parent_data_4[] = { 209 { .index = DT_BI_TCXO }, 210 { .hw = &gcc_gpll0.clkr.hw }, 211 { .hw = &gcc_gpll8.clkr.hw }, 212 { .hw = &gcc_gpll0_out_even.clkr.hw }, 213 }; 214 215 static const struct parent_map gcc_parent_map_5[] = { 216 { P_BI_TCXO, 0 }, 217 { P_GCC_GPLL0_OUT_MAIN, 1 }, 218 { P_GCC_GPLL7_OUT_MAIN, 2 }, 219 { P_SLEEP_CLK, 5 }, 220 }; 221 222 static const struct clk_parent_data gcc_parent_data_5[] = { 223 { .index = DT_BI_TCXO }, 224 { .hw = &gcc_gpll0.clkr.hw }, 225 { .hw = &gcc_gpll7.clkr.hw }, 226 { .index = DT_SLEEP_CLK }, 227 }; 228 229 static const struct parent_map gcc_parent_map_6[] = { 230 { P_BI_TCXO, 0 }, 231 { P_GCC_GPLL0_OUT_MAIN, 1 }, 232 { P_GCC_GPLL7_OUT_MAIN, 2 }, 233 }; 234 235 static const struct clk_parent_data gcc_parent_data_6[] = { 236 { .index = DT_BI_TCXO }, 237 { .hw = &gcc_gpll0.clkr.hw }, 238 { .hw = &gcc_gpll7.clkr.hw }, 239 }; 240 241 static const struct parent_map gcc_parent_map_7[] = { 242 { P_BI_TCXO, 0 }, 243 { P_GCC_GPLL0_OUT_MAIN, 1 }, 244 { P_GCC_GPLL4_OUT_MAIN, 5 }, 245 { P_GCC_GPLL0_OUT_EVEN, 6 }, 246 }; 247 248 static const struct clk_parent_data gcc_parent_data_7[] = { 249 { .index = DT_BI_TCXO }, 250 { .hw = &gcc_gpll0.clkr.hw }, 251 { .hw = &gcc_gpll4.clkr.hw }, 252 { .hw = &gcc_gpll0_out_even.clkr.hw }, 253 }; 254 255 static const struct parent_map gcc_parent_map_8[] = { 256 { P_BI_TCXO, 0 }, 257 { P_GCC_GPLL0_OUT_MAIN, 1 }, 258 { P_GCC_GPLL7_OUT_MAIN, 2 }, 259 { P_GCC_GPLL0_OUT_EVEN, 6 }, 260 }; 261 262 static const struct clk_parent_data gcc_parent_data_8[] = { 263 { .index = DT_BI_TCXO }, 264 { .hw = &gcc_gpll0.clkr.hw }, 265 { .hw = &gcc_gpll7.clkr.hw }, 266 { .hw = &gcc_gpll0_out_even.clkr.hw }, 267 }; 268 269 static const struct parent_map gcc_parent_map_9[] = { 270 { P_BI_TCXO, 0 }, 271 { P_GCC_GPLL0_OUT_MAIN, 1 }, 272 { P_GCC_GPLL9_OUT_MAIN, 2 }, 273 { P_GCC_GPLL4_OUT_MAIN, 5 }, 274 { P_GCC_GPLL0_OUT_EVEN, 6 }, 275 }; 276 277 static const struct clk_parent_data gcc_parent_data_10[] = { 278 { .index = DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE }, 279 { .index = DT_BI_TCXO }, 280 }; 281 282 static const struct parent_map gcc_parent_map_10[] = { 283 { P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 284 { P_BI_TCXO, 2 }, 285 }; 286 287 static const struct clk_parent_data gcc_parent_data_11[] = { 288 { .index = DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE }, 289 { .index = DT_BI_TCXO }, 290 }; 291 292 static const struct parent_map gcc_parent_map_11[] = { 293 { P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 294 { P_BI_TCXO, 2 }, 295 }; 296 297 static const struct clk_parent_data gcc_parent_data_12[] = { 298 { .index = DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE }, 299 { .index = DT_BI_TCXO }, 300 }; 301 302 static const struct parent_map gcc_parent_map_12[] = { 303 { P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 304 { P_BI_TCXO, 2 }, 305 }; 306 307 static const struct clk_parent_data gcc_parent_data_9[] = { 308 { .index = DT_BI_TCXO }, 309 { .hw = &gcc_gpll0.clkr.hw }, 310 { .hw = &gcc_gpll9.clkr.hw }, 311 { .hw = &gcc_gpll4.clkr.hw }, 312 { .hw = &gcc_gpll0_out_even.clkr.hw }, 313 }; 314 315 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 316 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 317 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 318 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 319 { } 320 }; 321 322 static struct clk_rcg2 gcc_gp1_clk_src = { 323 .cmd_rcgr = 0x64004, 324 .mnd_width = 16, 325 .hid_width = 5, 326 .parent_map = gcc_parent_map_2, 327 .freq_tbl = ftbl_gcc_gp1_clk_src, 328 .clkr.hw.init = &(const struct clk_init_data) { 329 .name = "gcc_gp1_clk_src", 330 .parent_data = gcc_parent_data_2, 331 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 332 .flags = CLK_SET_RATE_PARENT, 333 .ops = &clk_rcg2_shared_ops, 334 }, 335 }; 336 337 static struct clk_rcg2 gcc_gp2_clk_src = { 338 .cmd_rcgr = 0x65004, 339 .mnd_width = 16, 340 .hid_width = 5, 341 .parent_map = gcc_parent_map_2, 342 .freq_tbl = ftbl_gcc_gp1_clk_src, 343 .clkr.hw.init = &(const struct clk_init_data) { 344 .name = "gcc_gp2_clk_src", 345 .parent_data = gcc_parent_data_2, 346 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 347 .flags = CLK_SET_RATE_PARENT, 348 .ops = &clk_rcg2_shared_ops, 349 }, 350 }; 351 352 static struct clk_rcg2 gcc_gp3_clk_src = { 353 .cmd_rcgr = 0x66004, 354 .mnd_width = 16, 355 .hid_width = 5, 356 .parent_map = gcc_parent_map_2, 357 .freq_tbl = ftbl_gcc_gp1_clk_src, 358 .clkr.hw.init = &(const struct clk_init_data) { 359 .name = "gcc_gp3_clk_src", 360 .parent_data = gcc_parent_data_2, 361 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 362 .flags = CLK_SET_RATE_PARENT, 363 .ops = &clk_rcg2_shared_ops, 364 }, 365 }; 366 367 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 368 F(19200000, P_BI_TCXO, 1, 0, 0), 369 { } 370 }; 371 372 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 373 .cmd_rcgr = 0xa0180, 374 .mnd_width = 16, 375 .hid_width = 5, 376 .parent_map = gcc_parent_map_1, 377 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 378 .clkr.hw.init = &(const struct clk_init_data) { 379 .name = "gcc_pcie_0_aux_clk_src", 380 .parent_data = gcc_parent_data_1, 381 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 382 .flags = CLK_SET_RATE_PARENT, 383 .ops = &clk_rcg2_shared_ops, 384 }, 385 }; 386 387 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 388 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 389 { } 390 }; 391 392 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 393 .cmd_rcgr = 0xa0054, 394 .mnd_width = 0, 395 .hid_width = 5, 396 .parent_map = gcc_parent_map_0, 397 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 398 .clkr.hw.init = &(const struct clk_init_data) { 399 .name = "gcc_pcie_0_phy_rchng_clk_src", 400 .parent_data = gcc_parent_data_0, 401 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 402 .flags = CLK_SET_RATE_PARENT, 403 .ops = &clk_rcg2_shared_ops, 404 }, 405 }; 406 407 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 408 .cmd_rcgr = 0x2c180, 409 .mnd_width = 16, 410 .hid_width = 5, 411 .parent_map = gcc_parent_map_1, 412 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 413 .clkr.hw.init = &(const struct clk_init_data) { 414 .name = "gcc_pcie_1_aux_clk_src", 415 .parent_data = gcc_parent_data_1, 416 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 417 .flags = CLK_SET_RATE_PARENT, 418 .ops = &clk_rcg2_shared_ops, 419 }, 420 }; 421 422 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { 423 .cmd_rcgr = 0x2c054, 424 .mnd_width = 0, 425 .hid_width = 5, 426 .parent_map = gcc_parent_map_0, 427 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 428 .clkr.hw.init = &(const struct clk_init_data) { 429 .name = "gcc_pcie_1_phy_rchng_clk_src", 430 .parent_data = gcc_parent_data_0, 431 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 432 .flags = CLK_SET_RATE_PARENT, 433 .ops = &clk_rcg2_shared_ops, 434 }, 435 }; 436 437 static struct clk_rcg2 gcc_pcie_2_aux_clk_src = { 438 .cmd_rcgr = 0x13180, 439 .mnd_width = 16, 440 .hid_width = 5, 441 .parent_map = gcc_parent_map_1, 442 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 443 .clkr.hw.init = &(const struct clk_init_data) { 444 .name = "gcc_pcie_2_aux_clk_src", 445 .parent_data = gcc_parent_data_1, 446 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 447 .flags = CLK_SET_RATE_PARENT, 448 .ops = &clk_rcg2_shared_ops, 449 }, 450 }; 451 452 static struct clk_rcg2 gcc_pcie_2_phy_rchng_clk_src = { 453 .cmd_rcgr = 0x13054, 454 .mnd_width = 0, 455 .hid_width = 5, 456 .parent_map = gcc_parent_map_0, 457 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 458 .clkr.hw.init = &(const struct clk_init_data) { 459 .name = "gcc_pcie_2_phy_rchng_clk_src", 460 .parent_data = gcc_parent_data_0, 461 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 462 .flags = CLK_SET_RATE_PARENT, 463 .ops = &clk_rcg2_shared_ops, 464 }, 465 }; 466 467 static struct clk_rcg2 gcc_pcie_3_aux_clk_src = { 468 .cmd_rcgr = 0x5808c, 469 .mnd_width = 16, 470 .hid_width = 5, 471 .parent_map = gcc_parent_map_1, 472 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 473 .clkr.hw.init = &(const struct clk_init_data) { 474 .name = "gcc_pcie_3_aux_clk_src", 475 .parent_data = gcc_parent_data_1, 476 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 477 .flags = CLK_SET_RATE_PARENT, 478 .ops = &clk_rcg2_shared_ops, 479 }, 480 }; 481 482 static struct clk_rcg2 gcc_pcie_3_phy_rchng_clk_src = { 483 .cmd_rcgr = 0x58070, 484 .mnd_width = 0, 485 .hid_width = 5, 486 .parent_map = gcc_parent_map_0, 487 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 488 .clkr.hw.init = &(const struct clk_init_data) { 489 .name = "gcc_pcie_3_phy_rchng_clk_src", 490 .parent_data = gcc_parent_data_0, 491 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 492 .flags = CLK_SET_RATE_PARENT, 493 .ops = &clk_rcg2_shared_ops, 494 }, 495 }; 496 497 static struct clk_rcg2 gcc_pcie_4_aux_clk_src = { 498 .cmd_rcgr = 0x6b080, 499 .mnd_width = 16, 500 .hid_width = 5, 501 .parent_map = gcc_parent_map_1, 502 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 503 .clkr.hw.init = &(const struct clk_init_data) { 504 .name = "gcc_pcie_4_aux_clk_src", 505 .parent_data = gcc_parent_data_1, 506 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 507 .flags = CLK_SET_RATE_PARENT, 508 .ops = &clk_rcg2_shared_ops, 509 }, 510 }; 511 512 static struct clk_rcg2 gcc_pcie_4_phy_rchng_clk_src = { 513 .cmd_rcgr = 0x6b064, 514 .mnd_width = 0, 515 .hid_width = 5, 516 .parent_map = gcc_parent_map_0, 517 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 518 .clkr.hw.init = &(const struct clk_init_data) { 519 .name = "gcc_pcie_4_phy_rchng_clk_src", 520 .parent_data = gcc_parent_data_0, 521 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 522 .flags = CLK_SET_RATE_PARENT, 523 .ops = &clk_rcg2_shared_ops, 524 }, 525 }; 526 527 static struct clk_rcg2 gcc_pcie_5_aux_clk_src = { 528 .cmd_rcgr = 0x2f080, 529 .mnd_width = 16, 530 .hid_width = 5, 531 .parent_map = gcc_parent_map_1, 532 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 533 .clkr.hw.init = &(const struct clk_init_data) { 534 .name = "gcc_pcie_5_aux_clk_src", 535 .parent_data = gcc_parent_data_1, 536 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 537 .flags = CLK_SET_RATE_PARENT, 538 .ops = &clk_rcg2_shared_ops, 539 }, 540 }; 541 542 static struct clk_rcg2 gcc_pcie_5_phy_rchng_clk_src = { 543 .cmd_rcgr = 0x2f064, 544 .mnd_width = 0, 545 .hid_width = 5, 546 .parent_map = gcc_parent_map_0, 547 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 548 .clkr.hw.init = &(const struct clk_init_data) { 549 .name = "gcc_pcie_5_phy_rchng_clk_src", 550 .parent_data = gcc_parent_data_0, 551 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 552 .flags = CLK_SET_RATE_PARENT, 553 .ops = &clk_rcg2_shared_ops, 554 }, 555 }; 556 557 static struct clk_rcg2 gcc_pcie_6a_aux_clk_src = { 558 .cmd_rcgr = 0x3108c, 559 .mnd_width = 16, 560 .hid_width = 5, 561 .parent_map = gcc_parent_map_1, 562 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 563 .clkr.hw.init = &(const struct clk_init_data) { 564 .name = "gcc_pcie_6a_aux_clk_src", 565 .parent_data = gcc_parent_data_1, 566 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 567 .flags = CLK_SET_RATE_PARENT, 568 .ops = &clk_rcg2_shared_ops, 569 }, 570 }; 571 572 static struct clk_rcg2 gcc_pcie_6a_phy_rchng_clk_src = { 573 .cmd_rcgr = 0x31070, 574 .mnd_width = 0, 575 .hid_width = 5, 576 .parent_map = gcc_parent_map_0, 577 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 578 .clkr.hw.init = &(const struct clk_init_data) { 579 .name = "gcc_pcie_6a_phy_rchng_clk_src", 580 .parent_data = gcc_parent_data_0, 581 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 582 .flags = CLK_SET_RATE_PARENT, 583 .ops = &clk_rcg2_shared_ops, 584 }, 585 }; 586 587 static struct clk_rcg2 gcc_pcie_6b_aux_clk_src = { 588 .cmd_rcgr = 0x8d08c, 589 .mnd_width = 16, 590 .hid_width = 5, 591 .parent_map = gcc_parent_map_1, 592 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 593 .clkr.hw.init = &(const struct clk_init_data) { 594 .name = "gcc_pcie_6b_aux_clk_src", 595 .parent_data = gcc_parent_data_1, 596 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 597 .flags = CLK_SET_RATE_PARENT, 598 .ops = &clk_rcg2_shared_ops, 599 }, 600 }; 601 602 static struct clk_rcg2 gcc_pcie_6b_phy_rchng_clk_src = { 603 .cmd_rcgr = 0x8d070, 604 .mnd_width = 0, 605 .hid_width = 5, 606 .parent_map = gcc_parent_map_0, 607 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 608 .clkr.hw.init = &(const struct clk_init_data) { 609 .name = "gcc_pcie_6b_phy_rchng_clk_src", 610 .parent_data = gcc_parent_data_0, 611 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 612 .flags = CLK_SET_RATE_PARENT, 613 .ops = &clk_rcg2_shared_ops, 614 }, 615 }; 616 617 static struct clk_rcg2 gcc_pcie_rscc_xo_clk_src = { 618 .cmd_rcgr = 0xa400c, 619 .mnd_width = 0, 620 .hid_width = 5, 621 .parent_map = gcc_parent_map_3, 622 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 623 .clkr.hw.init = &(const struct clk_init_data) { 624 .name = "gcc_pcie_rscc_xo_clk_src", 625 .parent_data = gcc_parent_data_3, 626 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 627 .flags = CLK_SET_RATE_PARENT, 628 .ops = &clk_rcg2_shared_ops, 629 }, 630 }; 631 632 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 633 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 634 { } 635 }; 636 637 static struct clk_rcg2 gcc_pdm2_clk_src = { 638 .cmd_rcgr = 0x33010, 639 .mnd_width = 0, 640 .hid_width = 5, 641 .parent_map = gcc_parent_map_0, 642 .freq_tbl = ftbl_gcc_pdm2_clk_src, 643 .clkr.hw.init = &(const struct clk_init_data) { 644 .name = "gcc_pdm2_clk_src", 645 .parent_data = gcc_parent_data_0, 646 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 647 .flags = CLK_SET_RATE_PARENT, 648 .ops = &clk_rcg2_shared_ops, 649 }, 650 }; 651 652 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 653 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 654 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 655 F(19200000, P_BI_TCXO, 1, 0, 0), 656 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 657 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 658 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 659 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 660 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 661 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 662 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 663 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 664 { } 665 }; 666 667 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 668 .name = "gcc_qupv3_wrap0_s0_clk_src", 669 .parent_data = gcc_parent_data_0, 670 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 671 .flags = CLK_SET_RATE_PARENT, 672 .ops = &clk_rcg2_shared_ops, 673 }; 674 675 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 676 .cmd_rcgr = 0x42010, 677 .mnd_width = 16, 678 .hid_width = 5, 679 .parent_map = gcc_parent_map_0, 680 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 681 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 682 }; 683 684 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 685 .name = "gcc_qupv3_wrap0_s1_clk_src", 686 .parent_data = gcc_parent_data_0, 687 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 688 .flags = CLK_SET_RATE_PARENT, 689 .ops = &clk_rcg2_shared_ops, 690 }; 691 692 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 693 .cmd_rcgr = 0x42148, 694 .mnd_width = 16, 695 .hid_width = 5, 696 .parent_map = gcc_parent_map_0, 697 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 698 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 699 }; 700 701 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = { 702 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 703 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 704 F(19200000, P_BI_TCXO, 1, 0, 0), 705 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 706 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 707 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 708 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 709 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 710 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 711 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 712 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 713 { } 714 }; 715 716 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 717 .name = "gcc_qupv3_wrap0_s2_clk_src", 718 .parent_data = gcc_parent_data_0, 719 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 720 .flags = CLK_SET_RATE_PARENT, 721 .ops = &clk_rcg2_shared_ops, 722 }; 723 724 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 725 .cmd_rcgr = 0x42288, 726 .mnd_width = 16, 727 .hid_width = 5, 728 .parent_map = gcc_parent_map_0, 729 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 730 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 731 }; 732 733 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 734 .name = "gcc_qupv3_wrap0_s3_clk_src", 735 .parent_data = gcc_parent_data_0, 736 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 737 .flags = CLK_SET_RATE_PARENT, 738 .ops = &clk_rcg2_shared_ops, 739 }; 740 741 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 742 .cmd_rcgr = 0x423c8, 743 .mnd_width = 16, 744 .hid_width = 5, 745 .parent_map = gcc_parent_map_0, 746 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 747 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 748 }; 749 750 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s4_clk_src[] = { 751 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 752 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 753 F(19200000, P_BI_TCXO, 1, 0, 0), 754 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 755 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 756 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 757 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 758 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 759 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 760 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 761 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 762 { } 763 }; 764 765 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 766 .name = "gcc_qupv3_wrap0_s4_clk_src", 767 .parent_data = gcc_parent_data_0, 768 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 769 .flags = CLK_SET_RATE_PARENT, 770 .ops = &clk_rcg2_shared_ops, 771 }; 772 773 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 774 .cmd_rcgr = 0x42500, 775 .mnd_width = 16, 776 .hid_width = 5, 777 .parent_map = gcc_parent_map_0, 778 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 779 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 780 }; 781 782 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 783 .name = "gcc_qupv3_wrap0_s5_clk_src", 784 .parent_data = gcc_parent_data_0, 785 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 786 .flags = CLK_SET_RATE_PARENT, 787 .ops = &clk_rcg2_shared_ops, 788 }; 789 790 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 791 .cmd_rcgr = 0x42638, 792 .mnd_width = 16, 793 .hid_width = 5, 794 .parent_map = gcc_parent_map_0, 795 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 796 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 797 }; 798 799 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 800 .name = "gcc_qupv3_wrap0_s6_clk_src", 801 .parent_data = gcc_parent_data_0, 802 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 803 .flags = CLK_SET_RATE_PARENT, 804 .ops = &clk_rcg2_shared_ops, 805 }; 806 807 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 808 .cmd_rcgr = 0x42770, 809 .mnd_width = 16, 810 .hid_width = 5, 811 .parent_map = gcc_parent_map_0, 812 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 813 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 814 }; 815 816 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 817 .name = "gcc_qupv3_wrap0_s7_clk_src", 818 .parent_data = gcc_parent_data_0, 819 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 820 .flags = CLK_SET_RATE_PARENT, 821 .ops = &clk_rcg2_shared_ops, 822 }; 823 824 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 825 .cmd_rcgr = 0x428a8, 826 .mnd_width = 16, 827 .hid_width = 5, 828 .parent_map = gcc_parent_map_0, 829 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 830 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 831 }; 832 833 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 834 .name = "gcc_qupv3_wrap1_s0_clk_src", 835 .parent_data = gcc_parent_data_0, 836 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 837 .flags = CLK_SET_RATE_PARENT, 838 .ops = &clk_rcg2_shared_ops, 839 }; 840 841 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 842 .cmd_rcgr = 0x18010, 843 .mnd_width = 16, 844 .hid_width = 5, 845 .parent_map = gcc_parent_map_0, 846 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 847 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 848 }; 849 850 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 851 .name = "gcc_qupv3_wrap1_s1_clk_src", 852 .parent_data = gcc_parent_data_0, 853 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 854 .flags = CLK_SET_RATE_PARENT, 855 .ops = &clk_rcg2_shared_ops, 856 }; 857 858 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 859 .cmd_rcgr = 0x18148, 860 .mnd_width = 16, 861 .hid_width = 5, 862 .parent_map = gcc_parent_map_0, 863 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 864 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 865 }; 866 867 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 868 .name = "gcc_qupv3_wrap1_s2_clk_src", 869 .parent_data = gcc_parent_data_0, 870 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 871 .flags = CLK_SET_RATE_PARENT, 872 .ops = &clk_rcg2_shared_ops, 873 }; 874 875 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 876 .cmd_rcgr = 0x18288, 877 .mnd_width = 16, 878 .hid_width = 5, 879 .parent_map = gcc_parent_map_0, 880 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 881 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 882 }; 883 884 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 885 .name = "gcc_qupv3_wrap1_s3_clk_src", 886 .parent_data = gcc_parent_data_0, 887 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 888 .flags = CLK_SET_RATE_PARENT, 889 .ops = &clk_rcg2_shared_ops, 890 }; 891 892 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 893 .cmd_rcgr = 0x183c8, 894 .mnd_width = 16, 895 .hid_width = 5, 896 .parent_map = gcc_parent_map_0, 897 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 898 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 899 }; 900 901 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 902 .name = "gcc_qupv3_wrap1_s4_clk_src", 903 .parent_data = gcc_parent_data_0, 904 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 905 .flags = CLK_SET_RATE_PARENT, 906 .ops = &clk_rcg2_shared_ops, 907 }; 908 909 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 910 .cmd_rcgr = 0x18500, 911 .mnd_width = 16, 912 .hid_width = 5, 913 .parent_map = gcc_parent_map_0, 914 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 915 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 916 }; 917 918 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 919 .name = "gcc_qupv3_wrap1_s5_clk_src", 920 .parent_data = gcc_parent_data_0, 921 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 922 .flags = CLK_SET_RATE_PARENT, 923 .ops = &clk_rcg2_shared_ops, 924 }; 925 926 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 927 .cmd_rcgr = 0x18638, 928 .mnd_width = 16, 929 .hid_width = 5, 930 .parent_map = gcc_parent_map_0, 931 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 932 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 933 }; 934 935 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 936 .name = "gcc_qupv3_wrap1_s6_clk_src", 937 .parent_data = gcc_parent_data_0, 938 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 939 .flags = CLK_SET_RATE_PARENT, 940 .ops = &clk_rcg2_shared_ops, 941 }; 942 943 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 944 .cmd_rcgr = 0x18770, 945 .mnd_width = 16, 946 .hid_width = 5, 947 .parent_map = gcc_parent_map_0, 948 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 949 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 950 }; 951 952 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 953 .name = "gcc_qupv3_wrap1_s7_clk_src", 954 .parent_data = gcc_parent_data_0, 955 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 956 .flags = CLK_SET_RATE_PARENT, 957 .ops = &clk_rcg2_shared_ops, 958 }; 959 960 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 961 .cmd_rcgr = 0x188a8, 962 .mnd_width = 16, 963 .hid_width = 5, 964 .parent_map = gcc_parent_map_0, 965 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 966 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 967 }; 968 969 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 970 .name = "gcc_qupv3_wrap2_s0_clk_src", 971 .parent_data = gcc_parent_data_0, 972 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 973 .flags = CLK_SET_RATE_PARENT, 974 .ops = &clk_rcg2_shared_ops, 975 }; 976 977 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 978 .cmd_rcgr = 0x1e010, 979 .mnd_width = 16, 980 .hid_width = 5, 981 .parent_map = gcc_parent_map_0, 982 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 983 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 984 }; 985 986 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 987 .name = "gcc_qupv3_wrap2_s1_clk_src", 988 .parent_data = gcc_parent_data_0, 989 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 990 .flags = CLK_SET_RATE_PARENT, 991 .ops = &clk_rcg2_shared_ops, 992 }; 993 994 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 995 .cmd_rcgr = 0x1e148, 996 .mnd_width = 16, 997 .hid_width = 5, 998 .parent_map = gcc_parent_map_0, 999 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1000 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 1001 }; 1002 1003 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 1004 .name = "gcc_qupv3_wrap2_s2_clk_src", 1005 .parent_data = gcc_parent_data_0, 1006 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1007 .flags = CLK_SET_RATE_PARENT, 1008 .ops = &clk_rcg2_shared_ops, 1009 }; 1010 1011 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 1012 .cmd_rcgr = 0x1e288, 1013 .mnd_width = 16, 1014 .hid_width = 5, 1015 .parent_map = gcc_parent_map_0, 1016 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1017 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, 1018 }; 1019 1020 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 1021 .name = "gcc_qupv3_wrap2_s3_clk_src", 1022 .parent_data = gcc_parent_data_0, 1023 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1024 .flags = CLK_SET_RATE_PARENT, 1025 .ops = &clk_rcg2_shared_ops, 1026 }; 1027 1028 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 1029 .cmd_rcgr = 0x1e3c8, 1030 .mnd_width = 16, 1031 .hid_width = 5, 1032 .parent_map = gcc_parent_map_0, 1033 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1034 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, 1035 }; 1036 1037 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 1038 .name = "gcc_qupv3_wrap2_s4_clk_src", 1039 .parent_data = gcc_parent_data_0, 1040 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1041 .flags = CLK_SET_RATE_PARENT, 1042 .ops = &clk_rcg2_shared_ops, 1043 }; 1044 1045 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 1046 .cmd_rcgr = 0x1e500, 1047 .mnd_width = 16, 1048 .hid_width = 5, 1049 .parent_map = gcc_parent_map_0, 1050 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 1051 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 1052 }; 1053 1054 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { 1055 .name = "gcc_qupv3_wrap2_s5_clk_src", 1056 .parent_data = gcc_parent_data_0, 1057 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1058 .flags = CLK_SET_RATE_PARENT, 1059 .ops = &clk_rcg2_shared_ops, 1060 }; 1061 1062 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { 1063 .cmd_rcgr = 0x1e638, 1064 .mnd_width = 16, 1065 .hid_width = 5, 1066 .parent_map = gcc_parent_map_0, 1067 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 1068 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, 1069 }; 1070 1071 static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = { 1072 .name = "gcc_qupv3_wrap2_s6_clk_src", 1073 .parent_data = gcc_parent_data_8, 1074 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 1075 .flags = CLK_SET_RATE_PARENT, 1076 .ops = &clk_rcg2_shared_ops, 1077 }; 1078 1079 static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { 1080 .cmd_rcgr = 0x1e770, 1081 .mnd_width = 16, 1082 .hid_width = 5, 1083 .parent_map = gcc_parent_map_8, 1084 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 1085 .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init, 1086 }; 1087 1088 static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = { 1089 .name = "gcc_qupv3_wrap2_s7_clk_src", 1090 .parent_data = gcc_parent_data_0, 1091 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1092 .flags = CLK_SET_RATE_PARENT, 1093 .ops = &clk_rcg2_shared_ops, 1094 }; 1095 1096 static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = { 1097 .cmd_rcgr = 0x1e8a8, 1098 .mnd_width = 16, 1099 .hid_width = 5, 1100 .parent_map = gcc_parent_map_0, 1101 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 1102 .clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init, 1103 }; 1104 1105 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1106 F(400000, P_BI_TCXO, 12, 1, 4), 1107 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1108 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 1109 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1110 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), 1111 { } 1112 }; 1113 1114 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1115 .cmd_rcgr = 0x14018, 1116 .mnd_width = 8, 1117 .hid_width = 5, 1118 .parent_map = gcc_parent_map_9, 1119 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1120 .clkr.hw.init = &(const struct clk_init_data) { 1121 .name = "gcc_sdcc2_apps_clk_src", 1122 .parent_data = gcc_parent_data_9, 1123 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 1124 .flags = CLK_SET_RATE_PARENT, 1125 .ops = &clk_rcg2_floor_ops, 1126 }, 1127 }; 1128 1129 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 1130 F(400000, P_BI_TCXO, 12, 1, 4), 1131 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1132 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1133 { } 1134 }; 1135 1136 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 1137 .cmd_rcgr = 0x16018, 1138 .mnd_width = 8, 1139 .hid_width = 5, 1140 .parent_map = gcc_parent_map_0, 1141 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 1142 .clkr.hw.init = &(const struct clk_init_data) { 1143 .name = "gcc_sdcc4_apps_clk_src", 1144 .parent_data = gcc_parent_data_0, 1145 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1146 .flags = CLK_SET_RATE_PARENT, 1147 .ops = &clk_rcg2_floor_ops, 1148 }, 1149 }; 1150 1151 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 1152 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1153 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1154 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 1155 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 1156 { } 1157 }; 1158 1159 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1160 .cmd_rcgr = 0x77030, 1161 .mnd_width = 8, 1162 .hid_width = 5, 1163 .parent_map = gcc_parent_map_0, 1164 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 1165 .clkr.hw.init = &(const struct clk_init_data) { 1166 .name = "gcc_ufs_phy_axi_clk_src", 1167 .parent_data = gcc_parent_data_0, 1168 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1169 .flags = CLK_SET_RATE_PARENT, 1170 .ops = &clk_rcg2_shared_ops, 1171 }, 1172 }; 1173 1174 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1175 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1176 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), 1177 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 1178 { } 1179 }; 1180 1181 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1182 .cmd_rcgr = 0x77080, 1183 .mnd_width = 0, 1184 .hid_width = 5, 1185 .parent_map = gcc_parent_map_7, 1186 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1187 .clkr.hw.init = &(const struct clk_init_data) { 1188 .name = "gcc_ufs_phy_ice_core_clk_src", 1189 .parent_data = gcc_parent_data_7, 1190 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 1191 .flags = CLK_SET_RATE_PARENT, 1192 .ops = &clk_rcg2_shared_ops, 1193 }, 1194 }; 1195 1196 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1197 .cmd_rcgr = 0x770b4, 1198 .mnd_width = 0, 1199 .hid_width = 5, 1200 .parent_map = gcc_parent_map_3, 1201 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1202 .clkr.hw.init = &(const struct clk_init_data) { 1203 .name = "gcc_ufs_phy_phy_aux_clk_src", 1204 .parent_data = gcc_parent_data_3, 1205 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1206 .flags = CLK_SET_RATE_PARENT, 1207 .ops = &clk_rcg2_shared_ops, 1208 }, 1209 }; 1210 1211 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { 1212 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1213 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 1214 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 1215 { } 1216 }; 1217 1218 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1219 .cmd_rcgr = 0x77098, 1220 .mnd_width = 0, 1221 .hid_width = 5, 1222 .parent_map = gcc_parent_map_0, 1223 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, 1224 .clkr.hw.init = &(const struct clk_init_data) { 1225 .name = "gcc_ufs_phy_unipro_core_clk_src", 1226 .parent_data = gcc_parent_data_0, 1227 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1228 .flags = CLK_SET_RATE_PARENT, 1229 .ops = &clk_rcg2_shared_ops, 1230 }, 1231 }; 1232 1233 static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = { 1234 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 1235 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 1236 { } 1237 }; 1238 1239 static struct clk_rcg2 gcc_usb20_master_clk_src = { 1240 .cmd_rcgr = 0x2902c, 1241 .mnd_width = 8, 1242 .hid_width = 5, 1243 .parent_map = gcc_parent_map_0, 1244 .freq_tbl = ftbl_gcc_usb20_master_clk_src, 1245 .clkr.hw.init = &(const struct clk_init_data) { 1246 .name = "gcc_usb20_master_clk_src", 1247 .parent_data = gcc_parent_data_0, 1248 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1249 .flags = CLK_SET_RATE_PARENT, 1250 .ops = &clk_rcg2_shared_ops, 1251 }, 1252 }; 1253 1254 static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = { 1255 .cmd_rcgr = 0x29158, 1256 .mnd_width = 0, 1257 .hid_width = 5, 1258 .parent_map = gcc_parent_map_0, 1259 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1260 .clkr.hw.init = &(const struct clk_init_data) { 1261 .name = "gcc_usb20_mock_utmi_clk_src", 1262 .parent_data = gcc_parent_data_0, 1263 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1264 .flags = CLK_SET_RATE_PARENT, 1265 .ops = &clk_rcg2_shared_ops, 1266 }, 1267 }; 1268 1269 static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = { 1270 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), 1271 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 1272 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1273 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 1274 { } 1275 }; 1276 1277 static struct clk_rcg2 gcc_usb30_mp_master_clk_src = { 1278 .cmd_rcgr = 0x1702c, 1279 .mnd_width = 8, 1280 .hid_width = 5, 1281 .parent_map = gcc_parent_map_0, 1282 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 1283 .clkr.hw.init = &(const struct clk_init_data) { 1284 .name = "gcc_usb30_mp_master_clk_src", 1285 .parent_data = gcc_parent_data_0, 1286 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1287 .flags = CLK_SET_RATE_PARENT, 1288 .ops = &clk_rcg2_shared_ops, 1289 }, 1290 }; 1291 1292 static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = { 1293 .cmd_rcgr = 0x17158, 1294 .mnd_width = 0, 1295 .hid_width = 5, 1296 .parent_map = gcc_parent_map_0, 1297 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1298 .clkr.hw.init = &(const struct clk_init_data) { 1299 .name = "gcc_usb30_mp_mock_utmi_clk_src", 1300 .parent_data = gcc_parent_data_0, 1301 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1302 .flags = CLK_SET_RATE_PARENT, 1303 .ops = &clk_rcg2_shared_ops, 1304 }, 1305 }; 1306 1307 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1308 .cmd_rcgr = 0x3902c, 1309 .mnd_width = 8, 1310 .hid_width = 5, 1311 .parent_map = gcc_parent_map_0, 1312 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 1313 .clkr.hw.init = &(const struct clk_init_data) { 1314 .name = "gcc_usb30_prim_master_clk_src", 1315 .parent_data = gcc_parent_data_0, 1316 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1317 .flags = CLK_SET_RATE_PARENT, 1318 .ops = &clk_rcg2_shared_ops, 1319 }, 1320 }; 1321 1322 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1323 .cmd_rcgr = 0x39044, 1324 .mnd_width = 0, 1325 .hid_width = 5, 1326 .parent_map = gcc_parent_map_0, 1327 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1328 .clkr.hw.init = &(const struct clk_init_data) { 1329 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1330 .parent_data = gcc_parent_data_0, 1331 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1332 .flags = CLK_SET_RATE_PARENT, 1333 .ops = &clk_rcg2_shared_ops, 1334 }, 1335 }; 1336 1337 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { 1338 .cmd_rcgr = 0xa102c, 1339 .mnd_width = 8, 1340 .hid_width = 5, 1341 .parent_map = gcc_parent_map_0, 1342 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 1343 .clkr.hw.init = &(const struct clk_init_data) { 1344 .name = "gcc_usb30_sec_master_clk_src", 1345 .parent_data = gcc_parent_data_0, 1346 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1347 .flags = CLK_SET_RATE_PARENT, 1348 .ops = &clk_rcg2_shared_ops, 1349 }, 1350 }; 1351 1352 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { 1353 .cmd_rcgr = 0xa1044, 1354 .mnd_width = 0, 1355 .hid_width = 5, 1356 .parent_map = gcc_parent_map_0, 1357 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1358 .clkr.hw.init = &(const struct clk_init_data) { 1359 .name = "gcc_usb30_sec_mock_utmi_clk_src", 1360 .parent_data = gcc_parent_data_0, 1361 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1362 .flags = CLK_SET_RATE_PARENT, 1363 .ops = &clk_rcg2_shared_ops, 1364 }, 1365 }; 1366 1367 static struct clk_rcg2 gcc_usb30_tert_master_clk_src = { 1368 .cmd_rcgr = 0xa202c, 1369 .mnd_width = 8, 1370 .hid_width = 5, 1371 .parent_map = gcc_parent_map_0, 1372 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 1373 .clkr.hw.init = &(const struct clk_init_data) { 1374 .name = "gcc_usb30_tert_master_clk_src", 1375 .parent_data = gcc_parent_data_0, 1376 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1377 .flags = CLK_SET_RATE_PARENT, 1378 .ops = &clk_rcg2_shared_ops, 1379 }, 1380 }; 1381 1382 static struct clk_rcg2 gcc_usb30_tert_mock_utmi_clk_src = { 1383 .cmd_rcgr = 0xa2044, 1384 .mnd_width = 0, 1385 .hid_width = 5, 1386 .parent_map = gcc_parent_map_0, 1387 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1388 .clkr.hw.init = &(const struct clk_init_data) { 1389 .name = "gcc_usb30_tert_mock_utmi_clk_src", 1390 .parent_data = gcc_parent_data_0, 1391 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1392 .flags = CLK_SET_RATE_PARENT, 1393 .ops = &clk_rcg2_shared_ops, 1394 }, 1395 }; 1396 1397 static struct clk_rcg2 gcc_usb3_mp_phy_aux_clk_src = { 1398 .cmd_rcgr = 0x172a0, 1399 .mnd_width = 0, 1400 .hid_width = 5, 1401 .parent_map = gcc_parent_map_1, 1402 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1403 .clkr.hw.init = &(const struct clk_init_data) { 1404 .name = "gcc_usb3_mp_phy_aux_clk_src", 1405 .parent_data = gcc_parent_data_1, 1406 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1407 .flags = CLK_SET_RATE_PARENT, 1408 .ops = &clk_rcg2_shared_ops, 1409 }, 1410 }; 1411 1412 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1413 .cmd_rcgr = 0x39074, 1414 .mnd_width = 0, 1415 .hid_width = 5, 1416 .parent_map = gcc_parent_map_1, 1417 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1418 .clkr.hw.init = &(const struct clk_init_data) { 1419 .name = "gcc_usb3_prim_phy_aux_clk_src", 1420 .parent_data = gcc_parent_data_1, 1421 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1422 .flags = CLK_SET_RATE_PARENT, 1423 .ops = &clk_rcg2_shared_ops, 1424 }, 1425 }; 1426 1427 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { 1428 .cmd_rcgr = 0xa1074, 1429 .mnd_width = 0, 1430 .hid_width = 5, 1431 .parent_map = gcc_parent_map_1, 1432 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1433 .clkr.hw.init = &(const struct clk_init_data) { 1434 .name = "gcc_usb3_sec_phy_aux_clk_src", 1435 .parent_data = gcc_parent_data_1, 1436 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1437 .flags = CLK_SET_RATE_PARENT, 1438 .ops = &clk_rcg2_shared_ops, 1439 }, 1440 }; 1441 1442 static struct clk_rcg2 gcc_usb3_tert_phy_aux_clk_src = { 1443 .cmd_rcgr = 0xa2074, 1444 .mnd_width = 0, 1445 .hid_width = 5, 1446 .parent_map = gcc_parent_map_1, 1447 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1448 .clkr.hw.init = &(const struct clk_init_data) { 1449 .name = "gcc_usb3_tert_phy_aux_clk_src", 1450 .parent_data = gcc_parent_data_1, 1451 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1452 .flags = CLK_SET_RATE_PARENT, 1453 .ops = &clk_rcg2_shared_ops, 1454 }, 1455 }; 1456 1457 static const struct freq_tbl ftbl_gcc_usb4_0_master_clk_src[] = { 1458 F(85714286, P_GCC_GPLL0_OUT_EVEN, 3.5, 0, 0), 1459 F(175000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0), 1460 F(350000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0), 1461 { } 1462 }; 1463 1464 static struct clk_rcg2 gcc_usb4_0_master_clk_src = { 1465 .cmd_rcgr = 0x9f024, 1466 .mnd_width = 8, 1467 .hid_width = 5, 1468 .parent_map = gcc_parent_map_4, 1469 .freq_tbl = ftbl_gcc_usb4_0_master_clk_src, 1470 .clkr.hw.init = &(const struct clk_init_data) { 1471 .name = "gcc_usb4_0_master_clk_src", 1472 .parent_data = gcc_parent_data_4, 1473 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1474 .flags = CLK_SET_RATE_PARENT, 1475 .ops = &clk_rcg2_shared_ops, 1476 }, 1477 }; 1478 1479 static const struct freq_tbl ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src[] = { 1480 F(19200000, P_BI_TCXO, 1, 0, 0), 1481 F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0), 1482 F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0), 1483 { } 1484 }; 1485 1486 static struct clk_rcg2 gcc_usb4_0_phy_pcie_pipe_clk_src = { 1487 .cmd_rcgr = 0x9f0e8, 1488 .mnd_width = 0, 1489 .hid_width = 5, 1490 .parent_map = gcc_parent_map_5, 1491 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src, 1492 .clkr.hw.init = &(const struct clk_init_data) { 1493 .name = "gcc_usb4_0_phy_pcie_pipe_clk_src", 1494 .parent_data = gcc_parent_data_5, 1495 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1496 .flags = CLK_SET_RATE_PARENT, 1497 .ops = &clk_rcg2_shared_ops, 1498 }, 1499 }; 1500 1501 static struct clk_rcg2 gcc_usb4_0_sb_if_clk_src = { 1502 .cmd_rcgr = 0x9f08c, 1503 .mnd_width = 0, 1504 .hid_width = 5, 1505 .parent_map = gcc_parent_map_3, 1506 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1507 .clkr.hw.init = &(const struct clk_init_data) { 1508 .name = "gcc_usb4_0_sb_if_clk_src", 1509 .parent_data = gcc_parent_data_3, 1510 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1511 .flags = CLK_SET_RATE_PARENT, 1512 .ops = &clk_rcg2_shared_ops, 1513 }, 1514 }; 1515 1516 static const struct freq_tbl ftbl_gcc_usb4_0_tmu_clk_src[] = { 1517 F(19200000, P_BI_TCXO, 1, 0, 0), 1518 F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0), 1519 { } 1520 }; 1521 1522 static struct clk_rcg2 gcc_usb4_0_tmu_clk_src = { 1523 .cmd_rcgr = 0x9f070, 1524 .mnd_width = 0, 1525 .hid_width = 5, 1526 .parent_map = gcc_parent_map_6, 1527 .freq_tbl = ftbl_gcc_usb4_0_tmu_clk_src, 1528 .clkr.hw.init = &(const struct clk_init_data) { 1529 .name = "gcc_usb4_0_tmu_clk_src", 1530 .parent_data = gcc_parent_data_6, 1531 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 1532 .flags = CLK_SET_RATE_PARENT, 1533 .ops = &clk_rcg2_shared_ops, 1534 }, 1535 }; 1536 1537 static struct clk_rcg2 gcc_usb4_1_master_clk_src = { 1538 .cmd_rcgr = 0x2b024, 1539 .mnd_width = 8, 1540 .hid_width = 5, 1541 .parent_map = gcc_parent_map_4, 1542 .freq_tbl = ftbl_gcc_usb4_0_master_clk_src, 1543 .clkr.hw.init = &(const struct clk_init_data) { 1544 .name = "gcc_usb4_1_master_clk_src", 1545 .parent_data = gcc_parent_data_4, 1546 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1547 .flags = CLK_SET_RATE_PARENT, 1548 .ops = &clk_rcg2_shared_ops, 1549 }, 1550 }; 1551 1552 static struct clk_rcg2 gcc_usb4_1_phy_pcie_pipe_clk_src = { 1553 .cmd_rcgr = 0x2b0e8, 1554 .mnd_width = 0, 1555 .hid_width = 5, 1556 .parent_map = gcc_parent_map_5, 1557 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src, 1558 .clkr.hw.init = &(const struct clk_init_data) { 1559 .name = "gcc_usb4_1_phy_pcie_pipe_clk_src", 1560 .parent_data = gcc_parent_data_5, 1561 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1562 .flags = CLK_SET_RATE_PARENT, 1563 .ops = &clk_rcg2_shared_ops, 1564 }, 1565 }; 1566 1567 static struct clk_rcg2 gcc_usb4_1_sb_if_clk_src = { 1568 .cmd_rcgr = 0x2b08c, 1569 .mnd_width = 0, 1570 .hid_width = 5, 1571 .parent_map = gcc_parent_map_3, 1572 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1573 .clkr.hw.init = &(const struct clk_init_data) { 1574 .name = "gcc_usb4_1_sb_if_clk_src", 1575 .parent_data = gcc_parent_data_3, 1576 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1577 .flags = CLK_SET_RATE_PARENT, 1578 .ops = &clk_rcg2_shared_ops, 1579 }, 1580 }; 1581 1582 static struct clk_rcg2 gcc_usb4_1_tmu_clk_src = { 1583 .cmd_rcgr = 0x2b070, 1584 .mnd_width = 0, 1585 .hid_width = 5, 1586 .parent_map = gcc_parent_map_6, 1587 .freq_tbl = ftbl_gcc_usb4_0_tmu_clk_src, 1588 .clkr.hw.init = &(const struct clk_init_data) { 1589 .name = "gcc_usb4_1_tmu_clk_src", 1590 .parent_data = gcc_parent_data_6, 1591 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 1592 .flags = CLK_SET_RATE_PARENT, 1593 .ops = &clk_rcg2_shared_ops, 1594 }, 1595 }; 1596 1597 static struct clk_rcg2 gcc_usb4_2_master_clk_src = { 1598 .cmd_rcgr = 0x11024, 1599 .mnd_width = 8, 1600 .hid_width = 5, 1601 .parent_map = gcc_parent_map_4, 1602 .freq_tbl = ftbl_gcc_usb4_0_master_clk_src, 1603 .clkr.hw.init = &(const struct clk_init_data) { 1604 .name = "gcc_usb4_2_master_clk_src", 1605 .parent_data = gcc_parent_data_4, 1606 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1607 .flags = CLK_SET_RATE_PARENT, 1608 .ops = &clk_rcg2_shared_ops, 1609 }, 1610 }; 1611 1612 static struct clk_rcg2 gcc_usb4_2_phy_pcie_pipe_clk_src = { 1613 .cmd_rcgr = 0x110e8, 1614 .mnd_width = 0, 1615 .hid_width = 5, 1616 .parent_map = gcc_parent_map_5, 1617 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src, 1618 .clkr.hw.init = &(const struct clk_init_data) { 1619 .name = "gcc_usb4_2_phy_pcie_pipe_clk_src", 1620 .parent_data = gcc_parent_data_5, 1621 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1622 .flags = CLK_SET_RATE_PARENT, 1623 .ops = &clk_rcg2_shared_ops, 1624 }, 1625 }; 1626 1627 static struct clk_rcg2 gcc_usb4_2_sb_if_clk_src = { 1628 .cmd_rcgr = 0x1108c, 1629 .mnd_width = 0, 1630 .hid_width = 5, 1631 .parent_map = gcc_parent_map_3, 1632 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1633 .clkr.hw.init = &(const struct clk_init_data) { 1634 .name = "gcc_usb4_2_sb_if_clk_src", 1635 .parent_data = gcc_parent_data_3, 1636 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1637 .flags = CLK_SET_RATE_PARENT, 1638 .ops = &clk_rcg2_shared_ops, 1639 }, 1640 }; 1641 1642 static struct clk_rcg2 gcc_usb4_2_tmu_clk_src = { 1643 .cmd_rcgr = 0x11070, 1644 .mnd_width = 0, 1645 .hid_width = 5, 1646 .parent_map = gcc_parent_map_6, 1647 .freq_tbl = ftbl_gcc_usb4_0_tmu_clk_src, 1648 .clkr.hw.init = &(const struct clk_init_data) { 1649 .name = "gcc_usb4_2_tmu_clk_src", 1650 .parent_data = gcc_parent_data_6, 1651 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 1652 .flags = CLK_SET_RATE_PARENT, 1653 .ops = &clk_rcg2_shared_ops, 1654 }, 1655 }; 1656 1657 static struct clk_regmap_phy_mux gcc_pcie_3_pipe_clk_src = { 1658 .reg = 0x58088, 1659 .clkr = { 1660 .hw.init = &(struct clk_init_data){ 1661 .name = "gcc_pcie_3_pipe_clk_src", 1662 .parent_data = &(const struct clk_parent_data){ 1663 .index = DT_PCIE_3_PIPE, 1664 }, 1665 .num_parents = 1, 1666 .ops = &clk_regmap_phy_mux_ops, 1667 }, 1668 }, 1669 }; 1670 1671 static struct clk_regmap_div gcc_pcie_3_pipe_div_clk_src = { 1672 .reg = 0x5806c, 1673 .shift = 0, 1674 .width = 4, 1675 .clkr.hw.init = &(const struct clk_init_data) { 1676 .name = "gcc_pcie_3_pipe_div_clk_src", 1677 .parent_hws = (const struct clk_hw*[]) { 1678 &gcc_pcie_3_pipe_clk_src.clkr.hw, 1679 }, 1680 .num_parents = 1, 1681 .ops = &clk_regmap_div_ro_ops, 1682 }, 1683 }; 1684 1685 static struct clk_regmap_phy_mux gcc_pcie_4_pipe_clk_src = { 1686 .reg = 0x6b07c, 1687 .clkr = { 1688 .hw.init = &(struct clk_init_data){ 1689 .name = "gcc_pcie_4_pipe_clk_src", 1690 .parent_data = &(const struct clk_parent_data){ 1691 .index = DT_PCIE_4_PIPE, 1692 }, 1693 .num_parents = 1, 1694 .ops = &clk_regmap_phy_mux_ops, 1695 }, 1696 }, 1697 }; 1698 1699 static struct clk_regmap_div gcc_pcie_4_pipe_div_clk_src = { 1700 .reg = 0x6b060, 1701 .shift = 0, 1702 .width = 4, 1703 .clkr.hw.init = &(const struct clk_init_data) { 1704 .name = "gcc_pcie_4_pipe_div_clk_src", 1705 .parent_hws = (const struct clk_hw*[]) { 1706 &gcc_pcie_4_pipe_clk_src.clkr.hw, 1707 }, 1708 .num_parents = 1, 1709 .ops = &clk_regmap_div_ro_ops, 1710 }, 1711 }; 1712 1713 static struct clk_regmap_phy_mux gcc_pcie_5_pipe_clk_src = { 1714 .reg = 0x2f07c, 1715 .clkr = { 1716 .hw.init = &(struct clk_init_data){ 1717 .name = "gcc_pcie_5_pipe_clk_src", 1718 .parent_data = &(const struct clk_parent_data){ 1719 .index = DT_PCIE_5_PIPE, 1720 }, 1721 .num_parents = 1, 1722 .ops = &clk_regmap_phy_mux_ops, 1723 }, 1724 }, 1725 }; 1726 1727 static struct clk_regmap_div gcc_pcie_5_pipe_div_clk_src = { 1728 .reg = 0x2f060, 1729 .shift = 0, 1730 .width = 4, 1731 .clkr.hw.init = &(const struct clk_init_data) { 1732 .name = "gcc_pcie_5_pipe_div_clk_src", 1733 .parent_hws = (const struct clk_hw*[]) { 1734 &gcc_pcie_5_pipe_clk_src.clkr.hw, 1735 }, 1736 .num_parents = 1, 1737 .ops = &clk_regmap_div_ro_ops, 1738 }, 1739 }; 1740 1741 static struct clk_regmap_phy_mux gcc_pcie_6a_pipe_clk_src = { 1742 .reg = 0x31088, 1743 .clkr = { 1744 .hw.init = &(struct clk_init_data){ 1745 .name = "gcc_pcie_6a_pipe_clk_src", 1746 .parent_data = &(const struct clk_parent_data){ 1747 .index = DT_PCIE_6A_PIPE, 1748 }, 1749 .num_parents = 1, 1750 .ops = &clk_regmap_phy_mux_ops, 1751 }, 1752 }, 1753 }; 1754 1755 static struct clk_regmap_div gcc_pcie_6a_pipe_div_clk_src = { 1756 .reg = 0x3106c, 1757 .shift = 0, 1758 .width = 4, 1759 .clkr.hw.init = &(const struct clk_init_data) { 1760 .name = "gcc_pcie_6a_pipe_div_clk_src", 1761 .parent_hws = (const struct clk_hw*[]) { 1762 &gcc_pcie_6a_pipe_clk_src.clkr.hw, 1763 }, 1764 .num_parents = 1, 1765 .ops = &clk_regmap_div_ro_ops, 1766 }, 1767 }; 1768 1769 static struct clk_regmap_phy_mux gcc_pcie_6b_pipe_clk_src = { 1770 .reg = 0x8d088, 1771 .clkr = { 1772 .hw.init = &(struct clk_init_data){ 1773 .name = "gcc_pcie_6b_pipe_clk_src", 1774 .parent_data = &(const struct clk_parent_data){ 1775 .index = DT_PCIE_6B_PIPE, 1776 }, 1777 .num_parents = 1, 1778 .ops = &clk_regmap_phy_mux_ops, 1779 }, 1780 }, 1781 }; 1782 1783 static struct clk_regmap_div gcc_pcie_6b_pipe_div_clk_src = { 1784 .reg = 0x8d06c, 1785 .shift = 0, 1786 .width = 4, 1787 .clkr.hw.init = &(const struct clk_init_data) { 1788 .name = "gcc_pcie_6b_pipe_div_clk_src", 1789 .parent_hws = (const struct clk_hw*[]) { 1790 &gcc_pcie_6b_pipe_clk_src.clkr.hw, 1791 }, 1792 .num_parents = 1, 1793 .ops = &clk_regmap_div_ro_ops, 1794 }, 1795 }; 1796 1797 static struct clk_regmap_div gcc_qupv3_wrap0_s2_div_clk_src = { 1798 .reg = 0x42284, 1799 .shift = 0, 1800 .width = 4, 1801 .clkr.hw.init = &(const struct clk_init_data) { 1802 .name = "gcc_qupv3_wrap0_s2_div_clk_src", 1803 .parent_hws = (const struct clk_hw*[]) { 1804 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 1805 }, 1806 .num_parents = 1, 1807 .flags = CLK_SET_RATE_PARENT, 1808 .ops = &clk_regmap_div_ro_ops, 1809 }, 1810 }; 1811 1812 static struct clk_regmap_div gcc_qupv3_wrap0_s3_div_clk_src = { 1813 .reg = 0x423c4, 1814 .shift = 0, 1815 .width = 4, 1816 .clkr.hw.init = &(const struct clk_init_data) { 1817 .name = "gcc_qupv3_wrap0_s3_div_clk_src", 1818 .parent_hws = (const struct clk_hw*[]) { 1819 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 1820 }, 1821 .num_parents = 1, 1822 .flags = CLK_SET_RATE_PARENT, 1823 .ops = &clk_regmap_div_ro_ops, 1824 }, 1825 }; 1826 1827 static struct clk_regmap_div gcc_qupv3_wrap1_s2_div_clk_src = { 1828 .reg = 0x18284, 1829 .shift = 0, 1830 .width = 4, 1831 .clkr.hw.init = &(const struct clk_init_data) { 1832 .name = "gcc_qupv3_wrap1_s2_div_clk_src", 1833 .parent_hws = (const struct clk_hw*[]) { 1834 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 1835 }, 1836 .num_parents = 1, 1837 .flags = CLK_SET_RATE_PARENT, 1838 .ops = &clk_regmap_div_ro_ops, 1839 }, 1840 }; 1841 1842 static struct clk_regmap_div gcc_qupv3_wrap1_s3_div_clk_src = { 1843 .reg = 0x183c4, 1844 .shift = 0, 1845 .width = 4, 1846 .clkr.hw.init = &(const struct clk_init_data) { 1847 .name = "gcc_qupv3_wrap1_s3_div_clk_src", 1848 .parent_hws = (const struct clk_hw*[]) { 1849 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 1850 }, 1851 .num_parents = 1, 1852 .flags = CLK_SET_RATE_PARENT, 1853 .ops = &clk_regmap_div_ro_ops, 1854 }, 1855 }; 1856 1857 static struct clk_regmap_div gcc_qupv3_wrap2_s2_div_clk_src = { 1858 .reg = 0x1e284, 1859 .shift = 0, 1860 .width = 4, 1861 .clkr.hw.init = &(const struct clk_init_data) { 1862 .name = "gcc_qupv3_wrap2_s2_div_clk_src", 1863 .parent_hws = (const struct clk_hw*[]) { 1864 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 1865 }, 1866 .num_parents = 1, 1867 .flags = CLK_SET_RATE_PARENT, 1868 .ops = &clk_regmap_div_ro_ops, 1869 }, 1870 }; 1871 1872 static struct clk_regmap_div gcc_qupv3_wrap2_s3_div_clk_src = { 1873 .reg = 0x1e3c4, 1874 .shift = 0, 1875 .width = 4, 1876 .clkr.hw.init = &(const struct clk_init_data) { 1877 .name = "gcc_qupv3_wrap2_s3_div_clk_src", 1878 .parent_hws = (const struct clk_hw*[]) { 1879 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 1880 }, 1881 .num_parents = 1, 1882 .flags = CLK_SET_RATE_PARENT, 1883 .ops = &clk_regmap_div_ro_ops, 1884 }, 1885 }; 1886 1887 static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src = { 1888 .reg = 0x29284, 1889 .shift = 0, 1890 .width = 4, 1891 .clkr.hw.init = &(const struct clk_init_data) { 1892 .name = "gcc_usb20_mock_utmi_postdiv_clk_src", 1893 .parent_hws = (const struct clk_hw*[]) { 1894 &gcc_usb20_mock_utmi_clk_src.clkr.hw, 1895 }, 1896 .num_parents = 1, 1897 .flags = CLK_SET_RATE_PARENT, 1898 .ops = &clk_regmap_div_ro_ops, 1899 }, 1900 }; 1901 1902 static struct clk_regmap_div gcc_usb30_mp_mock_utmi_postdiv_clk_src = { 1903 .reg = 0x17284, 1904 .shift = 0, 1905 .width = 4, 1906 .clkr.hw.init = &(const struct clk_init_data) { 1907 .name = "gcc_usb30_mp_mock_utmi_postdiv_clk_src", 1908 .parent_hws = (const struct clk_hw*[]) { 1909 &gcc_usb30_mp_mock_utmi_clk_src.clkr.hw, 1910 }, 1911 .num_parents = 1, 1912 .flags = CLK_SET_RATE_PARENT, 1913 .ops = &clk_regmap_div_ro_ops, 1914 }, 1915 }; 1916 1917 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1918 .reg = 0x3905c, 1919 .shift = 0, 1920 .width = 4, 1921 .clkr.hw.init = &(const struct clk_init_data) { 1922 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1923 .parent_hws = (const struct clk_hw*[]) { 1924 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1925 }, 1926 .num_parents = 1, 1927 .flags = CLK_SET_RATE_PARENT, 1928 .ops = &clk_regmap_div_ro_ops, 1929 }, 1930 }; 1931 1932 static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = { 1933 .reg = 0xa105c, 1934 .shift = 0, 1935 .width = 4, 1936 .clkr.hw.init = &(const struct clk_init_data) { 1937 .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src", 1938 .parent_hws = (const struct clk_hw*[]) { 1939 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, 1940 }, 1941 .num_parents = 1, 1942 .flags = CLK_SET_RATE_PARENT, 1943 .ops = &clk_regmap_div_ro_ops, 1944 }, 1945 }; 1946 1947 static struct clk_regmap_div gcc_usb30_tert_mock_utmi_postdiv_clk_src = { 1948 .reg = 0xa205c, 1949 .shift = 0, 1950 .width = 4, 1951 .clkr.hw.init = &(const struct clk_init_data) { 1952 .name = "gcc_usb30_tert_mock_utmi_postdiv_clk_src", 1953 .parent_hws = (const struct clk_hw*[]) { 1954 &gcc_usb30_tert_mock_utmi_clk_src.clkr.hw, 1955 }, 1956 .num_parents = 1, 1957 .flags = CLK_SET_RATE_PARENT, 1958 .ops = &clk_regmap_div_ro_ops, 1959 }, 1960 }; 1961 1962 static struct clk_branch gcc_aggre_noc_usb_north_axi_clk = { 1963 .halt_reg = 0x2d17c, 1964 .halt_check = BRANCH_HALT_VOTED, 1965 .hwcg_reg = 0x2d17c, 1966 .hwcg_bit = 1, 1967 .clkr = { 1968 .enable_reg = 0x2d17c, 1969 .enable_mask = BIT(0), 1970 .hw.init = &(const struct clk_init_data) { 1971 .name = "gcc_aggre_noc_usb_north_axi_clk", 1972 .ops = &clk_branch2_ops, 1973 }, 1974 }, 1975 }; 1976 1977 static struct clk_branch gcc_aggre_noc_usb_south_axi_clk = { 1978 .halt_reg = 0x2d174, 1979 .halt_check = BRANCH_HALT_VOTED, 1980 .hwcg_reg = 0x2d174, 1981 .hwcg_bit = 1, 1982 .clkr = { 1983 .enable_reg = 0x2d174, 1984 .enable_mask = BIT(0), 1985 .hw.init = &(const struct clk_init_data) { 1986 .name = "gcc_aggre_noc_usb_south_axi_clk", 1987 .ops = &clk_branch2_ops, 1988 }, 1989 }, 1990 }; 1991 1992 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1993 .halt_reg = 0x770e4, 1994 .halt_check = BRANCH_HALT_VOTED, 1995 .hwcg_reg = 0x770e4, 1996 .hwcg_bit = 1, 1997 .clkr = { 1998 .enable_reg = 0x770e4, 1999 .enable_mask = BIT(0), 2000 .hw.init = &(const struct clk_init_data) { 2001 .name = "gcc_aggre_ufs_phy_axi_clk", 2002 .parent_hws = (const struct clk_hw*[]) { 2003 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2004 }, 2005 .num_parents = 1, 2006 .flags = CLK_SET_RATE_PARENT, 2007 .ops = &clk_branch2_ops, 2008 }, 2009 }, 2010 }; 2011 2012 static struct clk_branch gcc_aggre_usb2_prim_axi_clk = { 2013 .halt_reg = 0x2928c, 2014 .halt_check = BRANCH_HALT_VOTED, 2015 .hwcg_reg = 0x2928c, 2016 .hwcg_bit = 1, 2017 .clkr = { 2018 .enable_reg = 0x2928c, 2019 .enable_mask = BIT(0), 2020 .hw.init = &(const struct clk_init_data) { 2021 .name = "gcc_aggre_usb2_prim_axi_clk", 2022 .parent_hws = (const struct clk_hw*[]) { 2023 &gcc_usb20_master_clk_src.clkr.hw, 2024 }, 2025 .num_parents = 1, 2026 .flags = CLK_SET_RATE_PARENT, 2027 .ops = &clk_branch2_ops, 2028 }, 2029 }, 2030 }; 2031 2032 static struct clk_branch gcc_aggre_usb3_mp_axi_clk = { 2033 .halt_reg = 0x173d0, 2034 .halt_check = BRANCH_HALT_VOTED, 2035 .hwcg_reg = 0x173d0, 2036 .hwcg_bit = 1, 2037 .clkr = { 2038 .enable_reg = 0x173d0, 2039 .enable_mask = BIT(0), 2040 .hw.init = &(const struct clk_init_data) { 2041 .name = "gcc_aggre_usb3_mp_axi_clk", 2042 .parent_hws = (const struct clk_hw*[]) { 2043 &gcc_usb30_mp_master_clk_src.clkr.hw, 2044 }, 2045 .num_parents = 1, 2046 .flags = CLK_SET_RATE_PARENT, 2047 .ops = &clk_branch2_ops, 2048 }, 2049 }, 2050 }; 2051 2052 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 2053 .halt_reg = 0x39090, 2054 .halt_check = BRANCH_HALT_VOTED, 2055 .hwcg_reg = 0x39090, 2056 .hwcg_bit = 1, 2057 .clkr = { 2058 .enable_reg = 0x39090, 2059 .enable_mask = BIT(0), 2060 .hw.init = &(const struct clk_init_data) { 2061 .name = "gcc_aggre_usb3_prim_axi_clk", 2062 .parent_hws = (const struct clk_hw*[]) { 2063 &gcc_usb30_prim_master_clk_src.clkr.hw, 2064 }, 2065 .num_parents = 1, 2066 .flags = CLK_SET_RATE_PARENT, 2067 .ops = &clk_branch2_ops, 2068 }, 2069 }, 2070 }; 2071 2072 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { 2073 .halt_reg = 0xa1090, 2074 .halt_check = BRANCH_HALT_VOTED, 2075 .hwcg_reg = 0xa1090, 2076 .hwcg_bit = 1, 2077 .clkr = { 2078 .enable_reg = 0xa1090, 2079 .enable_mask = BIT(0), 2080 .hw.init = &(const struct clk_init_data) { 2081 .name = "gcc_aggre_usb3_sec_axi_clk", 2082 .parent_hws = (const struct clk_hw*[]) { 2083 &gcc_usb30_sec_master_clk_src.clkr.hw, 2084 }, 2085 .num_parents = 1, 2086 .flags = CLK_SET_RATE_PARENT, 2087 .ops = &clk_branch2_ops, 2088 }, 2089 }, 2090 }; 2091 2092 static struct clk_branch gcc_aggre_usb3_tert_axi_clk = { 2093 .halt_reg = 0xa2090, 2094 .halt_check = BRANCH_HALT_VOTED, 2095 .hwcg_reg = 0xa2090, 2096 .hwcg_bit = 1, 2097 .clkr = { 2098 .enable_reg = 0xa2090, 2099 .enable_mask = BIT(0), 2100 .hw.init = &(const struct clk_init_data) { 2101 .name = "gcc_aggre_usb3_tert_axi_clk", 2102 .parent_hws = (const struct clk_hw*[]) { 2103 &gcc_usb30_tert_master_clk_src.clkr.hw, 2104 }, 2105 .num_parents = 1, 2106 .flags = CLK_SET_RATE_PARENT, 2107 .ops = &clk_branch2_ops, 2108 }, 2109 }, 2110 }; 2111 2112 static struct clk_branch gcc_aggre_usb4_0_axi_clk = { 2113 .halt_reg = 0x9f118, 2114 .halt_check = BRANCH_HALT_VOTED, 2115 .hwcg_reg = 0x9f118, 2116 .hwcg_bit = 1, 2117 .clkr = { 2118 .enable_reg = 0x9f118, 2119 .enable_mask = BIT(0), 2120 .hw.init = &(const struct clk_init_data) { 2121 .name = "gcc_aggre_usb4_0_axi_clk", 2122 .parent_hws = (const struct clk_hw*[]) { 2123 &gcc_usb4_0_master_clk_src.clkr.hw, 2124 }, 2125 .num_parents = 1, 2126 .flags = CLK_SET_RATE_PARENT, 2127 .ops = &clk_branch2_ops, 2128 }, 2129 }, 2130 }; 2131 2132 static struct clk_branch gcc_aggre_usb4_1_axi_clk = { 2133 .halt_reg = 0x2b118, 2134 .halt_check = BRANCH_HALT_VOTED, 2135 .hwcg_reg = 0x2b118, 2136 .hwcg_bit = 1, 2137 .clkr = { 2138 .enable_reg = 0x2b118, 2139 .enable_mask = BIT(0), 2140 .hw.init = &(const struct clk_init_data) { 2141 .name = "gcc_aggre_usb4_1_axi_clk", 2142 .parent_hws = (const struct clk_hw*[]) { 2143 &gcc_usb4_1_master_clk_src.clkr.hw, 2144 }, 2145 .num_parents = 1, 2146 .flags = CLK_SET_RATE_PARENT, 2147 .ops = &clk_branch2_ops, 2148 }, 2149 }, 2150 }; 2151 2152 static struct clk_branch gcc_aggre_usb4_2_axi_clk = { 2153 .halt_reg = 0x11118, 2154 .halt_check = BRANCH_HALT_VOTED, 2155 .hwcg_reg = 0x11118, 2156 .hwcg_bit = 1, 2157 .clkr = { 2158 .enable_reg = 0x11118, 2159 .enable_mask = BIT(0), 2160 .hw.init = &(const struct clk_init_data) { 2161 .name = "gcc_aggre_usb4_2_axi_clk", 2162 .parent_hws = (const struct clk_hw*[]) { 2163 &gcc_usb4_2_master_clk_src.clkr.hw, 2164 }, 2165 .num_parents = 1, 2166 .flags = CLK_SET_RATE_PARENT, 2167 .ops = &clk_branch2_ops, 2168 }, 2169 }, 2170 }; 2171 2172 static struct clk_branch gcc_aggre_usb_noc_axi_clk = { 2173 .halt_reg = 0x2d034, 2174 .halt_check = BRANCH_HALT_VOTED, 2175 .hwcg_reg = 0x2d034, 2176 .hwcg_bit = 1, 2177 .clkr = { 2178 .enable_reg = 0x2d034, 2179 .enable_mask = BIT(0), 2180 .hw.init = &(const struct clk_init_data) { 2181 .name = "gcc_aggre_usb_noc_axi_clk", 2182 .ops = &clk_branch2_ops, 2183 }, 2184 }, 2185 }; 2186 2187 static struct clk_branch gcc_av1e_ahb_clk = { 2188 .halt_reg = 0x4a004, 2189 .halt_check = BRANCH_HALT_VOTED, 2190 .hwcg_reg = 0x4a004, 2191 .hwcg_bit = 1, 2192 .clkr = { 2193 .enable_reg = 0x4a004, 2194 .enable_mask = BIT(0), 2195 .hw.init = &(const struct clk_init_data) { 2196 .name = "gcc_av1e_ahb_clk", 2197 .ops = &clk_branch2_ops, 2198 }, 2199 }, 2200 }; 2201 2202 static struct clk_branch gcc_av1e_axi_clk = { 2203 .halt_reg = 0x4a008, 2204 .halt_check = BRANCH_HALT_SKIP, 2205 .hwcg_reg = 0x4a008, 2206 .hwcg_bit = 1, 2207 .clkr = { 2208 .enable_reg = 0x4a008, 2209 .enable_mask = BIT(0), 2210 .hw.init = &(const struct clk_init_data) { 2211 .name = "gcc_av1e_axi_clk", 2212 .ops = &clk_branch2_ops, 2213 }, 2214 }, 2215 }; 2216 2217 static struct clk_branch gcc_av1e_xo_clk = { 2218 .halt_reg = 0x4a014, 2219 .halt_check = BRANCH_HALT, 2220 .clkr = { 2221 .enable_reg = 0x4a014, 2222 .enable_mask = BIT(0), 2223 .hw.init = &(const struct clk_init_data) { 2224 .name = "gcc_av1e_xo_clk", 2225 .ops = &clk_branch2_ops, 2226 }, 2227 }, 2228 }; 2229 2230 static struct clk_branch gcc_boot_rom_ahb_clk = { 2231 .halt_reg = 0x38004, 2232 .halt_check = BRANCH_HALT_VOTED, 2233 .hwcg_reg = 0x38004, 2234 .hwcg_bit = 1, 2235 .clkr = { 2236 .enable_reg = 0x52000, 2237 .enable_mask = BIT(10), 2238 .hw.init = &(const struct clk_init_data) { 2239 .name = "gcc_boot_rom_ahb_clk", 2240 .ops = &clk_branch2_ops, 2241 }, 2242 }, 2243 }; 2244 2245 static struct clk_branch gcc_camera_hf_axi_clk = { 2246 .halt_reg = 0x26010, 2247 .halt_check = BRANCH_HALT_SKIP, 2248 .hwcg_reg = 0x26010, 2249 .hwcg_bit = 1, 2250 .clkr = { 2251 .enable_reg = 0x26010, 2252 .enable_mask = BIT(0), 2253 .hw.init = &(const struct clk_init_data) { 2254 .name = "gcc_camera_hf_axi_clk", 2255 .ops = &clk_branch2_ops, 2256 }, 2257 }, 2258 }; 2259 2260 static struct clk_branch gcc_camera_sf_axi_clk = { 2261 .halt_reg = 0x2601c, 2262 .halt_check = BRANCH_HALT_SKIP, 2263 .hwcg_reg = 0x2601c, 2264 .hwcg_bit = 1, 2265 .clkr = { 2266 .enable_reg = 0x2601c, 2267 .enable_mask = BIT(0), 2268 .hw.init = &(const struct clk_init_data) { 2269 .name = "gcc_camera_sf_axi_clk", 2270 .ops = &clk_branch2_ops, 2271 }, 2272 }, 2273 }; 2274 2275 static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = { 2276 .halt_reg = 0x10028, 2277 .halt_check = BRANCH_HALT_VOTED, 2278 .hwcg_reg = 0x10028, 2279 .hwcg_bit = 1, 2280 .clkr = { 2281 .enable_reg = 0x52028, 2282 .enable_mask = BIT(20), 2283 .hw.init = &(const struct clk_init_data) { 2284 .name = "gcc_cfg_noc_pcie_anoc_ahb_clk", 2285 .ops = &clk_branch2_ops, 2286 }, 2287 }, 2288 }; 2289 2290 static struct clk_branch gcc_cfg_noc_pcie_anoc_north_ahb_clk = { 2291 .halt_reg = 0x1002c, 2292 .halt_check = BRANCH_HALT_VOTED, 2293 .hwcg_reg = 0x1002c, 2294 .hwcg_bit = 1, 2295 .clkr = { 2296 .enable_reg = 0x52028, 2297 .enable_mask = BIT(22), 2298 .hw.init = &(const struct clk_init_data) { 2299 .name = "gcc_cfg_noc_pcie_anoc_north_ahb_clk", 2300 .ops = &clk_branch2_ops, 2301 }, 2302 }, 2303 }; 2304 2305 static struct clk_branch gcc_cfg_noc_pcie_anoc_south_ahb_clk = { 2306 .halt_reg = 0x10030, 2307 .halt_check = BRANCH_HALT_VOTED, 2308 .hwcg_reg = 0x10030, 2309 .hwcg_bit = 1, 2310 .clkr = { 2311 .enable_reg = 0x52000, 2312 .enable_mask = BIT(20), 2313 .hw.init = &(const struct clk_init_data) { 2314 .name = "gcc_cfg_noc_pcie_anoc_south_ahb_clk", 2315 .ops = &clk_branch2_ops, 2316 }, 2317 }, 2318 }; 2319 2320 static struct clk_branch gcc_cfg_noc_usb2_prim_axi_clk = { 2321 .halt_reg = 0x29288, 2322 .halt_check = BRANCH_HALT_VOTED, 2323 .hwcg_reg = 0x29288, 2324 .hwcg_bit = 1, 2325 .clkr = { 2326 .enable_reg = 0x29288, 2327 .enable_mask = BIT(0), 2328 .hw.init = &(const struct clk_init_data) { 2329 .name = "gcc_cfg_noc_usb2_prim_axi_clk", 2330 .parent_hws = (const struct clk_hw*[]) { 2331 &gcc_usb20_master_clk_src.clkr.hw, 2332 }, 2333 .num_parents = 1, 2334 .flags = CLK_SET_RATE_PARENT, 2335 .ops = &clk_branch2_ops, 2336 }, 2337 }, 2338 }; 2339 2340 static struct clk_branch gcc_cfg_noc_usb3_mp_axi_clk = { 2341 .halt_reg = 0x173cc, 2342 .halt_check = BRANCH_HALT_VOTED, 2343 .hwcg_reg = 0x173cc, 2344 .hwcg_bit = 1, 2345 .clkr = { 2346 .enable_reg = 0x173cc, 2347 .enable_mask = BIT(0), 2348 .hw.init = &(const struct clk_init_data) { 2349 .name = "gcc_cfg_noc_usb3_mp_axi_clk", 2350 .parent_hws = (const struct clk_hw*[]) { 2351 &gcc_usb30_mp_master_clk_src.clkr.hw, 2352 }, 2353 .num_parents = 1, 2354 .flags = CLK_SET_RATE_PARENT, 2355 .ops = &clk_branch2_ops, 2356 }, 2357 }, 2358 }; 2359 2360 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 2361 .halt_reg = 0x3908c, 2362 .halt_check = BRANCH_HALT_VOTED, 2363 .hwcg_reg = 0x3908c, 2364 .hwcg_bit = 1, 2365 .clkr = { 2366 .enable_reg = 0x3908c, 2367 .enable_mask = BIT(0), 2368 .hw.init = &(const struct clk_init_data) { 2369 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 2370 .parent_hws = (const struct clk_hw*[]) { 2371 &gcc_usb30_prim_master_clk_src.clkr.hw, 2372 }, 2373 .num_parents = 1, 2374 .flags = CLK_SET_RATE_PARENT, 2375 .ops = &clk_branch2_ops, 2376 }, 2377 }, 2378 }; 2379 2380 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { 2381 .halt_reg = 0xa108c, 2382 .halt_check = BRANCH_HALT_VOTED, 2383 .hwcg_reg = 0xa108c, 2384 .hwcg_bit = 1, 2385 .clkr = { 2386 .enable_reg = 0xa108c, 2387 .enable_mask = BIT(0), 2388 .hw.init = &(const struct clk_init_data) { 2389 .name = "gcc_cfg_noc_usb3_sec_axi_clk", 2390 .parent_hws = (const struct clk_hw*[]) { 2391 &gcc_usb30_sec_master_clk_src.clkr.hw, 2392 }, 2393 .num_parents = 1, 2394 .flags = CLK_SET_RATE_PARENT, 2395 .ops = &clk_branch2_ops, 2396 }, 2397 }, 2398 }; 2399 2400 static struct clk_branch gcc_cfg_noc_usb3_tert_axi_clk = { 2401 .halt_reg = 0xa208c, 2402 .halt_check = BRANCH_HALT_VOTED, 2403 .hwcg_reg = 0xa208c, 2404 .hwcg_bit = 1, 2405 .clkr = { 2406 .enable_reg = 0xa208c, 2407 .enable_mask = BIT(0), 2408 .hw.init = &(const struct clk_init_data) { 2409 .name = "gcc_cfg_noc_usb3_tert_axi_clk", 2410 .parent_hws = (const struct clk_hw*[]) { 2411 &gcc_usb30_tert_master_clk_src.clkr.hw, 2412 }, 2413 .num_parents = 1, 2414 .flags = CLK_SET_RATE_PARENT, 2415 .ops = &clk_branch2_ops, 2416 }, 2417 }, 2418 }; 2419 2420 static struct clk_branch gcc_cfg_noc_usb_anoc_ahb_clk = { 2421 .halt_reg = 0x2d024, 2422 .halt_check = BRANCH_HALT_VOTED, 2423 .hwcg_reg = 0x2d024, 2424 .hwcg_bit = 1, 2425 .clkr = { 2426 .enable_reg = 0x52028, 2427 .enable_mask = BIT(21), 2428 .hw.init = &(const struct clk_init_data) { 2429 .name = "gcc_cfg_noc_usb_anoc_ahb_clk", 2430 .ops = &clk_branch2_ops, 2431 }, 2432 }, 2433 }; 2434 2435 static struct clk_branch gcc_cfg_noc_usb_anoc_north_ahb_clk = { 2436 .halt_reg = 0x2d028, 2437 .halt_check = BRANCH_HALT_VOTED, 2438 .hwcg_reg = 0x2d028, 2439 .hwcg_bit = 1, 2440 .clkr = { 2441 .enable_reg = 0x52028, 2442 .enable_mask = BIT(23), 2443 .hw.init = &(const struct clk_init_data) { 2444 .name = "gcc_cfg_noc_usb_anoc_north_ahb_clk", 2445 .ops = &clk_branch2_ops, 2446 }, 2447 }, 2448 }; 2449 2450 static struct clk_branch gcc_cfg_noc_usb_anoc_south_ahb_clk = { 2451 .halt_reg = 0x2d02c, 2452 .halt_check = BRANCH_HALT_VOTED, 2453 .hwcg_reg = 0x2d02c, 2454 .hwcg_bit = 1, 2455 .clkr = { 2456 .enable_reg = 0x52018, 2457 .enable_mask = BIT(7), 2458 .hw.init = &(const struct clk_init_data) { 2459 .name = "gcc_cfg_noc_usb_anoc_south_ahb_clk", 2460 .ops = &clk_branch2_ops, 2461 }, 2462 }, 2463 }; 2464 2465 static struct clk_branch gcc_cnoc_pcie1_tunnel_clk = { 2466 .halt_reg = 0x2c2b4, 2467 .halt_check = BRANCH_HALT_VOTED, 2468 .clkr = { 2469 .enable_reg = 0x52010, 2470 .enable_mask = BIT(30), 2471 .hw.init = &(const struct clk_init_data) { 2472 .name = "gcc_cnoc_pcie1_tunnel_clk", 2473 .ops = &clk_branch2_ops, 2474 }, 2475 }, 2476 }; 2477 2478 static struct clk_branch gcc_cnoc_pcie2_tunnel_clk = { 2479 .halt_reg = 0x132b4, 2480 .halt_check = BRANCH_HALT_VOTED, 2481 .clkr = { 2482 .enable_reg = 0x52010, 2483 .enable_mask = BIT(31), 2484 .hw.init = &(const struct clk_init_data) { 2485 .name = "gcc_cnoc_pcie2_tunnel_clk", 2486 .ops = &clk_branch2_ops, 2487 }, 2488 }, 2489 }; 2490 2491 static struct clk_branch gcc_cnoc_pcie_north_sf_axi_clk = { 2492 .halt_reg = 0x10014, 2493 .halt_check = BRANCH_HALT_VOTED, 2494 .hwcg_reg = 0x10014, 2495 .hwcg_bit = 1, 2496 .clkr = { 2497 .enable_reg = 0x52008, 2498 .enable_mask = BIT(6), 2499 .hw.init = &(const struct clk_init_data) { 2500 .name = "gcc_cnoc_pcie_north_sf_axi_clk", 2501 .ops = &clk_branch2_ops, 2502 }, 2503 }, 2504 }; 2505 2506 static struct clk_branch gcc_cnoc_pcie_south_sf_axi_clk = { 2507 .halt_reg = 0x10018, 2508 .halt_check = BRANCH_HALT_VOTED, 2509 .hwcg_reg = 0x10018, 2510 .hwcg_bit = 1, 2511 .clkr = { 2512 .enable_reg = 0x52028, 2513 .enable_mask = BIT(12), 2514 .hw.init = &(const struct clk_init_data) { 2515 .name = "gcc_cnoc_pcie_south_sf_axi_clk", 2516 .ops = &clk_branch2_ops, 2517 }, 2518 }, 2519 }; 2520 2521 static struct clk_branch gcc_cnoc_pcie_tunnel_clk = { 2522 .halt_reg = 0xa02b4, 2523 .halt_check = BRANCH_HALT_VOTED, 2524 .hwcg_reg = 0xa02b4, 2525 .hwcg_bit = 1, 2526 .clkr = { 2527 .enable_reg = 0x52010, 2528 .enable_mask = BIT(29), 2529 .hw.init = &(const struct clk_init_data) { 2530 .name = "gcc_cnoc_pcie_tunnel_clk", 2531 .ops = &clk_branch2_ops, 2532 }, 2533 }, 2534 }; 2535 2536 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 2537 .halt_reg = 0x7115c, 2538 .halt_check = BRANCH_HALT_SKIP, 2539 .hwcg_reg = 0x7115c, 2540 .hwcg_bit = 1, 2541 .clkr = { 2542 .enable_reg = 0x7115c, 2543 .enable_mask = BIT(0), 2544 .hw.init = &(const struct clk_init_data) { 2545 .name = "gcc_ddrss_gpu_axi_clk", 2546 .ops = &clk_branch2_ops, 2547 }, 2548 }, 2549 }; 2550 2551 static struct clk_branch gcc_disp_hf_axi_clk = { 2552 .halt_reg = 0x2700c, 2553 .halt_check = BRANCH_HALT_SKIP, 2554 .hwcg_reg = 0x2700c, 2555 .hwcg_bit = 1, 2556 .clkr = { 2557 .enable_reg = 0x2700c, 2558 .enable_mask = BIT(0), 2559 .hw.init = &(const struct clk_init_data) { 2560 .name = "gcc_disp_hf_axi_clk", 2561 .ops = &clk_branch2_ops, 2562 }, 2563 }, 2564 }; 2565 2566 static struct clk_branch gcc_disp_xo_clk = { 2567 .halt_reg = 0x27018, 2568 .halt_check = BRANCH_HALT, 2569 .clkr = { 2570 .enable_reg = 0x27018, 2571 .enable_mask = BIT(0), 2572 .hw.init = &(const struct clk_init_data) { 2573 .name = "gcc_disp_xo_clk", 2574 .ops = &clk_branch2_ops, 2575 }, 2576 }, 2577 }; 2578 2579 static struct clk_branch gcc_gp1_clk = { 2580 .halt_reg = 0x64000, 2581 .halt_check = BRANCH_HALT, 2582 .clkr = { 2583 .enable_reg = 0x64000, 2584 .enable_mask = BIT(0), 2585 .hw.init = &(const struct clk_init_data) { 2586 .name = "gcc_gp1_clk", 2587 .parent_hws = (const struct clk_hw*[]) { 2588 &gcc_gp1_clk_src.clkr.hw, 2589 }, 2590 .num_parents = 1, 2591 .flags = CLK_SET_RATE_PARENT, 2592 .ops = &clk_branch2_ops, 2593 }, 2594 }, 2595 }; 2596 2597 static struct clk_branch gcc_gp2_clk = { 2598 .halt_reg = 0x65000, 2599 .halt_check = BRANCH_HALT, 2600 .clkr = { 2601 .enable_reg = 0x65000, 2602 .enable_mask = BIT(0), 2603 .hw.init = &(const struct clk_init_data) { 2604 .name = "gcc_gp2_clk", 2605 .parent_hws = (const struct clk_hw*[]) { 2606 &gcc_gp2_clk_src.clkr.hw, 2607 }, 2608 .num_parents = 1, 2609 .flags = CLK_SET_RATE_PARENT, 2610 .ops = &clk_branch2_ops, 2611 }, 2612 }, 2613 }; 2614 2615 static struct clk_branch gcc_gp3_clk = { 2616 .halt_reg = 0x66000, 2617 .halt_check = BRANCH_HALT, 2618 .clkr = { 2619 .enable_reg = 0x66000, 2620 .enable_mask = BIT(0), 2621 .hw.init = &(const struct clk_init_data) { 2622 .name = "gcc_gp3_clk", 2623 .parent_hws = (const struct clk_hw*[]) { 2624 &gcc_gp3_clk_src.clkr.hw, 2625 }, 2626 .num_parents = 1, 2627 .flags = CLK_SET_RATE_PARENT, 2628 .ops = &clk_branch2_ops, 2629 }, 2630 }, 2631 }; 2632 2633 static struct clk_branch gcc_gpu_cfg_ahb_clk = { 2634 .halt_reg = 0x71004, 2635 .halt_check = BRANCH_HALT_VOTED, 2636 .hwcg_reg = 0x71004, 2637 .hwcg_bit = 1, 2638 .clkr = { 2639 .enable_reg = 0x71004, 2640 .enable_mask = BIT(0), 2641 .hw.init = &(const struct clk_init_data) { 2642 .name = "gcc_gpu_cfg_ahb_clk", 2643 .ops = &clk_branch2_ops, 2644 }, 2645 }, 2646 }; 2647 2648 static struct clk_branch gcc_gpu_gpll0_cph_clk_src = { 2649 .halt_check = BRANCH_HALT_DELAY, 2650 .clkr = { 2651 .enable_reg = 0x52000, 2652 .enable_mask = BIT(15), 2653 .hw.init = &(const struct clk_init_data) { 2654 .name = "gcc_gpu_gpll0_cph_clk_src", 2655 .parent_hws = (const struct clk_hw*[]) { 2656 &gcc_gpll0.clkr.hw, 2657 }, 2658 .num_parents = 1, 2659 .flags = CLK_SET_RATE_PARENT, 2660 .ops = &clk_branch2_ops, 2661 }, 2662 }, 2663 }; 2664 2665 static struct clk_branch gcc_gpu_gpll0_div_cph_clk_src = { 2666 .halt_check = BRANCH_HALT_DELAY, 2667 .clkr = { 2668 .enable_reg = 0x52000, 2669 .enable_mask = BIT(16), 2670 .hw.init = &(const struct clk_init_data) { 2671 .name = "gcc_gpu_gpll0_div_cph_clk_src", 2672 .parent_hws = (const struct clk_hw*[]) { 2673 &gcc_gpll0_out_even.clkr.hw, 2674 }, 2675 .num_parents = 1, 2676 .flags = CLK_SET_RATE_PARENT, 2677 .ops = &clk_branch2_ops, 2678 }, 2679 }, 2680 }; 2681 2682 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 2683 .halt_reg = 0x71010, 2684 .halt_check = BRANCH_HALT_VOTED, 2685 .hwcg_reg = 0x71010, 2686 .hwcg_bit = 1, 2687 .clkr = { 2688 .enable_reg = 0x71010, 2689 .enable_mask = BIT(0), 2690 .hw.init = &(const struct clk_init_data) { 2691 .name = "gcc_gpu_memnoc_gfx_clk", 2692 .ops = &clk_branch2_ops, 2693 }, 2694 }, 2695 }; 2696 2697 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 2698 .halt_reg = 0x71018, 2699 .halt_check = BRANCH_HALT, 2700 .clkr = { 2701 .enable_reg = 0x71018, 2702 .enable_mask = BIT(0), 2703 .hw.init = &(const struct clk_init_data) { 2704 .name = "gcc_gpu_snoc_dvm_gfx_clk", 2705 .ops = &clk_branch2_ops, 2706 }, 2707 }, 2708 }; 2709 2710 static struct clk_branch gcc_pcie0_phy_rchng_clk = { 2711 .halt_reg = 0xa0050, 2712 .halt_check = BRANCH_HALT_VOTED, 2713 .clkr = { 2714 .enable_reg = 0x52010, 2715 .enable_mask = BIT(26), 2716 .hw.init = &(const struct clk_init_data) { 2717 .name = "gcc_pcie0_phy_rchng_clk", 2718 .parent_hws = (const struct clk_hw*[]) { 2719 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 2720 }, 2721 .num_parents = 1, 2722 .flags = CLK_SET_RATE_PARENT, 2723 .ops = &clk_branch2_ops, 2724 }, 2725 }, 2726 }; 2727 2728 static struct clk_branch gcc_pcie1_phy_rchng_clk = { 2729 .halt_reg = 0x2c050, 2730 .halt_check = BRANCH_HALT_VOTED, 2731 .clkr = { 2732 .enable_reg = 0x52020, 2733 .enable_mask = BIT(31), 2734 .hw.init = &(const struct clk_init_data) { 2735 .name = "gcc_pcie1_phy_rchng_clk", 2736 .parent_hws = (const struct clk_hw*[]) { 2737 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, 2738 }, 2739 .num_parents = 1, 2740 .flags = CLK_SET_RATE_PARENT, 2741 .ops = &clk_branch2_ops, 2742 }, 2743 }, 2744 }; 2745 2746 static struct clk_branch gcc_pcie2_phy_rchng_clk = { 2747 .halt_reg = 0x13050, 2748 .halt_check = BRANCH_HALT_VOTED, 2749 .clkr = { 2750 .enable_reg = 0x52020, 2751 .enable_mask = BIT(24), 2752 .hw.init = &(const struct clk_init_data) { 2753 .name = "gcc_pcie2_phy_rchng_clk", 2754 .parent_hws = (const struct clk_hw*[]) { 2755 &gcc_pcie_2_phy_rchng_clk_src.clkr.hw, 2756 }, 2757 .num_parents = 1, 2758 .flags = CLK_SET_RATE_PARENT, 2759 .ops = &clk_branch2_ops, 2760 }, 2761 }, 2762 }; 2763 2764 static struct clk_branch gcc_pcie_0_aux_clk = { 2765 .halt_reg = 0xa0038, 2766 .halt_check = BRANCH_HALT_VOTED, 2767 .clkr = { 2768 .enable_reg = 0x52010, 2769 .enable_mask = BIT(24), 2770 .hw.init = &(const struct clk_init_data) { 2771 .name = "gcc_pcie_0_aux_clk", 2772 .parent_hws = (const struct clk_hw*[]) { 2773 &gcc_pcie_0_aux_clk_src.clkr.hw, 2774 }, 2775 .num_parents = 1, 2776 .flags = CLK_SET_RATE_PARENT, 2777 .ops = &clk_branch2_ops, 2778 }, 2779 }, 2780 }; 2781 2782 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 2783 .halt_reg = 0xa0034, 2784 .halt_check = BRANCH_HALT_VOTED, 2785 .hwcg_reg = 0xa0034, 2786 .hwcg_bit = 1, 2787 .clkr = { 2788 .enable_reg = 0x52010, 2789 .enable_mask = BIT(23), 2790 .hw.init = &(const struct clk_init_data) { 2791 .name = "gcc_pcie_0_cfg_ahb_clk", 2792 .ops = &clk_branch2_ops, 2793 }, 2794 }, 2795 }; 2796 2797 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 2798 .halt_reg = 0xa0028, 2799 .halt_check = BRANCH_HALT_SKIP, 2800 .hwcg_reg = 0xa0028, 2801 .hwcg_bit = 1, 2802 .clkr = { 2803 .enable_reg = 0x52010, 2804 .enable_mask = BIT(22), 2805 .hw.init = &(const struct clk_init_data) { 2806 .name = "gcc_pcie_0_mstr_axi_clk", 2807 .ops = &clk_branch2_ops, 2808 }, 2809 }, 2810 }; 2811 2812 static struct clk_branch gcc_pcie_0_pipe_clk = { 2813 .halt_reg = 0xa0044, 2814 .halt_check = BRANCH_HALT_VOTED, 2815 .clkr = { 2816 .enable_reg = 0x52010, 2817 .enable_mask = BIT(25), 2818 .hw.init = &(const struct clk_init_data) { 2819 .name = "gcc_pcie_0_pipe_clk", 2820 .ops = &clk_branch2_ops, 2821 }, 2822 }, 2823 }; 2824 2825 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 2826 .halt_reg = 0xa001c, 2827 .halt_check = BRANCH_HALT_VOTED, 2828 .hwcg_reg = 0xa001c, 2829 .hwcg_bit = 1, 2830 .clkr = { 2831 .enable_reg = 0x52010, 2832 .enable_mask = BIT(21), 2833 .hw.init = &(const struct clk_init_data) { 2834 .name = "gcc_pcie_0_slv_axi_clk", 2835 .ops = &clk_branch2_ops, 2836 }, 2837 }, 2838 }; 2839 2840 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 2841 .halt_reg = 0xa0018, 2842 .halt_check = BRANCH_HALT_VOTED, 2843 .clkr = { 2844 .enable_reg = 0x52010, 2845 .enable_mask = BIT(20), 2846 .hw.init = &(const struct clk_init_data) { 2847 .name = "gcc_pcie_0_slv_q2a_axi_clk", 2848 .ops = &clk_branch2_ops, 2849 }, 2850 }, 2851 }; 2852 2853 static struct clk_branch gcc_pcie_1_aux_clk = { 2854 .halt_reg = 0x2c038, 2855 .halt_check = BRANCH_HALT_VOTED, 2856 .clkr = { 2857 .enable_reg = 0x52020, 2858 .enable_mask = BIT(29), 2859 .hw.init = &(const struct clk_init_data) { 2860 .name = "gcc_pcie_1_aux_clk", 2861 .parent_hws = (const struct clk_hw*[]) { 2862 &gcc_pcie_1_aux_clk_src.clkr.hw, 2863 }, 2864 .num_parents = 1, 2865 .flags = CLK_SET_RATE_PARENT, 2866 .ops = &clk_branch2_ops, 2867 }, 2868 }, 2869 }; 2870 2871 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 2872 .halt_reg = 0x2c034, 2873 .halt_check = BRANCH_HALT_VOTED, 2874 .hwcg_reg = 0x2c034, 2875 .hwcg_bit = 1, 2876 .clkr = { 2877 .enable_reg = 0x52020, 2878 .enable_mask = BIT(28), 2879 .hw.init = &(const struct clk_init_data) { 2880 .name = "gcc_pcie_1_cfg_ahb_clk", 2881 .ops = &clk_branch2_ops, 2882 }, 2883 }, 2884 }; 2885 2886 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 2887 .halt_reg = 0x2c028, 2888 .halt_check = BRANCH_HALT_SKIP, 2889 .hwcg_reg = 0x2c028, 2890 .hwcg_bit = 1, 2891 .clkr = { 2892 .enable_reg = 0x52020, 2893 .enable_mask = BIT(27), 2894 .hw.init = &(const struct clk_init_data) { 2895 .name = "gcc_pcie_1_mstr_axi_clk", 2896 .ops = &clk_branch2_ops, 2897 }, 2898 }, 2899 }; 2900 2901 static struct clk_branch gcc_pcie_1_pipe_clk = { 2902 .halt_reg = 0x2c044, 2903 .halt_check = BRANCH_HALT_VOTED, 2904 .clkr = { 2905 .enable_reg = 0x52020, 2906 .enable_mask = BIT(30), 2907 .hw.init = &(const struct clk_init_data) { 2908 .name = "gcc_pcie_1_pipe_clk", 2909 .ops = &clk_branch2_ops, 2910 }, 2911 }, 2912 }; 2913 2914 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 2915 .halt_reg = 0x2c01c, 2916 .halt_check = BRANCH_HALT_VOTED, 2917 .hwcg_reg = 0x2c01c, 2918 .hwcg_bit = 1, 2919 .clkr = { 2920 .enable_reg = 0x52020, 2921 .enable_mask = BIT(26), 2922 .hw.init = &(const struct clk_init_data) { 2923 .name = "gcc_pcie_1_slv_axi_clk", 2924 .ops = &clk_branch2_ops, 2925 }, 2926 }, 2927 }; 2928 2929 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 2930 .halt_reg = 0x2c018, 2931 .halt_check = BRANCH_HALT_VOTED, 2932 .clkr = { 2933 .enable_reg = 0x52020, 2934 .enable_mask = BIT(25), 2935 .hw.init = &(const struct clk_init_data) { 2936 .name = "gcc_pcie_1_slv_q2a_axi_clk", 2937 .ops = &clk_branch2_ops, 2938 }, 2939 }, 2940 }; 2941 2942 static struct clk_branch gcc_pcie_2_aux_clk = { 2943 .halt_reg = 0x13038, 2944 .halt_check = BRANCH_HALT_VOTED, 2945 .clkr = { 2946 .enable_reg = 0x52020, 2947 .enable_mask = BIT(22), 2948 .hw.init = &(const struct clk_init_data) { 2949 .name = "gcc_pcie_2_aux_clk", 2950 .parent_hws = (const struct clk_hw*[]) { 2951 &gcc_pcie_2_aux_clk_src.clkr.hw, 2952 }, 2953 .num_parents = 1, 2954 .flags = CLK_SET_RATE_PARENT, 2955 .ops = &clk_branch2_ops, 2956 }, 2957 }, 2958 }; 2959 2960 static struct clk_branch gcc_pcie_2_cfg_ahb_clk = { 2961 .halt_reg = 0x13034, 2962 .halt_check = BRANCH_HALT_VOTED, 2963 .hwcg_reg = 0x13034, 2964 .hwcg_bit = 1, 2965 .clkr = { 2966 .enable_reg = 0x52020, 2967 .enable_mask = BIT(21), 2968 .hw.init = &(const struct clk_init_data) { 2969 .name = "gcc_pcie_2_cfg_ahb_clk", 2970 .ops = &clk_branch2_ops, 2971 }, 2972 }, 2973 }; 2974 2975 static struct clk_branch gcc_pcie_2_mstr_axi_clk = { 2976 .halt_reg = 0x13028, 2977 .halt_check = BRANCH_HALT_SKIP, 2978 .hwcg_reg = 0x13028, 2979 .hwcg_bit = 1, 2980 .clkr = { 2981 .enable_reg = 0x52020, 2982 .enable_mask = BIT(20), 2983 .hw.init = &(const struct clk_init_data) { 2984 .name = "gcc_pcie_2_mstr_axi_clk", 2985 .ops = &clk_branch2_ops, 2986 }, 2987 }, 2988 }; 2989 2990 static struct clk_branch gcc_pcie_2_pipe_clk = { 2991 .halt_reg = 0x13044, 2992 .halt_check = BRANCH_HALT_VOTED, 2993 .clkr = { 2994 .enable_reg = 0x52020, 2995 .enable_mask = BIT(23), 2996 .hw.init = &(const struct clk_init_data) { 2997 .name = "gcc_pcie_2_pipe_clk", 2998 .ops = &clk_branch2_ops, 2999 }, 3000 }, 3001 }; 3002 3003 static struct clk_branch gcc_pcie_2_slv_axi_clk = { 3004 .halt_reg = 0x1301c, 3005 .halt_check = BRANCH_HALT_VOTED, 3006 .hwcg_reg = 0x1301c, 3007 .hwcg_bit = 1, 3008 .clkr = { 3009 .enable_reg = 0x52020, 3010 .enable_mask = BIT(19), 3011 .hw.init = &(const struct clk_init_data) { 3012 .name = "gcc_pcie_2_slv_axi_clk", 3013 .ops = &clk_branch2_ops, 3014 }, 3015 }, 3016 }; 3017 3018 static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = { 3019 .halt_reg = 0x13018, 3020 .halt_check = BRANCH_HALT_VOTED, 3021 .clkr = { 3022 .enable_reg = 0x52020, 3023 .enable_mask = BIT(18), 3024 .hw.init = &(const struct clk_init_data) { 3025 .name = "gcc_pcie_2_slv_q2a_axi_clk", 3026 .ops = &clk_branch2_ops, 3027 }, 3028 }, 3029 }; 3030 3031 static struct clk_branch gcc_pcie_3_aux_clk = { 3032 .halt_reg = 0x58038, 3033 .halt_check = BRANCH_HALT_VOTED, 3034 .clkr = { 3035 .enable_reg = 0x52020, 3036 .enable_mask = BIT(1), 3037 .hw.init = &(const struct clk_init_data) { 3038 .name = "gcc_pcie_3_aux_clk", 3039 .parent_hws = (const struct clk_hw*[]) { 3040 &gcc_pcie_3_aux_clk_src.clkr.hw, 3041 }, 3042 .num_parents = 1, 3043 .flags = CLK_SET_RATE_PARENT, 3044 .ops = &clk_branch2_ops, 3045 }, 3046 }, 3047 }; 3048 3049 static struct clk_branch gcc_pcie_3_cfg_ahb_clk = { 3050 .halt_reg = 0x58034, 3051 .halt_check = BRANCH_HALT_VOTED, 3052 .hwcg_reg = 0x58034, 3053 .hwcg_bit = 1, 3054 .clkr = { 3055 .enable_reg = 0x52020, 3056 .enable_mask = BIT(0), 3057 .hw.init = &(const struct clk_init_data) { 3058 .name = "gcc_pcie_3_cfg_ahb_clk", 3059 .ops = &clk_branch2_ops, 3060 }, 3061 }, 3062 }; 3063 3064 static struct clk_branch gcc_pcie_3_mstr_axi_clk = { 3065 .halt_reg = 0x58028, 3066 .halt_check = BRANCH_HALT_SKIP, 3067 .hwcg_reg = 0x58028, 3068 .hwcg_bit = 1, 3069 .clkr = { 3070 .enable_reg = 0x52018, 3071 .enable_mask = BIT(31), 3072 .hw.init = &(const struct clk_init_data) { 3073 .name = "gcc_pcie_3_mstr_axi_clk", 3074 .ops = &clk_branch2_ops, 3075 }, 3076 }, 3077 }; 3078 3079 static struct clk_branch gcc_pcie_3_phy_aux_clk = { 3080 .halt_reg = 0x58044, 3081 .halt_check = BRANCH_HALT_VOTED, 3082 .clkr = { 3083 .enable_reg = 0x52020, 3084 .enable_mask = BIT(2), 3085 .hw.init = &(const struct clk_init_data) { 3086 .name = "gcc_pcie_3_phy_aux_clk", 3087 .ops = &clk_branch2_ops, 3088 }, 3089 }, 3090 }; 3091 3092 static struct clk_branch gcc_pcie_3_phy_rchng_clk = { 3093 .halt_reg = 0x5805c, 3094 .halt_check = BRANCH_HALT_VOTED, 3095 .clkr = { 3096 .enable_reg = 0x52020, 3097 .enable_mask = BIT(4), 3098 .hw.init = &(const struct clk_init_data) { 3099 .name = "gcc_pcie_3_phy_rchng_clk", 3100 .parent_hws = (const struct clk_hw*[]) { 3101 &gcc_pcie_3_phy_rchng_clk_src.clkr.hw, 3102 }, 3103 .num_parents = 1, 3104 .flags = CLK_SET_RATE_PARENT, 3105 .ops = &clk_branch2_ops, 3106 }, 3107 }, 3108 }; 3109 3110 static struct clk_branch gcc_pcie_3_pipe_clk = { 3111 .halt_reg = 0x58050, 3112 .halt_check = BRANCH_HALT_VOTED, 3113 .clkr = { 3114 .enable_reg = 0x52020, 3115 .enable_mask = BIT(3), 3116 .hw.init = &(const struct clk_init_data) { 3117 .name = "gcc_pcie_3_pipe_clk", 3118 .ops = &clk_branch2_ops, 3119 }, 3120 }, 3121 }; 3122 3123 static struct clk_branch gcc_pcie_3_pipediv2_clk = { 3124 .halt_reg = 0x58060, 3125 .halt_check = BRANCH_HALT_VOTED, 3126 .clkr = { 3127 .enable_reg = 0x52020, 3128 .enable_mask = BIT(5), 3129 .hw.init = &(const struct clk_init_data) { 3130 .name = "gcc_pcie_3_pipediv2_clk", 3131 .parent_hws = (const struct clk_hw*[]) { 3132 &gcc_pcie_3_pipe_div_clk_src.clkr.hw, 3133 }, 3134 .num_parents = 1, 3135 .flags = CLK_SET_RATE_PARENT, 3136 .ops = &clk_branch2_ops, 3137 }, 3138 }, 3139 }; 3140 3141 static struct clk_branch gcc_pcie_3_slv_axi_clk = { 3142 .halt_reg = 0x5801c, 3143 .halt_check = BRANCH_HALT_VOTED, 3144 .hwcg_reg = 0x5801c, 3145 .hwcg_bit = 1, 3146 .clkr = { 3147 .enable_reg = 0x52018, 3148 .enable_mask = BIT(30), 3149 .hw.init = &(const struct clk_init_data) { 3150 .name = "gcc_pcie_3_slv_axi_clk", 3151 .ops = &clk_branch2_ops, 3152 }, 3153 }, 3154 }; 3155 3156 static struct clk_branch gcc_pcie_3_slv_q2a_axi_clk = { 3157 .halt_reg = 0x58018, 3158 .halt_check = BRANCH_HALT_VOTED, 3159 .clkr = { 3160 .enable_reg = 0x52018, 3161 .enable_mask = BIT(29), 3162 .hw.init = &(const struct clk_init_data) { 3163 .name = "gcc_pcie_3_slv_q2a_axi_clk", 3164 .ops = &clk_branch2_ops, 3165 }, 3166 }, 3167 }; 3168 3169 static struct clk_branch gcc_pcie_4_aux_clk = { 3170 .halt_reg = 0x6b038, 3171 .halt_check = BRANCH_HALT_VOTED, 3172 .clkr = { 3173 .enable_reg = 0x52008, 3174 .enable_mask = BIT(3), 3175 .hw.init = &(const struct clk_init_data) { 3176 .name = "gcc_pcie_4_aux_clk", 3177 .parent_hws = (const struct clk_hw*[]) { 3178 &gcc_pcie_4_aux_clk_src.clkr.hw, 3179 }, 3180 .num_parents = 1, 3181 .flags = CLK_SET_RATE_PARENT, 3182 .ops = &clk_branch2_ops, 3183 }, 3184 }, 3185 }; 3186 3187 static struct clk_branch gcc_pcie_4_cfg_ahb_clk = { 3188 .halt_reg = 0x6b034, 3189 .halt_check = BRANCH_HALT_VOTED, 3190 .hwcg_reg = 0x6b034, 3191 .hwcg_bit = 1, 3192 .clkr = { 3193 .enable_reg = 0x52008, 3194 .enable_mask = BIT(2), 3195 .hw.init = &(const struct clk_init_data) { 3196 .name = "gcc_pcie_4_cfg_ahb_clk", 3197 .ops = &clk_branch2_ops, 3198 }, 3199 }, 3200 }; 3201 3202 static struct clk_branch gcc_pcie_4_mstr_axi_clk = { 3203 .halt_reg = 0x6b028, 3204 .halt_check = BRANCH_HALT_SKIP, 3205 .hwcg_reg = 0x6b028, 3206 .hwcg_bit = 1, 3207 .clkr = { 3208 .enable_reg = 0x52008, 3209 .enable_mask = BIT(1), 3210 .hw.init = &(const struct clk_init_data) { 3211 .name = "gcc_pcie_4_mstr_axi_clk", 3212 .ops = &clk_branch2_ops, 3213 }, 3214 }, 3215 }; 3216 3217 static struct clk_branch gcc_pcie_4_phy_rchng_clk = { 3218 .halt_reg = 0x6b050, 3219 .halt_check = BRANCH_HALT_VOTED, 3220 .clkr = { 3221 .enable_reg = 0x52000, 3222 .enable_mask = BIT(22), 3223 .hw.init = &(const struct clk_init_data) { 3224 .name = "gcc_pcie_4_phy_rchng_clk", 3225 .parent_hws = (const struct clk_hw*[]) { 3226 &gcc_pcie_4_phy_rchng_clk_src.clkr.hw, 3227 }, 3228 .num_parents = 1, 3229 .flags = CLK_SET_RATE_PARENT, 3230 .ops = &clk_branch2_ops, 3231 }, 3232 }, 3233 }; 3234 3235 static struct clk_branch gcc_pcie_4_pipe_clk = { 3236 .halt_reg = 0x6b044, 3237 .halt_check = BRANCH_HALT_VOTED, 3238 .clkr = { 3239 .enable_reg = 0x52008, 3240 .enable_mask = BIT(4), 3241 .hw.init = &(const struct clk_init_data) { 3242 .name = "gcc_pcie_4_pipe_clk", 3243 .ops = &clk_branch2_ops, 3244 }, 3245 }, 3246 }; 3247 3248 static struct clk_branch gcc_pcie_4_pipediv2_clk = { 3249 .halt_reg = 0x6b054, 3250 .halt_check = BRANCH_HALT_VOTED, 3251 .clkr = { 3252 .enable_reg = 0x52010, 3253 .enable_mask = BIT(27), 3254 .hw.init = &(const struct clk_init_data) { 3255 .name = "gcc_pcie_4_pipediv2_clk", 3256 .parent_hws = (const struct clk_hw*[]) { 3257 &gcc_pcie_4_pipe_div_clk_src.clkr.hw, 3258 }, 3259 .num_parents = 1, 3260 .flags = CLK_SET_RATE_PARENT, 3261 .ops = &clk_branch2_ops, 3262 }, 3263 }, 3264 }; 3265 3266 static struct clk_branch gcc_pcie_4_slv_axi_clk = { 3267 .halt_reg = 0x6b01c, 3268 .halt_check = BRANCH_HALT_VOTED, 3269 .hwcg_reg = 0x6b01c, 3270 .hwcg_bit = 1, 3271 .clkr = { 3272 .enable_reg = 0x52008, 3273 .enable_mask = BIT(0), 3274 .hw.init = &(const struct clk_init_data) { 3275 .name = "gcc_pcie_4_slv_axi_clk", 3276 .ops = &clk_branch2_ops, 3277 }, 3278 }, 3279 }; 3280 3281 static struct clk_branch gcc_pcie_4_slv_q2a_axi_clk = { 3282 .halt_reg = 0x6b018, 3283 .halt_check = BRANCH_HALT_VOTED, 3284 .clkr = { 3285 .enable_reg = 0x52008, 3286 .enable_mask = BIT(5), 3287 .hw.init = &(const struct clk_init_data) { 3288 .name = "gcc_pcie_4_slv_q2a_axi_clk", 3289 .ops = &clk_branch2_ops, 3290 }, 3291 }, 3292 }; 3293 3294 static struct clk_branch gcc_pcie_5_aux_clk = { 3295 .halt_reg = 0x2f038, 3296 .halt_check = BRANCH_HALT_VOTED, 3297 .clkr = { 3298 .enable_reg = 0x52018, 3299 .enable_mask = BIT(16), 3300 .hw.init = &(const struct clk_init_data) { 3301 .name = "gcc_pcie_5_aux_clk", 3302 .parent_hws = (const struct clk_hw*[]) { 3303 &gcc_pcie_5_aux_clk_src.clkr.hw, 3304 }, 3305 .num_parents = 1, 3306 .flags = CLK_SET_RATE_PARENT, 3307 .ops = &clk_branch2_ops, 3308 }, 3309 }, 3310 }; 3311 3312 static struct clk_branch gcc_pcie_5_cfg_ahb_clk = { 3313 .halt_reg = 0x2f034, 3314 .halt_check = BRANCH_HALT_VOTED, 3315 .hwcg_reg = 0x2f034, 3316 .hwcg_bit = 1, 3317 .clkr = { 3318 .enable_reg = 0x52018, 3319 .enable_mask = BIT(15), 3320 .hw.init = &(const struct clk_init_data) { 3321 .name = "gcc_pcie_5_cfg_ahb_clk", 3322 .ops = &clk_branch2_ops, 3323 }, 3324 }, 3325 }; 3326 3327 static struct clk_branch gcc_pcie_5_mstr_axi_clk = { 3328 .halt_reg = 0x2f028, 3329 .halt_check = BRANCH_HALT_SKIP, 3330 .hwcg_reg = 0x2f028, 3331 .hwcg_bit = 1, 3332 .clkr = { 3333 .enable_reg = 0x52018, 3334 .enable_mask = BIT(14), 3335 .hw.init = &(const struct clk_init_data) { 3336 .name = "gcc_pcie_5_mstr_axi_clk", 3337 .ops = &clk_branch2_ops, 3338 }, 3339 }, 3340 }; 3341 3342 static struct clk_branch gcc_pcie_5_phy_rchng_clk = { 3343 .halt_reg = 0x2f050, 3344 .halt_check = BRANCH_HALT_VOTED, 3345 .clkr = { 3346 .enable_reg = 0x52018, 3347 .enable_mask = BIT(18), 3348 .hw.init = &(const struct clk_init_data) { 3349 .name = "gcc_pcie_5_phy_rchng_clk", 3350 .parent_hws = (const struct clk_hw*[]) { 3351 &gcc_pcie_5_phy_rchng_clk_src.clkr.hw, 3352 }, 3353 .num_parents = 1, 3354 .flags = CLK_SET_RATE_PARENT, 3355 .ops = &clk_branch2_ops, 3356 }, 3357 }, 3358 }; 3359 3360 static struct clk_branch gcc_pcie_5_pipe_clk = { 3361 .halt_reg = 0x2f044, 3362 .halt_check = BRANCH_HALT_VOTED, 3363 .clkr = { 3364 .enable_reg = 0x52018, 3365 .enable_mask = BIT(17), 3366 .hw.init = &(const struct clk_init_data) { 3367 .name = "gcc_pcie_5_pipe_clk", 3368 .ops = &clk_branch2_ops, 3369 }, 3370 }, 3371 }; 3372 3373 static struct clk_branch gcc_pcie_5_pipediv2_clk = { 3374 .halt_reg = 0x2f054, 3375 .halt_check = BRANCH_HALT_VOTED, 3376 .clkr = { 3377 .enable_reg = 0x52018, 3378 .enable_mask = BIT(19), 3379 .hw.init = &(const struct clk_init_data) { 3380 .name = "gcc_pcie_5_pipediv2_clk", 3381 .parent_hws = (const struct clk_hw*[]) { 3382 &gcc_pcie_5_pipe_div_clk_src.clkr.hw, 3383 }, 3384 .num_parents = 1, 3385 .flags = CLK_SET_RATE_PARENT, 3386 .ops = &clk_branch2_ops, 3387 }, 3388 }, 3389 }; 3390 3391 static struct clk_branch gcc_pcie_5_slv_axi_clk = { 3392 .halt_reg = 0x2f01c, 3393 .halt_check = BRANCH_HALT_VOTED, 3394 .hwcg_reg = 0x2f01c, 3395 .hwcg_bit = 1, 3396 .clkr = { 3397 .enable_reg = 0x52018, 3398 .enable_mask = BIT(13), 3399 .hw.init = &(const struct clk_init_data) { 3400 .name = "gcc_pcie_5_slv_axi_clk", 3401 .ops = &clk_branch2_ops, 3402 }, 3403 }, 3404 }; 3405 3406 static struct clk_branch gcc_pcie_5_slv_q2a_axi_clk = { 3407 .halt_reg = 0x2f018, 3408 .halt_check = BRANCH_HALT_VOTED, 3409 .clkr = { 3410 .enable_reg = 0x52018, 3411 .enable_mask = BIT(12), 3412 .hw.init = &(const struct clk_init_data) { 3413 .name = "gcc_pcie_5_slv_q2a_axi_clk", 3414 .ops = &clk_branch2_ops, 3415 }, 3416 }, 3417 }; 3418 3419 static struct clk_branch gcc_pcie_6a_aux_clk = { 3420 .halt_reg = 0x31038, 3421 .halt_check = BRANCH_HALT_VOTED, 3422 .clkr = { 3423 .enable_reg = 0x52018, 3424 .enable_mask = BIT(24), 3425 .hw.init = &(const struct clk_init_data) { 3426 .name = "gcc_pcie_6a_aux_clk", 3427 .parent_hws = (const struct clk_hw*[]) { 3428 &gcc_pcie_6a_aux_clk_src.clkr.hw, 3429 }, 3430 .num_parents = 1, 3431 .flags = CLK_SET_RATE_PARENT, 3432 .ops = &clk_branch2_ops, 3433 }, 3434 }, 3435 }; 3436 3437 static struct clk_branch gcc_pcie_6a_cfg_ahb_clk = { 3438 .halt_reg = 0x31034, 3439 .halt_check = BRANCH_HALT_VOTED, 3440 .hwcg_reg = 0x31034, 3441 .hwcg_bit = 1, 3442 .clkr = { 3443 .enable_reg = 0x52018, 3444 .enable_mask = BIT(23), 3445 .hw.init = &(const struct clk_init_data) { 3446 .name = "gcc_pcie_6a_cfg_ahb_clk", 3447 .ops = &clk_branch2_ops, 3448 }, 3449 }, 3450 }; 3451 3452 static struct clk_branch gcc_pcie_6a_mstr_axi_clk = { 3453 .halt_reg = 0x31028, 3454 .halt_check = BRANCH_HALT_SKIP, 3455 .hwcg_reg = 0x31028, 3456 .hwcg_bit = 1, 3457 .clkr = { 3458 .enable_reg = 0x52018, 3459 .enable_mask = BIT(22), 3460 .hw.init = &(const struct clk_init_data) { 3461 .name = "gcc_pcie_6a_mstr_axi_clk", 3462 .ops = &clk_branch2_ops, 3463 }, 3464 }, 3465 }; 3466 3467 static struct clk_branch gcc_pcie_6a_phy_aux_clk = { 3468 .halt_reg = 0x31044, 3469 .halt_check = BRANCH_HALT_VOTED, 3470 .clkr = { 3471 .enable_reg = 0x52018, 3472 .enable_mask = BIT(25), 3473 .hw.init = &(const struct clk_init_data) { 3474 .name = "gcc_pcie_6a_phy_aux_clk", 3475 .ops = &clk_branch2_ops, 3476 }, 3477 }, 3478 }; 3479 3480 static struct clk_branch gcc_pcie_6a_phy_rchng_clk = { 3481 .halt_reg = 0x3105c, 3482 .halt_check = BRANCH_HALT_VOTED, 3483 .clkr = { 3484 .enable_reg = 0x52018, 3485 .enable_mask = BIT(27), 3486 .hw.init = &(const struct clk_init_data) { 3487 .name = "gcc_pcie_6a_phy_rchng_clk", 3488 .parent_hws = (const struct clk_hw*[]) { 3489 &gcc_pcie_6a_phy_rchng_clk_src.clkr.hw, 3490 }, 3491 .num_parents = 1, 3492 .flags = CLK_SET_RATE_PARENT, 3493 .ops = &clk_branch2_ops, 3494 }, 3495 }, 3496 }; 3497 3498 static struct clk_branch gcc_pcie_6a_pipe_clk = { 3499 .halt_reg = 0x31050, 3500 .halt_check = BRANCH_HALT_VOTED, 3501 .clkr = { 3502 .enable_reg = 0x52018, 3503 .enable_mask = BIT(26), 3504 .hw.init = &(const struct clk_init_data) { 3505 .name = "gcc_pcie_6a_pipe_clk", 3506 .ops = &clk_branch2_ops, 3507 }, 3508 }, 3509 }; 3510 3511 static struct clk_branch gcc_pcie_6a_pipediv2_clk = { 3512 .halt_reg = 0x31060, 3513 .halt_check = BRANCH_HALT_VOTED, 3514 .clkr = { 3515 .enable_reg = 0x52018, 3516 .enable_mask = BIT(28), 3517 .hw.init = &(const struct clk_init_data) { 3518 .name = "gcc_pcie_6a_pipediv2_clk", 3519 .parent_hws = (const struct clk_hw*[]) { 3520 &gcc_pcie_6a_pipe_div_clk_src.clkr.hw, 3521 }, 3522 .num_parents = 1, 3523 .flags = CLK_SET_RATE_PARENT, 3524 .ops = &clk_branch2_ops, 3525 }, 3526 }, 3527 }; 3528 3529 static struct clk_branch gcc_pcie_6a_slv_axi_clk = { 3530 .halt_reg = 0x3101c, 3531 .halt_check = BRANCH_HALT_VOTED, 3532 .hwcg_reg = 0x3101c, 3533 .hwcg_bit = 1, 3534 .clkr = { 3535 .enable_reg = 0x52018, 3536 .enable_mask = BIT(21), 3537 .hw.init = &(const struct clk_init_data) { 3538 .name = "gcc_pcie_6a_slv_axi_clk", 3539 .ops = &clk_branch2_ops, 3540 }, 3541 }, 3542 }; 3543 3544 static struct clk_branch gcc_pcie_6a_slv_q2a_axi_clk = { 3545 .halt_reg = 0x31018, 3546 .halt_check = BRANCH_HALT_VOTED, 3547 .clkr = { 3548 .enable_reg = 0x52018, 3549 .enable_mask = BIT(20), 3550 .hw.init = &(const struct clk_init_data) { 3551 .name = "gcc_pcie_6a_slv_q2a_axi_clk", 3552 .ops = &clk_branch2_ops, 3553 }, 3554 }, 3555 }; 3556 3557 static struct clk_branch gcc_pcie_6b_aux_clk = { 3558 .halt_reg = 0x8d038, 3559 .halt_check = BRANCH_HALT_VOTED, 3560 .clkr = { 3561 .enable_reg = 0x52000, 3562 .enable_mask = BIT(29), 3563 .hw.init = &(const struct clk_init_data) { 3564 .name = "gcc_pcie_6b_aux_clk", 3565 .parent_hws = (const struct clk_hw*[]) { 3566 &gcc_pcie_6b_aux_clk_src.clkr.hw, 3567 }, 3568 .num_parents = 1, 3569 .flags = CLK_SET_RATE_PARENT, 3570 .ops = &clk_branch2_ops, 3571 }, 3572 }, 3573 }; 3574 3575 static struct clk_branch gcc_pcie_6b_cfg_ahb_clk = { 3576 .halt_reg = 0x8d034, 3577 .halt_check = BRANCH_HALT_VOTED, 3578 .hwcg_reg = 0x8d034, 3579 .hwcg_bit = 1, 3580 .clkr = { 3581 .enable_reg = 0x52000, 3582 .enable_mask = BIT(28), 3583 .hw.init = &(const struct clk_init_data) { 3584 .name = "gcc_pcie_6b_cfg_ahb_clk", 3585 .ops = &clk_branch2_ops, 3586 }, 3587 }, 3588 }; 3589 3590 static struct clk_branch gcc_pcie_6b_mstr_axi_clk = { 3591 .halt_reg = 0x8d028, 3592 .halt_check = BRANCH_HALT_SKIP, 3593 .hwcg_reg = 0x8d028, 3594 .hwcg_bit = 1, 3595 .clkr = { 3596 .enable_reg = 0x52000, 3597 .enable_mask = BIT(27), 3598 .hw.init = &(const struct clk_init_data) { 3599 .name = "gcc_pcie_6b_mstr_axi_clk", 3600 .ops = &clk_branch2_ops, 3601 }, 3602 }, 3603 }; 3604 3605 static struct clk_branch gcc_pcie_6b_phy_aux_clk = { 3606 .halt_reg = 0x8d044, 3607 .halt_check = BRANCH_HALT_VOTED, 3608 .clkr = { 3609 .enable_reg = 0x52000, 3610 .enable_mask = BIT(24), 3611 .hw.init = &(const struct clk_init_data) { 3612 .name = "gcc_pcie_6b_phy_aux_clk", 3613 .ops = &clk_branch2_ops, 3614 }, 3615 }, 3616 }; 3617 3618 static struct clk_branch gcc_pcie_6b_phy_rchng_clk = { 3619 .halt_reg = 0x8d05c, 3620 .halt_check = BRANCH_HALT_VOTED, 3621 .clkr = { 3622 .enable_reg = 0x52000, 3623 .enable_mask = BIT(23), 3624 .hw.init = &(const struct clk_init_data) { 3625 .name = "gcc_pcie_6b_phy_rchng_clk", 3626 .parent_hws = (const struct clk_hw*[]) { 3627 &gcc_pcie_6b_phy_rchng_clk_src.clkr.hw, 3628 }, 3629 .num_parents = 1, 3630 .flags = CLK_SET_RATE_PARENT, 3631 .ops = &clk_branch2_ops, 3632 }, 3633 }, 3634 }; 3635 3636 static struct clk_branch gcc_pcie_6b_pipe_clk = { 3637 .halt_reg = 0x8d050, 3638 .halt_check = BRANCH_HALT_VOTED, 3639 .clkr = { 3640 .enable_reg = 0x52000, 3641 .enable_mask = BIT(30), 3642 .hw.init = &(const struct clk_init_data) { 3643 .name = "gcc_pcie_6b_pipe_clk", 3644 .ops = &clk_branch2_ops, 3645 }, 3646 }, 3647 }; 3648 3649 static struct clk_branch gcc_pcie_6b_pipediv2_clk = { 3650 .halt_reg = 0x8d060, 3651 .halt_check = BRANCH_HALT_VOTED, 3652 .clkr = { 3653 .enable_reg = 0x52010, 3654 .enable_mask = BIT(28), 3655 .hw.init = &(const struct clk_init_data) { 3656 .name = "gcc_pcie_6b_pipediv2_clk", 3657 .parent_hws = (const struct clk_hw*[]) { 3658 &gcc_pcie_6b_pipe_div_clk_src.clkr.hw, 3659 }, 3660 .num_parents = 1, 3661 .flags = CLK_SET_RATE_PARENT, 3662 .ops = &clk_branch2_ops, 3663 }, 3664 }, 3665 }; 3666 3667 static struct clk_branch gcc_pcie_6b_slv_axi_clk = { 3668 .halt_reg = 0x8d01c, 3669 .halt_check = BRANCH_HALT_VOTED, 3670 .hwcg_reg = 0x8d01c, 3671 .hwcg_bit = 1, 3672 .clkr = { 3673 .enable_reg = 0x52000, 3674 .enable_mask = BIT(26), 3675 .hw.init = &(const struct clk_init_data) { 3676 .name = "gcc_pcie_6b_slv_axi_clk", 3677 .ops = &clk_branch2_ops, 3678 }, 3679 }, 3680 }; 3681 3682 static struct clk_branch gcc_pcie_6b_slv_q2a_axi_clk = { 3683 .halt_reg = 0x8d018, 3684 .halt_check = BRANCH_HALT_VOTED, 3685 .clkr = { 3686 .enable_reg = 0x52000, 3687 .enable_mask = BIT(25), 3688 .hw.init = &(const struct clk_init_data) { 3689 .name = "gcc_pcie_6b_slv_q2a_axi_clk", 3690 .ops = &clk_branch2_ops, 3691 }, 3692 }, 3693 }; 3694 3695 static struct clk_branch gcc_pcie_rscc_ahb_clk = { 3696 .halt_reg = 0xa4008, 3697 .halt_check = BRANCH_HALT_VOTED, 3698 .hwcg_reg = 0xa4008, 3699 .hwcg_bit = 1, 3700 .clkr = { 3701 .enable_reg = 0x52028, 3702 .enable_mask = BIT(18), 3703 .hw.init = &(const struct clk_init_data) { 3704 .name = "gcc_pcie_rscc_ahb_clk", 3705 .ops = &clk_branch2_ops, 3706 }, 3707 }, 3708 }; 3709 3710 static struct clk_branch gcc_pcie_rscc_xo_clk = { 3711 .halt_reg = 0xa4004, 3712 .halt_check = BRANCH_HALT_VOTED, 3713 .clkr = { 3714 .enable_reg = 0x52028, 3715 .enable_mask = BIT(17), 3716 .hw.init = &(const struct clk_init_data) { 3717 .name = "gcc_pcie_rscc_xo_clk", 3718 .parent_hws = (const struct clk_hw*[]) { 3719 &gcc_pcie_rscc_xo_clk_src.clkr.hw, 3720 }, 3721 .num_parents = 1, 3722 .flags = CLK_SET_RATE_PARENT, 3723 .ops = &clk_branch2_ops, 3724 }, 3725 }, 3726 }; 3727 3728 static struct clk_branch gcc_pdm2_clk = { 3729 .halt_reg = 0x3300c, 3730 .halt_check = BRANCH_HALT, 3731 .clkr = { 3732 .enable_reg = 0x3300c, 3733 .enable_mask = BIT(0), 3734 .hw.init = &(const struct clk_init_data) { 3735 .name = "gcc_pdm2_clk", 3736 .parent_hws = (const struct clk_hw*[]) { 3737 &gcc_pdm2_clk_src.clkr.hw, 3738 }, 3739 .num_parents = 1, 3740 .flags = CLK_SET_RATE_PARENT, 3741 .ops = &clk_branch2_ops, 3742 }, 3743 }, 3744 }; 3745 3746 static struct clk_branch gcc_pdm_ahb_clk = { 3747 .halt_reg = 0x33004, 3748 .halt_check = BRANCH_HALT_VOTED, 3749 .hwcg_reg = 0x33004, 3750 .hwcg_bit = 1, 3751 .clkr = { 3752 .enable_reg = 0x33004, 3753 .enable_mask = BIT(0), 3754 .hw.init = &(const struct clk_init_data) { 3755 .name = "gcc_pdm_ahb_clk", 3756 .ops = &clk_branch2_ops, 3757 }, 3758 }, 3759 }; 3760 3761 static struct clk_branch gcc_pdm_xo4_clk = { 3762 .halt_reg = 0x33008, 3763 .halt_check = BRANCH_HALT, 3764 .clkr = { 3765 .enable_reg = 0x33008, 3766 .enable_mask = BIT(0), 3767 .hw.init = &(const struct clk_init_data) { 3768 .name = "gcc_pdm_xo4_clk", 3769 .ops = &clk_branch2_ops, 3770 }, 3771 }, 3772 }; 3773 3774 static struct clk_branch gcc_qmip_av1e_ahb_clk = { 3775 .halt_reg = 0x4a018, 3776 .halt_check = BRANCH_HALT_VOTED, 3777 .hwcg_reg = 0x4a018, 3778 .hwcg_bit = 1, 3779 .clkr = { 3780 .enable_reg = 0x4a018, 3781 .enable_mask = BIT(0), 3782 .hw.init = &(const struct clk_init_data) { 3783 .name = "gcc_qmip_av1e_ahb_clk", 3784 .ops = &clk_branch2_ops, 3785 }, 3786 }, 3787 }; 3788 3789 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 3790 .halt_reg = 0x26008, 3791 .halt_check = BRANCH_HALT_VOTED, 3792 .hwcg_reg = 0x26008, 3793 .hwcg_bit = 1, 3794 .clkr = { 3795 .enable_reg = 0x26008, 3796 .enable_mask = BIT(0), 3797 .hw.init = &(const struct clk_init_data) { 3798 .name = "gcc_qmip_camera_nrt_ahb_clk", 3799 .ops = &clk_branch2_ops, 3800 }, 3801 }, 3802 }; 3803 3804 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 3805 .halt_reg = 0x2600c, 3806 .halt_check = BRANCH_HALT_VOTED, 3807 .hwcg_reg = 0x2600c, 3808 .hwcg_bit = 1, 3809 .clkr = { 3810 .enable_reg = 0x2600c, 3811 .enable_mask = BIT(0), 3812 .hw.init = &(const struct clk_init_data) { 3813 .name = "gcc_qmip_camera_rt_ahb_clk", 3814 .ops = &clk_branch2_ops, 3815 }, 3816 }, 3817 }; 3818 3819 static struct clk_branch gcc_qmip_disp_ahb_clk = { 3820 .halt_reg = 0x27008, 3821 .halt_check = BRANCH_HALT_VOTED, 3822 .hwcg_reg = 0x27008, 3823 .hwcg_bit = 1, 3824 .clkr = { 3825 .enable_reg = 0x27008, 3826 .enable_mask = BIT(0), 3827 .hw.init = &(const struct clk_init_data) { 3828 .name = "gcc_qmip_disp_ahb_clk", 3829 .ops = &clk_branch2_ops, 3830 }, 3831 }, 3832 }; 3833 3834 static struct clk_branch gcc_qmip_gpu_ahb_clk = { 3835 .halt_reg = 0x71008, 3836 .halt_check = BRANCH_HALT_VOTED, 3837 .hwcg_reg = 0x71008, 3838 .hwcg_bit = 1, 3839 .clkr = { 3840 .enable_reg = 0x71008, 3841 .enable_mask = BIT(0), 3842 .hw.init = &(const struct clk_init_data) { 3843 .name = "gcc_qmip_gpu_ahb_clk", 3844 .ops = &clk_branch2_ops, 3845 }, 3846 }, 3847 }; 3848 3849 static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = { 3850 .halt_reg = 0x32014, 3851 .halt_check = BRANCH_HALT_VOTED, 3852 .hwcg_reg = 0x32014, 3853 .hwcg_bit = 1, 3854 .clkr = { 3855 .enable_reg = 0x32014, 3856 .enable_mask = BIT(0), 3857 .hw.init = &(const struct clk_init_data) { 3858 .name = "gcc_qmip_video_cv_cpu_ahb_clk", 3859 .ops = &clk_branch2_ops, 3860 }, 3861 }, 3862 }; 3863 3864 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 3865 .halt_reg = 0x32008, 3866 .halt_check = BRANCH_HALT_VOTED, 3867 .hwcg_reg = 0x32008, 3868 .hwcg_bit = 1, 3869 .clkr = { 3870 .enable_reg = 0x32008, 3871 .enable_mask = BIT(0), 3872 .hw.init = &(const struct clk_init_data) { 3873 .name = "gcc_qmip_video_cvp_ahb_clk", 3874 .ops = &clk_branch2_ops, 3875 }, 3876 }, 3877 }; 3878 3879 static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = { 3880 .halt_reg = 0x32010, 3881 .halt_check = BRANCH_HALT_VOTED, 3882 .hwcg_reg = 0x32010, 3883 .hwcg_bit = 1, 3884 .clkr = { 3885 .enable_reg = 0x32010, 3886 .enable_mask = BIT(0), 3887 .hw.init = &(const struct clk_init_data) { 3888 .name = "gcc_qmip_video_v_cpu_ahb_clk", 3889 .ops = &clk_branch2_ops, 3890 }, 3891 }, 3892 }; 3893 3894 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 3895 .halt_reg = 0x3200c, 3896 .halt_check = BRANCH_HALT_VOTED, 3897 .hwcg_reg = 0x3200c, 3898 .hwcg_bit = 1, 3899 .clkr = { 3900 .enable_reg = 0x3200c, 3901 .enable_mask = BIT(0), 3902 .hw.init = &(const struct clk_init_data) { 3903 .name = "gcc_qmip_video_vcodec_ahb_clk", 3904 .ops = &clk_branch2_ops, 3905 }, 3906 }, 3907 }; 3908 3909 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 3910 .halt_reg = 0x23018, 3911 .halt_check = BRANCH_HALT_VOTED, 3912 .clkr = { 3913 .enable_reg = 0x52020, 3914 .enable_mask = BIT(9), 3915 .hw.init = &(const struct clk_init_data) { 3916 .name = "gcc_qupv3_wrap0_core_2x_clk", 3917 .ops = &clk_branch2_ops, 3918 }, 3919 }, 3920 }; 3921 3922 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 3923 .halt_reg = 0x23008, 3924 .halt_check = BRANCH_HALT_VOTED, 3925 .clkr = { 3926 .enable_reg = 0x52020, 3927 .enable_mask = BIT(8), 3928 .hw.init = &(const struct clk_init_data) { 3929 .name = "gcc_qupv3_wrap0_core_clk", 3930 .ops = &clk_branch2_ops, 3931 }, 3932 }, 3933 }; 3934 3935 static struct clk_branch gcc_qupv3_wrap0_qspi_s2_clk = { 3936 .halt_reg = 0x42280, 3937 .halt_check = BRANCH_HALT_VOTED, 3938 .clkr = { 3939 .enable_reg = 0x52028, 3940 .enable_mask = BIT(2), 3941 .hw.init = &(const struct clk_init_data) { 3942 .name = "gcc_qupv3_wrap0_qspi_s2_clk", 3943 .parent_hws = (const struct clk_hw*[]) { 3944 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 3945 }, 3946 .num_parents = 1, 3947 .flags = CLK_SET_RATE_PARENT, 3948 .ops = &clk_branch2_ops, 3949 }, 3950 }, 3951 }; 3952 3953 static struct clk_branch gcc_qupv3_wrap0_qspi_s3_clk = { 3954 .halt_reg = 0x423c0, 3955 .halt_check = BRANCH_HALT_VOTED, 3956 .clkr = { 3957 .enable_reg = 0x52028, 3958 .enable_mask = BIT(3), 3959 .hw.init = &(const struct clk_init_data) { 3960 .name = "gcc_qupv3_wrap0_qspi_s3_clk", 3961 .parent_hws = (const struct clk_hw*[]) { 3962 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 3963 }, 3964 .num_parents = 1, 3965 .flags = CLK_SET_RATE_PARENT, 3966 .ops = &clk_branch2_ops, 3967 }, 3968 }, 3969 }; 3970 3971 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 3972 .halt_reg = 0x42004, 3973 .halt_check = BRANCH_HALT_VOTED, 3974 .clkr = { 3975 .enable_reg = 0x52020, 3976 .enable_mask = BIT(10), 3977 .hw.init = &(const struct clk_init_data) { 3978 .name = "gcc_qupv3_wrap0_s0_clk", 3979 .parent_hws = (const struct clk_hw*[]) { 3980 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 3981 }, 3982 .num_parents = 1, 3983 .flags = CLK_SET_RATE_PARENT, 3984 .ops = &clk_branch2_ops, 3985 }, 3986 }, 3987 }; 3988 3989 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 3990 .halt_reg = 0x4213c, 3991 .halt_check = BRANCH_HALT_VOTED, 3992 .clkr = { 3993 .enable_reg = 0x52020, 3994 .enable_mask = BIT(11), 3995 .hw.init = &(const struct clk_init_data) { 3996 .name = "gcc_qupv3_wrap0_s1_clk", 3997 .parent_hws = (const struct clk_hw*[]) { 3998 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 3999 }, 4000 .num_parents = 1, 4001 .flags = CLK_SET_RATE_PARENT, 4002 .ops = &clk_branch2_ops, 4003 }, 4004 }, 4005 }; 4006 4007 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 4008 .halt_reg = 0x42274, 4009 .halt_check = BRANCH_HALT_VOTED, 4010 .clkr = { 4011 .enable_reg = 0x52020, 4012 .enable_mask = BIT(12), 4013 .hw.init = &(const struct clk_init_data) { 4014 .name = "gcc_qupv3_wrap0_s2_clk", 4015 .parent_hws = (const struct clk_hw*[]) { 4016 &gcc_qupv3_wrap0_s2_div_clk_src.clkr.hw, 4017 }, 4018 .num_parents = 1, 4019 .flags = CLK_SET_RATE_PARENT, 4020 .ops = &clk_branch2_ops, 4021 }, 4022 }, 4023 }; 4024 4025 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 4026 .halt_reg = 0x423b4, 4027 .halt_check = BRANCH_HALT_VOTED, 4028 .clkr = { 4029 .enable_reg = 0x52020, 4030 .enable_mask = BIT(13), 4031 .hw.init = &(const struct clk_init_data) { 4032 .name = "gcc_qupv3_wrap0_s3_clk", 4033 .parent_hws = (const struct clk_hw*[]) { 4034 &gcc_qupv3_wrap0_s3_div_clk_src.clkr.hw, 4035 }, 4036 .num_parents = 1, 4037 .flags = CLK_SET_RATE_PARENT, 4038 .ops = &clk_branch2_ops, 4039 }, 4040 }, 4041 }; 4042 4043 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 4044 .halt_reg = 0x424f4, 4045 .halt_check = BRANCH_HALT_VOTED, 4046 .clkr = { 4047 .enable_reg = 0x52020, 4048 .enable_mask = BIT(14), 4049 .hw.init = &(const struct clk_init_data) { 4050 .name = "gcc_qupv3_wrap0_s4_clk", 4051 .parent_hws = (const struct clk_hw*[]) { 4052 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 4053 }, 4054 .num_parents = 1, 4055 .flags = CLK_SET_RATE_PARENT, 4056 .ops = &clk_branch2_ops, 4057 }, 4058 }, 4059 }; 4060 4061 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 4062 .halt_reg = 0x4262c, 4063 .halt_check = BRANCH_HALT_VOTED, 4064 .clkr = { 4065 .enable_reg = 0x52020, 4066 .enable_mask = BIT(15), 4067 .hw.init = &(const struct clk_init_data) { 4068 .name = "gcc_qupv3_wrap0_s5_clk", 4069 .parent_hws = (const struct clk_hw*[]) { 4070 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 4071 }, 4072 .num_parents = 1, 4073 .flags = CLK_SET_RATE_PARENT, 4074 .ops = &clk_branch2_ops, 4075 }, 4076 }, 4077 }; 4078 4079 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 4080 .halt_reg = 0x42764, 4081 .halt_check = BRANCH_HALT_VOTED, 4082 .clkr = { 4083 .enable_reg = 0x52020, 4084 .enable_mask = BIT(16), 4085 .hw.init = &(const struct clk_init_data) { 4086 .name = "gcc_qupv3_wrap0_s6_clk", 4087 .parent_hws = (const struct clk_hw*[]) { 4088 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 4089 }, 4090 .num_parents = 1, 4091 .flags = CLK_SET_RATE_PARENT, 4092 .ops = &clk_branch2_ops, 4093 }, 4094 }, 4095 }; 4096 4097 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 4098 .halt_reg = 0x4289c, 4099 .halt_check = BRANCH_HALT_VOTED, 4100 .clkr = { 4101 .enable_reg = 0x52020, 4102 .enable_mask = BIT(17), 4103 .hw.init = &(const struct clk_init_data) { 4104 .name = "gcc_qupv3_wrap0_s7_clk", 4105 .parent_hws = (const struct clk_hw*[]) { 4106 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, 4107 }, 4108 .num_parents = 1, 4109 .flags = CLK_SET_RATE_PARENT, 4110 .ops = &clk_branch2_ops, 4111 }, 4112 }, 4113 }; 4114 4115 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 4116 .halt_reg = 0x23168, 4117 .halt_check = BRANCH_HALT_VOTED, 4118 .clkr = { 4119 .enable_reg = 0x52008, 4120 .enable_mask = BIT(18), 4121 .hw.init = &(const struct clk_init_data) { 4122 .name = "gcc_qupv3_wrap1_core_2x_clk", 4123 .ops = &clk_branch2_ops, 4124 }, 4125 }, 4126 }; 4127 4128 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 4129 .halt_reg = 0x23158, 4130 .halt_check = BRANCH_HALT_VOTED, 4131 .clkr = { 4132 .enable_reg = 0x52008, 4133 .enable_mask = BIT(19), 4134 .hw.init = &(const struct clk_init_data) { 4135 .name = "gcc_qupv3_wrap1_core_clk", 4136 .ops = &clk_branch2_ops, 4137 }, 4138 }, 4139 }; 4140 4141 static struct clk_branch gcc_qupv3_wrap1_qspi_s2_clk = { 4142 .halt_reg = 0x18280, 4143 .halt_check = BRANCH_HALT_VOTED, 4144 .clkr = { 4145 .enable_reg = 0x52028, 4146 .enable_mask = BIT(4), 4147 .hw.init = &(const struct clk_init_data) { 4148 .name = "gcc_qupv3_wrap1_qspi_s2_clk", 4149 .parent_hws = (const struct clk_hw*[]) { 4150 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 4151 }, 4152 .num_parents = 1, 4153 .flags = CLK_SET_RATE_PARENT, 4154 .ops = &clk_branch2_ops, 4155 }, 4156 }, 4157 }; 4158 4159 static struct clk_branch gcc_qupv3_wrap1_qspi_s3_clk = { 4160 .halt_reg = 0x183c0, 4161 .halt_check = BRANCH_HALT_VOTED, 4162 .clkr = { 4163 .enable_reg = 0x52028, 4164 .enable_mask = BIT(5), 4165 .hw.init = &(const struct clk_init_data) { 4166 .name = "gcc_qupv3_wrap1_qspi_s3_clk", 4167 .parent_hws = (const struct clk_hw*[]) { 4168 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 4169 }, 4170 .num_parents = 1, 4171 .flags = CLK_SET_RATE_PARENT, 4172 .ops = &clk_branch2_ops, 4173 }, 4174 }, 4175 }; 4176 4177 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 4178 .halt_reg = 0x18004, 4179 .halt_check = BRANCH_HALT_VOTED, 4180 .clkr = { 4181 .enable_reg = 0x52008, 4182 .enable_mask = BIT(22), 4183 .hw.init = &(const struct clk_init_data) { 4184 .name = "gcc_qupv3_wrap1_s0_clk", 4185 .parent_hws = (const struct clk_hw*[]) { 4186 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 4187 }, 4188 .num_parents = 1, 4189 .flags = CLK_SET_RATE_PARENT, 4190 .ops = &clk_branch2_ops, 4191 }, 4192 }, 4193 }; 4194 4195 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 4196 .halt_reg = 0x1813c, 4197 .halt_check = BRANCH_HALT_VOTED, 4198 .clkr = { 4199 .enable_reg = 0x52008, 4200 .enable_mask = BIT(23), 4201 .hw.init = &(const struct clk_init_data) { 4202 .name = "gcc_qupv3_wrap1_s1_clk", 4203 .parent_hws = (const struct clk_hw*[]) { 4204 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 4205 }, 4206 .num_parents = 1, 4207 .flags = CLK_SET_RATE_PARENT, 4208 .ops = &clk_branch2_ops, 4209 }, 4210 }, 4211 }; 4212 4213 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 4214 .halt_reg = 0x18274, 4215 .halt_check = BRANCH_HALT_VOTED, 4216 .clkr = { 4217 .enable_reg = 0x52008, 4218 .enable_mask = BIT(24), 4219 .hw.init = &(const struct clk_init_data) { 4220 .name = "gcc_qupv3_wrap1_s2_clk", 4221 .parent_hws = (const struct clk_hw*[]) { 4222 &gcc_qupv3_wrap1_s2_div_clk_src.clkr.hw, 4223 }, 4224 .num_parents = 1, 4225 .flags = CLK_SET_RATE_PARENT, 4226 .ops = &clk_branch2_ops, 4227 }, 4228 }, 4229 }; 4230 4231 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 4232 .halt_reg = 0x183b4, 4233 .halt_check = BRANCH_HALT_VOTED, 4234 .clkr = { 4235 .enable_reg = 0x52008, 4236 .enable_mask = BIT(25), 4237 .hw.init = &(const struct clk_init_data) { 4238 .name = "gcc_qupv3_wrap1_s3_clk", 4239 .parent_hws = (const struct clk_hw*[]) { 4240 &gcc_qupv3_wrap1_s3_div_clk_src.clkr.hw, 4241 }, 4242 .num_parents = 1, 4243 .flags = CLK_SET_RATE_PARENT, 4244 .ops = &clk_branch2_ops, 4245 }, 4246 }, 4247 }; 4248 4249 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 4250 .halt_reg = 0x184f4, 4251 .halt_check = BRANCH_HALT_VOTED, 4252 .clkr = { 4253 .enable_reg = 0x52008, 4254 .enable_mask = BIT(26), 4255 .hw.init = &(const struct clk_init_data) { 4256 .name = "gcc_qupv3_wrap1_s4_clk", 4257 .parent_hws = (const struct clk_hw*[]) { 4258 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 4259 }, 4260 .num_parents = 1, 4261 .flags = CLK_SET_RATE_PARENT, 4262 .ops = &clk_branch2_ops, 4263 }, 4264 }, 4265 }; 4266 4267 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 4268 .halt_reg = 0x1862c, 4269 .halt_check = BRANCH_HALT_VOTED, 4270 .clkr = { 4271 .enable_reg = 0x52008, 4272 .enable_mask = BIT(27), 4273 .hw.init = &(const struct clk_init_data) { 4274 .name = "gcc_qupv3_wrap1_s5_clk", 4275 .parent_hws = (const struct clk_hw*[]) { 4276 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 4277 }, 4278 .num_parents = 1, 4279 .flags = CLK_SET_RATE_PARENT, 4280 .ops = &clk_branch2_ops, 4281 }, 4282 }, 4283 }; 4284 4285 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 4286 .halt_reg = 0x18764, 4287 .halt_check = BRANCH_HALT_VOTED, 4288 .clkr = { 4289 .enable_reg = 0x52008, 4290 .enable_mask = BIT(28), 4291 .hw.init = &(const struct clk_init_data) { 4292 .name = "gcc_qupv3_wrap1_s6_clk", 4293 .parent_hws = (const struct clk_hw*[]) { 4294 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 4295 }, 4296 .num_parents = 1, 4297 .flags = CLK_SET_RATE_PARENT, 4298 .ops = &clk_branch2_ops, 4299 }, 4300 }, 4301 }; 4302 4303 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 4304 .halt_reg = 0x1889c, 4305 .halt_check = BRANCH_HALT_VOTED, 4306 .clkr = { 4307 .enable_reg = 0x52010, 4308 .enable_mask = BIT(16), 4309 .hw.init = &(const struct clk_init_data) { 4310 .name = "gcc_qupv3_wrap1_s7_clk", 4311 .parent_hws = (const struct clk_hw*[]) { 4312 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 4313 }, 4314 .num_parents = 1, 4315 .flags = CLK_SET_RATE_PARENT, 4316 .ops = &clk_branch2_ops, 4317 }, 4318 }, 4319 }; 4320 4321 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { 4322 .halt_reg = 0x232b8, 4323 .halt_check = BRANCH_HALT_VOTED, 4324 .clkr = { 4325 .enable_reg = 0x52010, 4326 .enable_mask = BIT(3), 4327 .hw.init = &(const struct clk_init_data) { 4328 .name = "gcc_qupv3_wrap2_core_2x_clk", 4329 .ops = &clk_branch2_ops, 4330 }, 4331 }, 4332 }; 4333 4334 static struct clk_branch gcc_qupv3_wrap2_core_clk = { 4335 .halt_reg = 0x232a8, 4336 .halt_check = BRANCH_HALT_VOTED, 4337 .clkr = { 4338 .enable_reg = 0x52010, 4339 .enable_mask = BIT(0), 4340 .hw.init = &(const struct clk_init_data) { 4341 .name = "gcc_qupv3_wrap2_core_clk", 4342 .ops = &clk_branch2_ops, 4343 }, 4344 }, 4345 }; 4346 4347 static struct clk_branch gcc_qupv3_wrap2_qspi_s2_clk = { 4348 .halt_reg = 0x1e280, 4349 .halt_check = BRANCH_HALT_VOTED, 4350 .clkr = { 4351 .enable_reg = 0x52028, 4352 .enable_mask = BIT(6), 4353 .hw.init = &(const struct clk_init_data) { 4354 .name = "gcc_qupv3_wrap2_qspi_s2_clk", 4355 .parent_hws = (const struct clk_hw*[]) { 4356 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 4357 }, 4358 .num_parents = 1, 4359 .flags = CLK_SET_RATE_PARENT, 4360 .ops = &clk_branch2_ops, 4361 }, 4362 }, 4363 }; 4364 4365 static struct clk_branch gcc_qupv3_wrap2_qspi_s3_clk = { 4366 .halt_reg = 0x1e3c0, 4367 .halt_check = BRANCH_HALT_VOTED, 4368 .clkr = { 4369 .enable_reg = 0x52028, 4370 .enable_mask = BIT(7), 4371 .hw.init = &(const struct clk_init_data) { 4372 .name = "gcc_qupv3_wrap2_qspi_s3_clk", 4373 .parent_hws = (const struct clk_hw*[]) { 4374 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 4375 }, 4376 .num_parents = 1, 4377 .flags = CLK_SET_RATE_PARENT, 4378 .ops = &clk_branch2_ops, 4379 }, 4380 }, 4381 }; 4382 4383 static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 4384 .halt_reg = 0x1e004, 4385 .halt_check = BRANCH_HALT_VOTED, 4386 .clkr = { 4387 .enable_reg = 0x52010, 4388 .enable_mask = BIT(4), 4389 .hw.init = &(const struct clk_init_data) { 4390 .name = "gcc_qupv3_wrap2_s0_clk", 4391 .parent_hws = (const struct clk_hw*[]) { 4392 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 4393 }, 4394 .num_parents = 1, 4395 .flags = CLK_SET_RATE_PARENT, 4396 .ops = &clk_branch2_ops, 4397 }, 4398 }, 4399 }; 4400 4401 static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 4402 .halt_reg = 0x1e13c, 4403 .halt_check = BRANCH_HALT_VOTED, 4404 .clkr = { 4405 .enable_reg = 0x52010, 4406 .enable_mask = BIT(5), 4407 .hw.init = &(const struct clk_init_data) { 4408 .name = "gcc_qupv3_wrap2_s1_clk", 4409 .parent_hws = (const struct clk_hw*[]) { 4410 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 4411 }, 4412 .num_parents = 1, 4413 .flags = CLK_SET_RATE_PARENT, 4414 .ops = &clk_branch2_ops, 4415 }, 4416 }, 4417 }; 4418 4419 static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 4420 .halt_reg = 0x1e274, 4421 .halt_check = BRANCH_HALT_VOTED, 4422 .clkr = { 4423 .enable_reg = 0x52010, 4424 .enable_mask = BIT(6), 4425 .hw.init = &(const struct clk_init_data) { 4426 .name = "gcc_qupv3_wrap2_s2_clk", 4427 .parent_hws = (const struct clk_hw*[]) { 4428 &gcc_qupv3_wrap2_s2_div_clk_src.clkr.hw, 4429 }, 4430 .num_parents = 1, 4431 .flags = CLK_SET_RATE_PARENT, 4432 .ops = &clk_branch2_ops, 4433 }, 4434 }, 4435 }; 4436 4437 static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 4438 .halt_reg = 0x1e3b4, 4439 .halt_check = BRANCH_HALT_VOTED, 4440 .clkr = { 4441 .enable_reg = 0x52010, 4442 .enable_mask = BIT(7), 4443 .hw.init = &(const struct clk_init_data) { 4444 .name = "gcc_qupv3_wrap2_s3_clk", 4445 .parent_hws = (const struct clk_hw*[]) { 4446 &gcc_qupv3_wrap2_s3_div_clk_src.clkr.hw, 4447 }, 4448 .num_parents = 1, 4449 .flags = CLK_SET_RATE_PARENT, 4450 .ops = &clk_branch2_ops, 4451 }, 4452 }, 4453 }; 4454 4455 static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 4456 .halt_reg = 0x1e4f4, 4457 .halt_check = BRANCH_HALT_VOTED, 4458 .clkr = { 4459 .enable_reg = 0x52010, 4460 .enable_mask = BIT(8), 4461 .hw.init = &(const struct clk_init_data) { 4462 .name = "gcc_qupv3_wrap2_s4_clk", 4463 .parent_hws = (const struct clk_hw*[]) { 4464 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 4465 }, 4466 .num_parents = 1, 4467 .flags = CLK_SET_RATE_PARENT, 4468 .ops = &clk_branch2_ops, 4469 }, 4470 }, 4471 }; 4472 4473 static struct clk_branch gcc_qupv3_wrap2_s5_clk = { 4474 .halt_reg = 0x1e62c, 4475 .halt_check = BRANCH_HALT_VOTED, 4476 .clkr = { 4477 .enable_reg = 0x52010, 4478 .enable_mask = BIT(9), 4479 .hw.init = &(const struct clk_init_data) { 4480 .name = "gcc_qupv3_wrap2_s5_clk", 4481 .parent_hws = (const struct clk_hw*[]) { 4482 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, 4483 }, 4484 .num_parents = 1, 4485 .flags = CLK_SET_RATE_PARENT, 4486 .ops = &clk_branch2_ops, 4487 }, 4488 }, 4489 }; 4490 4491 static struct clk_branch gcc_qupv3_wrap2_s6_clk = { 4492 .halt_reg = 0x1e764, 4493 .halt_check = BRANCH_HALT_VOTED, 4494 .clkr = { 4495 .enable_reg = 0x52010, 4496 .enable_mask = BIT(10), 4497 .hw.init = &(const struct clk_init_data) { 4498 .name = "gcc_qupv3_wrap2_s6_clk", 4499 .parent_hws = (const struct clk_hw*[]) { 4500 &gcc_qupv3_wrap2_s6_clk_src.clkr.hw, 4501 }, 4502 .num_parents = 1, 4503 .flags = CLK_SET_RATE_PARENT, 4504 .ops = &clk_branch2_ops, 4505 }, 4506 }, 4507 }; 4508 4509 static struct clk_branch gcc_qupv3_wrap2_s7_clk = { 4510 .halt_reg = 0x1e89c, 4511 .halt_check = BRANCH_HALT_VOTED, 4512 .clkr = { 4513 .enable_reg = 0x52010, 4514 .enable_mask = BIT(17), 4515 .hw.init = &(const struct clk_init_data) { 4516 .name = "gcc_qupv3_wrap2_s7_clk", 4517 .parent_hws = (const struct clk_hw*[]) { 4518 &gcc_qupv3_wrap2_s7_clk_src.clkr.hw, 4519 }, 4520 .num_parents = 1, 4521 .flags = CLK_SET_RATE_PARENT, 4522 .ops = &clk_branch2_ops, 4523 }, 4524 }, 4525 }; 4526 4527 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 4528 .halt_reg = 0x23000, 4529 .halt_check = BRANCH_HALT_VOTED, 4530 .hwcg_reg = 0x23000, 4531 .hwcg_bit = 1, 4532 .clkr = { 4533 .enable_reg = 0x52020, 4534 .enable_mask = BIT(6), 4535 .hw.init = &(const struct clk_init_data) { 4536 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 4537 .ops = &clk_branch2_ops, 4538 }, 4539 }, 4540 }; 4541 4542 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 4543 .halt_reg = 0x23004, 4544 .halt_check = BRANCH_HALT_VOTED, 4545 .hwcg_reg = 0x23004, 4546 .hwcg_bit = 1, 4547 .clkr = { 4548 .enable_reg = 0x52020, 4549 .enable_mask = BIT(7), 4550 .hw.init = &(const struct clk_init_data) { 4551 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 4552 .ops = &clk_branch2_ops, 4553 }, 4554 }, 4555 }; 4556 4557 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 4558 .halt_reg = 0x23150, 4559 .halt_check = BRANCH_HALT_VOTED, 4560 .hwcg_reg = 0x23150, 4561 .hwcg_bit = 1, 4562 .clkr = { 4563 .enable_reg = 0x52008, 4564 .enable_mask = BIT(20), 4565 .hw.init = &(const struct clk_init_data) { 4566 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 4567 .ops = &clk_branch2_ops, 4568 }, 4569 }, 4570 }; 4571 4572 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 4573 .halt_reg = 0x23154, 4574 .halt_check = BRANCH_HALT_VOTED, 4575 .hwcg_reg = 0x23154, 4576 .hwcg_bit = 1, 4577 .clkr = { 4578 .enable_reg = 0x52008, 4579 .enable_mask = BIT(21), 4580 .hw.init = &(const struct clk_init_data) { 4581 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 4582 .ops = &clk_branch2_ops, 4583 }, 4584 }, 4585 }; 4586 4587 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 4588 .halt_reg = 0x232a0, 4589 .halt_check = BRANCH_HALT_VOTED, 4590 .hwcg_reg = 0x232a0, 4591 .hwcg_bit = 1, 4592 .clkr = { 4593 .enable_reg = 0x52010, 4594 .enable_mask = BIT(2), 4595 .hw.init = &(const struct clk_init_data) { 4596 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 4597 .ops = &clk_branch2_ops, 4598 }, 4599 }, 4600 }; 4601 4602 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 4603 .halt_reg = 0x232a4, 4604 .halt_check = BRANCH_HALT_VOTED, 4605 .hwcg_reg = 0x232a4, 4606 .hwcg_bit = 1, 4607 .clkr = { 4608 .enable_reg = 0x52010, 4609 .enable_mask = BIT(1), 4610 .hw.init = &(const struct clk_init_data) { 4611 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 4612 .ops = &clk_branch2_ops, 4613 }, 4614 }, 4615 }; 4616 4617 static struct clk_branch gcc_sdcc2_ahb_clk = { 4618 .halt_reg = 0x14010, 4619 .halt_check = BRANCH_HALT, 4620 .clkr = { 4621 .enable_reg = 0x14010, 4622 .enable_mask = BIT(0), 4623 .hw.init = &(const struct clk_init_data) { 4624 .name = "gcc_sdcc2_ahb_clk", 4625 .ops = &clk_branch2_ops, 4626 }, 4627 }, 4628 }; 4629 4630 static struct clk_branch gcc_sdcc2_apps_clk = { 4631 .halt_reg = 0x14004, 4632 .halt_check = BRANCH_HALT, 4633 .clkr = { 4634 .enable_reg = 0x14004, 4635 .enable_mask = BIT(0), 4636 .hw.init = &(const struct clk_init_data) { 4637 .name = "gcc_sdcc2_apps_clk", 4638 .parent_hws = (const struct clk_hw*[]) { 4639 &gcc_sdcc2_apps_clk_src.clkr.hw, 4640 }, 4641 .num_parents = 1, 4642 .flags = CLK_SET_RATE_PARENT, 4643 .ops = &clk_branch2_ops, 4644 }, 4645 }, 4646 }; 4647 4648 static struct clk_branch gcc_sdcc4_ahb_clk = { 4649 .halt_reg = 0x16010, 4650 .halt_check = BRANCH_HALT, 4651 .clkr = { 4652 .enable_reg = 0x16010, 4653 .enable_mask = BIT(0), 4654 .hw.init = &(const struct clk_init_data) { 4655 .name = "gcc_sdcc4_ahb_clk", 4656 .ops = &clk_branch2_ops, 4657 }, 4658 }, 4659 }; 4660 4661 static struct clk_branch gcc_sdcc4_apps_clk = { 4662 .halt_reg = 0x16004, 4663 .halt_check = BRANCH_HALT, 4664 .clkr = { 4665 .enable_reg = 0x16004, 4666 .enable_mask = BIT(0), 4667 .hw.init = &(const struct clk_init_data) { 4668 .name = "gcc_sdcc4_apps_clk", 4669 .parent_hws = (const struct clk_hw*[]) { 4670 &gcc_sdcc4_apps_clk_src.clkr.hw, 4671 }, 4672 .num_parents = 1, 4673 .flags = CLK_SET_RATE_PARENT, 4674 .ops = &clk_branch2_ops, 4675 }, 4676 }, 4677 }; 4678 4679 static struct clk_branch gcc_sys_noc_usb_axi_clk = { 4680 .halt_reg = 0x2d014, 4681 .halt_check = BRANCH_HALT_VOTED, 4682 .hwcg_reg = 0x2d014, 4683 .hwcg_bit = 1, 4684 .clkr = { 4685 .enable_reg = 0x2d014, 4686 .enable_mask = BIT(0), 4687 .hw.init = &(const struct clk_init_data) { 4688 .name = "gcc_sys_noc_usb_axi_clk", 4689 .ops = &clk_branch2_ops, 4690 }, 4691 }, 4692 }; 4693 4694 static struct clk_branch gcc_ufs_phy_ahb_clk = { 4695 .halt_reg = 0x77024, 4696 .halt_check = BRANCH_HALT_VOTED, 4697 .hwcg_reg = 0x77024, 4698 .hwcg_bit = 1, 4699 .clkr = { 4700 .enable_reg = 0x77024, 4701 .enable_mask = BIT(0), 4702 .hw.init = &(const struct clk_init_data) { 4703 .name = "gcc_ufs_phy_ahb_clk", 4704 .ops = &clk_branch2_ops, 4705 }, 4706 }, 4707 }; 4708 4709 static struct clk_branch gcc_ufs_phy_axi_clk = { 4710 .halt_reg = 0x77018, 4711 .halt_check = BRANCH_HALT_VOTED, 4712 .hwcg_reg = 0x77018, 4713 .hwcg_bit = 1, 4714 .clkr = { 4715 .enable_reg = 0x77018, 4716 .enable_mask = BIT(0), 4717 .hw.init = &(const struct clk_init_data) { 4718 .name = "gcc_ufs_phy_axi_clk", 4719 .parent_hws = (const struct clk_hw*[]) { 4720 &gcc_ufs_phy_axi_clk_src.clkr.hw, 4721 }, 4722 .num_parents = 1, 4723 .flags = CLK_SET_RATE_PARENT, 4724 .ops = &clk_branch2_ops, 4725 }, 4726 }, 4727 }; 4728 4729 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 4730 .halt_reg = 0x77074, 4731 .halt_check = BRANCH_HALT_VOTED, 4732 .hwcg_reg = 0x77074, 4733 .hwcg_bit = 1, 4734 .clkr = { 4735 .enable_reg = 0x77074, 4736 .enable_mask = BIT(0), 4737 .hw.init = &(const struct clk_init_data) { 4738 .name = "gcc_ufs_phy_ice_core_clk", 4739 .parent_hws = (const struct clk_hw*[]) { 4740 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 4741 }, 4742 .num_parents = 1, 4743 .flags = CLK_SET_RATE_PARENT, 4744 .ops = &clk_branch2_ops, 4745 }, 4746 }, 4747 }; 4748 4749 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 4750 .halt_reg = 0x770b0, 4751 .halt_check = BRANCH_HALT_VOTED, 4752 .hwcg_reg = 0x770b0, 4753 .hwcg_bit = 1, 4754 .clkr = { 4755 .enable_reg = 0x770b0, 4756 .enable_mask = BIT(0), 4757 .hw.init = &(const struct clk_init_data) { 4758 .name = "gcc_ufs_phy_phy_aux_clk", 4759 .parent_hws = (const struct clk_hw*[]) { 4760 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 4761 }, 4762 .num_parents = 1, 4763 .flags = CLK_SET_RATE_PARENT, 4764 .ops = &clk_branch2_ops, 4765 }, 4766 }, 4767 }; 4768 4769 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 4770 .halt_reg = 0x7702c, 4771 .halt_check = BRANCH_HALT, 4772 .clkr = { 4773 .enable_reg = 0x7702c, 4774 .enable_mask = BIT(0), 4775 .hw.init = &(const struct clk_init_data) { 4776 .name = "gcc_ufs_phy_rx_symbol_0_clk", 4777 .ops = &clk_branch2_ops, 4778 }, 4779 }, 4780 }; 4781 4782 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 4783 .halt_reg = 0x770cc, 4784 .halt_check = BRANCH_HALT, 4785 .clkr = { 4786 .enable_reg = 0x770cc, 4787 .enable_mask = BIT(0), 4788 .hw.init = &(const struct clk_init_data) { 4789 .name = "gcc_ufs_phy_rx_symbol_1_clk", 4790 .ops = &clk_branch2_ops, 4791 }, 4792 }, 4793 }; 4794 4795 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 4796 .halt_reg = 0x77028, 4797 .halt_check = BRANCH_HALT, 4798 .clkr = { 4799 .enable_reg = 0x77028, 4800 .enable_mask = BIT(0), 4801 .hw.init = &(const struct clk_init_data) { 4802 .name = "gcc_ufs_phy_tx_symbol_0_clk", 4803 .ops = &clk_branch2_ops, 4804 }, 4805 }, 4806 }; 4807 4808 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 4809 .halt_reg = 0x77068, 4810 .halt_check = BRANCH_HALT_VOTED, 4811 .hwcg_reg = 0x77068, 4812 .hwcg_bit = 1, 4813 .clkr = { 4814 .enable_reg = 0x77068, 4815 .enable_mask = BIT(0), 4816 .hw.init = &(const struct clk_init_data) { 4817 .name = "gcc_ufs_phy_unipro_core_clk", 4818 .parent_hws = (const struct clk_hw*[]) { 4819 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 4820 }, 4821 .num_parents = 1, 4822 .flags = CLK_SET_RATE_PARENT, 4823 .ops = &clk_branch2_ops, 4824 }, 4825 }, 4826 }; 4827 4828 static struct clk_branch gcc_usb20_master_clk = { 4829 .halt_reg = 0x29018, 4830 .halt_check = BRANCH_HALT, 4831 .clkr = { 4832 .enable_reg = 0x29018, 4833 .enable_mask = BIT(0), 4834 .hw.init = &(const struct clk_init_data) { 4835 .name = "gcc_usb20_master_clk", 4836 .parent_hws = (const struct clk_hw*[]) { 4837 &gcc_usb20_master_clk_src.clkr.hw, 4838 }, 4839 .num_parents = 1, 4840 .flags = CLK_SET_RATE_PARENT, 4841 .ops = &clk_branch2_ops, 4842 }, 4843 }, 4844 }; 4845 4846 static struct clk_branch gcc_usb20_mock_utmi_clk = { 4847 .halt_reg = 0x29028, 4848 .halt_check = BRANCH_HALT, 4849 .clkr = { 4850 .enable_reg = 0x29028, 4851 .enable_mask = BIT(0), 4852 .hw.init = &(const struct clk_init_data) { 4853 .name = "gcc_usb20_mock_utmi_clk", 4854 .parent_hws = (const struct clk_hw*[]) { 4855 &gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw, 4856 }, 4857 .num_parents = 1, 4858 .flags = CLK_SET_RATE_PARENT, 4859 .ops = &clk_branch2_ops, 4860 }, 4861 }, 4862 }; 4863 4864 static struct clk_branch gcc_usb20_sleep_clk = { 4865 .halt_reg = 0x29024, 4866 .halt_check = BRANCH_HALT, 4867 .clkr = { 4868 .enable_reg = 0x29024, 4869 .enable_mask = BIT(0), 4870 .hw.init = &(const struct clk_init_data) { 4871 .name = "gcc_usb20_sleep_clk", 4872 .ops = &clk_branch2_ops, 4873 }, 4874 }, 4875 }; 4876 4877 static struct clk_branch gcc_usb30_mp_master_clk = { 4878 .halt_reg = 0x17018, 4879 .halt_check = BRANCH_HALT, 4880 .clkr = { 4881 .enable_reg = 0x17018, 4882 .enable_mask = BIT(0), 4883 .hw.init = &(const struct clk_init_data) { 4884 .name = "gcc_usb30_mp_master_clk", 4885 .parent_hws = (const struct clk_hw*[]) { 4886 &gcc_usb30_mp_master_clk_src.clkr.hw, 4887 }, 4888 .num_parents = 1, 4889 .flags = CLK_SET_RATE_PARENT, 4890 .ops = &clk_branch2_ops, 4891 }, 4892 }, 4893 }; 4894 4895 static struct clk_branch gcc_usb30_mp_mock_utmi_clk = { 4896 .halt_reg = 0x17028, 4897 .halt_check = BRANCH_HALT, 4898 .clkr = { 4899 .enable_reg = 0x17028, 4900 .enable_mask = BIT(0), 4901 .hw.init = &(const struct clk_init_data) { 4902 .name = "gcc_usb30_mp_mock_utmi_clk", 4903 .parent_hws = (const struct clk_hw*[]) { 4904 &gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr.hw, 4905 }, 4906 .num_parents = 1, 4907 .flags = CLK_SET_RATE_PARENT, 4908 .ops = &clk_branch2_ops, 4909 }, 4910 }, 4911 }; 4912 4913 static struct clk_branch gcc_usb30_mp_sleep_clk = { 4914 .halt_reg = 0x17024, 4915 .halt_check = BRANCH_HALT, 4916 .clkr = { 4917 .enable_reg = 0x17024, 4918 .enable_mask = BIT(0), 4919 .hw.init = &(const struct clk_init_data) { 4920 .name = "gcc_usb30_mp_sleep_clk", 4921 .ops = &clk_branch2_ops, 4922 }, 4923 }, 4924 }; 4925 4926 static struct clk_branch gcc_usb30_prim_master_clk = { 4927 .halt_reg = 0x39018, 4928 .halt_check = BRANCH_HALT, 4929 .clkr = { 4930 .enable_reg = 0x39018, 4931 .enable_mask = BIT(0), 4932 .hw.init = &(const struct clk_init_data) { 4933 .name = "gcc_usb30_prim_master_clk", 4934 .parent_hws = (const struct clk_hw*[]) { 4935 &gcc_usb30_prim_master_clk_src.clkr.hw, 4936 }, 4937 .num_parents = 1, 4938 .flags = CLK_SET_RATE_PARENT, 4939 .ops = &clk_branch2_ops, 4940 }, 4941 }, 4942 }; 4943 4944 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 4945 .halt_reg = 0x39028, 4946 .halt_check = BRANCH_HALT, 4947 .clkr = { 4948 .enable_reg = 0x39028, 4949 .enable_mask = BIT(0), 4950 .hw.init = &(const struct clk_init_data) { 4951 .name = "gcc_usb30_prim_mock_utmi_clk", 4952 .parent_hws = (const struct clk_hw*[]) { 4953 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 4954 }, 4955 .num_parents = 1, 4956 .flags = CLK_SET_RATE_PARENT, 4957 .ops = &clk_branch2_ops, 4958 }, 4959 }, 4960 }; 4961 4962 static struct clk_branch gcc_usb30_prim_sleep_clk = { 4963 .halt_reg = 0x39024, 4964 .halt_check = BRANCH_HALT, 4965 .clkr = { 4966 .enable_reg = 0x39024, 4967 .enable_mask = BIT(0), 4968 .hw.init = &(const struct clk_init_data) { 4969 .name = "gcc_usb30_prim_sleep_clk", 4970 .ops = &clk_branch2_ops, 4971 }, 4972 }, 4973 }; 4974 4975 static struct clk_branch gcc_usb30_sec_master_clk = { 4976 .halt_reg = 0xa1018, 4977 .halt_check = BRANCH_HALT, 4978 .clkr = { 4979 .enable_reg = 0xa1018, 4980 .enable_mask = BIT(0), 4981 .hw.init = &(const struct clk_init_data) { 4982 .name = "gcc_usb30_sec_master_clk", 4983 .parent_hws = (const struct clk_hw*[]) { 4984 &gcc_usb30_sec_master_clk_src.clkr.hw, 4985 }, 4986 .num_parents = 1, 4987 .flags = CLK_SET_RATE_PARENT, 4988 .ops = &clk_branch2_ops, 4989 }, 4990 }, 4991 }; 4992 4993 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { 4994 .halt_reg = 0xa1028, 4995 .halt_check = BRANCH_HALT, 4996 .clkr = { 4997 .enable_reg = 0xa1028, 4998 .enable_mask = BIT(0), 4999 .hw.init = &(const struct clk_init_data) { 5000 .name = "gcc_usb30_sec_mock_utmi_clk", 5001 .parent_hws = (const struct clk_hw*[]) { 5002 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw, 5003 }, 5004 .num_parents = 1, 5005 .flags = CLK_SET_RATE_PARENT, 5006 .ops = &clk_branch2_ops, 5007 }, 5008 }, 5009 }; 5010 5011 static struct clk_branch gcc_usb30_sec_sleep_clk = { 5012 .halt_reg = 0xa1024, 5013 .halt_check = BRANCH_HALT, 5014 .clkr = { 5015 .enable_reg = 0xa1024, 5016 .enable_mask = BIT(0), 5017 .hw.init = &(const struct clk_init_data) { 5018 .name = "gcc_usb30_sec_sleep_clk", 5019 .ops = &clk_branch2_ops, 5020 }, 5021 }, 5022 }; 5023 5024 static struct clk_branch gcc_usb30_tert_master_clk = { 5025 .halt_reg = 0xa2018, 5026 .halt_check = BRANCH_HALT, 5027 .clkr = { 5028 .enable_reg = 0xa2018, 5029 .enable_mask = BIT(0), 5030 .hw.init = &(const struct clk_init_data) { 5031 .name = "gcc_usb30_tert_master_clk", 5032 .parent_hws = (const struct clk_hw*[]) { 5033 &gcc_usb30_tert_master_clk_src.clkr.hw, 5034 }, 5035 .num_parents = 1, 5036 .flags = CLK_SET_RATE_PARENT, 5037 .ops = &clk_branch2_ops, 5038 }, 5039 }, 5040 }; 5041 5042 static struct clk_branch gcc_usb30_tert_mock_utmi_clk = { 5043 .halt_reg = 0xa2028, 5044 .halt_check = BRANCH_HALT, 5045 .clkr = { 5046 .enable_reg = 0xa2028, 5047 .enable_mask = BIT(0), 5048 .hw.init = &(const struct clk_init_data) { 5049 .name = "gcc_usb30_tert_mock_utmi_clk", 5050 .parent_hws = (const struct clk_hw*[]) { 5051 &gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr.hw, 5052 }, 5053 .num_parents = 1, 5054 .flags = CLK_SET_RATE_PARENT, 5055 .ops = &clk_branch2_ops, 5056 }, 5057 }, 5058 }; 5059 5060 static struct clk_branch gcc_usb30_tert_sleep_clk = { 5061 .halt_reg = 0xa2024, 5062 .halt_check = BRANCH_HALT, 5063 .clkr = { 5064 .enable_reg = 0xa2024, 5065 .enable_mask = BIT(0), 5066 .hw.init = &(const struct clk_init_data) { 5067 .name = "gcc_usb30_tert_sleep_clk", 5068 .ops = &clk_branch2_ops, 5069 }, 5070 }, 5071 }; 5072 5073 static struct clk_branch gcc_usb3_mp_phy_aux_clk = { 5074 .halt_reg = 0x17288, 5075 .halt_check = BRANCH_HALT, 5076 .clkr = { 5077 .enable_reg = 0x17288, 5078 .enable_mask = BIT(0), 5079 .hw.init = &(const struct clk_init_data) { 5080 .name = "gcc_usb3_mp_phy_aux_clk", 5081 .parent_hws = (const struct clk_hw*[]) { 5082 &gcc_usb3_mp_phy_aux_clk_src.clkr.hw, 5083 }, 5084 .num_parents = 1, 5085 .flags = CLK_SET_RATE_PARENT, 5086 .ops = &clk_branch2_ops, 5087 }, 5088 }, 5089 }; 5090 5091 static struct clk_branch gcc_usb3_mp_phy_com_aux_clk = { 5092 .halt_reg = 0x1728c, 5093 .halt_check = BRANCH_HALT, 5094 .clkr = { 5095 .enable_reg = 0x1728c, 5096 .enable_mask = BIT(0), 5097 .hw.init = &(const struct clk_init_data) { 5098 .name = "gcc_usb3_mp_phy_com_aux_clk", 5099 .parent_hws = (const struct clk_hw*[]) { 5100 &gcc_usb3_mp_phy_aux_clk_src.clkr.hw, 5101 }, 5102 .num_parents = 1, 5103 .flags = CLK_SET_RATE_PARENT, 5104 .ops = &clk_branch2_ops, 5105 }, 5106 }, 5107 }; 5108 5109 static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = { 5110 .halt_reg = 0x17290, 5111 .halt_check = BRANCH_HALT, 5112 .clkr = { 5113 .enable_reg = 0x17290, 5114 .enable_mask = BIT(0), 5115 .hw.init = &(const struct clk_init_data) { 5116 .name = "gcc_usb3_mp_phy_pipe_0_clk", 5117 .ops = &clk_branch2_ops, 5118 }, 5119 }, 5120 }; 5121 5122 static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = { 5123 .halt_reg = 0x17298, 5124 .halt_check = BRANCH_HALT, 5125 .clkr = { 5126 .enable_reg = 0x17298, 5127 .enable_mask = BIT(0), 5128 .hw.init = &(const struct clk_init_data) { 5129 .name = "gcc_usb3_mp_phy_pipe_1_clk", 5130 .ops = &clk_branch2_ops, 5131 }, 5132 }, 5133 }; 5134 5135 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 5136 .halt_reg = 0x39060, 5137 .halt_check = BRANCH_HALT, 5138 .clkr = { 5139 .enable_reg = 0x39060, 5140 .enable_mask = BIT(0), 5141 .hw.init = &(const struct clk_init_data) { 5142 .name = "gcc_usb3_prim_phy_aux_clk", 5143 .parent_hws = (const struct clk_hw*[]) { 5144 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 5145 }, 5146 .num_parents = 1, 5147 .flags = CLK_SET_RATE_PARENT, 5148 .ops = &clk_branch2_ops, 5149 }, 5150 }, 5151 }; 5152 5153 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 5154 .halt_reg = 0x39064, 5155 .halt_check = BRANCH_HALT, 5156 .clkr = { 5157 .enable_reg = 0x39064, 5158 .enable_mask = BIT(0), 5159 .hw.init = &(const struct clk_init_data) { 5160 .name = "gcc_usb3_prim_phy_com_aux_clk", 5161 .parent_hws = (const struct clk_hw*[]) { 5162 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 5163 }, 5164 .num_parents = 1, 5165 .flags = CLK_SET_RATE_PARENT, 5166 .ops = &clk_branch2_ops, 5167 }, 5168 }, 5169 }; 5170 5171 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 5172 .reg = 0x3906c, 5173 .shift = 0, 5174 .width = 2, 5175 .parent_map = gcc_parent_map_10, 5176 .clkr = { 5177 .hw.init = &(struct clk_init_data){ 5178 .name = "gcc_usb3_prim_phy_pipe_clk_src", 5179 .parent_data = gcc_parent_data_10, 5180 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 5181 .ops = &clk_regmap_mux_closest_ops, 5182 }, 5183 }, 5184 }; 5185 5186 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 5187 .halt_reg = 0x39068, 5188 .halt_check = BRANCH_HALT_VOTED, 5189 .hwcg_reg = 0x39068, 5190 .hwcg_bit = 1, 5191 .clkr = { 5192 .enable_reg = 0x39068, 5193 .enable_mask = BIT(0), 5194 .hw.init = &(const struct clk_init_data) { 5195 .name = "gcc_usb3_prim_phy_pipe_clk", 5196 .parent_hws = (const struct clk_hw*[]) { 5197 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 5198 }, 5199 .num_parents = 1, 5200 .flags = CLK_SET_RATE_PARENT, 5201 .ops = &clk_branch2_ops, 5202 }, 5203 }, 5204 }; 5205 5206 static struct clk_branch gcc_usb3_sec_phy_aux_clk = { 5207 .halt_reg = 0xa1060, 5208 .halt_check = BRANCH_HALT, 5209 .clkr = { 5210 .enable_reg = 0xa1060, 5211 .enable_mask = BIT(0), 5212 .hw.init = &(const struct clk_init_data) { 5213 .name = "gcc_usb3_sec_phy_aux_clk", 5214 .parent_hws = (const struct clk_hw*[]) { 5215 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 5216 }, 5217 .num_parents = 1, 5218 .flags = CLK_SET_RATE_PARENT, 5219 .ops = &clk_branch2_ops, 5220 }, 5221 }, 5222 }; 5223 5224 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { 5225 .halt_reg = 0xa1064, 5226 .halt_check = BRANCH_HALT, 5227 .clkr = { 5228 .enable_reg = 0xa1064, 5229 .enable_mask = BIT(0), 5230 .hw.init = &(const struct clk_init_data) { 5231 .name = "gcc_usb3_sec_phy_com_aux_clk", 5232 .parent_hws = (const struct clk_hw*[]) { 5233 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 5234 }, 5235 .num_parents = 1, 5236 .flags = CLK_SET_RATE_PARENT, 5237 .ops = &clk_branch2_ops, 5238 }, 5239 }, 5240 }; 5241 5242 static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = { 5243 .reg = 0xa106c, 5244 .shift = 0, 5245 .width = 2, 5246 .parent_map = gcc_parent_map_11, 5247 .clkr = { 5248 .hw.init = &(struct clk_init_data){ 5249 .name = "gcc_usb3_sec_phy_pipe_clk_src", 5250 .parent_data = gcc_parent_data_11, 5251 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 5252 .ops = &clk_regmap_mux_closest_ops, 5253 }, 5254 }, 5255 }; 5256 5257 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { 5258 .halt_reg = 0xa1068, 5259 .halt_check = BRANCH_HALT_VOTED, 5260 .hwcg_reg = 0xa1068, 5261 .hwcg_bit = 1, 5262 .clkr = { 5263 .enable_reg = 0xa1068, 5264 .enable_mask = BIT(0), 5265 .hw.init = &(const struct clk_init_data) { 5266 .name = "gcc_usb3_sec_phy_pipe_clk", 5267 .parent_hws = (const struct clk_hw*[]) { 5268 &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw, 5269 }, 5270 .num_parents = 1, 5271 .ops = &clk_branch2_ops, 5272 }, 5273 }, 5274 }; 5275 5276 static struct clk_branch gcc_usb3_tert_phy_aux_clk = { 5277 .halt_reg = 0xa2060, 5278 .halt_check = BRANCH_HALT, 5279 .clkr = { 5280 .enable_reg = 0xa2060, 5281 .enable_mask = BIT(0), 5282 .hw.init = &(const struct clk_init_data) { 5283 .name = "gcc_usb3_tert_phy_aux_clk", 5284 .parent_hws = (const struct clk_hw*[]) { 5285 &gcc_usb3_tert_phy_aux_clk_src.clkr.hw, 5286 }, 5287 .num_parents = 1, 5288 .flags = CLK_SET_RATE_PARENT, 5289 .ops = &clk_branch2_ops, 5290 }, 5291 }, 5292 }; 5293 5294 static struct clk_branch gcc_usb3_tert_phy_com_aux_clk = { 5295 .halt_reg = 0xa2064, 5296 .halt_check = BRANCH_HALT, 5297 .clkr = { 5298 .enable_reg = 0xa2064, 5299 .enable_mask = BIT(0), 5300 .hw.init = &(const struct clk_init_data) { 5301 .name = "gcc_usb3_tert_phy_com_aux_clk", 5302 .parent_hws = (const struct clk_hw*[]) { 5303 &gcc_usb3_tert_phy_aux_clk_src.clkr.hw, 5304 }, 5305 .num_parents = 1, 5306 .flags = CLK_SET_RATE_PARENT, 5307 .ops = &clk_branch2_ops, 5308 }, 5309 }, 5310 }; 5311 5312 static struct clk_regmap_mux gcc_usb3_tert_phy_pipe_clk_src = { 5313 .reg = 0xa206c, 5314 .shift = 0, 5315 .width = 2, 5316 .parent_map = gcc_parent_map_12, 5317 .clkr = { 5318 .hw.init = &(struct clk_init_data){ 5319 .name = "gcc_usb3_tert_phy_pipe_clk_src", 5320 .parent_data = gcc_parent_data_12, 5321 .num_parents = ARRAY_SIZE(gcc_parent_data_12), 5322 .ops = &clk_regmap_mux_closest_ops, 5323 }, 5324 }, 5325 }; 5326 5327 static struct clk_branch gcc_usb3_tert_phy_pipe_clk = { 5328 .halt_reg = 0xa2068, 5329 .halt_check = BRANCH_HALT_VOTED, 5330 .hwcg_reg = 0xa2068, 5331 .hwcg_bit = 1, 5332 .clkr = { 5333 .enable_reg = 0xa2068, 5334 .enable_mask = BIT(0), 5335 .hw.init = &(const struct clk_init_data) { 5336 .name = "gcc_usb3_tert_phy_pipe_clk", 5337 .parent_hws = (const struct clk_hw*[]) { 5338 &gcc_usb3_tert_phy_pipe_clk_src.clkr.hw, 5339 }, 5340 .num_parents = 1, 5341 .ops = &clk_branch2_ops, 5342 }, 5343 }, 5344 }; 5345 5346 static struct clk_branch gcc_usb4_0_cfg_ahb_clk = { 5347 .halt_reg = 0x9f0a8, 5348 .halt_check = BRANCH_HALT_VOTED, 5349 .hwcg_reg = 0x9f0a8, 5350 .hwcg_bit = 1, 5351 .clkr = { 5352 .enable_reg = 0x9f0a8, 5353 .enable_mask = BIT(0), 5354 .hw.init = &(const struct clk_init_data) { 5355 .name = "gcc_usb4_0_cfg_ahb_clk", 5356 .ops = &clk_branch2_ops, 5357 }, 5358 }, 5359 }; 5360 5361 static struct clk_branch gcc_usb4_0_dp0_clk = { 5362 .halt_reg = 0x9f060, 5363 .halt_check = BRANCH_HALT, 5364 .clkr = { 5365 .enable_reg = 0x9f060, 5366 .enable_mask = BIT(0), 5367 .hw.init = &(const struct clk_init_data) { 5368 .name = "gcc_usb4_0_dp0_clk", 5369 .ops = &clk_branch2_ops, 5370 }, 5371 }, 5372 }; 5373 5374 static struct clk_branch gcc_usb4_0_dp1_clk = { 5375 .halt_reg = 0x9f108, 5376 .halt_check = BRANCH_HALT, 5377 .clkr = { 5378 .enable_reg = 0x9f108, 5379 .enable_mask = BIT(0), 5380 .hw.init = &(const struct clk_init_data) { 5381 .name = "gcc_usb4_0_dp1_clk", 5382 .ops = &clk_branch2_ops, 5383 }, 5384 }, 5385 }; 5386 5387 static struct clk_branch gcc_usb4_0_master_clk = { 5388 .halt_reg = 0x9f018, 5389 .halt_check = BRANCH_HALT, 5390 .clkr = { 5391 .enable_reg = 0x9f018, 5392 .enable_mask = BIT(0), 5393 .hw.init = &(const struct clk_init_data) { 5394 .name = "gcc_usb4_0_master_clk", 5395 .parent_hws = (const struct clk_hw*[]) { 5396 &gcc_usb4_0_master_clk_src.clkr.hw, 5397 }, 5398 .num_parents = 1, 5399 .flags = CLK_SET_RATE_PARENT, 5400 .ops = &clk_branch2_ops, 5401 }, 5402 }, 5403 }; 5404 5405 static struct clk_branch gcc_usb4_0_phy_p2rr2p_pipe_clk = { 5406 .halt_reg = 0x9f0d8, 5407 .halt_check = BRANCH_HALT, 5408 .clkr = { 5409 .enable_reg = 0x9f0d8, 5410 .enable_mask = BIT(0), 5411 .hw.init = &(const struct clk_init_data) { 5412 .name = "gcc_usb4_0_phy_p2rr2p_pipe_clk", 5413 .ops = &clk_branch2_ops, 5414 }, 5415 }, 5416 }; 5417 5418 static struct clk_branch gcc_usb4_0_phy_pcie_pipe_clk = { 5419 .halt_reg = 0x9f048, 5420 .halt_check = BRANCH_HALT_VOTED, 5421 .clkr = { 5422 .enable_reg = 0x52010, 5423 .enable_mask = BIT(19), 5424 .hw.init = &(const struct clk_init_data) { 5425 .name = "gcc_usb4_0_phy_pcie_pipe_clk", 5426 .ops = &clk_branch2_ops, 5427 }, 5428 }, 5429 }; 5430 5431 static struct clk_branch gcc_usb4_0_phy_rx0_clk = { 5432 .halt_reg = 0x9f0b0, 5433 .halt_check = BRANCH_HALT, 5434 .clkr = { 5435 .enable_reg = 0x9f0b0, 5436 .enable_mask = BIT(0), 5437 .hw.init = &(const struct clk_init_data) { 5438 .name = "gcc_usb4_0_phy_rx0_clk", 5439 .ops = &clk_branch2_ops, 5440 }, 5441 }, 5442 }; 5443 5444 static struct clk_branch gcc_usb4_0_phy_rx1_clk = { 5445 .halt_reg = 0x9f0c0, 5446 .halt_check = BRANCH_HALT, 5447 .clkr = { 5448 .enable_reg = 0x9f0c0, 5449 .enable_mask = BIT(0), 5450 .hw.init = &(const struct clk_init_data) { 5451 .name = "gcc_usb4_0_phy_rx1_clk", 5452 .ops = &clk_branch2_ops, 5453 }, 5454 }, 5455 }; 5456 5457 static struct clk_branch gcc_usb4_0_phy_usb_pipe_clk = { 5458 .halt_reg = 0x9f0a4, 5459 .halt_check = BRANCH_HALT_VOTED, 5460 .hwcg_reg = 0x9f0a4, 5461 .hwcg_bit = 1, 5462 .clkr = { 5463 .enable_reg = 0x9f0a4, 5464 .enable_mask = BIT(0), 5465 .hw.init = &(const struct clk_init_data) { 5466 .name = "gcc_usb4_0_phy_usb_pipe_clk", 5467 .ops = &clk_branch2_ops, 5468 }, 5469 }, 5470 }; 5471 5472 static struct clk_branch gcc_usb4_0_sb_if_clk = { 5473 .halt_reg = 0x9f044, 5474 .halt_check = BRANCH_HALT, 5475 .clkr = { 5476 .enable_reg = 0x9f044, 5477 .enable_mask = BIT(0), 5478 .hw.init = &(const struct clk_init_data) { 5479 .name = "gcc_usb4_0_sb_if_clk", 5480 .parent_hws = (const struct clk_hw*[]) { 5481 &gcc_usb4_0_sb_if_clk_src.clkr.hw, 5482 }, 5483 .num_parents = 1, 5484 .flags = CLK_SET_RATE_PARENT, 5485 .ops = &clk_branch2_ops, 5486 }, 5487 }, 5488 }; 5489 5490 static struct clk_branch gcc_usb4_0_sys_clk = { 5491 .halt_reg = 0x9f054, 5492 .halt_check = BRANCH_HALT, 5493 .clkr = { 5494 .enable_reg = 0x9f054, 5495 .enable_mask = BIT(0), 5496 .hw.init = &(const struct clk_init_data) { 5497 .name = "gcc_usb4_0_sys_clk", 5498 .ops = &clk_branch2_ops, 5499 }, 5500 }, 5501 }; 5502 5503 static struct clk_branch gcc_usb4_0_tmu_clk = { 5504 .halt_reg = 0x9f088, 5505 .halt_check = BRANCH_HALT_VOTED, 5506 .hwcg_reg = 0x9f088, 5507 .hwcg_bit = 1, 5508 .clkr = { 5509 .enable_reg = 0x9f088, 5510 .enable_mask = BIT(0), 5511 .hw.init = &(const struct clk_init_data) { 5512 .name = "gcc_usb4_0_tmu_clk", 5513 .parent_hws = (const struct clk_hw*[]) { 5514 &gcc_usb4_0_tmu_clk_src.clkr.hw, 5515 }, 5516 .num_parents = 1, 5517 .flags = CLK_SET_RATE_PARENT, 5518 .ops = &clk_branch2_ops, 5519 }, 5520 }, 5521 }; 5522 5523 static struct clk_branch gcc_usb4_1_cfg_ahb_clk = { 5524 .halt_reg = 0x2b0a8, 5525 .halt_check = BRANCH_HALT_VOTED, 5526 .hwcg_reg = 0x2b0a8, 5527 .hwcg_bit = 1, 5528 .clkr = { 5529 .enable_reg = 0x2b0a8, 5530 .enable_mask = BIT(0), 5531 .hw.init = &(const struct clk_init_data) { 5532 .name = "gcc_usb4_1_cfg_ahb_clk", 5533 .ops = &clk_branch2_ops, 5534 }, 5535 }, 5536 }; 5537 5538 static struct clk_branch gcc_usb4_1_dp0_clk = { 5539 .halt_reg = 0x2b060, 5540 .halt_check = BRANCH_HALT, 5541 .clkr = { 5542 .enable_reg = 0x2b060, 5543 .enable_mask = BIT(0), 5544 .hw.init = &(const struct clk_init_data) { 5545 .name = "gcc_usb4_1_dp0_clk", 5546 .ops = &clk_branch2_ops, 5547 }, 5548 }, 5549 }; 5550 5551 static struct clk_branch gcc_usb4_1_dp1_clk = { 5552 .halt_reg = 0x2b108, 5553 .halt_check = BRANCH_HALT, 5554 .clkr = { 5555 .enable_reg = 0x2b108, 5556 .enable_mask = BIT(0), 5557 .hw.init = &(const struct clk_init_data) { 5558 .name = "gcc_usb4_1_dp1_clk", 5559 .ops = &clk_branch2_ops, 5560 }, 5561 }, 5562 }; 5563 5564 static struct clk_branch gcc_usb4_1_master_clk = { 5565 .halt_reg = 0x2b018, 5566 .halt_check = BRANCH_HALT, 5567 .clkr = { 5568 .enable_reg = 0x2b018, 5569 .enable_mask = BIT(0), 5570 .hw.init = &(const struct clk_init_data) { 5571 .name = "gcc_usb4_1_master_clk", 5572 .parent_hws = (const struct clk_hw*[]) { 5573 &gcc_usb4_1_master_clk_src.clkr.hw, 5574 }, 5575 .num_parents = 1, 5576 .flags = CLK_SET_RATE_PARENT, 5577 .ops = &clk_branch2_ops, 5578 }, 5579 }, 5580 }; 5581 5582 static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = { 5583 .halt_reg = 0x2b0d8, 5584 .halt_check = BRANCH_HALT, 5585 .clkr = { 5586 .enable_reg = 0x2b0d8, 5587 .enable_mask = BIT(0), 5588 .hw.init = &(const struct clk_init_data) { 5589 .name = "gcc_usb4_1_phy_p2rr2p_pipe_clk", 5590 .ops = &clk_branch2_ops, 5591 }, 5592 }, 5593 }; 5594 5595 static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk = { 5596 .halt_reg = 0x2b048, 5597 .halt_check = BRANCH_HALT_VOTED, 5598 .clkr = { 5599 .enable_reg = 0x52028, 5600 .enable_mask = BIT(0), 5601 .hw.init = &(const struct clk_init_data) { 5602 .name = "gcc_usb4_1_phy_pcie_pipe_clk", 5603 .ops = &clk_branch2_ops, 5604 }, 5605 }, 5606 }; 5607 5608 static struct clk_branch gcc_usb4_1_phy_rx0_clk = { 5609 .halt_reg = 0x2b0b0, 5610 .halt_check = BRANCH_HALT, 5611 .clkr = { 5612 .enable_reg = 0x2b0b0, 5613 .enable_mask = BIT(0), 5614 .hw.init = &(const struct clk_init_data) { 5615 .name = "gcc_usb4_1_phy_rx0_clk", 5616 .ops = &clk_branch2_ops, 5617 }, 5618 }, 5619 }; 5620 5621 static struct clk_branch gcc_usb4_1_phy_rx1_clk = { 5622 .halt_reg = 0x2b0c0, 5623 .halt_check = BRANCH_HALT, 5624 .clkr = { 5625 .enable_reg = 0x2b0c0, 5626 .enable_mask = BIT(0), 5627 .hw.init = &(const struct clk_init_data) { 5628 .name = "gcc_usb4_1_phy_rx1_clk", 5629 .ops = &clk_branch2_ops, 5630 }, 5631 }, 5632 }; 5633 5634 static struct clk_branch gcc_usb4_1_phy_usb_pipe_clk = { 5635 .halt_reg = 0x2b0a4, 5636 .halt_check = BRANCH_HALT_VOTED, 5637 .hwcg_reg = 0x2b0a4, 5638 .hwcg_bit = 1, 5639 .clkr = { 5640 .enable_reg = 0x2b0a4, 5641 .enable_mask = BIT(0), 5642 .hw.init = &(const struct clk_init_data) { 5643 .name = "gcc_usb4_1_phy_usb_pipe_clk", 5644 .ops = &clk_branch2_ops, 5645 }, 5646 }, 5647 }; 5648 5649 static struct clk_branch gcc_usb4_1_sb_if_clk = { 5650 .halt_reg = 0x2b044, 5651 .halt_check = BRANCH_HALT, 5652 .clkr = { 5653 .enable_reg = 0x2b044, 5654 .enable_mask = BIT(0), 5655 .hw.init = &(const struct clk_init_data) { 5656 .name = "gcc_usb4_1_sb_if_clk", 5657 .parent_hws = (const struct clk_hw*[]) { 5658 &gcc_usb4_1_sb_if_clk_src.clkr.hw, 5659 }, 5660 .num_parents = 1, 5661 .flags = CLK_SET_RATE_PARENT, 5662 .ops = &clk_branch2_ops, 5663 }, 5664 }, 5665 }; 5666 5667 static struct clk_branch gcc_usb4_1_sys_clk = { 5668 .halt_reg = 0x2b054, 5669 .halt_check = BRANCH_HALT, 5670 .clkr = { 5671 .enable_reg = 0x2b054, 5672 .enable_mask = BIT(0), 5673 .hw.init = &(const struct clk_init_data) { 5674 .name = "gcc_usb4_1_sys_clk", 5675 .ops = &clk_branch2_ops, 5676 }, 5677 }, 5678 }; 5679 5680 static struct clk_branch gcc_usb4_1_tmu_clk = { 5681 .halt_reg = 0x2b088, 5682 .halt_check = BRANCH_HALT_VOTED, 5683 .hwcg_reg = 0x2b088, 5684 .hwcg_bit = 1, 5685 .clkr = { 5686 .enable_reg = 0x2b088, 5687 .enable_mask = BIT(0), 5688 .hw.init = &(const struct clk_init_data) { 5689 .name = "gcc_usb4_1_tmu_clk", 5690 .parent_hws = (const struct clk_hw*[]) { 5691 &gcc_usb4_1_tmu_clk_src.clkr.hw, 5692 }, 5693 .num_parents = 1, 5694 .flags = CLK_SET_RATE_PARENT, 5695 .ops = &clk_branch2_ops, 5696 }, 5697 }, 5698 }; 5699 5700 static struct clk_branch gcc_usb4_2_cfg_ahb_clk = { 5701 .halt_reg = 0x110a8, 5702 .halt_check = BRANCH_HALT_VOTED, 5703 .hwcg_reg = 0x110a8, 5704 .hwcg_bit = 1, 5705 .clkr = { 5706 .enable_reg = 0x110a8, 5707 .enable_mask = BIT(0), 5708 .hw.init = &(const struct clk_init_data) { 5709 .name = "gcc_usb4_2_cfg_ahb_clk", 5710 .ops = &clk_branch2_ops, 5711 }, 5712 }, 5713 }; 5714 5715 static struct clk_branch gcc_usb4_2_dp0_clk = { 5716 .halt_reg = 0x11060, 5717 .halt_check = BRANCH_HALT, 5718 .clkr = { 5719 .enable_reg = 0x11060, 5720 .enable_mask = BIT(0), 5721 .hw.init = &(const struct clk_init_data) { 5722 .name = "gcc_usb4_2_dp0_clk", 5723 .ops = &clk_branch2_ops, 5724 }, 5725 }, 5726 }; 5727 5728 static struct clk_branch gcc_usb4_2_dp1_clk = { 5729 .halt_reg = 0x11108, 5730 .halt_check = BRANCH_HALT, 5731 .clkr = { 5732 .enable_reg = 0x11108, 5733 .enable_mask = BIT(0), 5734 .hw.init = &(const struct clk_init_data) { 5735 .name = "gcc_usb4_2_dp1_clk", 5736 .ops = &clk_branch2_ops, 5737 }, 5738 }, 5739 }; 5740 5741 static struct clk_branch gcc_usb4_2_master_clk = { 5742 .halt_reg = 0x11018, 5743 .halt_check = BRANCH_HALT, 5744 .clkr = { 5745 .enable_reg = 0x11018, 5746 .enable_mask = BIT(0), 5747 .hw.init = &(const struct clk_init_data) { 5748 .name = "gcc_usb4_2_master_clk", 5749 .parent_hws = (const struct clk_hw*[]) { 5750 &gcc_usb4_2_master_clk_src.clkr.hw, 5751 }, 5752 .num_parents = 1, 5753 .flags = CLK_SET_RATE_PARENT, 5754 .ops = &clk_branch2_ops, 5755 }, 5756 }, 5757 }; 5758 5759 static struct clk_branch gcc_usb4_2_phy_p2rr2p_pipe_clk = { 5760 .halt_reg = 0x110d8, 5761 .halt_check = BRANCH_HALT, 5762 .clkr = { 5763 .enable_reg = 0x110d8, 5764 .enable_mask = BIT(0), 5765 .hw.init = &(const struct clk_init_data) { 5766 .name = "gcc_usb4_2_phy_p2rr2p_pipe_clk", 5767 .ops = &clk_branch2_ops, 5768 }, 5769 }, 5770 }; 5771 5772 static struct clk_branch gcc_usb4_2_phy_pcie_pipe_clk = { 5773 .halt_reg = 0x11048, 5774 .halt_check = BRANCH_HALT_VOTED, 5775 .clkr = { 5776 .enable_reg = 0x52028, 5777 .enable_mask = BIT(1), 5778 .hw.init = &(const struct clk_init_data) { 5779 .name = "gcc_usb4_2_phy_pcie_pipe_clk", 5780 .ops = &clk_branch2_ops, 5781 }, 5782 }, 5783 }; 5784 5785 static struct clk_branch gcc_usb4_2_phy_rx0_clk = { 5786 .halt_reg = 0x110b0, 5787 .halt_check = BRANCH_HALT, 5788 .clkr = { 5789 .enable_reg = 0x110b0, 5790 .enable_mask = BIT(0), 5791 .hw.init = &(const struct clk_init_data) { 5792 .name = "gcc_usb4_2_phy_rx0_clk", 5793 .ops = &clk_branch2_ops, 5794 }, 5795 }, 5796 }; 5797 5798 static struct clk_branch gcc_usb4_2_phy_rx1_clk = { 5799 .halt_reg = 0x110c0, 5800 .halt_check = BRANCH_HALT, 5801 .clkr = { 5802 .enable_reg = 0x110c0, 5803 .enable_mask = BIT(0), 5804 .hw.init = &(const struct clk_init_data) { 5805 .name = "gcc_usb4_2_phy_rx1_clk", 5806 .ops = &clk_branch2_ops, 5807 }, 5808 }, 5809 }; 5810 5811 static struct clk_branch gcc_usb4_2_phy_usb_pipe_clk = { 5812 .halt_reg = 0x110a4, 5813 .halt_check = BRANCH_HALT_VOTED, 5814 .hwcg_reg = 0x110a4, 5815 .hwcg_bit = 1, 5816 .clkr = { 5817 .enable_reg = 0x110a4, 5818 .enable_mask = BIT(0), 5819 .hw.init = &(const struct clk_init_data) { 5820 .name = "gcc_usb4_2_phy_usb_pipe_clk", 5821 .ops = &clk_branch2_ops, 5822 }, 5823 }, 5824 }; 5825 5826 static struct clk_branch gcc_usb4_2_sb_if_clk = { 5827 .halt_reg = 0x11044, 5828 .halt_check = BRANCH_HALT, 5829 .clkr = { 5830 .enable_reg = 0x11044, 5831 .enable_mask = BIT(0), 5832 .hw.init = &(const struct clk_init_data) { 5833 .name = "gcc_usb4_2_sb_if_clk", 5834 .parent_hws = (const struct clk_hw*[]) { 5835 &gcc_usb4_2_sb_if_clk_src.clkr.hw, 5836 }, 5837 .num_parents = 1, 5838 .flags = CLK_SET_RATE_PARENT, 5839 .ops = &clk_branch2_ops, 5840 }, 5841 }, 5842 }; 5843 5844 static struct clk_branch gcc_usb4_2_sys_clk = { 5845 .halt_reg = 0x11054, 5846 .halt_check = BRANCH_HALT, 5847 .clkr = { 5848 .enable_reg = 0x11054, 5849 .enable_mask = BIT(0), 5850 .hw.init = &(const struct clk_init_data) { 5851 .name = "gcc_usb4_2_sys_clk", 5852 .ops = &clk_branch2_ops, 5853 }, 5854 }, 5855 }; 5856 5857 static struct clk_branch gcc_usb4_2_tmu_clk = { 5858 .halt_reg = 0x11088, 5859 .halt_check = BRANCH_HALT_VOTED, 5860 .hwcg_reg = 0x11088, 5861 .hwcg_bit = 1, 5862 .clkr = { 5863 .enable_reg = 0x11088, 5864 .enable_mask = BIT(0), 5865 .hw.init = &(const struct clk_init_data) { 5866 .name = "gcc_usb4_2_tmu_clk", 5867 .parent_hws = (const struct clk_hw*[]) { 5868 &gcc_usb4_2_tmu_clk_src.clkr.hw, 5869 }, 5870 .num_parents = 1, 5871 .flags = CLK_SET_RATE_PARENT, 5872 .ops = &clk_branch2_ops, 5873 }, 5874 }, 5875 }; 5876 5877 static struct clk_branch gcc_video_axi0_clk = { 5878 .halt_reg = 0x32018, 5879 .halt_check = BRANCH_HALT_SKIP, 5880 .hwcg_reg = 0x32018, 5881 .hwcg_bit = 1, 5882 .clkr = { 5883 .enable_reg = 0x32018, 5884 .enable_mask = BIT(0), 5885 .hw.init = &(const struct clk_init_data) { 5886 .name = "gcc_video_axi0_clk", 5887 .ops = &clk_branch2_ops, 5888 }, 5889 }, 5890 }; 5891 5892 static struct clk_branch gcc_video_axi1_clk = { 5893 .halt_reg = 0x32024, 5894 .halt_check = BRANCH_HALT_SKIP, 5895 .hwcg_reg = 0x32024, 5896 .hwcg_bit = 1, 5897 .clkr = { 5898 .enable_reg = 0x32024, 5899 .enable_mask = BIT(0), 5900 .hw.init = &(const struct clk_init_data) { 5901 .name = "gcc_video_axi1_clk", 5902 .ops = &clk_branch2_ops, 5903 }, 5904 }, 5905 }; 5906 5907 static struct gdsc gcc_pcie_0_tunnel_gdsc = { 5908 .gdscr = 0xa0004, 5909 .en_rest_wait_val = 0x2, 5910 .en_few_wait_val = 0x2, 5911 .clk_dis_wait_val = 0xf, 5912 .pd = { 5913 .name = "gcc_pcie_0_tunnel_gdsc", 5914 }, 5915 .pwrsts = PWRSTS_OFF_ON, 5916 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 5917 }; 5918 5919 static struct gdsc gcc_pcie_1_tunnel_gdsc = { 5920 .gdscr = 0x2c004, 5921 .en_rest_wait_val = 0x2, 5922 .en_few_wait_val = 0x2, 5923 .clk_dis_wait_val = 0xf, 5924 .pd = { 5925 .name = "gcc_pcie_1_tunnel_gdsc", 5926 }, 5927 .pwrsts = PWRSTS_OFF_ON, 5928 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 5929 }; 5930 5931 static struct gdsc gcc_pcie_2_tunnel_gdsc = { 5932 .gdscr = 0x13004, 5933 .en_rest_wait_val = 0x2, 5934 .en_few_wait_val = 0x2, 5935 .clk_dis_wait_val = 0xf, 5936 .pd = { 5937 .name = "gcc_pcie_2_tunnel_gdsc", 5938 }, 5939 .pwrsts = PWRSTS_OFF_ON, 5940 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 5941 }; 5942 5943 static struct gdsc gcc_pcie_3_gdsc = { 5944 .gdscr = 0x58004, 5945 .en_rest_wait_val = 0x2, 5946 .en_few_wait_val = 0x2, 5947 .clk_dis_wait_val = 0xf, 5948 .pd = { 5949 .name = "gcc_pcie_3_gdsc", 5950 }, 5951 .pwrsts = PWRSTS_OFF_ON, 5952 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 5953 }; 5954 5955 static struct gdsc gcc_pcie_3_phy_gdsc = { 5956 .gdscr = 0x3e000, 5957 .en_rest_wait_val = 0x2, 5958 .en_few_wait_val = 0x2, 5959 .clk_dis_wait_val = 0x2, 5960 .pd = { 5961 .name = "gcc_pcie_3_phy_gdsc", 5962 }, 5963 .pwrsts = PWRSTS_OFF_ON, 5964 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 5965 }; 5966 5967 static struct gdsc gcc_pcie_4_gdsc = { 5968 .gdscr = 0x6b004, 5969 .en_rest_wait_val = 0x2, 5970 .en_few_wait_val = 0x2, 5971 .clk_dis_wait_val = 0xf, 5972 .pd = { 5973 .name = "gcc_pcie_4_gdsc", 5974 }, 5975 .pwrsts = PWRSTS_OFF_ON, 5976 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 5977 }; 5978 5979 static struct gdsc gcc_pcie_4_phy_gdsc = { 5980 .gdscr = 0x6c000, 5981 .en_rest_wait_val = 0x2, 5982 .en_few_wait_val = 0x2, 5983 .clk_dis_wait_val = 0x2, 5984 .pd = { 5985 .name = "gcc_pcie_4_phy_gdsc", 5986 }, 5987 .pwrsts = PWRSTS_OFF_ON, 5988 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 5989 }; 5990 5991 static struct gdsc gcc_pcie_5_gdsc = { 5992 .gdscr = 0x2f004, 5993 .en_rest_wait_val = 0x2, 5994 .en_few_wait_val = 0x2, 5995 .clk_dis_wait_val = 0xf, 5996 .pd = { 5997 .name = "gcc_pcie_5_gdsc", 5998 }, 5999 .pwrsts = PWRSTS_OFF_ON, 6000 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 6001 }; 6002 6003 static struct gdsc gcc_pcie_5_phy_gdsc = { 6004 .gdscr = 0x30000, 6005 .en_rest_wait_val = 0x2, 6006 .en_few_wait_val = 0x2, 6007 .clk_dis_wait_val = 0x2, 6008 .pd = { 6009 .name = "gcc_pcie_5_phy_gdsc", 6010 }, 6011 .pwrsts = PWRSTS_OFF_ON, 6012 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 6013 }; 6014 6015 static struct gdsc gcc_pcie_6_phy_gdsc = { 6016 .gdscr = 0x8e000, 6017 .en_rest_wait_val = 0x2, 6018 .en_few_wait_val = 0x2, 6019 .clk_dis_wait_val = 0x2, 6020 .pd = { 6021 .name = "gcc_pcie_6_phy_gdsc", 6022 }, 6023 .pwrsts = PWRSTS_OFF_ON, 6024 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 6025 }; 6026 6027 static struct gdsc gcc_pcie_6a_gdsc = { 6028 .gdscr = 0x31004, 6029 .en_rest_wait_val = 0x2, 6030 .en_few_wait_val = 0x2, 6031 .clk_dis_wait_val = 0xf, 6032 .pd = { 6033 .name = "gcc_pcie_6a_gdsc", 6034 }, 6035 .pwrsts = PWRSTS_OFF_ON, 6036 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 6037 }; 6038 6039 static struct gdsc gcc_pcie_6b_gdsc = { 6040 .gdscr = 0x8d004, 6041 .en_rest_wait_val = 0x2, 6042 .en_few_wait_val = 0x2, 6043 .clk_dis_wait_val = 0xf, 6044 .pd = { 6045 .name = "gcc_pcie_6b_gdsc", 6046 }, 6047 .pwrsts = PWRSTS_OFF_ON, 6048 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 6049 }; 6050 6051 static struct gdsc gcc_ufs_mem_phy_gdsc = { 6052 .gdscr = 0x9e000, 6053 .en_rest_wait_val = 0x2, 6054 .en_few_wait_val = 0x2, 6055 .clk_dis_wait_val = 0x2, 6056 .pd = { 6057 .name = "gcc_ufs_mem_phy_gdsc", 6058 }, 6059 .pwrsts = PWRSTS_OFF_ON, 6060 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6061 }; 6062 6063 static struct gdsc gcc_ufs_phy_gdsc = { 6064 .gdscr = 0x77004, 6065 .en_rest_wait_val = 0x2, 6066 .en_few_wait_val = 0x2, 6067 .clk_dis_wait_val = 0xf, 6068 .pd = { 6069 .name = "gcc_ufs_phy_gdsc", 6070 }, 6071 .pwrsts = PWRSTS_OFF_ON, 6072 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6073 }; 6074 6075 static struct gdsc gcc_usb20_prim_gdsc = { 6076 .gdscr = 0x29004, 6077 .en_rest_wait_val = 0x2, 6078 .en_few_wait_val = 0x2, 6079 .clk_dis_wait_val = 0xf, 6080 .pd = { 6081 .name = "gcc_usb20_prim_gdsc", 6082 }, 6083 .pwrsts = PWRSTS_OFF_ON, 6084 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6085 }; 6086 6087 static struct gdsc gcc_usb30_mp_gdsc = { 6088 .gdscr = 0x17004, 6089 .en_rest_wait_val = 0x2, 6090 .en_few_wait_val = 0x2, 6091 .clk_dis_wait_val = 0xf, 6092 .pd = { 6093 .name = "gcc_usb30_mp_gdsc", 6094 }, 6095 .pwrsts = PWRSTS_RET_ON, 6096 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6097 }; 6098 6099 static struct gdsc gcc_usb30_prim_gdsc = { 6100 .gdscr = 0x39004, 6101 .en_rest_wait_val = 0x2, 6102 .en_few_wait_val = 0x2, 6103 .clk_dis_wait_val = 0xf, 6104 .pd = { 6105 .name = "gcc_usb30_prim_gdsc", 6106 }, 6107 .pwrsts = PWRSTS_RET_ON, 6108 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6109 }; 6110 6111 static struct gdsc gcc_usb30_sec_gdsc = { 6112 .gdscr = 0xa1004, 6113 .en_rest_wait_val = 0x2, 6114 .en_few_wait_val = 0x2, 6115 .clk_dis_wait_val = 0xf, 6116 .pd = { 6117 .name = "gcc_usb30_sec_gdsc", 6118 }, 6119 .pwrsts = PWRSTS_RET_ON, 6120 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6121 }; 6122 6123 static struct gdsc gcc_usb30_tert_gdsc = { 6124 .gdscr = 0xa2004, 6125 .en_rest_wait_val = 0x2, 6126 .en_few_wait_val = 0x2, 6127 .clk_dis_wait_val = 0xf, 6128 .pd = { 6129 .name = "gcc_usb30_tert_gdsc", 6130 }, 6131 .pwrsts = PWRSTS_RET_ON, 6132 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6133 }; 6134 6135 static struct gdsc gcc_usb3_mp_ss0_phy_gdsc = { 6136 .gdscr = 0x1900c, 6137 .en_rest_wait_val = 0x2, 6138 .en_few_wait_val = 0x2, 6139 .clk_dis_wait_val = 0x2, 6140 .pd = { 6141 .name = "gcc_usb3_mp_ss0_phy_gdsc", 6142 }, 6143 .pwrsts = PWRSTS_RET_ON, 6144 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6145 }; 6146 6147 static struct gdsc gcc_usb3_mp_ss1_phy_gdsc = { 6148 .gdscr = 0x5400c, 6149 .en_rest_wait_val = 0x2, 6150 .en_few_wait_val = 0x2, 6151 .clk_dis_wait_val = 0x2, 6152 .pd = { 6153 .name = "gcc_usb3_mp_ss1_phy_gdsc", 6154 }, 6155 .pwrsts = PWRSTS_OFF_ON, 6156 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6157 }; 6158 6159 static struct gdsc gcc_usb4_0_gdsc = { 6160 .gdscr = 0x9f004, 6161 .en_rest_wait_val = 0x2, 6162 .en_few_wait_val = 0x2, 6163 .clk_dis_wait_val = 0xf, 6164 .pd = { 6165 .name = "gcc_usb4_0_gdsc", 6166 }, 6167 .pwrsts = PWRSTS_OFF_ON, 6168 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6169 }; 6170 6171 static struct gdsc gcc_usb4_1_gdsc = { 6172 .gdscr = 0x2b004, 6173 .en_rest_wait_val = 0x2, 6174 .en_few_wait_val = 0x2, 6175 .clk_dis_wait_val = 0xf, 6176 .pd = { 6177 .name = "gcc_usb4_1_gdsc", 6178 }, 6179 .pwrsts = PWRSTS_OFF_ON, 6180 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6181 }; 6182 6183 static struct gdsc gcc_usb4_2_gdsc = { 6184 .gdscr = 0x11004, 6185 .en_rest_wait_val = 0x2, 6186 .en_few_wait_val = 0x2, 6187 .clk_dis_wait_val = 0xf, 6188 .pd = { 6189 .name = "gcc_usb4_2_gdsc", 6190 }, 6191 .pwrsts = PWRSTS_OFF_ON, 6192 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6193 }; 6194 6195 static struct gdsc gcc_usb_0_phy_gdsc = { 6196 .gdscr = 0x50024, 6197 .en_rest_wait_val = 0x2, 6198 .en_few_wait_val = 0x2, 6199 .clk_dis_wait_val = 0x2, 6200 .pd = { 6201 .name = "gcc_usb_0_phy_gdsc", 6202 }, 6203 .pwrsts = PWRSTS_OFF_ON, 6204 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6205 }; 6206 6207 static struct gdsc gcc_usb_1_phy_gdsc = { 6208 .gdscr = 0x2a024, 6209 .en_rest_wait_val = 0x2, 6210 .en_few_wait_val = 0x2, 6211 .clk_dis_wait_val = 0x2, 6212 .pd = { 6213 .name = "gcc_usb_1_phy_gdsc", 6214 }, 6215 .pwrsts = PWRSTS_OFF_ON, 6216 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6217 }; 6218 6219 static struct gdsc gcc_usb_2_phy_gdsc = { 6220 .gdscr = 0xa3024, 6221 .en_rest_wait_val = 0x2, 6222 .en_few_wait_val = 0x2, 6223 .clk_dis_wait_val = 0x2, 6224 .pd = { 6225 .name = "gcc_usb_2_phy_gdsc", 6226 }, 6227 .pwrsts = PWRSTS_RET_ON, 6228 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6229 }; 6230 6231 static struct clk_regmap *gcc_x1e80100_clocks[] = { 6232 [GCC_AGGRE_NOC_USB_NORTH_AXI_CLK] = &gcc_aggre_noc_usb_north_axi_clk.clkr, 6233 [GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK] = &gcc_aggre_noc_usb_south_axi_clk.clkr, 6234 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 6235 [GCC_AGGRE_USB2_PRIM_AXI_CLK] = &gcc_aggre_usb2_prim_axi_clk.clkr, 6236 [GCC_AGGRE_USB3_MP_AXI_CLK] = &gcc_aggre_usb3_mp_axi_clk.clkr, 6237 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 6238 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, 6239 [GCC_AGGRE_USB3_TERT_AXI_CLK] = &gcc_aggre_usb3_tert_axi_clk.clkr, 6240 [GCC_AGGRE_USB4_0_AXI_CLK] = &gcc_aggre_usb4_0_axi_clk.clkr, 6241 [GCC_AGGRE_USB4_1_AXI_CLK] = &gcc_aggre_usb4_1_axi_clk.clkr, 6242 [GCC_AGGRE_USB4_2_AXI_CLK] = &gcc_aggre_usb4_2_axi_clk.clkr, 6243 [GCC_AGGRE_USB_NOC_AXI_CLK] = &gcc_aggre_usb_noc_axi_clk.clkr, 6244 [GCC_AV1E_AHB_CLK] = &gcc_av1e_ahb_clk.clkr, 6245 [GCC_AV1E_AXI_CLK] = &gcc_av1e_axi_clk.clkr, 6246 [GCC_AV1E_XO_CLK] = &gcc_av1e_xo_clk.clkr, 6247 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 6248 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 6249 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 6250 [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr, 6251 [GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_north_ahb_clk.clkr, 6252 [GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_south_ahb_clk.clkr, 6253 [GCC_CFG_NOC_USB2_PRIM_AXI_CLK] = &gcc_cfg_noc_usb2_prim_axi_clk.clkr, 6254 [GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr, 6255 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 6256 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, 6257 [GCC_CFG_NOC_USB3_TERT_AXI_CLK] = &gcc_cfg_noc_usb3_tert_axi_clk.clkr, 6258 [GCC_CFG_NOC_USB_ANOC_AHB_CLK] = &gcc_cfg_noc_usb_anoc_ahb_clk.clkr, 6259 [GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK] = &gcc_cfg_noc_usb_anoc_north_ahb_clk.clkr, 6260 [GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK] = &gcc_cfg_noc_usb_anoc_south_ahb_clk.clkr, 6261 [GCC_CNOC_PCIE1_TUNNEL_CLK] = &gcc_cnoc_pcie1_tunnel_clk.clkr, 6262 [GCC_CNOC_PCIE2_TUNNEL_CLK] = &gcc_cnoc_pcie2_tunnel_clk.clkr, 6263 [GCC_CNOC_PCIE_NORTH_SF_AXI_CLK] = &gcc_cnoc_pcie_north_sf_axi_clk.clkr, 6264 [GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK] = &gcc_cnoc_pcie_south_sf_axi_clk.clkr, 6265 [GCC_CNOC_PCIE_TUNNEL_CLK] = &gcc_cnoc_pcie_tunnel_clk.clkr, 6266 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 6267 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 6268 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, 6269 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 6270 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 6271 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 6272 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 6273 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 6274 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 6275 [GCC_GPLL0] = &gcc_gpll0.clkr, 6276 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 6277 [GCC_GPLL4] = &gcc_gpll4.clkr, 6278 [GCC_GPLL7] = &gcc_gpll7.clkr, 6279 [GCC_GPLL8] = &gcc_gpll8.clkr, 6280 [GCC_GPLL9] = &gcc_gpll9.clkr, 6281 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 6282 [GCC_GPU_GPLL0_CPH_CLK_SRC] = &gcc_gpu_gpll0_cph_clk_src.clkr, 6283 [GCC_GPU_GPLL0_DIV_CPH_CLK_SRC] = &gcc_gpu_gpll0_div_cph_clk_src.clkr, 6284 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 6285 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 6286 [GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr, 6287 [GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr, 6288 [GCC_PCIE2_PHY_RCHNG_CLK] = &gcc_pcie2_phy_rchng_clk.clkr, 6289 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 6290 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 6291 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 6292 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 6293 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 6294 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 6295 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 6296 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 6297 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 6298 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 6299 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 6300 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 6301 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, 6302 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 6303 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 6304 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 6305 [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr, 6306 [GCC_PCIE_2_AUX_CLK_SRC] = &gcc_pcie_2_aux_clk_src.clkr, 6307 [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr, 6308 [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr, 6309 [GCC_PCIE_2_PHY_RCHNG_CLK_SRC] = &gcc_pcie_2_phy_rchng_clk_src.clkr, 6310 [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr, 6311 [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr, 6312 [GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr, 6313 [GCC_PCIE_3_AUX_CLK] = &gcc_pcie_3_aux_clk.clkr, 6314 [GCC_PCIE_3_AUX_CLK_SRC] = &gcc_pcie_3_aux_clk_src.clkr, 6315 [GCC_PCIE_3_CFG_AHB_CLK] = &gcc_pcie_3_cfg_ahb_clk.clkr, 6316 [GCC_PCIE_3_MSTR_AXI_CLK] = &gcc_pcie_3_mstr_axi_clk.clkr, 6317 [GCC_PCIE_3_PHY_AUX_CLK] = &gcc_pcie_3_phy_aux_clk.clkr, 6318 [GCC_PCIE_3_PHY_RCHNG_CLK] = &gcc_pcie_3_phy_rchng_clk.clkr, 6319 [GCC_PCIE_3_PHY_RCHNG_CLK_SRC] = &gcc_pcie_3_phy_rchng_clk_src.clkr, 6320 [GCC_PCIE_3_PIPE_CLK] = &gcc_pcie_3_pipe_clk.clkr, 6321 [GCC_PCIE_3_PIPE_CLK_SRC] = &gcc_pcie_3_pipe_clk_src.clkr, 6322 [GCC_PCIE_3_PIPE_DIV_CLK_SRC] = &gcc_pcie_3_pipe_div_clk_src.clkr, 6323 [GCC_PCIE_3_PIPEDIV2_CLK] = &gcc_pcie_3_pipediv2_clk.clkr, 6324 [GCC_PCIE_3_SLV_AXI_CLK] = &gcc_pcie_3_slv_axi_clk.clkr, 6325 [GCC_PCIE_3_SLV_Q2A_AXI_CLK] = &gcc_pcie_3_slv_q2a_axi_clk.clkr, 6326 [GCC_PCIE_4_AUX_CLK] = &gcc_pcie_4_aux_clk.clkr, 6327 [GCC_PCIE_4_AUX_CLK_SRC] = &gcc_pcie_4_aux_clk_src.clkr, 6328 [GCC_PCIE_4_CFG_AHB_CLK] = &gcc_pcie_4_cfg_ahb_clk.clkr, 6329 [GCC_PCIE_4_MSTR_AXI_CLK] = &gcc_pcie_4_mstr_axi_clk.clkr, 6330 [GCC_PCIE_4_PHY_RCHNG_CLK] = &gcc_pcie_4_phy_rchng_clk.clkr, 6331 [GCC_PCIE_4_PHY_RCHNG_CLK_SRC] = &gcc_pcie_4_phy_rchng_clk_src.clkr, 6332 [GCC_PCIE_4_PIPE_CLK] = &gcc_pcie_4_pipe_clk.clkr, 6333 [GCC_PCIE_4_PIPE_CLK_SRC] = &gcc_pcie_4_pipe_clk_src.clkr, 6334 [GCC_PCIE_4_PIPE_DIV_CLK_SRC] = &gcc_pcie_4_pipe_div_clk_src.clkr, 6335 [GCC_PCIE_4_PIPEDIV2_CLK] = &gcc_pcie_4_pipediv2_clk.clkr, 6336 [GCC_PCIE_4_SLV_AXI_CLK] = &gcc_pcie_4_slv_axi_clk.clkr, 6337 [GCC_PCIE_4_SLV_Q2A_AXI_CLK] = &gcc_pcie_4_slv_q2a_axi_clk.clkr, 6338 [GCC_PCIE_5_AUX_CLK] = &gcc_pcie_5_aux_clk.clkr, 6339 [GCC_PCIE_5_AUX_CLK_SRC] = &gcc_pcie_5_aux_clk_src.clkr, 6340 [GCC_PCIE_5_CFG_AHB_CLK] = &gcc_pcie_5_cfg_ahb_clk.clkr, 6341 [GCC_PCIE_5_MSTR_AXI_CLK] = &gcc_pcie_5_mstr_axi_clk.clkr, 6342 [GCC_PCIE_5_PHY_RCHNG_CLK] = &gcc_pcie_5_phy_rchng_clk.clkr, 6343 [GCC_PCIE_5_PHY_RCHNG_CLK_SRC] = &gcc_pcie_5_phy_rchng_clk_src.clkr, 6344 [GCC_PCIE_5_PIPE_CLK] = &gcc_pcie_5_pipe_clk.clkr, 6345 [GCC_PCIE_5_PIPE_CLK_SRC] = &gcc_pcie_5_pipe_clk_src.clkr, 6346 [GCC_PCIE_5_PIPE_DIV_CLK_SRC] = &gcc_pcie_5_pipe_div_clk_src.clkr, 6347 [GCC_PCIE_5_PIPEDIV2_CLK] = &gcc_pcie_5_pipediv2_clk.clkr, 6348 [GCC_PCIE_5_SLV_AXI_CLK] = &gcc_pcie_5_slv_axi_clk.clkr, 6349 [GCC_PCIE_5_SLV_Q2A_AXI_CLK] = &gcc_pcie_5_slv_q2a_axi_clk.clkr, 6350 [GCC_PCIE_6A_AUX_CLK] = &gcc_pcie_6a_aux_clk.clkr, 6351 [GCC_PCIE_6A_AUX_CLK_SRC] = &gcc_pcie_6a_aux_clk_src.clkr, 6352 [GCC_PCIE_6A_CFG_AHB_CLK] = &gcc_pcie_6a_cfg_ahb_clk.clkr, 6353 [GCC_PCIE_6A_MSTR_AXI_CLK] = &gcc_pcie_6a_mstr_axi_clk.clkr, 6354 [GCC_PCIE_6A_PHY_AUX_CLK] = &gcc_pcie_6a_phy_aux_clk.clkr, 6355 [GCC_PCIE_6A_PHY_RCHNG_CLK] = &gcc_pcie_6a_phy_rchng_clk.clkr, 6356 [GCC_PCIE_6A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_6a_phy_rchng_clk_src.clkr, 6357 [GCC_PCIE_6A_PIPE_CLK] = &gcc_pcie_6a_pipe_clk.clkr, 6358 [GCC_PCIE_6A_PIPE_CLK_SRC] = &gcc_pcie_6a_pipe_clk_src.clkr, 6359 [GCC_PCIE_6A_PIPE_DIV_CLK_SRC] = &gcc_pcie_6a_pipe_div_clk_src.clkr, 6360 [GCC_PCIE_6A_PIPEDIV2_CLK] = &gcc_pcie_6a_pipediv2_clk.clkr, 6361 [GCC_PCIE_6A_SLV_AXI_CLK] = &gcc_pcie_6a_slv_axi_clk.clkr, 6362 [GCC_PCIE_6A_SLV_Q2A_AXI_CLK] = &gcc_pcie_6a_slv_q2a_axi_clk.clkr, 6363 [GCC_PCIE_6B_AUX_CLK] = &gcc_pcie_6b_aux_clk.clkr, 6364 [GCC_PCIE_6B_AUX_CLK_SRC] = &gcc_pcie_6b_aux_clk_src.clkr, 6365 [GCC_PCIE_6B_CFG_AHB_CLK] = &gcc_pcie_6b_cfg_ahb_clk.clkr, 6366 [GCC_PCIE_6B_MSTR_AXI_CLK] = &gcc_pcie_6b_mstr_axi_clk.clkr, 6367 [GCC_PCIE_6B_PHY_AUX_CLK] = &gcc_pcie_6b_phy_aux_clk.clkr, 6368 [GCC_PCIE_6B_PHY_RCHNG_CLK] = &gcc_pcie_6b_phy_rchng_clk.clkr, 6369 [GCC_PCIE_6B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_6b_phy_rchng_clk_src.clkr, 6370 [GCC_PCIE_6B_PIPE_CLK] = &gcc_pcie_6b_pipe_clk.clkr, 6371 [GCC_PCIE_6B_PIPE_CLK_SRC] = &gcc_pcie_6b_pipe_clk_src.clkr, 6372 [GCC_PCIE_6B_PIPE_DIV_CLK_SRC] = &gcc_pcie_6b_pipe_div_clk_src.clkr, 6373 [GCC_PCIE_6B_PIPEDIV2_CLK] = &gcc_pcie_6b_pipediv2_clk.clkr, 6374 [GCC_PCIE_6B_SLV_AXI_CLK] = &gcc_pcie_6b_slv_axi_clk.clkr, 6375 [GCC_PCIE_6B_SLV_Q2A_AXI_CLK] = &gcc_pcie_6b_slv_q2a_axi_clk.clkr, 6376 [GCC_PCIE_RSCC_AHB_CLK] = &gcc_pcie_rscc_ahb_clk.clkr, 6377 [GCC_PCIE_RSCC_XO_CLK] = &gcc_pcie_rscc_xo_clk.clkr, 6378 [GCC_PCIE_RSCC_XO_CLK_SRC] = &gcc_pcie_rscc_xo_clk_src.clkr, 6379 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 6380 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 6381 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 6382 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 6383 [GCC_QMIP_AV1E_AHB_CLK] = &gcc_qmip_av1e_ahb_clk.clkr, 6384 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 6385 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 6386 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 6387 [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr, 6388 [GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr, 6389 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 6390 [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr, 6391 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 6392 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 6393 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 6394 [GCC_QUPV3_WRAP0_QSPI_S2_CLK] = &gcc_qupv3_wrap0_qspi_s2_clk.clkr, 6395 [GCC_QUPV3_WRAP0_QSPI_S3_CLK] = &gcc_qupv3_wrap0_qspi_s3_clk.clkr, 6396 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 6397 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 6398 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 6399 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 6400 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 6401 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 6402 [GCC_QUPV3_WRAP0_S2_DIV_CLK_SRC] = &gcc_qupv3_wrap0_s2_div_clk_src.clkr, 6403 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 6404 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 6405 [GCC_QUPV3_WRAP0_S3_DIV_CLK_SRC] = &gcc_qupv3_wrap0_s3_div_clk_src.clkr, 6406 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 6407 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 6408 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 6409 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 6410 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 6411 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 6412 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 6413 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 6414 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 6415 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 6416 [GCC_QUPV3_WRAP1_QSPI_S2_CLK] = &gcc_qupv3_wrap1_qspi_s2_clk.clkr, 6417 [GCC_QUPV3_WRAP1_QSPI_S3_CLK] = &gcc_qupv3_wrap1_qspi_s3_clk.clkr, 6418 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 6419 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 6420 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 6421 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 6422 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 6423 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 6424 [GCC_QUPV3_WRAP1_S2_DIV_CLK_SRC] = &gcc_qupv3_wrap1_s2_div_clk_src.clkr, 6425 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 6426 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 6427 [GCC_QUPV3_WRAP1_S3_DIV_CLK_SRC] = &gcc_qupv3_wrap1_s3_div_clk_src.clkr, 6428 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 6429 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 6430 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 6431 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 6432 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 6433 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 6434 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 6435 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 6436 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, 6437 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, 6438 [GCC_QUPV3_WRAP2_QSPI_S2_CLK] = &gcc_qupv3_wrap2_qspi_s2_clk.clkr, 6439 [GCC_QUPV3_WRAP2_QSPI_S3_CLK] = &gcc_qupv3_wrap2_qspi_s3_clk.clkr, 6440 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 6441 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 6442 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 6443 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 6444 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 6445 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 6446 [GCC_QUPV3_WRAP2_S2_DIV_CLK_SRC] = &gcc_qupv3_wrap2_s2_div_clk_src.clkr, 6447 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 6448 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 6449 [GCC_QUPV3_WRAP2_S3_DIV_CLK_SRC] = &gcc_qupv3_wrap2_s3_div_clk_src.clkr, 6450 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 6451 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 6452 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, 6453 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, 6454 [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr, 6455 [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr, 6456 [GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr, 6457 [GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr, 6458 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 6459 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 6460 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 6461 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 6462 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 6463 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 6464 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 6465 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 6466 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 6467 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 6468 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 6469 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 6470 [GCC_SYS_NOC_USB_AXI_CLK] = &gcc_sys_noc_usb_axi_clk.clkr, 6471 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 6472 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 6473 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 6474 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 6475 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 6476 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 6477 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 6478 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 6479 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 6480 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 6481 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 6482 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 6483 [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr, 6484 [GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr, 6485 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr, 6486 [GCC_USB20_MOCK_UTMI_CLK_SRC] = &gcc_usb20_mock_utmi_clk_src.clkr, 6487 [GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb20_mock_utmi_postdiv_clk_src.clkr, 6488 [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr, 6489 [GCC_USB30_MP_MASTER_CLK] = &gcc_usb30_mp_master_clk.clkr, 6490 [GCC_USB30_MP_MASTER_CLK_SRC] = &gcc_usb30_mp_master_clk_src.clkr, 6491 [GCC_USB30_MP_MOCK_UTMI_CLK] = &gcc_usb30_mp_mock_utmi_clk.clkr, 6492 [GCC_USB30_MP_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mp_mock_utmi_clk_src.clkr, 6493 [GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr, 6494 [GCC_USB30_MP_SLEEP_CLK] = &gcc_usb30_mp_sleep_clk.clkr, 6495 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 6496 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 6497 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 6498 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 6499 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 6500 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 6501 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, 6502 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, 6503 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, 6504 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr, 6505 [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr, 6506 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, 6507 [GCC_USB30_TERT_MASTER_CLK] = &gcc_usb30_tert_master_clk.clkr, 6508 [GCC_USB30_TERT_MASTER_CLK_SRC] = &gcc_usb30_tert_master_clk_src.clkr, 6509 [GCC_USB30_TERT_MOCK_UTMI_CLK] = &gcc_usb30_tert_mock_utmi_clk.clkr, 6510 [GCC_USB30_TERT_MOCK_UTMI_CLK_SRC] = &gcc_usb30_tert_mock_utmi_clk_src.clkr, 6511 [GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr, 6512 [GCC_USB30_TERT_SLEEP_CLK] = &gcc_usb30_tert_sleep_clk.clkr, 6513 [GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr, 6514 [GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr, 6515 [GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr, 6516 [GCC_USB3_MP_PHY_PIPE_0_CLK] = &gcc_usb3_mp_phy_pipe_0_clk.clkr, 6517 [GCC_USB3_MP_PHY_PIPE_1_CLK] = &gcc_usb3_mp_phy_pipe_1_clk.clkr, 6518 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 6519 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 6520 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 6521 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 6522 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 6523 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, 6524 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, 6525 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, 6526 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, 6527 [GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr, 6528 [GCC_USB3_TERT_PHY_AUX_CLK] = &gcc_usb3_tert_phy_aux_clk.clkr, 6529 [GCC_USB3_TERT_PHY_AUX_CLK_SRC] = &gcc_usb3_tert_phy_aux_clk_src.clkr, 6530 [GCC_USB3_TERT_PHY_COM_AUX_CLK] = &gcc_usb3_tert_phy_com_aux_clk.clkr, 6531 [GCC_USB3_TERT_PHY_PIPE_CLK] = &gcc_usb3_tert_phy_pipe_clk.clkr, 6532 [GCC_USB3_TERT_PHY_PIPE_CLK_SRC] = &gcc_usb3_tert_phy_pipe_clk_src.clkr, 6533 [GCC_USB4_0_CFG_AHB_CLK] = &gcc_usb4_0_cfg_ahb_clk.clkr, 6534 [GCC_USB4_0_DP0_CLK] = &gcc_usb4_0_dp0_clk.clkr, 6535 [GCC_USB4_0_DP1_CLK] = &gcc_usb4_0_dp1_clk.clkr, 6536 [GCC_USB4_0_MASTER_CLK] = &gcc_usb4_0_master_clk.clkr, 6537 [GCC_USB4_0_MASTER_CLK_SRC] = &gcc_usb4_0_master_clk_src.clkr, 6538 [GCC_USB4_0_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_0_phy_p2rr2p_pipe_clk.clkr, 6539 [GCC_USB4_0_PHY_PCIE_PIPE_CLK] = &gcc_usb4_0_phy_pcie_pipe_clk.clkr, 6540 [GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_clk_src.clkr, 6541 [GCC_USB4_0_PHY_RX0_CLK] = &gcc_usb4_0_phy_rx0_clk.clkr, 6542 [GCC_USB4_0_PHY_RX1_CLK] = &gcc_usb4_0_phy_rx1_clk.clkr, 6543 [GCC_USB4_0_PHY_USB_PIPE_CLK] = &gcc_usb4_0_phy_usb_pipe_clk.clkr, 6544 [GCC_USB4_0_SB_IF_CLK] = &gcc_usb4_0_sb_if_clk.clkr, 6545 [GCC_USB4_0_SB_IF_CLK_SRC] = &gcc_usb4_0_sb_if_clk_src.clkr, 6546 [GCC_USB4_0_SYS_CLK] = &gcc_usb4_0_sys_clk.clkr, 6547 [GCC_USB4_0_TMU_CLK] = &gcc_usb4_0_tmu_clk.clkr, 6548 [GCC_USB4_0_TMU_CLK_SRC] = &gcc_usb4_0_tmu_clk_src.clkr, 6549 [GCC_USB4_1_CFG_AHB_CLK] = &gcc_usb4_1_cfg_ahb_clk.clkr, 6550 [GCC_USB4_1_DP0_CLK] = &gcc_usb4_1_dp0_clk.clkr, 6551 [GCC_USB4_1_DP1_CLK] = &gcc_usb4_1_dp1_clk.clkr, 6552 [GCC_USB4_1_MASTER_CLK] = &gcc_usb4_1_master_clk.clkr, 6553 [GCC_USB4_1_MASTER_CLK_SRC] = &gcc_usb4_1_master_clk_src.clkr, 6554 [GCC_USB4_1_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_1_phy_p2rr2p_pipe_clk.clkr, 6555 [GCC_USB4_1_PHY_PCIE_PIPE_CLK] = &gcc_usb4_1_phy_pcie_pipe_clk.clkr, 6556 [GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_clk_src.clkr, 6557 [GCC_USB4_1_PHY_RX0_CLK] = &gcc_usb4_1_phy_rx0_clk.clkr, 6558 [GCC_USB4_1_PHY_RX1_CLK] = &gcc_usb4_1_phy_rx1_clk.clkr, 6559 [GCC_USB4_1_PHY_USB_PIPE_CLK] = &gcc_usb4_1_phy_usb_pipe_clk.clkr, 6560 [GCC_USB4_1_SB_IF_CLK] = &gcc_usb4_1_sb_if_clk.clkr, 6561 [GCC_USB4_1_SB_IF_CLK_SRC] = &gcc_usb4_1_sb_if_clk_src.clkr, 6562 [GCC_USB4_1_SYS_CLK] = &gcc_usb4_1_sys_clk.clkr, 6563 [GCC_USB4_1_TMU_CLK] = &gcc_usb4_1_tmu_clk.clkr, 6564 [GCC_USB4_1_TMU_CLK_SRC] = &gcc_usb4_1_tmu_clk_src.clkr, 6565 [GCC_USB4_2_CFG_AHB_CLK] = &gcc_usb4_2_cfg_ahb_clk.clkr, 6566 [GCC_USB4_2_DP0_CLK] = &gcc_usb4_2_dp0_clk.clkr, 6567 [GCC_USB4_2_DP1_CLK] = &gcc_usb4_2_dp1_clk.clkr, 6568 [GCC_USB4_2_MASTER_CLK] = &gcc_usb4_2_master_clk.clkr, 6569 [GCC_USB4_2_MASTER_CLK_SRC] = &gcc_usb4_2_master_clk_src.clkr, 6570 [GCC_USB4_2_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_2_phy_p2rr2p_pipe_clk.clkr, 6571 [GCC_USB4_2_PHY_PCIE_PIPE_CLK] = &gcc_usb4_2_phy_pcie_pipe_clk.clkr, 6572 [GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_clk_src.clkr, 6573 [GCC_USB4_2_PHY_RX0_CLK] = &gcc_usb4_2_phy_rx0_clk.clkr, 6574 [GCC_USB4_2_PHY_RX1_CLK] = &gcc_usb4_2_phy_rx1_clk.clkr, 6575 [GCC_USB4_2_PHY_USB_PIPE_CLK] = &gcc_usb4_2_phy_usb_pipe_clk.clkr, 6576 [GCC_USB4_2_SB_IF_CLK] = &gcc_usb4_2_sb_if_clk.clkr, 6577 [GCC_USB4_2_SB_IF_CLK_SRC] = &gcc_usb4_2_sb_if_clk_src.clkr, 6578 [GCC_USB4_2_SYS_CLK] = &gcc_usb4_2_sys_clk.clkr, 6579 [GCC_USB4_2_TMU_CLK] = &gcc_usb4_2_tmu_clk.clkr, 6580 [GCC_USB4_2_TMU_CLK_SRC] = &gcc_usb4_2_tmu_clk_src.clkr, 6581 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 6582 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 6583 }; 6584 6585 static struct gdsc *gcc_x1e80100_gdscs[] = { 6586 [GCC_PCIE_0_TUNNEL_GDSC] = &gcc_pcie_0_tunnel_gdsc, 6587 [GCC_PCIE_1_TUNNEL_GDSC] = &gcc_pcie_1_tunnel_gdsc, 6588 [GCC_PCIE_2_TUNNEL_GDSC] = &gcc_pcie_2_tunnel_gdsc, 6589 [GCC_PCIE_3_GDSC] = &gcc_pcie_3_gdsc, 6590 [GCC_PCIE_3_PHY_GDSC] = &gcc_pcie_3_phy_gdsc, 6591 [GCC_PCIE_4_GDSC] = &gcc_pcie_4_gdsc, 6592 [GCC_PCIE_4_PHY_GDSC] = &gcc_pcie_4_phy_gdsc, 6593 [GCC_PCIE_5_GDSC] = &gcc_pcie_5_gdsc, 6594 [GCC_PCIE_5_PHY_GDSC] = &gcc_pcie_5_phy_gdsc, 6595 [GCC_PCIE_6_PHY_GDSC] = &gcc_pcie_6_phy_gdsc, 6596 [GCC_PCIE_6A_GDSC] = &gcc_pcie_6a_gdsc, 6597 [GCC_PCIE_6B_GDSC] = &gcc_pcie_6b_gdsc, 6598 [GCC_UFS_MEM_PHY_GDSC] = &gcc_ufs_mem_phy_gdsc, 6599 [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc, 6600 [GCC_USB20_PRIM_GDSC] = &gcc_usb20_prim_gdsc, 6601 [GCC_USB30_MP_GDSC] = &gcc_usb30_mp_gdsc, 6602 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, 6603 [GCC_USB30_SEC_GDSC] = &gcc_usb30_sec_gdsc, 6604 [GCC_USB30_TERT_GDSC] = &gcc_usb30_tert_gdsc, 6605 [GCC_USB3_MP_SS0_PHY_GDSC] = &gcc_usb3_mp_ss0_phy_gdsc, 6606 [GCC_USB3_MP_SS1_PHY_GDSC] = &gcc_usb3_mp_ss1_phy_gdsc, 6607 [GCC_USB4_0_GDSC] = &gcc_usb4_0_gdsc, 6608 [GCC_USB4_1_GDSC] = &gcc_usb4_1_gdsc, 6609 [GCC_USB4_2_GDSC] = &gcc_usb4_2_gdsc, 6610 [GCC_USB_0_PHY_GDSC] = &gcc_usb_0_phy_gdsc, 6611 [GCC_USB_1_PHY_GDSC] = &gcc_usb_1_phy_gdsc, 6612 [GCC_USB_2_PHY_GDSC] = &gcc_usb_2_phy_gdsc, 6613 }; 6614 6615 static const struct qcom_reset_map gcc_x1e80100_resets[] = { 6616 [GCC_AV1E_BCR] = { 0x4a000 }, 6617 [GCC_CAMERA_BCR] = { 0x26000 }, 6618 [GCC_DISPLAY_BCR] = { 0x27000 }, 6619 [GCC_GPU_BCR] = { 0x71000 }, 6620 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, 6621 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, 6622 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 6623 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 }, 6624 [GCC_PCIE_0_TUNNEL_BCR] = { 0xa0000 }, 6625 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 }, 6626 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 }, 6627 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, 6628 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 }, 6629 [GCC_PCIE_1_TUNNEL_BCR] = { 0x2c000 }, 6630 [GCC_PCIE_2_LINK_DOWN_BCR] = { 0xa5014 }, 6631 [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0xa5020 }, 6632 [GCC_PCIE_2_PHY_BCR] = { 0xa501c }, 6633 [GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0xa5028 }, 6634 [GCC_PCIE_2_TUNNEL_BCR] = { 0x13000 }, 6635 [GCC_PCIE_3_BCR] = { 0x58000 }, 6636 [GCC_PCIE_3_LINK_DOWN_BCR] = { 0xab014 }, 6637 [GCC_PCIE_3_NOCSR_COM_PHY_BCR] = { 0xab020 }, 6638 [GCC_PCIE_3_PHY_BCR] = { 0xab01c }, 6639 [GCC_PCIE_3_PHY_NOCSR_COM_PHY_BCR] = { 0xab024 }, 6640 [GCC_PCIE_4_BCR] = { 0x6b000 }, 6641 [GCC_PCIE_4_LINK_DOWN_BCR] = { 0xb3014 }, 6642 [GCC_PCIE_4_NOCSR_COM_PHY_BCR] = { 0xb3020 }, 6643 [GCC_PCIE_4_PHY_BCR] = { 0xb301c }, 6644 [GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] = { 0xb3028 }, 6645 [GCC_PCIE_5_BCR] = { 0x2f000 }, 6646 [GCC_PCIE_5_LINK_DOWN_BCR] = { 0xaa014 }, 6647 [GCC_PCIE_5_NOCSR_COM_PHY_BCR] = { 0xaa020 }, 6648 [GCC_PCIE_5_PHY_BCR] = { 0xaa01c }, 6649 [GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR] = { 0xaa028 }, 6650 [GCC_PCIE_6A_BCR] = { 0x31000 }, 6651 [GCC_PCIE_6A_LINK_DOWN_BCR] = { 0xac014 }, 6652 [GCC_PCIE_6A_NOCSR_COM_PHY_BCR] = { 0xac020 }, 6653 [GCC_PCIE_6A_PHY_BCR] = { 0xac01c }, 6654 [GCC_PCIE_6A_PHY_NOCSR_COM_PHY_BCR] = { 0xac024 }, 6655 [GCC_PCIE_6B_BCR] = { 0x8d000 }, 6656 [GCC_PCIE_6B_LINK_DOWN_BCR] = { 0xb5014 }, 6657 [GCC_PCIE_6B_NOCSR_COM_PHY_BCR] = { 0xb5020 }, 6658 [GCC_PCIE_6B_PHY_BCR] = { 0xb501c }, 6659 [GCC_PCIE_6B_PHY_NOCSR_COM_PHY_BCR] = { 0xb5024 }, 6660 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 6661 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c }, 6662 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, 6663 [GCC_PCIE_RSCC_BCR] = { 0xa4000 }, 6664 [GCC_PDM_BCR] = { 0x33000 }, 6665 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x42000 }, 6666 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, 6667 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, 6668 [GCC_QUSB2PHY_HS0_MP_BCR] = { 0x1200c }, 6669 [GCC_QUSB2PHY_HS1_MP_BCR] = { 0x12010 }, 6670 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 6671 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 6672 [GCC_QUSB2PHY_TERT_BCR] = { 0x12008 }, 6673 [GCC_QUSB2PHY_USB20_HS_BCR] = { 0x12014 }, 6674 [GCC_SDCC2_BCR] = { 0x14000 }, 6675 [GCC_SDCC4_BCR] = { 0x16000 }, 6676 [GCC_UFS_PHY_BCR] = { 0x77000 }, 6677 [GCC_USB20_PRIM_BCR] = { 0x29000 }, 6678 [GCC_USB30_MP_BCR] = { 0x17000 }, 6679 [GCC_USB30_PRIM_BCR] = { 0x39000 }, 6680 [GCC_USB30_SEC_BCR] = { 0xa1000 }, 6681 [GCC_USB30_TERT_BCR] = { 0xa2000 }, 6682 [GCC_USB3_MP_SS0_PHY_BCR] = { 0x19008 }, 6683 [GCC_USB3_MP_SS1_PHY_BCR] = { 0x54008 }, 6684 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 6685 [GCC_USB3_PHY_SEC_BCR] = { 0x2a000 }, 6686 [GCC_USB3_PHY_TERT_BCR] = { 0xa3000 }, 6687 [GCC_USB3_UNIPHY_MP0_BCR] = { 0x19000 }, 6688 [GCC_USB3_UNIPHY_MP1_BCR] = { 0x54000 }, 6689 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 6690 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x2a004 }, 6691 [GCC_USB3PHY_PHY_TERT_BCR] = { 0xa3004 }, 6692 [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x19004 }, 6693 [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x54004 }, 6694 [GCC_USB4_0_BCR] = { 0x9f000 }, 6695 [GCC_USB4_0_DP0_PHY_PRIM_BCR] = { 0x50010 }, 6696 [GCC_USB4_1_DP0_PHY_SEC_BCR] = { 0x2a010 }, 6697 [GCC_USB4_2_DP0_PHY_TERT_BCR] = { 0xa3010 }, 6698 [GCC_USB4_1_BCR] = { 0x2b000 }, 6699 [GCC_USB4_2_BCR] = { 0x11000 }, 6700 [GCC_USB_0_PHY_BCR] = { 0x50020 }, 6701 [GCC_USB_1_PHY_BCR] = { 0x2a020 }, 6702 [GCC_USB_2_PHY_BCR] = { 0xa3020 }, 6703 [GCC_VIDEO_BCR] = { 0x32000 }, 6704 }; 6705 6706 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 6707 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 6708 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 6709 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 6710 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 6711 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 6712 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 6713 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 6714 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 6715 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 6716 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 6717 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 6718 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 6719 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 6720 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 6721 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 6722 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 6723 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 6724 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 6725 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), 6726 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), 6727 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 6728 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), 6729 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src), 6730 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src), 6731 }; 6732 6733 static const struct regmap_config gcc_x1e80100_regmap_config = { 6734 .reg_bits = 32, 6735 .reg_stride = 4, 6736 .val_bits = 32, 6737 .max_register = 0x1f41f0, 6738 .fast_io = true, 6739 }; 6740 6741 static const struct qcom_cc_desc gcc_x1e80100_desc = { 6742 .config = &gcc_x1e80100_regmap_config, 6743 .clks = gcc_x1e80100_clocks, 6744 .num_clks = ARRAY_SIZE(gcc_x1e80100_clocks), 6745 .resets = gcc_x1e80100_resets, 6746 .num_resets = ARRAY_SIZE(gcc_x1e80100_resets), 6747 .gdscs = gcc_x1e80100_gdscs, 6748 .num_gdscs = ARRAY_SIZE(gcc_x1e80100_gdscs), 6749 }; 6750 6751 static const struct of_device_id gcc_x1e80100_match_table[] = { 6752 { .compatible = "qcom,x1e80100-gcc" }, 6753 { } 6754 }; 6755 MODULE_DEVICE_TABLE(of, gcc_x1e80100_match_table); 6756 6757 static int gcc_x1e80100_probe(struct platform_device *pdev) 6758 { 6759 struct regmap *regmap; 6760 int ret; 6761 6762 regmap = qcom_cc_map(pdev, &gcc_x1e80100_desc); 6763 if (IS_ERR(regmap)) 6764 return PTR_ERR(regmap); 6765 6766 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 6767 ARRAY_SIZE(gcc_dfs_clocks)); 6768 if (ret) 6769 return ret; 6770 6771 /* Keep the critical clock always-On */ 6772 regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); /* gcc_camera_ahb_clk */ 6773 regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); /* gcc_camera_xo_clk */ 6774 regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); /* gcc_disp_ahb_clk */ 6775 regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0)); /* gcc_disp_xo_clk */ 6776 regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); /* gcc_video_ahb_clk */ 6777 regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0)); /* gcc_video_xo_clk */ 6778 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); /* gcc_gpu_cfg_ahb_clk */ 6779 6780 /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */ 6781 regmap_write(regmap, 0x52224, 0x0); 6782 6783 return qcom_cc_really_probe(pdev, &gcc_x1e80100_desc, regmap); 6784 } 6785 6786 static struct platform_driver gcc_x1e80100_driver = { 6787 .probe = gcc_x1e80100_probe, 6788 .driver = { 6789 .name = "gcc-x1e80100", 6790 .of_match_table = gcc_x1e80100_match_table, 6791 }, 6792 }; 6793 6794 static int __init gcc_x1e80100_init(void) 6795 { 6796 return platform_driver_register(&gcc_x1e80100_driver); 6797 } 6798 subsys_initcall(gcc_x1e80100_init); 6799 6800 static void __exit gcc_x1e80100_exit(void) 6801 { 6802 platform_driver_unregister(&gcc_x1e80100_driver); 6803 } 6804 module_exit(gcc_x1e80100_exit); 6805 6806 MODULE_DESCRIPTION("QTI GCC X1E80100 Driver"); 6807 MODULE_LICENSE("GPL"); 6808