1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,x1e80100-gcc.h> 12 13 #include "clk-alpha-pll.h" 14 #include "clk-branch.h" 15 #include "clk-rcg.h" 16 #include "clk-regmap.h" 17 #include "clk-regmap-divider.h" 18 #include "clk-regmap-mux.h" 19 #include "clk-regmap-phy-mux.h" 20 #include "gdsc.h" 21 #include "reset.h" 22 23 enum { 24 DT_BI_TCXO, 25 DT_SLEEP_CLK, 26 DT_PCIE_3_PIPE, 27 DT_PCIE_4_PIPE, 28 DT_PCIE_5_PIPE, 29 DT_PCIE_6A_PIPE, 30 DT_PCIE_6B_PIPE, 31 DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE, 32 DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE, 33 DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE, 34 DT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC, 35 DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC, 36 DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC, 37 DT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC, 38 DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC, 39 DT_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC, 40 DT_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC, 41 DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC, 42 DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, 43 DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 44 DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC, 45 DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC, 46 DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC, 47 DT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC, 48 DT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC, 49 DT_QUSB4PHY_0_GCC_USB4_RX0_CLK, 50 DT_QUSB4PHY_0_GCC_USB4_RX1_CLK, 51 DT_QUSB4PHY_1_GCC_USB4_RX0_CLK, 52 DT_QUSB4PHY_1_GCC_USB4_RX1_CLK, 53 DT_QUSB4PHY_2_GCC_USB4_RX0_CLK, 54 DT_QUSB4PHY_2_GCC_USB4_RX1_CLK, 55 DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 56 DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 57 DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 58 DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 59 DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 60 DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 61 DT_UFS_PHY_RX_SYMBOL_0_CLK, 62 DT_UFS_PHY_RX_SYMBOL_1_CLK, 63 DT_UFS_PHY_TX_SYMBOL_0_CLK, 64 }; 65 66 enum { 67 P_BI_TCXO, 68 P_GCC_GPLL0_OUT_EVEN, 69 P_GCC_GPLL0_OUT_MAIN, 70 P_GCC_GPLL4_OUT_MAIN, 71 P_GCC_GPLL7_OUT_MAIN, 72 P_GCC_GPLL8_OUT_MAIN, 73 P_GCC_GPLL9_OUT_MAIN, 74 P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 75 P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC, 76 P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC, 77 P_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC, 78 P_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC, 79 P_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC, 80 P_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC, 81 P_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC, 82 P_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC, 83 P_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC, 84 P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC, 85 P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, 86 P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 87 P_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC, 88 P_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC, 89 P_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC, 90 P_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC, 91 P_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC, 92 P_QUSB4PHY_0_GCC_USB4_RX0_CLK, 93 P_QUSB4PHY_0_GCC_USB4_RX1_CLK, 94 P_QUSB4PHY_1_GCC_USB4_RX0_CLK, 95 P_QUSB4PHY_1_GCC_USB4_RX1_CLK, 96 P_QUSB4PHY_2_GCC_USB4_RX0_CLK, 97 P_QUSB4PHY_2_GCC_USB4_RX1_CLK, 98 P_SLEEP_CLK, 99 P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 100 P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 101 P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 102 P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 103 P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 104 P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 105 P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 106 P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 107 P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 108 P_UFS_PHY_RX_SYMBOL_0_CLK, 109 P_UFS_PHY_RX_SYMBOL_1_CLK, 110 P_UFS_PHY_TX_SYMBOL_0_CLK, 111 }; 112 113 static struct clk_alpha_pll gcc_gpll0 = { 114 .offset = 0x0, 115 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 116 .clkr = { 117 .enable_reg = 0x52030, 118 .enable_mask = BIT(0), 119 .hw.init = &(const struct clk_init_data) { 120 .name = "gcc_gpll0", 121 .parent_data = &(const struct clk_parent_data) { 122 .index = DT_BI_TCXO, 123 }, 124 .num_parents = 1, 125 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 126 }, 127 }, 128 }; 129 130 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 131 { 0x1, 2 }, 132 { } 133 }; 134 135 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 136 .offset = 0x0, 137 .post_div_shift = 10, 138 .post_div_table = post_div_table_gcc_gpll0_out_even, 139 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 140 .width = 4, 141 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 142 .clkr.hw.init = &(const struct clk_init_data) { 143 .name = "gcc_gpll0_out_even", 144 .parent_hws = (const struct clk_hw*[]) { 145 &gcc_gpll0.clkr.hw, 146 }, 147 .num_parents = 1, 148 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 149 }, 150 }; 151 152 static struct clk_alpha_pll gcc_gpll4 = { 153 .offset = 0x4000, 154 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 155 .clkr = { 156 .enable_reg = 0x52030, 157 .enable_mask = BIT(4), 158 .hw.init = &(const struct clk_init_data) { 159 .name = "gcc_gpll4", 160 .parent_data = &(const struct clk_parent_data) { 161 .index = DT_BI_TCXO, 162 }, 163 .num_parents = 1, 164 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 165 }, 166 }, 167 }; 168 169 static struct clk_alpha_pll gcc_gpll7 = { 170 .offset = 0x7000, 171 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 172 .clkr = { 173 .enable_reg = 0x52030, 174 .enable_mask = BIT(7), 175 .hw.init = &(const struct clk_init_data) { 176 .name = "gcc_gpll7", 177 .parent_data = &(const struct clk_parent_data) { 178 .index = DT_BI_TCXO, 179 }, 180 .num_parents = 1, 181 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 182 }, 183 }, 184 }; 185 186 static struct clk_alpha_pll gcc_gpll8 = { 187 .offset = 0x8000, 188 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 189 .clkr = { 190 .enable_reg = 0x52030, 191 .enable_mask = BIT(8), 192 .hw.init = &(const struct clk_init_data) { 193 .name = "gcc_gpll8", 194 .parent_data = &(const struct clk_parent_data) { 195 .index = DT_BI_TCXO, 196 }, 197 .num_parents = 1, 198 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 199 }, 200 }, 201 }; 202 203 static struct clk_alpha_pll gcc_gpll9 = { 204 .offset = 0x9000, 205 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 206 .clkr = { 207 .enable_reg = 0x52030, 208 .enable_mask = BIT(9), 209 .hw.init = &(const struct clk_init_data) { 210 .name = "gcc_gpll9", 211 .parent_data = &(const struct clk_parent_data) { 212 .index = DT_BI_TCXO, 213 }, 214 .num_parents = 1, 215 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 216 }, 217 }, 218 }; 219 220 static const struct parent_map gcc_parent_map_0[] = { 221 { P_BI_TCXO, 0 }, 222 { P_GCC_GPLL0_OUT_MAIN, 1 }, 223 { P_GCC_GPLL0_OUT_EVEN, 6 }, 224 }; 225 226 static const struct clk_parent_data gcc_parent_data_0[] = { 227 { .index = DT_BI_TCXO }, 228 { .hw = &gcc_gpll0.clkr.hw }, 229 { .hw = &gcc_gpll0_out_even.clkr.hw }, 230 }; 231 232 static const struct parent_map gcc_parent_map_1[] = { 233 { P_BI_TCXO, 0 }, 234 { P_SLEEP_CLK, 5 }, 235 }; 236 237 static const struct clk_parent_data gcc_parent_data_1[] = { 238 { .index = DT_BI_TCXO }, 239 { .index = DT_SLEEP_CLK }, 240 }; 241 242 static const struct parent_map gcc_parent_map_2[] = { 243 { P_BI_TCXO, 0 }, 244 { P_GCC_GPLL0_OUT_MAIN, 1 }, 245 { P_SLEEP_CLK, 5 }, 246 { P_GCC_GPLL0_OUT_EVEN, 6 }, 247 }; 248 249 static const struct clk_parent_data gcc_parent_data_2[] = { 250 { .index = DT_BI_TCXO }, 251 { .hw = &gcc_gpll0.clkr.hw }, 252 { .index = DT_SLEEP_CLK }, 253 { .hw = &gcc_gpll0_out_even.clkr.hw }, 254 }; 255 256 static const struct parent_map gcc_parent_map_3[] = { 257 { P_BI_TCXO, 0 }, 258 }; 259 260 static const struct clk_parent_data gcc_parent_data_3[] = { 261 { .index = DT_BI_TCXO }, 262 }; 263 264 static const struct parent_map gcc_parent_map_4[] = { 265 { P_BI_TCXO, 0 }, 266 { P_GCC_GPLL0_OUT_MAIN, 1 }, 267 { P_GCC_GPLL8_OUT_MAIN, 2 }, 268 { P_GCC_GPLL0_OUT_EVEN, 6 }, 269 }; 270 271 static const struct clk_parent_data gcc_parent_data_4[] = { 272 { .index = DT_BI_TCXO }, 273 { .hw = &gcc_gpll0.clkr.hw }, 274 { .hw = &gcc_gpll8.clkr.hw }, 275 { .hw = &gcc_gpll0_out_even.clkr.hw }, 276 }; 277 278 static const struct parent_map gcc_parent_map_5[] = { 279 { P_BI_TCXO, 0 }, 280 { P_GCC_GPLL0_OUT_MAIN, 1 }, 281 { P_GCC_GPLL7_OUT_MAIN, 2 }, 282 { P_SLEEP_CLK, 5 }, 283 }; 284 285 static const struct clk_parent_data gcc_parent_data_5[] = { 286 { .index = DT_BI_TCXO }, 287 { .hw = &gcc_gpll0.clkr.hw }, 288 { .hw = &gcc_gpll7.clkr.hw }, 289 { .index = DT_SLEEP_CLK }, 290 }; 291 292 static const struct parent_map gcc_parent_map_6[] = { 293 { P_BI_TCXO, 0 }, 294 { P_GCC_GPLL0_OUT_MAIN, 1 }, 295 { P_GCC_GPLL7_OUT_MAIN, 2 }, 296 }; 297 298 static const struct clk_parent_data gcc_parent_data_6[] = { 299 { .index = DT_BI_TCXO }, 300 { .hw = &gcc_gpll0.clkr.hw }, 301 { .hw = &gcc_gpll7.clkr.hw }, 302 }; 303 304 static const struct parent_map gcc_parent_map_7[] = { 305 { P_BI_TCXO, 0 }, 306 { P_GCC_GPLL0_OUT_MAIN, 1 }, 307 { P_GCC_GPLL4_OUT_MAIN, 5 }, 308 { P_GCC_GPLL0_OUT_EVEN, 6 }, 309 }; 310 311 static const struct clk_parent_data gcc_parent_data_7[] = { 312 { .index = DT_BI_TCXO }, 313 { .hw = &gcc_gpll0.clkr.hw }, 314 { .hw = &gcc_gpll4.clkr.hw }, 315 { .hw = &gcc_gpll0_out_even.clkr.hw }, 316 }; 317 318 static const struct parent_map gcc_parent_map_8[] = { 319 { P_BI_TCXO, 0 }, 320 { P_GCC_GPLL0_OUT_MAIN, 1 }, 321 { P_GCC_GPLL7_OUT_MAIN, 2 }, 322 { P_GCC_GPLL0_OUT_EVEN, 6 }, 323 }; 324 325 static const struct clk_parent_data gcc_parent_data_8[] = { 326 { .index = DT_BI_TCXO }, 327 { .hw = &gcc_gpll0.clkr.hw }, 328 { .hw = &gcc_gpll7.clkr.hw }, 329 { .hw = &gcc_gpll0_out_even.clkr.hw }, 330 }; 331 332 static const struct parent_map gcc_parent_map_9[] = { 333 { P_BI_TCXO, 0 }, 334 { P_GCC_GPLL0_OUT_MAIN, 1 }, 335 { P_GCC_GPLL9_OUT_MAIN, 2 }, 336 { P_GCC_GPLL4_OUT_MAIN, 5 }, 337 { P_GCC_GPLL0_OUT_EVEN, 6 }, 338 }; 339 340 static const struct clk_parent_data gcc_parent_data_10[] = { 341 { .index = DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE }, 342 { .index = DT_BI_TCXO }, 343 }; 344 345 static const struct parent_map gcc_parent_map_10[] = { 346 { P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 347 { P_BI_TCXO, 2 }, 348 }; 349 350 static const struct clk_parent_data gcc_parent_data_11[] = { 351 { .index = DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE }, 352 { .index = DT_BI_TCXO }, 353 }; 354 355 static const struct parent_map gcc_parent_map_11[] = { 356 { P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 357 { P_BI_TCXO, 2 }, 358 }; 359 360 static const struct clk_parent_data gcc_parent_data_12[] = { 361 { .index = DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE }, 362 { .index = DT_BI_TCXO }, 363 }; 364 365 static const struct parent_map gcc_parent_map_12[] = { 366 { P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 367 { P_BI_TCXO, 2 }, 368 }; 369 370 static const struct clk_parent_data gcc_parent_data_9[] = { 371 { .index = DT_BI_TCXO }, 372 { .hw = &gcc_gpll0.clkr.hw }, 373 { .hw = &gcc_gpll9.clkr.hw }, 374 { .hw = &gcc_gpll4.clkr.hw }, 375 { .hw = &gcc_gpll0_out_even.clkr.hw }, 376 }; 377 378 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 379 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 380 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 381 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 382 { } 383 }; 384 385 static const struct clk_parent_data gcc_parent_data_13[] = { 386 { .index = DT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC }, 387 { .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 388 }; 389 390 static const struct clk_parent_data gcc_parent_data_14[] = { 391 { .index = DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC }, 392 { .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 393 }; 394 395 static const struct clk_parent_data gcc_parent_data_15[] = { 396 { .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK }, 397 { .index = DT_BI_TCXO }, 398 }; 399 400 static const struct clk_parent_data gcc_parent_data_16[] = { 401 { .index = DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC }, 402 { .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK }, 403 }; 404 405 static const struct clk_parent_data gcc_parent_data_17[] = { 406 { .index = DT_QUSB4PHY_0_GCC_USB4_RX0_CLK }, 407 { .index = DT_BI_TCXO }, 408 }; 409 410 static const struct clk_parent_data gcc_parent_data_18[] = { 411 { .index = DT_QUSB4PHY_0_GCC_USB4_RX1_CLK }, 412 { .index = DT_BI_TCXO }, 413 }; 414 415 static const struct clk_parent_data gcc_parent_data_19[] = { 416 { .index = DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC }, 417 { .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK }, 418 }; 419 420 static const struct clk_parent_data gcc_parent_data_20[] = { 421 { .index = DT_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC }, 422 { .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 423 }; 424 425 static const struct clk_parent_data gcc_parent_data_21[] = { 426 { .index = DT_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC }, 427 { .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 428 }; 429 430 static const struct clk_parent_data gcc_parent_data_22[] = { 431 { .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK }, 432 { .index = DT_BI_TCXO }, 433 }; 434 435 static const struct clk_parent_data gcc_parent_data_23[] = { 436 { .index = DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC }, 437 { .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK }, 438 }; 439 440 static const struct clk_parent_data gcc_parent_data_24[] = { 441 { .index = DT_QUSB4PHY_1_GCC_USB4_RX0_CLK }, 442 { .index = DT_BI_TCXO }, 443 }; 444 445 static const struct clk_parent_data gcc_parent_data_25[] = { 446 { .index = DT_QUSB4PHY_1_GCC_USB4_RX1_CLK }, 447 { .index = DT_BI_TCXO }, 448 }; 449 450 static const struct clk_parent_data gcc_parent_data_26[] = { 451 { .index = DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC }, 452 { .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK }, 453 }; 454 455 static const struct clk_parent_data gcc_parent_data_27[] = { 456 { .index = DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC }, 457 { .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 458 }; 459 460 static const struct clk_parent_data gcc_parent_data_28[] = { 461 { .index = DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC }, 462 { .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 463 }; 464 465 static const struct clk_parent_data gcc_parent_data_29[] = { 466 { .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK }, 467 { .index = DT_BI_TCXO }, 468 }; 469 470 static const struct clk_parent_data gcc_parent_data_30[] = { 471 { .index = DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC }, 472 { .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK }, 473 }; 474 475 static const struct clk_parent_data gcc_parent_data_31[] = { 476 { .index = DT_QUSB4PHY_2_GCC_USB4_RX0_CLK }, 477 { .index = DT_BI_TCXO }, 478 }; 479 480 static const struct clk_parent_data gcc_parent_data_32[] = { 481 { .index = DT_QUSB4PHY_2_GCC_USB4_RX1_CLK }, 482 { .index = DT_BI_TCXO }, 483 }; 484 485 static const struct clk_parent_data gcc_parent_data_33[] = { 486 { .index = DT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC }, 487 { .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK }, 488 }; 489 490 static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_0_clk_src = { 491 .reg = 0x77064, 492 .clkr = { 493 .hw.init = &(const struct clk_init_data) { 494 .name = "gcc_ufs_phy_rx_symbol_0_clk_src", 495 .parent_data = &(const struct clk_parent_data) { 496 .index = DT_UFS_PHY_RX_SYMBOL_0_CLK, 497 }, 498 .num_parents = 1, 499 .ops = &clk_regmap_phy_mux_ops, 500 }, 501 }, 502 }; 503 504 static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_1_clk_src = { 505 .reg = 0x770e0, 506 .clkr = { 507 .hw.init = &(const struct clk_init_data) { 508 .name = "gcc_ufs_phy_rx_symbol_1_clk_src", 509 .parent_data = &(const struct clk_parent_data) { 510 .index = DT_UFS_PHY_RX_SYMBOL_1_CLK, 511 }, 512 .num_parents = 1, 513 .ops = &clk_regmap_phy_mux_ops, 514 }, 515 }, 516 }; 517 518 static struct clk_regmap_phy_mux gcc_ufs_phy_tx_symbol_0_clk_src = { 519 .reg = 0x77054, 520 .clkr = { 521 .hw.init = &(const struct clk_init_data) { 522 .name = "gcc_ufs_phy_tx_symbol_0_clk_src", 523 .parent_data = &(const struct clk_parent_data) { 524 .index = DT_UFS_PHY_TX_SYMBOL_0_CLK, 525 }, 526 .num_parents = 1, 527 .ops = &clk_regmap_phy_mux_ops, 528 }, 529 }, 530 }; 531 532 static struct clk_regmap_phy_mux gcc_usb4_0_phy_dp0_clk_src = { 533 .reg = 0x9f06c, 534 .clkr = { 535 .hw.init = &(const struct clk_init_data) { 536 .name = "gcc_usb4_0_phy_dp0_clk_src", 537 .parent_data = gcc_parent_data_13, 538 .ops = &clk_regmap_phy_mux_ops, 539 }, 540 }, 541 }; 542 543 static struct clk_regmap_phy_mux gcc_usb4_0_phy_dp1_clk_src = { 544 .reg = 0x9f114, 545 .clkr = { 546 .hw.init = &(const struct clk_init_data) { 547 .name = "gcc_usb4_0_phy_dp1_clk_src", 548 .parent_data = gcc_parent_data_14, 549 .ops = &clk_regmap_phy_mux_ops, 550 }, 551 }, 552 }; 553 554 static struct clk_regmap_phy_mux gcc_usb4_0_phy_p2rr2p_pipe_clk_src = { 555 .reg = 0x9f0d4, 556 .clkr = { 557 .hw.init = &(const struct clk_init_data) { 558 .name = "gcc_usb4_0_phy_p2rr2p_pipe_clk_src", 559 .parent_data = gcc_parent_data_15, 560 .ops = &clk_regmap_phy_mux_ops, 561 }, 562 }, 563 }; 564 565 static struct clk_regmap_phy_mux gcc_usb4_0_phy_pcie_pipe_mux_clk_src = { 566 .reg = 0x9f104, 567 .clkr = { 568 .hw.init = &(const struct clk_init_data) { 569 .name = "gcc_usb4_0_phy_pcie_pipe_mux_clk_src", 570 .parent_data = gcc_parent_data_16, 571 .ops = &clk_regmap_phy_mux_ops, 572 }, 573 }, 574 }; 575 576 static struct clk_regmap_phy_mux gcc_usb4_0_phy_rx0_clk_src = { 577 .reg = 0x9f0ac, 578 .clkr = { 579 .hw.init = &(const struct clk_init_data) { 580 .name = "gcc_usb4_0_phy_rx0_clk_src", 581 .parent_data = gcc_parent_data_17, 582 .ops = &clk_regmap_phy_mux_ops, 583 }, 584 }, 585 }; 586 587 static struct clk_regmap_phy_mux gcc_usb4_0_phy_rx1_clk_src = { 588 .reg = 0x9f0bc, 589 .clkr = { 590 .hw.init = &(const struct clk_init_data) { 591 .name = "gcc_usb4_0_phy_rx1_clk_src", 592 .parent_data = gcc_parent_data_18, 593 .ops = &clk_regmap_phy_mux_ops, 594 }, 595 }, 596 }; 597 598 static struct clk_regmap_phy_mux gcc_usb4_0_phy_sys_clk_src = { 599 .reg = 0x9f0e4, 600 .clkr = { 601 .hw.init = &(const struct clk_init_data) { 602 .name = "gcc_usb4_0_phy_sys_clk_src", 603 .parent_data = gcc_parent_data_19, 604 .ops = &clk_regmap_phy_mux_ops, 605 }, 606 }, 607 }; 608 609 static struct clk_regmap_phy_mux gcc_usb4_1_phy_dp0_clk_src = { 610 .reg = 0x2b06c, 611 .clkr = { 612 .hw.init = &(const struct clk_init_data) { 613 .name = "gcc_usb4_1_phy_dp0_clk_src", 614 .parent_data = gcc_parent_data_20, 615 .ops = &clk_regmap_phy_mux_ops, 616 }, 617 }, 618 }; 619 620 static struct clk_regmap_phy_mux gcc_usb4_1_phy_dp1_clk_src = { 621 .reg = 0x2b114, 622 .clkr = { 623 .hw.init = &(const struct clk_init_data) { 624 .name = "gcc_usb4_1_phy_dp1_clk_src", 625 .parent_data = gcc_parent_data_21, 626 .ops = &clk_regmap_phy_mux_ops, 627 }, 628 }, 629 }; 630 631 static struct clk_regmap_phy_mux gcc_usb4_1_phy_p2rr2p_pipe_clk_src = { 632 .reg = 0x2b0d4, 633 .clkr = { 634 .hw.init = &(const struct clk_init_data) { 635 .name = "gcc_usb4_1_phy_p2rr2p_pipe_clk_src", 636 .parent_data = gcc_parent_data_22, 637 .ops = &clk_regmap_phy_mux_ops, 638 }, 639 }, 640 }; 641 642 static struct clk_regmap_phy_mux gcc_usb4_1_phy_pcie_pipe_mux_clk_src = { 643 .reg = 0x2b104, 644 .clkr = { 645 .hw.init = &(const struct clk_init_data) { 646 .name = "gcc_usb4_1_phy_pcie_pipe_mux_clk_src", 647 .parent_data = gcc_parent_data_23, 648 .ops = &clk_regmap_phy_mux_ops, 649 }, 650 }, 651 }; 652 653 static struct clk_regmap_phy_mux gcc_usb4_1_phy_rx0_clk_src = { 654 .reg = 0x2b0ac, 655 .clkr = { 656 .hw.init = &(const struct clk_init_data) { 657 .name = "gcc_usb4_1_phy_rx0_clk_src", 658 .parent_data = gcc_parent_data_24, 659 .ops = &clk_regmap_phy_mux_ops, 660 }, 661 }, 662 }; 663 664 static struct clk_regmap_phy_mux gcc_usb4_1_phy_rx1_clk_src = { 665 .reg = 0x2b0bc, 666 .clkr = { 667 .hw.init = &(const struct clk_init_data) { 668 .name = "gcc_usb4_1_phy_rx1_clk_src", 669 .parent_data = gcc_parent_data_25, 670 .ops = &clk_regmap_phy_mux_ops, 671 }, 672 }, 673 }; 674 675 static struct clk_regmap_phy_mux gcc_usb4_1_phy_sys_clk_src = { 676 .reg = 0x2b0e4, 677 .clkr = { 678 .hw.init = &(const struct clk_init_data) { 679 .name = "gcc_usb4_1_phy_sys_clk_src", 680 .parent_data = gcc_parent_data_26, 681 .ops = &clk_regmap_phy_mux_ops, 682 }, 683 }, 684 }; 685 686 static struct clk_regmap_phy_mux gcc_usb4_2_phy_dp0_clk_src = { 687 .reg = 0x1106c, 688 .clkr = { 689 .hw.init = &(const struct clk_init_data) { 690 .name = "gcc_usb4_2_phy_dp0_clk_src", 691 .parent_data = gcc_parent_data_27, 692 .ops = &clk_regmap_phy_mux_ops, 693 }, 694 }, 695 }; 696 697 static struct clk_regmap_phy_mux gcc_usb4_2_phy_dp1_clk_src = { 698 .reg = 0x11114, 699 .clkr = { 700 .hw.init = &(const struct clk_init_data) { 701 .name = "gcc_usb4_2_phy_dp1_clk_src", 702 .parent_data = gcc_parent_data_28, 703 .ops = &clk_regmap_phy_mux_ops, 704 }, 705 }, 706 }; 707 708 static struct clk_regmap_phy_mux gcc_usb4_2_phy_p2rr2p_pipe_clk_src = { 709 .reg = 0x110d4, 710 .clkr = { 711 .hw.init = &(const struct clk_init_data) { 712 .name = "gcc_usb4_2_phy_p2rr2p_pipe_clk_src", 713 .parent_data = gcc_parent_data_29, 714 .ops = &clk_regmap_phy_mux_ops, 715 }, 716 }, 717 }; 718 719 static struct clk_regmap_phy_mux gcc_usb4_2_phy_pcie_pipe_mux_clk_src = { 720 .reg = 0x11104, 721 .clkr = { 722 .hw.init = &(const struct clk_init_data) { 723 .name = "gcc_usb4_2_phy_pcie_pipe_mux_clk_src", 724 .parent_data = gcc_parent_data_30, 725 .ops = &clk_regmap_phy_mux_ops, 726 }, 727 }, 728 }; 729 730 static struct clk_regmap_phy_mux gcc_usb4_2_phy_rx0_clk_src = { 731 .reg = 0x110ac, 732 .clkr = { 733 .hw.init = &(const struct clk_init_data) { 734 .name = "gcc_usb4_2_phy_rx0_clk_src", 735 .parent_data = gcc_parent_data_31, 736 .ops = &clk_regmap_phy_mux_ops, 737 }, 738 }, 739 }; 740 741 static struct clk_regmap_phy_mux gcc_usb4_2_phy_rx1_clk_src = { 742 .reg = 0x110bc, 743 .clkr = { 744 .hw.init = &(const struct clk_init_data) { 745 .name = "gcc_usb4_2_phy_rx1_clk_src", 746 .parent_data = gcc_parent_data_32, 747 .ops = &clk_regmap_phy_mux_ops, 748 }, 749 }, 750 }; 751 752 static struct clk_regmap_phy_mux gcc_usb4_2_phy_sys_clk_src = { 753 .reg = 0x110e4, 754 .clkr = { 755 .hw.init = &(const struct clk_init_data) { 756 .name = "gcc_usb4_2_phy_sys_clk_src", 757 .parent_data = gcc_parent_data_33, 758 .ops = &clk_regmap_phy_mux_ops, 759 }, 760 }, 761 }; 762 763 static struct clk_rcg2 gcc_gp1_clk_src = { 764 .cmd_rcgr = 0x64004, 765 .mnd_width = 16, 766 .hid_width = 5, 767 .parent_map = gcc_parent_map_2, 768 .freq_tbl = ftbl_gcc_gp1_clk_src, 769 .clkr.hw.init = &(const struct clk_init_data) { 770 .name = "gcc_gp1_clk_src", 771 .parent_data = gcc_parent_data_2, 772 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 773 .flags = CLK_SET_RATE_PARENT, 774 .ops = &clk_rcg2_shared_ops, 775 }, 776 }; 777 778 static struct clk_rcg2 gcc_gp2_clk_src = { 779 .cmd_rcgr = 0x65004, 780 .mnd_width = 16, 781 .hid_width = 5, 782 .parent_map = gcc_parent_map_2, 783 .freq_tbl = ftbl_gcc_gp1_clk_src, 784 .clkr.hw.init = &(const struct clk_init_data) { 785 .name = "gcc_gp2_clk_src", 786 .parent_data = gcc_parent_data_2, 787 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 788 .flags = CLK_SET_RATE_PARENT, 789 .ops = &clk_rcg2_shared_ops, 790 }, 791 }; 792 793 static struct clk_rcg2 gcc_gp3_clk_src = { 794 .cmd_rcgr = 0x66004, 795 .mnd_width = 16, 796 .hid_width = 5, 797 .parent_map = gcc_parent_map_2, 798 .freq_tbl = ftbl_gcc_gp1_clk_src, 799 .clkr.hw.init = &(const struct clk_init_data) { 800 .name = "gcc_gp3_clk_src", 801 .parent_data = gcc_parent_data_2, 802 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 803 .flags = CLK_SET_RATE_PARENT, 804 .ops = &clk_rcg2_shared_ops, 805 }, 806 }; 807 808 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 809 F(19200000, P_BI_TCXO, 1, 0, 0), 810 { } 811 }; 812 813 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 814 .cmd_rcgr = 0xa0180, 815 .mnd_width = 16, 816 .hid_width = 5, 817 .parent_map = gcc_parent_map_1, 818 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 819 .clkr.hw.init = &(const struct clk_init_data) { 820 .name = "gcc_pcie_0_aux_clk_src", 821 .parent_data = gcc_parent_data_1, 822 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 823 .flags = CLK_SET_RATE_PARENT, 824 .ops = &clk_rcg2_shared_ops, 825 }, 826 }; 827 828 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 829 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 830 { } 831 }; 832 833 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 834 .cmd_rcgr = 0xa0054, 835 .mnd_width = 0, 836 .hid_width = 5, 837 .parent_map = gcc_parent_map_0, 838 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 839 .clkr.hw.init = &(const struct clk_init_data) { 840 .name = "gcc_pcie_0_phy_rchng_clk_src", 841 .parent_data = gcc_parent_data_0, 842 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 843 .flags = CLK_SET_RATE_PARENT, 844 .ops = &clk_rcg2_shared_ops, 845 }, 846 }; 847 848 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 849 .cmd_rcgr = 0x2c180, 850 .mnd_width = 16, 851 .hid_width = 5, 852 .parent_map = gcc_parent_map_1, 853 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 854 .clkr.hw.init = &(const struct clk_init_data) { 855 .name = "gcc_pcie_1_aux_clk_src", 856 .parent_data = gcc_parent_data_1, 857 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 858 .flags = CLK_SET_RATE_PARENT, 859 .ops = &clk_rcg2_shared_ops, 860 }, 861 }; 862 863 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { 864 .cmd_rcgr = 0x2c054, 865 .mnd_width = 0, 866 .hid_width = 5, 867 .parent_map = gcc_parent_map_0, 868 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 869 .clkr.hw.init = &(const struct clk_init_data) { 870 .name = "gcc_pcie_1_phy_rchng_clk_src", 871 .parent_data = gcc_parent_data_0, 872 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 873 .flags = CLK_SET_RATE_PARENT, 874 .ops = &clk_rcg2_shared_ops, 875 }, 876 }; 877 878 static struct clk_rcg2 gcc_pcie_2_aux_clk_src = { 879 .cmd_rcgr = 0x13180, 880 .mnd_width = 16, 881 .hid_width = 5, 882 .parent_map = gcc_parent_map_1, 883 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 884 .clkr.hw.init = &(const struct clk_init_data) { 885 .name = "gcc_pcie_2_aux_clk_src", 886 .parent_data = gcc_parent_data_1, 887 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 888 .flags = CLK_SET_RATE_PARENT, 889 .ops = &clk_rcg2_shared_ops, 890 }, 891 }; 892 893 static struct clk_rcg2 gcc_pcie_2_phy_rchng_clk_src = { 894 .cmd_rcgr = 0x13054, 895 .mnd_width = 0, 896 .hid_width = 5, 897 .parent_map = gcc_parent_map_0, 898 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 899 .clkr.hw.init = &(const struct clk_init_data) { 900 .name = "gcc_pcie_2_phy_rchng_clk_src", 901 .parent_data = gcc_parent_data_0, 902 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 903 .flags = CLK_SET_RATE_PARENT, 904 .ops = &clk_rcg2_shared_ops, 905 }, 906 }; 907 908 static struct clk_rcg2 gcc_pcie_3_aux_clk_src = { 909 .cmd_rcgr = 0x5808c, 910 .mnd_width = 16, 911 .hid_width = 5, 912 .parent_map = gcc_parent_map_1, 913 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 914 .clkr.hw.init = &(const struct clk_init_data) { 915 .name = "gcc_pcie_3_aux_clk_src", 916 .parent_data = gcc_parent_data_1, 917 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 918 .flags = CLK_SET_RATE_PARENT, 919 .ops = &clk_rcg2_shared_ops, 920 }, 921 }; 922 923 static struct clk_rcg2 gcc_pcie_3_phy_rchng_clk_src = { 924 .cmd_rcgr = 0x58070, 925 .mnd_width = 0, 926 .hid_width = 5, 927 .parent_map = gcc_parent_map_0, 928 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 929 .clkr.hw.init = &(const struct clk_init_data) { 930 .name = "gcc_pcie_3_phy_rchng_clk_src", 931 .parent_data = gcc_parent_data_0, 932 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 933 .flags = CLK_SET_RATE_PARENT, 934 .ops = &clk_rcg2_shared_ops, 935 }, 936 }; 937 938 static struct clk_rcg2 gcc_pcie_4_aux_clk_src = { 939 .cmd_rcgr = 0x6b080, 940 .mnd_width = 16, 941 .hid_width = 5, 942 .parent_map = gcc_parent_map_1, 943 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 944 .clkr.hw.init = &(const struct clk_init_data) { 945 .name = "gcc_pcie_4_aux_clk_src", 946 .parent_data = gcc_parent_data_1, 947 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 948 .flags = CLK_SET_RATE_PARENT, 949 .ops = &clk_rcg2_shared_ops, 950 }, 951 }; 952 953 static struct clk_rcg2 gcc_pcie_4_phy_rchng_clk_src = { 954 .cmd_rcgr = 0x6b064, 955 .mnd_width = 0, 956 .hid_width = 5, 957 .parent_map = gcc_parent_map_0, 958 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 959 .clkr.hw.init = &(const struct clk_init_data) { 960 .name = "gcc_pcie_4_phy_rchng_clk_src", 961 .parent_data = gcc_parent_data_0, 962 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 963 .flags = CLK_SET_RATE_PARENT, 964 .ops = &clk_rcg2_shared_ops, 965 }, 966 }; 967 968 static struct clk_rcg2 gcc_pcie_5_aux_clk_src = { 969 .cmd_rcgr = 0x2f080, 970 .mnd_width = 16, 971 .hid_width = 5, 972 .parent_map = gcc_parent_map_1, 973 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 974 .clkr.hw.init = &(const struct clk_init_data) { 975 .name = "gcc_pcie_5_aux_clk_src", 976 .parent_data = gcc_parent_data_1, 977 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 978 .flags = CLK_SET_RATE_PARENT, 979 .ops = &clk_rcg2_shared_ops, 980 }, 981 }; 982 983 static struct clk_rcg2 gcc_pcie_5_phy_rchng_clk_src = { 984 .cmd_rcgr = 0x2f064, 985 .mnd_width = 0, 986 .hid_width = 5, 987 .parent_map = gcc_parent_map_0, 988 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 989 .clkr.hw.init = &(const struct clk_init_data) { 990 .name = "gcc_pcie_5_phy_rchng_clk_src", 991 .parent_data = gcc_parent_data_0, 992 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 993 .flags = CLK_SET_RATE_PARENT, 994 .ops = &clk_rcg2_shared_ops, 995 }, 996 }; 997 998 static struct clk_rcg2 gcc_pcie_6a_aux_clk_src = { 999 .cmd_rcgr = 0x3108c, 1000 .mnd_width = 16, 1001 .hid_width = 5, 1002 .parent_map = gcc_parent_map_1, 1003 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1004 .clkr.hw.init = &(const struct clk_init_data) { 1005 .name = "gcc_pcie_6a_aux_clk_src", 1006 .parent_data = gcc_parent_data_1, 1007 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1008 .flags = CLK_SET_RATE_PARENT, 1009 .ops = &clk_rcg2_shared_ops, 1010 }, 1011 }; 1012 1013 static struct clk_rcg2 gcc_pcie_6a_phy_rchng_clk_src = { 1014 .cmd_rcgr = 0x31070, 1015 .mnd_width = 0, 1016 .hid_width = 5, 1017 .parent_map = gcc_parent_map_0, 1018 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1019 .clkr.hw.init = &(const struct clk_init_data) { 1020 .name = "gcc_pcie_6a_phy_rchng_clk_src", 1021 .parent_data = gcc_parent_data_0, 1022 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1023 .flags = CLK_SET_RATE_PARENT, 1024 .ops = &clk_rcg2_shared_ops, 1025 }, 1026 }; 1027 1028 static struct clk_rcg2 gcc_pcie_6b_aux_clk_src = { 1029 .cmd_rcgr = 0x8d08c, 1030 .mnd_width = 16, 1031 .hid_width = 5, 1032 .parent_map = gcc_parent_map_1, 1033 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1034 .clkr.hw.init = &(const struct clk_init_data) { 1035 .name = "gcc_pcie_6b_aux_clk_src", 1036 .parent_data = gcc_parent_data_1, 1037 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1038 .flags = CLK_SET_RATE_PARENT, 1039 .ops = &clk_rcg2_shared_ops, 1040 }, 1041 }; 1042 1043 static struct clk_rcg2 gcc_pcie_6b_phy_rchng_clk_src = { 1044 .cmd_rcgr = 0x8d070, 1045 .mnd_width = 0, 1046 .hid_width = 5, 1047 .parent_map = gcc_parent_map_0, 1048 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1049 .clkr.hw.init = &(const struct clk_init_data) { 1050 .name = "gcc_pcie_6b_phy_rchng_clk_src", 1051 .parent_data = gcc_parent_data_0, 1052 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1053 .flags = CLK_SET_RATE_PARENT, 1054 .ops = &clk_rcg2_shared_ops, 1055 }, 1056 }; 1057 1058 static struct clk_rcg2 gcc_pcie_rscc_xo_clk_src = { 1059 .cmd_rcgr = 0xa400c, 1060 .mnd_width = 0, 1061 .hid_width = 5, 1062 .parent_map = gcc_parent_map_3, 1063 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1064 .clkr.hw.init = &(const struct clk_init_data) { 1065 .name = "gcc_pcie_rscc_xo_clk_src", 1066 .parent_data = gcc_parent_data_3, 1067 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1068 .flags = CLK_SET_RATE_PARENT, 1069 .ops = &clk_rcg2_shared_ops, 1070 }, 1071 }; 1072 1073 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 1074 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 1075 { } 1076 }; 1077 1078 static struct clk_rcg2 gcc_pdm2_clk_src = { 1079 .cmd_rcgr = 0x33010, 1080 .mnd_width = 0, 1081 .hid_width = 5, 1082 .parent_map = gcc_parent_map_0, 1083 .freq_tbl = ftbl_gcc_pdm2_clk_src, 1084 .clkr.hw.init = &(const struct clk_init_data) { 1085 .name = "gcc_pdm2_clk_src", 1086 .parent_data = gcc_parent_data_0, 1087 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1088 .flags = CLK_SET_RATE_PARENT, 1089 .ops = &clk_rcg2_shared_ops, 1090 }, 1091 }; 1092 1093 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 1094 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 1095 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 1096 F(19200000, P_BI_TCXO, 1, 0, 0), 1097 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 1098 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 1099 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 1100 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 1101 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1102 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 1103 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 1104 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 1105 { } 1106 }; 1107 1108 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 1109 .name = "gcc_qupv3_wrap0_s0_clk_src", 1110 .parent_data = gcc_parent_data_0, 1111 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1112 .flags = CLK_SET_RATE_PARENT, 1113 .ops = &clk_rcg2_ops, 1114 }; 1115 1116 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 1117 .cmd_rcgr = 0x42010, 1118 .mnd_width = 16, 1119 .hid_width = 5, 1120 .parent_map = gcc_parent_map_0, 1121 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1122 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 1123 }; 1124 1125 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 1126 .name = "gcc_qupv3_wrap0_s1_clk_src", 1127 .parent_data = gcc_parent_data_0, 1128 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1129 .flags = CLK_SET_RATE_PARENT, 1130 .ops = &clk_rcg2_ops, 1131 }; 1132 1133 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 1134 .cmd_rcgr = 0x42148, 1135 .mnd_width = 16, 1136 .hid_width = 5, 1137 .parent_map = gcc_parent_map_0, 1138 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1139 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 1140 }; 1141 1142 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = { 1143 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 1144 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 1145 F(19200000, P_BI_TCXO, 1, 0, 0), 1146 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 1147 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 1148 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 1149 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 1150 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 1151 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 1152 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 1153 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1154 { } 1155 }; 1156 1157 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 1158 .name = "gcc_qupv3_wrap0_s2_clk_src", 1159 .parent_data = gcc_parent_data_0, 1160 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1161 .flags = CLK_SET_RATE_PARENT, 1162 .ops = &clk_rcg2_ops, 1163 }; 1164 1165 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 1166 .cmd_rcgr = 0x42288, 1167 .mnd_width = 16, 1168 .hid_width = 5, 1169 .parent_map = gcc_parent_map_0, 1170 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1171 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 1172 }; 1173 1174 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 1175 .name = "gcc_qupv3_wrap0_s3_clk_src", 1176 .parent_data = gcc_parent_data_0, 1177 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1178 .flags = CLK_SET_RATE_PARENT, 1179 .ops = &clk_rcg2_ops, 1180 }; 1181 1182 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 1183 .cmd_rcgr = 0x423c8, 1184 .mnd_width = 16, 1185 .hid_width = 5, 1186 .parent_map = gcc_parent_map_0, 1187 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1188 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 1189 }; 1190 1191 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s4_clk_src[] = { 1192 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 1193 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 1194 F(19200000, P_BI_TCXO, 1, 0, 0), 1195 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 1196 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 1197 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 1198 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 1199 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1200 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 1201 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 1202 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 1203 { } 1204 }; 1205 1206 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 1207 .name = "gcc_qupv3_wrap0_s4_clk_src", 1208 .parent_data = gcc_parent_data_0, 1209 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1210 .flags = CLK_SET_RATE_PARENT, 1211 .ops = &clk_rcg2_ops, 1212 }; 1213 1214 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 1215 .cmd_rcgr = 0x42500, 1216 .mnd_width = 16, 1217 .hid_width = 5, 1218 .parent_map = gcc_parent_map_0, 1219 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 1220 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 1221 }; 1222 1223 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 1224 .name = "gcc_qupv3_wrap0_s5_clk_src", 1225 .parent_data = gcc_parent_data_0, 1226 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1227 .flags = CLK_SET_RATE_PARENT, 1228 .ops = &clk_rcg2_ops, 1229 }; 1230 1231 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 1232 .cmd_rcgr = 0x42638, 1233 .mnd_width = 16, 1234 .hid_width = 5, 1235 .parent_map = gcc_parent_map_0, 1236 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 1237 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 1238 }; 1239 1240 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 1241 .name = "gcc_qupv3_wrap0_s6_clk_src", 1242 .parent_data = gcc_parent_data_0, 1243 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1244 .flags = CLK_SET_RATE_PARENT, 1245 .ops = &clk_rcg2_ops, 1246 }; 1247 1248 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 1249 .cmd_rcgr = 0x42770, 1250 .mnd_width = 16, 1251 .hid_width = 5, 1252 .parent_map = gcc_parent_map_0, 1253 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 1254 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 1255 }; 1256 1257 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 1258 .name = "gcc_qupv3_wrap0_s7_clk_src", 1259 .parent_data = gcc_parent_data_0, 1260 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1261 .flags = CLK_SET_RATE_PARENT, 1262 .ops = &clk_rcg2_ops, 1263 }; 1264 1265 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 1266 .cmd_rcgr = 0x428a8, 1267 .mnd_width = 16, 1268 .hid_width = 5, 1269 .parent_map = gcc_parent_map_0, 1270 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 1271 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 1272 }; 1273 1274 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 1275 .name = "gcc_qupv3_wrap1_s0_clk_src", 1276 .parent_data = gcc_parent_data_0, 1277 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1278 .flags = CLK_SET_RATE_PARENT, 1279 .ops = &clk_rcg2_ops, 1280 }; 1281 1282 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 1283 .cmd_rcgr = 0x18010, 1284 .mnd_width = 16, 1285 .hid_width = 5, 1286 .parent_map = gcc_parent_map_0, 1287 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1288 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 1289 }; 1290 1291 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 1292 .name = "gcc_qupv3_wrap1_s1_clk_src", 1293 .parent_data = gcc_parent_data_0, 1294 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1295 .flags = CLK_SET_RATE_PARENT, 1296 .ops = &clk_rcg2_ops, 1297 }; 1298 1299 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 1300 .cmd_rcgr = 0x18148, 1301 .mnd_width = 16, 1302 .hid_width = 5, 1303 .parent_map = gcc_parent_map_0, 1304 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1305 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 1306 }; 1307 1308 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 1309 .name = "gcc_qupv3_wrap1_s2_clk_src", 1310 .parent_data = gcc_parent_data_0, 1311 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1312 .flags = CLK_SET_RATE_PARENT, 1313 .ops = &clk_rcg2_ops, 1314 }; 1315 1316 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 1317 .cmd_rcgr = 0x18288, 1318 .mnd_width = 16, 1319 .hid_width = 5, 1320 .parent_map = gcc_parent_map_0, 1321 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1322 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 1323 }; 1324 1325 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 1326 .name = "gcc_qupv3_wrap1_s3_clk_src", 1327 .parent_data = gcc_parent_data_0, 1328 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1329 .flags = CLK_SET_RATE_PARENT, 1330 .ops = &clk_rcg2_ops, 1331 }; 1332 1333 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 1334 .cmd_rcgr = 0x183c8, 1335 .mnd_width = 16, 1336 .hid_width = 5, 1337 .parent_map = gcc_parent_map_0, 1338 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1339 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 1340 }; 1341 1342 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 1343 .name = "gcc_qupv3_wrap1_s4_clk_src", 1344 .parent_data = gcc_parent_data_0, 1345 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1346 .flags = CLK_SET_RATE_PARENT, 1347 .ops = &clk_rcg2_ops, 1348 }; 1349 1350 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 1351 .cmd_rcgr = 0x18500, 1352 .mnd_width = 16, 1353 .hid_width = 5, 1354 .parent_map = gcc_parent_map_0, 1355 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 1356 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 1357 }; 1358 1359 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 1360 .name = "gcc_qupv3_wrap1_s5_clk_src", 1361 .parent_data = gcc_parent_data_0, 1362 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1363 .flags = CLK_SET_RATE_PARENT, 1364 .ops = &clk_rcg2_ops, 1365 }; 1366 1367 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 1368 .cmd_rcgr = 0x18638, 1369 .mnd_width = 16, 1370 .hid_width = 5, 1371 .parent_map = gcc_parent_map_0, 1372 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 1373 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 1374 }; 1375 1376 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 1377 .name = "gcc_qupv3_wrap1_s6_clk_src", 1378 .parent_data = gcc_parent_data_0, 1379 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1380 .flags = CLK_SET_RATE_PARENT, 1381 .ops = &clk_rcg2_ops, 1382 }; 1383 1384 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 1385 .cmd_rcgr = 0x18770, 1386 .mnd_width = 16, 1387 .hid_width = 5, 1388 .parent_map = gcc_parent_map_0, 1389 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 1390 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 1391 }; 1392 1393 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 1394 .name = "gcc_qupv3_wrap1_s7_clk_src", 1395 .parent_data = gcc_parent_data_0, 1396 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1397 .flags = CLK_SET_RATE_PARENT, 1398 .ops = &clk_rcg2_ops, 1399 }; 1400 1401 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 1402 .cmd_rcgr = 0x188a8, 1403 .mnd_width = 16, 1404 .hid_width = 5, 1405 .parent_map = gcc_parent_map_0, 1406 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 1407 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 1408 }; 1409 1410 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 1411 .name = "gcc_qupv3_wrap2_s0_clk_src", 1412 .parent_data = gcc_parent_data_0, 1413 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1414 .flags = CLK_SET_RATE_PARENT, 1415 .ops = &clk_rcg2_ops, 1416 }; 1417 1418 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 1419 .cmd_rcgr = 0x1e010, 1420 .mnd_width = 16, 1421 .hid_width = 5, 1422 .parent_map = gcc_parent_map_0, 1423 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1424 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 1425 }; 1426 1427 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 1428 .name = "gcc_qupv3_wrap2_s1_clk_src", 1429 .parent_data = gcc_parent_data_0, 1430 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1431 .flags = CLK_SET_RATE_PARENT, 1432 .ops = &clk_rcg2_ops, 1433 }; 1434 1435 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 1436 .cmd_rcgr = 0x1e148, 1437 .mnd_width = 16, 1438 .hid_width = 5, 1439 .parent_map = gcc_parent_map_0, 1440 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1441 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 1442 }; 1443 1444 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 1445 .name = "gcc_qupv3_wrap2_s2_clk_src", 1446 .parent_data = gcc_parent_data_0, 1447 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1448 .flags = CLK_SET_RATE_PARENT, 1449 .ops = &clk_rcg2_ops, 1450 }; 1451 1452 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 1453 .cmd_rcgr = 0x1e288, 1454 .mnd_width = 16, 1455 .hid_width = 5, 1456 .parent_map = gcc_parent_map_0, 1457 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1458 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, 1459 }; 1460 1461 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 1462 .name = "gcc_qupv3_wrap2_s3_clk_src", 1463 .parent_data = gcc_parent_data_0, 1464 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1465 .flags = CLK_SET_RATE_PARENT, 1466 .ops = &clk_rcg2_ops, 1467 }; 1468 1469 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 1470 .cmd_rcgr = 0x1e3c8, 1471 .mnd_width = 16, 1472 .hid_width = 5, 1473 .parent_map = gcc_parent_map_0, 1474 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1475 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, 1476 }; 1477 1478 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 1479 .name = "gcc_qupv3_wrap2_s4_clk_src", 1480 .parent_data = gcc_parent_data_0, 1481 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1482 .flags = CLK_SET_RATE_PARENT, 1483 .ops = &clk_rcg2_ops, 1484 }; 1485 1486 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 1487 .cmd_rcgr = 0x1e500, 1488 .mnd_width = 16, 1489 .hid_width = 5, 1490 .parent_map = gcc_parent_map_0, 1491 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 1492 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 1493 }; 1494 1495 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { 1496 .name = "gcc_qupv3_wrap2_s5_clk_src", 1497 .parent_data = gcc_parent_data_0, 1498 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1499 .flags = CLK_SET_RATE_PARENT, 1500 .ops = &clk_rcg2_ops, 1501 }; 1502 1503 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { 1504 .cmd_rcgr = 0x1e638, 1505 .mnd_width = 16, 1506 .hid_width = 5, 1507 .parent_map = gcc_parent_map_0, 1508 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 1509 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, 1510 }; 1511 1512 static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = { 1513 .name = "gcc_qupv3_wrap2_s6_clk_src", 1514 .parent_data = gcc_parent_data_8, 1515 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 1516 .flags = CLK_SET_RATE_PARENT, 1517 .ops = &clk_rcg2_ops, 1518 }; 1519 1520 static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { 1521 .cmd_rcgr = 0x1e770, 1522 .mnd_width = 16, 1523 .hid_width = 5, 1524 .parent_map = gcc_parent_map_8, 1525 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 1526 .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init, 1527 }; 1528 1529 static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = { 1530 .name = "gcc_qupv3_wrap2_s7_clk_src", 1531 .parent_data = gcc_parent_data_0, 1532 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1533 .flags = CLK_SET_RATE_PARENT, 1534 .ops = &clk_rcg2_ops, 1535 }; 1536 1537 static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = { 1538 .cmd_rcgr = 0x1e8a8, 1539 .mnd_width = 16, 1540 .hid_width = 5, 1541 .parent_map = gcc_parent_map_0, 1542 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 1543 .clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init, 1544 }; 1545 1546 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1547 F(400000, P_BI_TCXO, 12, 1, 4), 1548 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1549 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 1550 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1551 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), 1552 { } 1553 }; 1554 1555 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1556 .cmd_rcgr = 0x14018, 1557 .mnd_width = 8, 1558 .hid_width = 5, 1559 .parent_map = gcc_parent_map_9, 1560 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1561 .clkr.hw.init = &(const struct clk_init_data) { 1562 .name = "gcc_sdcc2_apps_clk_src", 1563 .parent_data = gcc_parent_data_9, 1564 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 1565 .flags = CLK_SET_RATE_PARENT, 1566 .ops = &clk_rcg2_shared_floor_ops, 1567 }, 1568 }; 1569 1570 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 1571 F(400000, P_BI_TCXO, 12, 1, 4), 1572 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1573 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1574 { } 1575 }; 1576 1577 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 1578 .cmd_rcgr = 0x16018, 1579 .mnd_width = 8, 1580 .hid_width = 5, 1581 .parent_map = gcc_parent_map_0, 1582 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 1583 .clkr.hw.init = &(const struct clk_init_data) { 1584 .name = "gcc_sdcc4_apps_clk_src", 1585 .parent_data = gcc_parent_data_0, 1586 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1587 .flags = CLK_SET_RATE_PARENT, 1588 .ops = &clk_rcg2_shared_floor_ops, 1589 }, 1590 }; 1591 1592 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 1593 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1594 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1595 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 1596 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 1597 { } 1598 }; 1599 1600 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1601 .cmd_rcgr = 0x77030, 1602 .mnd_width = 8, 1603 .hid_width = 5, 1604 .parent_map = gcc_parent_map_0, 1605 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 1606 .clkr.hw.init = &(const struct clk_init_data) { 1607 .name = "gcc_ufs_phy_axi_clk_src", 1608 .parent_data = gcc_parent_data_0, 1609 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1610 .flags = CLK_SET_RATE_PARENT, 1611 .ops = &clk_rcg2_shared_ops, 1612 }, 1613 }; 1614 1615 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1616 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1617 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), 1618 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 1619 { } 1620 }; 1621 1622 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1623 .cmd_rcgr = 0x77080, 1624 .mnd_width = 0, 1625 .hid_width = 5, 1626 .parent_map = gcc_parent_map_7, 1627 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1628 .clkr.hw.init = &(const struct clk_init_data) { 1629 .name = "gcc_ufs_phy_ice_core_clk_src", 1630 .parent_data = gcc_parent_data_7, 1631 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 1632 .flags = CLK_SET_RATE_PARENT, 1633 .ops = &clk_rcg2_shared_ops, 1634 }, 1635 }; 1636 1637 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1638 .cmd_rcgr = 0x770b4, 1639 .mnd_width = 0, 1640 .hid_width = 5, 1641 .parent_map = gcc_parent_map_3, 1642 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1643 .clkr.hw.init = &(const struct clk_init_data) { 1644 .name = "gcc_ufs_phy_phy_aux_clk_src", 1645 .parent_data = gcc_parent_data_3, 1646 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1647 .flags = CLK_SET_RATE_PARENT, 1648 .ops = &clk_rcg2_shared_ops, 1649 }, 1650 }; 1651 1652 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { 1653 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1654 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 1655 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 1656 { } 1657 }; 1658 1659 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1660 .cmd_rcgr = 0x77098, 1661 .mnd_width = 0, 1662 .hid_width = 5, 1663 .parent_map = gcc_parent_map_0, 1664 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, 1665 .clkr.hw.init = &(const struct clk_init_data) { 1666 .name = "gcc_ufs_phy_unipro_core_clk_src", 1667 .parent_data = gcc_parent_data_0, 1668 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1669 .flags = CLK_SET_RATE_PARENT, 1670 .ops = &clk_rcg2_shared_ops, 1671 }, 1672 }; 1673 1674 static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = { 1675 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 1676 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 1677 { } 1678 }; 1679 1680 static struct clk_rcg2 gcc_usb20_master_clk_src = { 1681 .cmd_rcgr = 0x2902c, 1682 .mnd_width = 8, 1683 .hid_width = 5, 1684 .parent_map = gcc_parent_map_0, 1685 .freq_tbl = ftbl_gcc_usb20_master_clk_src, 1686 .clkr.hw.init = &(const struct clk_init_data) { 1687 .name = "gcc_usb20_master_clk_src", 1688 .parent_data = gcc_parent_data_0, 1689 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1690 .flags = CLK_SET_RATE_PARENT, 1691 .ops = &clk_rcg2_shared_ops, 1692 }, 1693 }; 1694 1695 static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = { 1696 .cmd_rcgr = 0x29158, 1697 .mnd_width = 0, 1698 .hid_width = 5, 1699 .parent_map = gcc_parent_map_0, 1700 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1701 .clkr.hw.init = &(const struct clk_init_data) { 1702 .name = "gcc_usb20_mock_utmi_clk_src", 1703 .parent_data = gcc_parent_data_0, 1704 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1705 .flags = CLK_SET_RATE_PARENT, 1706 .ops = &clk_rcg2_shared_ops, 1707 }, 1708 }; 1709 1710 static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = { 1711 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), 1712 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 1713 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1714 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 1715 { } 1716 }; 1717 1718 static struct clk_rcg2 gcc_usb30_mp_master_clk_src = { 1719 .cmd_rcgr = 0x1702c, 1720 .mnd_width = 8, 1721 .hid_width = 5, 1722 .parent_map = gcc_parent_map_0, 1723 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 1724 .clkr.hw.init = &(const struct clk_init_data) { 1725 .name = "gcc_usb30_mp_master_clk_src", 1726 .parent_data = gcc_parent_data_0, 1727 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1728 .flags = CLK_SET_RATE_PARENT, 1729 .ops = &clk_rcg2_shared_ops, 1730 }, 1731 }; 1732 1733 static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = { 1734 .cmd_rcgr = 0x17158, 1735 .mnd_width = 0, 1736 .hid_width = 5, 1737 .parent_map = gcc_parent_map_0, 1738 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1739 .clkr.hw.init = &(const struct clk_init_data) { 1740 .name = "gcc_usb30_mp_mock_utmi_clk_src", 1741 .parent_data = gcc_parent_data_0, 1742 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1743 .flags = CLK_SET_RATE_PARENT, 1744 .ops = &clk_rcg2_shared_ops, 1745 }, 1746 }; 1747 1748 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1749 .cmd_rcgr = 0x3902c, 1750 .mnd_width = 8, 1751 .hid_width = 5, 1752 .parent_map = gcc_parent_map_0, 1753 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 1754 .clkr.hw.init = &(const struct clk_init_data) { 1755 .name = "gcc_usb30_prim_master_clk_src", 1756 .parent_data = gcc_parent_data_0, 1757 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1758 .flags = CLK_SET_RATE_PARENT, 1759 .ops = &clk_rcg2_shared_ops, 1760 }, 1761 }; 1762 1763 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1764 .cmd_rcgr = 0x39044, 1765 .mnd_width = 0, 1766 .hid_width = 5, 1767 .parent_map = gcc_parent_map_0, 1768 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1769 .clkr.hw.init = &(const struct clk_init_data) { 1770 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1771 .parent_data = gcc_parent_data_0, 1772 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1773 .flags = CLK_SET_RATE_PARENT, 1774 .ops = &clk_rcg2_shared_ops, 1775 }, 1776 }; 1777 1778 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { 1779 .cmd_rcgr = 0xa102c, 1780 .mnd_width = 8, 1781 .hid_width = 5, 1782 .parent_map = gcc_parent_map_0, 1783 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 1784 .clkr.hw.init = &(const struct clk_init_data) { 1785 .name = "gcc_usb30_sec_master_clk_src", 1786 .parent_data = gcc_parent_data_0, 1787 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1788 .flags = CLK_SET_RATE_PARENT, 1789 .ops = &clk_rcg2_shared_ops, 1790 }, 1791 }; 1792 1793 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { 1794 .cmd_rcgr = 0xa1044, 1795 .mnd_width = 0, 1796 .hid_width = 5, 1797 .parent_map = gcc_parent_map_0, 1798 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1799 .clkr.hw.init = &(const struct clk_init_data) { 1800 .name = "gcc_usb30_sec_mock_utmi_clk_src", 1801 .parent_data = gcc_parent_data_0, 1802 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1803 .flags = CLK_SET_RATE_PARENT, 1804 .ops = &clk_rcg2_shared_ops, 1805 }, 1806 }; 1807 1808 static struct clk_rcg2 gcc_usb30_tert_master_clk_src = { 1809 .cmd_rcgr = 0xa202c, 1810 .mnd_width = 8, 1811 .hid_width = 5, 1812 .parent_map = gcc_parent_map_0, 1813 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 1814 .clkr.hw.init = &(const struct clk_init_data) { 1815 .name = "gcc_usb30_tert_master_clk_src", 1816 .parent_data = gcc_parent_data_0, 1817 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1818 .flags = CLK_SET_RATE_PARENT, 1819 .ops = &clk_rcg2_shared_ops, 1820 }, 1821 }; 1822 1823 static struct clk_rcg2 gcc_usb30_tert_mock_utmi_clk_src = { 1824 .cmd_rcgr = 0xa2044, 1825 .mnd_width = 0, 1826 .hid_width = 5, 1827 .parent_map = gcc_parent_map_0, 1828 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1829 .clkr.hw.init = &(const struct clk_init_data) { 1830 .name = "gcc_usb30_tert_mock_utmi_clk_src", 1831 .parent_data = gcc_parent_data_0, 1832 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1833 .flags = CLK_SET_RATE_PARENT, 1834 .ops = &clk_rcg2_shared_ops, 1835 }, 1836 }; 1837 1838 static struct clk_rcg2 gcc_usb3_mp_phy_aux_clk_src = { 1839 .cmd_rcgr = 0x172a0, 1840 .mnd_width = 0, 1841 .hid_width = 5, 1842 .parent_map = gcc_parent_map_1, 1843 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1844 .clkr.hw.init = &(const struct clk_init_data) { 1845 .name = "gcc_usb3_mp_phy_aux_clk_src", 1846 .parent_data = gcc_parent_data_1, 1847 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1848 .flags = CLK_SET_RATE_PARENT, 1849 .ops = &clk_rcg2_shared_ops, 1850 }, 1851 }; 1852 1853 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1854 .cmd_rcgr = 0x39074, 1855 .mnd_width = 0, 1856 .hid_width = 5, 1857 .parent_map = gcc_parent_map_1, 1858 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1859 .clkr.hw.init = &(const struct clk_init_data) { 1860 .name = "gcc_usb3_prim_phy_aux_clk_src", 1861 .parent_data = gcc_parent_data_1, 1862 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1863 .flags = CLK_SET_RATE_PARENT, 1864 .ops = &clk_rcg2_shared_ops, 1865 }, 1866 }; 1867 1868 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { 1869 .cmd_rcgr = 0xa1074, 1870 .mnd_width = 0, 1871 .hid_width = 5, 1872 .parent_map = gcc_parent_map_1, 1873 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1874 .clkr.hw.init = &(const struct clk_init_data) { 1875 .name = "gcc_usb3_sec_phy_aux_clk_src", 1876 .parent_data = gcc_parent_data_1, 1877 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1878 .flags = CLK_SET_RATE_PARENT, 1879 .ops = &clk_rcg2_shared_ops, 1880 }, 1881 }; 1882 1883 static struct clk_rcg2 gcc_usb3_tert_phy_aux_clk_src = { 1884 .cmd_rcgr = 0xa2074, 1885 .mnd_width = 0, 1886 .hid_width = 5, 1887 .parent_map = gcc_parent_map_1, 1888 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1889 .clkr.hw.init = &(const struct clk_init_data) { 1890 .name = "gcc_usb3_tert_phy_aux_clk_src", 1891 .parent_data = gcc_parent_data_1, 1892 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1893 .flags = CLK_SET_RATE_PARENT, 1894 .ops = &clk_rcg2_shared_ops, 1895 }, 1896 }; 1897 1898 static const struct freq_tbl ftbl_gcc_usb4_0_master_clk_src[] = { 1899 F(175000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0), 1900 F(350000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0), 1901 { } 1902 }; 1903 1904 static struct clk_rcg2 gcc_usb4_0_master_clk_src = { 1905 .cmd_rcgr = 0x9f024, 1906 .mnd_width = 8, 1907 .hid_width = 5, 1908 .parent_map = gcc_parent_map_4, 1909 .freq_tbl = ftbl_gcc_usb4_0_master_clk_src, 1910 .clkr.hw.init = &(const struct clk_init_data) { 1911 .name = "gcc_usb4_0_master_clk_src", 1912 .parent_data = gcc_parent_data_4, 1913 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1914 .flags = CLK_SET_RATE_PARENT, 1915 .ops = &clk_rcg2_shared_ops, 1916 }, 1917 }; 1918 1919 static const struct freq_tbl ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src[] = { 1920 F(19200000, P_BI_TCXO, 1, 0, 0), 1921 F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0), 1922 F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0), 1923 { } 1924 }; 1925 1926 static struct clk_rcg2 gcc_usb4_0_phy_pcie_pipe_clk_src = { 1927 .cmd_rcgr = 0x9f0e8, 1928 .mnd_width = 0, 1929 .hid_width = 5, 1930 .parent_map = gcc_parent_map_5, 1931 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src, 1932 .clkr.hw.init = &(const struct clk_init_data) { 1933 .name = "gcc_usb4_0_phy_pcie_pipe_clk_src", 1934 .parent_data = gcc_parent_data_5, 1935 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1936 .flags = CLK_SET_RATE_PARENT, 1937 .ops = &clk_rcg2_shared_ops, 1938 }, 1939 }; 1940 1941 static struct clk_rcg2 gcc_usb4_0_sb_if_clk_src = { 1942 .cmd_rcgr = 0x9f08c, 1943 .mnd_width = 0, 1944 .hid_width = 5, 1945 .parent_map = gcc_parent_map_3, 1946 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1947 .clkr.hw.init = &(const struct clk_init_data) { 1948 .name = "gcc_usb4_0_sb_if_clk_src", 1949 .parent_data = gcc_parent_data_3, 1950 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1951 .flags = CLK_SET_RATE_PARENT, 1952 .ops = &clk_rcg2_shared_ops, 1953 }, 1954 }; 1955 1956 static const struct freq_tbl ftbl_gcc_usb4_0_tmu_clk_src[] = { 1957 F(19200000, P_BI_TCXO, 1, 0, 0), 1958 F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0), 1959 { } 1960 }; 1961 1962 static struct clk_rcg2 gcc_usb4_0_tmu_clk_src = { 1963 .cmd_rcgr = 0x9f070, 1964 .mnd_width = 0, 1965 .hid_width = 5, 1966 .parent_map = gcc_parent_map_6, 1967 .freq_tbl = ftbl_gcc_usb4_0_tmu_clk_src, 1968 .clkr.hw.init = &(const struct clk_init_data) { 1969 .name = "gcc_usb4_0_tmu_clk_src", 1970 .parent_data = gcc_parent_data_6, 1971 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 1972 .flags = CLK_SET_RATE_PARENT, 1973 .ops = &clk_rcg2_shared_ops, 1974 }, 1975 }; 1976 1977 static struct clk_rcg2 gcc_usb4_1_master_clk_src = { 1978 .cmd_rcgr = 0x2b024, 1979 .mnd_width = 8, 1980 .hid_width = 5, 1981 .parent_map = gcc_parent_map_4, 1982 .freq_tbl = ftbl_gcc_usb4_0_master_clk_src, 1983 .clkr.hw.init = &(const struct clk_init_data) { 1984 .name = "gcc_usb4_1_master_clk_src", 1985 .parent_data = gcc_parent_data_4, 1986 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1987 .flags = CLK_SET_RATE_PARENT, 1988 .ops = &clk_rcg2_shared_ops, 1989 }, 1990 }; 1991 1992 static struct clk_rcg2 gcc_usb4_1_phy_pcie_pipe_clk_src = { 1993 .cmd_rcgr = 0x2b0e8, 1994 .mnd_width = 0, 1995 .hid_width = 5, 1996 .parent_map = gcc_parent_map_5, 1997 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src, 1998 .clkr.hw.init = &(const struct clk_init_data) { 1999 .name = "gcc_usb4_1_phy_pcie_pipe_clk_src", 2000 .parent_data = gcc_parent_data_5, 2001 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 2002 .flags = CLK_SET_RATE_PARENT, 2003 .ops = &clk_rcg2_shared_ops, 2004 }, 2005 }; 2006 2007 static struct clk_rcg2 gcc_usb4_1_sb_if_clk_src = { 2008 .cmd_rcgr = 0x2b08c, 2009 .mnd_width = 0, 2010 .hid_width = 5, 2011 .parent_map = gcc_parent_map_3, 2012 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2013 .clkr.hw.init = &(const struct clk_init_data) { 2014 .name = "gcc_usb4_1_sb_if_clk_src", 2015 .parent_data = gcc_parent_data_3, 2016 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 2017 .flags = CLK_SET_RATE_PARENT, 2018 .ops = &clk_rcg2_shared_ops, 2019 }, 2020 }; 2021 2022 static struct clk_rcg2 gcc_usb4_1_tmu_clk_src = { 2023 .cmd_rcgr = 0x2b070, 2024 .mnd_width = 0, 2025 .hid_width = 5, 2026 .parent_map = gcc_parent_map_6, 2027 .freq_tbl = ftbl_gcc_usb4_0_tmu_clk_src, 2028 .clkr.hw.init = &(const struct clk_init_data) { 2029 .name = "gcc_usb4_1_tmu_clk_src", 2030 .parent_data = gcc_parent_data_6, 2031 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 2032 .flags = CLK_SET_RATE_PARENT, 2033 .ops = &clk_rcg2_shared_ops, 2034 }, 2035 }; 2036 2037 static struct clk_rcg2 gcc_usb4_2_master_clk_src = { 2038 .cmd_rcgr = 0x11024, 2039 .mnd_width = 8, 2040 .hid_width = 5, 2041 .parent_map = gcc_parent_map_4, 2042 .freq_tbl = ftbl_gcc_usb4_0_master_clk_src, 2043 .clkr.hw.init = &(const struct clk_init_data) { 2044 .name = "gcc_usb4_2_master_clk_src", 2045 .parent_data = gcc_parent_data_4, 2046 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 2047 .flags = CLK_SET_RATE_PARENT, 2048 .ops = &clk_rcg2_shared_ops, 2049 }, 2050 }; 2051 2052 static struct clk_rcg2 gcc_usb4_2_phy_pcie_pipe_clk_src = { 2053 .cmd_rcgr = 0x110e8, 2054 .mnd_width = 0, 2055 .hid_width = 5, 2056 .parent_map = gcc_parent_map_5, 2057 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src, 2058 .clkr.hw.init = &(const struct clk_init_data) { 2059 .name = "gcc_usb4_2_phy_pcie_pipe_clk_src", 2060 .parent_data = gcc_parent_data_5, 2061 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 2062 .flags = CLK_SET_RATE_PARENT, 2063 .ops = &clk_rcg2_shared_ops, 2064 }, 2065 }; 2066 2067 static struct clk_rcg2 gcc_usb4_2_sb_if_clk_src = { 2068 .cmd_rcgr = 0x1108c, 2069 .mnd_width = 0, 2070 .hid_width = 5, 2071 .parent_map = gcc_parent_map_3, 2072 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2073 .clkr.hw.init = &(const struct clk_init_data) { 2074 .name = "gcc_usb4_2_sb_if_clk_src", 2075 .parent_data = gcc_parent_data_3, 2076 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 2077 .flags = CLK_SET_RATE_PARENT, 2078 .ops = &clk_rcg2_shared_ops, 2079 }, 2080 }; 2081 2082 static struct clk_rcg2 gcc_usb4_2_tmu_clk_src = { 2083 .cmd_rcgr = 0x11070, 2084 .mnd_width = 0, 2085 .hid_width = 5, 2086 .parent_map = gcc_parent_map_6, 2087 .freq_tbl = ftbl_gcc_usb4_0_tmu_clk_src, 2088 .clkr.hw.init = &(const struct clk_init_data) { 2089 .name = "gcc_usb4_2_tmu_clk_src", 2090 .parent_data = gcc_parent_data_6, 2091 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 2092 .flags = CLK_SET_RATE_PARENT, 2093 .ops = &clk_rcg2_shared_ops, 2094 }, 2095 }; 2096 2097 static struct clk_regmap_phy_mux gcc_pcie_3_pipe_clk_src = { 2098 .reg = 0x58088, 2099 .clkr = { 2100 .hw.init = &(struct clk_init_data){ 2101 .name = "gcc_pcie_3_pipe_clk_src", 2102 .parent_data = &(const struct clk_parent_data){ 2103 .index = DT_PCIE_3_PIPE, 2104 }, 2105 .num_parents = 1, 2106 .ops = &clk_regmap_phy_mux_ops, 2107 }, 2108 }, 2109 }; 2110 2111 static struct clk_regmap_div gcc_pcie_3_pipe_div_clk_src = { 2112 .reg = 0x5806c, 2113 .shift = 0, 2114 .width = 4, 2115 .clkr.hw.init = &(const struct clk_init_data) { 2116 .name = "gcc_pcie_3_pipe_div_clk_src", 2117 .parent_hws = (const struct clk_hw*[]) { 2118 &gcc_pcie_3_pipe_clk_src.clkr.hw, 2119 }, 2120 .num_parents = 1, 2121 .ops = &clk_regmap_div_ro_ops, 2122 }, 2123 }; 2124 2125 static struct clk_regmap_phy_mux gcc_pcie_4_pipe_clk_src = { 2126 .reg = 0x6b07c, 2127 .clkr = { 2128 .hw.init = &(struct clk_init_data){ 2129 .name = "gcc_pcie_4_pipe_clk_src", 2130 .parent_data = &(const struct clk_parent_data){ 2131 .index = DT_PCIE_4_PIPE, 2132 }, 2133 .num_parents = 1, 2134 .ops = &clk_regmap_phy_mux_ops, 2135 }, 2136 }, 2137 }; 2138 2139 static struct clk_regmap_div gcc_pcie_4_pipe_div_clk_src = { 2140 .reg = 0x6b060, 2141 .shift = 0, 2142 .width = 4, 2143 .clkr.hw.init = &(const struct clk_init_data) { 2144 .name = "gcc_pcie_4_pipe_div_clk_src", 2145 .parent_hws = (const struct clk_hw*[]) { 2146 &gcc_pcie_4_pipe_clk_src.clkr.hw, 2147 }, 2148 .num_parents = 1, 2149 .ops = &clk_regmap_div_ro_ops, 2150 }, 2151 }; 2152 2153 static struct clk_regmap_phy_mux gcc_pcie_5_pipe_clk_src = { 2154 .reg = 0x2f07c, 2155 .clkr = { 2156 .hw.init = &(struct clk_init_data){ 2157 .name = "gcc_pcie_5_pipe_clk_src", 2158 .parent_data = &(const struct clk_parent_data){ 2159 .index = DT_PCIE_5_PIPE, 2160 }, 2161 .num_parents = 1, 2162 .ops = &clk_regmap_phy_mux_ops, 2163 }, 2164 }, 2165 }; 2166 2167 static struct clk_regmap_div gcc_pcie_5_pipe_div_clk_src = { 2168 .reg = 0x2f060, 2169 .shift = 0, 2170 .width = 4, 2171 .clkr.hw.init = &(const struct clk_init_data) { 2172 .name = "gcc_pcie_5_pipe_div_clk_src", 2173 .parent_hws = (const struct clk_hw*[]) { 2174 &gcc_pcie_5_pipe_clk_src.clkr.hw, 2175 }, 2176 .num_parents = 1, 2177 .ops = &clk_regmap_div_ro_ops, 2178 }, 2179 }; 2180 2181 static struct clk_regmap_phy_mux gcc_pcie_6a_pipe_clk_src = { 2182 .reg = 0x31088, 2183 .clkr = { 2184 .hw.init = &(struct clk_init_data){ 2185 .name = "gcc_pcie_6a_pipe_clk_src", 2186 .parent_data = &(const struct clk_parent_data){ 2187 .index = DT_PCIE_6A_PIPE, 2188 }, 2189 .num_parents = 1, 2190 .ops = &clk_regmap_phy_mux_ops, 2191 }, 2192 }, 2193 }; 2194 2195 static struct clk_regmap_div gcc_pcie_6a_pipe_div_clk_src = { 2196 .reg = 0x3106c, 2197 .shift = 0, 2198 .width = 4, 2199 .clkr.hw.init = &(const struct clk_init_data) { 2200 .name = "gcc_pcie_6a_pipe_div_clk_src", 2201 .parent_hws = (const struct clk_hw*[]) { 2202 &gcc_pcie_6a_pipe_clk_src.clkr.hw, 2203 }, 2204 .num_parents = 1, 2205 .ops = &clk_regmap_div_ro_ops, 2206 }, 2207 }; 2208 2209 static struct clk_regmap_phy_mux gcc_pcie_6b_pipe_clk_src = { 2210 .reg = 0x8d088, 2211 .clkr = { 2212 .hw.init = &(struct clk_init_data){ 2213 .name = "gcc_pcie_6b_pipe_clk_src", 2214 .parent_data = &(const struct clk_parent_data){ 2215 .index = DT_PCIE_6B_PIPE, 2216 }, 2217 .num_parents = 1, 2218 .ops = &clk_regmap_phy_mux_ops, 2219 }, 2220 }, 2221 }; 2222 2223 static struct clk_regmap_div gcc_pcie_6b_pipe_div_clk_src = { 2224 .reg = 0x8d06c, 2225 .shift = 0, 2226 .width = 4, 2227 .clkr.hw.init = &(const struct clk_init_data) { 2228 .name = "gcc_pcie_6b_pipe_div_clk_src", 2229 .parent_hws = (const struct clk_hw*[]) { 2230 &gcc_pcie_6b_pipe_clk_src.clkr.hw, 2231 }, 2232 .num_parents = 1, 2233 .ops = &clk_regmap_div_ro_ops, 2234 }, 2235 }; 2236 2237 static struct clk_regmap_div gcc_qupv3_wrap0_s2_div_clk_src = { 2238 .reg = 0x42284, 2239 .shift = 0, 2240 .width = 4, 2241 .clkr.hw.init = &(const struct clk_init_data) { 2242 .name = "gcc_qupv3_wrap0_s2_div_clk_src", 2243 .parent_hws = (const struct clk_hw*[]) { 2244 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 2245 }, 2246 .num_parents = 1, 2247 .flags = CLK_SET_RATE_PARENT, 2248 .ops = &clk_regmap_div_ro_ops, 2249 }, 2250 }; 2251 2252 static struct clk_regmap_div gcc_qupv3_wrap0_s3_div_clk_src = { 2253 .reg = 0x423c4, 2254 .shift = 0, 2255 .width = 4, 2256 .clkr.hw.init = &(const struct clk_init_data) { 2257 .name = "gcc_qupv3_wrap0_s3_div_clk_src", 2258 .parent_hws = (const struct clk_hw*[]) { 2259 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 2260 }, 2261 .num_parents = 1, 2262 .flags = CLK_SET_RATE_PARENT, 2263 .ops = &clk_regmap_div_ro_ops, 2264 }, 2265 }; 2266 2267 static struct clk_regmap_div gcc_qupv3_wrap1_s2_div_clk_src = { 2268 .reg = 0x18284, 2269 .shift = 0, 2270 .width = 4, 2271 .clkr.hw.init = &(const struct clk_init_data) { 2272 .name = "gcc_qupv3_wrap1_s2_div_clk_src", 2273 .parent_hws = (const struct clk_hw*[]) { 2274 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 2275 }, 2276 .num_parents = 1, 2277 .flags = CLK_SET_RATE_PARENT, 2278 .ops = &clk_regmap_div_ro_ops, 2279 }, 2280 }; 2281 2282 static struct clk_regmap_div gcc_qupv3_wrap1_s3_div_clk_src = { 2283 .reg = 0x183c4, 2284 .shift = 0, 2285 .width = 4, 2286 .clkr.hw.init = &(const struct clk_init_data) { 2287 .name = "gcc_qupv3_wrap1_s3_div_clk_src", 2288 .parent_hws = (const struct clk_hw*[]) { 2289 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2290 }, 2291 .num_parents = 1, 2292 .flags = CLK_SET_RATE_PARENT, 2293 .ops = &clk_regmap_div_ro_ops, 2294 }, 2295 }; 2296 2297 static struct clk_regmap_div gcc_qupv3_wrap2_s2_div_clk_src = { 2298 .reg = 0x1e284, 2299 .shift = 0, 2300 .width = 4, 2301 .clkr.hw.init = &(const struct clk_init_data) { 2302 .name = "gcc_qupv3_wrap2_s2_div_clk_src", 2303 .parent_hws = (const struct clk_hw*[]) { 2304 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 2305 }, 2306 .num_parents = 1, 2307 .flags = CLK_SET_RATE_PARENT, 2308 .ops = &clk_regmap_div_ro_ops, 2309 }, 2310 }; 2311 2312 static struct clk_regmap_div gcc_qupv3_wrap2_s3_div_clk_src = { 2313 .reg = 0x1e3c4, 2314 .shift = 0, 2315 .width = 4, 2316 .clkr.hw.init = &(const struct clk_init_data) { 2317 .name = "gcc_qupv3_wrap2_s3_div_clk_src", 2318 .parent_hws = (const struct clk_hw*[]) { 2319 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 2320 }, 2321 .num_parents = 1, 2322 .flags = CLK_SET_RATE_PARENT, 2323 .ops = &clk_regmap_div_ro_ops, 2324 }, 2325 }; 2326 2327 static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src = { 2328 .reg = 0x29284, 2329 .shift = 0, 2330 .width = 4, 2331 .clkr.hw.init = &(const struct clk_init_data) { 2332 .name = "gcc_usb20_mock_utmi_postdiv_clk_src", 2333 .parent_hws = (const struct clk_hw*[]) { 2334 &gcc_usb20_mock_utmi_clk_src.clkr.hw, 2335 }, 2336 .num_parents = 1, 2337 .flags = CLK_SET_RATE_PARENT, 2338 .ops = &clk_regmap_div_ro_ops, 2339 }, 2340 }; 2341 2342 static struct clk_regmap_div gcc_usb30_mp_mock_utmi_postdiv_clk_src = { 2343 .reg = 0x17284, 2344 .shift = 0, 2345 .width = 4, 2346 .clkr.hw.init = &(const struct clk_init_data) { 2347 .name = "gcc_usb30_mp_mock_utmi_postdiv_clk_src", 2348 .parent_hws = (const struct clk_hw*[]) { 2349 &gcc_usb30_mp_mock_utmi_clk_src.clkr.hw, 2350 }, 2351 .num_parents = 1, 2352 .flags = CLK_SET_RATE_PARENT, 2353 .ops = &clk_regmap_div_ro_ops, 2354 }, 2355 }; 2356 2357 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 2358 .reg = 0x3905c, 2359 .shift = 0, 2360 .width = 4, 2361 .clkr.hw.init = &(const struct clk_init_data) { 2362 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 2363 .parent_hws = (const struct clk_hw*[]) { 2364 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 2365 }, 2366 .num_parents = 1, 2367 .flags = CLK_SET_RATE_PARENT, 2368 .ops = &clk_regmap_div_ro_ops, 2369 }, 2370 }; 2371 2372 static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = { 2373 .reg = 0xa105c, 2374 .shift = 0, 2375 .width = 4, 2376 .clkr.hw.init = &(const struct clk_init_data) { 2377 .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src", 2378 .parent_hws = (const struct clk_hw*[]) { 2379 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, 2380 }, 2381 .num_parents = 1, 2382 .flags = CLK_SET_RATE_PARENT, 2383 .ops = &clk_regmap_div_ro_ops, 2384 }, 2385 }; 2386 2387 static struct clk_regmap_div gcc_usb30_tert_mock_utmi_postdiv_clk_src = { 2388 .reg = 0xa205c, 2389 .shift = 0, 2390 .width = 4, 2391 .clkr.hw.init = &(const struct clk_init_data) { 2392 .name = "gcc_usb30_tert_mock_utmi_postdiv_clk_src", 2393 .parent_hws = (const struct clk_hw*[]) { 2394 &gcc_usb30_tert_mock_utmi_clk_src.clkr.hw, 2395 }, 2396 .num_parents = 1, 2397 .flags = CLK_SET_RATE_PARENT, 2398 .ops = &clk_regmap_div_ro_ops, 2399 }, 2400 }; 2401 2402 static struct clk_branch gcc_aggre_noc_usb_north_axi_clk = { 2403 .halt_reg = 0x2d17c, 2404 .halt_check = BRANCH_HALT_VOTED, 2405 .hwcg_reg = 0x2d17c, 2406 .hwcg_bit = 1, 2407 .clkr = { 2408 .enable_reg = 0x2d17c, 2409 .enable_mask = BIT(0), 2410 .hw.init = &(const struct clk_init_data) { 2411 .name = "gcc_aggre_noc_usb_north_axi_clk", 2412 .ops = &clk_branch2_ops, 2413 }, 2414 }, 2415 }; 2416 2417 static struct clk_branch gcc_aggre_noc_usb_south_axi_clk = { 2418 .halt_reg = 0x2d174, 2419 .halt_check = BRANCH_HALT_VOTED, 2420 .hwcg_reg = 0x2d174, 2421 .hwcg_bit = 1, 2422 .clkr = { 2423 .enable_reg = 0x2d174, 2424 .enable_mask = BIT(0), 2425 .hw.init = &(const struct clk_init_data) { 2426 .name = "gcc_aggre_noc_usb_south_axi_clk", 2427 .ops = &clk_branch2_ops, 2428 }, 2429 }, 2430 }; 2431 2432 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 2433 .halt_reg = 0x770e4, 2434 .halt_check = BRANCH_HALT_VOTED, 2435 .hwcg_reg = 0x770e4, 2436 .hwcg_bit = 1, 2437 .clkr = { 2438 .enable_reg = 0x770e4, 2439 .enable_mask = BIT(0), 2440 .hw.init = &(const struct clk_init_data) { 2441 .name = "gcc_aggre_ufs_phy_axi_clk", 2442 .parent_hws = (const struct clk_hw*[]) { 2443 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2444 }, 2445 .num_parents = 1, 2446 .flags = CLK_SET_RATE_PARENT, 2447 .ops = &clk_branch2_ops, 2448 }, 2449 }, 2450 }; 2451 2452 static struct clk_branch gcc_aggre_usb2_prim_axi_clk = { 2453 .halt_reg = 0x2928c, 2454 .halt_check = BRANCH_HALT_VOTED, 2455 .hwcg_reg = 0x2928c, 2456 .hwcg_bit = 1, 2457 .clkr = { 2458 .enable_reg = 0x2928c, 2459 .enable_mask = BIT(0), 2460 .hw.init = &(const struct clk_init_data) { 2461 .name = "gcc_aggre_usb2_prim_axi_clk", 2462 .parent_hws = (const struct clk_hw*[]) { 2463 &gcc_usb20_master_clk_src.clkr.hw, 2464 }, 2465 .num_parents = 1, 2466 .flags = CLK_SET_RATE_PARENT, 2467 .ops = &clk_branch2_ops, 2468 }, 2469 }, 2470 }; 2471 2472 static struct clk_branch gcc_aggre_usb3_mp_axi_clk = { 2473 .halt_reg = 0x173d0, 2474 .halt_check = BRANCH_HALT_VOTED, 2475 .hwcg_reg = 0x173d0, 2476 .hwcg_bit = 1, 2477 .clkr = { 2478 .enable_reg = 0x173d0, 2479 .enable_mask = BIT(0), 2480 .hw.init = &(const struct clk_init_data) { 2481 .name = "gcc_aggre_usb3_mp_axi_clk", 2482 .parent_hws = (const struct clk_hw*[]) { 2483 &gcc_usb30_mp_master_clk_src.clkr.hw, 2484 }, 2485 .num_parents = 1, 2486 .flags = CLK_SET_RATE_PARENT, 2487 .ops = &clk_branch2_ops, 2488 }, 2489 }, 2490 }; 2491 2492 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 2493 .halt_reg = 0x39090, 2494 .halt_check = BRANCH_HALT_VOTED, 2495 .hwcg_reg = 0x39090, 2496 .hwcg_bit = 1, 2497 .clkr = { 2498 .enable_reg = 0x39090, 2499 .enable_mask = BIT(0), 2500 .hw.init = &(const struct clk_init_data) { 2501 .name = "gcc_aggre_usb3_prim_axi_clk", 2502 .parent_hws = (const struct clk_hw*[]) { 2503 &gcc_usb30_prim_master_clk_src.clkr.hw, 2504 }, 2505 .num_parents = 1, 2506 .flags = CLK_SET_RATE_PARENT, 2507 .ops = &clk_branch2_ops, 2508 }, 2509 }, 2510 }; 2511 2512 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { 2513 .halt_reg = 0xa1090, 2514 .halt_check = BRANCH_HALT_VOTED, 2515 .hwcg_reg = 0xa1090, 2516 .hwcg_bit = 1, 2517 .clkr = { 2518 .enable_reg = 0xa1090, 2519 .enable_mask = BIT(0), 2520 .hw.init = &(const struct clk_init_data) { 2521 .name = "gcc_aggre_usb3_sec_axi_clk", 2522 .parent_hws = (const struct clk_hw*[]) { 2523 &gcc_usb30_sec_master_clk_src.clkr.hw, 2524 }, 2525 .num_parents = 1, 2526 .flags = CLK_SET_RATE_PARENT, 2527 .ops = &clk_branch2_ops, 2528 }, 2529 }, 2530 }; 2531 2532 static struct clk_branch gcc_aggre_usb3_tert_axi_clk = { 2533 .halt_reg = 0xa2090, 2534 .halt_check = BRANCH_HALT_VOTED, 2535 .hwcg_reg = 0xa2090, 2536 .hwcg_bit = 1, 2537 .clkr = { 2538 .enable_reg = 0xa2090, 2539 .enable_mask = BIT(0), 2540 .hw.init = &(const struct clk_init_data) { 2541 .name = "gcc_aggre_usb3_tert_axi_clk", 2542 .parent_hws = (const struct clk_hw*[]) { 2543 &gcc_usb30_tert_master_clk_src.clkr.hw, 2544 }, 2545 .num_parents = 1, 2546 .flags = CLK_SET_RATE_PARENT, 2547 .ops = &clk_branch2_ops, 2548 }, 2549 }, 2550 }; 2551 2552 static struct clk_branch gcc_aggre_usb4_0_axi_clk = { 2553 .halt_reg = 0x9f118, 2554 .halt_check = BRANCH_HALT_VOTED, 2555 .hwcg_reg = 0x9f118, 2556 .hwcg_bit = 1, 2557 .clkr = { 2558 .enable_reg = 0x9f118, 2559 .enable_mask = BIT(0), 2560 .hw.init = &(const struct clk_init_data) { 2561 .name = "gcc_aggre_usb4_0_axi_clk", 2562 .parent_hws = (const struct clk_hw*[]) { 2563 &gcc_usb4_0_master_clk_src.clkr.hw, 2564 }, 2565 .num_parents = 1, 2566 .flags = CLK_SET_RATE_PARENT, 2567 .ops = &clk_branch2_ops, 2568 }, 2569 }, 2570 }; 2571 2572 static struct clk_branch gcc_aggre_usb4_1_axi_clk = { 2573 .halt_reg = 0x2b118, 2574 .halt_check = BRANCH_HALT_VOTED, 2575 .hwcg_reg = 0x2b118, 2576 .hwcg_bit = 1, 2577 .clkr = { 2578 .enable_reg = 0x2b118, 2579 .enable_mask = BIT(0), 2580 .hw.init = &(const struct clk_init_data) { 2581 .name = "gcc_aggre_usb4_1_axi_clk", 2582 .parent_hws = (const struct clk_hw*[]) { 2583 &gcc_usb4_1_master_clk_src.clkr.hw, 2584 }, 2585 .num_parents = 1, 2586 .flags = CLK_SET_RATE_PARENT, 2587 .ops = &clk_branch2_ops, 2588 }, 2589 }, 2590 }; 2591 2592 static struct clk_branch gcc_aggre_usb4_2_axi_clk = { 2593 .halt_reg = 0x11118, 2594 .halt_check = BRANCH_HALT_VOTED, 2595 .hwcg_reg = 0x11118, 2596 .hwcg_bit = 1, 2597 .clkr = { 2598 .enable_reg = 0x11118, 2599 .enable_mask = BIT(0), 2600 .hw.init = &(const struct clk_init_data) { 2601 .name = "gcc_aggre_usb4_2_axi_clk", 2602 .parent_hws = (const struct clk_hw*[]) { 2603 &gcc_usb4_2_master_clk_src.clkr.hw, 2604 }, 2605 .num_parents = 1, 2606 .flags = CLK_SET_RATE_PARENT, 2607 .ops = &clk_branch2_ops, 2608 }, 2609 }, 2610 }; 2611 2612 static struct clk_branch gcc_aggre_usb_noc_axi_clk = { 2613 .halt_reg = 0x2d034, 2614 .halt_check = BRANCH_HALT_VOTED, 2615 .hwcg_reg = 0x2d034, 2616 .hwcg_bit = 1, 2617 .clkr = { 2618 .enable_reg = 0x2d034, 2619 .enable_mask = BIT(0), 2620 .hw.init = &(const struct clk_init_data) { 2621 .name = "gcc_aggre_usb_noc_axi_clk", 2622 .ops = &clk_branch2_ops, 2623 }, 2624 }, 2625 }; 2626 2627 static struct clk_branch gcc_av1e_ahb_clk = { 2628 .halt_reg = 0x4a004, 2629 .halt_check = BRANCH_HALT_VOTED, 2630 .hwcg_reg = 0x4a004, 2631 .hwcg_bit = 1, 2632 .clkr = { 2633 .enable_reg = 0x4a004, 2634 .enable_mask = BIT(0), 2635 .hw.init = &(const struct clk_init_data) { 2636 .name = "gcc_av1e_ahb_clk", 2637 .ops = &clk_branch2_ops, 2638 }, 2639 }, 2640 }; 2641 2642 static struct clk_branch gcc_av1e_axi_clk = { 2643 .halt_reg = 0x4a008, 2644 .halt_check = BRANCH_HALT_SKIP, 2645 .hwcg_reg = 0x4a008, 2646 .hwcg_bit = 1, 2647 .clkr = { 2648 .enable_reg = 0x4a008, 2649 .enable_mask = BIT(0), 2650 .hw.init = &(const struct clk_init_data) { 2651 .name = "gcc_av1e_axi_clk", 2652 .ops = &clk_branch2_ops, 2653 }, 2654 }, 2655 }; 2656 2657 static struct clk_branch gcc_av1e_xo_clk = { 2658 .halt_reg = 0x4a014, 2659 .halt_check = BRANCH_HALT, 2660 .clkr = { 2661 .enable_reg = 0x4a014, 2662 .enable_mask = BIT(0), 2663 .hw.init = &(const struct clk_init_data) { 2664 .name = "gcc_av1e_xo_clk", 2665 .ops = &clk_branch2_ops, 2666 }, 2667 }, 2668 }; 2669 2670 static struct clk_branch gcc_boot_rom_ahb_clk = { 2671 .halt_reg = 0x38004, 2672 .halt_check = BRANCH_HALT_VOTED, 2673 .hwcg_reg = 0x38004, 2674 .hwcg_bit = 1, 2675 .clkr = { 2676 .enable_reg = 0x52000, 2677 .enable_mask = BIT(10), 2678 .hw.init = &(const struct clk_init_data) { 2679 .name = "gcc_boot_rom_ahb_clk", 2680 .ops = &clk_branch2_ops, 2681 }, 2682 }, 2683 }; 2684 2685 static struct clk_branch gcc_camera_hf_axi_clk = { 2686 .halt_reg = 0x26010, 2687 .halt_check = BRANCH_HALT_SKIP, 2688 .hwcg_reg = 0x26010, 2689 .hwcg_bit = 1, 2690 .clkr = { 2691 .enable_reg = 0x26010, 2692 .enable_mask = BIT(0), 2693 .hw.init = &(const struct clk_init_data) { 2694 .name = "gcc_camera_hf_axi_clk", 2695 .ops = &clk_branch2_ops, 2696 }, 2697 }, 2698 }; 2699 2700 static struct clk_branch gcc_camera_sf_axi_clk = { 2701 .halt_reg = 0x2601c, 2702 .halt_check = BRANCH_HALT_SKIP, 2703 .hwcg_reg = 0x2601c, 2704 .hwcg_bit = 1, 2705 .clkr = { 2706 .enable_reg = 0x2601c, 2707 .enable_mask = BIT(0), 2708 .hw.init = &(const struct clk_init_data) { 2709 .name = "gcc_camera_sf_axi_clk", 2710 .ops = &clk_branch2_ops, 2711 }, 2712 }, 2713 }; 2714 2715 static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = { 2716 .halt_reg = 0x10028, 2717 .halt_check = BRANCH_HALT_VOTED, 2718 .hwcg_reg = 0x10028, 2719 .hwcg_bit = 1, 2720 .clkr = { 2721 .enable_reg = 0x52028, 2722 .enable_mask = BIT(20), 2723 .hw.init = &(const struct clk_init_data) { 2724 .name = "gcc_cfg_noc_pcie_anoc_ahb_clk", 2725 .ops = &clk_branch2_ops, 2726 }, 2727 }, 2728 }; 2729 2730 static struct clk_branch gcc_cfg_noc_pcie_anoc_north_ahb_clk = { 2731 .halt_reg = 0x1002c, 2732 .halt_check = BRANCH_HALT_VOTED, 2733 .hwcg_reg = 0x1002c, 2734 .hwcg_bit = 1, 2735 .clkr = { 2736 .enable_reg = 0x52028, 2737 .enable_mask = BIT(22), 2738 .hw.init = &(const struct clk_init_data) { 2739 .name = "gcc_cfg_noc_pcie_anoc_north_ahb_clk", 2740 .ops = &clk_branch2_ops, 2741 }, 2742 }, 2743 }; 2744 2745 static struct clk_branch gcc_cfg_noc_pcie_anoc_south_ahb_clk = { 2746 .halt_reg = 0x10030, 2747 .halt_check = BRANCH_HALT_VOTED, 2748 .hwcg_reg = 0x10030, 2749 .hwcg_bit = 1, 2750 .clkr = { 2751 .enable_reg = 0x52000, 2752 .enable_mask = BIT(20), 2753 .hw.init = &(const struct clk_init_data) { 2754 .name = "gcc_cfg_noc_pcie_anoc_south_ahb_clk", 2755 .ops = &clk_branch2_ops, 2756 }, 2757 }, 2758 }; 2759 2760 static struct clk_branch gcc_cfg_noc_usb2_prim_axi_clk = { 2761 .halt_reg = 0x29288, 2762 .halt_check = BRANCH_HALT_VOTED, 2763 .hwcg_reg = 0x29288, 2764 .hwcg_bit = 1, 2765 .clkr = { 2766 .enable_reg = 0x29288, 2767 .enable_mask = BIT(0), 2768 .hw.init = &(const struct clk_init_data) { 2769 .name = "gcc_cfg_noc_usb2_prim_axi_clk", 2770 .parent_hws = (const struct clk_hw*[]) { 2771 &gcc_usb20_master_clk_src.clkr.hw, 2772 }, 2773 .num_parents = 1, 2774 .flags = CLK_SET_RATE_PARENT, 2775 .ops = &clk_branch2_ops, 2776 }, 2777 }, 2778 }; 2779 2780 static struct clk_branch gcc_cfg_noc_usb3_mp_axi_clk = { 2781 .halt_reg = 0x173cc, 2782 .halt_check = BRANCH_HALT_VOTED, 2783 .hwcg_reg = 0x173cc, 2784 .hwcg_bit = 1, 2785 .clkr = { 2786 .enable_reg = 0x173cc, 2787 .enable_mask = BIT(0), 2788 .hw.init = &(const struct clk_init_data) { 2789 .name = "gcc_cfg_noc_usb3_mp_axi_clk", 2790 .parent_hws = (const struct clk_hw*[]) { 2791 &gcc_usb30_mp_master_clk_src.clkr.hw, 2792 }, 2793 .num_parents = 1, 2794 .flags = CLK_SET_RATE_PARENT, 2795 .ops = &clk_branch2_ops, 2796 }, 2797 }, 2798 }; 2799 2800 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 2801 .halt_reg = 0x3908c, 2802 .halt_check = BRANCH_HALT_VOTED, 2803 .hwcg_reg = 0x3908c, 2804 .hwcg_bit = 1, 2805 .clkr = { 2806 .enable_reg = 0x3908c, 2807 .enable_mask = BIT(0), 2808 .hw.init = &(const struct clk_init_data) { 2809 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 2810 .parent_hws = (const struct clk_hw*[]) { 2811 &gcc_usb30_prim_master_clk_src.clkr.hw, 2812 }, 2813 .num_parents = 1, 2814 .flags = CLK_SET_RATE_PARENT, 2815 .ops = &clk_branch2_ops, 2816 }, 2817 }, 2818 }; 2819 2820 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { 2821 .halt_reg = 0xa108c, 2822 .halt_check = BRANCH_HALT_VOTED, 2823 .hwcg_reg = 0xa108c, 2824 .hwcg_bit = 1, 2825 .clkr = { 2826 .enable_reg = 0xa108c, 2827 .enable_mask = BIT(0), 2828 .hw.init = &(const struct clk_init_data) { 2829 .name = "gcc_cfg_noc_usb3_sec_axi_clk", 2830 .parent_hws = (const struct clk_hw*[]) { 2831 &gcc_usb30_sec_master_clk_src.clkr.hw, 2832 }, 2833 .num_parents = 1, 2834 .flags = CLK_SET_RATE_PARENT, 2835 .ops = &clk_branch2_ops, 2836 }, 2837 }, 2838 }; 2839 2840 static struct clk_branch gcc_cfg_noc_usb3_tert_axi_clk = { 2841 .halt_reg = 0xa208c, 2842 .halt_check = BRANCH_HALT_VOTED, 2843 .hwcg_reg = 0xa208c, 2844 .hwcg_bit = 1, 2845 .clkr = { 2846 .enable_reg = 0xa208c, 2847 .enable_mask = BIT(0), 2848 .hw.init = &(const struct clk_init_data) { 2849 .name = "gcc_cfg_noc_usb3_tert_axi_clk", 2850 .parent_hws = (const struct clk_hw*[]) { 2851 &gcc_usb30_tert_master_clk_src.clkr.hw, 2852 }, 2853 .num_parents = 1, 2854 .flags = CLK_SET_RATE_PARENT, 2855 .ops = &clk_branch2_ops, 2856 }, 2857 }, 2858 }; 2859 2860 static struct clk_branch gcc_cfg_noc_usb_anoc_ahb_clk = { 2861 .halt_reg = 0x2d024, 2862 .halt_check = BRANCH_HALT_VOTED, 2863 .hwcg_reg = 0x2d024, 2864 .hwcg_bit = 1, 2865 .clkr = { 2866 .enable_reg = 0x52028, 2867 .enable_mask = BIT(21), 2868 .hw.init = &(const struct clk_init_data) { 2869 .name = "gcc_cfg_noc_usb_anoc_ahb_clk", 2870 .ops = &clk_branch2_ops, 2871 }, 2872 }, 2873 }; 2874 2875 static struct clk_branch gcc_cfg_noc_usb_anoc_north_ahb_clk = { 2876 .halt_reg = 0x2d028, 2877 .halt_check = BRANCH_HALT_VOTED, 2878 .hwcg_reg = 0x2d028, 2879 .hwcg_bit = 1, 2880 .clkr = { 2881 .enable_reg = 0x52028, 2882 .enable_mask = BIT(23), 2883 .hw.init = &(const struct clk_init_data) { 2884 .name = "gcc_cfg_noc_usb_anoc_north_ahb_clk", 2885 .ops = &clk_branch2_ops, 2886 }, 2887 }, 2888 }; 2889 2890 static struct clk_branch gcc_cfg_noc_usb_anoc_south_ahb_clk = { 2891 .halt_reg = 0x2d02c, 2892 .halt_check = BRANCH_HALT_VOTED, 2893 .hwcg_reg = 0x2d02c, 2894 .hwcg_bit = 1, 2895 .clkr = { 2896 .enable_reg = 0x52018, 2897 .enable_mask = BIT(7), 2898 .hw.init = &(const struct clk_init_data) { 2899 .name = "gcc_cfg_noc_usb_anoc_south_ahb_clk", 2900 .ops = &clk_branch2_ops, 2901 }, 2902 }, 2903 }; 2904 2905 static struct clk_branch gcc_cnoc_pcie1_tunnel_clk = { 2906 .halt_reg = 0x2c2b4, 2907 .halt_check = BRANCH_HALT_VOTED, 2908 .clkr = { 2909 .enable_reg = 0x52010, 2910 .enable_mask = BIT(30), 2911 .hw.init = &(const struct clk_init_data) { 2912 .name = "gcc_cnoc_pcie1_tunnel_clk", 2913 .ops = &clk_branch2_ops, 2914 }, 2915 }, 2916 }; 2917 2918 static struct clk_branch gcc_cnoc_pcie2_tunnel_clk = { 2919 .halt_reg = 0x132b4, 2920 .halt_check = BRANCH_HALT_VOTED, 2921 .clkr = { 2922 .enable_reg = 0x52010, 2923 .enable_mask = BIT(31), 2924 .hw.init = &(const struct clk_init_data) { 2925 .name = "gcc_cnoc_pcie2_tunnel_clk", 2926 .ops = &clk_branch2_ops, 2927 }, 2928 }, 2929 }; 2930 2931 static struct clk_branch gcc_cnoc_pcie_north_sf_axi_clk = { 2932 .halt_reg = 0x10014, 2933 .halt_check = BRANCH_HALT_VOTED, 2934 .hwcg_reg = 0x10014, 2935 .hwcg_bit = 1, 2936 .clkr = { 2937 .enable_reg = 0x52008, 2938 .enable_mask = BIT(6), 2939 .hw.init = &(const struct clk_init_data) { 2940 .name = "gcc_cnoc_pcie_north_sf_axi_clk", 2941 .ops = &clk_branch2_ops, 2942 }, 2943 }, 2944 }; 2945 2946 static struct clk_branch gcc_cnoc_pcie_south_sf_axi_clk = { 2947 .halt_reg = 0x10018, 2948 .halt_check = BRANCH_HALT_VOTED, 2949 .hwcg_reg = 0x10018, 2950 .hwcg_bit = 1, 2951 .clkr = { 2952 .enable_reg = 0x52028, 2953 .enable_mask = BIT(12), 2954 .hw.init = &(const struct clk_init_data) { 2955 .name = "gcc_cnoc_pcie_south_sf_axi_clk", 2956 .ops = &clk_branch2_ops, 2957 }, 2958 }, 2959 }; 2960 2961 static struct clk_branch gcc_cnoc_pcie_tunnel_clk = { 2962 .halt_reg = 0xa02b4, 2963 .halt_check = BRANCH_HALT_VOTED, 2964 .hwcg_reg = 0xa02b4, 2965 .hwcg_bit = 1, 2966 .clkr = { 2967 .enable_reg = 0x52010, 2968 .enable_mask = BIT(29), 2969 .hw.init = &(const struct clk_init_data) { 2970 .name = "gcc_cnoc_pcie_tunnel_clk", 2971 .ops = &clk_branch2_ops, 2972 }, 2973 }, 2974 }; 2975 2976 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 2977 .halt_reg = 0x7115c, 2978 .halt_check = BRANCH_HALT_SKIP, 2979 .hwcg_reg = 0x7115c, 2980 .hwcg_bit = 1, 2981 .clkr = { 2982 .enable_reg = 0x7115c, 2983 .enable_mask = BIT(0), 2984 .hw.init = &(const struct clk_init_data) { 2985 .name = "gcc_ddrss_gpu_axi_clk", 2986 .ops = &clk_branch2_ops, 2987 }, 2988 }, 2989 }; 2990 2991 static struct clk_branch gcc_disp_hf_axi_clk = { 2992 .halt_reg = 0x2700c, 2993 .halt_check = BRANCH_HALT_SKIP, 2994 .hwcg_reg = 0x2700c, 2995 .hwcg_bit = 1, 2996 .clkr = { 2997 .enable_reg = 0x2700c, 2998 .enable_mask = BIT(0), 2999 .hw.init = &(const struct clk_init_data) { 3000 .name = "gcc_disp_hf_axi_clk", 3001 .ops = &clk_branch2_ops, 3002 }, 3003 }, 3004 }; 3005 3006 static struct clk_branch gcc_gp1_clk = { 3007 .halt_reg = 0x64000, 3008 .halt_check = BRANCH_HALT, 3009 .clkr = { 3010 .enable_reg = 0x64000, 3011 .enable_mask = BIT(0), 3012 .hw.init = &(const struct clk_init_data) { 3013 .name = "gcc_gp1_clk", 3014 .parent_hws = (const struct clk_hw*[]) { 3015 &gcc_gp1_clk_src.clkr.hw, 3016 }, 3017 .num_parents = 1, 3018 .flags = CLK_SET_RATE_PARENT, 3019 .ops = &clk_branch2_ops, 3020 }, 3021 }, 3022 }; 3023 3024 static struct clk_branch gcc_gp2_clk = { 3025 .halt_reg = 0x65000, 3026 .halt_check = BRANCH_HALT, 3027 .clkr = { 3028 .enable_reg = 0x65000, 3029 .enable_mask = BIT(0), 3030 .hw.init = &(const struct clk_init_data) { 3031 .name = "gcc_gp2_clk", 3032 .parent_hws = (const struct clk_hw*[]) { 3033 &gcc_gp2_clk_src.clkr.hw, 3034 }, 3035 .num_parents = 1, 3036 .flags = CLK_SET_RATE_PARENT, 3037 .ops = &clk_branch2_ops, 3038 }, 3039 }, 3040 }; 3041 3042 static struct clk_branch gcc_gp3_clk = { 3043 .halt_reg = 0x66000, 3044 .halt_check = BRANCH_HALT, 3045 .clkr = { 3046 .enable_reg = 0x66000, 3047 .enable_mask = BIT(0), 3048 .hw.init = &(const struct clk_init_data) { 3049 .name = "gcc_gp3_clk", 3050 .parent_hws = (const struct clk_hw*[]) { 3051 &gcc_gp3_clk_src.clkr.hw, 3052 }, 3053 .num_parents = 1, 3054 .flags = CLK_SET_RATE_PARENT, 3055 .ops = &clk_branch2_ops, 3056 }, 3057 }, 3058 }; 3059 3060 static struct clk_branch gcc_gpu_gpll0_cph_clk_src = { 3061 .halt_check = BRANCH_HALT_DELAY, 3062 .clkr = { 3063 .enable_reg = 0x52000, 3064 .enable_mask = BIT(15), 3065 .hw.init = &(const struct clk_init_data) { 3066 .name = "gcc_gpu_gpll0_cph_clk_src", 3067 .parent_hws = (const struct clk_hw*[]) { 3068 &gcc_gpll0.clkr.hw, 3069 }, 3070 .num_parents = 1, 3071 .flags = CLK_SET_RATE_PARENT, 3072 .ops = &clk_branch2_ops, 3073 }, 3074 }, 3075 }; 3076 3077 static struct clk_branch gcc_gpu_gpll0_div_cph_clk_src = { 3078 .halt_check = BRANCH_HALT_DELAY, 3079 .clkr = { 3080 .enable_reg = 0x52000, 3081 .enable_mask = BIT(16), 3082 .hw.init = &(const struct clk_init_data) { 3083 .name = "gcc_gpu_gpll0_div_cph_clk_src", 3084 .parent_hws = (const struct clk_hw*[]) { 3085 &gcc_gpll0_out_even.clkr.hw, 3086 }, 3087 .num_parents = 1, 3088 .flags = CLK_SET_RATE_PARENT, 3089 .ops = &clk_branch2_ops, 3090 }, 3091 }, 3092 }; 3093 3094 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 3095 .halt_reg = 0x71010, 3096 .halt_check = BRANCH_HALT_VOTED, 3097 .hwcg_reg = 0x71010, 3098 .hwcg_bit = 1, 3099 .clkr = { 3100 .enable_reg = 0x71010, 3101 .enable_mask = BIT(0), 3102 .hw.init = &(const struct clk_init_data) { 3103 .name = "gcc_gpu_memnoc_gfx_clk", 3104 .ops = &clk_branch2_ops, 3105 }, 3106 }, 3107 }; 3108 3109 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 3110 .halt_reg = 0x71018, 3111 .halt_check = BRANCH_HALT, 3112 .clkr = { 3113 .enable_reg = 0x71018, 3114 .enable_mask = BIT(0), 3115 .hw.init = &(const struct clk_init_data) { 3116 .name = "gcc_gpu_snoc_dvm_gfx_clk", 3117 .ops = &clk_branch2_ops, 3118 }, 3119 }, 3120 }; 3121 3122 static struct clk_branch gcc_pcie0_phy_rchng_clk = { 3123 .halt_reg = 0xa0050, 3124 .halt_check = BRANCH_HALT_VOTED, 3125 .clkr = { 3126 .enable_reg = 0x52010, 3127 .enable_mask = BIT(26), 3128 .hw.init = &(const struct clk_init_data) { 3129 .name = "gcc_pcie0_phy_rchng_clk", 3130 .parent_hws = (const struct clk_hw*[]) { 3131 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 3132 }, 3133 .num_parents = 1, 3134 .flags = CLK_SET_RATE_PARENT, 3135 .ops = &clk_branch2_ops, 3136 }, 3137 }, 3138 }; 3139 3140 static struct clk_branch gcc_pcie1_phy_rchng_clk = { 3141 .halt_reg = 0x2c050, 3142 .halt_check = BRANCH_HALT_VOTED, 3143 .clkr = { 3144 .enable_reg = 0x52020, 3145 .enable_mask = BIT(31), 3146 .hw.init = &(const struct clk_init_data) { 3147 .name = "gcc_pcie1_phy_rchng_clk", 3148 .parent_hws = (const struct clk_hw*[]) { 3149 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, 3150 }, 3151 .num_parents = 1, 3152 .flags = CLK_SET_RATE_PARENT, 3153 .ops = &clk_branch2_ops, 3154 }, 3155 }, 3156 }; 3157 3158 static struct clk_branch gcc_pcie2_phy_rchng_clk = { 3159 .halt_reg = 0x13050, 3160 .halt_check = BRANCH_HALT_VOTED, 3161 .clkr = { 3162 .enable_reg = 0x52020, 3163 .enable_mask = BIT(24), 3164 .hw.init = &(const struct clk_init_data) { 3165 .name = "gcc_pcie2_phy_rchng_clk", 3166 .parent_hws = (const struct clk_hw*[]) { 3167 &gcc_pcie_2_phy_rchng_clk_src.clkr.hw, 3168 }, 3169 .num_parents = 1, 3170 .flags = CLK_SET_RATE_PARENT, 3171 .ops = &clk_branch2_ops, 3172 }, 3173 }, 3174 }; 3175 3176 static struct clk_branch gcc_pcie_0_aux_clk = { 3177 .halt_reg = 0xa0038, 3178 .halt_check = BRANCH_HALT_VOTED, 3179 .clkr = { 3180 .enable_reg = 0x52010, 3181 .enable_mask = BIT(24), 3182 .hw.init = &(const struct clk_init_data) { 3183 .name = "gcc_pcie_0_aux_clk", 3184 .parent_hws = (const struct clk_hw*[]) { 3185 &gcc_pcie_0_aux_clk_src.clkr.hw, 3186 }, 3187 .num_parents = 1, 3188 .flags = CLK_SET_RATE_PARENT, 3189 .ops = &clk_branch2_ops, 3190 }, 3191 }, 3192 }; 3193 3194 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 3195 .halt_reg = 0xa0034, 3196 .halt_check = BRANCH_HALT_VOTED, 3197 .hwcg_reg = 0xa0034, 3198 .hwcg_bit = 1, 3199 .clkr = { 3200 .enable_reg = 0x52010, 3201 .enable_mask = BIT(23), 3202 .hw.init = &(const struct clk_init_data) { 3203 .name = "gcc_pcie_0_cfg_ahb_clk", 3204 .ops = &clk_branch2_ops, 3205 }, 3206 }, 3207 }; 3208 3209 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 3210 .halt_reg = 0xa0028, 3211 .halt_check = BRANCH_HALT_SKIP, 3212 .hwcg_reg = 0xa0028, 3213 .hwcg_bit = 1, 3214 .clkr = { 3215 .enable_reg = 0x52010, 3216 .enable_mask = BIT(22), 3217 .hw.init = &(const struct clk_init_data) { 3218 .name = "gcc_pcie_0_mstr_axi_clk", 3219 .ops = &clk_branch2_ops, 3220 }, 3221 }, 3222 }; 3223 3224 static struct clk_branch gcc_pcie_0_pipe_clk = { 3225 .halt_reg = 0xa0044, 3226 .halt_check = BRANCH_HALT_SKIP, 3227 .clkr = { 3228 .enable_reg = 0x52010, 3229 .enable_mask = BIT(25), 3230 .hw.init = &(const struct clk_init_data) { 3231 .name = "gcc_pcie_0_pipe_clk", 3232 .parent_hws = (const struct clk_hw*[]) { 3233 &gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr.hw, 3234 }, 3235 .num_parents = 1, 3236 .flags = CLK_SET_RATE_PARENT, 3237 .ops = &clk_branch2_ops, 3238 }, 3239 }, 3240 }; 3241 3242 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 3243 .halt_reg = 0xa001c, 3244 .halt_check = BRANCH_HALT_VOTED, 3245 .hwcg_reg = 0xa001c, 3246 .hwcg_bit = 1, 3247 .clkr = { 3248 .enable_reg = 0x52010, 3249 .enable_mask = BIT(21), 3250 .hw.init = &(const struct clk_init_data) { 3251 .name = "gcc_pcie_0_slv_axi_clk", 3252 .ops = &clk_branch2_ops, 3253 }, 3254 }, 3255 }; 3256 3257 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 3258 .halt_reg = 0xa0018, 3259 .halt_check = BRANCH_HALT_VOTED, 3260 .clkr = { 3261 .enable_reg = 0x52010, 3262 .enable_mask = BIT(20), 3263 .hw.init = &(const struct clk_init_data) { 3264 .name = "gcc_pcie_0_slv_q2a_axi_clk", 3265 .ops = &clk_branch2_ops, 3266 }, 3267 }, 3268 }; 3269 3270 static struct clk_branch gcc_pcie_1_aux_clk = { 3271 .halt_reg = 0x2c038, 3272 .halt_check = BRANCH_HALT_VOTED, 3273 .clkr = { 3274 .enable_reg = 0x52020, 3275 .enable_mask = BIT(29), 3276 .hw.init = &(const struct clk_init_data) { 3277 .name = "gcc_pcie_1_aux_clk", 3278 .parent_hws = (const struct clk_hw*[]) { 3279 &gcc_pcie_1_aux_clk_src.clkr.hw, 3280 }, 3281 .num_parents = 1, 3282 .flags = CLK_SET_RATE_PARENT, 3283 .ops = &clk_branch2_ops, 3284 }, 3285 }, 3286 }; 3287 3288 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 3289 .halt_reg = 0x2c034, 3290 .halt_check = BRANCH_HALT_VOTED, 3291 .hwcg_reg = 0x2c034, 3292 .hwcg_bit = 1, 3293 .clkr = { 3294 .enable_reg = 0x52020, 3295 .enable_mask = BIT(28), 3296 .hw.init = &(const struct clk_init_data) { 3297 .name = "gcc_pcie_1_cfg_ahb_clk", 3298 .ops = &clk_branch2_ops, 3299 }, 3300 }, 3301 }; 3302 3303 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 3304 .halt_reg = 0x2c028, 3305 .halt_check = BRANCH_HALT_SKIP, 3306 .hwcg_reg = 0x2c028, 3307 .hwcg_bit = 1, 3308 .clkr = { 3309 .enable_reg = 0x52020, 3310 .enable_mask = BIT(27), 3311 .hw.init = &(const struct clk_init_data) { 3312 .name = "gcc_pcie_1_mstr_axi_clk", 3313 .ops = &clk_branch2_ops, 3314 }, 3315 }, 3316 }; 3317 3318 static struct clk_branch gcc_pcie_1_pipe_clk = { 3319 .halt_reg = 0x2c044, 3320 .halt_check = BRANCH_HALT_SKIP, 3321 .clkr = { 3322 .enable_reg = 0x52020, 3323 .enable_mask = BIT(30), 3324 .hw.init = &(const struct clk_init_data) { 3325 .name = "gcc_pcie_1_pipe_clk", 3326 .parent_hws = (const struct clk_hw*[]) { 3327 &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw, 3328 }, 3329 .num_parents = 1, 3330 .flags = CLK_SET_RATE_PARENT, 3331 .ops = &clk_branch2_ops, 3332 }, 3333 }, 3334 }; 3335 3336 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 3337 .halt_reg = 0x2c01c, 3338 .halt_check = BRANCH_HALT_VOTED, 3339 .hwcg_reg = 0x2c01c, 3340 .hwcg_bit = 1, 3341 .clkr = { 3342 .enable_reg = 0x52020, 3343 .enable_mask = BIT(26), 3344 .hw.init = &(const struct clk_init_data) { 3345 .name = "gcc_pcie_1_slv_axi_clk", 3346 .ops = &clk_branch2_ops, 3347 }, 3348 }, 3349 }; 3350 3351 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 3352 .halt_reg = 0x2c018, 3353 .halt_check = BRANCH_HALT_VOTED, 3354 .clkr = { 3355 .enable_reg = 0x52020, 3356 .enable_mask = BIT(25), 3357 .hw.init = &(const struct clk_init_data) { 3358 .name = "gcc_pcie_1_slv_q2a_axi_clk", 3359 .ops = &clk_branch2_ops, 3360 }, 3361 }, 3362 }; 3363 3364 static struct clk_branch gcc_pcie_2_aux_clk = { 3365 .halt_reg = 0x13038, 3366 .halt_check = BRANCH_HALT_VOTED, 3367 .clkr = { 3368 .enable_reg = 0x52020, 3369 .enable_mask = BIT(22), 3370 .hw.init = &(const struct clk_init_data) { 3371 .name = "gcc_pcie_2_aux_clk", 3372 .parent_hws = (const struct clk_hw*[]) { 3373 &gcc_pcie_2_aux_clk_src.clkr.hw, 3374 }, 3375 .num_parents = 1, 3376 .flags = CLK_SET_RATE_PARENT, 3377 .ops = &clk_branch2_ops, 3378 }, 3379 }, 3380 }; 3381 3382 static struct clk_branch gcc_pcie_2_cfg_ahb_clk = { 3383 .halt_reg = 0x13034, 3384 .halt_check = BRANCH_HALT_VOTED, 3385 .hwcg_reg = 0x13034, 3386 .hwcg_bit = 1, 3387 .clkr = { 3388 .enable_reg = 0x52020, 3389 .enable_mask = BIT(21), 3390 .hw.init = &(const struct clk_init_data) { 3391 .name = "gcc_pcie_2_cfg_ahb_clk", 3392 .ops = &clk_branch2_ops, 3393 }, 3394 }, 3395 }; 3396 3397 static struct clk_branch gcc_pcie_2_mstr_axi_clk = { 3398 .halt_reg = 0x13028, 3399 .halt_check = BRANCH_HALT_SKIP, 3400 .hwcg_reg = 0x13028, 3401 .hwcg_bit = 1, 3402 .clkr = { 3403 .enable_reg = 0x52020, 3404 .enable_mask = BIT(20), 3405 .hw.init = &(const struct clk_init_data) { 3406 .name = "gcc_pcie_2_mstr_axi_clk", 3407 .ops = &clk_branch2_ops, 3408 }, 3409 }, 3410 }; 3411 3412 static struct clk_branch gcc_pcie_2_pipe_clk = { 3413 .halt_reg = 0x13044, 3414 .halt_check = BRANCH_HALT_SKIP, 3415 .clkr = { 3416 .enable_reg = 0x52020, 3417 .enable_mask = BIT(23), 3418 .hw.init = &(const struct clk_init_data) { 3419 .name = "gcc_pcie_2_pipe_clk", 3420 .parent_hws = (const struct clk_hw*[]) { 3421 &gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr.hw, 3422 }, 3423 .num_parents = 1, 3424 .flags = CLK_SET_RATE_PARENT, 3425 .ops = &clk_branch2_ops, 3426 }, 3427 }, 3428 }; 3429 3430 static struct clk_branch gcc_pcie_2_slv_axi_clk = { 3431 .halt_reg = 0x1301c, 3432 .halt_check = BRANCH_HALT_VOTED, 3433 .hwcg_reg = 0x1301c, 3434 .hwcg_bit = 1, 3435 .clkr = { 3436 .enable_reg = 0x52020, 3437 .enable_mask = BIT(19), 3438 .hw.init = &(const struct clk_init_data) { 3439 .name = "gcc_pcie_2_slv_axi_clk", 3440 .ops = &clk_branch2_ops, 3441 }, 3442 }, 3443 }; 3444 3445 static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = { 3446 .halt_reg = 0x13018, 3447 .halt_check = BRANCH_HALT_VOTED, 3448 .clkr = { 3449 .enable_reg = 0x52020, 3450 .enable_mask = BIT(18), 3451 .hw.init = &(const struct clk_init_data) { 3452 .name = "gcc_pcie_2_slv_q2a_axi_clk", 3453 .ops = &clk_branch2_ops, 3454 }, 3455 }, 3456 }; 3457 3458 static struct clk_branch gcc_pcie_3_aux_clk = { 3459 .halt_reg = 0x58038, 3460 .halt_check = BRANCH_HALT_VOTED, 3461 .clkr = { 3462 .enable_reg = 0x52020, 3463 .enable_mask = BIT(1), 3464 .hw.init = &(const struct clk_init_data) { 3465 .name = "gcc_pcie_3_aux_clk", 3466 .parent_hws = (const struct clk_hw*[]) { 3467 &gcc_pcie_3_aux_clk_src.clkr.hw, 3468 }, 3469 .num_parents = 1, 3470 .flags = CLK_SET_RATE_PARENT, 3471 .ops = &clk_branch2_ops, 3472 }, 3473 }, 3474 }; 3475 3476 static struct clk_branch gcc_pcie_3_cfg_ahb_clk = { 3477 .halt_reg = 0x58034, 3478 .halt_check = BRANCH_HALT_VOTED, 3479 .hwcg_reg = 0x58034, 3480 .hwcg_bit = 1, 3481 .clkr = { 3482 .enable_reg = 0x52020, 3483 .enable_mask = BIT(0), 3484 .hw.init = &(const struct clk_init_data) { 3485 .name = "gcc_pcie_3_cfg_ahb_clk", 3486 .ops = &clk_branch2_ops, 3487 }, 3488 }, 3489 }; 3490 3491 static struct clk_branch gcc_pcie_3_mstr_axi_clk = { 3492 .halt_reg = 0x58028, 3493 .halt_check = BRANCH_HALT_SKIP, 3494 .hwcg_reg = 0x58028, 3495 .hwcg_bit = 1, 3496 .clkr = { 3497 .enable_reg = 0x52018, 3498 .enable_mask = BIT(31), 3499 .hw.init = &(const struct clk_init_data) { 3500 .name = "gcc_pcie_3_mstr_axi_clk", 3501 .ops = &clk_branch2_ops, 3502 }, 3503 }, 3504 }; 3505 3506 static struct clk_branch gcc_pcie_3_phy_aux_clk = { 3507 .halt_reg = 0x58044, 3508 .halt_check = BRANCH_HALT_VOTED, 3509 .clkr = { 3510 .enable_reg = 0x52020, 3511 .enable_mask = BIT(2), 3512 .hw.init = &(const struct clk_init_data) { 3513 .name = "gcc_pcie_3_phy_aux_clk", 3514 .ops = &clk_branch2_ops, 3515 }, 3516 }, 3517 }; 3518 3519 static struct clk_branch gcc_pcie_3_phy_rchng_clk = { 3520 .halt_reg = 0x5805c, 3521 .halt_check = BRANCH_HALT_VOTED, 3522 .clkr = { 3523 .enable_reg = 0x52020, 3524 .enable_mask = BIT(4), 3525 .hw.init = &(const struct clk_init_data) { 3526 .name = "gcc_pcie_3_phy_rchng_clk", 3527 .parent_hws = (const struct clk_hw*[]) { 3528 &gcc_pcie_3_phy_rchng_clk_src.clkr.hw, 3529 }, 3530 .num_parents = 1, 3531 .flags = CLK_SET_RATE_PARENT, 3532 .ops = &clk_branch2_ops, 3533 }, 3534 }, 3535 }; 3536 3537 static struct clk_branch gcc_pcie_3_pipe_clk = { 3538 .halt_reg = 0x58050, 3539 .halt_check = BRANCH_HALT_SKIP, 3540 .clkr = { 3541 .enable_reg = 0x52020, 3542 .enable_mask = BIT(3), 3543 .hw.init = &(const struct clk_init_data) { 3544 .name = "gcc_pcie_3_pipe_clk", 3545 .ops = &clk_branch2_ops, 3546 }, 3547 }, 3548 }; 3549 3550 static struct clk_branch gcc_pcie_3_pipediv2_clk = { 3551 .halt_reg = 0x58060, 3552 .halt_check = BRANCH_HALT_SKIP, 3553 .clkr = { 3554 .enable_reg = 0x52020, 3555 .enable_mask = BIT(5), 3556 .hw.init = &(const struct clk_init_data) { 3557 .name = "gcc_pcie_3_pipediv2_clk", 3558 .parent_hws = (const struct clk_hw*[]) { 3559 &gcc_pcie_3_pipe_div_clk_src.clkr.hw, 3560 }, 3561 .num_parents = 1, 3562 .flags = CLK_SET_RATE_PARENT, 3563 .ops = &clk_branch2_ops, 3564 }, 3565 }, 3566 }; 3567 3568 static struct clk_branch gcc_pcie_3_slv_axi_clk = { 3569 .halt_reg = 0x5801c, 3570 .halt_check = BRANCH_HALT_VOTED, 3571 .hwcg_reg = 0x5801c, 3572 .hwcg_bit = 1, 3573 .clkr = { 3574 .enable_reg = 0x52018, 3575 .enable_mask = BIT(30), 3576 .hw.init = &(const struct clk_init_data) { 3577 .name = "gcc_pcie_3_slv_axi_clk", 3578 .ops = &clk_branch2_ops, 3579 }, 3580 }, 3581 }; 3582 3583 static struct clk_branch gcc_pcie_3_slv_q2a_axi_clk = { 3584 .halt_reg = 0x58018, 3585 .halt_check = BRANCH_HALT_VOTED, 3586 .clkr = { 3587 .enable_reg = 0x52018, 3588 .enable_mask = BIT(29), 3589 .hw.init = &(const struct clk_init_data) { 3590 .name = "gcc_pcie_3_slv_q2a_axi_clk", 3591 .ops = &clk_branch2_ops, 3592 }, 3593 }, 3594 }; 3595 3596 static struct clk_branch gcc_pcie_4_aux_clk = { 3597 .halt_reg = 0x6b038, 3598 .halt_check = BRANCH_HALT_VOTED, 3599 .clkr = { 3600 .enable_reg = 0x52008, 3601 .enable_mask = BIT(3), 3602 .hw.init = &(const struct clk_init_data) { 3603 .name = "gcc_pcie_4_aux_clk", 3604 .parent_hws = (const struct clk_hw*[]) { 3605 &gcc_pcie_4_aux_clk_src.clkr.hw, 3606 }, 3607 .num_parents = 1, 3608 .flags = CLK_SET_RATE_PARENT, 3609 .ops = &clk_branch2_ops, 3610 }, 3611 }, 3612 }; 3613 3614 static struct clk_branch gcc_pcie_4_cfg_ahb_clk = { 3615 .halt_reg = 0x6b034, 3616 .halt_check = BRANCH_HALT_VOTED, 3617 .hwcg_reg = 0x6b034, 3618 .hwcg_bit = 1, 3619 .clkr = { 3620 .enable_reg = 0x52008, 3621 .enable_mask = BIT(2), 3622 .hw.init = &(const struct clk_init_data) { 3623 .name = "gcc_pcie_4_cfg_ahb_clk", 3624 .ops = &clk_branch2_ops, 3625 }, 3626 }, 3627 }; 3628 3629 static struct clk_branch gcc_pcie_4_mstr_axi_clk = { 3630 .halt_reg = 0x6b028, 3631 .halt_check = BRANCH_HALT_SKIP, 3632 .hwcg_reg = 0x6b028, 3633 .hwcg_bit = 1, 3634 .clkr = { 3635 .enable_reg = 0x52008, 3636 .enable_mask = BIT(1), 3637 .hw.init = &(const struct clk_init_data) { 3638 .name = "gcc_pcie_4_mstr_axi_clk", 3639 .ops = &clk_branch2_ops, 3640 }, 3641 }, 3642 }; 3643 3644 static struct clk_branch gcc_pcie_4_phy_rchng_clk = { 3645 .halt_reg = 0x6b050, 3646 .halt_check = BRANCH_HALT_VOTED, 3647 .clkr = { 3648 .enable_reg = 0x52000, 3649 .enable_mask = BIT(22), 3650 .hw.init = &(const struct clk_init_data) { 3651 .name = "gcc_pcie_4_phy_rchng_clk", 3652 .parent_hws = (const struct clk_hw*[]) { 3653 &gcc_pcie_4_phy_rchng_clk_src.clkr.hw, 3654 }, 3655 .num_parents = 1, 3656 .flags = CLK_SET_RATE_PARENT, 3657 .ops = &clk_branch2_ops, 3658 }, 3659 }, 3660 }; 3661 3662 static struct clk_branch gcc_pcie_4_pipe_clk = { 3663 .halt_reg = 0x6b044, 3664 .halt_check = BRANCH_HALT_SKIP, 3665 .clkr = { 3666 .enable_reg = 0x52008, 3667 .enable_mask = BIT(4), 3668 .hw.init = &(const struct clk_init_data) { 3669 .name = "gcc_pcie_4_pipe_clk", 3670 .ops = &clk_branch2_ops, 3671 }, 3672 }, 3673 }; 3674 3675 static struct clk_branch gcc_pcie_4_pipediv2_clk = { 3676 .halt_reg = 0x6b054, 3677 .halt_check = BRANCH_HALT_SKIP, 3678 .clkr = { 3679 .enable_reg = 0x52010, 3680 .enable_mask = BIT(27), 3681 .hw.init = &(const struct clk_init_data) { 3682 .name = "gcc_pcie_4_pipediv2_clk", 3683 .parent_hws = (const struct clk_hw*[]) { 3684 &gcc_pcie_4_pipe_div_clk_src.clkr.hw, 3685 }, 3686 .num_parents = 1, 3687 .flags = CLK_SET_RATE_PARENT, 3688 .ops = &clk_branch2_ops, 3689 }, 3690 }, 3691 }; 3692 3693 static struct clk_branch gcc_pcie_4_slv_axi_clk = { 3694 .halt_reg = 0x6b01c, 3695 .halt_check = BRANCH_HALT_VOTED, 3696 .hwcg_reg = 0x6b01c, 3697 .hwcg_bit = 1, 3698 .clkr = { 3699 .enable_reg = 0x52008, 3700 .enable_mask = BIT(0), 3701 .hw.init = &(const struct clk_init_data) { 3702 .name = "gcc_pcie_4_slv_axi_clk", 3703 .ops = &clk_branch2_ops, 3704 }, 3705 }, 3706 }; 3707 3708 static struct clk_branch gcc_pcie_4_slv_q2a_axi_clk = { 3709 .halt_reg = 0x6b018, 3710 .halt_check = BRANCH_HALT_VOTED, 3711 .clkr = { 3712 .enable_reg = 0x52008, 3713 .enable_mask = BIT(5), 3714 .hw.init = &(const struct clk_init_data) { 3715 .name = "gcc_pcie_4_slv_q2a_axi_clk", 3716 .ops = &clk_branch2_ops, 3717 }, 3718 }, 3719 }; 3720 3721 static struct clk_branch gcc_pcie_5_aux_clk = { 3722 .halt_reg = 0x2f038, 3723 .halt_check = BRANCH_HALT_VOTED, 3724 .clkr = { 3725 .enable_reg = 0x52018, 3726 .enable_mask = BIT(16), 3727 .hw.init = &(const struct clk_init_data) { 3728 .name = "gcc_pcie_5_aux_clk", 3729 .parent_hws = (const struct clk_hw*[]) { 3730 &gcc_pcie_5_aux_clk_src.clkr.hw, 3731 }, 3732 .num_parents = 1, 3733 .flags = CLK_SET_RATE_PARENT, 3734 .ops = &clk_branch2_ops, 3735 }, 3736 }, 3737 }; 3738 3739 static struct clk_branch gcc_pcie_5_cfg_ahb_clk = { 3740 .halt_reg = 0x2f034, 3741 .halt_check = BRANCH_HALT_VOTED, 3742 .hwcg_reg = 0x2f034, 3743 .hwcg_bit = 1, 3744 .clkr = { 3745 .enable_reg = 0x52018, 3746 .enable_mask = BIT(15), 3747 .hw.init = &(const struct clk_init_data) { 3748 .name = "gcc_pcie_5_cfg_ahb_clk", 3749 .ops = &clk_branch2_ops, 3750 }, 3751 }, 3752 }; 3753 3754 static struct clk_branch gcc_pcie_5_mstr_axi_clk = { 3755 .halt_reg = 0x2f028, 3756 .halt_check = BRANCH_HALT_SKIP, 3757 .hwcg_reg = 0x2f028, 3758 .hwcg_bit = 1, 3759 .clkr = { 3760 .enable_reg = 0x52018, 3761 .enable_mask = BIT(14), 3762 .hw.init = &(const struct clk_init_data) { 3763 .name = "gcc_pcie_5_mstr_axi_clk", 3764 .ops = &clk_branch2_ops, 3765 }, 3766 }, 3767 }; 3768 3769 static struct clk_branch gcc_pcie_5_phy_rchng_clk = { 3770 .halt_reg = 0x2f050, 3771 .halt_check = BRANCH_HALT_VOTED, 3772 .clkr = { 3773 .enable_reg = 0x52018, 3774 .enable_mask = BIT(18), 3775 .hw.init = &(const struct clk_init_data) { 3776 .name = "gcc_pcie_5_phy_rchng_clk", 3777 .parent_hws = (const struct clk_hw*[]) { 3778 &gcc_pcie_5_phy_rchng_clk_src.clkr.hw, 3779 }, 3780 .num_parents = 1, 3781 .flags = CLK_SET_RATE_PARENT, 3782 .ops = &clk_branch2_ops, 3783 }, 3784 }, 3785 }; 3786 3787 static struct clk_branch gcc_pcie_5_pipe_clk = { 3788 .halt_reg = 0x2f044, 3789 .halt_check = BRANCH_HALT_SKIP, 3790 .clkr = { 3791 .enable_reg = 0x52018, 3792 .enable_mask = BIT(17), 3793 .hw.init = &(const struct clk_init_data) { 3794 .name = "gcc_pcie_5_pipe_clk", 3795 .ops = &clk_branch2_ops, 3796 }, 3797 }, 3798 }; 3799 3800 static struct clk_branch gcc_pcie_5_pipediv2_clk = { 3801 .halt_reg = 0x2f054, 3802 .halt_check = BRANCH_HALT_SKIP, 3803 .clkr = { 3804 .enable_reg = 0x52018, 3805 .enable_mask = BIT(19), 3806 .hw.init = &(const struct clk_init_data) { 3807 .name = "gcc_pcie_5_pipediv2_clk", 3808 .parent_hws = (const struct clk_hw*[]) { 3809 &gcc_pcie_5_pipe_div_clk_src.clkr.hw, 3810 }, 3811 .num_parents = 1, 3812 .flags = CLK_SET_RATE_PARENT, 3813 .ops = &clk_branch2_ops, 3814 }, 3815 }, 3816 }; 3817 3818 static struct clk_branch gcc_pcie_5_slv_axi_clk = { 3819 .halt_reg = 0x2f01c, 3820 .halt_check = BRANCH_HALT_VOTED, 3821 .hwcg_reg = 0x2f01c, 3822 .hwcg_bit = 1, 3823 .clkr = { 3824 .enable_reg = 0x52018, 3825 .enable_mask = BIT(13), 3826 .hw.init = &(const struct clk_init_data) { 3827 .name = "gcc_pcie_5_slv_axi_clk", 3828 .ops = &clk_branch2_ops, 3829 }, 3830 }, 3831 }; 3832 3833 static struct clk_branch gcc_pcie_5_slv_q2a_axi_clk = { 3834 .halt_reg = 0x2f018, 3835 .halt_check = BRANCH_HALT_VOTED, 3836 .clkr = { 3837 .enable_reg = 0x52018, 3838 .enable_mask = BIT(12), 3839 .hw.init = &(const struct clk_init_data) { 3840 .name = "gcc_pcie_5_slv_q2a_axi_clk", 3841 .ops = &clk_branch2_ops, 3842 }, 3843 }, 3844 }; 3845 3846 static struct clk_branch gcc_pcie_6a_aux_clk = { 3847 .halt_reg = 0x31038, 3848 .halt_check = BRANCH_HALT_VOTED, 3849 .clkr = { 3850 .enable_reg = 0x52018, 3851 .enable_mask = BIT(24), 3852 .hw.init = &(const struct clk_init_data) { 3853 .name = "gcc_pcie_6a_aux_clk", 3854 .parent_hws = (const struct clk_hw*[]) { 3855 &gcc_pcie_6a_aux_clk_src.clkr.hw, 3856 }, 3857 .num_parents = 1, 3858 .flags = CLK_SET_RATE_PARENT, 3859 .ops = &clk_branch2_ops, 3860 }, 3861 }, 3862 }; 3863 3864 static struct clk_branch gcc_pcie_6a_cfg_ahb_clk = { 3865 .halt_reg = 0x31034, 3866 .halt_check = BRANCH_HALT_VOTED, 3867 .hwcg_reg = 0x31034, 3868 .hwcg_bit = 1, 3869 .clkr = { 3870 .enable_reg = 0x52018, 3871 .enable_mask = BIT(23), 3872 .hw.init = &(const struct clk_init_data) { 3873 .name = "gcc_pcie_6a_cfg_ahb_clk", 3874 .ops = &clk_branch2_ops, 3875 }, 3876 }, 3877 }; 3878 3879 static struct clk_branch gcc_pcie_6a_mstr_axi_clk = { 3880 .halt_reg = 0x31028, 3881 .halt_check = BRANCH_HALT_SKIP, 3882 .hwcg_reg = 0x31028, 3883 .hwcg_bit = 1, 3884 .clkr = { 3885 .enable_reg = 0x52018, 3886 .enable_mask = BIT(22), 3887 .hw.init = &(const struct clk_init_data) { 3888 .name = "gcc_pcie_6a_mstr_axi_clk", 3889 .ops = &clk_branch2_ops, 3890 }, 3891 }, 3892 }; 3893 3894 static struct clk_branch gcc_pcie_6a_phy_aux_clk = { 3895 .halt_reg = 0x31044, 3896 .halt_check = BRANCH_HALT_VOTED, 3897 .clkr = { 3898 .enable_reg = 0x52018, 3899 .enable_mask = BIT(25), 3900 .hw.init = &(const struct clk_init_data) { 3901 .name = "gcc_pcie_6a_phy_aux_clk", 3902 .ops = &clk_branch2_ops, 3903 }, 3904 }, 3905 }; 3906 3907 static struct clk_branch gcc_pcie_6a_phy_rchng_clk = { 3908 .halt_reg = 0x3105c, 3909 .halt_check = BRANCH_HALT_VOTED, 3910 .clkr = { 3911 .enable_reg = 0x52018, 3912 .enable_mask = BIT(27), 3913 .hw.init = &(const struct clk_init_data) { 3914 .name = "gcc_pcie_6a_phy_rchng_clk", 3915 .parent_hws = (const struct clk_hw*[]) { 3916 &gcc_pcie_6a_phy_rchng_clk_src.clkr.hw, 3917 }, 3918 .num_parents = 1, 3919 .flags = CLK_SET_RATE_PARENT, 3920 .ops = &clk_branch2_ops, 3921 }, 3922 }, 3923 }; 3924 3925 static struct clk_branch gcc_pcie_6a_pipe_clk = { 3926 .halt_reg = 0x31050, 3927 .halt_check = BRANCH_HALT_SKIP, 3928 .clkr = { 3929 .enable_reg = 0x52018, 3930 .enable_mask = BIT(26), 3931 .hw.init = &(const struct clk_init_data) { 3932 .name = "gcc_pcie_6a_pipe_clk", 3933 .ops = &clk_branch2_ops, 3934 }, 3935 }, 3936 }; 3937 3938 static struct clk_branch gcc_pcie_6a_pipediv2_clk = { 3939 .halt_reg = 0x31060, 3940 .halt_check = BRANCH_HALT_SKIP, 3941 .clkr = { 3942 .enable_reg = 0x52018, 3943 .enable_mask = BIT(28), 3944 .hw.init = &(const struct clk_init_data) { 3945 .name = "gcc_pcie_6a_pipediv2_clk", 3946 .parent_hws = (const struct clk_hw*[]) { 3947 &gcc_pcie_6a_pipe_div_clk_src.clkr.hw, 3948 }, 3949 .num_parents = 1, 3950 .flags = CLK_SET_RATE_PARENT, 3951 .ops = &clk_branch2_ops, 3952 }, 3953 }, 3954 }; 3955 3956 static struct clk_branch gcc_pcie_6a_slv_axi_clk = { 3957 .halt_reg = 0x3101c, 3958 .halt_check = BRANCH_HALT_VOTED, 3959 .hwcg_reg = 0x3101c, 3960 .hwcg_bit = 1, 3961 .clkr = { 3962 .enable_reg = 0x52018, 3963 .enable_mask = BIT(21), 3964 .hw.init = &(const struct clk_init_data) { 3965 .name = "gcc_pcie_6a_slv_axi_clk", 3966 .ops = &clk_branch2_ops, 3967 }, 3968 }, 3969 }; 3970 3971 static struct clk_branch gcc_pcie_6a_slv_q2a_axi_clk = { 3972 .halt_reg = 0x31018, 3973 .halt_check = BRANCH_HALT_VOTED, 3974 .clkr = { 3975 .enable_reg = 0x52018, 3976 .enable_mask = BIT(20), 3977 .hw.init = &(const struct clk_init_data) { 3978 .name = "gcc_pcie_6a_slv_q2a_axi_clk", 3979 .ops = &clk_branch2_ops, 3980 }, 3981 }, 3982 }; 3983 3984 static struct clk_branch gcc_pcie_6b_aux_clk = { 3985 .halt_reg = 0x8d038, 3986 .halt_check = BRANCH_HALT_VOTED, 3987 .clkr = { 3988 .enable_reg = 0x52000, 3989 .enable_mask = BIT(29), 3990 .hw.init = &(const struct clk_init_data) { 3991 .name = "gcc_pcie_6b_aux_clk", 3992 .parent_hws = (const struct clk_hw*[]) { 3993 &gcc_pcie_6b_aux_clk_src.clkr.hw, 3994 }, 3995 .num_parents = 1, 3996 .flags = CLK_SET_RATE_PARENT, 3997 .ops = &clk_branch2_ops, 3998 }, 3999 }, 4000 }; 4001 4002 static struct clk_branch gcc_pcie_6b_cfg_ahb_clk = { 4003 .halt_reg = 0x8d034, 4004 .halt_check = BRANCH_HALT_VOTED, 4005 .hwcg_reg = 0x8d034, 4006 .hwcg_bit = 1, 4007 .clkr = { 4008 .enable_reg = 0x52000, 4009 .enable_mask = BIT(28), 4010 .hw.init = &(const struct clk_init_data) { 4011 .name = "gcc_pcie_6b_cfg_ahb_clk", 4012 .ops = &clk_branch2_ops, 4013 }, 4014 }, 4015 }; 4016 4017 static struct clk_branch gcc_pcie_6b_mstr_axi_clk = { 4018 .halt_reg = 0x8d028, 4019 .halt_check = BRANCH_HALT_SKIP, 4020 .hwcg_reg = 0x8d028, 4021 .hwcg_bit = 1, 4022 .clkr = { 4023 .enable_reg = 0x52000, 4024 .enable_mask = BIT(27), 4025 .hw.init = &(const struct clk_init_data) { 4026 .name = "gcc_pcie_6b_mstr_axi_clk", 4027 .ops = &clk_branch2_ops, 4028 }, 4029 }, 4030 }; 4031 4032 static struct clk_branch gcc_pcie_6b_phy_aux_clk = { 4033 .halt_reg = 0x8d044, 4034 .halt_check = BRANCH_HALT_VOTED, 4035 .clkr = { 4036 .enable_reg = 0x52000, 4037 .enable_mask = BIT(24), 4038 .hw.init = &(const struct clk_init_data) { 4039 .name = "gcc_pcie_6b_phy_aux_clk", 4040 .ops = &clk_branch2_ops, 4041 }, 4042 }, 4043 }; 4044 4045 static struct clk_branch gcc_pcie_6b_phy_rchng_clk = { 4046 .halt_reg = 0x8d05c, 4047 .halt_check = BRANCH_HALT_VOTED, 4048 .clkr = { 4049 .enable_reg = 0x52000, 4050 .enable_mask = BIT(23), 4051 .hw.init = &(const struct clk_init_data) { 4052 .name = "gcc_pcie_6b_phy_rchng_clk", 4053 .parent_hws = (const struct clk_hw*[]) { 4054 &gcc_pcie_6b_phy_rchng_clk_src.clkr.hw, 4055 }, 4056 .num_parents = 1, 4057 .flags = CLK_SET_RATE_PARENT, 4058 .ops = &clk_branch2_ops, 4059 }, 4060 }, 4061 }; 4062 4063 static struct clk_branch gcc_pcie_6b_pipe_clk = { 4064 .halt_reg = 0x8d050, 4065 .halt_check = BRANCH_HALT_SKIP, 4066 .clkr = { 4067 .enable_reg = 0x52000, 4068 .enable_mask = BIT(30), 4069 .hw.init = &(const struct clk_init_data) { 4070 .name = "gcc_pcie_6b_pipe_clk", 4071 .ops = &clk_branch2_ops, 4072 }, 4073 }, 4074 }; 4075 4076 static struct clk_branch gcc_pcie_6b_pipediv2_clk = { 4077 .halt_reg = 0x8d060, 4078 .halt_check = BRANCH_HALT_SKIP, 4079 .clkr = { 4080 .enable_reg = 0x52010, 4081 .enable_mask = BIT(28), 4082 .hw.init = &(const struct clk_init_data) { 4083 .name = "gcc_pcie_6b_pipediv2_clk", 4084 .parent_hws = (const struct clk_hw*[]) { 4085 &gcc_pcie_6b_pipe_div_clk_src.clkr.hw, 4086 }, 4087 .num_parents = 1, 4088 .flags = CLK_SET_RATE_PARENT, 4089 .ops = &clk_branch2_ops, 4090 }, 4091 }, 4092 }; 4093 4094 static struct clk_branch gcc_pcie_6b_slv_axi_clk = { 4095 .halt_reg = 0x8d01c, 4096 .halt_check = BRANCH_HALT_VOTED, 4097 .hwcg_reg = 0x8d01c, 4098 .hwcg_bit = 1, 4099 .clkr = { 4100 .enable_reg = 0x52000, 4101 .enable_mask = BIT(26), 4102 .hw.init = &(const struct clk_init_data) { 4103 .name = "gcc_pcie_6b_slv_axi_clk", 4104 .ops = &clk_branch2_ops, 4105 }, 4106 }, 4107 }; 4108 4109 static struct clk_branch gcc_pcie_6b_slv_q2a_axi_clk = { 4110 .halt_reg = 0x8d018, 4111 .halt_check = BRANCH_HALT_VOTED, 4112 .clkr = { 4113 .enable_reg = 0x52000, 4114 .enable_mask = BIT(25), 4115 .hw.init = &(const struct clk_init_data) { 4116 .name = "gcc_pcie_6b_slv_q2a_axi_clk", 4117 .ops = &clk_branch2_ops, 4118 }, 4119 }, 4120 }; 4121 4122 static struct clk_branch gcc_pcie_rscc_ahb_clk = { 4123 .halt_reg = 0xa4008, 4124 .halt_check = BRANCH_HALT_VOTED, 4125 .hwcg_reg = 0xa4008, 4126 .hwcg_bit = 1, 4127 .clkr = { 4128 .enable_reg = 0x52028, 4129 .enable_mask = BIT(18), 4130 .hw.init = &(const struct clk_init_data) { 4131 .name = "gcc_pcie_rscc_ahb_clk", 4132 .ops = &clk_branch2_ops, 4133 }, 4134 }, 4135 }; 4136 4137 static struct clk_branch gcc_pcie_rscc_xo_clk = { 4138 .halt_reg = 0xa4004, 4139 .halt_check = BRANCH_HALT_VOTED, 4140 .clkr = { 4141 .enable_reg = 0x52028, 4142 .enable_mask = BIT(17), 4143 .hw.init = &(const struct clk_init_data) { 4144 .name = "gcc_pcie_rscc_xo_clk", 4145 .parent_hws = (const struct clk_hw*[]) { 4146 &gcc_pcie_rscc_xo_clk_src.clkr.hw, 4147 }, 4148 .num_parents = 1, 4149 .flags = CLK_SET_RATE_PARENT, 4150 .ops = &clk_branch2_ops, 4151 }, 4152 }, 4153 }; 4154 4155 static struct clk_branch gcc_pdm2_clk = { 4156 .halt_reg = 0x3300c, 4157 .halt_check = BRANCH_HALT, 4158 .clkr = { 4159 .enable_reg = 0x3300c, 4160 .enable_mask = BIT(0), 4161 .hw.init = &(const struct clk_init_data) { 4162 .name = "gcc_pdm2_clk", 4163 .parent_hws = (const struct clk_hw*[]) { 4164 &gcc_pdm2_clk_src.clkr.hw, 4165 }, 4166 .num_parents = 1, 4167 .flags = CLK_SET_RATE_PARENT, 4168 .ops = &clk_branch2_ops, 4169 }, 4170 }, 4171 }; 4172 4173 static struct clk_branch gcc_pdm_ahb_clk = { 4174 .halt_reg = 0x33004, 4175 .halt_check = BRANCH_HALT_VOTED, 4176 .hwcg_reg = 0x33004, 4177 .hwcg_bit = 1, 4178 .clkr = { 4179 .enable_reg = 0x33004, 4180 .enable_mask = BIT(0), 4181 .hw.init = &(const struct clk_init_data) { 4182 .name = "gcc_pdm_ahb_clk", 4183 .ops = &clk_branch2_ops, 4184 }, 4185 }, 4186 }; 4187 4188 static struct clk_branch gcc_pdm_xo4_clk = { 4189 .halt_reg = 0x33008, 4190 .halt_check = BRANCH_HALT, 4191 .clkr = { 4192 .enable_reg = 0x33008, 4193 .enable_mask = BIT(0), 4194 .hw.init = &(const struct clk_init_data) { 4195 .name = "gcc_pdm_xo4_clk", 4196 .ops = &clk_branch2_ops, 4197 }, 4198 }, 4199 }; 4200 4201 static struct clk_branch gcc_qmip_av1e_ahb_clk = { 4202 .halt_reg = 0x4a018, 4203 .halt_check = BRANCH_HALT_VOTED, 4204 .hwcg_reg = 0x4a018, 4205 .hwcg_bit = 1, 4206 .clkr = { 4207 .enable_reg = 0x4a018, 4208 .enable_mask = BIT(0), 4209 .hw.init = &(const struct clk_init_data) { 4210 .name = "gcc_qmip_av1e_ahb_clk", 4211 .ops = &clk_branch2_ops, 4212 }, 4213 }, 4214 }; 4215 4216 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 4217 .halt_reg = 0x26008, 4218 .halt_check = BRANCH_HALT_VOTED, 4219 .hwcg_reg = 0x26008, 4220 .hwcg_bit = 1, 4221 .clkr = { 4222 .enable_reg = 0x26008, 4223 .enable_mask = BIT(0), 4224 .hw.init = &(const struct clk_init_data) { 4225 .name = "gcc_qmip_camera_nrt_ahb_clk", 4226 .ops = &clk_branch2_ops, 4227 }, 4228 }, 4229 }; 4230 4231 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 4232 .halt_reg = 0x2600c, 4233 .halt_check = BRANCH_HALT_VOTED, 4234 .hwcg_reg = 0x2600c, 4235 .hwcg_bit = 1, 4236 .clkr = { 4237 .enable_reg = 0x2600c, 4238 .enable_mask = BIT(0), 4239 .hw.init = &(const struct clk_init_data) { 4240 .name = "gcc_qmip_camera_rt_ahb_clk", 4241 .ops = &clk_branch2_ops, 4242 }, 4243 }, 4244 }; 4245 4246 static struct clk_branch gcc_qmip_disp_ahb_clk = { 4247 .halt_reg = 0x27008, 4248 .halt_check = BRANCH_HALT_VOTED, 4249 .hwcg_reg = 0x27008, 4250 .hwcg_bit = 1, 4251 .clkr = { 4252 .enable_reg = 0x27008, 4253 .enable_mask = BIT(0), 4254 .hw.init = &(const struct clk_init_data) { 4255 .name = "gcc_qmip_disp_ahb_clk", 4256 .ops = &clk_branch2_ops, 4257 }, 4258 }, 4259 }; 4260 4261 static struct clk_branch gcc_qmip_gpu_ahb_clk = { 4262 .halt_reg = 0x71008, 4263 .halt_check = BRANCH_HALT_VOTED, 4264 .hwcg_reg = 0x71008, 4265 .hwcg_bit = 1, 4266 .clkr = { 4267 .enable_reg = 0x71008, 4268 .enable_mask = BIT(0), 4269 .hw.init = &(const struct clk_init_data) { 4270 .name = "gcc_qmip_gpu_ahb_clk", 4271 .ops = &clk_branch2_ops, 4272 }, 4273 }, 4274 }; 4275 4276 static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = { 4277 .halt_reg = 0x32014, 4278 .halt_check = BRANCH_HALT_VOTED, 4279 .hwcg_reg = 0x32014, 4280 .hwcg_bit = 1, 4281 .clkr = { 4282 .enable_reg = 0x32014, 4283 .enable_mask = BIT(0), 4284 .hw.init = &(const struct clk_init_data) { 4285 .name = "gcc_qmip_video_cv_cpu_ahb_clk", 4286 .ops = &clk_branch2_ops, 4287 }, 4288 }, 4289 }; 4290 4291 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 4292 .halt_reg = 0x32008, 4293 .halt_check = BRANCH_HALT_VOTED, 4294 .hwcg_reg = 0x32008, 4295 .hwcg_bit = 1, 4296 .clkr = { 4297 .enable_reg = 0x32008, 4298 .enable_mask = BIT(0), 4299 .hw.init = &(const struct clk_init_data) { 4300 .name = "gcc_qmip_video_cvp_ahb_clk", 4301 .ops = &clk_branch2_ops, 4302 }, 4303 }, 4304 }; 4305 4306 static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = { 4307 .halt_reg = 0x32010, 4308 .halt_check = BRANCH_HALT_VOTED, 4309 .hwcg_reg = 0x32010, 4310 .hwcg_bit = 1, 4311 .clkr = { 4312 .enable_reg = 0x32010, 4313 .enable_mask = BIT(0), 4314 .hw.init = &(const struct clk_init_data) { 4315 .name = "gcc_qmip_video_v_cpu_ahb_clk", 4316 .ops = &clk_branch2_ops, 4317 }, 4318 }, 4319 }; 4320 4321 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 4322 .halt_reg = 0x3200c, 4323 .halt_check = BRANCH_HALT_VOTED, 4324 .hwcg_reg = 0x3200c, 4325 .hwcg_bit = 1, 4326 .clkr = { 4327 .enable_reg = 0x3200c, 4328 .enable_mask = BIT(0), 4329 .hw.init = &(const struct clk_init_data) { 4330 .name = "gcc_qmip_video_vcodec_ahb_clk", 4331 .ops = &clk_branch2_ops, 4332 }, 4333 }, 4334 }; 4335 4336 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 4337 .halt_reg = 0x23018, 4338 .halt_check = BRANCH_HALT_VOTED, 4339 .clkr = { 4340 .enable_reg = 0x52020, 4341 .enable_mask = BIT(9), 4342 .hw.init = &(const struct clk_init_data) { 4343 .name = "gcc_qupv3_wrap0_core_2x_clk", 4344 .ops = &clk_branch2_ops, 4345 }, 4346 }, 4347 }; 4348 4349 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 4350 .halt_reg = 0x23008, 4351 .halt_check = BRANCH_HALT_VOTED, 4352 .clkr = { 4353 .enable_reg = 0x52020, 4354 .enable_mask = BIT(8), 4355 .hw.init = &(const struct clk_init_data) { 4356 .name = "gcc_qupv3_wrap0_core_clk", 4357 .ops = &clk_branch2_ops, 4358 }, 4359 }, 4360 }; 4361 4362 static struct clk_branch gcc_qupv3_wrap0_qspi_s2_clk = { 4363 .halt_reg = 0x42280, 4364 .halt_check = BRANCH_HALT_VOTED, 4365 .clkr = { 4366 .enable_reg = 0x52028, 4367 .enable_mask = BIT(2), 4368 .hw.init = &(const struct clk_init_data) { 4369 .name = "gcc_qupv3_wrap0_qspi_s2_clk", 4370 .parent_hws = (const struct clk_hw*[]) { 4371 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 4372 }, 4373 .num_parents = 1, 4374 .flags = CLK_SET_RATE_PARENT, 4375 .ops = &clk_branch2_ops, 4376 }, 4377 }, 4378 }; 4379 4380 static struct clk_branch gcc_qupv3_wrap0_qspi_s3_clk = { 4381 .halt_reg = 0x423c0, 4382 .halt_check = BRANCH_HALT_VOTED, 4383 .clkr = { 4384 .enable_reg = 0x52028, 4385 .enable_mask = BIT(3), 4386 .hw.init = &(const struct clk_init_data) { 4387 .name = "gcc_qupv3_wrap0_qspi_s3_clk", 4388 .parent_hws = (const struct clk_hw*[]) { 4389 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 4390 }, 4391 .num_parents = 1, 4392 .flags = CLK_SET_RATE_PARENT, 4393 .ops = &clk_branch2_ops, 4394 }, 4395 }, 4396 }; 4397 4398 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 4399 .halt_reg = 0x42004, 4400 .halt_check = BRANCH_HALT_VOTED, 4401 .clkr = { 4402 .enable_reg = 0x52020, 4403 .enable_mask = BIT(10), 4404 .hw.init = &(const struct clk_init_data) { 4405 .name = "gcc_qupv3_wrap0_s0_clk", 4406 .parent_hws = (const struct clk_hw*[]) { 4407 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 4408 }, 4409 .num_parents = 1, 4410 .flags = CLK_SET_RATE_PARENT, 4411 .ops = &clk_branch2_ops, 4412 }, 4413 }, 4414 }; 4415 4416 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 4417 .halt_reg = 0x4213c, 4418 .halt_check = BRANCH_HALT_VOTED, 4419 .clkr = { 4420 .enable_reg = 0x52020, 4421 .enable_mask = BIT(11), 4422 .hw.init = &(const struct clk_init_data) { 4423 .name = "gcc_qupv3_wrap0_s1_clk", 4424 .parent_hws = (const struct clk_hw*[]) { 4425 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 4426 }, 4427 .num_parents = 1, 4428 .flags = CLK_SET_RATE_PARENT, 4429 .ops = &clk_branch2_ops, 4430 }, 4431 }, 4432 }; 4433 4434 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 4435 .halt_reg = 0x42274, 4436 .halt_check = BRANCH_HALT_VOTED, 4437 .clkr = { 4438 .enable_reg = 0x52020, 4439 .enable_mask = BIT(12), 4440 .hw.init = &(const struct clk_init_data) { 4441 .name = "gcc_qupv3_wrap0_s2_clk", 4442 .parent_hws = (const struct clk_hw*[]) { 4443 &gcc_qupv3_wrap0_s2_div_clk_src.clkr.hw, 4444 }, 4445 .num_parents = 1, 4446 .flags = CLK_SET_RATE_PARENT, 4447 .ops = &clk_branch2_ops, 4448 }, 4449 }, 4450 }; 4451 4452 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 4453 .halt_reg = 0x423b4, 4454 .halt_check = BRANCH_HALT_VOTED, 4455 .clkr = { 4456 .enable_reg = 0x52020, 4457 .enable_mask = BIT(13), 4458 .hw.init = &(const struct clk_init_data) { 4459 .name = "gcc_qupv3_wrap0_s3_clk", 4460 .parent_hws = (const struct clk_hw*[]) { 4461 &gcc_qupv3_wrap0_s3_div_clk_src.clkr.hw, 4462 }, 4463 .num_parents = 1, 4464 .flags = CLK_SET_RATE_PARENT, 4465 .ops = &clk_branch2_ops, 4466 }, 4467 }, 4468 }; 4469 4470 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 4471 .halt_reg = 0x424f4, 4472 .halt_check = BRANCH_HALT_VOTED, 4473 .clkr = { 4474 .enable_reg = 0x52020, 4475 .enable_mask = BIT(14), 4476 .hw.init = &(const struct clk_init_data) { 4477 .name = "gcc_qupv3_wrap0_s4_clk", 4478 .parent_hws = (const struct clk_hw*[]) { 4479 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 4480 }, 4481 .num_parents = 1, 4482 .flags = CLK_SET_RATE_PARENT, 4483 .ops = &clk_branch2_ops, 4484 }, 4485 }, 4486 }; 4487 4488 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 4489 .halt_reg = 0x4262c, 4490 .halt_check = BRANCH_HALT_VOTED, 4491 .clkr = { 4492 .enable_reg = 0x52020, 4493 .enable_mask = BIT(15), 4494 .hw.init = &(const struct clk_init_data) { 4495 .name = "gcc_qupv3_wrap0_s5_clk", 4496 .parent_hws = (const struct clk_hw*[]) { 4497 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 4498 }, 4499 .num_parents = 1, 4500 .flags = CLK_SET_RATE_PARENT, 4501 .ops = &clk_branch2_ops, 4502 }, 4503 }, 4504 }; 4505 4506 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 4507 .halt_reg = 0x42764, 4508 .halt_check = BRANCH_HALT_VOTED, 4509 .clkr = { 4510 .enable_reg = 0x52020, 4511 .enable_mask = BIT(16), 4512 .hw.init = &(const struct clk_init_data) { 4513 .name = "gcc_qupv3_wrap0_s6_clk", 4514 .parent_hws = (const struct clk_hw*[]) { 4515 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 4516 }, 4517 .num_parents = 1, 4518 .flags = CLK_SET_RATE_PARENT, 4519 .ops = &clk_branch2_ops, 4520 }, 4521 }, 4522 }; 4523 4524 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 4525 .halt_reg = 0x4289c, 4526 .halt_check = BRANCH_HALT_VOTED, 4527 .clkr = { 4528 .enable_reg = 0x52020, 4529 .enable_mask = BIT(17), 4530 .hw.init = &(const struct clk_init_data) { 4531 .name = "gcc_qupv3_wrap0_s7_clk", 4532 .parent_hws = (const struct clk_hw*[]) { 4533 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, 4534 }, 4535 .num_parents = 1, 4536 .flags = CLK_SET_RATE_PARENT, 4537 .ops = &clk_branch2_ops, 4538 }, 4539 }, 4540 }; 4541 4542 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 4543 .halt_reg = 0x23168, 4544 .halt_check = BRANCH_HALT_VOTED, 4545 .clkr = { 4546 .enable_reg = 0x52008, 4547 .enable_mask = BIT(18), 4548 .hw.init = &(const struct clk_init_data) { 4549 .name = "gcc_qupv3_wrap1_core_2x_clk", 4550 .ops = &clk_branch2_ops, 4551 }, 4552 }, 4553 }; 4554 4555 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 4556 .halt_reg = 0x23158, 4557 .halt_check = BRANCH_HALT_VOTED, 4558 .clkr = { 4559 .enable_reg = 0x52008, 4560 .enable_mask = BIT(19), 4561 .hw.init = &(const struct clk_init_data) { 4562 .name = "gcc_qupv3_wrap1_core_clk", 4563 .ops = &clk_branch2_ops, 4564 }, 4565 }, 4566 }; 4567 4568 static struct clk_branch gcc_qupv3_wrap1_qspi_s2_clk = { 4569 .halt_reg = 0x18280, 4570 .halt_check = BRANCH_HALT_VOTED, 4571 .clkr = { 4572 .enable_reg = 0x52028, 4573 .enable_mask = BIT(4), 4574 .hw.init = &(const struct clk_init_data) { 4575 .name = "gcc_qupv3_wrap1_qspi_s2_clk", 4576 .parent_hws = (const struct clk_hw*[]) { 4577 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 4578 }, 4579 .num_parents = 1, 4580 .flags = CLK_SET_RATE_PARENT, 4581 .ops = &clk_branch2_ops, 4582 }, 4583 }, 4584 }; 4585 4586 static struct clk_branch gcc_qupv3_wrap1_qspi_s3_clk = { 4587 .halt_reg = 0x183c0, 4588 .halt_check = BRANCH_HALT_VOTED, 4589 .clkr = { 4590 .enable_reg = 0x52028, 4591 .enable_mask = BIT(5), 4592 .hw.init = &(const struct clk_init_data) { 4593 .name = "gcc_qupv3_wrap1_qspi_s3_clk", 4594 .parent_hws = (const struct clk_hw*[]) { 4595 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 4596 }, 4597 .num_parents = 1, 4598 .flags = CLK_SET_RATE_PARENT, 4599 .ops = &clk_branch2_ops, 4600 }, 4601 }, 4602 }; 4603 4604 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 4605 .halt_reg = 0x18004, 4606 .halt_check = BRANCH_HALT_VOTED, 4607 .clkr = { 4608 .enable_reg = 0x52008, 4609 .enable_mask = BIT(22), 4610 .hw.init = &(const struct clk_init_data) { 4611 .name = "gcc_qupv3_wrap1_s0_clk", 4612 .parent_hws = (const struct clk_hw*[]) { 4613 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 4614 }, 4615 .num_parents = 1, 4616 .flags = CLK_SET_RATE_PARENT, 4617 .ops = &clk_branch2_ops, 4618 }, 4619 }, 4620 }; 4621 4622 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 4623 .halt_reg = 0x1813c, 4624 .halt_check = BRANCH_HALT_VOTED, 4625 .clkr = { 4626 .enable_reg = 0x52008, 4627 .enable_mask = BIT(23), 4628 .hw.init = &(const struct clk_init_data) { 4629 .name = "gcc_qupv3_wrap1_s1_clk", 4630 .parent_hws = (const struct clk_hw*[]) { 4631 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 4632 }, 4633 .num_parents = 1, 4634 .flags = CLK_SET_RATE_PARENT, 4635 .ops = &clk_branch2_ops, 4636 }, 4637 }, 4638 }; 4639 4640 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 4641 .halt_reg = 0x18274, 4642 .halt_check = BRANCH_HALT_VOTED, 4643 .clkr = { 4644 .enable_reg = 0x52008, 4645 .enable_mask = BIT(24), 4646 .hw.init = &(const struct clk_init_data) { 4647 .name = "gcc_qupv3_wrap1_s2_clk", 4648 .parent_hws = (const struct clk_hw*[]) { 4649 &gcc_qupv3_wrap1_s2_div_clk_src.clkr.hw, 4650 }, 4651 .num_parents = 1, 4652 .flags = CLK_SET_RATE_PARENT, 4653 .ops = &clk_branch2_ops, 4654 }, 4655 }, 4656 }; 4657 4658 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 4659 .halt_reg = 0x183b4, 4660 .halt_check = BRANCH_HALT_VOTED, 4661 .clkr = { 4662 .enable_reg = 0x52008, 4663 .enable_mask = BIT(25), 4664 .hw.init = &(const struct clk_init_data) { 4665 .name = "gcc_qupv3_wrap1_s3_clk", 4666 .parent_hws = (const struct clk_hw*[]) { 4667 &gcc_qupv3_wrap1_s3_div_clk_src.clkr.hw, 4668 }, 4669 .num_parents = 1, 4670 .flags = CLK_SET_RATE_PARENT, 4671 .ops = &clk_branch2_ops, 4672 }, 4673 }, 4674 }; 4675 4676 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 4677 .halt_reg = 0x184f4, 4678 .halt_check = BRANCH_HALT_VOTED, 4679 .clkr = { 4680 .enable_reg = 0x52008, 4681 .enable_mask = BIT(26), 4682 .hw.init = &(const struct clk_init_data) { 4683 .name = "gcc_qupv3_wrap1_s4_clk", 4684 .parent_hws = (const struct clk_hw*[]) { 4685 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 4686 }, 4687 .num_parents = 1, 4688 .flags = CLK_SET_RATE_PARENT, 4689 .ops = &clk_branch2_ops, 4690 }, 4691 }, 4692 }; 4693 4694 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 4695 .halt_reg = 0x1862c, 4696 .halt_check = BRANCH_HALT_VOTED, 4697 .clkr = { 4698 .enable_reg = 0x52008, 4699 .enable_mask = BIT(27), 4700 .hw.init = &(const struct clk_init_data) { 4701 .name = "gcc_qupv3_wrap1_s5_clk", 4702 .parent_hws = (const struct clk_hw*[]) { 4703 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 4704 }, 4705 .num_parents = 1, 4706 .flags = CLK_SET_RATE_PARENT, 4707 .ops = &clk_branch2_ops, 4708 }, 4709 }, 4710 }; 4711 4712 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 4713 .halt_reg = 0x18764, 4714 .halt_check = BRANCH_HALT_VOTED, 4715 .clkr = { 4716 .enable_reg = 0x52008, 4717 .enable_mask = BIT(28), 4718 .hw.init = &(const struct clk_init_data) { 4719 .name = "gcc_qupv3_wrap1_s6_clk", 4720 .parent_hws = (const struct clk_hw*[]) { 4721 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 4722 }, 4723 .num_parents = 1, 4724 .flags = CLK_SET_RATE_PARENT, 4725 .ops = &clk_branch2_ops, 4726 }, 4727 }, 4728 }; 4729 4730 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 4731 .halt_reg = 0x1889c, 4732 .halt_check = BRANCH_HALT_VOTED, 4733 .clkr = { 4734 .enable_reg = 0x52010, 4735 .enable_mask = BIT(16), 4736 .hw.init = &(const struct clk_init_data) { 4737 .name = "gcc_qupv3_wrap1_s7_clk", 4738 .parent_hws = (const struct clk_hw*[]) { 4739 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 4740 }, 4741 .num_parents = 1, 4742 .flags = CLK_SET_RATE_PARENT, 4743 .ops = &clk_branch2_ops, 4744 }, 4745 }, 4746 }; 4747 4748 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { 4749 .halt_reg = 0x232b8, 4750 .halt_check = BRANCH_HALT_VOTED, 4751 .clkr = { 4752 .enable_reg = 0x52010, 4753 .enable_mask = BIT(3), 4754 .hw.init = &(const struct clk_init_data) { 4755 .name = "gcc_qupv3_wrap2_core_2x_clk", 4756 .ops = &clk_branch2_ops, 4757 }, 4758 }, 4759 }; 4760 4761 static struct clk_branch gcc_qupv3_wrap2_core_clk = { 4762 .halt_reg = 0x232a8, 4763 .halt_check = BRANCH_HALT_VOTED, 4764 .clkr = { 4765 .enable_reg = 0x52010, 4766 .enable_mask = BIT(0), 4767 .hw.init = &(const struct clk_init_data) { 4768 .name = "gcc_qupv3_wrap2_core_clk", 4769 .ops = &clk_branch2_ops, 4770 }, 4771 }, 4772 }; 4773 4774 static struct clk_branch gcc_qupv3_wrap2_qspi_s2_clk = { 4775 .halt_reg = 0x1e280, 4776 .halt_check = BRANCH_HALT_VOTED, 4777 .clkr = { 4778 .enable_reg = 0x52028, 4779 .enable_mask = BIT(6), 4780 .hw.init = &(const struct clk_init_data) { 4781 .name = "gcc_qupv3_wrap2_qspi_s2_clk", 4782 .parent_hws = (const struct clk_hw*[]) { 4783 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 4784 }, 4785 .num_parents = 1, 4786 .flags = CLK_SET_RATE_PARENT, 4787 .ops = &clk_branch2_ops, 4788 }, 4789 }, 4790 }; 4791 4792 static struct clk_branch gcc_qupv3_wrap2_qspi_s3_clk = { 4793 .halt_reg = 0x1e3c0, 4794 .halt_check = BRANCH_HALT_VOTED, 4795 .clkr = { 4796 .enable_reg = 0x52028, 4797 .enable_mask = BIT(7), 4798 .hw.init = &(const struct clk_init_data) { 4799 .name = "gcc_qupv3_wrap2_qspi_s3_clk", 4800 .parent_hws = (const struct clk_hw*[]) { 4801 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 4802 }, 4803 .num_parents = 1, 4804 .flags = CLK_SET_RATE_PARENT, 4805 .ops = &clk_branch2_ops, 4806 }, 4807 }, 4808 }; 4809 4810 static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 4811 .halt_reg = 0x1e004, 4812 .halt_check = BRANCH_HALT_VOTED, 4813 .clkr = { 4814 .enable_reg = 0x52010, 4815 .enable_mask = BIT(4), 4816 .hw.init = &(const struct clk_init_data) { 4817 .name = "gcc_qupv3_wrap2_s0_clk", 4818 .parent_hws = (const struct clk_hw*[]) { 4819 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 4820 }, 4821 .num_parents = 1, 4822 .flags = CLK_SET_RATE_PARENT, 4823 .ops = &clk_branch2_ops, 4824 }, 4825 }, 4826 }; 4827 4828 static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 4829 .halt_reg = 0x1e13c, 4830 .halt_check = BRANCH_HALT_VOTED, 4831 .clkr = { 4832 .enable_reg = 0x52010, 4833 .enable_mask = BIT(5), 4834 .hw.init = &(const struct clk_init_data) { 4835 .name = "gcc_qupv3_wrap2_s1_clk", 4836 .parent_hws = (const struct clk_hw*[]) { 4837 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 4838 }, 4839 .num_parents = 1, 4840 .flags = CLK_SET_RATE_PARENT, 4841 .ops = &clk_branch2_ops, 4842 }, 4843 }, 4844 }; 4845 4846 static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 4847 .halt_reg = 0x1e274, 4848 .halt_check = BRANCH_HALT_VOTED, 4849 .clkr = { 4850 .enable_reg = 0x52010, 4851 .enable_mask = BIT(6), 4852 .hw.init = &(const struct clk_init_data) { 4853 .name = "gcc_qupv3_wrap2_s2_clk", 4854 .parent_hws = (const struct clk_hw*[]) { 4855 &gcc_qupv3_wrap2_s2_div_clk_src.clkr.hw, 4856 }, 4857 .num_parents = 1, 4858 .flags = CLK_SET_RATE_PARENT, 4859 .ops = &clk_branch2_ops, 4860 }, 4861 }, 4862 }; 4863 4864 static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 4865 .halt_reg = 0x1e3b4, 4866 .halt_check = BRANCH_HALT_VOTED, 4867 .clkr = { 4868 .enable_reg = 0x52010, 4869 .enable_mask = BIT(7), 4870 .hw.init = &(const struct clk_init_data) { 4871 .name = "gcc_qupv3_wrap2_s3_clk", 4872 .parent_hws = (const struct clk_hw*[]) { 4873 &gcc_qupv3_wrap2_s3_div_clk_src.clkr.hw, 4874 }, 4875 .num_parents = 1, 4876 .flags = CLK_SET_RATE_PARENT, 4877 .ops = &clk_branch2_ops, 4878 }, 4879 }, 4880 }; 4881 4882 static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 4883 .halt_reg = 0x1e4f4, 4884 .halt_check = BRANCH_HALT_VOTED, 4885 .clkr = { 4886 .enable_reg = 0x52010, 4887 .enable_mask = BIT(8), 4888 .hw.init = &(const struct clk_init_data) { 4889 .name = "gcc_qupv3_wrap2_s4_clk", 4890 .parent_hws = (const struct clk_hw*[]) { 4891 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 4892 }, 4893 .num_parents = 1, 4894 .flags = CLK_SET_RATE_PARENT, 4895 .ops = &clk_branch2_ops, 4896 }, 4897 }, 4898 }; 4899 4900 static struct clk_branch gcc_qupv3_wrap2_s5_clk = { 4901 .halt_reg = 0x1e62c, 4902 .halt_check = BRANCH_HALT_VOTED, 4903 .clkr = { 4904 .enable_reg = 0x52010, 4905 .enable_mask = BIT(9), 4906 .hw.init = &(const struct clk_init_data) { 4907 .name = "gcc_qupv3_wrap2_s5_clk", 4908 .parent_hws = (const struct clk_hw*[]) { 4909 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, 4910 }, 4911 .num_parents = 1, 4912 .flags = CLK_SET_RATE_PARENT, 4913 .ops = &clk_branch2_ops, 4914 }, 4915 }, 4916 }; 4917 4918 static struct clk_branch gcc_qupv3_wrap2_s6_clk = { 4919 .halt_reg = 0x1e764, 4920 .halt_check = BRANCH_HALT_VOTED, 4921 .clkr = { 4922 .enable_reg = 0x52010, 4923 .enable_mask = BIT(10), 4924 .hw.init = &(const struct clk_init_data) { 4925 .name = "gcc_qupv3_wrap2_s6_clk", 4926 .parent_hws = (const struct clk_hw*[]) { 4927 &gcc_qupv3_wrap2_s6_clk_src.clkr.hw, 4928 }, 4929 .num_parents = 1, 4930 .flags = CLK_SET_RATE_PARENT, 4931 .ops = &clk_branch2_ops, 4932 }, 4933 }, 4934 }; 4935 4936 static struct clk_branch gcc_qupv3_wrap2_s7_clk = { 4937 .halt_reg = 0x1e89c, 4938 .halt_check = BRANCH_HALT_VOTED, 4939 .clkr = { 4940 .enable_reg = 0x52010, 4941 .enable_mask = BIT(17), 4942 .hw.init = &(const struct clk_init_data) { 4943 .name = "gcc_qupv3_wrap2_s7_clk", 4944 .parent_hws = (const struct clk_hw*[]) { 4945 &gcc_qupv3_wrap2_s7_clk_src.clkr.hw, 4946 }, 4947 .num_parents = 1, 4948 .flags = CLK_SET_RATE_PARENT, 4949 .ops = &clk_branch2_ops, 4950 }, 4951 }, 4952 }; 4953 4954 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 4955 .halt_reg = 0x23000, 4956 .halt_check = BRANCH_HALT_VOTED, 4957 .hwcg_reg = 0x23000, 4958 .hwcg_bit = 1, 4959 .clkr = { 4960 .enable_reg = 0x52020, 4961 .enable_mask = BIT(6), 4962 .hw.init = &(const struct clk_init_data) { 4963 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 4964 .ops = &clk_branch2_ops, 4965 }, 4966 }, 4967 }; 4968 4969 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 4970 .halt_reg = 0x23004, 4971 .halt_check = BRANCH_HALT_VOTED, 4972 .hwcg_reg = 0x23004, 4973 .hwcg_bit = 1, 4974 .clkr = { 4975 .enable_reg = 0x52020, 4976 .enable_mask = BIT(7), 4977 .hw.init = &(const struct clk_init_data) { 4978 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 4979 .ops = &clk_branch2_ops, 4980 }, 4981 }, 4982 }; 4983 4984 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 4985 .halt_reg = 0x23150, 4986 .halt_check = BRANCH_HALT_VOTED, 4987 .hwcg_reg = 0x23150, 4988 .hwcg_bit = 1, 4989 .clkr = { 4990 .enable_reg = 0x52008, 4991 .enable_mask = BIT(20), 4992 .hw.init = &(const struct clk_init_data) { 4993 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 4994 .ops = &clk_branch2_ops, 4995 }, 4996 }, 4997 }; 4998 4999 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 5000 .halt_reg = 0x23154, 5001 .halt_check = BRANCH_HALT_VOTED, 5002 .hwcg_reg = 0x23154, 5003 .hwcg_bit = 1, 5004 .clkr = { 5005 .enable_reg = 0x52008, 5006 .enable_mask = BIT(21), 5007 .hw.init = &(const struct clk_init_data) { 5008 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 5009 .ops = &clk_branch2_ops, 5010 }, 5011 }, 5012 }; 5013 5014 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 5015 .halt_reg = 0x232a0, 5016 .halt_check = BRANCH_HALT_VOTED, 5017 .hwcg_reg = 0x232a0, 5018 .hwcg_bit = 1, 5019 .clkr = { 5020 .enable_reg = 0x52010, 5021 .enable_mask = BIT(2), 5022 .hw.init = &(const struct clk_init_data) { 5023 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 5024 .ops = &clk_branch2_ops, 5025 }, 5026 }, 5027 }; 5028 5029 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 5030 .halt_reg = 0x232a4, 5031 .halt_check = BRANCH_HALT_VOTED, 5032 .hwcg_reg = 0x232a4, 5033 .hwcg_bit = 1, 5034 .clkr = { 5035 .enable_reg = 0x52010, 5036 .enable_mask = BIT(1), 5037 .hw.init = &(const struct clk_init_data) { 5038 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 5039 .ops = &clk_branch2_ops, 5040 }, 5041 }, 5042 }; 5043 5044 static struct clk_branch gcc_sdcc2_ahb_clk = { 5045 .halt_reg = 0x14010, 5046 .halt_check = BRANCH_HALT, 5047 .clkr = { 5048 .enable_reg = 0x14010, 5049 .enable_mask = BIT(0), 5050 .hw.init = &(const struct clk_init_data) { 5051 .name = "gcc_sdcc2_ahb_clk", 5052 .ops = &clk_branch2_ops, 5053 }, 5054 }, 5055 }; 5056 5057 static struct clk_branch gcc_sdcc2_apps_clk = { 5058 .halt_reg = 0x14004, 5059 .halt_check = BRANCH_HALT, 5060 .clkr = { 5061 .enable_reg = 0x14004, 5062 .enable_mask = BIT(0), 5063 .hw.init = &(const struct clk_init_data) { 5064 .name = "gcc_sdcc2_apps_clk", 5065 .parent_hws = (const struct clk_hw*[]) { 5066 &gcc_sdcc2_apps_clk_src.clkr.hw, 5067 }, 5068 .num_parents = 1, 5069 .flags = CLK_SET_RATE_PARENT, 5070 .ops = &clk_branch2_ops, 5071 }, 5072 }, 5073 }; 5074 5075 static struct clk_branch gcc_sdcc4_ahb_clk = { 5076 .halt_reg = 0x16010, 5077 .halt_check = BRANCH_HALT, 5078 .clkr = { 5079 .enable_reg = 0x16010, 5080 .enable_mask = BIT(0), 5081 .hw.init = &(const struct clk_init_data) { 5082 .name = "gcc_sdcc4_ahb_clk", 5083 .ops = &clk_branch2_ops, 5084 }, 5085 }, 5086 }; 5087 5088 static struct clk_branch gcc_sdcc4_apps_clk = { 5089 .halt_reg = 0x16004, 5090 .halt_check = BRANCH_HALT, 5091 .clkr = { 5092 .enable_reg = 0x16004, 5093 .enable_mask = BIT(0), 5094 .hw.init = &(const struct clk_init_data) { 5095 .name = "gcc_sdcc4_apps_clk", 5096 .parent_hws = (const struct clk_hw*[]) { 5097 &gcc_sdcc4_apps_clk_src.clkr.hw, 5098 }, 5099 .num_parents = 1, 5100 .flags = CLK_SET_RATE_PARENT, 5101 .ops = &clk_branch2_ops, 5102 }, 5103 }, 5104 }; 5105 5106 static struct clk_branch gcc_sys_noc_usb_axi_clk = { 5107 .halt_reg = 0x2d014, 5108 .halt_check = BRANCH_HALT_VOTED, 5109 .hwcg_reg = 0x2d014, 5110 .hwcg_bit = 1, 5111 .clkr = { 5112 .enable_reg = 0x2d014, 5113 .enable_mask = BIT(0), 5114 .hw.init = &(const struct clk_init_data) { 5115 .name = "gcc_sys_noc_usb_axi_clk", 5116 .ops = &clk_branch2_ops, 5117 }, 5118 }, 5119 }; 5120 5121 static struct clk_branch gcc_ufs_phy_ahb_clk = { 5122 .halt_reg = 0x77024, 5123 .halt_check = BRANCH_HALT_VOTED, 5124 .hwcg_reg = 0x77024, 5125 .hwcg_bit = 1, 5126 .clkr = { 5127 .enable_reg = 0x77024, 5128 .enable_mask = BIT(0), 5129 .hw.init = &(const struct clk_init_data) { 5130 .name = "gcc_ufs_phy_ahb_clk", 5131 .ops = &clk_branch2_ops, 5132 }, 5133 }, 5134 }; 5135 5136 static struct clk_branch gcc_ufs_phy_axi_clk = { 5137 .halt_reg = 0x77018, 5138 .halt_check = BRANCH_HALT_VOTED, 5139 .hwcg_reg = 0x77018, 5140 .hwcg_bit = 1, 5141 .clkr = { 5142 .enable_reg = 0x77018, 5143 .enable_mask = BIT(0), 5144 .hw.init = &(const struct clk_init_data) { 5145 .name = "gcc_ufs_phy_axi_clk", 5146 .parent_hws = (const struct clk_hw*[]) { 5147 &gcc_ufs_phy_axi_clk_src.clkr.hw, 5148 }, 5149 .num_parents = 1, 5150 .flags = CLK_SET_RATE_PARENT, 5151 .ops = &clk_branch2_ops, 5152 }, 5153 }, 5154 }; 5155 5156 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 5157 .halt_reg = 0x77074, 5158 .halt_check = BRANCH_HALT_VOTED, 5159 .hwcg_reg = 0x77074, 5160 .hwcg_bit = 1, 5161 .clkr = { 5162 .enable_reg = 0x77074, 5163 .enable_mask = BIT(0), 5164 .hw.init = &(const struct clk_init_data) { 5165 .name = "gcc_ufs_phy_ice_core_clk", 5166 .parent_hws = (const struct clk_hw*[]) { 5167 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 5168 }, 5169 .num_parents = 1, 5170 .flags = CLK_SET_RATE_PARENT, 5171 .ops = &clk_branch2_ops, 5172 }, 5173 }, 5174 }; 5175 5176 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 5177 .halt_reg = 0x770b0, 5178 .halt_check = BRANCH_HALT_VOTED, 5179 .hwcg_reg = 0x770b0, 5180 .hwcg_bit = 1, 5181 .clkr = { 5182 .enable_reg = 0x770b0, 5183 .enable_mask = BIT(0), 5184 .hw.init = &(const struct clk_init_data) { 5185 .name = "gcc_ufs_phy_phy_aux_clk", 5186 .parent_hws = (const struct clk_hw*[]) { 5187 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 5188 }, 5189 .num_parents = 1, 5190 .flags = CLK_SET_RATE_PARENT, 5191 .ops = &clk_branch2_ops, 5192 }, 5193 }, 5194 }; 5195 5196 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 5197 .halt_reg = 0x7702c, 5198 .halt_check = BRANCH_HALT_DELAY, 5199 .clkr = { 5200 .enable_reg = 0x7702c, 5201 .enable_mask = BIT(0), 5202 .hw.init = &(const struct clk_init_data) { 5203 .name = "gcc_ufs_phy_rx_symbol_0_clk", 5204 .parent_hws = (const struct clk_hw*[]) { 5205 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, 5206 }, 5207 .num_parents = 1, 5208 .flags = CLK_SET_RATE_PARENT, 5209 .ops = &clk_branch2_ops, 5210 }, 5211 }, 5212 }; 5213 5214 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 5215 .halt_reg = 0x770cc, 5216 .halt_check = BRANCH_HALT_DELAY, 5217 .clkr = { 5218 .enable_reg = 0x770cc, 5219 .enable_mask = BIT(0), 5220 .hw.init = &(const struct clk_init_data) { 5221 .name = "gcc_ufs_phy_rx_symbol_1_clk", 5222 .parent_hws = (const struct clk_hw*[]) { 5223 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, 5224 }, 5225 .num_parents = 1, 5226 .flags = CLK_SET_RATE_PARENT, 5227 .ops = &clk_branch2_ops, 5228 }, 5229 }, 5230 }; 5231 5232 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 5233 .halt_reg = 0x77028, 5234 .halt_check = BRANCH_HALT_DELAY, 5235 .clkr = { 5236 .enable_reg = 0x77028, 5237 .enable_mask = BIT(0), 5238 .hw.init = &(const struct clk_init_data) { 5239 .name = "gcc_ufs_phy_tx_symbol_0_clk", 5240 .parent_hws = (const struct clk_hw*[]) { 5241 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, 5242 }, 5243 .num_parents = 1, 5244 .flags = CLK_SET_RATE_PARENT, 5245 .ops = &clk_branch2_ops, 5246 }, 5247 }, 5248 }; 5249 5250 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 5251 .halt_reg = 0x77068, 5252 .halt_check = BRANCH_HALT_VOTED, 5253 .hwcg_reg = 0x77068, 5254 .hwcg_bit = 1, 5255 .clkr = { 5256 .enable_reg = 0x77068, 5257 .enable_mask = BIT(0), 5258 .hw.init = &(const struct clk_init_data) { 5259 .name = "gcc_ufs_phy_unipro_core_clk", 5260 .parent_hws = (const struct clk_hw*[]) { 5261 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 5262 }, 5263 .num_parents = 1, 5264 .flags = CLK_SET_RATE_PARENT, 5265 .ops = &clk_branch2_ops, 5266 }, 5267 }, 5268 }; 5269 5270 static struct clk_branch gcc_usb20_master_clk = { 5271 .halt_reg = 0x29018, 5272 .halt_check = BRANCH_HALT, 5273 .clkr = { 5274 .enable_reg = 0x29018, 5275 .enable_mask = BIT(0), 5276 .hw.init = &(const struct clk_init_data) { 5277 .name = "gcc_usb20_master_clk", 5278 .parent_hws = (const struct clk_hw*[]) { 5279 &gcc_usb20_master_clk_src.clkr.hw, 5280 }, 5281 .num_parents = 1, 5282 .flags = CLK_SET_RATE_PARENT, 5283 .ops = &clk_branch2_ops, 5284 }, 5285 }, 5286 }; 5287 5288 static struct clk_branch gcc_usb20_mock_utmi_clk = { 5289 .halt_reg = 0x29028, 5290 .halt_check = BRANCH_HALT, 5291 .clkr = { 5292 .enable_reg = 0x29028, 5293 .enable_mask = BIT(0), 5294 .hw.init = &(const struct clk_init_data) { 5295 .name = "gcc_usb20_mock_utmi_clk", 5296 .parent_hws = (const struct clk_hw*[]) { 5297 &gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw, 5298 }, 5299 .num_parents = 1, 5300 .flags = CLK_SET_RATE_PARENT, 5301 .ops = &clk_branch2_ops, 5302 }, 5303 }, 5304 }; 5305 5306 static struct clk_branch gcc_usb20_sleep_clk = { 5307 .halt_reg = 0x29024, 5308 .halt_check = BRANCH_HALT, 5309 .clkr = { 5310 .enable_reg = 0x29024, 5311 .enable_mask = BIT(0), 5312 .hw.init = &(const struct clk_init_data) { 5313 .name = "gcc_usb20_sleep_clk", 5314 .ops = &clk_branch2_ops, 5315 }, 5316 }, 5317 }; 5318 5319 static struct clk_branch gcc_usb30_mp_master_clk = { 5320 .halt_reg = 0x17018, 5321 .halt_check = BRANCH_HALT, 5322 .clkr = { 5323 .enable_reg = 0x17018, 5324 .enable_mask = BIT(0), 5325 .hw.init = &(const struct clk_init_data) { 5326 .name = "gcc_usb30_mp_master_clk", 5327 .parent_hws = (const struct clk_hw*[]) { 5328 &gcc_usb30_mp_master_clk_src.clkr.hw, 5329 }, 5330 .num_parents = 1, 5331 .flags = CLK_SET_RATE_PARENT, 5332 .ops = &clk_branch2_ops, 5333 }, 5334 }, 5335 }; 5336 5337 static struct clk_branch gcc_usb30_mp_mock_utmi_clk = { 5338 .halt_reg = 0x17028, 5339 .halt_check = BRANCH_HALT, 5340 .clkr = { 5341 .enable_reg = 0x17028, 5342 .enable_mask = BIT(0), 5343 .hw.init = &(const struct clk_init_data) { 5344 .name = "gcc_usb30_mp_mock_utmi_clk", 5345 .parent_hws = (const struct clk_hw*[]) { 5346 &gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr.hw, 5347 }, 5348 .num_parents = 1, 5349 .flags = CLK_SET_RATE_PARENT, 5350 .ops = &clk_branch2_ops, 5351 }, 5352 }, 5353 }; 5354 5355 static struct clk_branch gcc_usb30_mp_sleep_clk = { 5356 .halt_reg = 0x17024, 5357 .halt_check = BRANCH_HALT, 5358 .clkr = { 5359 .enable_reg = 0x17024, 5360 .enable_mask = BIT(0), 5361 .hw.init = &(const struct clk_init_data) { 5362 .name = "gcc_usb30_mp_sleep_clk", 5363 .ops = &clk_branch2_ops, 5364 }, 5365 }, 5366 }; 5367 5368 static struct clk_branch gcc_usb30_prim_master_clk = { 5369 .halt_reg = 0x39018, 5370 .halt_check = BRANCH_HALT, 5371 .clkr = { 5372 .enable_reg = 0x39018, 5373 .enable_mask = BIT(0), 5374 .hw.init = &(const struct clk_init_data) { 5375 .name = "gcc_usb30_prim_master_clk", 5376 .parent_hws = (const struct clk_hw*[]) { 5377 &gcc_usb30_prim_master_clk_src.clkr.hw, 5378 }, 5379 .num_parents = 1, 5380 .flags = CLK_SET_RATE_PARENT, 5381 .ops = &clk_branch2_ops, 5382 }, 5383 }, 5384 }; 5385 5386 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 5387 .halt_reg = 0x39028, 5388 .halt_check = BRANCH_HALT, 5389 .clkr = { 5390 .enable_reg = 0x39028, 5391 .enable_mask = BIT(0), 5392 .hw.init = &(const struct clk_init_data) { 5393 .name = "gcc_usb30_prim_mock_utmi_clk", 5394 .parent_hws = (const struct clk_hw*[]) { 5395 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 5396 }, 5397 .num_parents = 1, 5398 .flags = CLK_SET_RATE_PARENT, 5399 .ops = &clk_branch2_ops, 5400 }, 5401 }, 5402 }; 5403 5404 static struct clk_branch gcc_usb30_prim_sleep_clk = { 5405 .halt_reg = 0x39024, 5406 .halt_check = BRANCH_HALT, 5407 .clkr = { 5408 .enable_reg = 0x39024, 5409 .enable_mask = BIT(0), 5410 .hw.init = &(const struct clk_init_data) { 5411 .name = "gcc_usb30_prim_sleep_clk", 5412 .ops = &clk_branch2_ops, 5413 }, 5414 }, 5415 }; 5416 5417 static struct clk_branch gcc_usb30_sec_master_clk = { 5418 .halt_reg = 0xa1018, 5419 .halt_check = BRANCH_HALT, 5420 .clkr = { 5421 .enable_reg = 0xa1018, 5422 .enable_mask = BIT(0), 5423 .hw.init = &(const struct clk_init_data) { 5424 .name = "gcc_usb30_sec_master_clk", 5425 .parent_hws = (const struct clk_hw*[]) { 5426 &gcc_usb30_sec_master_clk_src.clkr.hw, 5427 }, 5428 .num_parents = 1, 5429 .flags = CLK_SET_RATE_PARENT, 5430 .ops = &clk_branch2_ops, 5431 }, 5432 }, 5433 }; 5434 5435 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { 5436 .halt_reg = 0xa1028, 5437 .halt_check = BRANCH_HALT, 5438 .clkr = { 5439 .enable_reg = 0xa1028, 5440 .enable_mask = BIT(0), 5441 .hw.init = &(const struct clk_init_data) { 5442 .name = "gcc_usb30_sec_mock_utmi_clk", 5443 .parent_hws = (const struct clk_hw*[]) { 5444 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw, 5445 }, 5446 .num_parents = 1, 5447 .flags = CLK_SET_RATE_PARENT, 5448 .ops = &clk_branch2_ops, 5449 }, 5450 }, 5451 }; 5452 5453 static struct clk_branch gcc_usb30_sec_sleep_clk = { 5454 .halt_reg = 0xa1024, 5455 .halt_check = BRANCH_HALT, 5456 .clkr = { 5457 .enable_reg = 0xa1024, 5458 .enable_mask = BIT(0), 5459 .hw.init = &(const struct clk_init_data) { 5460 .name = "gcc_usb30_sec_sleep_clk", 5461 .ops = &clk_branch2_ops, 5462 }, 5463 }, 5464 }; 5465 5466 static struct clk_branch gcc_usb30_tert_master_clk = { 5467 .halt_reg = 0xa2018, 5468 .halt_check = BRANCH_HALT, 5469 .clkr = { 5470 .enable_reg = 0xa2018, 5471 .enable_mask = BIT(0), 5472 .hw.init = &(const struct clk_init_data) { 5473 .name = "gcc_usb30_tert_master_clk", 5474 .parent_hws = (const struct clk_hw*[]) { 5475 &gcc_usb30_tert_master_clk_src.clkr.hw, 5476 }, 5477 .num_parents = 1, 5478 .flags = CLK_SET_RATE_PARENT, 5479 .ops = &clk_branch2_ops, 5480 }, 5481 }, 5482 }; 5483 5484 static struct clk_branch gcc_usb30_tert_mock_utmi_clk = { 5485 .halt_reg = 0xa2028, 5486 .halt_check = BRANCH_HALT, 5487 .clkr = { 5488 .enable_reg = 0xa2028, 5489 .enable_mask = BIT(0), 5490 .hw.init = &(const struct clk_init_data) { 5491 .name = "gcc_usb30_tert_mock_utmi_clk", 5492 .parent_hws = (const struct clk_hw*[]) { 5493 &gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr.hw, 5494 }, 5495 .num_parents = 1, 5496 .flags = CLK_SET_RATE_PARENT, 5497 .ops = &clk_branch2_ops, 5498 }, 5499 }, 5500 }; 5501 5502 static struct clk_branch gcc_usb30_tert_sleep_clk = { 5503 .halt_reg = 0xa2024, 5504 .halt_check = BRANCH_HALT, 5505 .clkr = { 5506 .enable_reg = 0xa2024, 5507 .enable_mask = BIT(0), 5508 .hw.init = &(const struct clk_init_data) { 5509 .name = "gcc_usb30_tert_sleep_clk", 5510 .ops = &clk_branch2_ops, 5511 }, 5512 }, 5513 }; 5514 5515 static struct clk_branch gcc_usb3_mp_phy_aux_clk = { 5516 .halt_reg = 0x17288, 5517 .halt_check = BRANCH_HALT, 5518 .clkr = { 5519 .enable_reg = 0x17288, 5520 .enable_mask = BIT(0), 5521 .hw.init = &(const struct clk_init_data) { 5522 .name = "gcc_usb3_mp_phy_aux_clk", 5523 .parent_hws = (const struct clk_hw*[]) { 5524 &gcc_usb3_mp_phy_aux_clk_src.clkr.hw, 5525 }, 5526 .num_parents = 1, 5527 .flags = CLK_SET_RATE_PARENT, 5528 .ops = &clk_branch2_ops, 5529 }, 5530 }, 5531 }; 5532 5533 static struct clk_branch gcc_usb3_mp_phy_com_aux_clk = { 5534 .halt_reg = 0x1728c, 5535 .halt_check = BRANCH_HALT, 5536 .clkr = { 5537 .enable_reg = 0x1728c, 5538 .enable_mask = BIT(0), 5539 .hw.init = &(const struct clk_init_data) { 5540 .name = "gcc_usb3_mp_phy_com_aux_clk", 5541 .parent_hws = (const struct clk_hw*[]) { 5542 &gcc_usb3_mp_phy_aux_clk_src.clkr.hw, 5543 }, 5544 .num_parents = 1, 5545 .flags = CLK_SET_RATE_PARENT, 5546 .ops = &clk_branch2_ops, 5547 }, 5548 }, 5549 }; 5550 5551 static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = { 5552 .halt_reg = 0x17290, 5553 .halt_check = BRANCH_HALT_SKIP, 5554 .clkr = { 5555 .enable_reg = 0x17290, 5556 .enable_mask = BIT(0), 5557 .hw.init = &(const struct clk_init_data) { 5558 .name = "gcc_usb3_mp_phy_pipe_0_clk", 5559 .ops = &clk_branch2_ops, 5560 }, 5561 }, 5562 }; 5563 5564 static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = { 5565 .halt_reg = 0x17298, 5566 .halt_check = BRANCH_HALT_SKIP, 5567 .clkr = { 5568 .enable_reg = 0x17298, 5569 .enable_mask = BIT(0), 5570 .hw.init = &(const struct clk_init_data) { 5571 .name = "gcc_usb3_mp_phy_pipe_1_clk", 5572 .ops = &clk_branch2_ops, 5573 }, 5574 }, 5575 }; 5576 5577 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 5578 .halt_reg = 0x39060, 5579 .halt_check = BRANCH_HALT, 5580 .clkr = { 5581 .enable_reg = 0x39060, 5582 .enable_mask = BIT(0), 5583 .hw.init = &(const struct clk_init_data) { 5584 .name = "gcc_usb3_prim_phy_aux_clk", 5585 .parent_hws = (const struct clk_hw*[]) { 5586 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 5587 }, 5588 .num_parents = 1, 5589 .flags = CLK_SET_RATE_PARENT, 5590 .ops = &clk_branch2_ops, 5591 }, 5592 }, 5593 }; 5594 5595 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 5596 .halt_reg = 0x39064, 5597 .halt_check = BRANCH_HALT, 5598 .clkr = { 5599 .enable_reg = 0x39064, 5600 .enable_mask = BIT(0), 5601 .hw.init = &(const struct clk_init_data) { 5602 .name = "gcc_usb3_prim_phy_com_aux_clk", 5603 .parent_hws = (const struct clk_hw*[]) { 5604 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 5605 }, 5606 .num_parents = 1, 5607 .flags = CLK_SET_RATE_PARENT, 5608 .ops = &clk_branch2_ops, 5609 }, 5610 }, 5611 }; 5612 5613 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 5614 .reg = 0x3906c, 5615 .shift = 0, 5616 .width = 2, 5617 .parent_map = gcc_parent_map_10, 5618 .clkr = { 5619 .hw.init = &(struct clk_init_data){ 5620 .name = "gcc_usb3_prim_phy_pipe_clk_src", 5621 .parent_data = gcc_parent_data_10, 5622 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 5623 .ops = &clk_regmap_mux_closest_ops, 5624 }, 5625 }, 5626 }; 5627 5628 static const struct parent_map gcc_parent_map_34[] = { 5629 { P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 0 }, 5630 { P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 }, 5631 { P_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC, 3 }, 5632 }; 5633 5634 static const struct clk_parent_data gcc_parent_data_34[] = { 5635 { .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw }, 5636 { .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 5637 { .index = DT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC }, 5638 }; 5639 5640 static struct clk_regmap_mux gcc_usb34_prim_phy_pipe_clk_src = { 5641 .reg = 0x39070, 5642 .shift = 0, 5643 .width = 2, 5644 .parent_map = gcc_parent_map_34, 5645 .clkr = { 5646 .hw.init = &(const struct clk_init_data) { 5647 .name = "gcc_usb34_prim_phy_pipe_clk_src", 5648 .parent_data = gcc_parent_data_34, 5649 .num_parents = ARRAY_SIZE(gcc_parent_data_34), 5650 .ops = &clk_regmap_mux_closest_ops, 5651 }, 5652 }, 5653 }; 5654 5655 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 5656 .halt_reg = 0x39068, 5657 .halt_check = BRANCH_HALT_SKIP, 5658 .hwcg_reg = 0x39068, 5659 .hwcg_bit = 1, 5660 .clkr = { 5661 .enable_reg = 0x39068, 5662 .enable_mask = BIT(0), 5663 .hw.init = &(const struct clk_init_data) { 5664 .name = "gcc_usb3_prim_phy_pipe_clk", 5665 .parent_hws = (const struct clk_hw*[]) { 5666 &gcc_usb34_prim_phy_pipe_clk_src.clkr.hw, 5667 }, 5668 .num_parents = 1, 5669 .flags = CLK_SET_RATE_PARENT, 5670 .ops = &clk_branch2_ops, 5671 }, 5672 }, 5673 }; 5674 5675 static struct clk_branch gcc_usb3_sec_phy_aux_clk = { 5676 .halt_reg = 0xa1060, 5677 .halt_check = BRANCH_HALT, 5678 .clkr = { 5679 .enable_reg = 0xa1060, 5680 .enable_mask = BIT(0), 5681 .hw.init = &(const struct clk_init_data) { 5682 .name = "gcc_usb3_sec_phy_aux_clk", 5683 .parent_hws = (const struct clk_hw*[]) { 5684 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 5685 }, 5686 .num_parents = 1, 5687 .flags = CLK_SET_RATE_PARENT, 5688 .ops = &clk_branch2_ops, 5689 }, 5690 }, 5691 }; 5692 5693 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { 5694 .halt_reg = 0xa1064, 5695 .halt_check = BRANCH_HALT, 5696 .clkr = { 5697 .enable_reg = 0xa1064, 5698 .enable_mask = BIT(0), 5699 .hw.init = &(const struct clk_init_data) { 5700 .name = "gcc_usb3_sec_phy_com_aux_clk", 5701 .parent_hws = (const struct clk_hw*[]) { 5702 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 5703 }, 5704 .num_parents = 1, 5705 .flags = CLK_SET_RATE_PARENT, 5706 .ops = &clk_branch2_ops, 5707 }, 5708 }, 5709 }; 5710 5711 static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = { 5712 .reg = 0xa106c, 5713 .shift = 0, 5714 .width = 2, 5715 .parent_map = gcc_parent_map_11, 5716 .clkr = { 5717 .hw.init = &(struct clk_init_data){ 5718 .name = "gcc_usb3_sec_phy_pipe_clk_src", 5719 .parent_data = gcc_parent_data_11, 5720 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 5721 .ops = &clk_regmap_mux_closest_ops, 5722 }, 5723 }, 5724 }; 5725 5726 static const struct parent_map gcc_parent_map_35[] = { 5727 { P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC, 0 }, 5728 { P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 }, 5729 { P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, 3 }, 5730 }; 5731 5732 static const struct clk_parent_data gcc_parent_data_35[] = { 5733 { .hw = &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw }, 5734 { .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 5735 { .index = DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC }, 5736 }; 5737 5738 static struct clk_regmap_mux gcc_usb34_sec_phy_pipe_clk_src = { 5739 .reg = 0xa1070, 5740 .shift = 0, 5741 .width = 2, 5742 .parent_map = gcc_parent_map_35, 5743 .clkr = { 5744 .hw.init = &(const struct clk_init_data) { 5745 .name = "gcc_usb34_sec_phy_pipe_clk_src", 5746 .parent_data = gcc_parent_data_35, 5747 .num_parents = ARRAY_SIZE(gcc_parent_data_35), 5748 .ops = &clk_regmap_mux_closest_ops, 5749 }, 5750 }, 5751 }; 5752 5753 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { 5754 .halt_reg = 0xa1068, 5755 .halt_check = BRANCH_HALT_SKIP, 5756 .hwcg_reg = 0xa1068, 5757 .hwcg_bit = 1, 5758 .clkr = { 5759 .enable_reg = 0xa1068, 5760 .enable_mask = BIT(0), 5761 .hw.init = &(const struct clk_init_data) { 5762 .name = "gcc_usb3_sec_phy_pipe_clk", 5763 .parent_hws = (const struct clk_hw*[]) { 5764 &gcc_usb34_sec_phy_pipe_clk_src.clkr.hw, 5765 }, 5766 .num_parents = 1, 5767 .flags = CLK_SET_RATE_PARENT, 5768 .ops = &clk_branch2_ops, 5769 }, 5770 }, 5771 }; 5772 5773 static struct clk_branch gcc_usb3_tert_phy_aux_clk = { 5774 .halt_reg = 0xa2060, 5775 .halt_check = BRANCH_HALT, 5776 .clkr = { 5777 .enable_reg = 0xa2060, 5778 .enable_mask = BIT(0), 5779 .hw.init = &(const struct clk_init_data) { 5780 .name = "gcc_usb3_tert_phy_aux_clk", 5781 .parent_hws = (const struct clk_hw*[]) { 5782 &gcc_usb3_tert_phy_aux_clk_src.clkr.hw, 5783 }, 5784 .num_parents = 1, 5785 .flags = CLK_SET_RATE_PARENT, 5786 .ops = &clk_branch2_ops, 5787 }, 5788 }, 5789 }; 5790 5791 static struct clk_branch gcc_usb3_tert_phy_com_aux_clk = { 5792 .halt_reg = 0xa2064, 5793 .halt_check = BRANCH_HALT, 5794 .clkr = { 5795 .enable_reg = 0xa2064, 5796 .enable_mask = BIT(0), 5797 .hw.init = &(const struct clk_init_data) { 5798 .name = "gcc_usb3_tert_phy_com_aux_clk", 5799 .parent_hws = (const struct clk_hw*[]) { 5800 &gcc_usb3_tert_phy_aux_clk_src.clkr.hw, 5801 }, 5802 .num_parents = 1, 5803 .flags = CLK_SET_RATE_PARENT, 5804 .ops = &clk_branch2_ops, 5805 }, 5806 }, 5807 }; 5808 5809 static struct clk_regmap_mux gcc_usb3_tert_phy_pipe_clk_src = { 5810 .reg = 0xa206c, 5811 .shift = 0, 5812 .width = 2, 5813 .parent_map = gcc_parent_map_12, 5814 .clkr = { 5815 .hw.init = &(struct clk_init_data){ 5816 .name = "gcc_usb3_tert_phy_pipe_clk_src", 5817 .parent_data = gcc_parent_data_12, 5818 .num_parents = ARRAY_SIZE(gcc_parent_data_12), 5819 .ops = &clk_regmap_mux_closest_ops, 5820 }, 5821 }, 5822 }; 5823 5824 static const struct parent_map gcc_parent_map_36[] = { 5825 { P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC, 0 }, 5826 { P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 }, 5827 { P_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC, 3 }, 5828 }; 5829 5830 static const struct clk_parent_data gcc_parent_data_36[] = { 5831 { .hw = &gcc_usb3_tert_phy_pipe_clk_src.clkr.hw }, 5832 { .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 5833 { .index = DT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC }, 5834 }; 5835 5836 static struct clk_regmap_mux gcc_usb34_tert_phy_pipe_clk_src = { 5837 .reg = 0xa2070, 5838 .shift = 0, 5839 .width = 2, 5840 .parent_map = gcc_parent_map_36, 5841 .clkr = { 5842 .hw.init = &(const struct clk_init_data) { 5843 .name = "gcc_usb34_tert_phy_pipe_clk_src", 5844 .parent_data = gcc_parent_data_36, 5845 .num_parents = ARRAY_SIZE(gcc_parent_data_36), 5846 .ops = &clk_regmap_mux_closest_ops, 5847 }, 5848 }, 5849 }; 5850 5851 static struct clk_branch gcc_usb3_tert_phy_pipe_clk = { 5852 .halt_reg = 0xa2068, 5853 .halt_check = BRANCH_HALT_SKIP, 5854 .hwcg_reg = 0xa2068, 5855 .hwcg_bit = 1, 5856 .clkr = { 5857 .enable_reg = 0xa2068, 5858 .enable_mask = BIT(0), 5859 .hw.init = &(const struct clk_init_data) { 5860 .name = "gcc_usb3_tert_phy_pipe_clk", 5861 .parent_hws = (const struct clk_hw*[]) { 5862 &gcc_usb34_tert_phy_pipe_clk_src.clkr.hw, 5863 }, 5864 .num_parents = 1, 5865 .flags = CLK_SET_RATE_PARENT, 5866 .ops = &clk_branch2_ops, 5867 }, 5868 }, 5869 }; 5870 5871 static struct clk_branch gcc_usb4_0_cfg_ahb_clk = { 5872 .halt_reg = 0x9f0a8, 5873 .halt_check = BRANCH_HALT_VOTED, 5874 .hwcg_reg = 0x9f0a8, 5875 .hwcg_bit = 1, 5876 .clkr = { 5877 .enable_reg = 0x9f0a8, 5878 .enable_mask = BIT(0), 5879 .hw.init = &(const struct clk_init_data) { 5880 .name = "gcc_usb4_0_cfg_ahb_clk", 5881 .ops = &clk_branch2_ops, 5882 }, 5883 }, 5884 }; 5885 5886 static struct clk_branch gcc_usb4_0_dp0_clk = { 5887 .halt_reg = 0x9f060, 5888 .halt_check = BRANCH_HALT_SKIP, 5889 .clkr = { 5890 .enable_reg = 0x9f060, 5891 .enable_mask = BIT(0), 5892 .hw.init = &(const struct clk_init_data) { 5893 .name = "gcc_usb4_0_dp0_clk", 5894 .parent_hws = (const struct clk_hw*[]) { 5895 &gcc_usb4_0_phy_dp0_clk_src.clkr.hw, 5896 }, 5897 .num_parents = 1, 5898 .flags = CLK_SET_RATE_PARENT, 5899 .ops = &clk_branch2_ops, 5900 }, 5901 }, 5902 }; 5903 5904 static struct clk_branch gcc_usb4_0_dp1_clk = { 5905 .halt_reg = 0x9f108, 5906 .halt_check = BRANCH_HALT_SKIP, 5907 .clkr = { 5908 .enable_reg = 0x9f108, 5909 .enable_mask = BIT(0), 5910 .hw.init = &(const struct clk_init_data) { 5911 .name = "gcc_usb4_0_dp1_clk", 5912 .parent_hws = (const struct clk_hw*[]) { 5913 &gcc_usb4_0_phy_dp1_clk_src.clkr.hw, 5914 }, 5915 .num_parents = 1, 5916 .flags = CLK_SET_RATE_PARENT, 5917 .ops = &clk_branch2_ops, 5918 }, 5919 }, 5920 }; 5921 5922 static struct clk_branch gcc_usb4_0_master_clk = { 5923 .halt_reg = 0x9f018, 5924 .halt_check = BRANCH_HALT, 5925 .clkr = { 5926 .enable_reg = 0x9f018, 5927 .enable_mask = BIT(0), 5928 .hw.init = &(const struct clk_init_data) { 5929 .name = "gcc_usb4_0_master_clk", 5930 .parent_hws = (const struct clk_hw*[]) { 5931 &gcc_usb4_0_master_clk_src.clkr.hw, 5932 }, 5933 .num_parents = 1, 5934 .flags = CLK_SET_RATE_PARENT, 5935 .ops = &clk_branch2_ops, 5936 }, 5937 }, 5938 }; 5939 5940 static struct clk_branch gcc_usb4_0_phy_p2rr2p_pipe_clk = { 5941 .halt_reg = 0x9f0d8, 5942 .halt_check = BRANCH_HALT_SKIP, 5943 .clkr = { 5944 .enable_reg = 0x9f0d8, 5945 .enable_mask = BIT(0), 5946 .hw.init = &(const struct clk_init_data) { 5947 .name = "gcc_usb4_0_phy_p2rr2p_pipe_clk", 5948 .parent_hws = (const struct clk_hw*[]) { 5949 &gcc_usb4_0_phy_p2rr2p_pipe_clk_src.clkr.hw, 5950 }, 5951 .num_parents = 1, 5952 .flags = CLK_SET_RATE_PARENT, 5953 .ops = &clk_branch2_ops, 5954 }, 5955 }, 5956 }; 5957 5958 static struct clk_branch gcc_usb4_0_phy_pcie_pipe_clk = { 5959 .halt_reg = 0x9f048, 5960 .halt_check = BRANCH_HALT_SKIP, 5961 .clkr = { 5962 .enable_reg = 0x52010, 5963 .enable_mask = BIT(19), 5964 .hw.init = &(const struct clk_init_data) { 5965 .name = "gcc_usb4_0_phy_pcie_pipe_clk", 5966 .parent_hws = (const struct clk_hw*[]) { 5967 &gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr.hw, 5968 }, 5969 .num_parents = 1, 5970 .flags = CLK_SET_RATE_PARENT, 5971 .ops = &clk_branch2_ops, 5972 }, 5973 }, 5974 }; 5975 5976 static struct clk_branch gcc_usb4_0_phy_rx0_clk = { 5977 .halt_reg = 0x9f0b0, 5978 .halt_check = BRANCH_HALT_SKIP, 5979 .clkr = { 5980 .enable_reg = 0x9f0b0, 5981 .enable_mask = BIT(0), 5982 .hw.init = &(const struct clk_init_data) { 5983 .name = "gcc_usb4_0_phy_rx0_clk", 5984 .parent_hws = (const struct clk_hw*[]) { 5985 &gcc_usb4_0_phy_rx0_clk_src.clkr.hw, 5986 }, 5987 .num_parents = 1, 5988 .flags = CLK_SET_RATE_PARENT, 5989 .ops = &clk_branch2_ops, 5990 }, 5991 }, 5992 }; 5993 5994 static struct clk_branch gcc_usb4_0_phy_rx1_clk = { 5995 .halt_reg = 0x9f0c0, 5996 .halt_check = BRANCH_HALT_SKIP, 5997 .clkr = { 5998 .enable_reg = 0x9f0c0, 5999 .enable_mask = BIT(0), 6000 .hw.init = &(const struct clk_init_data) { 6001 .name = "gcc_usb4_0_phy_rx1_clk", 6002 .parent_hws = (const struct clk_hw*[]) { 6003 &gcc_usb4_0_phy_rx1_clk_src.clkr.hw, 6004 }, 6005 .num_parents = 1, 6006 .flags = CLK_SET_RATE_PARENT, 6007 .ops = &clk_branch2_ops, 6008 }, 6009 }, 6010 }; 6011 6012 static struct clk_branch gcc_usb4_0_phy_usb_pipe_clk = { 6013 .halt_reg = 0x9f0a4, 6014 .halt_check = BRANCH_HALT_SKIP, 6015 .hwcg_reg = 0x9f0a4, 6016 .hwcg_bit = 1, 6017 .clkr = { 6018 .enable_reg = 0x9f0a4, 6019 .enable_mask = BIT(0), 6020 .hw.init = &(const struct clk_init_data) { 6021 .name = "gcc_usb4_0_phy_usb_pipe_clk", 6022 .parent_hws = (const struct clk_hw*[]) { 6023 &gcc_usb34_prim_phy_pipe_clk_src.clkr.hw, 6024 }, 6025 .num_parents = 1, 6026 .flags = CLK_SET_RATE_PARENT, 6027 .ops = &clk_branch2_ops, 6028 }, 6029 }, 6030 }; 6031 6032 static struct clk_branch gcc_usb4_0_sb_if_clk = { 6033 .halt_reg = 0x9f044, 6034 .halt_check = BRANCH_HALT, 6035 .clkr = { 6036 .enable_reg = 0x9f044, 6037 .enable_mask = BIT(0), 6038 .hw.init = &(const struct clk_init_data) { 6039 .name = "gcc_usb4_0_sb_if_clk", 6040 .parent_hws = (const struct clk_hw*[]) { 6041 &gcc_usb4_0_sb_if_clk_src.clkr.hw, 6042 }, 6043 .num_parents = 1, 6044 .flags = CLK_SET_RATE_PARENT, 6045 .ops = &clk_branch2_ops, 6046 }, 6047 }, 6048 }; 6049 6050 static struct clk_branch gcc_usb4_0_sys_clk = { 6051 .halt_reg = 0x9f054, 6052 .halt_check = BRANCH_HALT, 6053 .clkr = { 6054 .enable_reg = 0x9f054, 6055 .enable_mask = BIT(0), 6056 .hw.init = &(const struct clk_init_data) { 6057 .name = "gcc_usb4_0_sys_clk", 6058 .parent_hws = (const struct clk_hw*[]) { 6059 &gcc_usb4_0_phy_sys_clk_src.clkr.hw, 6060 }, 6061 .num_parents = 1, 6062 .flags = CLK_SET_RATE_PARENT, 6063 .ops = &clk_branch2_ops, 6064 }, 6065 }, 6066 }; 6067 6068 static struct clk_branch gcc_usb4_0_tmu_clk = { 6069 .halt_reg = 0x9f088, 6070 .halt_check = BRANCH_HALT_VOTED, 6071 .hwcg_reg = 0x9f088, 6072 .hwcg_bit = 1, 6073 .clkr = { 6074 .enable_reg = 0x9f088, 6075 .enable_mask = BIT(0), 6076 .hw.init = &(const struct clk_init_data) { 6077 .name = "gcc_usb4_0_tmu_clk", 6078 .parent_hws = (const struct clk_hw*[]) { 6079 &gcc_usb4_0_tmu_clk_src.clkr.hw, 6080 }, 6081 .num_parents = 1, 6082 .flags = CLK_SET_RATE_PARENT, 6083 .ops = &clk_branch2_ops, 6084 }, 6085 }, 6086 }; 6087 6088 static struct clk_branch gcc_usb4_1_cfg_ahb_clk = { 6089 .halt_reg = 0x2b0a8, 6090 .halt_check = BRANCH_HALT_VOTED, 6091 .hwcg_reg = 0x2b0a8, 6092 .hwcg_bit = 1, 6093 .clkr = { 6094 .enable_reg = 0x2b0a8, 6095 .enable_mask = BIT(0), 6096 .hw.init = &(const struct clk_init_data) { 6097 .name = "gcc_usb4_1_cfg_ahb_clk", 6098 .ops = &clk_branch2_ops, 6099 }, 6100 }, 6101 }; 6102 6103 static struct clk_branch gcc_usb4_1_dp0_clk = { 6104 .halt_reg = 0x2b060, 6105 .halt_check = BRANCH_HALT_SKIP, 6106 .clkr = { 6107 .enable_reg = 0x2b060, 6108 .enable_mask = BIT(0), 6109 .hw.init = &(const struct clk_init_data) { 6110 .name = "gcc_usb4_1_dp0_clk", 6111 .parent_hws = (const struct clk_hw*[]) { 6112 &gcc_usb4_1_phy_dp0_clk_src.clkr.hw, 6113 }, 6114 .num_parents = 1, 6115 .flags = CLK_SET_RATE_PARENT, 6116 .ops = &clk_branch2_ops, 6117 }, 6118 }, 6119 }; 6120 6121 static struct clk_branch gcc_usb4_1_dp1_clk = { 6122 .halt_reg = 0x2b108, 6123 .halt_check = BRANCH_HALT_SKIP, 6124 .clkr = { 6125 .enable_reg = 0x2b108, 6126 .enable_mask = BIT(0), 6127 .hw.init = &(const struct clk_init_data) { 6128 .name = "gcc_usb4_1_dp1_clk", 6129 .parent_hws = (const struct clk_hw*[]) { 6130 &gcc_usb4_1_phy_dp1_clk_src.clkr.hw, 6131 }, 6132 .num_parents = 1, 6133 .flags = CLK_SET_RATE_PARENT, 6134 .ops = &clk_branch2_ops, 6135 }, 6136 }, 6137 }; 6138 6139 static struct clk_branch gcc_usb4_1_master_clk = { 6140 .halt_reg = 0x2b018, 6141 .halt_check = BRANCH_HALT, 6142 .clkr = { 6143 .enable_reg = 0x2b018, 6144 .enable_mask = BIT(0), 6145 .hw.init = &(const struct clk_init_data) { 6146 .name = "gcc_usb4_1_master_clk", 6147 .parent_hws = (const struct clk_hw*[]) { 6148 &gcc_usb4_1_master_clk_src.clkr.hw, 6149 }, 6150 .num_parents = 1, 6151 .flags = CLK_SET_RATE_PARENT, 6152 .ops = &clk_branch2_ops, 6153 }, 6154 }, 6155 }; 6156 6157 static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = { 6158 .halt_reg = 0x2b0d8, 6159 .halt_check = BRANCH_HALT_SKIP, 6160 .clkr = { 6161 .enable_reg = 0x2b0d8, 6162 .enable_mask = BIT(0), 6163 .hw.init = &(const struct clk_init_data) { 6164 .name = "gcc_usb4_1_phy_p2rr2p_pipe_clk", 6165 .parent_hws = (const struct clk_hw*[]) { 6166 &gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr.hw, 6167 }, 6168 .num_parents = 1, 6169 .flags = CLK_SET_RATE_PARENT, 6170 .ops = &clk_branch2_ops, 6171 }, 6172 }, 6173 }; 6174 6175 static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk = { 6176 .halt_reg = 0x2b048, 6177 .halt_check = BRANCH_HALT_SKIP, 6178 .clkr = { 6179 .enable_reg = 0x52028, 6180 .enable_mask = BIT(0), 6181 .hw.init = &(const struct clk_init_data) { 6182 .name = "gcc_usb4_1_phy_pcie_pipe_clk", 6183 .parent_hws = (const struct clk_hw*[]) { 6184 &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw, 6185 }, 6186 .num_parents = 1, 6187 .flags = CLK_SET_RATE_PARENT, 6188 .ops = &clk_branch2_ops, 6189 }, 6190 }, 6191 }; 6192 6193 static struct clk_branch gcc_usb4_1_phy_rx0_clk = { 6194 .halt_reg = 0x2b0b0, 6195 .halt_check = BRANCH_HALT_SKIP, 6196 .clkr = { 6197 .enable_reg = 0x2b0b0, 6198 .enable_mask = BIT(0), 6199 .hw.init = &(const struct clk_init_data) { 6200 .name = "gcc_usb4_1_phy_rx0_clk", 6201 .parent_hws = (const struct clk_hw*[]) { 6202 &gcc_usb4_1_phy_rx0_clk_src.clkr.hw, 6203 }, 6204 .num_parents = 1, 6205 .flags = CLK_SET_RATE_PARENT, 6206 .ops = &clk_branch2_ops, 6207 }, 6208 }, 6209 }; 6210 6211 static struct clk_branch gcc_usb4_1_phy_rx1_clk = { 6212 .halt_reg = 0x2b0c0, 6213 .halt_check = BRANCH_HALT_SKIP, 6214 .clkr = { 6215 .enable_reg = 0x2b0c0, 6216 .enable_mask = BIT(0), 6217 .hw.init = &(const struct clk_init_data) { 6218 .name = "gcc_usb4_1_phy_rx1_clk", 6219 .parent_hws = (const struct clk_hw*[]) { 6220 &gcc_usb4_1_phy_rx1_clk_src.clkr.hw, 6221 }, 6222 .num_parents = 1, 6223 .flags = CLK_SET_RATE_PARENT, 6224 .ops = &clk_branch2_ops, 6225 }, 6226 }, 6227 }; 6228 6229 static struct clk_branch gcc_usb4_1_phy_usb_pipe_clk = { 6230 .halt_reg = 0x2b0a4, 6231 .halt_check = BRANCH_HALT_SKIP, 6232 .hwcg_reg = 0x2b0a4, 6233 .hwcg_bit = 1, 6234 .clkr = { 6235 .enable_reg = 0x2b0a4, 6236 .enable_mask = BIT(0), 6237 .hw.init = &(const struct clk_init_data) { 6238 .name = "gcc_usb4_1_phy_usb_pipe_clk", 6239 .parent_hws = (const struct clk_hw*[]) { 6240 &gcc_usb34_sec_phy_pipe_clk_src.clkr.hw, 6241 }, 6242 .num_parents = 1, 6243 .flags = CLK_SET_RATE_PARENT, 6244 .ops = &clk_branch2_ops, 6245 }, 6246 }, 6247 }; 6248 6249 static struct clk_branch gcc_usb4_1_sb_if_clk = { 6250 .halt_reg = 0x2b044, 6251 .halt_check = BRANCH_HALT, 6252 .clkr = { 6253 .enable_reg = 0x2b044, 6254 .enable_mask = BIT(0), 6255 .hw.init = &(const struct clk_init_data) { 6256 .name = "gcc_usb4_1_sb_if_clk", 6257 .parent_hws = (const struct clk_hw*[]) { 6258 &gcc_usb4_1_sb_if_clk_src.clkr.hw, 6259 }, 6260 .num_parents = 1, 6261 .flags = CLK_SET_RATE_PARENT, 6262 .ops = &clk_branch2_ops, 6263 }, 6264 }, 6265 }; 6266 6267 static struct clk_branch gcc_usb4_1_sys_clk = { 6268 .halt_reg = 0x2b054, 6269 .halt_check = BRANCH_HALT, 6270 .clkr = { 6271 .enable_reg = 0x2b054, 6272 .enable_mask = BIT(0), 6273 .hw.init = &(const struct clk_init_data) { 6274 .name = "gcc_usb4_1_sys_clk", 6275 .parent_hws = (const struct clk_hw*[]) { 6276 &gcc_usb4_1_phy_sys_clk_src.clkr.hw, 6277 }, 6278 .num_parents = 1, 6279 .flags = CLK_SET_RATE_PARENT, 6280 .ops = &clk_branch2_ops, 6281 }, 6282 }, 6283 }; 6284 6285 static struct clk_branch gcc_usb4_1_tmu_clk = { 6286 .halt_reg = 0x2b088, 6287 .halt_check = BRANCH_HALT_VOTED, 6288 .hwcg_reg = 0x2b088, 6289 .hwcg_bit = 1, 6290 .clkr = { 6291 .enable_reg = 0x2b088, 6292 .enable_mask = BIT(0), 6293 .hw.init = &(const struct clk_init_data) { 6294 .name = "gcc_usb4_1_tmu_clk", 6295 .parent_hws = (const struct clk_hw*[]) { 6296 &gcc_usb4_1_tmu_clk_src.clkr.hw, 6297 }, 6298 .num_parents = 1, 6299 .flags = CLK_SET_RATE_PARENT, 6300 .ops = &clk_branch2_ops, 6301 }, 6302 }, 6303 }; 6304 6305 static struct clk_branch gcc_usb4_2_cfg_ahb_clk = { 6306 .halt_reg = 0x110a8, 6307 .halt_check = BRANCH_HALT_VOTED, 6308 .hwcg_reg = 0x110a8, 6309 .hwcg_bit = 1, 6310 .clkr = { 6311 .enable_reg = 0x110a8, 6312 .enable_mask = BIT(0), 6313 .hw.init = &(const struct clk_init_data) { 6314 .name = "gcc_usb4_2_cfg_ahb_clk", 6315 .ops = &clk_branch2_ops, 6316 }, 6317 }, 6318 }; 6319 6320 static struct clk_branch gcc_usb4_2_dp0_clk = { 6321 .halt_reg = 0x11060, 6322 .halt_check = BRANCH_HALT_SKIP, 6323 .clkr = { 6324 .enable_reg = 0x11060, 6325 .enable_mask = BIT(0), 6326 .hw.init = &(const struct clk_init_data) { 6327 .name = "gcc_usb4_2_dp0_clk", 6328 .parent_hws = (const struct clk_hw*[]) { 6329 &gcc_usb4_2_phy_dp0_clk_src.clkr.hw, 6330 }, 6331 .num_parents = 1, 6332 .flags = CLK_SET_RATE_PARENT, 6333 .ops = &clk_branch2_ops, 6334 }, 6335 }, 6336 }; 6337 6338 static struct clk_branch gcc_usb4_2_dp1_clk = { 6339 .halt_reg = 0x11108, 6340 .halt_check = BRANCH_HALT_SKIP, 6341 .clkr = { 6342 .enable_reg = 0x11108, 6343 .enable_mask = BIT(0), 6344 .hw.init = &(const struct clk_init_data) { 6345 .name = "gcc_usb4_2_dp1_clk", 6346 .parent_hws = (const struct clk_hw*[]) { 6347 &gcc_usb4_2_phy_dp1_clk_src.clkr.hw, 6348 }, 6349 .num_parents = 1, 6350 .flags = CLK_SET_RATE_PARENT, 6351 .ops = &clk_branch2_ops, 6352 }, 6353 }, 6354 }; 6355 6356 static struct clk_branch gcc_usb4_2_master_clk = { 6357 .halt_reg = 0x11018, 6358 .halt_check = BRANCH_HALT, 6359 .clkr = { 6360 .enable_reg = 0x11018, 6361 .enable_mask = BIT(0), 6362 .hw.init = &(const struct clk_init_data) { 6363 .name = "gcc_usb4_2_master_clk", 6364 .parent_hws = (const struct clk_hw*[]) { 6365 &gcc_usb4_2_master_clk_src.clkr.hw, 6366 }, 6367 .num_parents = 1, 6368 .flags = CLK_SET_RATE_PARENT, 6369 .ops = &clk_branch2_ops, 6370 }, 6371 }, 6372 }; 6373 6374 static struct clk_branch gcc_usb4_2_phy_p2rr2p_pipe_clk = { 6375 .halt_reg = 0x110d8, 6376 .halt_check = BRANCH_HALT_SKIP, 6377 .clkr = { 6378 .enable_reg = 0x110d8, 6379 .enable_mask = BIT(0), 6380 .hw.init = &(const struct clk_init_data) { 6381 .name = "gcc_usb4_2_phy_p2rr2p_pipe_clk", 6382 .parent_hws = (const struct clk_hw*[]) { 6383 &gcc_usb4_2_phy_p2rr2p_pipe_clk_src.clkr.hw, 6384 }, 6385 .num_parents = 1, 6386 .flags = CLK_SET_RATE_PARENT, 6387 .ops = &clk_branch2_ops, 6388 }, 6389 }, 6390 }; 6391 6392 static struct clk_branch gcc_usb4_2_phy_pcie_pipe_clk = { 6393 .halt_reg = 0x11048, 6394 .halt_check = BRANCH_HALT_SKIP, 6395 .clkr = { 6396 .enable_reg = 0x52028, 6397 .enable_mask = BIT(1), 6398 .hw.init = &(const struct clk_init_data) { 6399 .name = "gcc_usb4_2_phy_pcie_pipe_clk", 6400 .parent_hws = (const struct clk_hw*[]) { 6401 &gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr.hw, 6402 }, 6403 .num_parents = 1, 6404 .flags = CLK_SET_RATE_PARENT, 6405 .ops = &clk_branch2_ops, 6406 }, 6407 }, 6408 }; 6409 6410 static struct clk_branch gcc_usb4_2_phy_rx0_clk = { 6411 .halt_reg = 0x110b0, 6412 .halt_check = BRANCH_HALT_SKIP, 6413 .clkr = { 6414 .enable_reg = 0x110b0, 6415 .enable_mask = BIT(0), 6416 .hw.init = &(const struct clk_init_data) { 6417 .name = "gcc_usb4_2_phy_rx0_clk", 6418 .parent_hws = (const struct clk_hw*[]) { 6419 &gcc_usb4_2_phy_rx0_clk_src.clkr.hw, 6420 }, 6421 .num_parents = 1, 6422 .flags = CLK_SET_RATE_PARENT, 6423 .ops = &clk_branch2_ops, 6424 }, 6425 }, 6426 }; 6427 6428 static struct clk_branch gcc_usb4_2_phy_rx1_clk = { 6429 .halt_reg = 0x110c0, 6430 .halt_check = BRANCH_HALT_SKIP, 6431 .clkr = { 6432 .enable_reg = 0x110c0, 6433 .enable_mask = BIT(0), 6434 .hw.init = &(const struct clk_init_data) { 6435 .name = "gcc_usb4_2_phy_rx1_clk", 6436 .parent_hws = (const struct clk_hw*[]) { 6437 &gcc_usb4_2_phy_rx1_clk_src.clkr.hw, 6438 }, 6439 .num_parents = 1, 6440 .flags = CLK_SET_RATE_PARENT, 6441 .ops = &clk_branch2_ops, 6442 }, 6443 }, 6444 }; 6445 6446 static struct clk_branch gcc_usb4_2_phy_usb_pipe_clk = { 6447 .halt_reg = 0x110a4, 6448 .halt_check = BRANCH_HALT_SKIP, 6449 .hwcg_reg = 0x110a4, 6450 .hwcg_bit = 1, 6451 .clkr = { 6452 .enable_reg = 0x110a4, 6453 .enable_mask = BIT(0), 6454 .hw.init = &(const struct clk_init_data) { 6455 .name = "gcc_usb4_2_phy_usb_pipe_clk", 6456 .parent_hws = (const struct clk_hw*[]) { 6457 &gcc_usb34_tert_phy_pipe_clk_src.clkr.hw, 6458 }, 6459 .num_parents = 1, 6460 .flags = CLK_SET_RATE_PARENT, 6461 .ops = &clk_branch2_ops, 6462 }, 6463 }, 6464 }; 6465 6466 static struct clk_branch gcc_usb4_2_sb_if_clk = { 6467 .halt_reg = 0x11044, 6468 .halt_check = BRANCH_HALT, 6469 .clkr = { 6470 .enable_reg = 0x11044, 6471 .enable_mask = BIT(0), 6472 .hw.init = &(const struct clk_init_data) { 6473 .name = "gcc_usb4_2_sb_if_clk", 6474 .parent_hws = (const struct clk_hw*[]) { 6475 &gcc_usb4_2_sb_if_clk_src.clkr.hw, 6476 }, 6477 .num_parents = 1, 6478 .flags = CLK_SET_RATE_PARENT, 6479 .ops = &clk_branch2_ops, 6480 }, 6481 }, 6482 }; 6483 6484 static struct clk_branch gcc_usb4_2_sys_clk = { 6485 .halt_reg = 0x11054, 6486 .halt_check = BRANCH_HALT, 6487 .clkr = { 6488 .enable_reg = 0x11054, 6489 .enable_mask = BIT(0), 6490 .hw.init = &(const struct clk_init_data) { 6491 .name = "gcc_usb4_2_sys_clk", 6492 .ops = &clk_branch2_ops, 6493 }, 6494 }, 6495 }; 6496 6497 static struct clk_branch gcc_usb4_2_tmu_clk = { 6498 .halt_reg = 0x11088, 6499 .halt_check = BRANCH_HALT_VOTED, 6500 .hwcg_reg = 0x11088, 6501 .hwcg_bit = 1, 6502 .clkr = { 6503 .enable_reg = 0x11088, 6504 .enable_mask = BIT(0), 6505 .hw.init = &(const struct clk_init_data) { 6506 .name = "gcc_usb4_2_tmu_clk", 6507 .parent_hws = (const struct clk_hw*[]) { 6508 &gcc_usb4_2_tmu_clk_src.clkr.hw, 6509 }, 6510 .num_parents = 1, 6511 .flags = CLK_SET_RATE_PARENT, 6512 .ops = &clk_branch2_ops, 6513 }, 6514 }, 6515 }; 6516 6517 static struct clk_branch gcc_video_axi0_clk = { 6518 .halt_reg = 0x32018, 6519 .halt_check = BRANCH_HALT_SKIP, 6520 .hwcg_reg = 0x32018, 6521 .hwcg_bit = 1, 6522 .clkr = { 6523 .enable_reg = 0x32018, 6524 .enable_mask = BIT(0), 6525 .hw.init = &(const struct clk_init_data) { 6526 .name = "gcc_video_axi0_clk", 6527 .ops = &clk_branch2_ops, 6528 }, 6529 }, 6530 }; 6531 6532 static struct clk_branch gcc_video_axi1_clk = { 6533 .halt_reg = 0x32024, 6534 .halt_check = BRANCH_HALT_SKIP, 6535 .hwcg_reg = 0x32024, 6536 .hwcg_bit = 1, 6537 .clkr = { 6538 .enable_reg = 0x32024, 6539 .enable_mask = BIT(0), 6540 .hw.init = &(const struct clk_init_data) { 6541 .name = "gcc_video_axi1_clk", 6542 .ops = &clk_branch2_ops, 6543 }, 6544 }, 6545 }; 6546 6547 static struct gdsc gcc_pcie_0_tunnel_gdsc = { 6548 .gdscr = 0xa0004, 6549 .en_rest_wait_val = 0x2, 6550 .en_few_wait_val = 0x2, 6551 .clk_dis_wait_val = 0xf, 6552 .pd = { 6553 .name = "gcc_pcie_0_tunnel_gdsc", 6554 }, 6555 .pwrsts = PWRSTS_OFF_ON, 6556 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 6557 }; 6558 6559 static struct gdsc gcc_pcie_1_tunnel_gdsc = { 6560 .gdscr = 0x2c004, 6561 .en_rest_wait_val = 0x2, 6562 .en_few_wait_val = 0x2, 6563 .clk_dis_wait_val = 0xf, 6564 .pd = { 6565 .name = "gcc_pcie_1_tunnel_gdsc", 6566 }, 6567 .pwrsts = PWRSTS_OFF_ON, 6568 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 6569 }; 6570 6571 static struct gdsc gcc_pcie_2_tunnel_gdsc = { 6572 .gdscr = 0x13004, 6573 .en_rest_wait_val = 0x2, 6574 .en_few_wait_val = 0x2, 6575 .clk_dis_wait_val = 0xf, 6576 .pd = { 6577 .name = "gcc_pcie_2_tunnel_gdsc", 6578 }, 6579 .pwrsts = PWRSTS_OFF_ON, 6580 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 6581 }; 6582 6583 static struct gdsc gcc_pcie_3_gdsc = { 6584 .gdscr = 0x58004, 6585 .en_rest_wait_val = 0x2, 6586 .en_few_wait_val = 0x2, 6587 .clk_dis_wait_val = 0xf, 6588 .pd = { 6589 .name = "gcc_pcie_3_gdsc", 6590 }, 6591 .pwrsts = PWRSTS_OFF_ON, 6592 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 6593 }; 6594 6595 static struct gdsc gcc_pcie_3_phy_gdsc = { 6596 .gdscr = 0x3e000, 6597 .en_rest_wait_val = 0x2, 6598 .en_few_wait_val = 0x2, 6599 .clk_dis_wait_val = 0x2, 6600 .pd = { 6601 .name = "gcc_pcie_3_phy_gdsc", 6602 }, 6603 .pwrsts = PWRSTS_OFF_ON, 6604 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 6605 }; 6606 6607 static struct gdsc gcc_pcie_4_gdsc = { 6608 .gdscr = 0x6b004, 6609 .en_rest_wait_val = 0x2, 6610 .en_few_wait_val = 0x2, 6611 .clk_dis_wait_val = 0xf, 6612 .pd = { 6613 .name = "gcc_pcie_4_gdsc", 6614 }, 6615 .pwrsts = PWRSTS_OFF_ON, 6616 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 6617 }; 6618 6619 static struct gdsc gcc_pcie_4_phy_gdsc = { 6620 .gdscr = 0x6c000, 6621 .en_rest_wait_val = 0x2, 6622 .en_few_wait_val = 0x2, 6623 .clk_dis_wait_val = 0x2, 6624 .pd = { 6625 .name = "gcc_pcie_4_phy_gdsc", 6626 }, 6627 .pwrsts = PWRSTS_OFF_ON, 6628 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 6629 }; 6630 6631 static struct gdsc gcc_pcie_5_gdsc = { 6632 .gdscr = 0x2f004, 6633 .en_rest_wait_val = 0x2, 6634 .en_few_wait_val = 0x2, 6635 .clk_dis_wait_val = 0xf, 6636 .pd = { 6637 .name = "gcc_pcie_5_gdsc", 6638 }, 6639 .pwrsts = PWRSTS_OFF_ON, 6640 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 6641 }; 6642 6643 static struct gdsc gcc_pcie_5_phy_gdsc = { 6644 .gdscr = 0x30000, 6645 .en_rest_wait_val = 0x2, 6646 .en_few_wait_val = 0x2, 6647 .clk_dis_wait_val = 0x2, 6648 .pd = { 6649 .name = "gcc_pcie_5_phy_gdsc", 6650 }, 6651 .pwrsts = PWRSTS_OFF_ON, 6652 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 6653 }; 6654 6655 static struct gdsc gcc_pcie_6_phy_gdsc = { 6656 .gdscr = 0x8e000, 6657 .en_rest_wait_val = 0x2, 6658 .en_few_wait_val = 0x2, 6659 .clk_dis_wait_val = 0x2, 6660 .pd = { 6661 .name = "gcc_pcie_6_phy_gdsc", 6662 }, 6663 .pwrsts = PWRSTS_OFF_ON, 6664 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 6665 }; 6666 6667 static struct gdsc gcc_pcie_6a_gdsc = { 6668 .gdscr = 0x31004, 6669 .en_rest_wait_val = 0x2, 6670 .en_few_wait_val = 0x2, 6671 .clk_dis_wait_val = 0xf, 6672 .pd = { 6673 .name = "gcc_pcie_6a_gdsc", 6674 }, 6675 .pwrsts = PWRSTS_OFF_ON, 6676 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 6677 }; 6678 6679 static struct gdsc gcc_pcie_6b_gdsc = { 6680 .gdscr = 0x8d004, 6681 .en_rest_wait_val = 0x2, 6682 .en_few_wait_val = 0x2, 6683 .clk_dis_wait_val = 0xf, 6684 .pd = { 6685 .name = "gcc_pcie_6b_gdsc", 6686 }, 6687 .pwrsts = PWRSTS_OFF_ON, 6688 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 6689 }; 6690 6691 static struct gdsc gcc_ufs_mem_phy_gdsc = { 6692 .gdscr = 0x9e000, 6693 .en_rest_wait_val = 0x2, 6694 .en_few_wait_val = 0x2, 6695 .clk_dis_wait_val = 0x2, 6696 .pd = { 6697 .name = "gcc_ufs_mem_phy_gdsc", 6698 }, 6699 .pwrsts = PWRSTS_OFF_ON, 6700 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6701 }; 6702 6703 static struct gdsc gcc_ufs_phy_gdsc = { 6704 .gdscr = 0x77004, 6705 .en_rest_wait_val = 0x2, 6706 .en_few_wait_val = 0x2, 6707 .clk_dis_wait_val = 0xf, 6708 .pd = { 6709 .name = "gcc_ufs_phy_gdsc", 6710 }, 6711 .pwrsts = PWRSTS_OFF_ON, 6712 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6713 }; 6714 6715 static struct gdsc gcc_usb20_prim_gdsc = { 6716 .gdscr = 0x29004, 6717 .en_rest_wait_val = 0x2, 6718 .en_few_wait_val = 0x2, 6719 .clk_dis_wait_val = 0xf, 6720 .pd = { 6721 .name = "gcc_usb20_prim_gdsc", 6722 }, 6723 .pwrsts = PWRSTS_RET_ON, 6724 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6725 }; 6726 6727 static struct gdsc gcc_usb30_mp_gdsc = { 6728 .gdscr = 0x17004, 6729 .en_rest_wait_val = 0x2, 6730 .en_few_wait_val = 0x2, 6731 .clk_dis_wait_val = 0xf, 6732 .pd = { 6733 .name = "gcc_usb30_mp_gdsc", 6734 }, 6735 .pwrsts = PWRSTS_RET_ON, 6736 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6737 }; 6738 6739 static struct gdsc gcc_usb30_prim_gdsc = { 6740 .gdscr = 0x39004, 6741 .en_rest_wait_val = 0x2, 6742 .en_few_wait_val = 0x2, 6743 .clk_dis_wait_val = 0xf, 6744 .pd = { 6745 .name = "gcc_usb30_prim_gdsc", 6746 }, 6747 .pwrsts = PWRSTS_RET_ON, 6748 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6749 }; 6750 6751 static struct gdsc gcc_usb30_sec_gdsc = { 6752 .gdscr = 0xa1004, 6753 .en_rest_wait_val = 0x2, 6754 .en_few_wait_val = 0x2, 6755 .clk_dis_wait_val = 0xf, 6756 .pd = { 6757 .name = "gcc_usb30_sec_gdsc", 6758 }, 6759 .pwrsts = PWRSTS_RET_ON, 6760 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6761 }; 6762 6763 static struct gdsc gcc_usb30_tert_gdsc = { 6764 .gdscr = 0xa2004, 6765 .en_rest_wait_val = 0x2, 6766 .en_few_wait_val = 0x2, 6767 .clk_dis_wait_val = 0xf, 6768 .pd = { 6769 .name = "gcc_usb30_tert_gdsc", 6770 }, 6771 .pwrsts = PWRSTS_RET_ON, 6772 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6773 }; 6774 6775 static struct gdsc gcc_usb3_mp_ss0_phy_gdsc = { 6776 .gdscr = 0x1900c, 6777 .en_rest_wait_val = 0x2, 6778 .en_few_wait_val = 0x2, 6779 .clk_dis_wait_val = 0x2, 6780 .pd = { 6781 .name = "gcc_usb3_mp_ss0_phy_gdsc", 6782 }, 6783 .pwrsts = PWRSTS_RET_ON, 6784 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6785 }; 6786 6787 static struct gdsc gcc_usb3_mp_ss1_phy_gdsc = { 6788 .gdscr = 0x5400c, 6789 .en_rest_wait_val = 0x2, 6790 .en_few_wait_val = 0x2, 6791 .clk_dis_wait_val = 0x2, 6792 .pd = { 6793 .name = "gcc_usb3_mp_ss1_phy_gdsc", 6794 }, 6795 .pwrsts = PWRSTS_RET_ON, 6796 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6797 }; 6798 6799 static struct gdsc gcc_usb4_0_gdsc = { 6800 .gdscr = 0x9f004, 6801 .en_rest_wait_val = 0x2, 6802 .en_few_wait_val = 0x2, 6803 .clk_dis_wait_val = 0xf, 6804 .pd = { 6805 .name = "gcc_usb4_0_gdsc", 6806 }, 6807 .pwrsts = PWRSTS_OFF_ON, 6808 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6809 }; 6810 6811 static struct gdsc gcc_usb4_1_gdsc = { 6812 .gdscr = 0x2b004, 6813 .en_rest_wait_val = 0x2, 6814 .en_few_wait_val = 0x2, 6815 .clk_dis_wait_val = 0xf, 6816 .pd = { 6817 .name = "gcc_usb4_1_gdsc", 6818 }, 6819 .pwrsts = PWRSTS_OFF_ON, 6820 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6821 }; 6822 6823 static struct gdsc gcc_usb4_2_gdsc = { 6824 .gdscr = 0x11004, 6825 .en_rest_wait_val = 0x2, 6826 .en_few_wait_val = 0x2, 6827 .clk_dis_wait_val = 0xf, 6828 .pd = { 6829 .name = "gcc_usb4_2_gdsc", 6830 }, 6831 .pwrsts = PWRSTS_OFF_ON, 6832 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6833 }; 6834 6835 static struct gdsc gcc_usb_0_phy_gdsc = { 6836 .gdscr = 0x50024, 6837 .en_rest_wait_val = 0x2, 6838 .en_few_wait_val = 0x2, 6839 .clk_dis_wait_val = 0x2, 6840 .pd = { 6841 .name = "gcc_usb_0_phy_gdsc", 6842 }, 6843 .pwrsts = PWRSTS_RET_ON, 6844 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6845 }; 6846 6847 static struct gdsc gcc_usb_1_phy_gdsc = { 6848 .gdscr = 0x2a024, 6849 .en_rest_wait_val = 0x2, 6850 .en_few_wait_val = 0x2, 6851 .clk_dis_wait_val = 0x2, 6852 .pd = { 6853 .name = "gcc_usb_1_phy_gdsc", 6854 }, 6855 .pwrsts = PWRSTS_RET_ON, 6856 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6857 }; 6858 6859 static struct gdsc gcc_usb_2_phy_gdsc = { 6860 .gdscr = 0xa3024, 6861 .en_rest_wait_val = 0x2, 6862 .en_few_wait_val = 0x2, 6863 .clk_dis_wait_val = 0x2, 6864 .pd = { 6865 .name = "gcc_usb_2_phy_gdsc", 6866 }, 6867 .pwrsts = PWRSTS_RET_ON, 6868 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 6869 }; 6870 6871 static struct clk_regmap *gcc_x1e80100_clocks[] = { 6872 [GCC_AGGRE_NOC_USB_NORTH_AXI_CLK] = &gcc_aggre_noc_usb_north_axi_clk.clkr, 6873 [GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK] = &gcc_aggre_noc_usb_south_axi_clk.clkr, 6874 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 6875 [GCC_AGGRE_USB2_PRIM_AXI_CLK] = &gcc_aggre_usb2_prim_axi_clk.clkr, 6876 [GCC_AGGRE_USB3_MP_AXI_CLK] = &gcc_aggre_usb3_mp_axi_clk.clkr, 6877 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 6878 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, 6879 [GCC_AGGRE_USB3_TERT_AXI_CLK] = &gcc_aggre_usb3_tert_axi_clk.clkr, 6880 [GCC_AGGRE_USB4_0_AXI_CLK] = &gcc_aggre_usb4_0_axi_clk.clkr, 6881 [GCC_AGGRE_USB4_1_AXI_CLK] = &gcc_aggre_usb4_1_axi_clk.clkr, 6882 [GCC_AGGRE_USB4_2_AXI_CLK] = &gcc_aggre_usb4_2_axi_clk.clkr, 6883 [GCC_AGGRE_USB_NOC_AXI_CLK] = &gcc_aggre_usb_noc_axi_clk.clkr, 6884 [GCC_AV1E_AHB_CLK] = &gcc_av1e_ahb_clk.clkr, 6885 [GCC_AV1E_AXI_CLK] = &gcc_av1e_axi_clk.clkr, 6886 [GCC_AV1E_XO_CLK] = &gcc_av1e_xo_clk.clkr, 6887 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 6888 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 6889 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 6890 [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr, 6891 [GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_north_ahb_clk.clkr, 6892 [GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_south_ahb_clk.clkr, 6893 [GCC_CFG_NOC_USB2_PRIM_AXI_CLK] = &gcc_cfg_noc_usb2_prim_axi_clk.clkr, 6894 [GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr, 6895 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 6896 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, 6897 [GCC_CFG_NOC_USB3_TERT_AXI_CLK] = &gcc_cfg_noc_usb3_tert_axi_clk.clkr, 6898 [GCC_CFG_NOC_USB_ANOC_AHB_CLK] = &gcc_cfg_noc_usb_anoc_ahb_clk.clkr, 6899 [GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK] = &gcc_cfg_noc_usb_anoc_north_ahb_clk.clkr, 6900 [GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK] = &gcc_cfg_noc_usb_anoc_south_ahb_clk.clkr, 6901 [GCC_CNOC_PCIE1_TUNNEL_CLK] = &gcc_cnoc_pcie1_tunnel_clk.clkr, 6902 [GCC_CNOC_PCIE2_TUNNEL_CLK] = &gcc_cnoc_pcie2_tunnel_clk.clkr, 6903 [GCC_CNOC_PCIE_NORTH_SF_AXI_CLK] = &gcc_cnoc_pcie_north_sf_axi_clk.clkr, 6904 [GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK] = &gcc_cnoc_pcie_south_sf_axi_clk.clkr, 6905 [GCC_CNOC_PCIE_TUNNEL_CLK] = &gcc_cnoc_pcie_tunnel_clk.clkr, 6906 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 6907 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 6908 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 6909 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 6910 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 6911 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 6912 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 6913 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 6914 [GCC_GPLL0] = &gcc_gpll0.clkr, 6915 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 6916 [GCC_GPLL4] = &gcc_gpll4.clkr, 6917 [GCC_GPLL7] = &gcc_gpll7.clkr, 6918 [GCC_GPLL8] = &gcc_gpll8.clkr, 6919 [GCC_GPLL9] = &gcc_gpll9.clkr, 6920 [GCC_GPU_GPLL0_CPH_CLK_SRC] = &gcc_gpu_gpll0_cph_clk_src.clkr, 6921 [GCC_GPU_GPLL0_DIV_CPH_CLK_SRC] = &gcc_gpu_gpll0_div_cph_clk_src.clkr, 6922 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 6923 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 6924 [GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr, 6925 [GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr, 6926 [GCC_PCIE2_PHY_RCHNG_CLK] = &gcc_pcie2_phy_rchng_clk.clkr, 6927 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 6928 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 6929 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 6930 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 6931 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 6932 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 6933 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 6934 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 6935 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 6936 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 6937 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 6938 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 6939 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, 6940 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 6941 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 6942 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 6943 [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr, 6944 [GCC_PCIE_2_AUX_CLK_SRC] = &gcc_pcie_2_aux_clk_src.clkr, 6945 [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr, 6946 [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr, 6947 [GCC_PCIE_2_PHY_RCHNG_CLK_SRC] = &gcc_pcie_2_phy_rchng_clk_src.clkr, 6948 [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr, 6949 [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr, 6950 [GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr, 6951 [GCC_PCIE_3_AUX_CLK] = &gcc_pcie_3_aux_clk.clkr, 6952 [GCC_PCIE_3_AUX_CLK_SRC] = &gcc_pcie_3_aux_clk_src.clkr, 6953 [GCC_PCIE_3_CFG_AHB_CLK] = &gcc_pcie_3_cfg_ahb_clk.clkr, 6954 [GCC_PCIE_3_MSTR_AXI_CLK] = &gcc_pcie_3_mstr_axi_clk.clkr, 6955 [GCC_PCIE_3_PHY_AUX_CLK] = &gcc_pcie_3_phy_aux_clk.clkr, 6956 [GCC_PCIE_3_PHY_RCHNG_CLK] = &gcc_pcie_3_phy_rchng_clk.clkr, 6957 [GCC_PCIE_3_PHY_RCHNG_CLK_SRC] = &gcc_pcie_3_phy_rchng_clk_src.clkr, 6958 [GCC_PCIE_3_PIPE_CLK] = &gcc_pcie_3_pipe_clk.clkr, 6959 [GCC_PCIE_3_PIPE_CLK_SRC] = &gcc_pcie_3_pipe_clk_src.clkr, 6960 [GCC_PCIE_3_PIPE_DIV_CLK_SRC] = &gcc_pcie_3_pipe_div_clk_src.clkr, 6961 [GCC_PCIE_3_PIPEDIV2_CLK] = &gcc_pcie_3_pipediv2_clk.clkr, 6962 [GCC_PCIE_3_SLV_AXI_CLK] = &gcc_pcie_3_slv_axi_clk.clkr, 6963 [GCC_PCIE_3_SLV_Q2A_AXI_CLK] = &gcc_pcie_3_slv_q2a_axi_clk.clkr, 6964 [GCC_PCIE_4_AUX_CLK] = &gcc_pcie_4_aux_clk.clkr, 6965 [GCC_PCIE_4_AUX_CLK_SRC] = &gcc_pcie_4_aux_clk_src.clkr, 6966 [GCC_PCIE_4_CFG_AHB_CLK] = &gcc_pcie_4_cfg_ahb_clk.clkr, 6967 [GCC_PCIE_4_MSTR_AXI_CLK] = &gcc_pcie_4_mstr_axi_clk.clkr, 6968 [GCC_PCIE_4_PHY_RCHNG_CLK] = &gcc_pcie_4_phy_rchng_clk.clkr, 6969 [GCC_PCIE_4_PHY_RCHNG_CLK_SRC] = &gcc_pcie_4_phy_rchng_clk_src.clkr, 6970 [GCC_PCIE_4_PIPE_CLK] = &gcc_pcie_4_pipe_clk.clkr, 6971 [GCC_PCIE_4_PIPE_CLK_SRC] = &gcc_pcie_4_pipe_clk_src.clkr, 6972 [GCC_PCIE_4_PIPE_DIV_CLK_SRC] = &gcc_pcie_4_pipe_div_clk_src.clkr, 6973 [GCC_PCIE_4_PIPEDIV2_CLK] = &gcc_pcie_4_pipediv2_clk.clkr, 6974 [GCC_PCIE_4_SLV_AXI_CLK] = &gcc_pcie_4_slv_axi_clk.clkr, 6975 [GCC_PCIE_4_SLV_Q2A_AXI_CLK] = &gcc_pcie_4_slv_q2a_axi_clk.clkr, 6976 [GCC_PCIE_5_AUX_CLK] = &gcc_pcie_5_aux_clk.clkr, 6977 [GCC_PCIE_5_AUX_CLK_SRC] = &gcc_pcie_5_aux_clk_src.clkr, 6978 [GCC_PCIE_5_CFG_AHB_CLK] = &gcc_pcie_5_cfg_ahb_clk.clkr, 6979 [GCC_PCIE_5_MSTR_AXI_CLK] = &gcc_pcie_5_mstr_axi_clk.clkr, 6980 [GCC_PCIE_5_PHY_RCHNG_CLK] = &gcc_pcie_5_phy_rchng_clk.clkr, 6981 [GCC_PCIE_5_PHY_RCHNG_CLK_SRC] = &gcc_pcie_5_phy_rchng_clk_src.clkr, 6982 [GCC_PCIE_5_PIPE_CLK] = &gcc_pcie_5_pipe_clk.clkr, 6983 [GCC_PCIE_5_PIPE_CLK_SRC] = &gcc_pcie_5_pipe_clk_src.clkr, 6984 [GCC_PCIE_5_PIPE_DIV_CLK_SRC] = &gcc_pcie_5_pipe_div_clk_src.clkr, 6985 [GCC_PCIE_5_PIPEDIV2_CLK] = &gcc_pcie_5_pipediv2_clk.clkr, 6986 [GCC_PCIE_5_SLV_AXI_CLK] = &gcc_pcie_5_slv_axi_clk.clkr, 6987 [GCC_PCIE_5_SLV_Q2A_AXI_CLK] = &gcc_pcie_5_slv_q2a_axi_clk.clkr, 6988 [GCC_PCIE_6A_AUX_CLK] = &gcc_pcie_6a_aux_clk.clkr, 6989 [GCC_PCIE_6A_AUX_CLK_SRC] = &gcc_pcie_6a_aux_clk_src.clkr, 6990 [GCC_PCIE_6A_CFG_AHB_CLK] = &gcc_pcie_6a_cfg_ahb_clk.clkr, 6991 [GCC_PCIE_6A_MSTR_AXI_CLK] = &gcc_pcie_6a_mstr_axi_clk.clkr, 6992 [GCC_PCIE_6A_PHY_AUX_CLK] = &gcc_pcie_6a_phy_aux_clk.clkr, 6993 [GCC_PCIE_6A_PHY_RCHNG_CLK] = &gcc_pcie_6a_phy_rchng_clk.clkr, 6994 [GCC_PCIE_6A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_6a_phy_rchng_clk_src.clkr, 6995 [GCC_PCIE_6A_PIPE_CLK] = &gcc_pcie_6a_pipe_clk.clkr, 6996 [GCC_PCIE_6A_PIPE_CLK_SRC] = &gcc_pcie_6a_pipe_clk_src.clkr, 6997 [GCC_PCIE_6A_PIPE_DIV_CLK_SRC] = &gcc_pcie_6a_pipe_div_clk_src.clkr, 6998 [GCC_PCIE_6A_PIPEDIV2_CLK] = &gcc_pcie_6a_pipediv2_clk.clkr, 6999 [GCC_PCIE_6A_SLV_AXI_CLK] = &gcc_pcie_6a_slv_axi_clk.clkr, 7000 [GCC_PCIE_6A_SLV_Q2A_AXI_CLK] = &gcc_pcie_6a_slv_q2a_axi_clk.clkr, 7001 [GCC_PCIE_6B_AUX_CLK] = &gcc_pcie_6b_aux_clk.clkr, 7002 [GCC_PCIE_6B_AUX_CLK_SRC] = &gcc_pcie_6b_aux_clk_src.clkr, 7003 [GCC_PCIE_6B_CFG_AHB_CLK] = &gcc_pcie_6b_cfg_ahb_clk.clkr, 7004 [GCC_PCIE_6B_MSTR_AXI_CLK] = &gcc_pcie_6b_mstr_axi_clk.clkr, 7005 [GCC_PCIE_6B_PHY_AUX_CLK] = &gcc_pcie_6b_phy_aux_clk.clkr, 7006 [GCC_PCIE_6B_PHY_RCHNG_CLK] = &gcc_pcie_6b_phy_rchng_clk.clkr, 7007 [GCC_PCIE_6B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_6b_phy_rchng_clk_src.clkr, 7008 [GCC_PCIE_6B_PIPE_CLK] = &gcc_pcie_6b_pipe_clk.clkr, 7009 [GCC_PCIE_6B_PIPE_CLK_SRC] = &gcc_pcie_6b_pipe_clk_src.clkr, 7010 [GCC_PCIE_6B_PIPE_DIV_CLK_SRC] = &gcc_pcie_6b_pipe_div_clk_src.clkr, 7011 [GCC_PCIE_6B_PIPEDIV2_CLK] = &gcc_pcie_6b_pipediv2_clk.clkr, 7012 [GCC_PCIE_6B_SLV_AXI_CLK] = &gcc_pcie_6b_slv_axi_clk.clkr, 7013 [GCC_PCIE_6B_SLV_Q2A_AXI_CLK] = &gcc_pcie_6b_slv_q2a_axi_clk.clkr, 7014 [GCC_PCIE_RSCC_AHB_CLK] = &gcc_pcie_rscc_ahb_clk.clkr, 7015 [GCC_PCIE_RSCC_XO_CLK] = &gcc_pcie_rscc_xo_clk.clkr, 7016 [GCC_PCIE_RSCC_XO_CLK_SRC] = &gcc_pcie_rscc_xo_clk_src.clkr, 7017 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 7018 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 7019 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 7020 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 7021 [GCC_QMIP_AV1E_AHB_CLK] = &gcc_qmip_av1e_ahb_clk.clkr, 7022 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 7023 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 7024 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 7025 [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr, 7026 [GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr, 7027 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 7028 [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr, 7029 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 7030 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 7031 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 7032 [GCC_QUPV3_WRAP0_QSPI_S2_CLK] = &gcc_qupv3_wrap0_qspi_s2_clk.clkr, 7033 [GCC_QUPV3_WRAP0_QSPI_S3_CLK] = &gcc_qupv3_wrap0_qspi_s3_clk.clkr, 7034 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 7035 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 7036 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 7037 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 7038 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 7039 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 7040 [GCC_QUPV3_WRAP0_S2_DIV_CLK_SRC] = &gcc_qupv3_wrap0_s2_div_clk_src.clkr, 7041 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 7042 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 7043 [GCC_QUPV3_WRAP0_S3_DIV_CLK_SRC] = &gcc_qupv3_wrap0_s3_div_clk_src.clkr, 7044 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 7045 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 7046 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 7047 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 7048 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 7049 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 7050 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 7051 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 7052 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 7053 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 7054 [GCC_QUPV3_WRAP1_QSPI_S2_CLK] = &gcc_qupv3_wrap1_qspi_s2_clk.clkr, 7055 [GCC_QUPV3_WRAP1_QSPI_S3_CLK] = &gcc_qupv3_wrap1_qspi_s3_clk.clkr, 7056 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 7057 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 7058 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 7059 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 7060 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 7061 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 7062 [GCC_QUPV3_WRAP1_S2_DIV_CLK_SRC] = &gcc_qupv3_wrap1_s2_div_clk_src.clkr, 7063 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 7064 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 7065 [GCC_QUPV3_WRAP1_S3_DIV_CLK_SRC] = &gcc_qupv3_wrap1_s3_div_clk_src.clkr, 7066 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 7067 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 7068 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 7069 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 7070 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 7071 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 7072 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 7073 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 7074 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, 7075 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, 7076 [GCC_QUPV3_WRAP2_QSPI_S2_CLK] = &gcc_qupv3_wrap2_qspi_s2_clk.clkr, 7077 [GCC_QUPV3_WRAP2_QSPI_S3_CLK] = &gcc_qupv3_wrap2_qspi_s3_clk.clkr, 7078 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 7079 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 7080 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 7081 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 7082 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 7083 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 7084 [GCC_QUPV3_WRAP2_S2_DIV_CLK_SRC] = &gcc_qupv3_wrap2_s2_div_clk_src.clkr, 7085 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 7086 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 7087 [GCC_QUPV3_WRAP2_S3_DIV_CLK_SRC] = &gcc_qupv3_wrap2_s3_div_clk_src.clkr, 7088 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 7089 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 7090 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, 7091 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, 7092 [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr, 7093 [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr, 7094 [GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr, 7095 [GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr, 7096 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 7097 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 7098 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 7099 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 7100 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 7101 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 7102 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 7103 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 7104 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 7105 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 7106 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 7107 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 7108 [GCC_SYS_NOC_USB_AXI_CLK] = &gcc_sys_noc_usb_axi_clk.clkr, 7109 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 7110 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 7111 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 7112 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 7113 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 7114 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 7115 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 7116 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 7117 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 7118 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 7119 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 7120 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 7121 [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr, 7122 [GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr, 7123 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr, 7124 [GCC_USB20_MOCK_UTMI_CLK_SRC] = &gcc_usb20_mock_utmi_clk_src.clkr, 7125 [GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb20_mock_utmi_postdiv_clk_src.clkr, 7126 [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr, 7127 [GCC_USB30_MP_MASTER_CLK] = &gcc_usb30_mp_master_clk.clkr, 7128 [GCC_USB30_MP_MASTER_CLK_SRC] = &gcc_usb30_mp_master_clk_src.clkr, 7129 [GCC_USB30_MP_MOCK_UTMI_CLK] = &gcc_usb30_mp_mock_utmi_clk.clkr, 7130 [GCC_USB30_MP_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mp_mock_utmi_clk_src.clkr, 7131 [GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr, 7132 [GCC_USB30_MP_SLEEP_CLK] = &gcc_usb30_mp_sleep_clk.clkr, 7133 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 7134 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 7135 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 7136 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 7137 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 7138 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 7139 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, 7140 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, 7141 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, 7142 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr, 7143 [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr, 7144 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, 7145 [GCC_USB30_TERT_MASTER_CLK] = &gcc_usb30_tert_master_clk.clkr, 7146 [GCC_USB30_TERT_MASTER_CLK_SRC] = &gcc_usb30_tert_master_clk_src.clkr, 7147 [GCC_USB30_TERT_MOCK_UTMI_CLK] = &gcc_usb30_tert_mock_utmi_clk.clkr, 7148 [GCC_USB30_TERT_MOCK_UTMI_CLK_SRC] = &gcc_usb30_tert_mock_utmi_clk_src.clkr, 7149 [GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr, 7150 [GCC_USB30_TERT_SLEEP_CLK] = &gcc_usb30_tert_sleep_clk.clkr, 7151 [GCC_USB34_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb34_prim_phy_pipe_clk_src.clkr, 7152 [GCC_USB34_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb34_sec_phy_pipe_clk_src.clkr, 7153 [GCC_USB34_TERT_PHY_PIPE_CLK_SRC] = &gcc_usb34_tert_phy_pipe_clk_src.clkr, 7154 [GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr, 7155 [GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr, 7156 [GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr, 7157 [GCC_USB3_MP_PHY_PIPE_0_CLK] = &gcc_usb3_mp_phy_pipe_0_clk.clkr, 7158 [GCC_USB3_MP_PHY_PIPE_1_CLK] = &gcc_usb3_mp_phy_pipe_1_clk.clkr, 7159 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 7160 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 7161 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 7162 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 7163 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 7164 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, 7165 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, 7166 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, 7167 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, 7168 [GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr, 7169 [GCC_USB3_TERT_PHY_AUX_CLK] = &gcc_usb3_tert_phy_aux_clk.clkr, 7170 [GCC_USB3_TERT_PHY_AUX_CLK_SRC] = &gcc_usb3_tert_phy_aux_clk_src.clkr, 7171 [GCC_USB3_TERT_PHY_COM_AUX_CLK] = &gcc_usb3_tert_phy_com_aux_clk.clkr, 7172 [GCC_USB3_TERT_PHY_PIPE_CLK] = &gcc_usb3_tert_phy_pipe_clk.clkr, 7173 [GCC_USB3_TERT_PHY_PIPE_CLK_SRC] = &gcc_usb3_tert_phy_pipe_clk_src.clkr, 7174 [GCC_USB4_0_CFG_AHB_CLK] = &gcc_usb4_0_cfg_ahb_clk.clkr, 7175 [GCC_USB4_0_DP0_CLK] = &gcc_usb4_0_dp0_clk.clkr, 7176 [GCC_USB4_0_DP1_CLK] = &gcc_usb4_0_dp1_clk.clkr, 7177 [GCC_USB4_0_MASTER_CLK] = &gcc_usb4_0_master_clk.clkr, 7178 [GCC_USB4_0_MASTER_CLK_SRC] = &gcc_usb4_0_master_clk_src.clkr, 7179 [GCC_USB4_0_PHY_DP0_CLK_SRC] = &gcc_usb4_0_phy_dp0_clk_src.clkr, 7180 [GCC_USB4_0_PHY_DP1_CLK_SRC] = &gcc_usb4_0_phy_dp1_clk_src.clkr, 7181 [GCC_USB4_0_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_0_phy_p2rr2p_pipe_clk.clkr, 7182 [GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_0_phy_p2rr2p_pipe_clk_src.clkr, 7183 [GCC_USB4_0_PHY_PCIE_PIPE_CLK] = &gcc_usb4_0_phy_pcie_pipe_clk.clkr, 7184 [GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_clk_src.clkr, 7185 [GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr, 7186 [GCC_USB4_0_PHY_RX0_CLK] = &gcc_usb4_0_phy_rx0_clk.clkr, 7187 [GCC_USB4_0_PHY_RX0_CLK_SRC] = &gcc_usb4_0_phy_rx0_clk_src.clkr, 7188 [GCC_USB4_0_PHY_RX1_CLK] = &gcc_usb4_0_phy_rx1_clk.clkr, 7189 [GCC_USB4_0_PHY_RX1_CLK_SRC] = &gcc_usb4_0_phy_rx1_clk_src.clkr, 7190 [GCC_USB4_0_PHY_SYS_CLK_SRC] = &gcc_usb4_0_phy_sys_clk_src.clkr, 7191 [GCC_USB4_0_PHY_USB_PIPE_CLK] = &gcc_usb4_0_phy_usb_pipe_clk.clkr, 7192 [GCC_USB4_0_SB_IF_CLK] = &gcc_usb4_0_sb_if_clk.clkr, 7193 [GCC_USB4_0_SB_IF_CLK_SRC] = &gcc_usb4_0_sb_if_clk_src.clkr, 7194 [GCC_USB4_0_SYS_CLK] = &gcc_usb4_0_sys_clk.clkr, 7195 [GCC_USB4_0_TMU_CLK] = &gcc_usb4_0_tmu_clk.clkr, 7196 [GCC_USB4_0_TMU_CLK_SRC] = &gcc_usb4_0_tmu_clk_src.clkr, 7197 [GCC_USB4_1_CFG_AHB_CLK] = &gcc_usb4_1_cfg_ahb_clk.clkr, 7198 [GCC_USB4_1_DP0_CLK] = &gcc_usb4_1_dp0_clk.clkr, 7199 [GCC_USB4_1_DP1_CLK] = &gcc_usb4_1_dp1_clk.clkr, 7200 [GCC_USB4_1_MASTER_CLK] = &gcc_usb4_1_master_clk.clkr, 7201 [GCC_USB4_1_MASTER_CLK_SRC] = &gcc_usb4_1_master_clk_src.clkr, 7202 [GCC_USB4_1_PHY_DP0_CLK_SRC] = &gcc_usb4_1_phy_dp0_clk_src.clkr, 7203 [GCC_USB4_1_PHY_DP1_CLK_SRC] = &gcc_usb4_1_phy_dp1_clk_src.clkr, 7204 [GCC_USB4_1_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_1_phy_p2rr2p_pipe_clk.clkr, 7205 [GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr, 7206 [GCC_USB4_1_PHY_PCIE_PIPE_CLK] = &gcc_usb4_1_phy_pcie_pipe_clk.clkr, 7207 [GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_clk_src.clkr, 7208 [GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr, 7209 [GCC_USB4_1_PHY_RX0_CLK] = &gcc_usb4_1_phy_rx0_clk.clkr, 7210 [GCC_USB4_1_PHY_RX0_CLK_SRC] = &gcc_usb4_1_phy_rx0_clk_src.clkr, 7211 [GCC_USB4_1_PHY_RX1_CLK] = &gcc_usb4_1_phy_rx1_clk.clkr, 7212 [GCC_USB4_1_PHY_RX1_CLK_SRC] = &gcc_usb4_1_phy_rx1_clk_src.clkr, 7213 [GCC_USB4_1_PHY_SYS_CLK_SRC] = &gcc_usb4_1_phy_sys_clk_src.clkr, 7214 [GCC_USB4_1_PHY_USB_PIPE_CLK] = &gcc_usb4_1_phy_usb_pipe_clk.clkr, 7215 [GCC_USB4_1_SB_IF_CLK] = &gcc_usb4_1_sb_if_clk.clkr, 7216 [GCC_USB4_1_SB_IF_CLK_SRC] = &gcc_usb4_1_sb_if_clk_src.clkr, 7217 [GCC_USB4_1_SYS_CLK] = &gcc_usb4_1_sys_clk.clkr, 7218 [GCC_USB4_1_TMU_CLK] = &gcc_usb4_1_tmu_clk.clkr, 7219 [GCC_USB4_1_TMU_CLK_SRC] = &gcc_usb4_1_tmu_clk_src.clkr, 7220 [GCC_USB4_2_CFG_AHB_CLK] = &gcc_usb4_2_cfg_ahb_clk.clkr, 7221 [GCC_USB4_2_DP0_CLK] = &gcc_usb4_2_dp0_clk.clkr, 7222 [GCC_USB4_2_DP1_CLK] = &gcc_usb4_2_dp1_clk.clkr, 7223 [GCC_USB4_2_MASTER_CLK] = &gcc_usb4_2_master_clk.clkr, 7224 [GCC_USB4_2_MASTER_CLK_SRC] = &gcc_usb4_2_master_clk_src.clkr, 7225 [GCC_USB4_2_PHY_DP0_CLK_SRC] = &gcc_usb4_2_phy_dp0_clk_src.clkr, 7226 [GCC_USB4_2_PHY_DP1_CLK_SRC] = &gcc_usb4_2_phy_dp1_clk_src.clkr, 7227 [GCC_USB4_2_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_2_phy_p2rr2p_pipe_clk.clkr, 7228 [GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_2_phy_p2rr2p_pipe_clk_src.clkr, 7229 [GCC_USB4_2_PHY_PCIE_PIPE_CLK] = &gcc_usb4_2_phy_pcie_pipe_clk.clkr, 7230 [GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_clk_src.clkr, 7231 [GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr, 7232 [GCC_USB4_2_PHY_RX0_CLK] = &gcc_usb4_2_phy_rx0_clk.clkr, 7233 [GCC_USB4_2_PHY_RX0_CLK_SRC] = &gcc_usb4_2_phy_rx0_clk_src.clkr, 7234 [GCC_USB4_2_PHY_RX1_CLK] = &gcc_usb4_2_phy_rx1_clk.clkr, 7235 [GCC_USB4_2_PHY_RX1_CLK_SRC] = &gcc_usb4_2_phy_rx1_clk_src.clkr, 7236 [GCC_USB4_2_PHY_SYS_CLK_SRC] = &gcc_usb4_2_phy_sys_clk_src.clkr, 7237 [GCC_USB4_2_PHY_USB_PIPE_CLK] = &gcc_usb4_2_phy_usb_pipe_clk.clkr, 7238 [GCC_USB4_2_SB_IF_CLK] = &gcc_usb4_2_sb_if_clk.clkr, 7239 [GCC_USB4_2_SB_IF_CLK_SRC] = &gcc_usb4_2_sb_if_clk_src.clkr, 7240 [GCC_USB4_2_SYS_CLK] = &gcc_usb4_2_sys_clk.clkr, 7241 [GCC_USB4_2_TMU_CLK] = &gcc_usb4_2_tmu_clk.clkr, 7242 [GCC_USB4_2_TMU_CLK_SRC] = &gcc_usb4_2_tmu_clk_src.clkr, 7243 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 7244 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 7245 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr, 7246 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr, 7247 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr, 7248 }; 7249 7250 static struct gdsc *gcc_x1e80100_gdscs[] = { 7251 [GCC_PCIE_0_TUNNEL_GDSC] = &gcc_pcie_0_tunnel_gdsc, 7252 [GCC_PCIE_1_TUNNEL_GDSC] = &gcc_pcie_1_tunnel_gdsc, 7253 [GCC_PCIE_2_TUNNEL_GDSC] = &gcc_pcie_2_tunnel_gdsc, 7254 [GCC_PCIE_3_GDSC] = &gcc_pcie_3_gdsc, 7255 [GCC_PCIE_3_PHY_GDSC] = &gcc_pcie_3_phy_gdsc, 7256 [GCC_PCIE_4_GDSC] = &gcc_pcie_4_gdsc, 7257 [GCC_PCIE_4_PHY_GDSC] = &gcc_pcie_4_phy_gdsc, 7258 [GCC_PCIE_5_GDSC] = &gcc_pcie_5_gdsc, 7259 [GCC_PCIE_5_PHY_GDSC] = &gcc_pcie_5_phy_gdsc, 7260 [GCC_PCIE_6_PHY_GDSC] = &gcc_pcie_6_phy_gdsc, 7261 [GCC_PCIE_6A_GDSC] = &gcc_pcie_6a_gdsc, 7262 [GCC_PCIE_6B_GDSC] = &gcc_pcie_6b_gdsc, 7263 [GCC_UFS_MEM_PHY_GDSC] = &gcc_ufs_mem_phy_gdsc, 7264 [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc, 7265 [GCC_USB20_PRIM_GDSC] = &gcc_usb20_prim_gdsc, 7266 [GCC_USB30_MP_GDSC] = &gcc_usb30_mp_gdsc, 7267 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, 7268 [GCC_USB30_SEC_GDSC] = &gcc_usb30_sec_gdsc, 7269 [GCC_USB30_TERT_GDSC] = &gcc_usb30_tert_gdsc, 7270 [GCC_USB3_MP_SS0_PHY_GDSC] = &gcc_usb3_mp_ss0_phy_gdsc, 7271 [GCC_USB3_MP_SS1_PHY_GDSC] = &gcc_usb3_mp_ss1_phy_gdsc, 7272 [GCC_USB4_0_GDSC] = &gcc_usb4_0_gdsc, 7273 [GCC_USB4_1_GDSC] = &gcc_usb4_1_gdsc, 7274 [GCC_USB4_2_GDSC] = &gcc_usb4_2_gdsc, 7275 [GCC_USB_0_PHY_GDSC] = &gcc_usb_0_phy_gdsc, 7276 [GCC_USB_1_PHY_GDSC] = &gcc_usb_1_phy_gdsc, 7277 [GCC_USB_2_PHY_GDSC] = &gcc_usb_2_phy_gdsc, 7278 }; 7279 7280 static const struct qcom_reset_map gcc_x1e80100_resets[] = { 7281 [GCC_AV1E_BCR] = { 0x4a000 }, 7282 [GCC_CAMERA_BCR] = { 0x26000 }, 7283 [GCC_DISPLAY_BCR] = { 0x27000 }, 7284 [GCC_GPU_BCR] = { 0x71000 }, 7285 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, 7286 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, 7287 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 7288 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 }, 7289 [GCC_PCIE_0_TUNNEL_BCR] = { 0xa0000 }, 7290 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 }, 7291 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 }, 7292 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, 7293 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 }, 7294 [GCC_PCIE_1_TUNNEL_BCR] = { 0x2c000 }, 7295 [GCC_PCIE_2_LINK_DOWN_BCR] = { 0xa5014 }, 7296 [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0xa5020 }, 7297 [GCC_PCIE_2_PHY_BCR] = { 0xa501c }, 7298 [GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0xa5028 }, 7299 [GCC_PCIE_2_TUNNEL_BCR] = { 0x13000 }, 7300 [GCC_PCIE_3_BCR] = { 0x58000 }, 7301 [GCC_PCIE_3_LINK_DOWN_BCR] = { 0xab014 }, 7302 [GCC_PCIE_3_NOCSR_COM_PHY_BCR] = { 0xab020 }, 7303 [GCC_PCIE_3_PHY_BCR] = { 0xab01c }, 7304 [GCC_PCIE_3_PHY_NOCSR_COM_PHY_BCR] = { 0xab024 }, 7305 [GCC_PCIE_4_BCR] = { 0x6b000 }, 7306 [GCC_PCIE_4_LINK_DOWN_BCR] = { 0xb3014 }, 7307 [GCC_PCIE_4_NOCSR_COM_PHY_BCR] = { 0xb3020 }, 7308 [GCC_PCIE_4_PHY_BCR] = { 0xb301c }, 7309 [GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] = { 0xb3028 }, 7310 [GCC_PCIE_5_BCR] = { 0x2f000 }, 7311 [GCC_PCIE_5_LINK_DOWN_BCR] = { 0xaa014 }, 7312 [GCC_PCIE_5_NOCSR_COM_PHY_BCR] = { 0xaa020 }, 7313 [GCC_PCIE_5_PHY_BCR] = { 0xaa01c }, 7314 [GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR] = { 0xaa028 }, 7315 [GCC_PCIE_6A_BCR] = { 0x31000 }, 7316 [GCC_PCIE_6A_LINK_DOWN_BCR] = { 0xac014 }, 7317 [GCC_PCIE_6A_NOCSR_COM_PHY_BCR] = { 0xac020 }, 7318 [GCC_PCIE_6A_PHY_BCR] = { 0xac01c }, 7319 [GCC_PCIE_6A_PHY_NOCSR_COM_PHY_BCR] = { 0xac024 }, 7320 [GCC_PCIE_6B_BCR] = { 0x8d000 }, 7321 [GCC_PCIE_6B_LINK_DOWN_BCR] = { 0xb5014 }, 7322 [GCC_PCIE_6B_NOCSR_COM_PHY_BCR] = { 0xb5020 }, 7323 [GCC_PCIE_6B_PHY_BCR] = { 0xb501c }, 7324 [GCC_PCIE_6B_PHY_NOCSR_COM_PHY_BCR] = { 0xb5024 }, 7325 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 7326 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c }, 7327 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, 7328 [GCC_PCIE_RSCC_BCR] = { 0xa4000 }, 7329 [GCC_PDM_BCR] = { 0x33000 }, 7330 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x42000 }, 7331 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, 7332 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, 7333 [GCC_QUSB2PHY_HS0_MP_BCR] = { 0x1200c }, 7334 [GCC_QUSB2PHY_HS1_MP_BCR] = { 0x12010 }, 7335 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 7336 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 7337 [GCC_QUSB2PHY_TERT_BCR] = { 0x12008 }, 7338 [GCC_QUSB2PHY_USB20_HS_BCR] = { 0x12014 }, 7339 [GCC_SDCC2_BCR] = { 0x14000 }, 7340 [GCC_SDCC4_BCR] = { 0x16000 }, 7341 [GCC_UFS_PHY_BCR] = { 0x77000 }, 7342 [GCC_USB20_PRIM_BCR] = { 0x29000 }, 7343 [GCC_USB30_MP_BCR] = { 0x17000 }, 7344 [GCC_USB30_PRIM_BCR] = { 0x39000 }, 7345 [GCC_USB30_SEC_BCR] = { 0xa1000 }, 7346 [GCC_USB30_TERT_BCR] = { 0xa2000 }, 7347 [GCC_USB3_MP_SS0_PHY_BCR] = { 0x19008 }, 7348 [GCC_USB3_MP_SS1_PHY_BCR] = { 0x54008 }, 7349 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 7350 [GCC_USB3_PHY_SEC_BCR] = { 0x2a000 }, 7351 [GCC_USB3_PHY_TERT_BCR] = { 0xa3000 }, 7352 [GCC_USB3_UNIPHY_MP0_BCR] = { 0x19000 }, 7353 [GCC_USB3_UNIPHY_MP1_BCR] = { 0x54000 }, 7354 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 7355 [GCC_USB4PHY_PHY_PRIM_BCR] = { 0x5000c }, 7356 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x2a004 }, 7357 [GCC_USB4PHY_PHY_SEC_BCR] = { 0x2a00c }, 7358 [GCC_USB3PHY_PHY_TERT_BCR] = { 0xa3004 }, 7359 [GCC_USB4PHY_PHY_TERT_BCR] = { 0xa300c }, 7360 [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x19004 }, 7361 [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x54004 }, 7362 [GCC_USB4_0_BCR] = { 0x9f000 }, 7363 [GCC_USB4_0_DP0_PHY_PRIM_BCR] = { 0x50010 }, 7364 [GCC_USB4_0_MISC_USB4_SYS_BCR] = { .reg = 0xad0f8, .bit = 0 }, 7365 [GCC_USB4_0_MISC_RX_CLK_0_BCR] = { .reg = 0xad0f8, .bit = 1 }, 7366 [GCC_USB4_0_MISC_RX_CLK_1_BCR] = { .reg = 0xad0f8, .bit = 2 }, 7367 [GCC_USB4_0_MISC_USB_PIPE_BCR] = { .reg = 0xad0f8, .bit = 3 }, 7368 [GCC_USB4_0_MISC_PCIE_PIPE_BCR] = { .reg = 0xad0f8, .bit = 4 }, 7369 [GCC_USB4_0_MISC_TMU_BCR] = { .reg = 0xad0f8, .bit = 5 }, 7370 [GCC_USB4_0_MISC_SB_IF_BCR] = { .reg = 0xad0f8, .bit = 6 }, 7371 [GCC_USB4_0_MISC_HIA_MSTR_BCR] = { .reg = 0xad0f8, .bit = 7 }, 7372 [GCC_USB4_0_MISC_AHB_BCR] = { .reg = 0xad0f8, .bit = 8 }, 7373 [GCC_USB4_0_MISC_DP0_MAX_PCLK_BCR] = { .reg = 0xad0f8, .bit = 9 }, 7374 [GCC_USB4_0_MISC_DP1_MAX_PCLK_BCR] = { .reg = 0xad0f8, .bit = 10 }, 7375 [GCC_USB4_1_BCR] = { 0x2b000 }, 7376 [GCC_USB4_1_DP0_PHY_SEC_BCR] = { 0x2a010 }, 7377 [GCC_USB4_1_MISC_USB4_SYS_BCR] = { .reg = 0xae0f8, .bit = 0 }, 7378 [GCC_USB4_1_MISC_RX_CLK_0_BCR] = { .reg = 0xae0f8, .bit = 1 }, 7379 [GCC_USB4_1_MISC_RX_CLK_1_BCR] = { .reg = 0xae0f8, .bit = 2 }, 7380 [GCC_USB4_1_MISC_USB_PIPE_BCR] = { .reg = 0xae0f8, .bit = 3 }, 7381 [GCC_USB4_1_MISC_PCIE_PIPE_BCR] = { .reg = 0xae0f8, .bit = 4 }, 7382 [GCC_USB4_1_MISC_TMU_BCR] = { .reg = 0xae0f8, .bit = 5 }, 7383 [GCC_USB4_1_MISC_SB_IF_BCR] = { .reg = 0xae0f8, .bit = 6 }, 7384 [GCC_USB4_1_MISC_HIA_MSTR_BCR] = { .reg = 0xae0f8, .bit = 7 }, 7385 [GCC_USB4_1_MISC_AHB_BCR] = { .reg = 0xae0f8, .bit = 8 }, 7386 [GCC_USB4_1_MISC_DP0_MAX_PCLK_BCR] = { .reg = 0xae0f8, .bit = 9 }, 7387 [GCC_USB4_1_MISC_DP1_MAX_PCLK_BCR] = { .reg = 0xae0f8, .bit = 10 }, 7388 [GCC_USB4_2_BCR] = { 0x11000 }, 7389 [GCC_USB4_2_DP0_PHY_TERT_BCR] = { 0xa3010 }, 7390 [GCC_USB4_2_MISC_USB4_SYS_BCR] = { .reg = 0xaf0f8, .bit = 0 }, 7391 [GCC_USB4_2_MISC_RX_CLK_0_BCR] = { .reg = 0xaf0f8, .bit = 1 }, 7392 [GCC_USB4_2_MISC_RX_CLK_1_BCR] = { .reg = 0xaf0f8, .bit = 2 }, 7393 [GCC_USB4_2_MISC_USB_PIPE_BCR] = { .reg = 0xaf0f8, .bit = 3 }, 7394 [GCC_USB4_2_MISC_PCIE_PIPE_BCR] = { .reg = 0xaf0f8, .bit = 4 }, 7395 [GCC_USB4_2_MISC_TMU_BCR] = { .reg = 0xaf0f8, .bit = 5 }, 7396 [GCC_USB4_2_MISC_SB_IF_BCR] = { .reg = 0xaf0f8, .bit = 6 }, 7397 [GCC_USB4_2_MISC_HIA_MSTR_BCR] = { .reg = 0xaf0f8, .bit = 7 }, 7398 [GCC_USB4_2_MISC_AHB_BCR] = { .reg = 0xaf0f8, .bit = 8 }, 7399 [GCC_USB4_2_MISC_DP0_MAX_PCLK_BCR] = { .reg = 0xaf0f8, .bit = 9 }, 7400 [GCC_USB4_2_MISC_DP1_MAX_PCLK_BCR] = { .reg = 0xaf0f8, .bit = 10 }, 7401 [GCC_USB_0_PHY_BCR] = { 0x50020 }, 7402 [GCC_USB_1_PHY_BCR] = { 0x2a020 }, 7403 [GCC_USB_2_PHY_BCR] = { 0xa3020 }, 7404 [GCC_VIDEO_BCR] = { 0x32000 }, 7405 [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x32018, .bit = 2, .udelay = 1000 }, 7406 [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x32024, .bit = 2, .udelay = 1000 }, 7407 }; 7408 7409 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 7410 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 7411 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 7412 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 7413 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 7414 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 7415 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 7416 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 7417 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 7418 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 7419 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 7420 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 7421 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 7422 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 7423 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 7424 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 7425 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 7426 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 7427 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 7428 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), 7429 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), 7430 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 7431 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), 7432 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src), 7433 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src), 7434 }; 7435 7436 static const struct regmap_config gcc_x1e80100_regmap_config = { 7437 .reg_bits = 32, 7438 .reg_stride = 4, 7439 .val_bits = 32, 7440 .max_register = 0x1f41f0, 7441 .fast_io = true, 7442 }; 7443 7444 static const struct qcom_cc_desc gcc_x1e80100_desc = { 7445 .config = &gcc_x1e80100_regmap_config, 7446 .clks = gcc_x1e80100_clocks, 7447 .num_clks = ARRAY_SIZE(gcc_x1e80100_clocks), 7448 .resets = gcc_x1e80100_resets, 7449 .num_resets = ARRAY_SIZE(gcc_x1e80100_resets), 7450 .gdscs = gcc_x1e80100_gdscs, 7451 .num_gdscs = ARRAY_SIZE(gcc_x1e80100_gdscs), 7452 }; 7453 7454 static const struct of_device_id gcc_x1e80100_match_table[] = { 7455 { .compatible = "qcom,x1e80100-gcc" }, 7456 { } 7457 }; 7458 MODULE_DEVICE_TABLE(of, gcc_x1e80100_match_table); 7459 7460 static int gcc_x1e80100_probe(struct platform_device *pdev) 7461 { 7462 struct regmap *regmap; 7463 int ret; 7464 7465 regmap = qcom_cc_map(pdev, &gcc_x1e80100_desc); 7466 if (IS_ERR(regmap)) 7467 return PTR_ERR(regmap); 7468 7469 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 7470 ARRAY_SIZE(gcc_dfs_clocks)); 7471 if (ret) 7472 return ret; 7473 7474 /* Keep some clocks always-on */ 7475 qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ 7476 qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */ 7477 qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ 7478 qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */ 7479 qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */ 7480 qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */ 7481 qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ 7482 qcom_branch_set_clk_en(regmap, 0x7d01c); /* GCC_HLOS1_VOTE_AGGRE_NOC_MMU_USB_QTB_CLK */ 7483 7484 /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */ 7485 regmap_write(regmap, 0x52224, 0x0); 7486 7487 /* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks */ 7488 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); 7489 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true); 7490 7491 return qcom_cc_really_probe(&pdev->dev, &gcc_x1e80100_desc, regmap); 7492 } 7493 7494 static struct platform_driver gcc_x1e80100_driver = { 7495 .probe = gcc_x1e80100_probe, 7496 .driver = { 7497 .name = "gcc-x1e80100", 7498 .of_match_table = gcc_x1e80100_match_table, 7499 }, 7500 }; 7501 7502 static int __init gcc_x1e80100_init(void) 7503 { 7504 return platform_driver_register(&gcc_x1e80100_driver); 7505 } 7506 subsys_initcall(gcc_x1e80100_init); 7507 7508 static void __exit gcc_x1e80100_exit(void) 7509 { 7510 platform_driver_unregister(&gcc_x1e80100_driver); 7511 } 7512 module_exit(gcc_x1e80100_exit); 7513 7514 MODULE_DESCRIPTION("QTI GCC X1E80100 Driver"); 7515 MODULE_LICENSE("GPL"); 7516