1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,sm8750-gcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-pll.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "clk-regmap-divider.h" 20 #include "clk-regmap-mux.h" 21 #include "clk-regmap-phy-mux.h" 22 #include "common.h" 23 #include "gdsc.h" 24 #include "reset.h" 25 26 enum { 27 DT_BI_TCXO, 28 DT_BI_TCXO_AO, 29 DT_SLEEP_CLK, 30 DT_PCIE_0_PIPE_CLK, 31 DT_UFS_PHY_RX_SYMBOL_0_CLK, 32 DT_UFS_PHY_RX_SYMBOL_1_CLK, 33 DT_UFS_PHY_TX_SYMBOL_0_CLK, 34 DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 35 }; 36 37 enum { 38 P_BI_TCXO, 39 P_GCC_GPLL0_OUT_EVEN, 40 P_GCC_GPLL0_OUT_MAIN, 41 P_GCC_GPLL1_OUT_MAIN, 42 P_GCC_GPLL4_OUT_MAIN, 43 P_GCC_GPLL7_OUT_MAIN, 44 P_GCC_GPLL9_OUT_MAIN, 45 P_PCIE_0_PIPE_CLK, 46 P_SLEEP_CLK, 47 P_UFS_PHY_RX_SYMBOL_0_CLK, 48 P_UFS_PHY_RX_SYMBOL_1_CLK, 49 P_UFS_PHY_TX_SYMBOL_0_CLK, 50 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 51 }; 52 53 static struct clk_alpha_pll gcc_gpll0 = { 54 .offset = 0x0, 55 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 56 .clkr = { 57 .enable_reg = 0x52020, 58 .enable_mask = BIT(0), 59 .hw.init = &(const struct clk_init_data) { 60 .name = "gcc_gpll0", 61 .parent_data = &(const struct clk_parent_data) { 62 .index = DT_BI_TCXO, 63 }, 64 .num_parents = 1, 65 .ops = &clk_alpha_pll_fixed_taycan_elu_ops, 66 }, 67 }, 68 }; 69 70 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 71 { 0x1, 2 }, 72 { } 73 }; 74 75 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 76 .offset = 0x0, 77 .post_div_shift = 10, 78 .post_div_table = post_div_table_gcc_gpll0_out_even, 79 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 80 .width = 4, 81 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 82 .clkr.hw.init = &(const struct clk_init_data) { 83 .name = "gcc_gpll0_out_even", 84 .parent_hws = (const struct clk_hw*[]) { 85 &gcc_gpll0.clkr.hw, 86 }, 87 .num_parents = 1, 88 .ops = &clk_alpha_pll_postdiv_taycan_elu_ops, 89 }, 90 }; 91 92 static struct clk_alpha_pll gcc_gpll1 = { 93 .offset = 0x1000, 94 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 95 .clkr = { 96 .enable_reg = 0x52020, 97 .enable_mask = BIT(1), 98 .hw.init = &(const struct clk_init_data) { 99 .name = "gcc_gpll1", 100 .parent_data = &(const struct clk_parent_data) { 101 .index = DT_BI_TCXO, 102 }, 103 .num_parents = 1, 104 .ops = &clk_alpha_pll_fixed_taycan_elu_ops, 105 }, 106 }, 107 }; 108 109 static struct clk_alpha_pll gcc_gpll4 = { 110 .offset = 0x4000, 111 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 112 .clkr = { 113 .enable_reg = 0x52020, 114 .enable_mask = BIT(4), 115 .hw.init = &(const struct clk_init_data) { 116 .name = "gcc_gpll4", 117 .parent_data = &(const struct clk_parent_data) { 118 .index = DT_BI_TCXO, 119 }, 120 .num_parents = 1, 121 .ops = &clk_alpha_pll_fixed_taycan_elu_ops, 122 }, 123 }, 124 }; 125 126 static struct clk_alpha_pll gcc_gpll7 = { 127 .offset = 0x7000, 128 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 129 .clkr = { 130 .enable_reg = 0x52020, 131 .enable_mask = BIT(7), 132 .hw.init = &(const struct clk_init_data) { 133 .name = "gcc_gpll7", 134 .parent_data = &(const struct clk_parent_data) { 135 .index = DT_BI_TCXO, 136 }, 137 .num_parents = 1, 138 .ops = &clk_alpha_pll_fixed_taycan_elu_ops, 139 }, 140 }, 141 }; 142 143 static struct clk_alpha_pll gcc_gpll9 = { 144 .offset = 0x9000, 145 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], 146 .clkr = { 147 .enable_reg = 0x52020, 148 .enable_mask = BIT(9), 149 .hw.init = &(const struct clk_init_data) { 150 .name = "gcc_gpll9", 151 .parent_data = &(const struct clk_parent_data) { 152 .index = DT_BI_TCXO, 153 }, 154 .num_parents = 1, 155 .ops = &clk_alpha_pll_fixed_taycan_elu_ops, 156 }, 157 }, 158 }; 159 160 static const struct parent_map gcc_parent_map_0[] = { 161 { P_BI_TCXO, 0 }, 162 { P_GCC_GPLL0_OUT_MAIN, 1 }, 163 { P_GCC_GPLL0_OUT_EVEN, 6 }, 164 }; 165 166 static const struct clk_parent_data gcc_parent_data_0[] = { 167 { .index = DT_BI_TCXO }, 168 { .hw = &gcc_gpll0.clkr.hw }, 169 { .hw = &gcc_gpll0_out_even.clkr.hw }, 170 }; 171 172 static const struct parent_map gcc_parent_map_1[] = { 173 { P_BI_TCXO, 0 }, 174 { P_GCC_GPLL0_OUT_MAIN, 1 }, 175 { P_SLEEP_CLK, 5 }, 176 { P_GCC_GPLL0_OUT_EVEN, 6 }, 177 }; 178 179 static const struct clk_parent_data gcc_parent_data_1[] = { 180 { .index = DT_BI_TCXO }, 181 { .hw = &gcc_gpll0.clkr.hw }, 182 { .index = DT_SLEEP_CLK }, 183 { .hw = &gcc_gpll0_out_even.clkr.hw }, 184 }; 185 186 static const struct parent_map gcc_parent_map_2[] = { 187 { P_BI_TCXO, 0 }, 188 { P_GCC_GPLL0_OUT_MAIN, 1 }, 189 { P_GCC_GPLL1_OUT_MAIN, 4 }, 190 { P_GCC_GPLL4_OUT_MAIN, 5 }, 191 { P_GCC_GPLL0_OUT_EVEN, 6 }, 192 }; 193 194 static const struct clk_parent_data gcc_parent_data_2[] = { 195 { .index = DT_BI_TCXO }, 196 { .hw = &gcc_gpll0.clkr.hw }, 197 { .hw = &gcc_gpll1.clkr.hw }, 198 { .hw = &gcc_gpll4.clkr.hw }, 199 { .hw = &gcc_gpll0_out_even.clkr.hw }, 200 }; 201 202 static const struct parent_map gcc_parent_map_3[] = { 203 { P_BI_TCXO, 0 }, 204 { P_GCC_GPLL0_OUT_MAIN, 1 }, 205 { P_GCC_GPLL4_OUT_MAIN, 5 }, 206 { P_GCC_GPLL0_OUT_EVEN, 6 }, 207 }; 208 209 static const struct clk_parent_data gcc_parent_data_3[] = { 210 { .index = DT_BI_TCXO }, 211 { .hw = &gcc_gpll0.clkr.hw }, 212 { .hw = &gcc_gpll4.clkr.hw }, 213 { .hw = &gcc_gpll0_out_even.clkr.hw }, 214 }; 215 216 static const struct parent_map gcc_parent_map_4[] = { 217 { P_BI_TCXO, 0 }, 218 { P_SLEEP_CLK, 5 }, 219 }; 220 221 static const struct clk_parent_data gcc_parent_data_4[] = { 222 { .index = DT_BI_TCXO }, 223 { .index = DT_SLEEP_CLK }, 224 }; 225 226 static const struct parent_map gcc_parent_map_5[] = { 227 { P_BI_TCXO, 0 }, 228 { P_GCC_GPLL0_OUT_MAIN, 1 }, 229 { P_GCC_GPLL7_OUT_MAIN, 2 }, 230 { P_GCC_GPLL0_OUT_EVEN, 6 }, 231 }; 232 233 static const struct clk_parent_data gcc_parent_data_5[] = { 234 { .index = DT_BI_TCXO }, 235 { .hw = &gcc_gpll0.clkr.hw }, 236 { .hw = &gcc_gpll7.clkr.hw }, 237 { .hw = &gcc_gpll0_out_even.clkr.hw }, 238 }; 239 240 static const struct parent_map gcc_parent_map_6[] = { 241 { P_BI_TCXO, 0 }, 242 }; 243 244 static const struct clk_parent_data gcc_parent_data_6[] = { 245 { .index = DT_BI_TCXO }, 246 }; 247 248 static const struct parent_map gcc_parent_map_8[] = { 249 { P_BI_TCXO, 0 }, 250 { P_GCC_GPLL0_OUT_MAIN, 1 }, 251 { P_GCC_GPLL9_OUT_MAIN, 2 }, 252 { P_GCC_GPLL4_OUT_MAIN, 5 }, 253 { P_GCC_GPLL0_OUT_EVEN, 6 }, 254 }; 255 256 static const struct clk_parent_data gcc_parent_data_8[] = { 257 { .index = DT_BI_TCXO }, 258 { .hw = &gcc_gpll0.clkr.hw }, 259 { .hw = &gcc_gpll9.clkr.hw }, 260 { .hw = &gcc_gpll4.clkr.hw }, 261 { .hw = &gcc_gpll0_out_even.clkr.hw }, 262 }; 263 264 static const struct parent_map gcc_parent_map_9[] = { 265 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 }, 266 { P_BI_TCXO, 2 }, 267 }; 268 269 static const struct clk_parent_data gcc_parent_data_9[] = { 270 { .index = DT_UFS_PHY_RX_SYMBOL_0_CLK }, 271 { .index = DT_BI_TCXO }, 272 }; 273 274 static const struct parent_map gcc_parent_map_10[] = { 275 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 }, 276 { P_BI_TCXO, 2 }, 277 }; 278 279 static const struct clk_parent_data gcc_parent_data_10[] = { 280 { .index = DT_UFS_PHY_RX_SYMBOL_1_CLK }, 281 { .index = DT_BI_TCXO }, 282 }; 283 284 static const struct parent_map gcc_parent_map_11[] = { 285 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 }, 286 { P_BI_TCXO, 2 }, 287 }; 288 289 static const struct clk_parent_data gcc_parent_data_11[] = { 290 { .index = DT_UFS_PHY_TX_SYMBOL_0_CLK }, 291 { .index = DT_BI_TCXO }, 292 }; 293 294 static const struct parent_map gcc_parent_map_12[] = { 295 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 296 { P_BI_TCXO, 2 }, 297 }; 298 299 static const struct clk_parent_data gcc_parent_data_12[] = { 300 { .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK }, 301 { .index = DT_BI_TCXO }, 302 }; 303 304 static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { 305 .reg = 0x6b080, 306 .clkr = { 307 .hw.init = &(const struct clk_init_data) { 308 .name = "gcc_pcie_0_pipe_clk_src", 309 .parent_data = &(const struct clk_parent_data){ 310 .index = DT_PCIE_0_PIPE_CLK, 311 }, 312 .num_parents = 1, 313 .ops = &clk_regmap_phy_mux_ops, 314 }, 315 }, 316 }; 317 318 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = { 319 .reg = 0x77068, 320 .shift = 0, 321 .width = 2, 322 .parent_map = gcc_parent_map_9, 323 .clkr = { 324 .hw.init = &(const struct clk_init_data) { 325 .name = "gcc_ufs_phy_rx_symbol_0_clk_src", 326 .parent_data = gcc_parent_data_9, 327 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 328 .ops = &clk_regmap_mux_closest_ops, 329 }, 330 }, 331 }; 332 333 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = { 334 .reg = 0x770ec, 335 .shift = 0, 336 .width = 2, 337 .parent_map = gcc_parent_map_10, 338 .clkr = { 339 .hw.init = &(const struct clk_init_data) { 340 .name = "gcc_ufs_phy_rx_symbol_1_clk_src", 341 .parent_data = gcc_parent_data_10, 342 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 343 .ops = &clk_regmap_mux_closest_ops, 344 }, 345 }, 346 }; 347 348 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = { 349 .reg = 0x77058, 350 .shift = 0, 351 .width = 2, 352 .parent_map = gcc_parent_map_11, 353 .clkr = { 354 .hw.init = &(const struct clk_init_data) { 355 .name = "gcc_ufs_phy_tx_symbol_0_clk_src", 356 .parent_data = gcc_parent_data_11, 357 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 358 .ops = &clk_regmap_mux_closest_ops, 359 }, 360 }, 361 }; 362 363 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 364 .reg = 0x39070, 365 .shift = 0, 366 .width = 2, 367 .parent_map = gcc_parent_map_12, 368 .clkr = { 369 .hw.init = &(const struct clk_init_data) { 370 .name = "gcc_usb3_prim_phy_pipe_clk_src", 371 .parent_data = gcc_parent_data_12, 372 .num_parents = ARRAY_SIZE(gcc_parent_data_12), 373 .ops = &clk_regmap_mux_closest_ops, 374 }, 375 }, 376 }; 377 378 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 379 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 380 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 381 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 382 { } 383 }; 384 385 static struct clk_rcg2 gcc_gp1_clk_src = { 386 .cmd_rcgr = 0x64004, 387 .mnd_width = 16, 388 .hid_width = 5, 389 .parent_map = gcc_parent_map_1, 390 .freq_tbl = ftbl_gcc_gp1_clk_src, 391 .clkr.hw.init = &(const struct clk_init_data) { 392 .name = "gcc_gp1_clk_src", 393 .parent_data = gcc_parent_data_1, 394 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 395 .flags = CLK_SET_RATE_PARENT, 396 .ops = &clk_rcg2_shared_ops, 397 }, 398 }; 399 400 static struct clk_rcg2 gcc_gp2_clk_src = { 401 .cmd_rcgr = 0x65004, 402 .mnd_width = 16, 403 .hid_width = 5, 404 .parent_map = gcc_parent_map_1, 405 .freq_tbl = ftbl_gcc_gp1_clk_src, 406 .clkr.hw.init = &(const struct clk_init_data) { 407 .name = "gcc_gp2_clk_src", 408 .parent_data = gcc_parent_data_1, 409 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 410 .flags = CLK_SET_RATE_PARENT, 411 .ops = &clk_rcg2_shared_ops, 412 }, 413 }; 414 415 static struct clk_rcg2 gcc_gp3_clk_src = { 416 .cmd_rcgr = 0x66004, 417 .mnd_width = 16, 418 .hid_width = 5, 419 .parent_map = gcc_parent_map_1, 420 .freq_tbl = ftbl_gcc_gp1_clk_src, 421 .clkr.hw.init = &(const struct clk_init_data) { 422 .name = "gcc_gp3_clk_src", 423 .parent_data = gcc_parent_data_1, 424 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 425 .flags = CLK_SET_RATE_PARENT, 426 .ops = &clk_rcg2_shared_ops, 427 }, 428 }; 429 430 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 431 F(19200000, P_BI_TCXO, 1, 0, 0), 432 { } 433 }; 434 435 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 436 .cmd_rcgr = 0x6b084, 437 .mnd_width = 16, 438 .hid_width = 5, 439 .parent_map = gcc_parent_map_4, 440 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 441 .clkr.hw.init = &(const struct clk_init_data) { 442 .name = "gcc_pcie_0_aux_clk_src", 443 .parent_data = gcc_parent_data_4, 444 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 445 .flags = CLK_SET_RATE_PARENT, 446 .ops = &clk_rcg2_shared_ops, 447 }, 448 }; 449 450 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 451 F(19200000, P_BI_TCXO, 1, 0, 0), 452 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 453 { } 454 }; 455 456 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 457 .cmd_rcgr = 0x6b068, 458 .mnd_width = 0, 459 .hid_width = 5, 460 .parent_map = gcc_parent_map_0, 461 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 462 .clkr.hw.init = &(const struct clk_init_data) { 463 .name = "gcc_pcie_0_phy_rchng_clk_src", 464 .parent_data = gcc_parent_data_0, 465 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 466 .flags = CLK_SET_RATE_PARENT, 467 .ops = &clk_rcg2_shared_ops, 468 }, 469 }; 470 471 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 472 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 473 { } 474 }; 475 476 static struct clk_rcg2 gcc_pdm2_clk_src = { 477 .cmd_rcgr = 0x33010, 478 .mnd_width = 0, 479 .hid_width = 5, 480 .parent_map = gcc_parent_map_0, 481 .freq_tbl = ftbl_gcc_pdm2_clk_src, 482 .clkr.hw.init = &(const struct clk_init_data) { 483 .name = "gcc_pdm2_clk_src", 484 .parent_data = gcc_parent_data_0, 485 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 486 .flags = CLK_SET_RATE_PARENT, 487 .ops = &clk_rcg2_shared_ops, 488 }, 489 }; 490 491 static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = { 492 .cmd_rcgr = 0x17008, 493 .mnd_width = 0, 494 .hid_width = 5, 495 .parent_map = gcc_parent_map_0, 496 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 497 .clkr.hw.init = &(const struct clk_init_data) { 498 .name = "gcc_qupv3_i2c_s0_clk_src", 499 .parent_data = gcc_parent_data_0, 500 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 501 .flags = CLK_SET_RATE_PARENT, 502 .ops = &clk_rcg2_shared_ops, 503 }, 504 }; 505 506 static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = { 507 .cmd_rcgr = 0x17024, 508 .mnd_width = 0, 509 .hid_width = 5, 510 .parent_map = gcc_parent_map_0, 511 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 512 .clkr.hw.init = &(const struct clk_init_data) { 513 .name = "gcc_qupv3_i2c_s1_clk_src", 514 .parent_data = gcc_parent_data_0, 515 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 516 .flags = CLK_SET_RATE_PARENT, 517 .ops = &clk_rcg2_shared_ops, 518 }, 519 }; 520 521 static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = { 522 .cmd_rcgr = 0x17040, 523 .mnd_width = 0, 524 .hid_width = 5, 525 .parent_map = gcc_parent_map_0, 526 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 527 .clkr.hw.init = &(const struct clk_init_data) { 528 .name = "gcc_qupv3_i2c_s2_clk_src", 529 .parent_data = gcc_parent_data_0, 530 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 531 .flags = CLK_SET_RATE_PARENT, 532 .ops = &clk_rcg2_shared_ops, 533 }, 534 }; 535 536 static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = { 537 .cmd_rcgr = 0x1705c, 538 .mnd_width = 0, 539 .hid_width = 5, 540 .parent_map = gcc_parent_map_0, 541 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 542 .clkr.hw.init = &(const struct clk_init_data) { 543 .name = "gcc_qupv3_i2c_s3_clk_src", 544 .parent_data = gcc_parent_data_0, 545 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 546 .flags = CLK_SET_RATE_PARENT, 547 .ops = &clk_rcg2_shared_ops, 548 }, 549 }; 550 551 static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = { 552 .cmd_rcgr = 0x17078, 553 .mnd_width = 0, 554 .hid_width = 5, 555 .parent_map = gcc_parent_map_0, 556 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 557 .clkr.hw.init = &(const struct clk_init_data) { 558 .name = "gcc_qupv3_i2c_s4_clk_src", 559 .parent_data = gcc_parent_data_0, 560 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 561 .flags = CLK_SET_RATE_PARENT, 562 .ops = &clk_rcg2_shared_ops, 563 }, 564 }; 565 566 static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src = { 567 .cmd_rcgr = 0x17094, 568 .mnd_width = 0, 569 .hid_width = 5, 570 .parent_map = gcc_parent_map_0, 571 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 572 .clkr.hw.init = &(const struct clk_init_data) { 573 .name = "gcc_qupv3_i2c_s5_clk_src", 574 .parent_data = gcc_parent_data_0, 575 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 576 .flags = CLK_SET_RATE_PARENT, 577 .ops = &clk_rcg2_shared_ops, 578 }, 579 }; 580 581 static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src = { 582 .cmd_rcgr = 0x170b0, 583 .mnd_width = 0, 584 .hid_width = 5, 585 .parent_map = gcc_parent_map_0, 586 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 587 .clkr.hw.init = &(const struct clk_init_data) { 588 .name = "gcc_qupv3_i2c_s6_clk_src", 589 .parent_data = gcc_parent_data_0, 590 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 591 .flags = CLK_SET_RATE_PARENT, 592 .ops = &clk_rcg2_shared_ops, 593 }, 594 }; 595 596 static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src = { 597 .cmd_rcgr = 0x170cc, 598 .mnd_width = 0, 599 .hid_width = 5, 600 .parent_map = gcc_parent_map_0, 601 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 602 .clkr.hw.init = &(const struct clk_init_data) { 603 .name = "gcc_qupv3_i2c_s7_clk_src", 604 .parent_data = gcc_parent_data_0, 605 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 606 .flags = CLK_SET_RATE_PARENT, 607 .ops = &clk_rcg2_shared_ops, 608 }, 609 }; 610 611 static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src = { 612 .cmd_rcgr = 0x170e8, 613 .mnd_width = 0, 614 .hid_width = 5, 615 .parent_map = gcc_parent_map_0, 616 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 617 .clkr.hw.init = &(const struct clk_init_data) { 618 .name = "gcc_qupv3_i2c_s8_clk_src", 619 .parent_data = gcc_parent_data_0, 620 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 621 .flags = CLK_SET_RATE_PARENT, 622 .ops = &clk_rcg2_shared_ops, 623 }, 624 }; 625 626 static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src = { 627 .cmd_rcgr = 0x17104, 628 .mnd_width = 0, 629 .hid_width = 5, 630 .parent_map = gcc_parent_map_0, 631 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 632 .clkr.hw.init = &(const struct clk_init_data) { 633 .name = "gcc_qupv3_i2c_s9_clk_src", 634 .parent_data = gcc_parent_data_0, 635 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 636 .flags = CLK_SET_RATE_PARENT, 637 .ops = &clk_rcg2_shared_ops, 638 }, 639 }; 640 641 /* Check this frequency table.*/ 642 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src[] = { 643 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 644 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 645 F(19200000, P_BI_TCXO, 1, 0, 0), 646 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 647 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 648 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 649 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 650 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 651 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 652 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 653 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 654 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 655 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 656 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 657 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 658 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 659 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 660 F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0), 661 { } 662 }; 663 664 static struct clk_init_data gcc_qupv3_wrap1_qspi_ref_clk_src_init = { 665 .name = "gcc_qupv3_wrap1_qspi_ref_clk_src", 666 .parent_data = gcc_parent_data_5, 667 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 668 .flags = CLK_SET_RATE_PARENT, 669 .ops = &clk_rcg2_shared_ops, 670 }; 671 672 static struct clk_rcg2 gcc_qupv3_wrap1_qspi_ref_clk_src = { 673 .cmd_rcgr = 0x188c0, 674 .mnd_width = 16, 675 .hid_width = 5, 676 .parent_map = gcc_parent_map_5, 677 .freq_tbl = ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src, 678 .clkr.hw.init = &gcc_qupv3_wrap1_qspi_ref_clk_src_init, 679 }; 680 681 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = { 682 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 683 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 684 F(19200000, P_BI_TCXO, 1, 0, 0), 685 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 686 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 687 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 688 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 689 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 690 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 691 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 692 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 693 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 694 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 695 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 696 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 697 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 698 { } 699 }; 700 701 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 702 .name = "gcc_qupv3_wrap1_s0_clk_src", 703 .parent_data = gcc_parent_data_0, 704 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 705 .flags = CLK_SET_RATE_PARENT, 706 .ops = &clk_rcg2_shared_ops, 707 }; 708 709 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 710 .cmd_rcgr = 0x18014, 711 .mnd_width = 16, 712 .hid_width = 5, 713 .parent_map = gcc_parent_map_0, 714 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 715 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 716 }; 717 718 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 719 .name = "gcc_qupv3_wrap1_s1_clk_src", 720 .parent_data = gcc_parent_data_0, 721 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 722 .flags = CLK_SET_RATE_PARENT, 723 .ops = &clk_rcg2_shared_ops, 724 }; 725 726 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 727 .cmd_rcgr = 0x18150, 728 .mnd_width = 16, 729 .hid_width = 5, 730 .parent_map = gcc_parent_map_0, 731 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 732 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 733 }; 734 735 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s3_clk_src[] = { 736 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 737 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 738 F(19200000, P_BI_TCXO, 1, 0, 0), 739 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 740 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 741 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 742 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 743 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 744 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 745 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 746 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 747 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 748 { } 749 }; 750 751 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 752 .name = "gcc_qupv3_wrap1_s3_clk_src", 753 .parent_data = gcc_parent_data_0, 754 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 755 .flags = CLK_SET_RATE_PARENT, 756 .ops = &clk_rcg2_shared_ops, 757 }; 758 759 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 760 .cmd_rcgr = 0x182a0, 761 .mnd_width = 16, 762 .hid_width = 5, 763 .parent_map = gcc_parent_map_0, 764 .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src, 765 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 766 }; 767 768 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 769 .name = "gcc_qupv3_wrap1_s4_clk_src", 770 .parent_data = gcc_parent_data_0, 771 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 772 .flags = CLK_SET_RATE_PARENT, 773 .ops = &clk_rcg2_shared_ops, 774 }; 775 776 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 777 .cmd_rcgr = 0x183dc, 778 .mnd_width = 16, 779 .hid_width = 5, 780 .parent_map = gcc_parent_map_0, 781 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 782 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 783 }; 784 785 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 786 .name = "gcc_qupv3_wrap1_s5_clk_src", 787 .parent_data = gcc_parent_data_0, 788 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 789 .flags = CLK_SET_RATE_PARENT, 790 .ops = &clk_rcg2_shared_ops, 791 }; 792 793 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 794 .cmd_rcgr = 0x18518, 795 .mnd_width = 16, 796 .hid_width = 5, 797 .parent_map = gcc_parent_map_0, 798 .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src, 799 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 800 }; 801 802 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 803 .name = "gcc_qupv3_wrap1_s6_clk_src", 804 .parent_data = gcc_parent_data_0, 805 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 806 .flags = CLK_SET_RATE_PARENT, 807 .ops = &clk_rcg2_shared_ops, 808 }; 809 810 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 811 .cmd_rcgr = 0x18654, 812 .mnd_width = 16, 813 .hid_width = 5, 814 .parent_map = gcc_parent_map_0, 815 .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src, 816 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 817 }; 818 819 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 820 .name = "gcc_qupv3_wrap1_s7_clk_src", 821 .parent_data = gcc_parent_data_0, 822 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 823 .flags = CLK_SET_RATE_PARENT, 824 .ops = &clk_rcg2_shared_ops, 825 }; 826 827 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 828 .cmd_rcgr = 0x18790, 829 .mnd_width = 16, 830 .hid_width = 5, 831 .parent_map = gcc_parent_map_0, 832 .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src, 833 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 834 }; 835 836 static const struct freq_tbl ftbl_gcc_qupv3_wrap2_ibi_ctrl_0_clk_src[] = { 837 F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0), 838 { } 839 }; 840 841 static struct clk_rcg2 gcc_qupv3_wrap2_ibi_ctrl_0_clk_src = { 842 .cmd_rcgr = 0x1e9f4, 843 .mnd_width = 0, 844 .hid_width = 5, 845 .parent_map = gcc_parent_map_2, 846 .freq_tbl = ftbl_gcc_qupv3_wrap2_ibi_ctrl_0_clk_src, 847 .clkr.hw.init = &(const struct clk_init_data) { 848 .name = "gcc_qupv3_wrap2_ibi_ctrl_0_clk_src", 849 .parent_data = gcc_parent_data_2, 850 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 851 .flags = CLK_SET_RATE_PARENT, 852 .ops = &clk_rcg2_shared_ops, 853 }, 854 }; 855 856 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 857 .name = "gcc_qupv3_wrap2_s0_clk_src", 858 .parent_data = gcc_parent_data_0, 859 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 860 .flags = CLK_SET_RATE_PARENT, 861 .ops = &clk_rcg2_shared_ops, 862 }; 863 864 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 865 .cmd_rcgr = 0x1e014, 866 .mnd_width = 16, 867 .hid_width = 5, 868 .parent_map = gcc_parent_map_0, 869 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 870 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 871 }; 872 873 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 874 .name = "gcc_qupv3_wrap2_s1_clk_src", 875 .parent_data = gcc_parent_data_0, 876 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 877 .flags = CLK_SET_RATE_PARENT, 878 .ops = &clk_rcg2_shared_ops, 879 }; 880 881 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 882 .cmd_rcgr = 0x1e150, 883 .mnd_width = 16, 884 .hid_width = 5, 885 .parent_map = gcc_parent_map_0, 886 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 887 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 888 }; 889 890 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 891 .name = "gcc_qupv3_wrap2_s2_clk_src", 892 .parent_data = gcc_parent_data_0, 893 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 894 .flags = CLK_SET_RATE_PARENT, 895 .ops = &clk_rcg2_shared_ops, 896 }; 897 898 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 899 .cmd_rcgr = 0x1e28c, 900 .mnd_width = 16, 901 .hid_width = 5, 902 .parent_map = gcc_parent_map_0, 903 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 904 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, 905 }; 906 907 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 908 .name = "gcc_qupv3_wrap2_s3_clk_src", 909 .parent_data = gcc_parent_data_0, 910 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 911 .flags = CLK_SET_RATE_PARENT, 912 .ops = &clk_rcg2_shared_ops, 913 }; 914 915 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 916 .cmd_rcgr = 0x1e3c8, 917 .mnd_width = 16, 918 .hid_width = 5, 919 .parent_map = gcc_parent_map_0, 920 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 921 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, 922 }; 923 924 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 925 .name = "gcc_qupv3_wrap2_s4_clk_src", 926 .parent_data = gcc_parent_data_0, 927 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 928 .flags = CLK_SET_RATE_PARENT, 929 .ops = &clk_rcg2_shared_ops, 930 }; 931 932 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 933 .cmd_rcgr = 0x1e504, 934 .mnd_width = 16, 935 .hid_width = 5, 936 .parent_map = gcc_parent_map_0, 937 .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src, 938 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 939 }; 940 941 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { 942 .name = "gcc_qupv3_wrap2_s5_clk_src", 943 .parent_data = gcc_parent_data_0, 944 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 945 .flags = CLK_SET_RATE_PARENT, 946 .ops = &clk_rcg2_shared_ops, 947 }; 948 949 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { 950 .cmd_rcgr = 0x1e640, 951 .mnd_width = 16, 952 .hid_width = 5, 953 .parent_map = gcc_parent_map_0, 954 .freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src, 955 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, 956 }; 957 958 static const struct freq_tbl ftbl_gcc_qupv3_wrap2_s6_clk_src[] = { 959 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 960 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 961 F(19200000, P_BI_TCXO, 1, 0, 0), 962 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 963 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 964 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 965 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 966 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 967 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 968 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 969 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 970 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 971 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 972 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 973 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 974 F(128000000, P_GCC_GPLL0_OUT_MAIN, 1, 16, 75), 975 { } 976 }; 977 978 static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = { 979 .name = "gcc_qupv3_wrap2_s6_clk_src", 980 .parent_data = gcc_parent_data_5, 981 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 982 .flags = CLK_SET_RATE_PARENT, 983 .ops = &clk_rcg2_shared_ops, 984 }; 985 986 static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { 987 .cmd_rcgr = 0x1e77c, 988 .mnd_width = 16, 989 .hid_width = 5, 990 .parent_map = gcc_parent_map_5, 991 .freq_tbl = ftbl_gcc_qupv3_wrap2_s6_clk_src, 992 .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init, 993 }; 994 995 static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = { 996 .name = "gcc_qupv3_wrap2_s7_clk_src", 997 .parent_data = gcc_parent_data_0, 998 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 999 .flags = CLK_SET_RATE_PARENT, 1000 .ops = &clk_rcg2_shared_ops, 1001 }; 1002 1003 static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = { 1004 .cmd_rcgr = 0x1e8b8, 1005 .mnd_width = 16, 1006 .hid_width = 5, 1007 .parent_map = gcc_parent_map_0, 1008 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 1009 .clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init, 1010 }; 1011 1012 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1013 F(400000, P_BI_TCXO, 12, 1, 4), 1014 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1015 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 1016 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1017 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), 1018 { } 1019 }; 1020 1021 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1022 .cmd_rcgr = 0x1401c, 1023 .mnd_width = 8, 1024 .hid_width = 5, 1025 .parent_map = gcc_parent_map_8, 1026 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1027 .clkr.hw.init = &(const struct clk_init_data) { 1028 .name = "gcc_sdcc2_apps_clk_src", 1029 .parent_data = gcc_parent_data_8, 1030 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 1031 .flags = CLK_SET_RATE_PARENT, 1032 .ops = &clk_rcg2_floor_ops, 1033 }, 1034 }; 1035 1036 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 1037 F(400000, P_BI_TCXO, 12, 1, 4), 1038 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1039 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1040 { } 1041 }; 1042 1043 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 1044 .cmd_rcgr = 0x1601c, 1045 .mnd_width = 8, 1046 .hid_width = 5, 1047 .parent_map = gcc_parent_map_0, 1048 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 1049 .clkr.hw.init = &(const struct clk_init_data) { 1050 .name = "gcc_sdcc4_apps_clk_src", 1051 .parent_data = gcc_parent_data_0, 1052 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1053 .flags = CLK_SET_RATE_PARENT, 1054 .ops = &clk_rcg2_floor_ops, 1055 }, 1056 }; 1057 1058 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 1059 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1060 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1061 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), 1062 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 1063 { } 1064 }; 1065 1066 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1067 .cmd_rcgr = 0x77034, 1068 .mnd_width = 8, 1069 .hid_width = 5, 1070 .parent_map = gcc_parent_map_3, 1071 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 1072 .clkr.hw.init = &(const struct clk_init_data) { 1073 .name = "gcc_ufs_phy_axi_clk_src", 1074 .parent_data = gcc_parent_data_3, 1075 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1076 .flags = CLK_SET_RATE_PARENT, 1077 .ops = &clk_rcg2_shared_ops, 1078 }, 1079 }; 1080 1081 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1082 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1083 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), 1084 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 1085 { } 1086 }; 1087 1088 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1089 .cmd_rcgr = 0x7708c, 1090 .mnd_width = 0, 1091 .hid_width = 5, 1092 .parent_map = gcc_parent_map_3, 1093 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1094 .clkr.hw.init = &(const struct clk_init_data) { 1095 .name = "gcc_ufs_phy_ice_core_clk_src", 1096 .parent_data = gcc_parent_data_3, 1097 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1098 .flags = CLK_SET_RATE_PARENT, 1099 .ops = &clk_rcg2_shared_ops, 1100 }, 1101 }; 1102 1103 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 1104 F(9600000, P_BI_TCXO, 2, 0, 0), 1105 F(19200000, P_BI_TCXO, 1, 0, 0), 1106 { } 1107 }; 1108 1109 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1110 .cmd_rcgr = 0x770c0, 1111 .mnd_width = 0, 1112 .hid_width = 5, 1113 .parent_map = gcc_parent_map_6, 1114 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 1115 .clkr.hw.init = &(const struct clk_init_data) { 1116 .name = "gcc_ufs_phy_phy_aux_clk_src", 1117 .parent_data = gcc_parent_data_6, 1118 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 1119 .flags = CLK_SET_RATE_PARENT, 1120 .ops = &clk_rcg2_shared_ops, 1121 }, 1122 }; 1123 1124 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1125 .cmd_rcgr = 0x770a4, 1126 .mnd_width = 0, 1127 .hid_width = 5, 1128 .parent_map = gcc_parent_map_3, 1129 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1130 .clkr.hw.init = &(const struct clk_init_data) { 1131 .name = "gcc_ufs_phy_unipro_core_clk_src", 1132 .parent_data = gcc_parent_data_3, 1133 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1134 .flags = CLK_SET_RATE_PARENT, 1135 .ops = &clk_rcg2_shared_ops, 1136 }, 1137 }; 1138 1139 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1140 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), 1141 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 1142 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1143 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 1144 { } 1145 }; 1146 1147 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1148 .cmd_rcgr = 0x39030, 1149 .mnd_width = 8, 1150 .hid_width = 5, 1151 .parent_map = gcc_parent_map_0, 1152 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1153 .clkr.hw.init = &(const struct clk_init_data) { 1154 .name = "gcc_usb30_prim_master_clk_src", 1155 .parent_data = gcc_parent_data_0, 1156 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1157 .flags = CLK_SET_RATE_PARENT, 1158 .ops = &clk_rcg2_shared_ops, 1159 }, 1160 }; 1161 1162 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1163 .cmd_rcgr = 0x39048, 1164 .mnd_width = 0, 1165 .hid_width = 5, 1166 .parent_map = gcc_parent_map_0, 1167 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1168 .clkr.hw.init = &(const struct clk_init_data) { 1169 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1170 .parent_data = gcc_parent_data_0, 1171 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1172 .flags = CLK_SET_RATE_PARENT, 1173 .ops = &clk_rcg2_shared_ops, 1174 }, 1175 }; 1176 1177 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1178 .cmd_rcgr = 0x39074, 1179 .mnd_width = 0, 1180 .hid_width = 5, 1181 .parent_map = gcc_parent_map_4, 1182 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1183 .clkr.hw.init = &(const struct clk_init_data) { 1184 .name = "gcc_usb3_prim_phy_aux_clk_src", 1185 .parent_data = gcc_parent_data_4, 1186 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1187 .flags = CLK_SET_RATE_PARENT, 1188 .ops = &clk_rcg2_shared_ops, 1189 }, 1190 }; 1191 1192 static struct clk_regmap_div gcc_qupv3_wrap1_s2_clk_src = { 1193 .reg = 0x1828c, 1194 .shift = 0, 1195 .width = 4, 1196 .clkr.hw.init = &(const struct clk_init_data) { 1197 .name = "gcc_qupv3_wrap1_s2_clk_src", 1198 .parent_hws = (const struct clk_hw*[]) { 1199 &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw, 1200 }, 1201 .num_parents = 1, 1202 .flags = CLK_SET_RATE_PARENT, 1203 .ops = &clk_regmap_div_ro_ops, 1204 }, 1205 }; 1206 1207 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1208 .reg = 0x39060, 1209 .shift = 0, 1210 .width = 4, 1211 .clkr.hw.init = &(const struct clk_init_data) { 1212 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1213 .parent_hws = (const struct clk_hw*[]) { 1214 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1215 }, 1216 .num_parents = 1, 1217 .flags = CLK_SET_RATE_PARENT, 1218 .ops = &clk_regmap_div_ro_ops, 1219 }, 1220 }; 1221 1222 static struct clk_branch gcc_aggre_noc_pcie_axi_clk = { 1223 .halt_reg = 0x10068, 1224 .halt_check = BRANCH_HALT_SKIP, 1225 .hwcg_reg = 0x10068, 1226 .hwcg_bit = 1, 1227 .clkr = { 1228 .enable_reg = 0x52000, 1229 .enable_mask = BIT(12), 1230 .hw.init = &(const struct clk_init_data) { 1231 .name = "gcc_aggre_noc_pcie_axi_clk", 1232 .ops = &clk_branch2_ops, 1233 }, 1234 }, 1235 }; 1236 1237 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1238 .halt_reg = 0x770f0, 1239 .halt_check = BRANCH_HALT_VOTED, 1240 .hwcg_reg = 0x770f0, 1241 .hwcg_bit = 1, 1242 .clkr = { 1243 .enable_reg = 0x770f0, 1244 .enable_mask = BIT(0), 1245 .hw.init = &(const struct clk_init_data) { 1246 .name = "gcc_aggre_ufs_phy_axi_clk", 1247 .parent_hws = (const struct clk_hw*[]) { 1248 &gcc_ufs_phy_axi_clk_src.clkr.hw, 1249 }, 1250 .num_parents = 1, 1251 .flags = CLK_SET_RATE_PARENT, 1252 .ops = &clk_branch2_ops, 1253 }, 1254 }, 1255 }; 1256 1257 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1258 .halt_reg = 0x39090, 1259 .halt_check = BRANCH_HALT_VOTED, 1260 .hwcg_reg = 0x39090, 1261 .hwcg_bit = 1, 1262 .clkr = { 1263 .enable_reg = 0x39090, 1264 .enable_mask = BIT(0), 1265 .hw.init = &(const struct clk_init_data) { 1266 .name = "gcc_aggre_usb3_prim_axi_clk", 1267 .parent_hws = (const struct clk_hw*[]) { 1268 &gcc_usb30_prim_master_clk_src.clkr.hw, 1269 }, 1270 .num_parents = 1, 1271 .flags = CLK_SET_RATE_PARENT, 1272 .ops = &clk_branch2_ops, 1273 }, 1274 }, 1275 }; 1276 1277 static struct clk_branch gcc_boot_rom_ahb_clk = { 1278 .halt_reg = 0x38004, 1279 .halt_check = BRANCH_HALT_VOTED, 1280 .hwcg_reg = 0x38004, 1281 .hwcg_bit = 1, 1282 .clkr = { 1283 .enable_reg = 0x52000, 1284 .enable_mask = BIT(10), 1285 .hw.init = &(const struct clk_init_data) { 1286 .name = "gcc_boot_rom_ahb_clk", 1287 .ops = &clk_branch2_ops, 1288 }, 1289 }, 1290 }; 1291 1292 static struct clk_branch gcc_camera_hf_axi_clk = { 1293 .halt_reg = 0x26014, 1294 .halt_check = BRANCH_HALT_SKIP, 1295 .hwcg_reg = 0x26014, 1296 .hwcg_bit = 1, 1297 .clkr = { 1298 .enable_reg = 0x26014, 1299 .enable_mask = BIT(0), 1300 .hw.init = &(const struct clk_init_data) { 1301 .name = "gcc_camera_hf_axi_clk", 1302 .ops = &clk_branch2_ops, 1303 }, 1304 }, 1305 }; 1306 1307 static struct clk_branch gcc_camera_sf_axi_clk = { 1308 .halt_reg = 0x26024, 1309 .halt_check = BRANCH_HALT_SKIP, 1310 .hwcg_reg = 0x26024, 1311 .hwcg_bit = 1, 1312 .clkr = { 1313 .enable_reg = 0x26024, 1314 .enable_mask = BIT(0), 1315 .hw.init = &(const struct clk_init_data) { 1316 .name = "gcc_camera_sf_axi_clk", 1317 .ops = &clk_branch2_ops, 1318 }, 1319 }, 1320 }; 1321 1322 static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = { 1323 .halt_reg = 0x10050, 1324 .halt_check = BRANCH_HALT_VOTED, 1325 .hwcg_reg = 0x10050, 1326 .hwcg_bit = 1, 1327 .clkr = { 1328 .enable_reg = 0x52000, 1329 .enable_mask = BIT(20), 1330 .hw.init = &(const struct clk_init_data) { 1331 .name = "gcc_cfg_noc_pcie_anoc_ahb_clk", 1332 .ops = &clk_branch2_ops, 1333 }, 1334 }, 1335 }; 1336 1337 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1338 .halt_reg = 0x3908c, 1339 .halt_check = BRANCH_HALT_VOTED, 1340 .hwcg_reg = 0x3908c, 1341 .hwcg_bit = 1, 1342 .clkr = { 1343 .enable_reg = 0x3908c, 1344 .enable_mask = BIT(0), 1345 .hw.init = &(const struct clk_init_data) { 1346 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1347 .parent_hws = (const struct clk_hw*[]) { 1348 &gcc_usb30_prim_master_clk_src.clkr.hw, 1349 }, 1350 .num_parents = 1, 1351 .flags = CLK_SET_RATE_PARENT, 1352 .ops = &clk_branch2_ops, 1353 }, 1354 }, 1355 }; 1356 1357 static struct clk_branch gcc_cnoc_pcie_sf_axi_clk = { 1358 .halt_reg = 0x10058, 1359 .halt_check = BRANCH_HALT_VOTED, 1360 .hwcg_reg = 0x10058, 1361 .hwcg_bit = 1, 1362 .clkr = { 1363 .enable_reg = 0x52008, 1364 .enable_mask = BIT(6), 1365 .hw.init = &(const struct clk_init_data) { 1366 .name = "gcc_cnoc_pcie_sf_axi_clk", 1367 .ops = &clk_branch2_ops, 1368 }, 1369 }, 1370 }; 1371 1372 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1373 .halt_reg = 0x71150, 1374 .halt_check = BRANCH_HALT_SKIP, 1375 .hwcg_reg = 0x71150, 1376 .hwcg_bit = 1, 1377 .clkr = { 1378 .enable_reg = 0x71150, 1379 .enable_mask = BIT(0), 1380 .hw.init = &(const struct clk_init_data) { 1381 .name = "gcc_ddrss_gpu_axi_clk", 1382 .ops = &clk_branch2_aon_ops, 1383 }, 1384 }, 1385 }; 1386 1387 static struct clk_branch gcc_ddrss_pcie_sf_qtb_clk = { 1388 .halt_reg = 0x1007c, 1389 .halt_check = BRANCH_HALT_SKIP, 1390 .hwcg_reg = 0x1007c, 1391 .hwcg_bit = 1, 1392 .clkr = { 1393 .enable_reg = 0x52000, 1394 .enable_mask = BIT(19), 1395 .hw.init = &(const struct clk_init_data) { 1396 .name = "gcc_ddrss_pcie_sf_qtb_clk", 1397 .ops = &clk_branch2_ops, 1398 }, 1399 }, 1400 }; 1401 1402 static struct clk_branch gcc_disp_hf_axi_clk = { 1403 .halt_reg = 0x27008, 1404 .halt_check = BRANCH_HALT_SKIP, 1405 .clkr = { 1406 .enable_reg = 0x27008, 1407 .enable_mask = BIT(0), 1408 .hw.init = &(const struct clk_init_data) { 1409 .name = "gcc_disp_hf_axi_clk", 1410 .ops = &clk_branch2_ops, 1411 }, 1412 }, 1413 }; 1414 1415 static struct clk_branch gcc_eva_axi0_clk = { 1416 .halt_reg = 0x9f008, 1417 .halt_check = BRANCH_HALT_SKIP, 1418 .hwcg_reg = 0x9f008, 1419 .hwcg_bit = 1, 1420 .clkr = { 1421 .enable_reg = 0x9f008, 1422 .enable_mask = BIT(0), 1423 .hw.init = &(const struct clk_init_data) { 1424 .name = "gcc_eva_axi0_clk", 1425 .ops = &clk_branch2_ops, 1426 }, 1427 }, 1428 }; 1429 1430 static struct clk_branch gcc_eva_axi0c_clk = { 1431 .halt_reg = 0x9f018, 1432 .halt_check = BRANCH_HALT_SKIP, 1433 .hwcg_reg = 0x9f018, 1434 .hwcg_bit = 1, 1435 .clkr = { 1436 .enable_reg = 0x9f018, 1437 .enable_mask = BIT(0), 1438 .hw.init = &(const struct clk_init_data) { 1439 .name = "gcc_eva_axi0c_clk", 1440 .ops = &clk_branch2_ops, 1441 }, 1442 }, 1443 }; 1444 1445 static struct clk_branch gcc_gp1_clk = { 1446 .halt_reg = 0x64000, 1447 .halt_check = BRANCH_HALT, 1448 .clkr = { 1449 .enable_reg = 0x64000, 1450 .enable_mask = BIT(0), 1451 .hw.init = &(const struct clk_init_data) { 1452 .name = "gcc_gp1_clk", 1453 .parent_hws = (const struct clk_hw*[]) { 1454 &gcc_gp1_clk_src.clkr.hw, 1455 }, 1456 .num_parents = 1, 1457 .flags = CLK_SET_RATE_PARENT, 1458 .ops = &clk_branch2_ops, 1459 }, 1460 }, 1461 }; 1462 1463 static struct clk_branch gcc_gp2_clk = { 1464 .halt_reg = 0x65000, 1465 .halt_check = BRANCH_HALT, 1466 .clkr = { 1467 .enable_reg = 0x65000, 1468 .enable_mask = BIT(0), 1469 .hw.init = &(const struct clk_init_data) { 1470 .name = "gcc_gp2_clk", 1471 .parent_hws = (const struct clk_hw*[]) { 1472 &gcc_gp2_clk_src.clkr.hw, 1473 }, 1474 .num_parents = 1, 1475 .flags = CLK_SET_RATE_PARENT, 1476 .ops = &clk_branch2_ops, 1477 }, 1478 }, 1479 }; 1480 1481 static struct clk_branch gcc_gp3_clk = { 1482 .halt_reg = 0x66000, 1483 .halt_check = BRANCH_HALT, 1484 .clkr = { 1485 .enable_reg = 0x66000, 1486 .enable_mask = BIT(0), 1487 .hw.init = &(const struct clk_init_data) { 1488 .name = "gcc_gp3_clk", 1489 .parent_hws = (const struct clk_hw*[]) { 1490 &gcc_gp3_clk_src.clkr.hw, 1491 }, 1492 .num_parents = 1, 1493 .flags = CLK_SET_RATE_PARENT, 1494 .ops = &clk_branch2_ops, 1495 }, 1496 }, 1497 }; 1498 1499 static struct clk_branch gcc_gpu_gemnoc_gfx_clk = { 1500 .halt_reg = 0x71010, 1501 .halt_check = BRANCH_HALT_VOTED, 1502 .hwcg_reg = 0x71010, 1503 .hwcg_bit = 1, 1504 .clkr = { 1505 .enable_reg = 0x71010, 1506 .enable_mask = BIT(0), 1507 .hw.init = &(const struct clk_init_data) { 1508 .name = "gcc_gpu_gemnoc_gfx_clk", 1509 .ops = &clk_branch2_ops, 1510 }, 1511 }, 1512 }; 1513 1514 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1515 .halt_check = BRANCH_HALT_DELAY, 1516 .clkr = { 1517 .enable_reg = 0x52000, 1518 .enable_mask = BIT(15), 1519 .hw.init = &(const struct clk_init_data) { 1520 .name = "gcc_gpu_gpll0_clk_src", 1521 .parent_hws = (const struct clk_hw*[]) { 1522 &gcc_gpll0.clkr.hw, 1523 }, 1524 .num_parents = 1, 1525 .flags = CLK_SET_RATE_PARENT, 1526 .ops = &clk_branch2_ops, 1527 }, 1528 }, 1529 }; 1530 1531 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1532 .halt_check = BRANCH_HALT_DELAY, 1533 .clkr = { 1534 .enable_reg = 0x52000, 1535 .enable_mask = BIT(16), 1536 .hw.init = &(const struct clk_init_data) { 1537 .name = "gcc_gpu_gpll0_div_clk_src", 1538 .parent_hws = (const struct clk_hw*[]) { 1539 &gcc_gpll0_out_even.clkr.hw, 1540 }, 1541 .num_parents = 1, 1542 .flags = CLK_SET_RATE_PARENT, 1543 .ops = &clk_branch2_ops, 1544 }, 1545 }, 1546 }; 1547 1548 static struct clk_branch gcc_pcie_0_aux_clk = { 1549 .halt_reg = 0x6b044, 1550 .halt_check = BRANCH_HALT_VOTED, 1551 .clkr = { 1552 .enable_reg = 0x52008, 1553 .enable_mask = BIT(3), 1554 .hw.init = &(const struct clk_init_data) { 1555 .name = "gcc_pcie_0_aux_clk", 1556 .parent_hws = (const struct clk_hw*[]) { 1557 &gcc_pcie_0_aux_clk_src.clkr.hw, 1558 }, 1559 .num_parents = 1, 1560 .flags = CLK_SET_RATE_PARENT, 1561 .ops = &clk_branch2_ops, 1562 }, 1563 }, 1564 }; 1565 1566 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1567 .halt_reg = 0x6b040, 1568 .halt_check = BRANCH_HALT_VOTED, 1569 .hwcg_reg = 0x6b040, 1570 .hwcg_bit = 1, 1571 .clkr = { 1572 .enable_reg = 0x52008, 1573 .enable_mask = BIT(2), 1574 .hw.init = &(const struct clk_init_data) { 1575 .name = "gcc_pcie_0_cfg_ahb_clk", 1576 .ops = &clk_branch2_ops, 1577 }, 1578 }, 1579 }; 1580 1581 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1582 .halt_reg = 0x6b030, 1583 .halt_check = BRANCH_HALT_SKIP, 1584 .hwcg_reg = 0x6b030, 1585 .hwcg_bit = 1, 1586 .clkr = { 1587 .enable_reg = 0x52008, 1588 .enable_mask = BIT(1), 1589 .hw.init = &(const struct clk_init_data) { 1590 .name = "gcc_pcie_0_mstr_axi_clk", 1591 .ops = &clk_branch2_ops, 1592 }, 1593 }, 1594 }; 1595 1596 static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 1597 .halt_reg = 0x6b064, 1598 .halt_check = BRANCH_HALT_VOTED, 1599 .clkr = { 1600 .enable_reg = 0x52000, 1601 .enable_mask = BIT(22), 1602 .hw.init = &(const struct clk_init_data) { 1603 .name = "gcc_pcie_0_phy_rchng_clk", 1604 .parent_hws = (const struct clk_hw*[]) { 1605 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 1606 }, 1607 .num_parents = 1, 1608 .flags = CLK_SET_RATE_PARENT, 1609 .ops = &clk_branch2_ops, 1610 }, 1611 }, 1612 }; 1613 1614 static struct clk_branch gcc_pcie_0_pipe_clk = { 1615 .halt_reg = 0x6b054, 1616 .halt_check = BRANCH_HALT_SKIP, 1617 .clkr = { 1618 .enable_reg = 0x52008, 1619 .enable_mask = BIT(4), 1620 .hw.init = &(const struct clk_init_data) { 1621 .name = "gcc_pcie_0_pipe_clk", 1622 .parent_hws = (const struct clk_hw*[]) { 1623 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1624 }, 1625 .num_parents = 1, 1626 .flags = CLK_SET_RATE_PARENT, 1627 .ops = &clk_branch2_ops, 1628 }, 1629 }, 1630 }; 1631 1632 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1633 .halt_reg = 0x6b020, 1634 .halt_check = BRANCH_HALT_VOTED, 1635 .hwcg_reg = 0x6b020, 1636 .hwcg_bit = 1, 1637 .clkr = { 1638 .enable_reg = 0x52008, 1639 .enable_mask = BIT(0), 1640 .hw.init = &(const struct clk_init_data) { 1641 .name = "gcc_pcie_0_slv_axi_clk", 1642 .ops = &clk_branch2_ops, 1643 }, 1644 }, 1645 }; 1646 1647 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1648 .halt_reg = 0x6b01c, 1649 .halt_check = BRANCH_HALT_VOTED, 1650 .clkr = { 1651 .enable_reg = 0x52008, 1652 .enable_mask = BIT(5), 1653 .hw.init = &(const struct clk_init_data) { 1654 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1655 .ops = &clk_branch2_ops, 1656 }, 1657 }, 1658 }; 1659 1660 static struct clk_branch gcc_pdm2_clk = { 1661 .halt_reg = 0x3300c, 1662 .halt_check = BRANCH_HALT, 1663 .clkr = { 1664 .enable_reg = 0x3300c, 1665 .enable_mask = BIT(0), 1666 .hw.init = &(const struct clk_init_data) { 1667 .name = "gcc_pdm2_clk", 1668 .parent_hws = (const struct clk_hw*[]) { 1669 &gcc_pdm2_clk_src.clkr.hw, 1670 }, 1671 .num_parents = 1, 1672 .flags = CLK_SET_RATE_PARENT, 1673 .ops = &clk_branch2_ops, 1674 }, 1675 }, 1676 }; 1677 1678 static struct clk_branch gcc_pdm_ahb_clk = { 1679 .halt_reg = 0x33004, 1680 .halt_check = BRANCH_HALT_VOTED, 1681 .hwcg_reg = 0x33004, 1682 .hwcg_bit = 1, 1683 .clkr = { 1684 .enable_reg = 0x33004, 1685 .enable_mask = BIT(0), 1686 .hw.init = &(const struct clk_init_data) { 1687 .name = "gcc_pdm_ahb_clk", 1688 .ops = &clk_branch2_ops, 1689 }, 1690 }, 1691 }; 1692 1693 static struct clk_branch gcc_pdm_xo4_clk = { 1694 .halt_reg = 0x33008, 1695 .halt_check = BRANCH_HALT, 1696 .clkr = { 1697 .enable_reg = 0x33008, 1698 .enable_mask = BIT(0), 1699 .hw.init = &(const struct clk_init_data) { 1700 .name = "gcc_pdm_xo4_clk", 1701 .ops = &clk_branch2_ops, 1702 }, 1703 }, 1704 }; 1705 1706 static struct clk_branch gcc_qmip_camera_cmd_ahb_clk = { 1707 .halt_reg = 0x26010, 1708 .halt_check = BRANCH_HALT_VOTED, 1709 .hwcg_reg = 0x26010, 1710 .hwcg_bit = 1, 1711 .clkr = { 1712 .enable_reg = 0x26010, 1713 .enable_mask = BIT(0), 1714 .hw.init = &(const struct clk_init_data) { 1715 .name = "gcc_qmip_camera_cmd_ahb_clk", 1716 .ops = &clk_branch2_ops, 1717 }, 1718 }, 1719 }; 1720 1721 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 1722 .halt_reg = 0x26008, 1723 .halt_check = BRANCH_HALT_VOTED, 1724 .hwcg_reg = 0x26008, 1725 .hwcg_bit = 1, 1726 .clkr = { 1727 .enable_reg = 0x26008, 1728 .enable_mask = BIT(0), 1729 .hw.init = &(const struct clk_init_data) { 1730 .name = "gcc_qmip_camera_nrt_ahb_clk", 1731 .ops = &clk_branch2_ops, 1732 }, 1733 }, 1734 }; 1735 1736 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 1737 .halt_reg = 0x2600c, 1738 .halt_check = BRANCH_HALT_VOTED, 1739 .hwcg_reg = 0x2600c, 1740 .hwcg_bit = 1, 1741 .clkr = { 1742 .enable_reg = 0x2600c, 1743 .enable_mask = BIT(0), 1744 .hw.init = &(const struct clk_init_data) { 1745 .name = "gcc_qmip_camera_rt_ahb_clk", 1746 .ops = &clk_branch2_ops, 1747 }, 1748 }, 1749 }; 1750 1751 static struct clk_branch gcc_qmip_gpu_ahb_clk = { 1752 .halt_reg = 0x71008, 1753 .halt_check = BRANCH_HALT_VOTED, 1754 .hwcg_reg = 0x71008, 1755 .hwcg_bit = 1, 1756 .clkr = { 1757 .enable_reg = 0x71008, 1758 .enable_mask = BIT(0), 1759 .hw.init = &(const struct clk_init_data) { 1760 .name = "gcc_qmip_gpu_ahb_clk", 1761 .ops = &clk_branch2_ops, 1762 }, 1763 }, 1764 }; 1765 1766 static struct clk_branch gcc_qmip_pcie_ahb_clk = { 1767 .halt_reg = 0x6b018, 1768 .halt_check = BRANCH_HALT_VOTED, 1769 .hwcg_reg = 0x6b018, 1770 .hwcg_bit = 1, 1771 .clkr = { 1772 .enable_reg = 0x52000, 1773 .enable_mask = BIT(11), 1774 .hw.init = &(const struct clk_init_data) { 1775 .name = "gcc_qmip_pcie_ahb_clk", 1776 .ops = &clk_branch2_ops, 1777 }, 1778 }, 1779 }; 1780 1781 static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = { 1782 .halt_reg = 0x32014, 1783 .halt_check = BRANCH_HALT_VOTED, 1784 .hwcg_reg = 0x32014, 1785 .hwcg_bit = 1, 1786 .clkr = { 1787 .enable_reg = 0x32014, 1788 .enable_mask = BIT(0), 1789 .hw.init = &(const struct clk_init_data) { 1790 .name = "gcc_qmip_video_cv_cpu_ahb_clk", 1791 .ops = &clk_branch2_ops, 1792 }, 1793 }, 1794 }; 1795 1796 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 1797 .halt_reg = 0x32008, 1798 .halt_check = BRANCH_HALT_VOTED, 1799 .hwcg_reg = 0x32008, 1800 .hwcg_bit = 1, 1801 .clkr = { 1802 .enable_reg = 0x32008, 1803 .enable_mask = BIT(0), 1804 .hw.init = &(const struct clk_init_data) { 1805 .name = "gcc_qmip_video_cvp_ahb_clk", 1806 .ops = &clk_branch2_ops, 1807 }, 1808 }, 1809 }; 1810 1811 static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = { 1812 .halt_reg = 0x32010, 1813 .halt_check = BRANCH_HALT_VOTED, 1814 .hwcg_reg = 0x32010, 1815 .hwcg_bit = 1, 1816 .clkr = { 1817 .enable_reg = 0x32010, 1818 .enable_mask = BIT(0), 1819 .hw.init = &(const struct clk_init_data) { 1820 .name = "gcc_qmip_video_v_cpu_ahb_clk", 1821 .ops = &clk_branch2_ops, 1822 }, 1823 }, 1824 }; 1825 1826 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 1827 .halt_reg = 0x3200c, 1828 .halt_check = BRANCH_HALT_VOTED, 1829 .hwcg_reg = 0x3200c, 1830 .hwcg_bit = 1, 1831 .clkr = { 1832 .enable_reg = 0x3200c, 1833 .enable_mask = BIT(0), 1834 .hw.init = &(const struct clk_init_data) { 1835 .name = "gcc_qmip_video_vcodec_ahb_clk", 1836 .ops = &clk_branch2_ops, 1837 }, 1838 }, 1839 }; 1840 1841 static struct clk_branch gcc_qupv3_i2c_core_clk = { 1842 .halt_reg = 0x23004, 1843 .halt_check = BRANCH_HALT_VOTED, 1844 .clkr = { 1845 .enable_reg = 0x52008, 1846 .enable_mask = BIT(8), 1847 .hw.init = &(const struct clk_init_data) { 1848 .name = "gcc_qupv3_i2c_core_clk", 1849 .ops = &clk_branch2_ops, 1850 }, 1851 }, 1852 }; 1853 1854 static struct clk_branch gcc_qupv3_i2c_s0_clk = { 1855 .halt_reg = 0x17004, 1856 .halt_check = BRANCH_HALT_VOTED, 1857 .clkr = { 1858 .enable_reg = 0x52008, 1859 .enable_mask = BIT(10), 1860 .hw.init = &(const struct clk_init_data) { 1861 .name = "gcc_qupv3_i2c_s0_clk", 1862 .parent_hws = (const struct clk_hw*[]) { 1863 &gcc_qupv3_i2c_s0_clk_src.clkr.hw, 1864 }, 1865 .num_parents = 1, 1866 .flags = CLK_SET_RATE_PARENT, 1867 .ops = &clk_branch2_ops, 1868 }, 1869 }, 1870 }; 1871 1872 static struct clk_branch gcc_qupv3_i2c_s1_clk = { 1873 .halt_reg = 0x17020, 1874 .halt_check = BRANCH_HALT_VOTED, 1875 .clkr = { 1876 .enable_reg = 0x52008, 1877 .enable_mask = BIT(11), 1878 .hw.init = &(const struct clk_init_data) { 1879 .name = "gcc_qupv3_i2c_s1_clk", 1880 .parent_hws = (const struct clk_hw*[]) { 1881 &gcc_qupv3_i2c_s1_clk_src.clkr.hw, 1882 }, 1883 .num_parents = 1, 1884 .flags = CLK_SET_RATE_PARENT, 1885 .ops = &clk_branch2_ops, 1886 }, 1887 }, 1888 }; 1889 1890 static struct clk_branch gcc_qupv3_i2c_s2_clk = { 1891 .halt_reg = 0x1703c, 1892 .halt_check = BRANCH_HALT_VOTED, 1893 .clkr = { 1894 .enable_reg = 0x52008, 1895 .enable_mask = BIT(12), 1896 .hw.init = &(const struct clk_init_data) { 1897 .name = "gcc_qupv3_i2c_s2_clk", 1898 .parent_hws = (const struct clk_hw*[]) { 1899 &gcc_qupv3_i2c_s2_clk_src.clkr.hw, 1900 }, 1901 .num_parents = 1, 1902 .flags = CLK_SET_RATE_PARENT, 1903 .ops = &clk_branch2_ops, 1904 }, 1905 }, 1906 }; 1907 1908 static struct clk_branch gcc_qupv3_i2c_s3_clk = { 1909 .halt_reg = 0x17058, 1910 .halt_check = BRANCH_HALT_VOTED, 1911 .clkr = { 1912 .enable_reg = 0x52008, 1913 .enable_mask = BIT(13), 1914 .hw.init = &(const struct clk_init_data) { 1915 .name = "gcc_qupv3_i2c_s3_clk", 1916 .parent_hws = (const struct clk_hw*[]) { 1917 &gcc_qupv3_i2c_s3_clk_src.clkr.hw, 1918 }, 1919 .num_parents = 1, 1920 .flags = CLK_SET_RATE_PARENT, 1921 .ops = &clk_branch2_ops, 1922 }, 1923 }, 1924 }; 1925 1926 static struct clk_branch gcc_qupv3_i2c_s4_clk = { 1927 .halt_reg = 0x17074, 1928 .halt_check = BRANCH_HALT_VOTED, 1929 .clkr = { 1930 .enable_reg = 0x52008, 1931 .enable_mask = BIT(14), 1932 .hw.init = &(const struct clk_init_data) { 1933 .name = "gcc_qupv3_i2c_s4_clk", 1934 .parent_hws = (const struct clk_hw*[]) { 1935 &gcc_qupv3_i2c_s4_clk_src.clkr.hw, 1936 }, 1937 .num_parents = 1, 1938 .flags = CLK_SET_RATE_PARENT, 1939 .ops = &clk_branch2_ops, 1940 }, 1941 }, 1942 }; 1943 1944 static struct clk_branch gcc_qupv3_i2c_s5_clk = { 1945 .halt_reg = 0x17090, 1946 .halt_check = BRANCH_HALT_VOTED, 1947 .clkr = { 1948 .enable_reg = 0x52008, 1949 .enable_mask = BIT(15), 1950 .hw.init = &(const struct clk_init_data) { 1951 .name = "gcc_qupv3_i2c_s5_clk", 1952 .parent_hws = (const struct clk_hw*[]) { 1953 &gcc_qupv3_i2c_s5_clk_src.clkr.hw, 1954 }, 1955 .num_parents = 1, 1956 .flags = CLK_SET_RATE_PARENT, 1957 .ops = &clk_branch2_ops, 1958 }, 1959 }, 1960 }; 1961 1962 static struct clk_branch gcc_qupv3_i2c_s6_clk = { 1963 .halt_reg = 0x170ac, 1964 .halt_check = BRANCH_HALT_VOTED, 1965 .clkr = { 1966 .enable_reg = 0x52008, 1967 .enable_mask = BIT(16), 1968 .hw.init = &(const struct clk_init_data) { 1969 .name = "gcc_qupv3_i2c_s6_clk", 1970 .parent_hws = (const struct clk_hw*[]) { 1971 &gcc_qupv3_i2c_s6_clk_src.clkr.hw, 1972 }, 1973 .num_parents = 1, 1974 .flags = CLK_SET_RATE_PARENT, 1975 .ops = &clk_branch2_ops, 1976 }, 1977 }, 1978 }; 1979 1980 static struct clk_branch gcc_qupv3_i2c_s7_clk = { 1981 .halt_reg = 0x170c8, 1982 .halt_check = BRANCH_HALT_VOTED, 1983 .clkr = { 1984 .enable_reg = 0x52008, 1985 .enable_mask = BIT(17), 1986 .hw.init = &(const struct clk_init_data) { 1987 .name = "gcc_qupv3_i2c_s7_clk", 1988 .parent_hws = (const struct clk_hw*[]) { 1989 &gcc_qupv3_i2c_s7_clk_src.clkr.hw, 1990 }, 1991 .num_parents = 1, 1992 .flags = CLK_SET_RATE_PARENT, 1993 .ops = &clk_branch2_ops, 1994 }, 1995 }, 1996 }; 1997 1998 static struct clk_branch gcc_qupv3_i2c_s8_clk = { 1999 .halt_reg = 0x170e4, 2000 .halt_check = BRANCH_HALT_VOTED, 2001 .clkr = { 2002 .enable_reg = 0x52010, 2003 .enable_mask = BIT(14), 2004 .hw.init = &(const struct clk_init_data) { 2005 .name = "gcc_qupv3_i2c_s8_clk", 2006 .parent_hws = (const struct clk_hw*[]) { 2007 &gcc_qupv3_i2c_s8_clk_src.clkr.hw, 2008 }, 2009 .num_parents = 1, 2010 .flags = CLK_SET_RATE_PARENT, 2011 .ops = &clk_branch2_ops, 2012 }, 2013 }, 2014 }; 2015 2016 static struct clk_branch gcc_qupv3_i2c_s9_clk = { 2017 .halt_reg = 0x17100, 2018 .halt_check = BRANCH_HALT_VOTED, 2019 .clkr = { 2020 .enable_reg = 0x52010, 2021 .enable_mask = BIT(15), 2022 .hw.init = &(const struct clk_init_data) { 2023 .name = "gcc_qupv3_i2c_s9_clk", 2024 .parent_hws = (const struct clk_hw*[]) { 2025 &gcc_qupv3_i2c_s9_clk_src.clkr.hw, 2026 }, 2027 .num_parents = 1, 2028 .flags = CLK_SET_RATE_PARENT, 2029 .ops = &clk_branch2_ops, 2030 }, 2031 }, 2032 }; 2033 2034 static struct clk_branch gcc_qupv3_i2c_s_ahb_clk = { 2035 .halt_reg = 0x23000, 2036 .halt_check = BRANCH_HALT_VOTED, 2037 .hwcg_reg = 0x23000, 2038 .hwcg_bit = 1, 2039 .clkr = { 2040 .enable_reg = 0x52008, 2041 .enable_mask = BIT(7), 2042 .hw.init = &(const struct clk_init_data) { 2043 .name = "gcc_qupv3_i2c_s_ahb_clk", 2044 .ops = &clk_branch2_ops, 2045 }, 2046 }, 2047 }; 2048 2049 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 2050 .halt_reg = 0x2315c, 2051 .halt_check = BRANCH_HALT_VOTED, 2052 .clkr = { 2053 .enable_reg = 0x52008, 2054 .enable_mask = BIT(18), 2055 .hw.init = &(const struct clk_init_data) { 2056 .name = "gcc_qupv3_wrap1_core_2x_clk", 2057 .ops = &clk_branch2_ops, 2058 }, 2059 }, 2060 }; 2061 2062 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 2063 .halt_reg = 0x23148, 2064 .halt_check = BRANCH_HALT_VOTED, 2065 .clkr = { 2066 .enable_reg = 0x52008, 2067 .enable_mask = BIT(19), 2068 .hw.init = &(const struct clk_init_data) { 2069 .name = "gcc_qupv3_wrap1_core_clk", 2070 .ops = &clk_branch2_ops, 2071 }, 2072 }, 2073 }; 2074 2075 static struct clk_branch gcc_qupv3_wrap1_qspi_ref_clk = { 2076 .halt_reg = 0x188bc, 2077 .halt_check = BRANCH_HALT_VOTED, 2078 .clkr = { 2079 .enable_reg = 0x52010, 2080 .enable_mask = BIT(29), 2081 .hw.init = &(const struct clk_init_data) { 2082 .name = "gcc_qupv3_wrap1_qspi_ref_clk", 2083 .parent_hws = (const struct clk_hw*[]) { 2084 &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw, 2085 }, 2086 .num_parents = 1, 2087 .flags = CLK_SET_RATE_PARENT, 2088 .ops = &clk_branch2_ops, 2089 }, 2090 }, 2091 }; 2092 2093 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2094 .halt_reg = 0x18004, 2095 .halt_check = BRANCH_HALT_VOTED, 2096 .clkr = { 2097 .enable_reg = 0x52008, 2098 .enable_mask = BIT(22), 2099 .hw.init = &(const struct clk_init_data) { 2100 .name = "gcc_qupv3_wrap1_s0_clk", 2101 .parent_hws = (const struct clk_hw*[]) { 2102 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 2103 }, 2104 .num_parents = 1, 2105 .flags = CLK_SET_RATE_PARENT, 2106 .ops = &clk_branch2_ops, 2107 }, 2108 }, 2109 }; 2110 2111 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2112 .halt_reg = 0x18140, 2113 .halt_check = BRANCH_HALT_VOTED, 2114 .clkr = { 2115 .enable_reg = 0x52008, 2116 .enable_mask = BIT(23), 2117 .hw.init = &(const struct clk_init_data) { 2118 .name = "gcc_qupv3_wrap1_s1_clk", 2119 .parent_hws = (const struct clk_hw*[]) { 2120 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 2121 }, 2122 .num_parents = 1, 2123 .flags = CLK_SET_RATE_PARENT, 2124 .ops = &clk_branch2_ops, 2125 }, 2126 }, 2127 }; 2128 2129 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2130 .halt_reg = 0x1827c, 2131 .halt_check = BRANCH_HALT_VOTED, 2132 .clkr = { 2133 .enable_reg = 0x52008, 2134 .enable_mask = BIT(24), 2135 .hw.init = &(const struct clk_init_data) { 2136 .name = "gcc_qupv3_wrap1_s2_clk", 2137 .parent_hws = (const struct clk_hw*[]) { 2138 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 2139 }, 2140 .num_parents = 1, 2141 .flags = CLK_SET_RATE_PARENT, 2142 .ops = &clk_branch2_ops, 2143 }, 2144 }, 2145 }; 2146 2147 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2148 .halt_reg = 0x18290, 2149 .halt_check = BRANCH_HALT_VOTED, 2150 .clkr = { 2151 .enable_reg = 0x52008, 2152 .enable_mask = BIT(25), 2153 .hw.init = &(const struct clk_init_data) { 2154 .name = "gcc_qupv3_wrap1_s3_clk", 2155 .parent_hws = (const struct clk_hw*[]) { 2156 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2157 }, 2158 .num_parents = 1, 2159 .flags = CLK_SET_RATE_PARENT, 2160 .ops = &clk_branch2_ops, 2161 }, 2162 }, 2163 }; 2164 2165 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2166 .halt_reg = 0x183cc, 2167 .halt_check = BRANCH_HALT_VOTED, 2168 .clkr = { 2169 .enable_reg = 0x52008, 2170 .enable_mask = BIT(26), 2171 .hw.init = &(const struct clk_init_data) { 2172 .name = "gcc_qupv3_wrap1_s4_clk", 2173 .parent_hws = (const struct clk_hw*[]) { 2174 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2175 }, 2176 .num_parents = 1, 2177 .flags = CLK_SET_RATE_PARENT, 2178 .ops = &clk_branch2_ops, 2179 }, 2180 }, 2181 }; 2182 2183 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2184 .halt_reg = 0x18508, 2185 .halt_check = BRANCH_HALT_VOTED, 2186 .clkr = { 2187 .enable_reg = 0x52008, 2188 .enable_mask = BIT(27), 2189 .hw.init = &(const struct clk_init_data) { 2190 .name = "gcc_qupv3_wrap1_s5_clk", 2191 .parent_hws = (const struct clk_hw*[]) { 2192 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 2193 }, 2194 .num_parents = 1, 2195 .flags = CLK_SET_RATE_PARENT, 2196 .ops = &clk_branch2_ops, 2197 }, 2198 }, 2199 }; 2200 2201 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 2202 .halt_reg = 0x18644, 2203 .halt_check = BRANCH_HALT_VOTED, 2204 .clkr = { 2205 .enable_reg = 0x52008, 2206 .enable_mask = BIT(28), 2207 .hw.init = &(const struct clk_init_data) { 2208 .name = "gcc_qupv3_wrap1_s6_clk", 2209 .parent_hws = (const struct clk_hw*[]) { 2210 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 2211 }, 2212 .num_parents = 1, 2213 .flags = CLK_SET_RATE_PARENT, 2214 .ops = &clk_branch2_ops, 2215 }, 2216 }, 2217 }; 2218 2219 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 2220 .halt_reg = 0x18780, 2221 .halt_check = BRANCH_HALT_VOTED, 2222 .clkr = { 2223 .enable_reg = 0x52010, 2224 .enable_mask = BIT(16), 2225 .hw.init = &(const struct clk_init_data) { 2226 .name = "gcc_qupv3_wrap1_s7_clk", 2227 .parent_hws = (const struct clk_hw*[]) { 2228 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 2229 }, 2230 .num_parents = 1, 2231 .flags = CLK_SET_RATE_PARENT, 2232 .ops = &clk_branch2_ops, 2233 }, 2234 }, 2235 }; 2236 2237 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { 2238 .halt_reg = 0x232b4, 2239 .halt_check = BRANCH_HALT_VOTED, 2240 .clkr = { 2241 .enable_reg = 0x52010, 2242 .enable_mask = BIT(3), 2243 .hw.init = &(const struct clk_init_data) { 2244 .name = "gcc_qupv3_wrap2_core_2x_clk", 2245 .ops = &clk_branch2_ops, 2246 }, 2247 }, 2248 }; 2249 2250 static struct clk_branch gcc_qupv3_wrap2_core_clk = { 2251 .halt_reg = 0x232a0, 2252 .halt_check = BRANCH_HALT_VOTED, 2253 .clkr = { 2254 .enable_reg = 0x52010, 2255 .enable_mask = BIT(0), 2256 .hw.init = &(const struct clk_init_data) { 2257 .name = "gcc_qupv3_wrap2_core_clk", 2258 .ops = &clk_branch2_ops, 2259 }, 2260 }, 2261 }; 2262 2263 static struct clk_branch gcc_qupv3_wrap2_ibi_ctrl_2_clk = { 2264 .halt_reg = 0x1e9ec, 2265 .halt_check = BRANCH_HALT_VOTED, 2266 .hwcg_reg = 0x1e9ec, 2267 .hwcg_bit = 1, 2268 .clkr = { 2269 .enable_reg = 0x52010, 2270 .enable_mask = BIT(27), 2271 .hw.init = &(const struct clk_init_data) { 2272 .name = "gcc_qupv3_wrap2_ibi_ctrl_2_clk", 2273 .parent_hws = (const struct clk_hw*[]) { 2274 &gcc_qupv3_wrap2_ibi_ctrl_0_clk_src.clkr.hw, 2275 }, 2276 .num_parents = 1, 2277 .flags = CLK_SET_RATE_PARENT, 2278 .ops = &clk_branch2_ops, 2279 }, 2280 }, 2281 }; 2282 2283 static struct clk_branch gcc_qupv3_wrap2_ibi_ctrl_3_clk = { 2284 .halt_reg = 0x1e9f0, 2285 .halt_check = BRANCH_HALT_VOTED, 2286 .hwcg_reg = 0x1e9f0, 2287 .hwcg_bit = 1, 2288 .clkr = { 2289 .enable_reg = 0x52010, 2290 .enable_mask = BIT(28), 2291 .hw.init = &(const struct clk_init_data) { 2292 .name = "gcc_qupv3_wrap2_ibi_ctrl_3_clk", 2293 .parent_hws = (const struct clk_hw*[]) { 2294 &gcc_qupv3_wrap2_ibi_ctrl_0_clk_src.clkr.hw, 2295 }, 2296 .num_parents = 1, 2297 .flags = CLK_SET_RATE_PARENT, 2298 .ops = &clk_branch2_ops, 2299 }, 2300 }, 2301 }; 2302 2303 static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 2304 .halt_reg = 0x1e004, 2305 .halt_check = BRANCH_HALT_VOTED, 2306 .clkr = { 2307 .enable_reg = 0x52010, 2308 .enable_mask = BIT(4), 2309 .hw.init = &(const struct clk_init_data) { 2310 .name = "gcc_qupv3_wrap2_s0_clk", 2311 .parent_hws = (const struct clk_hw*[]) { 2312 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 2313 }, 2314 .num_parents = 1, 2315 .flags = CLK_SET_RATE_PARENT, 2316 .ops = &clk_branch2_ops, 2317 }, 2318 }, 2319 }; 2320 2321 static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 2322 .halt_reg = 0x1e140, 2323 .halt_check = BRANCH_HALT_VOTED, 2324 .clkr = { 2325 .enable_reg = 0x52010, 2326 .enable_mask = BIT(5), 2327 .hw.init = &(const struct clk_init_data) { 2328 .name = "gcc_qupv3_wrap2_s1_clk", 2329 .parent_hws = (const struct clk_hw*[]) { 2330 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 2331 }, 2332 .num_parents = 1, 2333 .flags = CLK_SET_RATE_PARENT, 2334 .ops = &clk_branch2_ops, 2335 }, 2336 }, 2337 }; 2338 2339 static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 2340 .halt_reg = 0x1e27c, 2341 .halt_check = BRANCH_HALT_VOTED, 2342 .clkr = { 2343 .enable_reg = 0x52010, 2344 .enable_mask = BIT(6), 2345 .hw.init = &(const struct clk_init_data) { 2346 .name = "gcc_qupv3_wrap2_s2_clk", 2347 .parent_hws = (const struct clk_hw*[]) { 2348 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 2349 }, 2350 .num_parents = 1, 2351 .flags = CLK_SET_RATE_PARENT, 2352 .ops = &clk_branch2_ops, 2353 }, 2354 }, 2355 }; 2356 2357 static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 2358 .halt_reg = 0x1e3b8, 2359 .halt_check = BRANCH_HALT_VOTED, 2360 .clkr = { 2361 .enable_reg = 0x52010, 2362 .enable_mask = BIT(7), 2363 .hw.init = &(const struct clk_init_data) { 2364 .name = "gcc_qupv3_wrap2_s3_clk", 2365 .parent_hws = (const struct clk_hw*[]) { 2366 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 2367 }, 2368 .num_parents = 1, 2369 .flags = CLK_SET_RATE_PARENT, 2370 .ops = &clk_branch2_ops, 2371 }, 2372 }, 2373 }; 2374 2375 static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 2376 .halt_reg = 0x1e4f4, 2377 .halt_check = BRANCH_HALT_VOTED, 2378 .clkr = { 2379 .enable_reg = 0x52010, 2380 .enable_mask = BIT(8), 2381 .hw.init = &(const struct clk_init_data) { 2382 .name = "gcc_qupv3_wrap2_s4_clk", 2383 .parent_hws = (const struct clk_hw*[]) { 2384 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 2385 }, 2386 .num_parents = 1, 2387 .flags = CLK_SET_RATE_PARENT, 2388 .ops = &clk_branch2_ops, 2389 }, 2390 }, 2391 }; 2392 2393 static struct clk_branch gcc_qupv3_wrap2_s5_clk = { 2394 .halt_reg = 0x1e630, 2395 .halt_check = BRANCH_HALT_VOTED, 2396 .clkr = { 2397 .enable_reg = 0x52010, 2398 .enable_mask = BIT(9), 2399 .hw.init = &(const struct clk_init_data) { 2400 .name = "gcc_qupv3_wrap2_s5_clk", 2401 .parent_hws = (const struct clk_hw*[]) { 2402 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, 2403 }, 2404 .num_parents = 1, 2405 .flags = CLK_SET_RATE_PARENT, 2406 .ops = &clk_branch2_ops, 2407 }, 2408 }, 2409 }; 2410 2411 static struct clk_branch gcc_qupv3_wrap2_s6_clk = { 2412 .halt_reg = 0x1e76c, 2413 .halt_check = BRANCH_HALT_VOTED, 2414 .clkr = { 2415 .enable_reg = 0x52010, 2416 .enable_mask = BIT(10), 2417 .hw.init = &(const struct clk_init_data) { 2418 .name = "gcc_qupv3_wrap2_s6_clk", 2419 .parent_hws = (const struct clk_hw*[]) { 2420 &gcc_qupv3_wrap2_s6_clk_src.clkr.hw, 2421 }, 2422 .num_parents = 1, 2423 .flags = CLK_SET_RATE_PARENT, 2424 .ops = &clk_branch2_ops, 2425 }, 2426 }, 2427 }; 2428 2429 static struct clk_branch gcc_qupv3_wrap2_s7_clk = { 2430 .halt_reg = 0x1e8a8, 2431 .halt_check = BRANCH_HALT_VOTED, 2432 .clkr = { 2433 .enable_reg = 0x52010, 2434 .enable_mask = BIT(17), 2435 .hw.init = &(const struct clk_init_data) { 2436 .name = "gcc_qupv3_wrap2_s7_clk", 2437 .parent_hws = (const struct clk_hw*[]) { 2438 &gcc_qupv3_wrap2_s7_clk_src.clkr.hw, 2439 }, 2440 .num_parents = 1, 2441 .flags = CLK_SET_RATE_PARENT, 2442 .ops = &clk_branch2_ops, 2443 }, 2444 }, 2445 }; 2446 2447 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2448 .halt_reg = 0x23140, 2449 .halt_check = BRANCH_HALT_VOTED, 2450 .hwcg_reg = 0x23140, 2451 .hwcg_bit = 1, 2452 .clkr = { 2453 .enable_reg = 0x52008, 2454 .enable_mask = BIT(20), 2455 .hw.init = &(const struct clk_init_data) { 2456 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2457 .ops = &clk_branch2_ops, 2458 }, 2459 }, 2460 }; 2461 2462 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2463 .halt_reg = 0x23144, 2464 .halt_check = BRANCH_HALT_VOTED, 2465 .hwcg_reg = 0x23144, 2466 .hwcg_bit = 1, 2467 .clkr = { 2468 .enable_reg = 0x52008, 2469 .enable_mask = BIT(21), 2470 .hw.init = &(const struct clk_init_data) { 2471 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2472 .ops = &clk_branch2_ops, 2473 }, 2474 }, 2475 }; 2476 2477 static struct clk_branch gcc_qupv3_wrap_2_ibi_2_ahb_clk = { 2478 .halt_reg = 0x1e9e4, 2479 .halt_check = BRANCH_HALT_VOTED, 2480 .hwcg_reg = 0x1e9e4, 2481 .hwcg_bit = 1, 2482 .clkr = { 2483 .enable_reg = 0x52010, 2484 .enable_mask = BIT(25), 2485 .hw.init = &(const struct clk_init_data) { 2486 .name = "gcc_qupv3_wrap_2_ibi_2_ahb_clk", 2487 .ops = &clk_branch2_ops, 2488 }, 2489 }, 2490 }; 2491 2492 static struct clk_branch gcc_qupv3_wrap_2_ibi_3_ahb_clk = { 2493 .halt_reg = 0x1e9e8, 2494 .halt_check = BRANCH_HALT_VOTED, 2495 .hwcg_reg = 0x1e9e8, 2496 .hwcg_bit = 1, 2497 .clkr = { 2498 .enable_reg = 0x52010, 2499 .enable_mask = BIT(26), 2500 .hw.init = &(const struct clk_init_data) { 2501 .name = "gcc_qupv3_wrap_2_ibi_3_ahb_clk", 2502 .ops = &clk_branch2_ops, 2503 }, 2504 }, 2505 }; 2506 2507 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 2508 .halt_reg = 0x23298, 2509 .halt_check = BRANCH_HALT_VOTED, 2510 .hwcg_reg = 0x23298, 2511 .hwcg_bit = 1, 2512 .clkr = { 2513 .enable_reg = 0x52010, 2514 .enable_mask = BIT(2), 2515 .hw.init = &(const struct clk_init_data) { 2516 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 2517 .ops = &clk_branch2_ops, 2518 }, 2519 }, 2520 }; 2521 2522 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 2523 .halt_reg = 0x2329c, 2524 .halt_check = BRANCH_HALT_VOTED, 2525 .hwcg_reg = 0x2329c, 2526 .hwcg_bit = 1, 2527 .clkr = { 2528 .enable_reg = 0x52010, 2529 .enable_mask = BIT(1), 2530 .hw.init = &(const struct clk_init_data) { 2531 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 2532 .ops = &clk_branch2_ops, 2533 }, 2534 }, 2535 }; 2536 2537 static struct clk_branch gcc_sdcc2_ahb_clk = { 2538 .halt_reg = 0x14014, 2539 .halt_check = BRANCH_HALT, 2540 .clkr = { 2541 .enable_reg = 0x14014, 2542 .enable_mask = BIT(0), 2543 .hw.init = &(const struct clk_init_data) { 2544 .name = "gcc_sdcc2_ahb_clk", 2545 .ops = &clk_branch2_ops, 2546 }, 2547 }, 2548 }; 2549 2550 static struct clk_branch gcc_sdcc2_apps_clk = { 2551 .halt_reg = 0x14004, 2552 .halt_check = BRANCH_HALT, 2553 .clkr = { 2554 .enable_reg = 0x14004, 2555 .enable_mask = BIT(0), 2556 .hw.init = &(const struct clk_init_data) { 2557 .name = "gcc_sdcc2_apps_clk", 2558 .parent_hws = (const struct clk_hw*[]) { 2559 &gcc_sdcc2_apps_clk_src.clkr.hw, 2560 }, 2561 .num_parents = 1, 2562 .flags = CLK_SET_RATE_PARENT, 2563 .ops = &clk_branch2_ops, 2564 }, 2565 }, 2566 }; 2567 2568 static struct clk_branch gcc_sdcc4_ahb_clk = { 2569 .halt_reg = 0x16014, 2570 .halt_check = BRANCH_HALT, 2571 .clkr = { 2572 .enable_reg = 0x16014, 2573 .enable_mask = BIT(0), 2574 .hw.init = &(const struct clk_init_data) { 2575 .name = "gcc_sdcc4_ahb_clk", 2576 .ops = &clk_branch2_ops, 2577 }, 2578 }, 2579 }; 2580 2581 static struct clk_branch gcc_sdcc4_apps_clk = { 2582 .halt_reg = 0x16004, 2583 .halt_check = BRANCH_HALT, 2584 .clkr = { 2585 .enable_reg = 0x16004, 2586 .enable_mask = BIT(0), 2587 .hw.init = &(const struct clk_init_data) { 2588 .name = "gcc_sdcc4_apps_clk", 2589 .parent_hws = (const struct clk_hw*[]) { 2590 &gcc_sdcc4_apps_clk_src.clkr.hw, 2591 }, 2592 .num_parents = 1, 2593 .flags = CLK_SET_RATE_PARENT, 2594 .ops = &clk_branch2_ops, 2595 }, 2596 }, 2597 }; 2598 2599 static struct clk_branch gcc_ufs_phy_ahb_clk = { 2600 .halt_reg = 0x77028, 2601 .halt_check = BRANCH_HALT_VOTED, 2602 .hwcg_reg = 0x77028, 2603 .hwcg_bit = 1, 2604 .clkr = { 2605 .enable_reg = 0x77028, 2606 .enable_mask = BIT(0), 2607 .hw.init = &(const struct clk_init_data) { 2608 .name = "gcc_ufs_phy_ahb_clk", 2609 .ops = &clk_branch2_ops, 2610 }, 2611 }, 2612 }; 2613 2614 static struct clk_branch gcc_ufs_phy_axi_clk = { 2615 .halt_reg = 0x77018, 2616 .halt_check = BRANCH_HALT_VOTED, 2617 .hwcg_reg = 0x77018, 2618 .hwcg_bit = 1, 2619 .clkr = { 2620 .enable_reg = 0x77018, 2621 .enable_mask = BIT(0), 2622 .hw.init = &(const struct clk_init_data) { 2623 .name = "gcc_ufs_phy_axi_clk", 2624 .parent_hws = (const struct clk_hw*[]) { 2625 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2626 }, 2627 .num_parents = 1, 2628 .flags = CLK_SET_RATE_PARENT, 2629 .ops = &clk_branch2_ops, 2630 }, 2631 }, 2632 }; 2633 2634 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2635 .halt_reg = 0x7707c, 2636 .halt_check = BRANCH_HALT_VOTED, 2637 .hwcg_reg = 0x7707c, 2638 .hwcg_bit = 1, 2639 .clkr = { 2640 .enable_reg = 0x7707c, 2641 .enable_mask = BIT(0), 2642 .hw.init = &(const struct clk_init_data) { 2643 .name = "gcc_ufs_phy_ice_core_clk", 2644 .parent_hws = (const struct clk_hw*[]) { 2645 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2646 }, 2647 .num_parents = 1, 2648 .flags = CLK_SET_RATE_PARENT, 2649 .ops = &clk_branch2_ops, 2650 }, 2651 }, 2652 }; 2653 2654 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2655 .halt_reg = 0x770bc, 2656 .halt_check = BRANCH_HALT_VOTED, 2657 .hwcg_reg = 0x770bc, 2658 .hwcg_bit = 1, 2659 .clkr = { 2660 .enable_reg = 0x770bc, 2661 .enable_mask = BIT(0), 2662 .hw.init = &(const struct clk_init_data) { 2663 .name = "gcc_ufs_phy_phy_aux_clk", 2664 .parent_hws = (const struct clk_hw*[]) { 2665 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2666 }, 2667 .num_parents = 1, 2668 .flags = CLK_SET_RATE_PARENT, 2669 .ops = &clk_branch2_ops, 2670 }, 2671 }, 2672 }; 2673 2674 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2675 .halt_reg = 0x77030, 2676 .halt_check = BRANCH_HALT_DELAY, 2677 .clkr = { 2678 .enable_reg = 0x77030, 2679 .enable_mask = BIT(0), 2680 .hw.init = &(const struct clk_init_data) { 2681 .name = "gcc_ufs_phy_rx_symbol_0_clk", 2682 .parent_hws = (const struct clk_hw*[]) { 2683 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, 2684 }, 2685 .num_parents = 1, 2686 .flags = CLK_SET_RATE_PARENT, 2687 .ops = &clk_branch2_ops, 2688 }, 2689 }, 2690 }; 2691 2692 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 2693 .halt_reg = 0x770d8, 2694 .halt_check = BRANCH_HALT_DELAY, 2695 .clkr = { 2696 .enable_reg = 0x770d8, 2697 .enable_mask = BIT(0), 2698 .hw.init = &(const struct clk_init_data) { 2699 .name = "gcc_ufs_phy_rx_symbol_1_clk", 2700 .parent_hws = (const struct clk_hw*[]) { 2701 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, 2702 }, 2703 .num_parents = 1, 2704 .flags = CLK_SET_RATE_PARENT, 2705 .ops = &clk_branch2_ops, 2706 }, 2707 }, 2708 }; 2709 2710 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2711 .halt_reg = 0x7702c, 2712 .halt_check = BRANCH_HALT_DELAY, 2713 .clkr = { 2714 .enable_reg = 0x7702c, 2715 .enable_mask = BIT(0), 2716 .hw.init = &(const struct clk_init_data) { 2717 .name = "gcc_ufs_phy_tx_symbol_0_clk", 2718 .parent_hws = (const struct clk_hw*[]) { 2719 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, 2720 }, 2721 .num_parents = 1, 2722 .flags = CLK_SET_RATE_PARENT, 2723 .ops = &clk_branch2_ops, 2724 }, 2725 }, 2726 }; 2727 2728 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2729 .halt_reg = 0x7706c, 2730 .halt_check = BRANCH_HALT_VOTED, 2731 .hwcg_reg = 0x7706c, 2732 .hwcg_bit = 1, 2733 .clkr = { 2734 .enable_reg = 0x7706c, 2735 .enable_mask = BIT(0), 2736 .hw.init = &(const struct clk_init_data) { 2737 .name = "gcc_ufs_phy_unipro_core_clk", 2738 .parent_hws = (const struct clk_hw*[]) { 2739 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2740 }, 2741 .num_parents = 1, 2742 .flags = CLK_SET_RATE_PARENT, 2743 .ops = &clk_branch2_ops, 2744 }, 2745 }, 2746 }; 2747 2748 static struct clk_branch gcc_usb30_prim_master_clk = { 2749 .halt_reg = 0x39018, 2750 .halt_check = BRANCH_HALT, 2751 .clkr = { 2752 .enable_reg = 0x39018, 2753 .enable_mask = BIT(0), 2754 .hw.init = &(const struct clk_init_data) { 2755 .name = "gcc_usb30_prim_master_clk", 2756 .parent_hws = (const struct clk_hw*[]) { 2757 &gcc_usb30_prim_master_clk_src.clkr.hw, 2758 }, 2759 .num_parents = 1, 2760 .flags = CLK_SET_RATE_PARENT, 2761 .ops = &clk_branch2_ops, 2762 }, 2763 }, 2764 }; 2765 2766 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2767 .halt_reg = 0x3902c, 2768 .halt_check = BRANCH_HALT, 2769 .clkr = { 2770 .enable_reg = 0x3902c, 2771 .enable_mask = BIT(0), 2772 .hw.init = &(const struct clk_init_data) { 2773 .name = "gcc_usb30_prim_mock_utmi_clk", 2774 .parent_hws = (const struct clk_hw*[]) { 2775 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 2776 }, 2777 .num_parents = 1, 2778 .flags = CLK_SET_RATE_PARENT, 2779 .ops = &clk_branch2_ops, 2780 }, 2781 }, 2782 }; 2783 2784 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2785 .halt_reg = 0x39028, 2786 .halt_check = BRANCH_HALT, 2787 .clkr = { 2788 .enable_reg = 0x39028, 2789 .enable_mask = BIT(0), 2790 .hw.init = &(const struct clk_init_data) { 2791 .name = "gcc_usb30_prim_sleep_clk", 2792 .ops = &clk_branch2_ops, 2793 }, 2794 }, 2795 }; 2796 2797 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2798 .halt_reg = 0x39064, 2799 .halt_check = BRANCH_HALT, 2800 .clkr = { 2801 .enable_reg = 0x39064, 2802 .enable_mask = BIT(0), 2803 .hw.init = &(const struct clk_init_data) { 2804 .name = "gcc_usb3_prim_phy_aux_clk", 2805 .parent_hws = (const struct clk_hw*[]) { 2806 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2807 }, 2808 .num_parents = 1, 2809 .flags = CLK_SET_RATE_PARENT, 2810 .ops = &clk_branch2_ops, 2811 }, 2812 }, 2813 }; 2814 2815 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2816 .halt_reg = 0x39068, 2817 .halt_check = BRANCH_HALT, 2818 .clkr = { 2819 .enable_reg = 0x39068, 2820 .enable_mask = BIT(0), 2821 .hw.init = &(const struct clk_init_data) { 2822 .name = "gcc_usb3_prim_phy_com_aux_clk", 2823 .parent_hws = (const struct clk_hw*[]) { 2824 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2825 }, 2826 .num_parents = 1, 2827 .flags = CLK_SET_RATE_PARENT, 2828 .ops = &clk_branch2_ops, 2829 }, 2830 }, 2831 }; 2832 2833 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2834 .halt_reg = 0x3906c, 2835 .halt_check = BRANCH_HALT_DELAY, 2836 .hwcg_reg = 0x3906c, 2837 .hwcg_bit = 1, 2838 .clkr = { 2839 .enable_reg = 0x3906c, 2840 .enable_mask = BIT(0), 2841 .hw.init = &(const struct clk_init_data) { 2842 .name = "gcc_usb3_prim_phy_pipe_clk", 2843 .parent_hws = (const struct clk_hw*[]) { 2844 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 2845 }, 2846 .num_parents = 1, 2847 .flags = CLK_SET_RATE_PARENT, 2848 .ops = &clk_branch2_ops, 2849 }, 2850 }, 2851 }; 2852 2853 static struct clk_branch gcc_video_axi0_clk = { 2854 .halt_reg = 0x32018, 2855 .halt_check = BRANCH_HALT_SKIP, 2856 .hwcg_reg = 0x32018, 2857 .hwcg_bit = 1, 2858 .clkr = { 2859 .enable_reg = 0x32018, 2860 .enable_mask = BIT(0), 2861 .hw.init = &(const struct clk_init_data) { 2862 .name = "gcc_video_axi0_clk", 2863 .ops = &clk_branch2_ops, 2864 }, 2865 }, 2866 }; 2867 2868 static struct clk_branch gcc_video_axi1_clk = { 2869 .halt_reg = 0x32028, 2870 .halt_check = BRANCH_HALT_SKIP, 2871 .hwcg_reg = 0x32028, 2872 .hwcg_bit = 1, 2873 .clkr = { 2874 .enable_reg = 0x32028, 2875 .enable_mask = BIT(0), 2876 .hw.init = &(const struct clk_init_data) { 2877 .name = "gcc_video_axi1_clk", 2878 .ops = &clk_branch2_ops, 2879 }, 2880 }, 2881 }; 2882 2883 static struct gdsc gcc_pcie_0_gdsc = { 2884 .gdscr = 0x6b004, 2885 .en_rest_wait_val = 0x2, 2886 .en_few_wait_val = 0x2, 2887 .clk_dis_wait_val = 0xf, 2888 .collapse_ctrl = 0x5214c, 2889 .collapse_mask = BIT(0), 2890 .pd = { 2891 .name = "gcc_pcie_0_gdsc", 2892 }, 2893 .pwrsts = PWRSTS_OFF_ON, 2894 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 2895 }; 2896 2897 static struct gdsc gcc_pcie_0_phy_gdsc = { 2898 .gdscr = 0x6c000, 2899 .en_rest_wait_val = 0x2, 2900 .en_few_wait_val = 0x2, 2901 .clk_dis_wait_val = 0x2, 2902 .collapse_ctrl = 0x5214c, 2903 .collapse_mask = BIT(2), 2904 .pd = { 2905 .name = "gcc_pcie_0_phy_gdsc", 2906 }, 2907 .pwrsts = PWRSTS_OFF_ON, 2908 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 2909 }; 2910 2911 static struct gdsc gcc_ufs_mem_phy_gdsc = { 2912 .gdscr = 0x9e000, 2913 .en_rest_wait_val = 0x2, 2914 .en_few_wait_val = 0x2, 2915 .clk_dis_wait_val = 0x2, 2916 .pd = { 2917 .name = "gcc_ufs_mem_phy_gdsc", 2918 }, 2919 .pwrsts = PWRSTS_OFF_ON, 2920 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2921 }; 2922 2923 static struct gdsc gcc_ufs_phy_gdsc = { 2924 .gdscr = 0x77004, 2925 .en_rest_wait_val = 0x2, 2926 .en_few_wait_val = 0x2, 2927 .clk_dis_wait_val = 0xf, 2928 .pd = { 2929 .name = "gcc_ufs_phy_gdsc", 2930 }, 2931 .pwrsts = PWRSTS_OFF_ON, 2932 .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2933 }; 2934 2935 static struct gdsc gcc_usb30_prim_gdsc = { 2936 .gdscr = 0x39004, 2937 .en_rest_wait_val = 0x2, 2938 .en_few_wait_val = 0x2, 2939 .clk_dis_wait_val = 0xf, 2940 .pd = { 2941 .name = "gcc_usb30_prim_gdsc", 2942 }, 2943 .pwrsts = PWRSTS_OFF_ON, 2944 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2945 }; 2946 2947 static struct gdsc gcc_usb3_phy_gdsc = { 2948 .gdscr = 0x50018, 2949 .en_rest_wait_val = 0x2, 2950 .en_few_wait_val = 0x2, 2951 .clk_dis_wait_val = 0x2, 2952 .pd = { 2953 .name = "gcc_usb3_phy_gdsc", 2954 }, 2955 .pwrsts = PWRSTS_OFF_ON, 2956 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2957 }; 2958 2959 static struct clk_regmap *gcc_sm8750_clocks[] = { 2960 [GCC_AGGRE_NOC_PCIE_AXI_CLK] = &gcc_aggre_noc_pcie_axi_clk.clkr, 2961 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 2962 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 2963 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2964 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 2965 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 2966 [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr, 2967 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 2968 [GCC_CNOC_PCIE_SF_AXI_CLK] = &gcc_cnoc_pcie_sf_axi_clk.clkr, 2969 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 2970 [GCC_DDRSS_PCIE_SF_QTB_CLK] = &gcc_ddrss_pcie_sf_qtb_clk.clkr, 2971 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 2972 [GCC_EVA_AXI0_CLK] = &gcc_eva_axi0_clk.clkr, 2973 [GCC_EVA_AXI0C_CLK] = &gcc_eva_axi0c_clk.clkr, 2974 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2975 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 2976 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2977 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 2978 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2979 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 2980 [GCC_GPLL0] = &gcc_gpll0.clkr, 2981 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 2982 [GCC_GPLL1] = &gcc_gpll1.clkr, 2983 [GCC_GPLL4] = &gcc_gpll4.clkr, 2984 [GCC_GPLL7] = &gcc_gpll7.clkr, 2985 [GCC_GPLL9] = &gcc_gpll9.clkr, 2986 [GCC_GPU_GEMNOC_GFX_CLK] = &gcc_gpu_gemnoc_gfx_clk.clkr, 2987 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 2988 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 2989 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 2990 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 2991 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 2992 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 2993 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 2994 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 2995 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 2996 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 2997 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 2998 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 2999 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3000 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3001 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3002 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3003 [GCC_QMIP_CAMERA_CMD_AHB_CLK] = &gcc_qmip_camera_cmd_ahb_clk.clkr, 3004 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3005 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3006 [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr, 3007 [GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr, 3008 [GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr, 3009 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 3010 [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr, 3011 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3012 [GCC_QUPV3_I2C_CORE_CLK] = &gcc_qupv3_i2c_core_clk.clkr, 3013 [GCC_QUPV3_I2C_S0_CLK] = &gcc_qupv3_i2c_s0_clk.clkr, 3014 [GCC_QUPV3_I2C_S0_CLK_SRC] = &gcc_qupv3_i2c_s0_clk_src.clkr, 3015 [GCC_QUPV3_I2C_S1_CLK] = &gcc_qupv3_i2c_s1_clk.clkr, 3016 [GCC_QUPV3_I2C_S1_CLK_SRC] = &gcc_qupv3_i2c_s1_clk_src.clkr, 3017 [GCC_QUPV3_I2C_S2_CLK] = &gcc_qupv3_i2c_s2_clk.clkr, 3018 [GCC_QUPV3_I2C_S2_CLK_SRC] = &gcc_qupv3_i2c_s2_clk_src.clkr, 3019 [GCC_QUPV3_I2C_S3_CLK] = &gcc_qupv3_i2c_s3_clk.clkr, 3020 [GCC_QUPV3_I2C_S3_CLK_SRC] = &gcc_qupv3_i2c_s3_clk_src.clkr, 3021 [GCC_QUPV3_I2C_S4_CLK] = &gcc_qupv3_i2c_s4_clk.clkr, 3022 [GCC_QUPV3_I2C_S4_CLK_SRC] = &gcc_qupv3_i2c_s4_clk_src.clkr, 3023 [GCC_QUPV3_I2C_S5_CLK] = &gcc_qupv3_i2c_s5_clk.clkr, 3024 [GCC_QUPV3_I2C_S5_CLK_SRC] = &gcc_qupv3_i2c_s5_clk_src.clkr, 3025 [GCC_QUPV3_I2C_S6_CLK] = &gcc_qupv3_i2c_s6_clk.clkr, 3026 [GCC_QUPV3_I2C_S6_CLK_SRC] = &gcc_qupv3_i2c_s6_clk_src.clkr, 3027 [GCC_QUPV3_I2C_S7_CLK] = &gcc_qupv3_i2c_s7_clk.clkr, 3028 [GCC_QUPV3_I2C_S7_CLK_SRC] = &gcc_qupv3_i2c_s7_clk_src.clkr, 3029 [GCC_QUPV3_I2C_S8_CLK] = &gcc_qupv3_i2c_s8_clk.clkr, 3030 [GCC_QUPV3_I2C_S8_CLK_SRC] = &gcc_qupv3_i2c_s8_clk_src.clkr, 3031 [GCC_QUPV3_I2C_S9_CLK] = &gcc_qupv3_i2c_s9_clk.clkr, 3032 [GCC_QUPV3_I2C_S9_CLK_SRC] = &gcc_qupv3_i2c_s9_clk_src.clkr, 3033 [GCC_QUPV3_I2C_S_AHB_CLK] = &gcc_qupv3_i2c_s_ahb_clk.clkr, 3034 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 3035 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 3036 [GCC_QUPV3_WRAP1_QSPI_REF_CLK] = &gcc_qupv3_wrap1_qspi_ref_clk.clkr, 3037 [GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC] = &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr, 3038 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3039 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3040 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3041 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3042 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3043 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3044 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3045 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3046 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3047 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3048 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3049 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3050 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 3051 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 3052 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 3053 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 3054 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, 3055 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, 3056 [GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC] = &gcc_qupv3_wrap2_ibi_ctrl_0_clk_src.clkr, 3057 [GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK] = &gcc_qupv3_wrap2_ibi_ctrl_2_clk.clkr, 3058 [GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK] = &gcc_qupv3_wrap2_ibi_ctrl_3_clk.clkr, 3059 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 3060 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 3061 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 3062 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 3063 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 3064 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 3065 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 3066 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 3067 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 3068 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 3069 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, 3070 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, 3071 [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr, 3072 [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr, 3073 [GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr, 3074 [GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr, 3075 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 3076 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3077 [GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK] = &gcc_qupv3_wrap_2_ibi_2_ahb_clk.clkr, 3078 [GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK] = &gcc_qupv3_wrap_2_ibi_3_ahb_clk.clkr, 3079 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 3080 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 3081 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3082 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3083 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3084 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 3085 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 3086 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 3087 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3088 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3089 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3090 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3091 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3092 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3093 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3094 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3095 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr, 3096 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 3097 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr, 3098 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3099 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr, 3100 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3101 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 3102 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3103 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3104 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3105 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3106 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3107 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3108 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 3109 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3110 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3111 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3112 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 3113 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3114 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 3115 }; 3116 3117 static struct gdsc *gcc_sm8750_gdscs[] = { 3118 [GCC_PCIE_0_GDSC] = &gcc_pcie_0_gdsc, 3119 [GCC_PCIE_0_PHY_GDSC] = &gcc_pcie_0_phy_gdsc, 3120 [GCC_UFS_MEM_PHY_GDSC] = &gcc_ufs_mem_phy_gdsc, 3121 [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc, 3122 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, 3123 [GCC_USB3_PHY_GDSC] = &gcc_usb3_phy_gdsc, 3124 }; 3125 3126 static const struct qcom_reset_map gcc_sm8750_resets[] = { 3127 [GCC_CAMERA_BCR] = { 0x26000 }, 3128 [GCC_DISPLAY_BCR] = { 0x27000 }, 3129 [GCC_EVA_BCR] = { 0x9f000 }, 3130 [GCC_EVA_AXI0_CLK_ARES] = { 0x9f008, 2 }, 3131 [GCC_EVA_AXI0C_CLK_ARES] = { 0x9f018, 2 }, 3132 [GCC_GPU_BCR] = { 0x71000 }, 3133 [GCC_PCIE_0_BCR] = { 0x6b000 }, 3134 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, 3135 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, 3136 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 3137 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 }, 3138 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 3139 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c }, 3140 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, 3141 [GCC_PCIE_RSCC_BCR] = { 0x11000 }, 3142 [GCC_PDM_BCR] = { 0x33000 }, 3143 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, 3144 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, 3145 [GCC_QUPV3_WRAPPER_I2C_BCR] = { 0x17000 }, 3146 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 3147 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 3148 [GCC_SDCC2_BCR] = { 0x14000 }, 3149 [GCC_SDCC4_BCR] = { 0x16000 }, 3150 [GCC_UFS_PHY_BCR] = { 0x77000 }, 3151 [GCC_USB30_PRIM_BCR] = { 0x39000 }, 3152 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 3153 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, 3154 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 3155 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 3156 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 3157 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 3158 [GCC_VIDEO_BCR] = { 0x32000 }, 3159 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 }, 3160 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x32028, 2 }, 3161 }; 3162 3163 3164 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3165 DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_ref_clk_src), 3166 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3167 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3168 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3169 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3170 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3171 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 3172 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 3173 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 3174 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 3175 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), 3176 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), 3177 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 3178 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), 3179 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src), 3180 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src), 3181 }; 3182 3183 static const struct regmap_config gcc_sm8750_regmap_config = { 3184 .reg_bits = 32, 3185 .reg_stride = 4, 3186 .val_bits = 32, 3187 .max_register = 0x1f41f0, 3188 .fast_io = true, 3189 }; 3190 3191 static const struct qcom_cc_desc gcc_sm8750_desc = { 3192 .config = &gcc_sm8750_regmap_config, 3193 .clks = gcc_sm8750_clocks, 3194 .num_clks = ARRAY_SIZE(gcc_sm8750_clocks), 3195 .resets = gcc_sm8750_resets, 3196 .num_resets = ARRAY_SIZE(gcc_sm8750_resets), 3197 .gdscs = gcc_sm8750_gdscs, 3198 .num_gdscs = ARRAY_SIZE(gcc_sm8750_gdscs), 3199 }; 3200 3201 static const struct of_device_id gcc_sm8750_match_table[] = { 3202 { .compatible = "qcom,sm8750-gcc" }, 3203 { } 3204 }; 3205 MODULE_DEVICE_TABLE(of, gcc_sm8750_match_table); 3206 3207 static int gcc_sm8750_probe(struct platform_device *pdev) 3208 { 3209 struct regmap *regmap; 3210 int ret; 3211 3212 regmap = qcom_cc_map(pdev, &gcc_sm8750_desc); 3213 if (IS_ERR(regmap)) 3214 return PTR_ERR(regmap); 3215 3216 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3217 ARRAY_SIZE(gcc_dfs_clocks)); 3218 if (ret) 3219 return ret; 3220 3221 /* 3222 * Keep clocks always enabled: 3223 * gcc_cam_bist_mclk_ahb_clk 3224 * gcc_camera_ahb_clk 3225 * gcc_camera_xo_clk 3226 * gcc_disp_ahb_clk 3227 * gcc_eva_ahb_clk 3228 * gcc_eva_xo_clk 3229 * gcc_gpu_cfg_ahb_clk 3230 * gcc_video_ahb_clk 3231 * gcc_video_xo_clk 3232 * gcc_pcie_rscc_cfg_ahb_clk 3233 * gcc_pcie_rscc_xo_clk 3234 */ 3235 qcom_branch_set_clk_en(regmap, 0xa0004); 3236 qcom_branch_set_clk_en(regmap, 0x26004); 3237 qcom_branch_set_clk_en(regmap, 0x26034); 3238 qcom_branch_set_clk_en(regmap, 0x27004); 3239 qcom_branch_set_clk_en(regmap, 0x9f004); 3240 qcom_branch_set_clk_en(regmap, 0x9f01c); 3241 qcom_branch_set_clk_en(regmap, 0x71004); 3242 qcom_branch_set_clk_en(regmap, 0x32004); 3243 qcom_branch_set_clk_en(regmap, 0x32038); 3244 regmap_update_bits(regmap, 0x52010, BIT(20), BIT(20)); 3245 regmap_update_bits(regmap, 0x52010, BIT(21), BIT(21)); 3246 3247 /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ 3248 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); 3249 3250 return qcom_cc_really_probe(&pdev->dev, &gcc_sm8750_desc, regmap); 3251 } 3252 3253 static struct platform_driver gcc_sm8750_driver = { 3254 .probe = gcc_sm8750_probe, 3255 .driver = { 3256 .name = "gcc-sm8750", 3257 .of_match_table = gcc_sm8750_match_table, 3258 }, 3259 }; 3260 3261 static int __init gcc_sm8750_init(void) 3262 { 3263 return platform_driver_register(&gcc_sm8750_driver); 3264 } 3265 subsys_initcall(gcc_sm8750_init); 3266 3267 static void __exit gcc_sm8750_exit(void) 3268 { 3269 platform_driver_unregister(&gcc_sm8750_driver); 3270 } 3271 module_exit(gcc_sm8750_exit); 3272 3273 MODULE_DESCRIPTION("QTI GCC SM8750 Driver"); 3274 MODULE_LICENSE("GPL"); 3275