1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/module.h> 9 #include <linux/of_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,sm6375-gcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "clk-regmap-divider.h" 19 #include "clk-regmap-mux.h" 20 #include "clk-regmap-phy-mux.h" 21 #include "gdsc.h" 22 #include "reset.h" 23 24 enum { 25 DT_BI_TCXO, 26 DT_BI_TCXO_AO, 27 DT_SLEEP_CLK 28 }; 29 30 enum { 31 P_BI_TCXO, 32 P_GPLL0_OUT_EVEN, 33 P_GPLL0_OUT_MAIN, 34 P_GPLL0_OUT_ODD, 35 P_GPLL10_OUT_EVEN, 36 P_GPLL11_OUT_EVEN, 37 P_GPLL11_OUT_ODD, 38 P_GPLL3_OUT_EVEN, 39 P_GPLL3_OUT_MAIN, 40 P_GPLL4_OUT_EVEN, 41 P_GPLL5_OUT_EVEN, 42 P_GPLL6_OUT_EVEN, 43 P_GPLL6_OUT_MAIN, 44 P_GPLL7_OUT_EVEN, 45 P_GPLL8_OUT_EVEN, 46 P_GPLL8_OUT_MAIN, 47 P_GPLL9_OUT_EARLY, 48 P_GPLL9_OUT_MAIN, 49 P_SLEEP_CLK, 50 }; 51 52 static struct pll_vco lucid_vco[] = { 53 { 249600000, 2000000000, 0 }, 54 }; 55 56 static struct pll_vco zonda_vco[] = { 57 { 595200000, 3600000000UL, 0 }, 58 }; 59 60 static struct clk_alpha_pll gpll0 = { 61 .offset = 0x0, 62 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 63 .clkr = { 64 .enable_reg = 0x79000, 65 .enable_mask = BIT(0), 66 .hw.init = &(struct clk_init_data){ 67 .name = "gpll0", 68 .parent_data = &(const struct clk_parent_data){ 69 .index = DT_BI_TCXO, 70 }, 71 .num_parents = 1, 72 .ops = &clk_alpha_pll_fixed_lucid_ops, 73 }, 74 }, 75 }; 76 77 static const struct clk_div_table post_div_table_gpll0_out_even[] = { 78 { 0x1, 2 }, 79 { } 80 }; 81 82 static struct clk_alpha_pll_postdiv gpll0_out_even = { 83 .offset = 0x0, 84 .post_div_shift = 8, 85 .post_div_table = post_div_table_gpll0_out_even, 86 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even), 87 .width = 4, 88 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 89 .clkr.hw.init = &(struct clk_init_data){ 90 .name = "gpll0_out_even", 91 .parent_hws = (const struct clk_hw*[]){ 92 &gpll0.clkr.hw, 93 }, 94 .num_parents = 1, 95 .ops = &clk_alpha_pll_postdiv_lucid_ops, 96 }, 97 }; 98 99 static const struct clk_div_table post_div_table_gpll0_out_odd[] = { 100 { 0x3, 3 }, 101 { } 102 }; 103 104 static struct clk_alpha_pll_postdiv gpll0_out_odd = { 105 .offset = 0x0, 106 .post_div_shift = 12, 107 .post_div_table = post_div_table_gpll0_out_odd, 108 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_odd), 109 .width = 4, 110 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 111 .clkr.hw.init = &(struct clk_init_data){ 112 .name = "gpll0_out_odd", 113 .parent_hws = (const struct clk_hw*[]){ 114 &gpll0.clkr.hw, 115 }, 116 .num_parents = 1, 117 .ops = &clk_alpha_pll_postdiv_lucid_ops, 118 }, 119 }; 120 121 static struct clk_alpha_pll gpll1 = { 122 .offset = 0x1000, 123 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 124 .clkr = { 125 .enable_reg = 0x79000, 126 .enable_mask = BIT(1), 127 .hw.init = &(struct clk_init_data){ 128 .name = "gpll1", 129 .parent_data = &(const struct clk_parent_data){ 130 .index = DT_BI_TCXO, 131 }, 132 .num_parents = 1, 133 .ops = &clk_alpha_pll_lucid_ops, 134 }, 135 }, 136 }; 137 138 /* 1152MHz Configuration */ 139 static const struct alpha_pll_config gpll10_config = { 140 .l = 0x3c, 141 .alpha = 0x0, 142 .config_ctl_val = 0x20485699, 143 .config_ctl_hi_val = 0x00002261, 144 .config_ctl_hi1_val = 0x329a299c, 145 .user_ctl_val = 0x00000001, 146 .user_ctl_hi_val = 0x00000805, 147 .user_ctl_hi1_val = 0x00000000, 148 }; 149 150 static struct clk_alpha_pll gpll10 = { 151 .offset = 0xa000, 152 .vco_table = lucid_vco, 153 .num_vco = ARRAY_SIZE(lucid_vco), 154 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 155 .flags = SUPPORTS_FSM_LEGACY_MODE, 156 .clkr = { 157 .enable_reg = 0x79000, 158 .enable_mask = BIT(10), 159 .hw.init = &(struct clk_init_data){ 160 .name = "gpll10", 161 .parent_data = &(const struct clk_parent_data){ 162 .index = DT_BI_TCXO, 163 }, 164 .num_parents = 1, 165 .ops = &clk_alpha_pll_fixed_lucid_ops, 166 }, 167 }, 168 }; 169 170 /* 532MHz Configuration */ 171 static const struct alpha_pll_config gpll11_config = { 172 .l = 0x1b, 173 .alpha = 0xb555, 174 .config_ctl_val = 0x20485699, 175 .config_ctl_hi_val = 0x00002261, 176 .config_ctl_hi1_val = 0x329a299c, 177 .user_ctl_val = 0x00000001, 178 .user_ctl_hi_val = 0x00000805, 179 .user_ctl_hi1_val = 0x00000000, 180 }; 181 182 static struct clk_alpha_pll gpll11 = { 183 .offset = 0xb000, 184 .vco_table = lucid_vco, 185 .num_vco = ARRAY_SIZE(lucid_vco), 186 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 187 .flags = SUPPORTS_FSM_LEGACY_MODE, 188 .clkr = { 189 .enable_reg = 0x79000, 190 .enable_mask = BIT(11), 191 .hw.init = &(struct clk_init_data){ 192 .name = "gpll11", 193 .parent_data = &(const struct clk_parent_data){ 194 .index = DT_BI_TCXO, 195 }, 196 .num_parents = 1, 197 .ops = &clk_alpha_pll_lucid_ops, 198 }, 199 }, 200 }; 201 202 static struct clk_alpha_pll gpll3 = { 203 .offset = 0x3000, 204 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 205 .clkr = { 206 .enable_reg = 0x79000, 207 .enable_mask = BIT(3), 208 .hw.init = &(struct clk_init_data){ 209 .name = "gpll3", 210 .parent_data = &(const struct clk_parent_data){ 211 .index = DT_BI_TCXO, 212 }, 213 .num_parents = 1, 214 .ops = &clk_alpha_pll_fixed_lucid_ops, 215 }, 216 }, 217 }; 218 219 static const struct clk_div_table post_div_table_gpll3_out_even[] = { 220 { 0x1, 2 }, 221 { } 222 }; 223 224 static struct clk_alpha_pll_postdiv gpll3_out_even = { 225 .offset = 0x3000, 226 .post_div_shift = 8, 227 .post_div_table = post_div_table_gpll3_out_even, 228 .num_post_div = ARRAY_SIZE(post_div_table_gpll3_out_even), 229 .width = 4, 230 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 231 .clkr.hw.init = &(struct clk_init_data){ 232 .name = "gpll3_out_even", 233 .parent_hws = (const struct clk_hw*[]){ 234 &gpll3.clkr.hw, 235 }, 236 .num_parents = 1, 237 .ops = &clk_alpha_pll_postdiv_lucid_ops, 238 }, 239 }; 240 241 static struct clk_alpha_pll gpll4 = { 242 .offset = 0x4000, 243 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 244 .clkr = { 245 .enable_reg = 0x79000, 246 .enable_mask = BIT(4), 247 .hw.init = &(struct clk_init_data){ 248 .name = "gpll4", 249 .parent_data = &(const struct clk_parent_data){ 250 .index = DT_BI_TCXO, 251 }, 252 .num_parents = 1, 253 .ops = &clk_alpha_pll_fixed_lucid_ops, 254 }, 255 }, 256 }; 257 258 static struct clk_alpha_pll gpll5 = { 259 .offset = 0x5000, 260 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 261 .clkr = { 262 .enable_reg = 0x79000, 263 .enable_mask = BIT(5), 264 .hw.init = &(struct clk_init_data){ 265 .name = "gpll5", 266 .parent_data = &(const struct clk_parent_data){ 267 .index = DT_BI_TCXO, 268 }, 269 .num_parents = 1, 270 .ops = &clk_alpha_pll_fixed_lucid_ops, 271 }, 272 }, 273 }; 274 275 static struct clk_alpha_pll gpll6 = { 276 .offset = 0x6000, 277 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 278 .clkr = { 279 .enable_reg = 0x79000, 280 .enable_mask = BIT(6), 281 .hw.init = &(struct clk_init_data){ 282 .name = "gpll6", 283 .parent_data = &(const struct clk_parent_data){ 284 .index = DT_BI_TCXO, 285 }, 286 .num_parents = 1, 287 .ops = &clk_alpha_pll_fixed_lucid_ops, 288 }, 289 }, 290 }; 291 292 static const struct clk_div_table post_div_table_gpll6_out_even[] = { 293 { 0x1, 2 }, 294 { } 295 }; 296 297 static struct clk_alpha_pll_postdiv gpll6_out_even = { 298 .offset = 0x6000, 299 .post_div_shift = 8, 300 .post_div_table = post_div_table_gpll6_out_even, 301 .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_even), 302 .width = 4, 303 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 304 .clkr.hw.init = &(struct clk_init_data){ 305 .name = "gpll6_out_even", 306 .parent_hws = (const struct clk_hw*[]){ 307 &gpll6.clkr.hw, 308 }, 309 .num_parents = 1, 310 .ops = &clk_alpha_pll_postdiv_lucid_ops, 311 }, 312 }; 313 314 static struct clk_alpha_pll gpll7 = { 315 .offset = 0x7000, 316 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 317 .clkr = { 318 .enable_reg = 0x79000, 319 .enable_mask = BIT(7), 320 .hw.init = &(struct clk_init_data){ 321 .name = "gpll7", 322 .parent_data = &(const struct clk_parent_data){ 323 .index = DT_BI_TCXO, 324 }, 325 .num_parents = 1, 326 .ops = &clk_alpha_pll_fixed_lucid_ops, 327 }, 328 }, 329 }; 330 331 /* 400MHz Configuration */ 332 static const struct alpha_pll_config gpll8_config = { 333 .l = 0x14, 334 .alpha = 0xd555, 335 .config_ctl_val = 0x20485699, 336 .config_ctl_hi_val = 0x00002261, 337 .config_ctl_hi1_val = 0x329a299c, 338 .user_ctl_val = 0x00000101, 339 .user_ctl_hi_val = 0x00000805, 340 .user_ctl_hi1_val = 0x00000000, 341 }; 342 343 static struct clk_alpha_pll gpll8 = { 344 .offset = 0x8000, 345 .vco_table = lucid_vco, 346 .num_vco = ARRAY_SIZE(lucid_vco), 347 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 348 .flags = SUPPORTS_FSM_LEGACY_MODE, 349 .clkr = { 350 .enable_reg = 0x79000, 351 .enable_mask = BIT(8), 352 .hw.init = &(struct clk_init_data){ 353 .name = "gpll8", 354 .parent_data = &(const struct clk_parent_data){ 355 .index = DT_BI_TCXO, 356 }, 357 .num_parents = 1, 358 .ops = &clk_alpha_pll_lucid_ops, 359 }, 360 }, 361 }; 362 363 static const struct clk_div_table post_div_table_gpll8_out_even[] = { 364 { 0x1, 2 }, 365 { } 366 }; 367 368 static struct clk_alpha_pll_postdiv gpll8_out_even = { 369 .offset = 0x8000, 370 .post_div_shift = 8, 371 .post_div_table = post_div_table_gpll8_out_even, 372 .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_even), 373 .width = 4, 374 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 375 .clkr.hw.init = &(struct clk_init_data){ 376 .name = "gpll8_out_even", 377 .parent_hws = (const struct clk_hw*[]){ 378 &gpll8.clkr.hw, 379 }, 380 .num_parents = 1, 381 .flags = CLK_SET_RATE_PARENT, 382 .ops = &clk_alpha_pll_postdiv_lucid_ops, 383 }, 384 }; 385 386 /* 1440MHz Configuration */ 387 static const struct alpha_pll_config gpll9_config = { 388 .l = 0x4b, 389 .alpha = 0x0, 390 .config_ctl_val = 0x08200800, 391 .config_ctl_hi_val = 0x05022011, 392 .config_ctl_hi1_val = 0x08000000, 393 .user_ctl_val = 0x00000301, 394 }; 395 396 static struct clk_alpha_pll gpll9 = { 397 .offset = 0x9000, 398 .vco_table = zonda_vco, 399 .num_vco = ARRAY_SIZE(zonda_vco), 400 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], 401 .clkr = { 402 .enable_reg = 0x79000, 403 .enable_mask = BIT(9), 404 .hw.init = &(struct clk_init_data){ 405 .name = "gpll9", 406 .parent_data = &(const struct clk_parent_data){ 407 .index = DT_BI_TCXO, 408 }, 409 .num_parents = 1, 410 .ops = &clk_alpha_pll_zonda_ops, 411 }, 412 }, 413 }; 414 415 static const struct clk_div_table post_div_table_gpll9_out_main[] = { 416 { 0x3, 4 }, 417 { } 418 }; 419 420 static struct clk_alpha_pll_postdiv gpll9_out_main = { 421 .offset = 0x9000, 422 .post_div_shift = 8, 423 .post_div_table = post_div_table_gpll9_out_main, 424 .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main), 425 .width = 2, 426 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], 427 .clkr.hw.init = &(struct clk_init_data){ 428 .name = "gpll9_out_main", 429 .parent_hws = (const struct clk_hw*[]){ 430 &gpll9.clkr.hw, 431 }, 432 .num_parents = 1, 433 .flags = CLK_SET_RATE_PARENT, 434 .ops = &clk_alpha_pll_postdiv_zonda_ops, 435 }, 436 }; 437 438 static const struct parent_map gcc_parent_map_0[] = { 439 { P_BI_TCXO, 0 }, 440 { P_GPLL0_OUT_MAIN, 1 }, 441 { P_GPLL0_OUT_EVEN, 2 }, 442 }; 443 444 static const struct clk_parent_data gcc_parent_data_0[] = { 445 { .index = DT_BI_TCXO }, 446 { .hw = &gpll0.clkr.hw }, 447 { .hw = &gpll0_out_even.clkr.hw }, 448 }; 449 450 static const struct parent_map gcc_parent_map_1[] = { 451 { P_BI_TCXO, 0 }, 452 { P_GPLL0_OUT_MAIN, 1 }, 453 { P_GPLL0_OUT_EVEN, 2 }, 454 { P_GPLL6_OUT_EVEN, 4 }, 455 }; 456 457 static const struct clk_parent_data gcc_parent_data_1[] = { 458 { .index = DT_BI_TCXO }, 459 { .hw = &gpll0.clkr.hw }, 460 { .hw = &gpll0_out_even.clkr.hw }, 461 { .hw = &gpll6_out_even.clkr.hw }, 462 }; 463 464 static const struct parent_map gcc_parent_map_2[] = { 465 { P_BI_TCXO, 0 }, 466 { P_GPLL0_OUT_MAIN, 1 }, 467 { P_GPLL0_OUT_EVEN, 2 }, 468 { P_GPLL0_OUT_ODD, 4 }, 469 }; 470 471 static const struct clk_parent_data gcc_parent_data_2[] = { 472 { .index = DT_BI_TCXO }, 473 { .hw = &gpll0.clkr.hw }, 474 { .hw = &gpll0_out_even.clkr.hw }, 475 { .hw = &gpll0_out_odd.clkr.hw }, 476 }; 477 478 static const struct clk_parent_data gcc_parent_data_2_ao[] = { 479 { .index = DT_BI_TCXO_AO }, 480 { .hw = &gpll0.clkr.hw }, 481 { .hw = &gpll0_out_even.clkr.hw }, 482 { .hw = &gpll0_out_odd.clkr.hw }, 483 }; 484 485 static const struct parent_map gcc_parent_map_3[] = { 486 { P_BI_TCXO, 0 }, 487 { P_GPLL0_OUT_MAIN, 1 }, 488 { P_GPLL9_OUT_EARLY, 2 }, 489 { P_GPLL10_OUT_EVEN, 3 }, 490 { P_GPLL9_OUT_MAIN, 4 }, 491 { P_GPLL3_OUT_EVEN, 6 }, 492 }; 493 494 static const struct clk_parent_data gcc_parent_data_3[] = { 495 { .index = DT_BI_TCXO }, 496 { .hw = &gpll0.clkr.hw }, 497 { .hw = &gpll9.clkr.hw }, 498 { .hw = &gpll10.clkr.hw }, 499 { .hw = &gpll9_out_main.clkr.hw }, 500 { .hw = &gpll3_out_even.clkr.hw }, 501 }; 502 503 static const struct parent_map gcc_parent_map_4[] = { 504 { P_BI_TCXO, 0 }, 505 { P_GPLL0_OUT_MAIN, 1 }, 506 { P_GPLL0_OUT_EVEN, 2 }, 507 { P_GPLL0_OUT_ODD, 4 }, 508 { P_GPLL4_OUT_EVEN, 5 }, 509 { P_GPLL3_OUT_EVEN, 6 }, 510 }; 511 512 static const struct clk_parent_data gcc_parent_data_4[] = { 513 { .index = DT_BI_TCXO }, 514 { .hw = &gpll0.clkr.hw }, 515 { .hw = &gpll0_out_even.clkr.hw }, 516 { .hw = &gpll0_out_odd.clkr.hw }, 517 { .hw = &gpll4.clkr.hw }, 518 { .hw = &gpll3_out_even.clkr.hw }, 519 }; 520 521 static const struct parent_map gcc_parent_map_5[] = { 522 { P_BI_TCXO, 0 }, 523 { P_GPLL0_OUT_MAIN, 1 }, 524 { P_GPLL8_OUT_MAIN, 2 }, 525 { P_GPLL10_OUT_EVEN, 3 }, 526 { P_GPLL9_OUT_MAIN, 4 }, 527 { P_GPLL8_OUT_EVEN, 5 }, 528 { P_GPLL3_OUT_EVEN, 6 }, 529 }; 530 531 static const struct clk_parent_data gcc_parent_data_5[] = { 532 { .index = DT_BI_TCXO }, 533 { .hw = &gpll0.clkr.hw }, 534 { .hw = &gpll8.clkr.hw }, 535 { .hw = &gpll10.clkr.hw }, 536 { .hw = &gpll9_out_main.clkr.hw }, 537 { .hw = &gpll8_out_even.clkr.hw }, 538 { .hw = &gpll3_out_even.clkr.hw }, 539 }; 540 541 static const struct parent_map gcc_parent_map_6[] = { 542 { P_BI_TCXO, 0 }, 543 { P_GPLL0_OUT_MAIN, 1 }, 544 { P_GPLL8_OUT_MAIN, 2 }, 545 { P_GPLL5_OUT_EVEN, 3 }, 546 { P_GPLL9_OUT_MAIN, 4 }, 547 { P_GPLL8_OUT_EVEN, 5 }, 548 { P_GPLL3_OUT_MAIN, 6 }, 549 }; 550 551 static const struct clk_parent_data gcc_parent_data_6[] = { 552 { .index = DT_BI_TCXO }, 553 { .hw = &gpll0.clkr.hw }, 554 { .hw = &gpll8.clkr.hw }, 555 { .hw = &gpll5.clkr.hw }, 556 { .hw = &gpll9_out_main.clkr.hw }, 557 { .hw = &gpll8_out_even.clkr.hw }, 558 { .hw = &gpll3.clkr.hw }, 559 }; 560 561 static const struct parent_map gcc_parent_map_7[] = { 562 { P_BI_TCXO, 0 }, 563 { P_GPLL0_OUT_MAIN, 1 }, 564 { P_GPLL0_OUT_EVEN, 2 }, 565 { P_GPLL0_OUT_ODD, 4 }, 566 { P_SLEEP_CLK, 5 }, 567 }; 568 569 static const struct clk_parent_data gcc_parent_data_7[] = { 570 { .index = DT_BI_TCXO }, 571 { .hw = &gpll0.clkr.hw }, 572 { .hw = &gpll0_out_even.clkr.hw }, 573 { .hw = &gpll0_out_odd.clkr.hw }, 574 { .index = DT_SLEEP_CLK }, 575 }; 576 577 static const struct parent_map gcc_parent_map_8[] = { 578 { P_BI_TCXO, 0 }, 579 { P_GPLL0_OUT_MAIN, 1 }, 580 { P_GPLL0_OUT_EVEN, 2 }, 581 { P_GPLL10_OUT_EVEN, 3 }, 582 { P_GPLL4_OUT_EVEN, 5 }, 583 { P_GPLL3_OUT_MAIN, 6 }, 584 }; 585 586 static const struct clk_parent_data gcc_parent_data_8[] = { 587 { .index = DT_BI_TCXO }, 588 { .hw = &gpll0.clkr.hw }, 589 { .hw = &gpll0_out_even.clkr.hw }, 590 { .hw = &gpll10.clkr.hw }, 591 { .hw = &gpll4.clkr.hw }, 592 { .hw = &gpll3.clkr.hw }, 593 }; 594 595 static const struct parent_map gcc_parent_map_9[] = { 596 { P_BI_TCXO, 0 }, 597 { P_GPLL0_OUT_MAIN, 1 }, 598 { P_GPLL0_OUT_EVEN, 2 }, 599 { P_GPLL10_OUT_EVEN, 3 }, 600 { P_GPLL9_OUT_MAIN, 4 }, 601 { P_GPLL8_OUT_EVEN, 5 }, 602 { P_GPLL3_OUT_MAIN, 6 }, 603 }; 604 605 static const struct clk_parent_data gcc_parent_data_9[] = { 606 { .index = DT_BI_TCXO }, 607 { .hw = &gpll0.clkr.hw }, 608 { .hw = &gpll0_out_even.clkr.hw }, 609 { .hw = &gpll10.clkr.hw }, 610 { .hw = &gpll9_out_main.clkr.hw }, 611 { .hw = &gpll8_out_even.clkr.hw }, 612 { .hw = &gpll3.clkr.hw }, 613 }; 614 615 static const struct parent_map gcc_parent_map_10[] = { 616 { P_BI_TCXO, 0 }, 617 { P_GPLL0_OUT_MAIN, 1 }, 618 { P_GPLL8_OUT_MAIN, 2 }, 619 { P_GPLL10_OUT_EVEN, 3 }, 620 { P_GPLL9_OUT_MAIN, 4 }, 621 { P_GPLL8_OUT_EVEN, 5 }, 622 { P_GPLL3_OUT_MAIN, 6 }, 623 }; 624 625 static const struct clk_parent_data gcc_parent_data_10[] = { 626 { .index = DT_BI_TCXO }, 627 { .hw = &gpll0.clkr.hw }, 628 { .hw = &gpll8.clkr.hw }, 629 { .hw = &gpll10.clkr.hw }, 630 { .hw = &gpll9_out_main.clkr.hw }, 631 { .hw = &gpll8_out_even.clkr.hw }, 632 { .hw = &gpll3.clkr.hw }, 633 }; 634 635 static const struct parent_map gcc_parent_map_11[] = { 636 { P_BI_TCXO, 0 }, 637 { P_GPLL0_OUT_MAIN, 1 }, 638 { P_GPLL8_OUT_MAIN, 2 }, 639 { P_GPLL10_OUT_EVEN, 3 }, 640 { P_GPLL6_OUT_MAIN, 4 }, 641 { P_GPLL3_OUT_EVEN, 6 }, 642 }; 643 644 static const struct clk_parent_data gcc_parent_data_11[] = { 645 { .index = DT_BI_TCXO }, 646 { .hw = &gpll0.clkr.hw }, 647 { .hw = &gpll8.clkr.hw }, 648 { .hw = &gpll10.clkr.hw }, 649 { .hw = &gpll6.clkr.hw }, 650 { .hw = &gpll3_out_even.clkr.hw }, 651 }; 652 653 static const struct parent_map gcc_parent_map_12[] = { 654 { P_BI_TCXO, 0 }, 655 { P_GPLL0_OUT_MAIN, 1 }, 656 { P_GPLL0_OUT_EVEN, 2 }, 657 { P_GPLL7_OUT_EVEN, 3 }, 658 { P_GPLL4_OUT_EVEN, 5 }, 659 }; 660 661 static const struct clk_parent_data gcc_parent_data_12[] = { 662 { .index = DT_BI_TCXO }, 663 { .hw = &gpll0.clkr.hw }, 664 { .hw = &gpll0_out_even.clkr.hw }, 665 { .hw = &gpll7.clkr.hw }, 666 { .hw = &gpll4.clkr.hw }, 667 }; 668 669 static const struct parent_map gcc_parent_map_13[] = { 670 { P_BI_TCXO, 0 }, 671 { P_SLEEP_CLK, 5 }, 672 }; 673 674 static const struct clk_parent_data gcc_parent_data_13[] = { 675 { .index = DT_BI_TCXO }, 676 { .index = DT_SLEEP_CLK }, 677 }; 678 679 static const struct parent_map gcc_parent_map_14[] = { 680 { P_BI_TCXO, 0 }, 681 { P_GPLL11_OUT_ODD, 2 }, 682 { P_GPLL11_OUT_EVEN, 3 }, 683 }; 684 685 static const struct clk_parent_data gcc_parent_data_14[] = { 686 { .index = DT_BI_TCXO }, 687 { .hw = &gpll11.clkr.hw }, 688 { .hw = &gpll11.clkr.hw }, 689 }; 690 691 static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = { 692 F(19200000, P_BI_TCXO, 1, 0, 0), 693 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 694 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 695 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 696 { } 697 }; 698 699 static struct clk_rcg2 gcc_camss_axi_clk_src = { 700 .cmd_rcgr = 0x5802c, 701 .mnd_width = 0, 702 .hid_width = 5, 703 .parent_map = gcc_parent_map_8, 704 .freq_tbl = ftbl_gcc_camss_axi_clk_src, 705 .clkr.hw.init = &(struct clk_init_data){ 706 .name = "gcc_camss_axi_clk_src", 707 .parent_data = gcc_parent_data_8, 708 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 709 .ops = &clk_rcg2_shared_ops, 710 }, 711 }; 712 713 static const struct freq_tbl ftbl_gcc_camss_cci_0_clk_src[] = { 714 F(19200000, P_BI_TCXO, 1, 0, 0), 715 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 716 { } 717 }; 718 719 static struct clk_rcg2 gcc_camss_cci_0_clk_src = { 720 .cmd_rcgr = 0x56000, 721 .mnd_width = 0, 722 .hid_width = 5, 723 .parent_map = gcc_parent_map_9, 724 .freq_tbl = ftbl_gcc_camss_cci_0_clk_src, 725 .clkr.hw.init = &(struct clk_init_data){ 726 .name = "gcc_camss_cci_0_clk_src", 727 .parent_data = gcc_parent_data_9, 728 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 729 .ops = &clk_rcg2_shared_ops, 730 }, 731 }; 732 733 static struct clk_rcg2 gcc_camss_cci_1_clk_src = { 734 .cmd_rcgr = 0x5c000, 735 .mnd_width = 0, 736 .hid_width = 5, 737 .parent_map = gcc_parent_map_9, 738 .freq_tbl = ftbl_gcc_camss_cci_0_clk_src, 739 .clkr.hw.init = &(struct clk_init_data){ 740 .name = "gcc_camss_cci_1_clk_src", 741 .parent_data = gcc_parent_data_9, 742 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 743 .ops = &clk_rcg2_shared_ops, 744 }, 745 }; 746 747 static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = { 748 F(19200000, P_BI_TCXO, 1, 0, 0), 749 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0), 750 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 751 { } 752 }; 753 754 static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = { 755 .cmd_rcgr = 0x59000, 756 .mnd_width = 0, 757 .hid_width = 5, 758 .parent_map = gcc_parent_map_4, 759 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 760 .clkr.hw.init = &(struct clk_init_data){ 761 .name = "gcc_camss_csi0phytimer_clk_src", 762 .parent_data = gcc_parent_data_4, 763 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 764 .ops = &clk_rcg2_shared_ops, 765 }, 766 }; 767 768 static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = { 769 .cmd_rcgr = 0x5901c, 770 .mnd_width = 0, 771 .hid_width = 5, 772 .parent_map = gcc_parent_map_4, 773 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 774 .clkr.hw.init = &(struct clk_init_data){ 775 .name = "gcc_camss_csi1phytimer_clk_src", 776 .parent_data = gcc_parent_data_4, 777 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 778 .ops = &clk_rcg2_shared_ops, 779 }, 780 }; 781 782 static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = { 783 .cmd_rcgr = 0x59038, 784 .mnd_width = 0, 785 .hid_width = 5, 786 .parent_map = gcc_parent_map_4, 787 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 788 .clkr.hw.init = &(struct clk_init_data){ 789 .name = "gcc_camss_csi2phytimer_clk_src", 790 .parent_data = gcc_parent_data_4, 791 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 792 .ops = &clk_rcg2_shared_ops, 793 }, 794 }; 795 796 static struct clk_rcg2 gcc_camss_csi3phytimer_clk_src = { 797 .cmd_rcgr = 0x59054, 798 .mnd_width = 0, 799 .hid_width = 5, 800 .parent_map = gcc_parent_map_4, 801 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 802 .clkr.hw.init = &(struct clk_init_data){ 803 .name = "gcc_camss_csi3phytimer_clk_src", 804 .parent_data = gcc_parent_data_4, 805 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 806 .ops = &clk_rcg2_shared_ops, 807 }, 808 }; 809 810 static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = { 811 F(19200000, P_BI_TCXO, 1, 0, 0), 812 F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 15), 813 F(65454545, P_GPLL9_OUT_EARLY, 11, 1, 2), 814 { } 815 }; 816 817 static struct clk_rcg2 gcc_camss_mclk0_clk_src = { 818 .cmd_rcgr = 0x51000, 819 .mnd_width = 8, 820 .hid_width = 5, 821 .parent_map = gcc_parent_map_3, 822 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 823 .clkr.hw.init = &(struct clk_init_data){ 824 .name = "gcc_camss_mclk0_clk_src", 825 .parent_data = gcc_parent_data_3, 826 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 827 .ops = &clk_rcg2_shared_ops, 828 }, 829 }; 830 831 static struct clk_rcg2 gcc_camss_mclk1_clk_src = { 832 .cmd_rcgr = 0x5101c, 833 .mnd_width = 8, 834 .hid_width = 5, 835 .parent_map = gcc_parent_map_3, 836 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 837 .clkr.hw.init = &(struct clk_init_data){ 838 .name = "gcc_camss_mclk1_clk_src", 839 .parent_data = gcc_parent_data_3, 840 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 841 .ops = &clk_rcg2_shared_ops, 842 }, 843 }; 844 845 static struct clk_rcg2 gcc_camss_mclk2_clk_src = { 846 .cmd_rcgr = 0x51038, 847 .mnd_width = 8, 848 .hid_width = 5, 849 .parent_map = gcc_parent_map_3, 850 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 851 .clkr.hw.init = &(struct clk_init_data){ 852 .name = "gcc_camss_mclk2_clk_src", 853 .parent_data = gcc_parent_data_3, 854 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 855 .ops = &clk_rcg2_shared_ops, 856 }, 857 }; 858 859 static struct clk_rcg2 gcc_camss_mclk3_clk_src = { 860 .cmd_rcgr = 0x51054, 861 .mnd_width = 8, 862 .hid_width = 5, 863 .parent_map = gcc_parent_map_3, 864 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 865 .clkr.hw.init = &(struct clk_init_data){ 866 .name = "gcc_camss_mclk3_clk_src", 867 .parent_data = gcc_parent_data_3, 868 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 869 .ops = &clk_rcg2_shared_ops, 870 }, 871 }; 872 873 static struct clk_rcg2 gcc_camss_mclk4_clk_src = { 874 .cmd_rcgr = 0x51070, 875 .mnd_width = 8, 876 .hid_width = 5, 877 .parent_map = gcc_parent_map_3, 878 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 879 .clkr.hw.init = &(struct clk_init_data){ 880 .name = "gcc_camss_mclk4_clk_src", 881 .parent_data = gcc_parent_data_3, 882 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 883 .ops = &clk_rcg2_shared_ops, 884 }, 885 }; 886 887 static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = { 888 F(19200000, P_BI_TCXO, 1, 0, 0), 889 F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0), 890 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 891 { } 892 }; 893 894 static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = { 895 .cmd_rcgr = 0x55024, 896 .mnd_width = 0, 897 .hid_width = 5, 898 .parent_map = gcc_parent_map_10, 899 .freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src, 900 .clkr.hw.init = &(struct clk_init_data){ 901 .name = "gcc_camss_ope_ahb_clk_src", 902 .parent_data = gcc_parent_data_10, 903 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 904 .ops = &clk_rcg2_shared_ops, 905 }, 906 }; 907 908 static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = { 909 F(19200000, P_BI_TCXO, 1, 0, 0), 910 F(200000000, P_GPLL8_OUT_EVEN, 1, 0, 0), 911 F(266600000, P_GPLL8_OUT_EVEN, 1, 0, 0), 912 F(480000000, P_GPLL8_OUT_EVEN, 1, 0, 0), 913 F(580000000, P_GPLL8_OUT_EVEN, 1, 0, 0), 914 { } 915 }; 916 917 static struct clk_rcg2 gcc_camss_ope_clk_src = { 918 .cmd_rcgr = 0x55004, 919 .mnd_width = 0, 920 .hid_width = 5, 921 .parent_map = gcc_parent_map_10, 922 .freq_tbl = ftbl_gcc_camss_ope_clk_src, 923 .clkr.hw.init = &(struct clk_init_data){ 924 .name = "gcc_camss_ope_clk_src", 925 .parent_data = gcc_parent_data_10, 926 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 927 .flags = CLK_SET_RATE_PARENT, 928 .ops = &clk_rcg2_shared_ops, 929 }, 930 }; 931 932 static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = { 933 F(19200000, P_BI_TCXO, 1, 0, 0), 934 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), 935 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 936 F(144000000, P_GPLL9_OUT_MAIN, 2.5, 0, 0), 937 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 938 F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0), 939 F(180000000, P_GPLL9_OUT_MAIN, 2, 0, 0), 940 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 941 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 942 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 943 F(329142857, P_GPLL10_OUT_EVEN, 3.5, 0, 0), 944 F(384000000, P_GPLL10_OUT_EVEN, 3, 0, 0), 945 F(460800000, P_GPLL10_OUT_EVEN, 2.5, 0, 0), 946 F(576000000, P_GPLL10_OUT_EVEN, 2, 0, 0), 947 { } 948 }; 949 950 static struct clk_rcg2 gcc_camss_tfe_0_clk_src = { 951 .cmd_rcgr = 0x52004, 952 .mnd_width = 8, 953 .hid_width = 5, 954 .parent_map = gcc_parent_map_5, 955 .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 956 .clkr.hw.init = &(struct clk_init_data){ 957 .name = "gcc_camss_tfe_0_clk_src", 958 .parent_data = gcc_parent_data_5, 959 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 960 .ops = &clk_rcg2_shared_ops, 961 }, 962 }; 963 964 static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = { 965 F(19200000, P_BI_TCXO, 1, 0, 0), 966 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), 967 F(266571429, P_GPLL5_OUT_EVEN, 3.5, 0, 0), 968 F(426400000, P_GPLL3_OUT_MAIN, 2.5, 0, 0), 969 F(466500000, P_GPLL5_OUT_EVEN, 2, 0, 0), 970 { } 971 }; 972 973 static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = { 974 .cmd_rcgr = 0x52094, 975 .mnd_width = 0, 976 .hid_width = 5, 977 .parent_map = gcc_parent_map_6, 978 .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 979 .clkr.hw.init = &(struct clk_init_data){ 980 .name = "gcc_camss_tfe_0_csid_clk_src", 981 .parent_data = gcc_parent_data_6, 982 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 983 .ops = &clk_rcg2_shared_ops, 984 }, 985 }; 986 987 static struct clk_rcg2 gcc_camss_tfe_1_clk_src = { 988 .cmd_rcgr = 0x52024, 989 .mnd_width = 8, 990 .hid_width = 5, 991 .parent_map = gcc_parent_map_5, 992 .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 993 .clkr.hw.init = &(struct clk_init_data){ 994 .name = "gcc_camss_tfe_1_clk_src", 995 .parent_data = gcc_parent_data_5, 996 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 997 .ops = &clk_rcg2_shared_ops, 998 }, 999 }; 1000 1001 static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = { 1002 .cmd_rcgr = 0x520b4, 1003 .mnd_width = 0, 1004 .hid_width = 5, 1005 .parent_map = gcc_parent_map_6, 1006 .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 1007 .clkr.hw.init = &(struct clk_init_data){ 1008 .name = "gcc_camss_tfe_1_csid_clk_src", 1009 .parent_data = gcc_parent_data_6, 1010 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 1011 .ops = &clk_rcg2_shared_ops, 1012 }, 1013 }; 1014 1015 static struct clk_rcg2 gcc_camss_tfe_2_clk_src = { 1016 .cmd_rcgr = 0x52044, 1017 .mnd_width = 8, 1018 .hid_width = 5, 1019 .parent_map = gcc_parent_map_5, 1020 .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 1021 .clkr.hw.init = &(struct clk_init_data){ 1022 .name = "gcc_camss_tfe_2_clk_src", 1023 .parent_data = gcc_parent_data_5, 1024 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1025 .ops = &clk_rcg2_shared_ops, 1026 }, 1027 }; 1028 1029 static struct clk_rcg2 gcc_camss_tfe_2_csid_clk_src = { 1030 .cmd_rcgr = 0x520d4, 1031 .mnd_width = 0, 1032 .hid_width = 5, 1033 .parent_map = gcc_parent_map_6, 1034 .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 1035 .clkr.hw.init = &(struct clk_init_data){ 1036 .name = "gcc_camss_tfe_2_csid_clk_src", 1037 .parent_data = gcc_parent_data_6, 1038 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 1039 .ops = &clk_rcg2_shared_ops, 1040 }, 1041 }; 1042 1043 static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = { 1044 F(19200000, P_BI_TCXO, 1, 0, 0), 1045 F(256000000, P_GPLL6_OUT_MAIN, 3, 0, 0), 1046 F(384000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 1047 { } 1048 }; 1049 1050 static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = { 1051 .cmd_rcgr = 0x52064, 1052 .mnd_width = 0, 1053 .hid_width = 5, 1054 .parent_map = gcc_parent_map_11, 1055 .freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src, 1056 .clkr.hw.init = &(struct clk_init_data){ 1057 .name = "gcc_camss_tfe_cphy_rx_clk_src", 1058 .parent_data = gcc_parent_data_11, 1059 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 1060 .ops = &clk_rcg2_shared_ops, 1061 }, 1062 }; 1063 1064 static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = { 1065 F(19200000, P_BI_TCXO, 1, 0, 0), 1066 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0), 1067 F(80000000, P_GPLL0_OUT_MAIN, 7.5, 0, 0), 1068 { } 1069 }; 1070 1071 static struct clk_rcg2 gcc_camss_top_ahb_clk_src = { 1072 .cmd_rcgr = 0x58010, 1073 .mnd_width = 0, 1074 .hid_width = 5, 1075 .parent_map = gcc_parent_map_8, 1076 .freq_tbl = ftbl_gcc_camss_top_ahb_clk_src, 1077 .clkr.hw.init = &(struct clk_init_data){ 1078 .name = "gcc_camss_top_ahb_clk_src", 1079 .parent_data = gcc_parent_data_8, 1080 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 1081 .ops = &clk_rcg2_shared_ops, 1082 }, 1083 }; 1084 1085 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { 1086 F(19200000, P_BI_TCXO, 1, 0, 0), 1087 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0), 1088 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0), 1089 { } 1090 }; 1091 1092 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { 1093 .cmd_rcgr = 0x2b13c, 1094 .mnd_width = 0, 1095 .hid_width = 5, 1096 .parent_map = gcc_parent_map_2, 1097 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, 1098 .clkr.hw.init = &(struct clk_init_data){ 1099 .name = "gcc_cpuss_ahb_clk_src", 1100 .parent_data = gcc_parent_data_2_ao, 1101 .num_parents = ARRAY_SIZE(gcc_parent_data_2_ao), 1102 .ops = &clk_rcg2_shared_ops, 1103 }, 1104 }; 1105 1106 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 1107 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 1108 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0), 1109 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0), 1110 F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0), 1111 { } 1112 }; 1113 1114 static struct clk_rcg2 gcc_gp1_clk_src = { 1115 .cmd_rcgr = 0x4d004, 1116 .mnd_width = 16, 1117 .hid_width = 5, 1118 .parent_map = gcc_parent_map_7, 1119 .freq_tbl = ftbl_gcc_gp1_clk_src, 1120 .clkr.hw.init = &(struct clk_init_data){ 1121 .name = "gcc_gp1_clk_src", 1122 .parent_data = gcc_parent_data_7, 1123 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 1124 .ops = &clk_rcg2_shared_ops, 1125 }, 1126 }; 1127 1128 static struct clk_rcg2 gcc_gp2_clk_src = { 1129 .cmd_rcgr = 0x4e004, 1130 .mnd_width = 16, 1131 .hid_width = 5, 1132 .parent_map = gcc_parent_map_7, 1133 .freq_tbl = ftbl_gcc_gp1_clk_src, 1134 .clkr.hw.init = &(struct clk_init_data){ 1135 .name = "gcc_gp2_clk_src", 1136 .parent_data = gcc_parent_data_7, 1137 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 1138 .ops = &clk_rcg2_shared_ops, 1139 }, 1140 }; 1141 1142 static struct clk_rcg2 gcc_gp3_clk_src = { 1143 .cmd_rcgr = 0x4f004, 1144 .mnd_width = 16, 1145 .hid_width = 5, 1146 .parent_map = gcc_parent_map_7, 1147 .freq_tbl = ftbl_gcc_gp1_clk_src, 1148 .clkr.hw.init = &(struct clk_init_data){ 1149 .name = "gcc_gp3_clk_src", 1150 .parent_data = gcc_parent_data_7, 1151 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 1152 .ops = &clk_rcg2_shared_ops, 1153 }, 1154 }; 1155 1156 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 1157 F(19200000, P_BI_TCXO, 1, 0, 0), 1158 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0), 1159 { } 1160 }; 1161 1162 static struct clk_rcg2 gcc_pdm2_clk_src = { 1163 .cmd_rcgr = 0x20010, 1164 .mnd_width = 0, 1165 .hid_width = 5, 1166 .parent_map = gcc_parent_map_0, 1167 .freq_tbl = ftbl_gcc_pdm2_clk_src, 1168 .clkr.hw.init = &(struct clk_init_data){ 1169 .name = "gcc_pdm2_clk_src", 1170 .parent_data = gcc_parent_data_0, 1171 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1172 .ops = &clk_rcg2_shared_ops, 1173 }, 1174 }; 1175 1176 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 1177 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), 1178 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), 1179 F(19200000, P_BI_TCXO, 1, 0, 0), 1180 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), 1181 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), 1182 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), 1183 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), 1184 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 1185 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), 1186 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), 1187 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 1188 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), 1189 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), 1190 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), 1191 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), 1192 F(128000000, P_GPLL6_OUT_EVEN, 3, 0, 0), 1193 { } 1194 }; 1195 1196 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 1197 .name = "gcc_qupv3_wrap0_s0_clk_src", 1198 .parent_data = gcc_parent_data_1, 1199 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1200 .ops = &clk_rcg2_shared_ops, 1201 }; 1202 1203 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 1204 .cmd_rcgr = 0x1f148, 1205 .mnd_width = 16, 1206 .hid_width = 5, 1207 .parent_map = gcc_parent_map_1, 1208 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1209 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 1210 }; 1211 1212 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 1213 .name = "gcc_qupv3_wrap0_s1_clk_src", 1214 .parent_data = gcc_parent_data_1, 1215 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1216 .ops = &clk_rcg2_shared_ops, 1217 }; 1218 1219 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 1220 .cmd_rcgr = 0x1f278, 1221 .mnd_width = 16, 1222 .hid_width = 5, 1223 .parent_map = gcc_parent_map_1, 1224 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1225 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 1226 }; 1227 1228 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 1229 .name = "gcc_qupv3_wrap0_s2_clk_src", 1230 .parent_data = gcc_parent_data_1, 1231 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1232 .ops = &clk_rcg2_shared_ops, 1233 }; 1234 1235 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 1236 .cmd_rcgr = 0x1f3a8, 1237 .mnd_width = 16, 1238 .hid_width = 5, 1239 .parent_map = gcc_parent_map_1, 1240 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1241 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 1242 }; 1243 1244 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 1245 .name = "gcc_qupv3_wrap0_s3_clk_src", 1246 .parent_data = gcc_parent_data_1, 1247 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1248 .ops = &clk_rcg2_shared_ops, 1249 }; 1250 1251 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 1252 .cmd_rcgr = 0x1f4d8, 1253 .mnd_width = 16, 1254 .hid_width = 5, 1255 .parent_map = gcc_parent_map_1, 1256 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1257 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 1258 }; 1259 1260 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 1261 .name = "gcc_qupv3_wrap0_s4_clk_src", 1262 .parent_data = gcc_parent_data_1, 1263 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1264 .ops = &clk_rcg2_shared_ops, 1265 }; 1266 1267 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 1268 .cmd_rcgr = 0x1f608, 1269 .mnd_width = 16, 1270 .hid_width = 5, 1271 .parent_map = gcc_parent_map_1, 1272 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1273 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 1274 }; 1275 1276 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 1277 .name = "gcc_qupv3_wrap0_s5_clk_src", 1278 .parent_data = gcc_parent_data_1, 1279 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1280 .ops = &clk_rcg2_shared_ops, 1281 }; 1282 1283 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 1284 .cmd_rcgr = 0x1f738, 1285 .mnd_width = 16, 1286 .hid_width = 5, 1287 .parent_map = gcc_parent_map_1, 1288 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1289 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 1290 }; 1291 1292 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 1293 .name = "gcc_qupv3_wrap1_s0_clk_src", 1294 .parent_data = gcc_parent_data_1, 1295 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1296 .ops = &clk_rcg2_shared_ops, 1297 }; 1298 1299 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 1300 .cmd_rcgr = 0x5301c, 1301 .mnd_width = 16, 1302 .hid_width = 5, 1303 .parent_map = gcc_parent_map_1, 1304 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1305 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 1306 }; 1307 1308 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 1309 .name = "gcc_qupv3_wrap1_s1_clk_src", 1310 .parent_data = gcc_parent_data_1, 1311 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1312 .ops = &clk_rcg2_shared_ops, 1313 }; 1314 1315 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 1316 .cmd_rcgr = 0x5314c, 1317 .mnd_width = 16, 1318 .hid_width = 5, 1319 .parent_map = gcc_parent_map_1, 1320 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1321 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 1322 }; 1323 1324 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 1325 .name = "gcc_qupv3_wrap1_s2_clk_src", 1326 .parent_data = gcc_parent_data_1, 1327 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1328 .ops = &clk_rcg2_shared_ops, 1329 }; 1330 1331 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 1332 .cmd_rcgr = 0x5327c, 1333 .mnd_width = 16, 1334 .hid_width = 5, 1335 .parent_map = gcc_parent_map_1, 1336 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1337 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 1338 }; 1339 1340 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 1341 .name = "gcc_qupv3_wrap1_s3_clk_src", 1342 .parent_data = gcc_parent_data_1, 1343 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1344 .ops = &clk_rcg2_shared_ops, 1345 }; 1346 1347 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 1348 .cmd_rcgr = 0x533ac, 1349 .mnd_width = 16, 1350 .hid_width = 5, 1351 .parent_map = gcc_parent_map_1, 1352 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1353 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 1354 }; 1355 1356 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 1357 .name = "gcc_qupv3_wrap1_s4_clk_src", 1358 .parent_data = gcc_parent_data_1, 1359 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1360 .ops = &clk_rcg2_shared_ops, 1361 }; 1362 1363 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 1364 .cmd_rcgr = 0x534dc, 1365 .mnd_width = 16, 1366 .hid_width = 5, 1367 .parent_map = gcc_parent_map_1, 1368 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1369 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 1370 }; 1371 1372 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 1373 .name = "gcc_qupv3_wrap1_s5_clk_src", 1374 .parent_data = gcc_parent_data_1, 1375 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1376 .ops = &clk_rcg2_shared_ops, 1377 }; 1378 1379 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 1380 .cmd_rcgr = 0x5360c, 1381 .mnd_width = 16, 1382 .hid_width = 5, 1383 .parent_map = gcc_parent_map_1, 1384 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1385 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 1386 }; 1387 1388 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 1389 F(144000, P_BI_TCXO, 16, 3, 25), 1390 F(400000, P_BI_TCXO, 12, 1, 4), 1391 F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3), 1392 F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), 1393 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 1394 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 1395 F(192000000, P_GPLL6_OUT_EVEN, 2, 0, 0), 1396 F(384000000, P_GPLL6_OUT_EVEN, 1, 0, 0), 1397 { } 1398 }; 1399 1400 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 1401 .cmd_rcgr = 0x38028, 1402 .mnd_width = 8, 1403 .hid_width = 5, 1404 .parent_map = gcc_parent_map_1, 1405 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 1406 .clkr.hw.init = &(struct clk_init_data){ 1407 .name = "gcc_sdcc1_apps_clk_src", 1408 .parent_data = gcc_parent_data_1, 1409 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1410 .ops = &clk_rcg2_shared_ops, 1411 }, 1412 }; 1413 1414 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 1415 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 1416 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 1417 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 1418 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 1419 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 1420 { } 1421 }; 1422 1423 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 1424 .cmd_rcgr = 0x38010, 1425 .mnd_width = 0, 1426 .hid_width = 5, 1427 .parent_map = gcc_parent_map_0, 1428 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 1429 .clkr.hw.init = &(struct clk_init_data){ 1430 .name = "gcc_sdcc1_ice_core_clk_src", 1431 .parent_data = gcc_parent_data_0, 1432 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1433 .ops = &clk_rcg2_shared_ops, 1434 }, 1435 }; 1436 1437 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1438 F(400000, P_BI_TCXO, 12, 1, 4), 1439 F(19200000, P_BI_TCXO, 1, 0, 0), 1440 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 1441 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 1442 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 1443 F(202000000, P_GPLL7_OUT_EVEN, 4, 0, 0), 1444 { } 1445 }; 1446 1447 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1448 .cmd_rcgr = 0x1e00c, 1449 .mnd_width = 8, 1450 .hid_width = 5, 1451 .parent_map = gcc_parent_map_12, 1452 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1453 .clkr.hw.init = &(struct clk_init_data){ 1454 .name = "gcc_sdcc2_apps_clk_src", 1455 .parent_data = gcc_parent_data_12, 1456 .num_parents = ARRAY_SIZE(gcc_parent_data_12), 1457 .ops = &clk_rcg2_shared_ops, 1458 }, 1459 }; 1460 1461 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 1462 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 1463 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0), 1464 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0), 1465 F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0), 1466 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 1467 { } 1468 }; 1469 1470 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1471 .cmd_rcgr = 0x45020, 1472 .mnd_width = 8, 1473 .hid_width = 5, 1474 .parent_map = gcc_parent_map_2, 1475 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 1476 .clkr.hw.init = &(struct clk_init_data){ 1477 .name = "gcc_ufs_phy_axi_clk_src", 1478 .parent_data = gcc_parent_data_2, 1479 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1480 .ops = &clk_rcg2_shared_ops, 1481 }, 1482 }; 1483 1484 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1485 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 1486 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 1487 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 1488 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 1489 { } 1490 }; 1491 1492 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1493 .cmd_rcgr = 0x45048, 1494 .mnd_width = 0, 1495 .hid_width = 5, 1496 .parent_map = gcc_parent_map_0, 1497 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1498 .clkr.hw.init = &(struct clk_init_data){ 1499 .name = "gcc_ufs_phy_ice_core_clk_src", 1500 .parent_data = gcc_parent_data_0, 1501 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1502 .ops = &clk_rcg2_shared_ops, 1503 }, 1504 }; 1505 1506 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 1507 F(9600000, P_BI_TCXO, 2, 0, 0), 1508 F(19200000, P_BI_TCXO, 1, 0, 0), 1509 { } 1510 }; 1511 1512 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1513 .cmd_rcgr = 0x4507c, 1514 .mnd_width = 0, 1515 .hid_width = 5, 1516 .parent_map = gcc_parent_map_0, 1517 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 1518 .clkr.hw.init = &(struct clk_init_data){ 1519 .name = "gcc_ufs_phy_phy_aux_clk_src", 1520 .parent_data = gcc_parent_data_0, 1521 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1522 .ops = &clk_rcg2_shared_ops, 1523 }, 1524 }; 1525 1526 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { 1527 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 1528 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 1529 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 1530 { } 1531 }; 1532 1533 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1534 .cmd_rcgr = 0x45060, 1535 .mnd_width = 0, 1536 .hid_width = 5, 1537 .parent_map = gcc_parent_map_0, 1538 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, 1539 .clkr.hw.init = &(struct clk_init_data){ 1540 .name = "gcc_ufs_phy_unipro_core_clk_src", 1541 .parent_data = gcc_parent_data_0, 1542 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1543 .ops = &clk_rcg2_shared_ops, 1544 }, 1545 }; 1546 1547 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1548 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), 1549 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 1550 F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0), 1551 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 1552 { } 1553 }; 1554 1555 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1556 .cmd_rcgr = 0x1a01c, 1557 .mnd_width = 8, 1558 .hid_width = 5, 1559 .parent_map = gcc_parent_map_2, 1560 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1561 .clkr.hw.init = &(struct clk_init_data){ 1562 .name = "gcc_usb30_prim_master_clk_src", 1563 .parent_data = gcc_parent_data_2, 1564 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1565 .ops = &clk_rcg2_shared_ops, 1566 }, 1567 }; 1568 1569 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 1570 F(19200000, P_BI_TCXO, 1, 0, 0), 1571 { } 1572 }; 1573 1574 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1575 .cmd_rcgr = 0x1a034, 1576 .mnd_width = 0, 1577 .hid_width = 5, 1578 .parent_map = gcc_parent_map_0, 1579 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1580 .clkr.hw.init = &(struct clk_init_data){ 1581 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1582 .parent_data = gcc_parent_data_0, 1583 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1584 .ops = &clk_rcg2_shared_ops, 1585 }, 1586 }; 1587 1588 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1589 .cmd_rcgr = 0x1a060, 1590 .mnd_width = 0, 1591 .hid_width = 5, 1592 .parent_map = gcc_parent_map_13, 1593 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1594 .clkr.hw.init = &(struct clk_init_data){ 1595 .name = "gcc_usb3_prim_phy_aux_clk_src", 1596 .parent_data = gcc_parent_data_13, 1597 .num_parents = ARRAY_SIZE(gcc_parent_data_13), 1598 .ops = &clk_rcg2_shared_ops, 1599 }, 1600 }; 1601 1602 static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = { 1603 F(133000000, P_GPLL11_OUT_EVEN, 4, 0, 0), 1604 F(240000000, P_GPLL11_OUT_EVEN, 2.5, 0, 0), 1605 F(300000000, P_GPLL11_OUT_EVEN, 2, 0, 0), 1606 F(384000000, P_GPLL11_OUT_EVEN, 2, 0, 0), 1607 { } 1608 }; 1609 1610 static struct clk_rcg2 gcc_video_venus_clk_src = { 1611 .cmd_rcgr = 0x58060, 1612 .mnd_width = 0, 1613 .hid_width = 5, 1614 .parent_map = gcc_parent_map_14, 1615 .freq_tbl = ftbl_gcc_video_venus_clk_src, 1616 .clkr.hw.init = &(struct clk_init_data){ 1617 .name = "gcc_video_venus_clk_src", 1618 .parent_data = gcc_parent_data_14, 1619 .num_parents = ARRAY_SIZE(gcc_parent_data_14), 1620 .flags = CLK_SET_RATE_PARENT, 1621 .ops = &clk_rcg2_shared_ops, 1622 }, 1623 }; 1624 1625 static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = { 1626 .reg = 0x2b154, 1627 .shift = 0, 1628 .width = 4, 1629 .clkr.hw.init = &(struct clk_init_data) { 1630 .name = "gcc_cpuss_ahb_postdiv_clk_src", 1631 .parent_hws = (const struct clk_hw*[]){ 1632 &gcc_cpuss_ahb_clk_src.clkr.hw, 1633 }, 1634 .num_parents = 1, 1635 .flags = CLK_SET_RATE_PARENT, 1636 .ops = &clk_regmap_div_ro_ops, 1637 }, 1638 }; 1639 1640 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1641 .reg = 0x1a04c, 1642 .shift = 0, 1643 .width = 4, 1644 .clkr.hw.init = &(struct clk_init_data) { 1645 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1646 .parent_hws = (const struct clk_hw*[]){ 1647 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1648 }, 1649 .num_parents = 1, 1650 .flags = CLK_SET_RATE_PARENT, 1651 .ops = &clk_regmap_div_ro_ops, 1652 }, 1653 }; 1654 1655 static struct clk_branch gcc_ahb2phy_csi_clk = { 1656 .halt_reg = 0x1d004, 1657 .halt_check = BRANCH_HALT_VOTED, 1658 .hwcg_reg = 0x1d004, 1659 .hwcg_bit = 1, 1660 .clkr = { 1661 .enable_reg = 0x1d004, 1662 .enable_mask = BIT(0), 1663 .hw.init = &(struct clk_init_data){ 1664 .name = "gcc_ahb2phy_csi_clk", 1665 .ops = &clk_branch2_ops, 1666 }, 1667 }, 1668 }; 1669 1670 static struct clk_branch gcc_ahb2phy_usb_clk = { 1671 .halt_reg = 0x1d008, 1672 .halt_check = BRANCH_HALT_VOTED, 1673 .hwcg_reg = 0x1d008, 1674 .hwcg_bit = 1, 1675 .clkr = { 1676 .enable_reg = 0x1d008, 1677 .enable_mask = BIT(0), 1678 .hw.init = &(struct clk_init_data){ 1679 .name = "gcc_ahb2phy_usb_clk", 1680 .ops = &clk_branch2_ops, 1681 }, 1682 }, 1683 }; 1684 1685 static struct clk_branch gcc_bimc_gpu_axi_clk = { 1686 .halt_reg = 0x71154, 1687 .halt_check = BRANCH_HALT_VOTED, 1688 .hwcg_reg = 0x71154, 1689 .hwcg_bit = 1, 1690 .clkr = { 1691 .enable_reg = 0x71154, 1692 .enable_mask = BIT(0), 1693 .hw.init = &(struct clk_init_data){ 1694 .name = "gcc_bimc_gpu_axi_clk", 1695 .ops = &clk_branch2_ops, 1696 }, 1697 }, 1698 }; 1699 1700 static struct clk_branch gcc_boot_rom_ahb_clk = { 1701 .halt_reg = 0x23004, 1702 .halt_check = BRANCH_HALT_VOTED, 1703 .hwcg_reg = 0x23004, 1704 .hwcg_bit = 1, 1705 .clkr = { 1706 .enable_reg = 0x79004, 1707 .enable_mask = BIT(10), 1708 .hw.init = &(struct clk_init_data){ 1709 .name = "gcc_boot_rom_ahb_clk", 1710 .ops = &clk_branch2_ops, 1711 }, 1712 }, 1713 }; 1714 1715 static struct clk_branch gcc_cam_throttle_nrt_clk = { 1716 .halt_reg = 0x17070, 1717 .halt_check = BRANCH_HALT_VOTED, 1718 .hwcg_reg = 0x17070, 1719 .hwcg_bit = 1, 1720 .clkr = { 1721 .enable_reg = 0x79004, 1722 .enable_mask = BIT(27), 1723 .hw.init = &(struct clk_init_data){ 1724 .name = "gcc_cam_throttle_nrt_clk", 1725 .ops = &clk_branch2_ops, 1726 }, 1727 }, 1728 }; 1729 1730 static struct clk_branch gcc_cam_throttle_rt_clk = { 1731 .halt_reg = 0x1706c, 1732 .halt_check = BRANCH_HALT_VOTED, 1733 .hwcg_reg = 0x1706c, 1734 .hwcg_bit = 1, 1735 .clkr = { 1736 .enable_reg = 0x79004, 1737 .enable_mask = BIT(26), 1738 .hw.init = &(struct clk_init_data){ 1739 .name = "gcc_cam_throttle_rt_clk", 1740 .ops = &clk_branch2_ops, 1741 }, 1742 }, 1743 }; 1744 1745 static struct clk_branch gcc_camera_ahb_clk = { 1746 .halt_reg = 0x17008, 1747 .halt_check = BRANCH_HALT_DELAY, 1748 .hwcg_reg = 0x17008, 1749 .hwcg_bit = 1, 1750 .clkr = { 1751 .enable_reg = 0x17008, 1752 .enable_mask = BIT(0), 1753 .hw.init = &(struct clk_init_data){ 1754 .name = "gcc_camera_ahb_clk", 1755 .flags = CLK_IS_CRITICAL, 1756 .ops = &clk_branch2_ops, 1757 }, 1758 }, 1759 }; 1760 1761 static struct clk_branch gcc_camss_axi_clk = { 1762 .halt_reg = 0x58044, 1763 .halt_check = BRANCH_HALT, 1764 .clkr = { 1765 .enable_reg = 0x58044, 1766 .enable_mask = BIT(0), 1767 .hw.init = &(struct clk_init_data){ 1768 .name = "gcc_camss_axi_clk", 1769 .parent_hws = (const struct clk_hw*[]) { 1770 &gcc_camss_axi_clk_src.clkr.hw, 1771 }, 1772 .num_parents = 1, 1773 .flags = CLK_SET_RATE_PARENT, 1774 .ops = &clk_branch2_ops, 1775 }, 1776 }, 1777 }; 1778 1779 static struct clk_branch gcc_camss_cci_0_clk = { 1780 .halt_reg = 0x56018, 1781 .halt_check = BRANCH_HALT, 1782 .clkr = { 1783 .enable_reg = 0x56018, 1784 .enable_mask = BIT(0), 1785 .hw.init = &(struct clk_init_data){ 1786 .name = "gcc_camss_cci_0_clk", 1787 .parent_hws = (const struct clk_hw*[]) { 1788 &gcc_camss_cci_0_clk_src.clkr.hw, 1789 }, 1790 .num_parents = 1, 1791 .flags = CLK_SET_RATE_PARENT, 1792 .ops = &clk_branch2_ops, 1793 }, 1794 }, 1795 }; 1796 1797 static struct clk_branch gcc_camss_cci_1_clk = { 1798 .halt_reg = 0x5c018, 1799 .halt_check = BRANCH_HALT, 1800 .clkr = { 1801 .enable_reg = 0x5c018, 1802 .enable_mask = BIT(0), 1803 .hw.init = &(struct clk_init_data){ 1804 .name = "gcc_camss_cci_1_clk", 1805 .parent_hws = (const struct clk_hw*[]) { 1806 &gcc_camss_cci_1_clk_src.clkr.hw, 1807 }, 1808 .num_parents = 1, 1809 .flags = CLK_SET_RATE_PARENT, 1810 .ops = &clk_branch2_ops, 1811 }, 1812 }, 1813 }; 1814 1815 static struct clk_branch gcc_camss_cphy_0_clk = { 1816 .halt_reg = 0x52088, 1817 .halt_check = BRANCH_HALT, 1818 .clkr = { 1819 .enable_reg = 0x52088, 1820 .enable_mask = BIT(0), 1821 .hw.init = &(struct clk_init_data){ 1822 .name = "gcc_camss_cphy_0_clk", 1823 .parent_hws = (const struct clk_hw*[]) { 1824 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1825 }, 1826 .num_parents = 1, 1827 .flags = CLK_SET_RATE_PARENT, 1828 .ops = &clk_branch2_ops, 1829 }, 1830 }, 1831 }; 1832 1833 static struct clk_branch gcc_camss_cphy_1_clk = { 1834 .halt_reg = 0x5208c, 1835 .halt_check = BRANCH_HALT, 1836 .clkr = { 1837 .enable_reg = 0x5208c, 1838 .enable_mask = BIT(0), 1839 .hw.init = &(struct clk_init_data){ 1840 .name = "gcc_camss_cphy_1_clk", 1841 .parent_hws = (const struct clk_hw*[]) { 1842 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1843 }, 1844 .num_parents = 1, 1845 .flags = CLK_SET_RATE_PARENT, 1846 .ops = &clk_branch2_ops, 1847 }, 1848 }, 1849 }; 1850 1851 static struct clk_branch gcc_camss_cphy_2_clk = { 1852 .halt_reg = 0x52090, 1853 .halt_check = BRANCH_HALT, 1854 .clkr = { 1855 .enable_reg = 0x52090, 1856 .enable_mask = BIT(0), 1857 .hw.init = &(struct clk_init_data){ 1858 .name = "gcc_camss_cphy_2_clk", 1859 .parent_hws = (const struct clk_hw*[]) { 1860 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1861 }, 1862 .num_parents = 1, 1863 .flags = CLK_SET_RATE_PARENT, 1864 .ops = &clk_branch2_ops, 1865 }, 1866 }, 1867 }; 1868 1869 static struct clk_branch gcc_camss_cphy_3_clk = { 1870 .halt_reg = 0x520f8, 1871 .halt_check = BRANCH_HALT, 1872 .clkr = { 1873 .enable_reg = 0x520f8, 1874 .enable_mask = BIT(0), 1875 .hw.init = &(struct clk_init_data){ 1876 .name = "gcc_camss_cphy_3_clk", 1877 .parent_hws = (const struct clk_hw*[]) { 1878 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 1879 }, 1880 .num_parents = 1, 1881 .flags = CLK_SET_RATE_PARENT, 1882 .ops = &clk_branch2_ops, 1883 }, 1884 }, 1885 }; 1886 1887 static struct clk_branch gcc_camss_csi0phytimer_clk = { 1888 .halt_reg = 0x59018, 1889 .halt_check = BRANCH_HALT, 1890 .clkr = { 1891 .enable_reg = 0x59018, 1892 .enable_mask = BIT(0), 1893 .hw.init = &(struct clk_init_data){ 1894 .name = "gcc_camss_csi0phytimer_clk", 1895 .parent_hws = (const struct clk_hw*[]) { 1896 &gcc_camss_csi0phytimer_clk_src.clkr.hw, 1897 }, 1898 .num_parents = 1, 1899 .flags = CLK_SET_RATE_PARENT, 1900 .ops = &clk_branch2_ops, 1901 }, 1902 }, 1903 }; 1904 1905 static struct clk_branch gcc_camss_csi1phytimer_clk = { 1906 .halt_reg = 0x59034, 1907 .halt_check = BRANCH_HALT, 1908 .clkr = { 1909 .enable_reg = 0x59034, 1910 .enable_mask = BIT(0), 1911 .hw.init = &(struct clk_init_data){ 1912 .name = "gcc_camss_csi1phytimer_clk", 1913 .parent_hws = (const struct clk_hw*[]) { 1914 &gcc_camss_csi1phytimer_clk_src.clkr.hw, 1915 }, 1916 .num_parents = 1, 1917 .flags = CLK_SET_RATE_PARENT, 1918 .ops = &clk_branch2_ops, 1919 }, 1920 }, 1921 }; 1922 1923 static struct clk_branch gcc_camss_csi2phytimer_clk = { 1924 .halt_reg = 0x59050, 1925 .halt_check = BRANCH_HALT, 1926 .clkr = { 1927 .enable_reg = 0x59050, 1928 .enable_mask = BIT(0), 1929 .hw.init = &(struct clk_init_data){ 1930 .name = "gcc_camss_csi2phytimer_clk", 1931 .parent_hws = (const struct clk_hw*[]) { 1932 &gcc_camss_csi2phytimer_clk_src.clkr.hw, 1933 }, 1934 .num_parents = 1, 1935 .flags = CLK_SET_RATE_PARENT, 1936 .ops = &clk_branch2_ops, 1937 }, 1938 }, 1939 }; 1940 1941 static struct clk_branch gcc_camss_csi3phytimer_clk = { 1942 .halt_reg = 0x5906c, 1943 .halt_check = BRANCH_HALT, 1944 .clkr = { 1945 .enable_reg = 0x5906c, 1946 .enable_mask = BIT(0), 1947 .hw.init = &(struct clk_init_data){ 1948 .name = "gcc_camss_csi3phytimer_clk", 1949 .parent_hws = (const struct clk_hw*[]) { 1950 &gcc_camss_csi3phytimer_clk_src.clkr.hw, 1951 }, 1952 .num_parents = 1, 1953 .flags = CLK_SET_RATE_PARENT, 1954 .ops = &clk_branch2_ops, 1955 }, 1956 }, 1957 }; 1958 1959 static struct clk_branch gcc_camss_mclk0_clk = { 1960 .halt_reg = 0x51018, 1961 .halt_check = BRANCH_HALT, 1962 .clkr = { 1963 .enable_reg = 0x51018, 1964 .enable_mask = BIT(0), 1965 .hw.init = &(struct clk_init_data){ 1966 .name = "gcc_camss_mclk0_clk", 1967 .parent_hws = (const struct clk_hw*[]) { 1968 &gcc_camss_mclk0_clk_src.clkr.hw, 1969 }, 1970 .num_parents = 1, 1971 .flags = CLK_SET_RATE_PARENT, 1972 .ops = &clk_branch2_ops, 1973 }, 1974 }, 1975 }; 1976 1977 static struct clk_branch gcc_camss_mclk1_clk = { 1978 .halt_reg = 0x51034, 1979 .halt_check = BRANCH_HALT, 1980 .clkr = { 1981 .enable_reg = 0x51034, 1982 .enable_mask = BIT(0), 1983 .hw.init = &(struct clk_init_data){ 1984 .name = "gcc_camss_mclk1_clk", 1985 .parent_hws = (const struct clk_hw*[]) { 1986 &gcc_camss_mclk1_clk_src.clkr.hw, 1987 }, 1988 .num_parents = 1, 1989 .flags = CLK_SET_RATE_PARENT, 1990 .ops = &clk_branch2_ops, 1991 }, 1992 }, 1993 }; 1994 1995 static struct clk_branch gcc_camss_mclk2_clk = { 1996 .halt_reg = 0x51050, 1997 .halt_check = BRANCH_HALT, 1998 .clkr = { 1999 .enable_reg = 0x51050, 2000 .enable_mask = BIT(0), 2001 .hw.init = &(struct clk_init_data){ 2002 .name = "gcc_camss_mclk2_clk", 2003 .parent_hws = (const struct clk_hw*[]) { 2004 &gcc_camss_mclk2_clk_src.clkr.hw, 2005 }, 2006 .num_parents = 1, 2007 .flags = CLK_SET_RATE_PARENT, 2008 .ops = &clk_branch2_ops, 2009 }, 2010 }, 2011 }; 2012 2013 static struct clk_branch gcc_camss_mclk3_clk = { 2014 .halt_reg = 0x5106c, 2015 .halt_check = BRANCH_HALT, 2016 .clkr = { 2017 .enable_reg = 0x5106c, 2018 .enable_mask = BIT(0), 2019 .hw.init = &(struct clk_init_data){ 2020 .name = "gcc_camss_mclk3_clk", 2021 .parent_hws = (const struct clk_hw*[]) { 2022 &gcc_camss_mclk3_clk_src.clkr.hw, 2023 }, 2024 .num_parents = 1, 2025 .flags = CLK_SET_RATE_PARENT, 2026 .ops = &clk_branch2_ops, 2027 }, 2028 }, 2029 }; 2030 2031 static struct clk_branch gcc_camss_mclk4_clk = { 2032 .halt_reg = 0x51088, 2033 .halt_check = BRANCH_HALT, 2034 .clkr = { 2035 .enable_reg = 0x51088, 2036 .enable_mask = BIT(0), 2037 .hw.init = &(struct clk_init_data){ 2038 .name = "gcc_camss_mclk4_clk", 2039 .parent_hws = (const struct clk_hw*[]) { 2040 &gcc_camss_mclk4_clk_src.clkr.hw, 2041 }, 2042 .num_parents = 1, 2043 .flags = CLK_SET_RATE_PARENT, 2044 .ops = &clk_branch2_ops, 2045 }, 2046 }, 2047 }; 2048 2049 static struct clk_branch gcc_camss_nrt_axi_clk = { 2050 .halt_reg = 0x58054, 2051 .halt_check = BRANCH_HALT, 2052 .clkr = { 2053 .enable_reg = 0x58054, 2054 .enable_mask = BIT(0), 2055 .hw.init = &(struct clk_init_data){ 2056 .name = "gcc_camss_nrt_axi_clk", 2057 .ops = &clk_branch2_ops, 2058 }, 2059 }, 2060 }; 2061 2062 static struct clk_branch gcc_camss_ope_ahb_clk = { 2063 .halt_reg = 0x5503c, 2064 .halt_check = BRANCH_HALT, 2065 .clkr = { 2066 .enable_reg = 0x5503c, 2067 .enable_mask = BIT(0), 2068 .hw.init = &(struct clk_init_data){ 2069 .name = "gcc_camss_ope_ahb_clk", 2070 .parent_hws = (const struct clk_hw*[]) { 2071 &gcc_camss_ope_ahb_clk_src.clkr.hw, 2072 }, 2073 .num_parents = 1, 2074 .flags = CLK_SET_RATE_PARENT, 2075 .ops = &clk_branch2_ops, 2076 }, 2077 }, 2078 }; 2079 2080 static struct clk_branch gcc_camss_ope_clk = { 2081 .halt_reg = 0x5501c, 2082 .halt_check = BRANCH_HALT, 2083 .clkr = { 2084 .enable_reg = 0x5501c, 2085 .enable_mask = BIT(0), 2086 .hw.init = &(struct clk_init_data){ 2087 .name = "gcc_camss_ope_clk", 2088 .parent_hws = (const struct clk_hw*[]) { 2089 &gcc_camss_ope_clk_src.clkr.hw, 2090 }, 2091 .num_parents = 1, 2092 .flags = CLK_SET_RATE_PARENT, 2093 .ops = &clk_branch2_ops, 2094 }, 2095 }, 2096 }; 2097 2098 static struct clk_branch gcc_camss_rt_axi_clk = { 2099 .halt_reg = 0x5805c, 2100 .halt_check = BRANCH_HALT, 2101 .clkr = { 2102 .enable_reg = 0x5805c, 2103 .enable_mask = BIT(0), 2104 .hw.init = &(struct clk_init_data){ 2105 .name = "gcc_camss_rt_axi_clk", 2106 .ops = &clk_branch2_ops, 2107 }, 2108 }, 2109 }; 2110 2111 static struct clk_branch gcc_camss_tfe_0_clk = { 2112 .halt_reg = 0x5201c, 2113 .halt_check = BRANCH_HALT, 2114 .clkr = { 2115 .enable_reg = 0x5201c, 2116 .enable_mask = BIT(0), 2117 .hw.init = &(struct clk_init_data){ 2118 .name = "gcc_camss_tfe_0_clk", 2119 .parent_hws = (const struct clk_hw*[]) { 2120 &gcc_camss_tfe_0_clk_src.clkr.hw, 2121 }, 2122 .num_parents = 1, 2123 .flags = CLK_SET_RATE_PARENT, 2124 .ops = &clk_branch2_ops, 2125 }, 2126 }, 2127 }; 2128 2129 static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = { 2130 .halt_reg = 0x5207c, 2131 .halt_check = BRANCH_HALT, 2132 .clkr = { 2133 .enable_reg = 0x5207c, 2134 .enable_mask = BIT(0), 2135 .hw.init = &(struct clk_init_data){ 2136 .name = "gcc_camss_tfe_0_cphy_rx_clk", 2137 .parent_hws = (const struct clk_hw*[]) { 2138 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 2139 }, 2140 .num_parents = 1, 2141 .flags = CLK_SET_RATE_PARENT, 2142 .ops = &clk_branch2_ops, 2143 }, 2144 }, 2145 }; 2146 2147 static struct clk_branch gcc_camss_tfe_0_csid_clk = { 2148 .halt_reg = 0x520ac, 2149 .halt_check = BRANCH_HALT, 2150 .clkr = { 2151 .enable_reg = 0x520ac, 2152 .enable_mask = BIT(0), 2153 .hw.init = &(struct clk_init_data){ 2154 .name = "gcc_camss_tfe_0_csid_clk", 2155 .parent_hws = (const struct clk_hw*[]) { 2156 &gcc_camss_tfe_0_csid_clk_src.clkr.hw, 2157 }, 2158 .num_parents = 1, 2159 .flags = CLK_SET_RATE_PARENT, 2160 .ops = &clk_branch2_ops, 2161 }, 2162 }, 2163 }; 2164 2165 static struct clk_branch gcc_camss_tfe_1_clk = { 2166 .halt_reg = 0x5203c, 2167 .halt_check = BRANCH_HALT, 2168 .clkr = { 2169 .enable_reg = 0x5203c, 2170 .enable_mask = BIT(0), 2171 .hw.init = &(struct clk_init_data){ 2172 .name = "gcc_camss_tfe_1_clk", 2173 .parent_hws = (const struct clk_hw*[]) { 2174 &gcc_camss_tfe_1_clk_src.clkr.hw, 2175 }, 2176 .num_parents = 1, 2177 .flags = CLK_SET_RATE_PARENT, 2178 .ops = &clk_branch2_ops, 2179 }, 2180 }, 2181 }; 2182 2183 static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = { 2184 .halt_reg = 0x52080, 2185 .halt_check = BRANCH_HALT, 2186 .clkr = { 2187 .enable_reg = 0x52080, 2188 .enable_mask = BIT(0), 2189 .hw.init = &(struct clk_init_data){ 2190 .name = "gcc_camss_tfe_1_cphy_rx_clk", 2191 .parent_hws = (const struct clk_hw*[]) { 2192 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 2193 }, 2194 .num_parents = 1, 2195 .flags = CLK_SET_RATE_PARENT, 2196 .ops = &clk_branch2_ops, 2197 }, 2198 }, 2199 }; 2200 2201 static struct clk_branch gcc_camss_tfe_1_csid_clk = { 2202 .halt_reg = 0x520cc, 2203 .halt_check = BRANCH_HALT, 2204 .clkr = { 2205 .enable_reg = 0x520cc, 2206 .enable_mask = BIT(0), 2207 .hw.init = &(struct clk_init_data){ 2208 .name = "gcc_camss_tfe_1_csid_clk", 2209 .parent_hws = (const struct clk_hw*[]) { 2210 &gcc_camss_tfe_1_csid_clk_src.clkr.hw, 2211 }, 2212 .num_parents = 1, 2213 .flags = CLK_SET_RATE_PARENT, 2214 .ops = &clk_branch2_ops, 2215 }, 2216 }, 2217 }; 2218 2219 static struct clk_branch gcc_camss_tfe_2_clk = { 2220 .halt_reg = 0x5205c, 2221 .halt_check = BRANCH_HALT, 2222 .clkr = { 2223 .enable_reg = 0x5205c, 2224 .enable_mask = BIT(0), 2225 .hw.init = &(struct clk_init_data){ 2226 .name = "gcc_camss_tfe_2_clk", 2227 .parent_hws = (const struct clk_hw*[]) { 2228 &gcc_camss_tfe_2_clk_src.clkr.hw, 2229 }, 2230 .num_parents = 1, 2231 .flags = CLK_SET_RATE_PARENT, 2232 .ops = &clk_branch2_ops, 2233 }, 2234 }, 2235 }; 2236 2237 static struct clk_branch gcc_camss_tfe_2_cphy_rx_clk = { 2238 .halt_reg = 0x52084, 2239 .halt_check = BRANCH_HALT, 2240 .clkr = { 2241 .enable_reg = 0x52084, 2242 .enable_mask = BIT(0), 2243 .hw.init = &(struct clk_init_data){ 2244 .name = "gcc_camss_tfe_2_cphy_rx_clk", 2245 .parent_hws = (const struct clk_hw*[]) { 2246 &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, 2247 }, 2248 .num_parents = 1, 2249 .flags = CLK_SET_RATE_PARENT, 2250 .ops = &clk_branch2_ops, 2251 }, 2252 }, 2253 }; 2254 2255 static struct clk_branch gcc_camss_tfe_2_csid_clk = { 2256 .halt_reg = 0x520ec, 2257 .halt_check = BRANCH_HALT, 2258 .clkr = { 2259 .enable_reg = 0x520ec, 2260 .enable_mask = BIT(0), 2261 .hw.init = &(struct clk_init_data){ 2262 .name = "gcc_camss_tfe_2_csid_clk", 2263 .parent_hws = (const struct clk_hw*[]) { 2264 &gcc_camss_tfe_2_csid_clk_src.clkr.hw, 2265 }, 2266 .num_parents = 1, 2267 .flags = CLK_SET_RATE_PARENT, 2268 .ops = &clk_branch2_ops, 2269 }, 2270 }, 2271 }; 2272 2273 static struct clk_branch gcc_camss_top_ahb_clk = { 2274 .halt_reg = 0x58028, 2275 .halt_check = BRANCH_HALT, 2276 .clkr = { 2277 .enable_reg = 0x58028, 2278 .enable_mask = BIT(0), 2279 .hw.init = &(struct clk_init_data){ 2280 .name = "gcc_camss_top_ahb_clk", 2281 .parent_hws = (const struct clk_hw*[]) { 2282 &gcc_camss_top_ahb_clk_src.clkr.hw, 2283 }, 2284 .num_parents = 1, 2285 .flags = CLK_SET_RATE_PARENT, 2286 .ops = &clk_branch2_ops, 2287 }, 2288 }, 2289 }; 2290 2291 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 2292 .halt_reg = 0x1a084, 2293 .halt_check = BRANCH_HALT_VOTED, 2294 .hwcg_reg = 0x1a084, 2295 .hwcg_bit = 1, 2296 .clkr = { 2297 .enable_reg = 0x1a084, 2298 .enable_mask = BIT(0), 2299 .hw.init = &(struct clk_init_data){ 2300 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 2301 .parent_hws = (const struct clk_hw*[]) { 2302 &gcc_usb30_prim_master_clk_src.clkr.hw, 2303 }, 2304 .num_parents = 1, 2305 .flags = CLK_SET_RATE_PARENT, 2306 .ops = &clk_branch2_ops, 2307 }, 2308 }, 2309 }; 2310 2311 static struct clk_branch gcc_disp_ahb_clk = { 2312 .halt_reg = 0x1700c, 2313 .halt_check = BRANCH_HALT_VOTED, 2314 .hwcg_reg = 0x1700c, 2315 .hwcg_bit = 1, 2316 .clkr = { 2317 .enable_reg = 0x1700c, 2318 .enable_mask = BIT(0), 2319 .hw.init = &(struct clk_init_data){ 2320 .name = "gcc_disp_ahb_clk", 2321 .flags = CLK_IS_CRITICAL, 2322 .ops = &clk_branch2_ops, 2323 }, 2324 }, 2325 }; 2326 2327 static struct clk_regmap_div gcc_disp_gpll0_clk_src = { 2328 .reg = 0x17058, 2329 .shift = 0, 2330 .width = 2, 2331 .clkr.hw.init = &(struct clk_init_data) { 2332 .name = "gcc_disp_gpll0_clk_src", 2333 .parent_hws = (const struct clk_hw*[]){ 2334 &gpll0.clkr.hw, 2335 }, 2336 .num_parents = 1, 2337 .ops = &clk_regmap_div_ops, 2338 }, 2339 }; 2340 2341 static struct clk_branch gcc_disp_gpll0_div_clk_src = { 2342 .halt_check = BRANCH_HALT_DELAY, 2343 .clkr = { 2344 .enable_reg = 0x79004, 2345 .enable_mask = BIT(20), 2346 .hw.init = &(struct clk_init_data){ 2347 .name = "gcc_disp_gpll0_div_clk_src", 2348 .parent_hws = (const struct clk_hw*[]) { 2349 &gcc_disp_gpll0_clk_src.clkr.hw, 2350 }, 2351 .num_parents = 1, 2352 .flags = CLK_SET_RATE_PARENT, 2353 .ops = &clk_branch2_ops, 2354 }, 2355 }, 2356 }; 2357 2358 static struct clk_branch gcc_disp_hf_axi_clk = { 2359 .halt_reg = 0x17020, 2360 .halt_check = BRANCH_VOTED, 2361 .hwcg_reg = 0x17020, 2362 .hwcg_bit = 1, 2363 .clkr = { 2364 .enable_reg = 0x17020, 2365 .enable_mask = BIT(0), 2366 .hw.init = &(struct clk_init_data){ 2367 .name = "gcc_disp_hf_axi_clk", 2368 .ops = &clk_branch2_ops, 2369 }, 2370 }, 2371 }; 2372 2373 static struct clk_branch gcc_disp_sleep_clk = { 2374 .halt_reg = 0x17074, 2375 .halt_check = BRANCH_HALT_VOTED, 2376 .hwcg_reg = 0x17074, 2377 .hwcg_bit = 1, 2378 .clkr = { 2379 .enable_reg = 0x17074, 2380 .enable_mask = BIT(0), 2381 .hw.init = &(struct clk_init_data){ 2382 .name = "gcc_disp_sleep_clk", 2383 .ops = &clk_branch2_ops, 2384 }, 2385 }, 2386 }; 2387 2388 static struct clk_branch gcc_disp_throttle_core_clk = { 2389 .halt_reg = 0x17064, 2390 .halt_check = BRANCH_HALT_VOTED, 2391 .hwcg_reg = 0x17064, 2392 .hwcg_bit = 1, 2393 .clkr = { 2394 .enable_reg = 0x7900c, 2395 .enable_mask = BIT(5), 2396 .hw.init = &(struct clk_init_data){ 2397 .name = "gcc_disp_throttle_core_clk", 2398 .ops = &clk_branch2_ops, 2399 }, 2400 }, 2401 }; 2402 2403 static struct clk_branch gcc_gp1_clk = { 2404 .halt_reg = 0x4d000, 2405 .halt_check = BRANCH_HALT, 2406 .clkr = { 2407 .enable_reg = 0x4d000, 2408 .enable_mask = BIT(0), 2409 .hw.init = &(struct clk_init_data){ 2410 .name = "gcc_gp1_clk", 2411 .parent_hws = (const struct clk_hw*[]) { 2412 &gcc_gp1_clk_src.clkr.hw, 2413 }, 2414 .num_parents = 1, 2415 .flags = CLK_SET_RATE_PARENT, 2416 .ops = &clk_branch2_ops, 2417 }, 2418 }, 2419 }; 2420 2421 static struct clk_branch gcc_gp2_clk = { 2422 .halt_reg = 0x4e000, 2423 .halt_check = BRANCH_HALT, 2424 .clkr = { 2425 .enable_reg = 0x4e000, 2426 .enable_mask = BIT(0), 2427 .hw.init = &(struct clk_init_data){ 2428 .name = "gcc_gp2_clk", 2429 .parent_hws = (const struct clk_hw*[]) { 2430 &gcc_gp2_clk_src.clkr.hw, 2431 }, 2432 .num_parents = 1, 2433 .flags = CLK_SET_RATE_PARENT, 2434 .ops = &clk_branch2_ops, 2435 }, 2436 }, 2437 }; 2438 2439 static struct clk_branch gcc_gp3_clk = { 2440 .halt_reg = 0x4f000, 2441 .halt_check = BRANCH_HALT, 2442 .clkr = { 2443 .enable_reg = 0x4f000, 2444 .enable_mask = BIT(0), 2445 .hw.init = &(struct clk_init_data){ 2446 .name = "gcc_gp3_clk", 2447 .parent_hws = (const struct clk_hw*[]) { 2448 &gcc_gp3_clk_src.clkr.hw, 2449 }, 2450 .num_parents = 1, 2451 .flags = CLK_SET_RATE_PARENT, 2452 .ops = &clk_branch2_ops, 2453 }, 2454 }, 2455 }; 2456 2457 static struct clk_branch gcc_gpu_cfg_ahb_clk = { 2458 .halt_reg = 0x36004, 2459 .halt_check = BRANCH_HALT_VOTED, 2460 .hwcg_reg = 0x36004, 2461 .hwcg_bit = 1, 2462 .clkr = { 2463 .enable_reg = 0x36004, 2464 .enable_mask = BIT(0), 2465 .hw.init = &(struct clk_init_data){ 2466 .name = "gcc_gpu_cfg_ahb_clk", 2467 .flags = CLK_IS_CRITICAL, 2468 .ops = &clk_branch2_ops, 2469 }, 2470 }, 2471 }; 2472 2473 static struct clk_branch gcc_gpu_gpll0_clk_src = { 2474 .halt_check = BRANCH_HALT_DELAY, 2475 .clkr = { 2476 .enable_reg = 0x79004, 2477 .enable_mask = BIT(15), 2478 .hw.init = &(struct clk_init_data){ 2479 .name = "gcc_gpu_gpll0_clk_src", 2480 .parent_hws = (const struct clk_hw*[]) { 2481 &gpll0.clkr.hw, 2482 }, 2483 .num_parents = 1, 2484 .flags = CLK_SET_RATE_PARENT, 2485 .ops = &clk_branch2_ops, 2486 }, 2487 }, 2488 }; 2489 2490 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 2491 .halt_check = BRANCH_HALT_DELAY, 2492 .clkr = { 2493 .enable_reg = 0x79004, 2494 .enable_mask = BIT(16), 2495 .hw.init = &(struct clk_init_data){ 2496 .name = "gcc_gpu_gpll0_div_clk_src", 2497 .parent_hws = (const struct clk_hw*[]) { 2498 &gpll0_out_even.clkr.hw, 2499 }, 2500 .num_parents = 1, 2501 .flags = CLK_SET_RATE_PARENT, 2502 .ops = &clk_branch2_ops, 2503 }, 2504 }, 2505 }; 2506 2507 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 2508 .halt_reg = 0x3600c, 2509 .halt_check = BRANCH_VOTED, 2510 .hwcg_reg = 0x3600c, 2511 .hwcg_bit = 1, 2512 .clkr = { 2513 .enable_reg = 0x3600c, 2514 .enable_mask = BIT(0), 2515 .hw.init = &(struct clk_init_data){ 2516 .name = "gcc_gpu_memnoc_gfx_clk", 2517 .ops = &clk_branch2_ops, 2518 }, 2519 }, 2520 }; 2521 2522 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 2523 .halt_reg = 0x36018, 2524 .halt_check = BRANCH_HALT, 2525 .clkr = { 2526 .enable_reg = 0x36018, 2527 .enable_mask = BIT(0), 2528 .hw.init = &(struct clk_init_data){ 2529 .name = "gcc_gpu_snoc_dvm_gfx_clk", 2530 .ops = &clk_branch2_ops, 2531 }, 2532 }, 2533 }; 2534 2535 static struct clk_branch gcc_gpu_throttle_core_clk = { 2536 .halt_reg = 0x36048, 2537 .halt_check = BRANCH_HALT_VOTED, 2538 .hwcg_reg = 0x36048, 2539 .hwcg_bit = 1, 2540 .clkr = { 2541 .enable_reg = 0x79004, 2542 .enable_mask = BIT(31), 2543 .hw.init = &(struct clk_init_data){ 2544 .name = "gcc_gpu_throttle_core_clk", 2545 .ops = &clk_branch2_ops, 2546 }, 2547 }, 2548 }; 2549 2550 static struct clk_branch gcc_pdm2_clk = { 2551 .halt_reg = 0x2000c, 2552 .halt_check = BRANCH_HALT, 2553 .clkr = { 2554 .enable_reg = 0x2000c, 2555 .enable_mask = BIT(0), 2556 .hw.init = &(struct clk_init_data){ 2557 .name = "gcc_pdm2_clk", 2558 .parent_hws = (const struct clk_hw*[]) { 2559 &gcc_pdm2_clk_src.clkr.hw, 2560 }, 2561 .num_parents = 1, 2562 .flags = CLK_SET_RATE_PARENT, 2563 .ops = &clk_branch2_ops, 2564 }, 2565 }, 2566 }; 2567 2568 static struct clk_branch gcc_pdm_ahb_clk = { 2569 .halt_reg = 0x20004, 2570 .halt_check = BRANCH_HALT_VOTED, 2571 .hwcg_reg = 0x20004, 2572 .hwcg_bit = 1, 2573 .clkr = { 2574 .enable_reg = 0x20004, 2575 .enable_mask = BIT(0), 2576 .hw.init = &(struct clk_init_data){ 2577 .name = "gcc_pdm_ahb_clk", 2578 .ops = &clk_branch2_ops, 2579 }, 2580 }, 2581 }; 2582 2583 static struct clk_branch gcc_pdm_xo4_clk = { 2584 .halt_reg = 0x20008, 2585 .halt_check = BRANCH_HALT, 2586 .clkr = { 2587 .enable_reg = 0x20008, 2588 .enable_mask = BIT(0), 2589 .hw.init = &(struct clk_init_data){ 2590 .name = "gcc_pdm_xo4_clk", 2591 .ops = &clk_branch2_ops, 2592 }, 2593 }, 2594 }; 2595 2596 static struct clk_branch gcc_prng_ahb_clk = { 2597 .halt_reg = 0x21004, 2598 .halt_check = BRANCH_HALT_VOTED, 2599 .hwcg_reg = 0x21004, 2600 .hwcg_bit = 1, 2601 .clkr = { 2602 .enable_reg = 0x79004, 2603 .enable_mask = BIT(13), 2604 .hw.init = &(struct clk_init_data){ 2605 .name = "gcc_prng_ahb_clk", 2606 .ops = &clk_branch2_ops, 2607 }, 2608 }, 2609 }; 2610 2611 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 2612 .halt_reg = 0x17014, 2613 .halt_check = BRANCH_HALT_VOTED, 2614 .hwcg_reg = 0x17014, 2615 .hwcg_bit = 1, 2616 .clkr = { 2617 .enable_reg = 0x7900c, 2618 .enable_mask = BIT(0), 2619 .hw.init = &(struct clk_init_data){ 2620 .name = "gcc_qmip_camera_nrt_ahb_clk", 2621 .ops = &clk_branch2_ops, 2622 }, 2623 }, 2624 }; 2625 2626 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 2627 .halt_reg = 0x17060, 2628 .halt_check = BRANCH_HALT_VOTED, 2629 .hwcg_reg = 0x17060, 2630 .hwcg_bit = 1, 2631 .clkr = { 2632 .enable_reg = 0x7900c, 2633 .enable_mask = BIT(2), 2634 .hw.init = &(struct clk_init_data){ 2635 .name = "gcc_qmip_camera_rt_ahb_clk", 2636 .ops = &clk_branch2_ops, 2637 }, 2638 }, 2639 }; 2640 2641 static struct clk_branch gcc_qmip_disp_ahb_clk = { 2642 .halt_reg = 0x17018, 2643 .halt_check = BRANCH_HALT_VOTED, 2644 .hwcg_reg = 0x17018, 2645 .hwcg_bit = 1, 2646 .clkr = { 2647 .enable_reg = 0x7900c, 2648 .enable_mask = BIT(1), 2649 .hw.init = &(struct clk_init_data){ 2650 .name = "gcc_qmip_disp_ahb_clk", 2651 .ops = &clk_branch2_ops, 2652 }, 2653 }, 2654 }; 2655 2656 static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = { 2657 .halt_reg = 0x36040, 2658 .halt_check = BRANCH_HALT_VOTED, 2659 .hwcg_reg = 0x36040, 2660 .hwcg_bit = 1, 2661 .clkr = { 2662 .enable_reg = 0x7900c, 2663 .enable_mask = BIT(4), 2664 .hw.init = &(struct clk_init_data){ 2665 .name = "gcc_qmip_gpu_cfg_ahb_clk", 2666 .ops = &clk_branch2_ops, 2667 }, 2668 }, 2669 }; 2670 2671 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 2672 .halt_reg = 0x17010, 2673 .halt_check = BRANCH_HALT_VOTED, 2674 .hwcg_reg = 0x17010, 2675 .hwcg_bit = 1, 2676 .clkr = { 2677 .enable_reg = 0x79004, 2678 .enable_mask = BIT(25), 2679 .hw.init = &(struct clk_init_data){ 2680 .name = "gcc_qmip_video_vcodec_ahb_clk", 2681 .ops = &clk_branch2_ops, 2682 }, 2683 }, 2684 }; 2685 2686 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 2687 .halt_reg = 0x1f014, 2688 .halt_check = BRANCH_HALT_VOTED, 2689 .clkr = { 2690 .enable_reg = 0x7900c, 2691 .enable_mask = BIT(9), 2692 .hw.init = &(struct clk_init_data){ 2693 .name = "gcc_qupv3_wrap0_core_2x_clk", 2694 .ops = &clk_branch2_ops, 2695 }, 2696 }, 2697 }; 2698 2699 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 2700 .halt_reg = 0x1f00c, 2701 .halt_check = BRANCH_HALT_VOTED, 2702 .clkr = { 2703 .enable_reg = 0x7900c, 2704 .enable_mask = BIT(8), 2705 .hw.init = &(struct clk_init_data){ 2706 .name = "gcc_qupv3_wrap0_core_clk", 2707 .ops = &clk_branch2_ops, 2708 }, 2709 }, 2710 }; 2711 2712 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2713 .halt_reg = 0x1f144, 2714 .halt_check = BRANCH_HALT_VOTED, 2715 .clkr = { 2716 .enable_reg = 0x7900c, 2717 .enable_mask = BIT(10), 2718 .hw.init = &(struct clk_init_data){ 2719 .name = "gcc_qupv3_wrap0_s0_clk", 2720 .parent_hws = (const struct clk_hw*[]) { 2721 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 2722 }, 2723 .num_parents = 1, 2724 .flags = CLK_SET_RATE_PARENT, 2725 .ops = &clk_branch2_ops, 2726 }, 2727 }, 2728 }; 2729 2730 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2731 .halt_reg = 0x1f274, 2732 .halt_check = BRANCH_HALT_VOTED, 2733 .clkr = { 2734 .enable_reg = 0x7900c, 2735 .enable_mask = BIT(11), 2736 .hw.init = &(struct clk_init_data){ 2737 .name = "gcc_qupv3_wrap0_s1_clk", 2738 .parent_hws = (const struct clk_hw*[]) { 2739 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 2740 }, 2741 .num_parents = 1, 2742 .flags = CLK_SET_RATE_PARENT, 2743 .ops = &clk_branch2_ops, 2744 }, 2745 }, 2746 }; 2747 2748 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2749 .halt_reg = 0x1f3a4, 2750 .halt_check = BRANCH_HALT_VOTED, 2751 .clkr = { 2752 .enable_reg = 0x7900c, 2753 .enable_mask = BIT(12), 2754 .hw.init = &(struct clk_init_data){ 2755 .name = "gcc_qupv3_wrap0_s2_clk", 2756 .parent_hws = (const struct clk_hw*[]) { 2757 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 2758 }, 2759 .num_parents = 1, 2760 .flags = CLK_SET_RATE_PARENT, 2761 .ops = &clk_branch2_ops, 2762 }, 2763 }, 2764 }; 2765 2766 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2767 .halt_reg = 0x1f4d4, 2768 .halt_check = BRANCH_HALT_VOTED, 2769 .clkr = { 2770 .enable_reg = 0x7900c, 2771 .enable_mask = BIT(13), 2772 .hw.init = &(struct clk_init_data){ 2773 .name = "gcc_qupv3_wrap0_s3_clk", 2774 .parent_hws = (const struct clk_hw*[]) { 2775 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 2776 }, 2777 .num_parents = 1, 2778 .flags = CLK_SET_RATE_PARENT, 2779 .ops = &clk_branch2_ops, 2780 }, 2781 }, 2782 }; 2783 2784 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2785 .halt_reg = 0x1f604, 2786 .halt_check = BRANCH_HALT_VOTED, 2787 .clkr = { 2788 .enable_reg = 0x7900c, 2789 .enable_mask = BIT(14), 2790 .hw.init = &(struct clk_init_data){ 2791 .name = "gcc_qupv3_wrap0_s4_clk", 2792 .parent_hws = (const struct clk_hw*[]) { 2793 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 2794 }, 2795 .num_parents = 1, 2796 .flags = CLK_SET_RATE_PARENT, 2797 .ops = &clk_branch2_ops, 2798 }, 2799 }, 2800 }; 2801 2802 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2803 .halt_reg = 0x1f734, 2804 .halt_check = BRANCH_HALT_VOTED, 2805 .clkr = { 2806 .enable_reg = 0x7900c, 2807 .enable_mask = BIT(15), 2808 .hw.init = &(struct clk_init_data){ 2809 .name = "gcc_qupv3_wrap0_s5_clk", 2810 .parent_hws = (const struct clk_hw*[]) { 2811 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 2812 }, 2813 .num_parents = 1, 2814 .flags = CLK_SET_RATE_PARENT, 2815 .ops = &clk_branch2_ops, 2816 }, 2817 }, 2818 }; 2819 2820 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 2821 .halt_reg = 0x53014, 2822 .halt_check = BRANCH_HALT_VOTED, 2823 .clkr = { 2824 .enable_reg = 0x7900c, 2825 .enable_mask = BIT(20), 2826 .hw.init = &(struct clk_init_data){ 2827 .name = "gcc_qupv3_wrap1_core_2x_clk", 2828 .ops = &clk_branch2_ops, 2829 }, 2830 }, 2831 }; 2832 2833 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 2834 .halt_reg = 0x5300c, 2835 .halt_check = BRANCH_HALT_VOTED, 2836 .clkr = { 2837 .enable_reg = 0x7900c, 2838 .enable_mask = BIT(19), 2839 .hw.init = &(struct clk_init_data){ 2840 .name = "gcc_qupv3_wrap1_core_clk", 2841 .ops = &clk_branch2_ops, 2842 }, 2843 }, 2844 }; 2845 2846 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2847 .halt_reg = 0x53018, 2848 .halt_check = BRANCH_HALT_VOTED, 2849 .clkr = { 2850 .enable_reg = 0x7900c, 2851 .enable_mask = BIT(21), 2852 .hw.init = &(struct clk_init_data){ 2853 .name = "gcc_qupv3_wrap1_s0_clk", 2854 .parent_hws = (const struct clk_hw*[]) { 2855 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 2856 }, 2857 .num_parents = 1, 2858 .flags = CLK_SET_RATE_PARENT, 2859 .ops = &clk_branch2_ops, 2860 }, 2861 }, 2862 }; 2863 2864 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2865 .halt_reg = 0x53148, 2866 .halt_check = BRANCH_HALT_VOTED, 2867 .clkr = { 2868 .enable_reg = 0x7900c, 2869 .enable_mask = BIT(22), 2870 .hw.init = &(struct clk_init_data){ 2871 .name = "gcc_qupv3_wrap1_s1_clk", 2872 .parent_hws = (const struct clk_hw*[]) { 2873 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 2874 }, 2875 .num_parents = 1, 2876 .flags = CLK_SET_RATE_PARENT, 2877 .ops = &clk_branch2_ops, 2878 }, 2879 }, 2880 }; 2881 2882 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2883 .halt_reg = 0x53278, 2884 .halt_check = BRANCH_HALT_VOTED, 2885 .clkr = { 2886 .enable_reg = 0x7900c, 2887 .enable_mask = BIT(23), 2888 .hw.init = &(struct clk_init_data){ 2889 .name = "gcc_qupv3_wrap1_s2_clk", 2890 .parent_hws = (const struct clk_hw*[]) { 2891 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 2892 }, 2893 .num_parents = 1, 2894 .flags = CLK_SET_RATE_PARENT, 2895 .ops = &clk_branch2_ops, 2896 }, 2897 }, 2898 }; 2899 2900 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2901 .halt_reg = 0x533a8, 2902 .halt_check = BRANCH_HALT_VOTED, 2903 .clkr = { 2904 .enable_reg = 0x7900c, 2905 .enable_mask = BIT(24), 2906 .hw.init = &(struct clk_init_data){ 2907 .name = "gcc_qupv3_wrap1_s3_clk", 2908 .parent_hws = (const struct clk_hw*[]) { 2909 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2910 }, 2911 .num_parents = 1, 2912 .flags = CLK_SET_RATE_PARENT, 2913 .ops = &clk_branch2_ops, 2914 }, 2915 }, 2916 }; 2917 2918 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2919 .halt_reg = 0x534d8, 2920 .halt_check = BRANCH_HALT_VOTED, 2921 .clkr = { 2922 .enable_reg = 0x7900c, 2923 .enable_mask = BIT(25), 2924 .hw.init = &(struct clk_init_data){ 2925 .name = "gcc_qupv3_wrap1_s4_clk", 2926 .parent_hws = (const struct clk_hw*[]) { 2927 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2928 }, 2929 .num_parents = 1, 2930 .flags = CLK_SET_RATE_PARENT, 2931 .ops = &clk_branch2_ops, 2932 }, 2933 }, 2934 }; 2935 2936 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2937 .halt_reg = 0x53608, 2938 .halt_check = BRANCH_HALT_VOTED, 2939 .clkr = { 2940 .enable_reg = 0x7900c, 2941 .enable_mask = BIT(26), 2942 .hw.init = &(struct clk_init_data){ 2943 .name = "gcc_qupv3_wrap1_s5_clk", 2944 .parent_hws = (const struct clk_hw*[]) { 2945 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 2946 }, 2947 .num_parents = 1, 2948 .flags = CLK_SET_RATE_PARENT, 2949 .ops = &clk_branch2_ops, 2950 }, 2951 }, 2952 }; 2953 2954 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2955 .halt_reg = 0x1f004, 2956 .halt_check = BRANCH_HALT_VOTED, 2957 .hwcg_reg = 0x1f004, 2958 .hwcg_bit = 1, 2959 .clkr = { 2960 .enable_reg = 0x7900c, 2961 .enable_mask = BIT(6), 2962 .hw.init = &(struct clk_init_data){ 2963 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2964 .ops = &clk_branch2_ops, 2965 }, 2966 }, 2967 }; 2968 2969 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2970 .halt_reg = 0x1f008, 2971 .halt_check = BRANCH_HALT_VOTED, 2972 .hwcg_reg = 0x1f008, 2973 .hwcg_bit = 1, 2974 .clkr = { 2975 .enable_reg = 0x7900c, 2976 .enable_mask = BIT(7), 2977 .hw.init = &(struct clk_init_data){ 2978 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2979 .ops = &clk_branch2_ops, 2980 }, 2981 }, 2982 }; 2983 2984 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2985 .halt_reg = 0x53004, 2986 .halt_check = BRANCH_HALT_VOTED, 2987 .hwcg_reg = 0x53004, 2988 .hwcg_bit = 1, 2989 .clkr = { 2990 .enable_reg = 0x7900c, 2991 .enable_mask = BIT(17), 2992 .hw.init = &(struct clk_init_data){ 2993 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2994 .ops = &clk_branch2_ops, 2995 }, 2996 }, 2997 }; 2998 2999 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 3000 .halt_reg = 0x53008, 3001 .halt_check = BRANCH_HALT_VOTED, 3002 .hwcg_reg = 0x53008, 3003 .hwcg_bit = 1, 3004 .clkr = { 3005 .enable_reg = 0x7900c, 3006 .enable_mask = BIT(18), 3007 .hw.init = &(struct clk_init_data){ 3008 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 3009 .ops = &clk_branch2_ops, 3010 }, 3011 }, 3012 }; 3013 3014 static struct clk_branch gcc_sdcc1_ahb_clk = { 3015 .halt_reg = 0x38008, 3016 .halt_check = BRANCH_HALT, 3017 .clkr = { 3018 .enable_reg = 0x38008, 3019 .enable_mask = BIT(0), 3020 .hw.init = &(struct clk_init_data){ 3021 .name = "gcc_sdcc1_ahb_clk", 3022 .ops = &clk_branch2_ops, 3023 }, 3024 }, 3025 }; 3026 3027 static struct clk_branch gcc_sdcc1_apps_clk = { 3028 .halt_reg = 0x38004, 3029 .halt_check = BRANCH_HALT, 3030 .clkr = { 3031 .enable_reg = 0x38004, 3032 .enable_mask = BIT(0), 3033 .hw.init = &(struct clk_init_data){ 3034 .name = "gcc_sdcc1_apps_clk", 3035 .parent_hws = (const struct clk_hw*[]) { 3036 &gcc_sdcc1_apps_clk_src.clkr.hw, 3037 }, 3038 .num_parents = 1, 3039 .flags = CLK_SET_RATE_PARENT, 3040 .ops = &clk_branch2_ops, 3041 }, 3042 }, 3043 }; 3044 3045 static struct clk_branch gcc_sdcc1_ice_core_clk = { 3046 .halt_reg = 0x3800c, 3047 .halt_check = BRANCH_HALT_VOTED, 3048 .hwcg_reg = 0x3800c, 3049 .hwcg_bit = 1, 3050 .clkr = { 3051 .enable_reg = 0x3800c, 3052 .enable_mask = BIT(0), 3053 .hw.init = &(struct clk_init_data){ 3054 .name = "gcc_sdcc1_ice_core_clk", 3055 .parent_hws = (const struct clk_hw*[]) { 3056 &gcc_sdcc1_ice_core_clk_src.clkr.hw, 3057 }, 3058 .num_parents = 1, 3059 .flags = CLK_SET_RATE_PARENT, 3060 .ops = &clk_branch2_ops, 3061 }, 3062 }, 3063 }; 3064 3065 static struct clk_branch gcc_sdcc2_ahb_clk = { 3066 .halt_reg = 0x1e008, 3067 .halt_check = BRANCH_HALT, 3068 .clkr = { 3069 .enable_reg = 0x1e008, 3070 .enable_mask = BIT(0), 3071 .hw.init = &(struct clk_init_data){ 3072 .name = "gcc_sdcc2_ahb_clk", 3073 .ops = &clk_branch2_ops, 3074 }, 3075 }, 3076 }; 3077 3078 static struct clk_branch gcc_sdcc2_apps_clk = { 3079 .halt_reg = 0x1e004, 3080 .halt_check = BRANCH_HALT, 3081 .clkr = { 3082 .enable_reg = 0x1e004, 3083 .enable_mask = BIT(0), 3084 .hw.init = &(struct clk_init_data){ 3085 .name = "gcc_sdcc2_apps_clk", 3086 .parent_hws = (const struct clk_hw*[]) { 3087 &gcc_sdcc2_apps_clk_src.clkr.hw, 3088 }, 3089 .num_parents = 1, 3090 .flags = CLK_SET_RATE_PARENT, 3091 .ops = &clk_branch2_ops, 3092 }, 3093 }, 3094 }; 3095 3096 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 3097 .halt_reg = 0x2b06c, 3098 .halt_check = BRANCH_HALT_VOTED, 3099 .hwcg_reg = 0x2b06c, 3100 .hwcg_bit = 1, 3101 .clkr = { 3102 .enable_reg = 0x79004, 3103 .enable_mask = BIT(0), 3104 .hw.init = &(struct clk_init_data){ 3105 .name = "gcc_sys_noc_cpuss_ahb_clk", 3106 .parent_hws = (const struct clk_hw*[]) { 3107 &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, 3108 }, 3109 .num_parents = 1, 3110 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 3111 .ops = &clk_branch2_ops, 3112 }, 3113 }, 3114 }; 3115 3116 static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = { 3117 .halt_reg = 0x45098, 3118 .halt_check = BRANCH_HALT, 3119 .clkr = { 3120 .enable_reg = 0x45098, 3121 .enable_mask = BIT(0), 3122 .hw.init = &(struct clk_init_data){ 3123 .name = "gcc_sys_noc_ufs_phy_axi_clk", 3124 .parent_hws = (const struct clk_hw*[]) { 3125 &gcc_ufs_phy_axi_clk_src.clkr.hw, 3126 }, 3127 .num_parents = 1, 3128 .flags = CLK_SET_RATE_PARENT, 3129 .ops = &clk_branch2_ops, 3130 }, 3131 }, 3132 }; 3133 3134 static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { 3135 .halt_reg = 0x1a080, 3136 .halt_check = BRANCH_HALT_VOTED, 3137 .hwcg_reg = 0x1a080, 3138 .hwcg_bit = 1, 3139 .clkr = { 3140 .enable_reg = 0x1a080, 3141 .enable_mask = BIT(0), 3142 .hw.init = &(struct clk_init_data){ 3143 .name = "gcc_sys_noc_usb3_prim_axi_clk", 3144 .parent_hws = (const struct clk_hw*[]) { 3145 &gcc_usb30_prim_master_clk_src.clkr.hw, 3146 }, 3147 .num_parents = 1, 3148 .flags = CLK_SET_RATE_PARENT, 3149 .ops = &clk_branch2_ops, 3150 }, 3151 }, 3152 }; 3153 3154 static struct clk_branch gcc_ufs_phy_ahb_clk = { 3155 .halt_reg = 0x45014, 3156 .halt_check = BRANCH_HALT_VOTED, 3157 .hwcg_reg = 0x45014, 3158 .hwcg_bit = 1, 3159 .clkr = { 3160 .enable_reg = 0x45014, 3161 .enable_mask = BIT(0), 3162 .hw.init = &(struct clk_init_data){ 3163 .name = "gcc_ufs_phy_ahb_clk", 3164 .ops = &clk_branch2_ops, 3165 }, 3166 }, 3167 }; 3168 3169 static struct clk_branch gcc_ufs_phy_axi_clk = { 3170 .halt_reg = 0x45010, 3171 .halt_check = BRANCH_HALT_VOTED, 3172 .hwcg_reg = 0x45010, 3173 .hwcg_bit = 1, 3174 .clkr = { 3175 .enable_reg = 0x45010, 3176 .enable_mask = BIT(0), 3177 .hw.init = &(struct clk_init_data){ 3178 .name = "gcc_ufs_phy_axi_clk", 3179 .parent_hws = (const struct clk_hw*[]) { 3180 &gcc_ufs_phy_axi_clk_src.clkr.hw, 3181 }, 3182 .num_parents = 1, 3183 .flags = CLK_SET_RATE_PARENT, 3184 .ops = &clk_branch2_ops, 3185 }, 3186 }, 3187 }; 3188 3189 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 3190 .halt_reg = 0x45044, 3191 .halt_check = BRANCH_HALT_VOTED, 3192 .hwcg_reg = 0x45044, 3193 .hwcg_bit = 1, 3194 .clkr = { 3195 .enable_reg = 0x45044, 3196 .enable_mask = BIT(0), 3197 .hw.init = &(struct clk_init_data){ 3198 .name = "gcc_ufs_phy_ice_core_clk", 3199 .parent_hws = (const struct clk_hw*[]) { 3200 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 3201 }, 3202 .num_parents = 1, 3203 .flags = CLK_SET_RATE_PARENT, 3204 .ops = &clk_branch2_ops, 3205 }, 3206 }, 3207 }; 3208 3209 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 3210 .halt_reg = 0x45078, 3211 .halt_check = BRANCH_HALT_VOTED, 3212 .hwcg_reg = 0x45078, 3213 .hwcg_bit = 1, 3214 .clkr = { 3215 .enable_reg = 0x45078, 3216 .enable_mask = BIT(0), 3217 .hw.init = &(struct clk_init_data){ 3218 .name = "gcc_ufs_phy_phy_aux_clk", 3219 .parent_hws = (const struct clk_hw*[]) { 3220 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 3221 }, 3222 .num_parents = 1, 3223 .flags = CLK_SET_RATE_PARENT, 3224 .ops = &clk_branch2_ops, 3225 }, 3226 }, 3227 }; 3228 3229 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 3230 .halt_reg = 0x4501c, 3231 .halt_check = BRANCH_HALT_SKIP, 3232 .clkr = { 3233 .enable_reg = 0x4501c, 3234 .enable_mask = BIT(0), 3235 .hw.init = &(struct clk_init_data){ 3236 .name = "gcc_ufs_phy_rx_symbol_0_clk", 3237 .ops = &clk_branch2_ops, 3238 }, 3239 }, 3240 }; 3241 3242 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 3243 .halt_reg = 0x45018, 3244 .halt_check = BRANCH_HALT_SKIP, 3245 .clkr = { 3246 .enable_reg = 0x45018, 3247 .enable_mask = BIT(0), 3248 .hw.init = &(struct clk_init_data){ 3249 .name = "gcc_ufs_phy_tx_symbol_0_clk", 3250 .ops = &clk_branch2_ops, 3251 }, 3252 }, 3253 }; 3254 3255 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 3256 .halt_reg = 0x45040, 3257 .halt_check = BRANCH_HALT_VOTED, 3258 .hwcg_reg = 0x45040, 3259 .hwcg_bit = 1, 3260 .clkr = { 3261 .enable_reg = 0x45040, 3262 .enable_mask = BIT(0), 3263 .hw.init = &(struct clk_init_data){ 3264 .name = "gcc_ufs_phy_unipro_core_clk", 3265 .parent_hws = (const struct clk_hw*[]) { 3266 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 3267 }, 3268 .num_parents = 1, 3269 .flags = CLK_SET_RATE_PARENT, 3270 .ops = &clk_branch2_ops, 3271 }, 3272 }, 3273 }; 3274 3275 static struct clk_branch gcc_usb30_prim_master_clk = { 3276 .halt_reg = 0x1a010, 3277 .halt_check = BRANCH_HALT, 3278 .clkr = { 3279 .enable_reg = 0x1a010, 3280 .enable_mask = BIT(0), 3281 .hw.init = &(struct clk_init_data){ 3282 .name = "gcc_usb30_prim_master_clk", 3283 .parent_hws = (const struct clk_hw*[]) { 3284 &gcc_usb30_prim_master_clk_src.clkr.hw, 3285 }, 3286 .num_parents = 1, 3287 .flags = CLK_SET_RATE_PARENT, 3288 .ops = &clk_branch2_ops, 3289 }, 3290 }, 3291 }; 3292 3293 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 3294 .halt_reg = 0x1a018, 3295 .halt_check = BRANCH_HALT, 3296 .clkr = { 3297 .enable_reg = 0x1a018, 3298 .enable_mask = BIT(0), 3299 .hw.init = &(struct clk_init_data){ 3300 .name = "gcc_usb30_prim_mock_utmi_clk", 3301 .parent_hws = (const struct clk_hw*[]) { 3302 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 3303 }, 3304 .num_parents = 1, 3305 .flags = CLK_SET_RATE_PARENT, 3306 .ops = &clk_branch2_ops, 3307 }, 3308 }, 3309 }; 3310 3311 static struct clk_branch gcc_usb30_prim_sleep_clk = { 3312 .halt_reg = 0x1a014, 3313 .halt_check = BRANCH_HALT, 3314 .clkr = { 3315 .enable_reg = 0x1a014, 3316 .enable_mask = BIT(0), 3317 .hw.init = &(struct clk_init_data){ 3318 .name = "gcc_usb30_prim_sleep_clk", 3319 .ops = &clk_branch2_ops, 3320 }, 3321 }, 3322 }; 3323 3324 static struct clk_branch gcc_ufs_mem_clkref_clk = { 3325 .halt_reg = 0x8c000, 3326 .halt_check = BRANCH_HALT, 3327 .clkr = { 3328 .enable_reg = 0x8c000, 3329 .enable_mask = BIT(0), 3330 .hw.init = &(struct clk_init_data){ 3331 .name = "gcc_ufs_mem_clkref_clk", 3332 .ops = &clk_branch2_ops, 3333 }, 3334 }, 3335 }; 3336 3337 static struct clk_branch gcc_rx5_pcie_clkref_en_clk = { 3338 .halt_reg = 0x8c00c, 3339 .halt_check = BRANCH_HALT, 3340 .clkr = { 3341 .enable_reg = 0x8c00c, 3342 .enable_mask = BIT(0), 3343 .hw.init = &(struct clk_init_data){ 3344 .name = "gcc_rx5_pcie_clkref_en_clk", 3345 .ops = &clk_branch2_ops, 3346 }, 3347 }, 3348 }; 3349 3350 static struct clk_branch gcc_usb3_prim_clkref_clk = { 3351 .halt_reg = 0x8c010, 3352 .halt_check = BRANCH_HALT, 3353 .clkr = { 3354 .enable_reg = 0x8c010, 3355 .enable_mask = BIT(0), 3356 .hw.init = &(struct clk_init_data){ 3357 .name = "gcc_usb3_prim_clkref_clk", 3358 .ops = &clk_branch2_ops, 3359 }, 3360 }, 3361 }; 3362 3363 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 3364 .halt_reg = 0x1a054, 3365 .halt_check = BRANCH_HALT, 3366 .clkr = { 3367 .enable_reg = 0x1a054, 3368 .enable_mask = BIT(0), 3369 .hw.init = &(struct clk_init_data){ 3370 .name = "gcc_usb3_prim_phy_com_aux_clk", 3371 .parent_hws = (const struct clk_hw*[]) { 3372 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3373 }, 3374 .num_parents = 1, 3375 .flags = CLK_SET_RATE_PARENT, 3376 .ops = &clk_branch2_ops, 3377 }, 3378 }, 3379 }; 3380 3381 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 3382 .halt_reg = 0x1a058, 3383 .halt_check = BRANCH_HALT_SKIP, 3384 .hwcg_reg = 0x1a058, 3385 .hwcg_bit = 1, 3386 .clkr = { 3387 .enable_reg = 0x1a058, 3388 .enable_mask = BIT(0), 3389 .hw.init = &(struct clk_init_data){ 3390 .name = "gcc_usb3_prim_phy_pipe_clk", 3391 .ops = &clk_branch2_ops, 3392 }, 3393 }, 3394 }; 3395 3396 static struct clk_branch gcc_vcodec0_axi_clk = { 3397 .halt_reg = 0x6e008, 3398 .halt_check = BRANCH_HALT, 3399 .clkr = { 3400 .enable_reg = 0x6e008, 3401 .enable_mask = BIT(0), 3402 .hw.init = &(struct clk_init_data){ 3403 .name = "gcc_vcodec0_axi_clk", 3404 .ops = &clk_branch2_ops, 3405 }, 3406 }, 3407 }; 3408 3409 static struct clk_branch gcc_venus_ahb_clk = { 3410 .halt_reg = 0x6e010, 3411 .halt_check = BRANCH_HALT, 3412 .clkr = { 3413 .enable_reg = 0x6e010, 3414 .enable_mask = BIT(0), 3415 .hw.init = &(struct clk_init_data){ 3416 .name = "gcc_venus_ahb_clk", 3417 .ops = &clk_branch2_ops, 3418 }, 3419 }, 3420 }; 3421 3422 static struct clk_branch gcc_venus_ctl_axi_clk = { 3423 .halt_reg = 0x6e004, 3424 .halt_check = BRANCH_HALT, 3425 .clkr = { 3426 .enable_reg = 0x6e004, 3427 .enable_mask = BIT(0), 3428 .hw.init = &(struct clk_init_data){ 3429 .name = "gcc_venus_ctl_axi_clk", 3430 .ops = &clk_branch2_ops, 3431 }, 3432 }, 3433 }; 3434 3435 static struct clk_branch gcc_video_ahb_clk = { 3436 .halt_reg = 0x17004, 3437 .halt_check = BRANCH_HALT_DELAY, 3438 .hwcg_reg = 0x17004, 3439 .hwcg_bit = 1, 3440 .clkr = { 3441 .enable_reg = 0x17004, 3442 .enable_mask = BIT(0), 3443 .hw.init = &(struct clk_init_data){ 3444 .name = "gcc_video_ahb_clk", 3445 .flags = CLK_IS_CRITICAL, 3446 .ops = &clk_branch2_ops, 3447 }, 3448 }, 3449 }; 3450 3451 static struct clk_branch gcc_video_axi0_clk = { 3452 .halt_reg = 0x1701c, 3453 .halt_check = BRANCH_HALT_VOTED, 3454 .hwcg_reg = 0x1701c, 3455 .hwcg_bit = 1, 3456 .clkr = { 3457 .enable_reg = 0x1701c, 3458 .enable_mask = BIT(0), 3459 .hw.init = &(struct clk_init_data){ 3460 .name = "gcc_video_axi0_clk", 3461 .ops = &clk_branch2_ops, 3462 }, 3463 }, 3464 }; 3465 3466 static struct clk_branch gcc_video_throttle_core_clk = { 3467 .halt_reg = 0x17068, 3468 .halt_check = BRANCH_HALT_VOTED, 3469 .hwcg_reg = 0x17068, 3470 .hwcg_bit = 1, 3471 .clkr = { 3472 .enable_reg = 0x79004, 3473 .enable_mask = BIT(28), 3474 .hw.init = &(struct clk_init_data){ 3475 .name = "gcc_video_throttle_core_clk", 3476 .ops = &clk_branch2_ops, 3477 }, 3478 }, 3479 }; 3480 3481 static struct clk_branch gcc_video_vcodec0_sys_clk = { 3482 .halt_reg = 0x580a4, 3483 .halt_check = BRANCH_HALT_VOTED, 3484 .hwcg_reg = 0x580a4, 3485 .hwcg_bit = 1, 3486 .clkr = { 3487 .enable_reg = 0x580a4, 3488 .enable_mask = BIT(0), 3489 .hw.init = &(struct clk_init_data){ 3490 .name = "gcc_video_vcodec0_sys_clk", 3491 .parent_hws = (const struct clk_hw*[]) { 3492 &gcc_video_venus_clk_src.clkr.hw, 3493 }, 3494 .num_parents = 1, 3495 .flags = CLK_SET_RATE_PARENT, 3496 .ops = &clk_branch2_ops, 3497 }, 3498 }, 3499 }; 3500 3501 static struct clk_branch gcc_video_venus_ctl_clk = { 3502 .halt_reg = 0x5808c, 3503 .halt_check = BRANCH_HALT, 3504 .clkr = { 3505 .enable_reg = 0x5808c, 3506 .enable_mask = BIT(0), 3507 .hw.init = &(struct clk_init_data){ 3508 .name = "gcc_video_venus_ctl_clk", 3509 .parent_hws = (const struct clk_hw*[]) { 3510 &gcc_video_venus_clk_src.clkr.hw, 3511 }, 3512 .num_parents = 1, 3513 .flags = CLK_SET_RATE_PARENT, 3514 .ops = &clk_branch2_ops, 3515 }, 3516 }, 3517 }; 3518 3519 static struct clk_branch gcc_video_xo_clk = { 3520 .halt_reg = 0x17024, 3521 .halt_check = BRANCH_HALT, 3522 .clkr = { 3523 .enable_reg = 0x17024, 3524 .enable_mask = BIT(0), 3525 .hw.init = &(struct clk_init_data){ 3526 .name = "gcc_video_xo_clk", 3527 .ops = &clk_branch2_ops, 3528 }, 3529 }, 3530 }; 3531 3532 static struct gdsc usb30_prim_gdsc = { 3533 .gdscr = 0x1a004, 3534 .pd = { 3535 .name = "usb30_prim_gdsc", 3536 }, 3537 /* TODO: Change to OFF_ON when USB drivers get proper suspend support */ 3538 .pwrsts = PWRSTS_RET_ON, 3539 }; 3540 3541 static struct gdsc ufs_phy_gdsc = { 3542 .gdscr = 0x45004, 3543 .pd = { 3544 .name = "ufs_phy_gdsc", 3545 }, 3546 .pwrsts = PWRSTS_OFF_ON, 3547 }; 3548 3549 static struct gdsc camss_top_gdsc = { 3550 .gdscr = 0x58004, 3551 .pd = { 3552 .name = "camss_top_gdsc", 3553 }, 3554 .pwrsts = PWRSTS_OFF_ON, 3555 }; 3556 3557 static struct gdsc venus_gdsc = { 3558 .gdscr = 0x5807c, 3559 .pd = { 3560 .name = "venus_gdsc", 3561 }, 3562 .pwrsts = PWRSTS_OFF_ON, 3563 }; 3564 3565 static struct gdsc vcodec0_gdsc = { 3566 .gdscr = 0x58098, 3567 .pd = { 3568 .name = "vcodec0_gdsc", 3569 }, 3570 .pwrsts = PWRSTS_OFF_ON, 3571 .flags = HW_CTRL, 3572 }; 3573 3574 static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = { 3575 .gdscr = 0x7d074, 3576 .pd = { 3577 .name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc", 3578 }, 3579 .pwrsts = PWRSTS_OFF_ON, 3580 .flags = VOTABLE, 3581 }; 3582 3583 static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = { 3584 .gdscr = 0x7d078, 3585 .pd = { 3586 .name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc", 3587 }, 3588 .pwrsts = PWRSTS_OFF_ON, 3589 .flags = VOTABLE, 3590 }; 3591 3592 static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = { 3593 .gdscr = 0x7d060, 3594 .pd = { 3595 .name = "hlos1_vote_turing_mmu_tbu1_gdsc", 3596 }, 3597 .pwrsts = PWRSTS_OFF_ON, 3598 .flags = VOTABLE, 3599 }; 3600 3601 static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = { 3602 .gdscr = 0x7d07c, 3603 .pd = { 3604 .name = "hlos1_vote_turing_mmu_tbu0_gdsc", 3605 }, 3606 .pwrsts = PWRSTS_OFF_ON, 3607 .flags = VOTABLE, 3608 }; 3609 3610 static struct clk_regmap *gcc_sm6375_clocks[] = { 3611 [GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr, 3612 [GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr, 3613 [GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr, 3614 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3615 [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, 3616 [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, 3617 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, 3618 [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, 3619 [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, 3620 [GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr, 3621 [GCC_CAMSS_CCI_0_CLK_SRC] = &gcc_camss_cci_0_clk_src.clkr, 3622 [GCC_CAMSS_CCI_1_CLK] = &gcc_camss_cci_1_clk.clkr, 3623 [GCC_CAMSS_CCI_1_CLK_SRC] = &gcc_camss_cci_1_clk_src.clkr, 3624 [GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr, 3625 [GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr, 3626 [GCC_CAMSS_CPHY_2_CLK] = &gcc_camss_cphy_2_clk.clkr, 3627 [GCC_CAMSS_CPHY_3_CLK] = &gcc_camss_cphy_3_clk.clkr, 3628 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, 3629 [GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr, 3630 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, 3631 [GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr, 3632 [GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr, 3633 [GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr, 3634 [GCC_CAMSS_CSI3PHYTIMER_CLK] = &gcc_camss_csi3phytimer_clk.clkr, 3635 [GCC_CAMSS_CSI3PHYTIMER_CLK_SRC] = &gcc_camss_csi3phytimer_clk_src.clkr, 3636 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, 3637 [GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr, 3638 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, 3639 [GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr, 3640 [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr, 3641 [GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr, 3642 [GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr, 3643 [GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr, 3644 [GCC_CAMSS_MCLK4_CLK] = &gcc_camss_mclk4_clk.clkr, 3645 [GCC_CAMSS_MCLK4_CLK_SRC] = &gcc_camss_mclk4_clk_src.clkr, 3646 [GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr, 3647 [GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr, 3648 [GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr, 3649 [GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr, 3650 [GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr, 3651 [GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr, 3652 [GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr, 3653 [GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr, 3654 [GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr, 3655 [GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr, 3656 [GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr, 3657 [GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr, 3658 [GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr, 3659 [GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr, 3660 [GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr, 3661 [GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr, 3662 [GCC_CAMSS_TFE_2_CLK] = &gcc_camss_tfe_2_clk.clkr, 3663 [GCC_CAMSS_TFE_2_CLK_SRC] = &gcc_camss_tfe_2_clk_src.clkr, 3664 [GCC_CAMSS_TFE_2_CPHY_RX_CLK] = &gcc_camss_tfe_2_cphy_rx_clk.clkr, 3665 [GCC_CAMSS_TFE_2_CSID_CLK] = &gcc_camss_tfe_2_csid_clk.clkr, 3666 [GCC_CAMSS_TFE_2_CSID_CLK_SRC] = &gcc_camss_tfe_2_csid_clk_src.clkr, 3667 [GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr, 3668 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, 3669 [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, 3670 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3671 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, 3672 [GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr, 3673 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, 3674 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, 3675 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, 3676 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3677 [GCC_DISP_SLEEP_CLK] = &gcc_disp_sleep_clk.clkr, 3678 [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, 3679 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3680 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3681 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3682 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3683 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3684 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3685 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 3686 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3687 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3688 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3689 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3690 [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr, 3691 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3692 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3693 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3694 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3695 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3696 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3697 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3698 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3699 [GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr, 3700 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3701 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 3702 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 3703 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3704 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3705 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3706 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3707 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3708 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3709 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3710 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3711 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3712 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3713 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3714 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3715 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 3716 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 3717 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3718 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3719 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3720 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3721 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3722 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3723 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3724 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3725 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3726 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3727 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3728 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3729 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3730 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3731 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 3732 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3733 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 3734 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 3735 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 3736 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 3737 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 3738 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3739 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3740 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3741 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 3742 [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr, 3743 [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, 3744 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3745 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3746 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3747 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3748 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3749 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3750 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3751 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3752 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3753 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3754 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 3755 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3756 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3757 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3758 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3759 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3760 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3761 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 3762 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3763 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3764 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3765 [GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr, 3766 [GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr, 3767 [GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr, 3768 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, 3769 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3770 [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr, 3771 [GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr, 3772 [GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr, 3773 [GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr, 3774 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 3775 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, 3776 [GCC_RX5_PCIE_CLKREF_EN_CLK] = &gcc_rx5_pcie_clkref_en_clk.clkr, 3777 [GPLL0] = &gpll0.clkr, 3778 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 3779 [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr, 3780 [GPLL1] = &gpll1.clkr, 3781 [GPLL10] = &gpll10.clkr, 3782 [GPLL11] = &gpll11.clkr, 3783 [GPLL3] = &gpll3.clkr, 3784 [GPLL3_OUT_EVEN] = &gpll3_out_even.clkr, 3785 [GPLL4] = &gpll4.clkr, 3786 [GPLL5] = &gpll5.clkr, 3787 [GPLL6] = &gpll6.clkr, 3788 [GPLL6_OUT_EVEN] = &gpll6_out_even.clkr, 3789 [GPLL7] = &gpll7.clkr, 3790 [GPLL8] = &gpll8.clkr, 3791 [GPLL8_OUT_EVEN] = &gpll8_out_even.clkr, 3792 [GPLL9] = &gpll9.clkr, 3793 [GPLL9_OUT_MAIN] = &gpll9_out_main.clkr, 3794 }; 3795 3796 static const struct qcom_reset_map gcc_sm6375_resets[] = { 3797 [GCC_MMSS_BCR] = { 0x17000 }, 3798 [GCC_USB30_PRIM_BCR] = { 0x1a000 }, 3799 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, 3800 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x1b020 }, 3801 [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, 3802 [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 }, 3803 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, 3804 [GCC_SDCC2_BCR] = { 0x1e000 }, 3805 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x1f000 }, 3806 [GCC_PDM_BCR] = { 0x20000 }, 3807 [GCC_GPU_BCR] = { 0x36000 }, 3808 [GCC_SDCC1_BCR] = { 0x38000 }, 3809 [GCC_UFS_PHY_BCR] = { 0x45000 }, 3810 [GCC_CAMSS_TFE_BCR] = { 0x52000 }, 3811 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x53000 }, 3812 [GCC_CAMSS_OPE_BCR] = { 0x55000 }, 3813 [GCC_CAMSS_TOP_BCR] = { 0x58000 }, 3814 [GCC_VENUS_BCR] = { 0x58078 }, 3815 [GCC_VCODEC0_BCR] = { 0x58094 }, 3816 [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 }, 3817 }; 3818 3819 3820 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3821 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 3822 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 3823 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 3824 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 3825 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 3826 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 3827 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3828 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3829 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 3830 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3831 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3832 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3833 }; 3834 3835 static struct gdsc *gcc_sm6375_gdscs[] = { 3836 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 3837 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 3838 [CAMSS_TOP_GDSC] = &camss_top_gdsc, 3839 [VENUS_GDSC] = &venus_gdsc, 3840 [VCODEC0_GDSC] = &vcodec0_gdsc, 3841 [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc, 3842 [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc, 3843 [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc, 3844 [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc, 3845 }; 3846 3847 static const struct regmap_config gcc_sm6375_regmap_config = { 3848 .reg_bits = 32, 3849 .reg_stride = 4, 3850 .val_bits = 32, 3851 .max_register = 0xc7000, 3852 .fast_io = true, 3853 }; 3854 3855 static const struct qcom_cc_desc gcc_sm6375_desc = { 3856 .config = &gcc_sm6375_regmap_config, 3857 .clks = gcc_sm6375_clocks, 3858 .num_clks = ARRAY_SIZE(gcc_sm6375_clocks), 3859 .resets = gcc_sm6375_resets, 3860 .num_resets = ARRAY_SIZE(gcc_sm6375_resets), 3861 .gdscs = gcc_sm6375_gdscs, 3862 .num_gdscs = ARRAY_SIZE(gcc_sm6375_gdscs), 3863 }; 3864 3865 static const struct of_device_id gcc_sm6375_match_table[] = { 3866 { .compatible = "qcom,sm6375-gcc" }, 3867 { } 3868 }; 3869 MODULE_DEVICE_TABLE(of, gcc_sm6375_match_table); 3870 3871 static int gcc_sm6375_probe(struct platform_device *pdev) 3872 { 3873 struct regmap *regmap; 3874 int ret; 3875 3876 regmap = qcom_cc_map(pdev, &gcc_sm6375_desc); 3877 if (IS_ERR(regmap)) 3878 return PTR_ERR(regmap); 3879 3880 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); 3881 if (ret) 3882 return ret; 3883 3884 /* 3885 * Keep the following clocks always on: 3886 * GCC_CAMERA_XO_CLK, GCC_CPUSS_GNOC_CLK, GCC_DISP_XO_CLK 3887 */ 3888 regmap_update_bits(regmap, 0x17028, BIT(0), BIT(0)); 3889 regmap_update_bits(regmap, 0x2b004, BIT(0), BIT(0)); 3890 regmap_update_bits(regmap, 0x1702c, BIT(0), BIT(0)); 3891 3892 clk_lucid_pll_configure(&gpll10, regmap, &gpll10_config); 3893 clk_lucid_pll_configure(&gpll11, regmap, &gpll11_config); 3894 clk_lucid_pll_configure(&gpll8, regmap, &gpll8_config); 3895 clk_zonda_pll_configure(&gpll9, regmap, &gpll9_config); 3896 3897 return qcom_cc_really_probe(pdev, &gcc_sm6375_desc, regmap); 3898 } 3899 3900 static struct platform_driver gcc_sm6375_driver = { 3901 .probe = gcc_sm6375_probe, 3902 .driver = { 3903 .name = "gcc-sm6375", 3904 .of_match_table = gcc_sm6375_match_table, 3905 }, 3906 }; 3907 3908 static int __init gcc_sm6375_init(void) 3909 { 3910 return platform_driver_register(&gcc_sm6375_driver); 3911 } 3912 subsys_initcall(gcc_sm6375_init); 3913 3914 static void __exit gcc_sm6375_exit(void) 3915 { 3916 platform_driver_unregister(&gcc_sm6375_driver); 3917 } 3918 module_exit(gcc_sm6375_exit); 3919 3920 MODULE_DESCRIPTION("QTI GCC SM6375 Driver"); 3921 MODULE_LICENSE("GPL"); 3922