1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/bitops.h> 8 #include <linux/err.h> 9 #include <linux/platform_device.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/clk-provider.h> 14 #include <linux/regmap.h> 15 #include <linux/reset-controller.h> 16 17 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 18 19 #include "common.h" 20 #include "clk-regmap.h" 21 #include "clk-pll.h" 22 #include "clk-rcg.h" 23 #include "clk-branch.h" 24 #include "clk-alpha-pll.h" 25 #include "gdsc.h" 26 #include "reset.h" 27 28 enum { 29 P_BI_TCXO, 30 P_AUD_REF_CLK, 31 P_CORE_BI_PLL_TEST_SE, 32 P_GPLL0_OUT_EVEN, 33 P_GPLL0_OUT_MAIN, 34 P_GPLL4_OUT_MAIN, 35 P_SLEEP_CLK, 36 }; 37 38 static const struct parent_map gcc_parent_map_0[] = { 39 { P_BI_TCXO, 0 }, 40 { P_GPLL0_OUT_MAIN, 1 }, 41 { P_GPLL0_OUT_EVEN, 6 }, 42 { P_CORE_BI_PLL_TEST_SE, 7 }, 43 }; 44 45 static const char * const gcc_parent_names_0[] = { 46 "bi_tcxo", 47 "gpll0", 48 "gpll0_out_even", 49 "core_bi_pll_test_se", 50 }; 51 52 static const struct parent_map gcc_parent_map_1[] = { 53 { P_BI_TCXO, 0 }, 54 { P_GPLL0_OUT_MAIN, 1 }, 55 { P_SLEEP_CLK, 5 }, 56 { P_GPLL0_OUT_EVEN, 6 }, 57 { P_CORE_BI_PLL_TEST_SE, 7 }, 58 }; 59 60 static const char * const gcc_parent_names_1[] = { 61 "bi_tcxo", 62 "gpll0", 63 "core_pi_sleep_clk", 64 "gpll0_out_even", 65 "core_bi_pll_test_se", 66 }; 67 68 static const struct parent_map gcc_parent_map_2[] = { 69 { P_BI_TCXO, 0 }, 70 { P_SLEEP_CLK, 5 }, 71 { P_CORE_BI_PLL_TEST_SE, 7 }, 72 }; 73 74 static const char * const gcc_parent_names_2[] = { 75 "bi_tcxo", 76 "core_pi_sleep_clk", 77 "core_bi_pll_test_se", 78 }; 79 80 static const struct parent_map gcc_parent_map_3[] = { 81 { P_BI_TCXO, 0 }, 82 { P_GPLL0_OUT_MAIN, 1 }, 83 { P_CORE_BI_PLL_TEST_SE, 7 }, 84 }; 85 86 static const char * const gcc_parent_names_3[] = { 87 "bi_tcxo", 88 "gpll0", 89 "core_bi_pll_test_se", 90 }; 91 92 static const struct parent_map gcc_parent_map_4[] = { 93 { P_BI_TCXO, 0 }, 94 { P_CORE_BI_PLL_TEST_SE, 7 }, 95 }; 96 97 static const char * const gcc_parent_names_4[] = { 98 "bi_tcxo", 99 "core_bi_pll_test_se", 100 }; 101 102 static const struct parent_map gcc_parent_map_6[] = { 103 { P_BI_TCXO, 0 }, 104 { P_GPLL0_OUT_MAIN, 1 }, 105 { P_AUD_REF_CLK, 2 }, 106 { P_GPLL0_OUT_EVEN, 6 }, 107 { P_CORE_BI_PLL_TEST_SE, 7 }, 108 }; 109 110 static const char * const gcc_parent_names_6[] = { 111 "bi_tcxo", 112 "gpll0", 113 "aud_ref_clk", 114 "gpll0_out_even", 115 "core_bi_pll_test_se", 116 }; 117 118 static const char * const gcc_parent_names_7[] = { 119 "bi_tcxo", 120 "gpll0", 121 "gpll0_out_even", 122 "core_bi_pll_test_se", 123 }; 124 125 static const char * const gcc_parent_names_8[] = { 126 "bi_tcxo", 127 "gpll0", 128 "core_bi_pll_test_se", 129 }; 130 131 static const struct parent_map gcc_parent_map_10[] = { 132 { P_BI_TCXO, 0 }, 133 { P_GPLL0_OUT_MAIN, 1 }, 134 { P_GPLL4_OUT_MAIN, 5 }, 135 { P_GPLL0_OUT_EVEN, 6 }, 136 { P_CORE_BI_PLL_TEST_SE, 7 }, 137 }; 138 139 static const char * const gcc_parent_names_10[] = { 140 "bi_tcxo", 141 "gpll0", 142 "gpll4", 143 "gpll0_out_even", 144 "core_bi_pll_test_se", 145 }; 146 147 static struct clk_alpha_pll gpll0 = { 148 .offset = 0x0, 149 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 150 .clkr = { 151 .enable_reg = 0x52000, 152 .enable_mask = BIT(0), 153 .hw.init = &(struct clk_init_data){ 154 .name = "gpll0", 155 .parent_names = (const char *[]){ "bi_tcxo" }, 156 .num_parents = 1, 157 .ops = &clk_alpha_pll_fixed_fabia_ops, 158 }, 159 }, 160 }; 161 162 static struct clk_alpha_pll gpll4 = { 163 .offset = 0x76000, 164 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 165 .clkr = { 166 .enable_reg = 0x52000, 167 .enable_mask = BIT(4), 168 .hw.init = &(struct clk_init_data){ 169 .name = "gpll4", 170 .parent_names = (const char *[]){ "bi_tcxo" }, 171 .num_parents = 1, 172 .ops = &clk_alpha_pll_fixed_fabia_ops, 173 }, 174 }, 175 }; 176 177 static const struct clk_div_table post_div_table_fabia_even[] = { 178 { 0x0, 1 }, 179 { 0x1, 2 }, 180 { 0x3, 4 }, 181 { 0x7, 8 }, 182 { } 183 }; 184 185 static struct clk_alpha_pll_postdiv gpll0_out_even = { 186 .offset = 0x0, 187 .post_div_shift = 8, 188 .post_div_table = post_div_table_fabia_even, 189 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 190 .width = 4, 191 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 192 .clkr.hw.init = &(struct clk_init_data){ 193 .name = "gpll0_out_even", 194 .parent_names = (const char *[]){ "gpll0" }, 195 .num_parents = 1, 196 .ops = &clk_alpha_pll_postdiv_fabia_ops, 197 }, 198 }; 199 200 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { 201 F(19200000, P_BI_TCXO, 1, 0, 0), 202 { } 203 }; 204 205 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { 206 .cmd_rcgr = 0x48014, 207 .mnd_width = 0, 208 .hid_width = 5, 209 .parent_map = gcc_parent_map_0, 210 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, 211 .clkr.hw.init = &(struct clk_init_data){ 212 .name = "gcc_cpuss_ahb_clk_src", 213 .parent_names = gcc_parent_names_7, 214 .num_parents = 4, 215 .ops = &clk_rcg2_ops, 216 }, 217 }; 218 219 static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = { 220 F(19200000, P_BI_TCXO, 1, 0, 0), 221 { } 222 }; 223 224 static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = { 225 .cmd_rcgr = 0x4815c, 226 .mnd_width = 0, 227 .hid_width = 5, 228 .parent_map = gcc_parent_map_3, 229 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, 230 .clkr.hw.init = &(struct clk_init_data){ 231 .name = "gcc_cpuss_rbcpr_clk_src", 232 .parent_names = gcc_parent_names_8, 233 .num_parents = 3, 234 .ops = &clk_rcg2_ops, 235 }, 236 }; 237 238 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 239 F(19200000, P_BI_TCXO, 1, 0, 0), 240 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 241 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 242 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 243 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 244 { } 245 }; 246 247 static struct clk_rcg2 gcc_gp1_clk_src = { 248 .cmd_rcgr = 0x64004, 249 .mnd_width = 8, 250 .hid_width = 5, 251 .parent_map = gcc_parent_map_1, 252 .freq_tbl = ftbl_gcc_gp1_clk_src, 253 .clkr.hw.init = &(struct clk_init_data){ 254 .name = "gcc_gp1_clk_src", 255 .parent_names = gcc_parent_names_1, 256 .num_parents = 5, 257 .ops = &clk_rcg2_ops, 258 }, 259 }; 260 261 static struct clk_rcg2 gcc_gp2_clk_src = { 262 .cmd_rcgr = 0x65004, 263 .mnd_width = 8, 264 .hid_width = 5, 265 .parent_map = gcc_parent_map_1, 266 .freq_tbl = ftbl_gcc_gp1_clk_src, 267 .clkr.hw.init = &(struct clk_init_data){ 268 .name = "gcc_gp2_clk_src", 269 .parent_names = gcc_parent_names_1, 270 .num_parents = 5, 271 .ops = &clk_rcg2_ops, 272 }, 273 }; 274 275 static struct clk_rcg2 gcc_gp3_clk_src = { 276 .cmd_rcgr = 0x66004, 277 .mnd_width = 8, 278 .hid_width = 5, 279 .parent_map = gcc_parent_map_1, 280 .freq_tbl = ftbl_gcc_gp1_clk_src, 281 .clkr.hw.init = &(struct clk_init_data){ 282 .name = "gcc_gp3_clk_src", 283 .parent_names = gcc_parent_names_1, 284 .num_parents = 5, 285 .ops = &clk_rcg2_ops, 286 }, 287 }; 288 289 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 290 F(9600000, P_BI_TCXO, 2, 0, 0), 291 F(19200000, P_BI_TCXO, 1, 0, 0), 292 { } 293 }; 294 295 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 296 .cmd_rcgr = 0x6b028, 297 .mnd_width = 16, 298 .hid_width = 5, 299 .parent_map = gcc_parent_map_2, 300 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 301 .clkr.hw.init = &(struct clk_init_data){ 302 .name = "gcc_pcie_0_aux_clk_src", 303 .parent_names = gcc_parent_names_2, 304 .num_parents = 3, 305 .ops = &clk_rcg2_ops, 306 }, 307 }; 308 309 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 310 .cmd_rcgr = 0x8d028, 311 .mnd_width = 16, 312 .hid_width = 5, 313 .parent_map = gcc_parent_map_2, 314 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 315 .clkr.hw.init = &(struct clk_init_data){ 316 .name = "gcc_pcie_1_aux_clk_src", 317 .parent_names = gcc_parent_names_2, 318 .num_parents = 3, 319 .ops = &clk_rcg2_ops, 320 }, 321 }; 322 323 static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = { 324 F(19200000, P_BI_TCXO, 1, 0, 0), 325 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 326 { } 327 }; 328 329 static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { 330 .cmd_rcgr = 0x6f014, 331 .mnd_width = 0, 332 .hid_width = 5, 333 .parent_map = gcc_parent_map_0, 334 .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, 335 .clkr.hw.init = &(struct clk_init_data){ 336 .name = "gcc_pcie_phy_refgen_clk_src", 337 .parent_names = gcc_parent_names_0, 338 .num_parents = 4, 339 .ops = &clk_rcg2_ops, 340 }, 341 }; 342 343 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = { 344 F(19200000, P_BI_TCXO, 1, 0, 0), 345 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 346 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 347 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 348 { } 349 }; 350 351 static struct clk_rcg2 gcc_qspi_core_clk_src = { 352 .cmd_rcgr = 0x4b008, 353 .mnd_width = 0, 354 .hid_width = 5, 355 .parent_map = gcc_parent_map_0, 356 .freq_tbl = ftbl_gcc_qspi_core_clk_src, 357 .clkr.hw.init = &(struct clk_init_data){ 358 .name = "gcc_qspi_core_clk_src", 359 .parent_names = gcc_parent_names_0, 360 .num_parents = 4, 361 .ops = &clk_rcg2_floor_ops, 362 }, 363 }; 364 365 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 366 F(9600000, P_BI_TCXO, 2, 0, 0), 367 F(19200000, P_BI_TCXO, 1, 0, 0), 368 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 369 { } 370 }; 371 372 static struct clk_rcg2 gcc_pdm2_clk_src = { 373 .cmd_rcgr = 0x33010, 374 .mnd_width = 0, 375 .hid_width = 5, 376 .parent_map = gcc_parent_map_0, 377 .freq_tbl = ftbl_gcc_pdm2_clk_src, 378 .clkr.hw.init = &(struct clk_init_data){ 379 .name = "gcc_pdm2_clk_src", 380 .parent_names = gcc_parent_names_0, 381 .num_parents = 4, 382 .ops = &clk_rcg2_ops, 383 }, 384 }; 385 386 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 387 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), 388 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), 389 F(19200000, P_BI_TCXO, 1, 0, 0), 390 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), 391 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), 392 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), 393 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), 394 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), 395 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), 396 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 397 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), 398 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), 399 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), 400 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), 401 F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75), 402 { } 403 }; 404 405 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_init = { 406 .name = "gcc_qupv3_wrap0_s0_clk_src", 407 .parent_names = gcc_parent_names_0, 408 .num_parents = 4, 409 .ops = &clk_rcg2_shared_ops, 410 }; 411 412 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 413 .cmd_rcgr = 0x17034, 414 .mnd_width = 16, 415 .hid_width = 5, 416 .parent_map = gcc_parent_map_0, 417 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 418 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_init, 419 }; 420 421 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_init = { 422 .name = "gcc_qupv3_wrap0_s1_clk_src", 423 .parent_names = gcc_parent_names_0, 424 .num_parents = 4, 425 .ops = &clk_rcg2_shared_ops, 426 }; 427 428 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 429 .cmd_rcgr = 0x17164, 430 .mnd_width = 16, 431 .hid_width = 5, 432 .parent_map = gcc_parent_map_0, 433 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 434 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_init, 435 }; 436 437 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_init = { 438 .name = "gcc_qupv3_wrap0_s2_clk_src", 439 .parent_names = gcc_parent_names_0, 440 .num_parents = 4, 441 .ops = &clk_rcg2_shared_ops, 442 }; 443 444 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 445 .cmd_rcgr = 0x17294, 446 .mnd_width = 16, 447 .hid_width = 5, 448 .parent_map = gcc_parent_map_0, 449 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 450 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_init, 451 }; 452 453 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_init = { 454 .name = "gcc_qupv3_wrap0_s3_clk_src", 455 .parent_names = gcc_parent_names_0, 456 .num_parents = 4, 457 .ops = &clk_rcg2_shared_ops, 458 }; 459 460 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 461 .cmd_rcgr = 0x173c4, 462 .mnd_width = 16, 463 .hid_width = 5, 464 .parent_map = gcc_parent_map_0, 465 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 466 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_init, 467 }; 468 469 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_init = { 470 .name = "gcc_qupv3_wrap0_s4_clk_src", 471 .parent_names = gcc_parent_names_0, 472 .num_parents = 4, 473 .ops = &clk_rcg2_shared_ops, 474 }; 475 476 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 477 .cmd_rcgr = 0x174f4, 478 .mnd_width = 16, 479 .hid_width = 5, 480 .parent_map = gcc_parent_map_0, 481 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 482 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_init, 483 }; 484 485 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_init = { 486 .name = "gcc_qupv3_wrap0_s5_clk_src", 487 .parent_names = gcc_parent_names_0, 488 .num_parents = 4, 489 .ops = &clk_rcg2_shared_ops, 490 }; 491 492 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 493 .cmd_rcgr = 0x17624, 494 .mnd_width = 16, 495 .hid_width = 5, 496 .parent_map = gcc_parent_map_0, 497 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 498 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_init, 499 }; 500 501 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_init = { 502 .name = "gcc_qupv3_wrap0_s6_clk_src", 503 .parent_names = gcc_parent_names_0, 504 .num_parents = 4, 505 .ops = &clk_rcg2_shared_ops, 506 }; 507 508 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 509 .cmd_rcgr = 0x17754, 510 .mnd_width = 16, 511 .hid_width = 5, 512 .parent_map = gcc_parent_map_0, 513 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 514 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_init, 515 }; 516 517 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_init = { 518 .name = "gcc_qupv3_wrap0_s7_clk_src", 519 .parent_names = gcc_parent_names_0, 520 .num_parents = 4, 521 .ops = &clk_rcg2_shared_ops, 522 }; 523 524 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 525 .cmd_rcgr = 0x17884, 526 .mnd_width = 16, 527 .hid_width = 5, 528 .parent_map = gcc_parent_map_0, 529 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 530 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_init, 531 }; 532 533 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_init = { 534 .name = "gcc_qupv3_wrap1_s0_clk_src", 535 .parent_names = gcc_parent_names_0, 536 .num_parents = 4, 537 .ops = &clk_rcg2_shared_ops, 538 }; 539 540 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 541 .cmd_rcgr = 0x18018, 542 .mnd_width = 16, 543 .hid_width = 5, 544 .parent_map = gcc_parent_map_0, 545 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 546 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_init, 547 }; 548 549 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_init = { 550 .name = "gcc_qupv3_wrap1_s1_clk_src", 551 .parent_names = gcc_parent_names_0, 552 .num_parents = 4, 553 .ops = &clk_rcg2_shared_ops, 554 }; 555 556 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 557 .cmd_rcgr = 0x18148, 558 .mnd_width = 16, 559 .hid_width = 5, 560 .parent_map = gcc_parent_map_0, 561 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 562 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_init, 563 }; 564 565 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_init = { 566 .name = "gcc_qupv3_wrap1_s2_clk_src", 567 .parent_names = gcc_parent_names_0, 568 .num_parents = 4, 569 .ops = &clk_rcg2_shared_ops, 570 }; 571 572 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 573 .cmd_rcgr = 0x18278, 574 .mnd_width = 16, 575 .hid_width = 5, 576 .parent_map = gcc_parent_map_0, 577 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 578 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_init, 579 }; 580 581 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_init = { 582 .name = "gcc_qupv3_wrap1_s3_clk_src", 583 .parent_names = gcc_parent_names_0, 584 .num_parents = 4, 585 .ops = &clk_rcg2_shared_ops, 586 }; 587 588 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 589 .cmd_rcgr = 0x183a8, 590 .mnd_width = 16, 591 .hid_width = 5, 592 .parent_map = gcc_parent_map_0, 593 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 594 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_init, 595 }; 596 597 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_init = { 598 .name = "gcc_qupv3_wrap1_s4_clk_src", 599 .parent_names = gcc_parent_names_0, 600 .num_parents = 4, 601 .ops = &clk_rcg2_shared_ops, 602 }; 603 604 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 605 .cmd_rcgr = 0x184d8, 606 .mnd_width = 16, 607 .hid_width = 5, 608 .parent_map = gcc_parent_map_0, 609 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 610 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_init, 611 }; 612 613 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_init = { 614 .name = "gcc_qupv3_wrap1_s5_clk_src", 615 .parent_names = gcc_parent_names_0, 616 .num_parents = 4, 617 .ops = &clk_rcg2_shared_ops, 618 }; 619 620 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 621 .cmd_rcgr = 0x18608, 622 .mnd_width = 16, 623 .hid_width = 5, 624 .parent_map = gcc_parent_map_0, 625 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 626 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_init, 627 }; 628 629 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_init = { 630 .name = "gcc_qupv3_wrap1_s6_clk_src", 631 .parent_names = gcc_parent_names_0, 632 .num_parents = 4, 633 .ops = &clk_rcg2_shared_ops, 634 }; 635 636 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 637 .cmd_rcgr = 0x18738, 638 .mnd_width = 16, 639 .hid_width = 5, 640 .parent_map = gcc_parent_map_0, 641 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 642 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_init, 643 }; 644 645 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_init = { 646 .name = "gcc_qupv3_wrap1_s7_clk_src", 647 .parent_names = gcc_parent_names_0, 648 .num_parents = 4, 649 .ops = &clk_rcg2_shared_ops, 650 }; 651 652 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 653 .cmd_rcgr = 0x18868, 654 .mnd_width = 16, 655 .hid_width = 5, 656 .parent_map = gcc_parent_map_0, 657 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 658 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_init, 659 }; 660 661 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 662 F(400000, P_BI_TCXO, 12, 1, 4), 663 F(9600000, P_BI_TCXO, 2, 0, 0), 664 F(19200000, P_BI_TCXO, 1, 0, 0), 665 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 666 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 667 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 668 F(201500000, P_GPLL4_OUT_MAIN, 4, 0, 0), 669 { } 670 }; 671 672 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 673 .cmd_rcgr = 0x1400c, 674 .mnd_width = 8, 675 .hid_width = 5, 676 .parent_map = gcc_parent_map_10, 677 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 678 .clkr.hw.init = &(struct clk_init_data){ 679 .name = "gcc_sdcc2_apps_clk_src", 680 .parent_names = gcc_parent_names_10, 681 .num_parents = 5, 682 .ops = &clk_rcg2_ops, 683 }, 684 }; 685 686 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 687 F(400000, P_BI_TCXO, 12, 1, 4), 688 F(9600000, P_BI_TCXO, 2, 0, 0), 689 F(19200000, P_BI_TCXO, 1, 0, 0), 690 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 691 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 692 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 693 { } 694 }; 695 696 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 697 .cmd_rcgr = 0x1600c, 698 .mnd_width = 8, 699 .hid_width = 5, 700 .parent_map = gcc_parent_map_0, 701 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 702 .clkr.hw.init = &(struct clk_init_data){ 703 .name = "gcc_sdcc4_apps_clk_src", 704 .parent_names = gcc_parent_names_0, 705 .num_parents = 4, 706 .ops = &clk_rcg2_ops, 707 }, 708 }; 709 710 static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = { 711 F(105495, P_BI_TCXO, 2, 1, 91), 712 { } 713 }; 714 715 static struct clk_rcg2 gcc_tsif_ref_clk_src = { 716 .cmd_rcgr = 0x36010, 717 .mnd_width = 8, 718 .hid_width = 5, 719 .parent_map = gcc_parent_map_6, 720 .freq_tbl = ftbl_gcc_tsif_ref_clk_src, 721 .clkr.hw.init = &(struct clk_init_data){ 722 .name = "gcc_tsif_ref_clk_src", 723 .parent_names = gcc_parent_names_6, 724 .num_parents = 5, 725 .ops = &clk_rcg2_ops, 726 }, 727 }; 728 729 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { 730 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 731 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 732 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 733 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 734 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 735 { } 736 }; 737 738 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { 739 .cmd_rcgr = 0x7501c, 740 .mnd_width = 8, 741 .hid_width = 5, 742 .parent_map = gcc_parent_map_0, 743 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, 744 .clkr.hw.init = &(struct clk_init_data){ 745 .name = "gcc_ufs_card_axi_clk_src", 746 .parent_names = gcc_parent_names_0, 747 .num_parents = 4, 748 .ops = &clk_rcg2_shared_ops, 749 }, 750 }; 751 752 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { 753 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 754 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 755 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 756 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 757 { } 758 }; 759 760 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { 761 .cmd_rcgr = 0x7505c, 762 .mnd_width = 0, 763 .hid_width = 5, 764 .parent_map = gcc_parent_map_0, 765 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 766 .clkr.hw.init = &(struct clk_init_data){ 767 .name = "gcc_ufs_card_ice_core_clk_src", 768 .parent_names = gcc_parent_names_0, 769 .num_parents = 4, 770 .ops = &clk_rcg2_shared_ops, 771 }, 772 }; 773 774 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { 775 .cmd_rcgr = 0x75090, 776 .mnd_width = 0, 777 .hid_width = 5, 778 .parent_map = gcc_parent_map_4, 779 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, 780 .clkr.hw.init = &(struct clk_init_data){ 781 .name = "gcc_ufs_card_phy_aux_clk_src", 782 .parent_names = gcc_parent_names_4, 783 .num_parents = 2, 784 .ops = &clk_rcg2_ops, 785 }, 786 }; 787 788 static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = { 789 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 790 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 791 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 792 { } 793 }; 794 795 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { 796 .cmd_rcgr = 0x75074, 797 .mnd_width = 0, 798 .hid_width = 5, 799 .parent_map = gcc_parent_map_0, 800 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, 801 .clkr.hw.init = &(struct clk_init_data){ 802 .name = "gcc_ufs_card_unipro_core_clk_src", 803 .parent_names = gcc_parent_names_0, 804 .num_parents = 4, 805 .ops = &clk_rcg2_shared_ops, 806 }, 807 }; 808 809 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 810 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 811 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 812 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 813 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 814 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 815 { } 816 }; 817 818 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 819 .cmd_rcgr = 0x7701c, 820 .mnd_width = 8, 821 .hid_width = 5, 822 .parent_map = gcc_parent_map_0, 823 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 824 .clkr.hw.init = &(struct clk_init_data){ 825 .name = "gcc_ufs_phy_axi_clk_src", 826 .parent_names = gcc_parent_names_0, 827 .num_parents = 4, 828 .ops = &clk_rcg2_shared_ops, 829 }, 830 }; 831 832 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 833 .cmd_rcgr = 0x7705c, 834 .mnd_width = 0, 835 .hid_width = 5, 836 .parent_map = gcc_parent_map_0, 837 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 838 .clkr.hw.init = &(struct clk_init_data){ 839 .name = "gcc_ufs_phy_ice_core_clk_src", 840 .parent_names = gcc_parent_names_0, 841 .num_parents = 4, 842 .ops = &clk_rcg2_shared_ops, 843 }, 844 }; 845 846 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 847 .cmd_rcgr = 0x77090, 848 .mnd_width = 0, 849 .hid_width = 5, 850 .parent_map = gcc_parent_map_4, 851 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 852 .clkr.hw.init = &(struct clk_init_data){ 853 .name = "gcc_ufs_phy_phy_aux_clk_src", 854 .parent_names = gcc_parent_names_4, 855 .num_parents = 2, 856 .ops = &clk_rcg2_shared_ops, 857 }, 858 }; 859 860 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 861 .cmd_rcgr = 0x77074, 862 .mnd_width = 0, 863 .hid_width = 5, 864 .parent_map = gcc_parent_map_0, 865 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, 866 .clkr.hw.init = &(struct clk_init_data){ 867 .name = "gcc_ufs_phy_unipro_core_clk_src", 868 .parent_names = gcc_parent_names_0, 869 .num_parents = 4, 870 .ops = &clk_rcg2_shared_ops, 871 }, 872 }; 873 874 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 875 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), 876 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), 877 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 878 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 879 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 880 { } 881 }; 882 883 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 884 .cmd_rcgr = 0xf018, 885 .mnd_width = 8, 886 .hid_width = 5, 887 .parent_map = gcc_parent_map_0, 888 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 889 .clkr.hw.init = &(struct clk_init_data){ 890 .name = "gcc_usb30_prim_master_clk_src", 891 .parent_names = gcc_parent_names_0, 892 .num_parents = 4, 893 .ops = &clk_rcg2_shared_ops, 894 }, 895 }; 896 897 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 898 F(19200000, P_BI_TCXO, 1, 0, 0), 899 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0), 900 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0), 901 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 902 { } 903 }; 904 905 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 906 .cmd_rcgr = 0xf030, 907 .mnd_width = 0, 908 .hid_width = 5, 909 .parent_map = gcc_parent_map_0, 910 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 911 .clkr.hw.init = &(struct clk_init_data){ 912 .name = "gcc_usb30_prim_mock_utmi_clk_src", 913 .parent_names = gcc_parent_names_0, 914 .num_parents = 4, 915 .ops = &clk_rcg2_shared_ops, 916 }, 917 }; 918 919 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { 920 .cmd_rcgr = 0x10018, 921 .mnd_width = 8, 922 .hid_width = 5, 923 .parent_map = gcc_parent_map_0, 924 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 925 .clkr.hw.init = &(struct clk_init_data){ 926 .name = "gcc_usb30_sec_master_clk_src", 927 .parent_names = gcc_parent_names_0, 928 .num_parents = 4, 929 .ops = &clk_rcg2_ops, 930 }, 931 }; 932 933 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { 934 .cmd_rcgr = 0x10030, 935 .mnd_width = 0, 936 .hid_width = 5, 937 .parent_map = gcc_parent_map_0, 938 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 939 .clkr.hw.init = &(struct clk_init_data){ 940 .name = "gcc_usb30_sec_mock_utmi_clk_src", 941 .parent_names = gcc_parent_names_0, 942 .num_parents = 4, 943 .ops = &clk_rcg2_ops, 944 }, 945 }; 946 947 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 948 .cmd_rcgr = 0xf05c, 949 .mnd_width = 0, 950 .hid_width = 5, 951 .parent_map = gcc_parent_map_2, 952 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, 953 .clkr.hw.init = &(struct clk_init_data){ 954 .name = "gcc_usb3_prim_phy_aux_clk_src", 955 .parent_names = gcc_parent_names_2, 956 .num_parents = 3, 957 .ops = &clk_rcg2_ops, 958 }, 959 }; 960 961 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { 962 .cmd_rcgr = 0x1005c, 963 .mnd_width = 0, 964 .hid_width = 5, 965 .parent_map = gcc_parent_map_2, 966 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, 967 .clkr.hw.init = &(struct clk_init_data){ 968 .name = "gcc_usb3_sec_phy_aux_clk_src", 969 .parent_names = gcc_parent_names_2, 970 .num_parents = 3, 971 .ops = &clk_rcg2_shared_ops, 972 }, 973 }; 974 975 static struct clk_rcg2 gcc_vs_ctrl_clk_src = { 976 .cmd_rcgr = 0x7a030, 977 .mnd_width = 0, 978 .hid_width = 5, 979 .parent_map = gcc_parent_map_3, 980 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, 981 .clkr.hw.init = &(struct clk_init_data){ 982 .name = "gcc_vs_ctrl_clk_src", 983 .parent_names = gcc_parent_names_3, 984 .num_parents = 3, 985 .ops = &clk_rcg2_ops, 986 }, 987 }; 988 989 static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = { 990 F(19200000, P_BI_TCXO, 1, 0, 0), 991 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 992 F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0), 993 { } 994 }; 995 996 static struct clk_rcg2 gcc_vsensor_clk_src = { 997 .cmd_rcgr = 0x7a018, 998 .mnd_width = 0, 999 .hid_width = 5, 1000 .parent_map = gcc_parent_map_3, 1001 .freq_tbl = ftbl_gcc_vsensor_clk_src, 1002 .clkr.hw.init = &(struct clk_init_data){ 1003 .name = "gcc_vsensor_clk_src", 1004 .parent_names = gcc_parent_names_8, 1005 .num_parents = 3, 1006 .ops = &clk_rcg2_ops, 1007 }, 1008 }; 1009 1010 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { 1011 .halt_reg = 0x90014, 1012 .halt_check = BRANCH_HALT, 1013 .clkr = { 1014 .enable_reg = 0x90014, 1015 .enable_mask = BIT(0), 1016 .hw.init = &(struct clk_init_data){ 1017 .name = "gcc_aggre_noc_pcie_tbu_clk", 1018 .ops = &clk_branch2_ops, 1019 }, 1020 }, 1021 }; 1022 1023 static struct clk_branch gcc_aggre_ufs_card_axi_clk = { 1024 .halt_reg = 0x82028, 1025 .halt_check = BRANCH_HALT, 1026 .hwcg_reg = 0x82028, 1027 .hwcg_bit = 1, 1028 .clkr = { 1029 .enable_reg = 0x82028, 1030 .enable_mask = BIT(0), 1031 .hw.init = &(struct clk_init_data){ 1032 .name = "gcc_aggre_ufs_card_axi_clk", 1033 .parent_names = (const char *[]){ 1034 "gcc_ufs_card_axi_clk_src", 1035 }, 1036 .num_parents = 1, 1037 .flags = CLK_SET_RATE_PARENT, 1038 .ops = &clk_branch2_ops, 1039 }, 1040 }, 1041 }; 1042 1043 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1044 .halt_reg = 0x82024, 1045 .halt_check = BRANCH_HALT, 1046 .hwcg_reg = 0x82024, 1047 .hwcg_bit = 1, 1048 .clkr = { 1049 .enable_reg = 0x82024, 1050 .enable_mask = BIT(0), 1051 .hw.init = &(struct clk_init_data){ 1052 .name = "gcc_aggre_ufs_phy_axi_clk", 1053 .parent_names = (const char *[]){ 1054 "gcc_ufs_phy_axi_clk_src", 1055 }, 1056 .num_parents = 1, 1057 .flags = CLK_SET_RATE_PARENT, 1058 .ops = &clk_branch2_ops, 1059 }, 1060 }, 1061 }; 1062 1063 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1064 .halt_reg = 0x8201c, 1065 .halt_check = BRANCH_HALT, 1066 .clkr = { 1067 .enable_reg = 0x8201c, 1068 .enable_mask = BIT(0), 1069 .hw.init = &(struct clk_init_data){ 1070 .name = "gcc_aggre_usb3_prim_axi_clk", 1071 .parent_names = (const char *[]){ 1072 "gcc_usb30_prim_master_clk_src", 1073 }, 1074 .num_parents = 1, 1075 .flags = CLK_SET_RATE_PARENT, 1076 .ops = &clk_branch2_ops, 1077 }, 1078 }, 1079 }; 1080 1081 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { 1082 .halt_reg = 0x82020, 1083 .halt_check = BRANCH_HALT, 1084 .clkr = { 1085 .enable_reg = 0x82020, 1086 .enable_mask = BIT(0), 1087 .hw.init = &(struct clk_init_data){ 1088 .name = "gcc_aggre_usb3_sec_axi_clk", 1089 .parent_names = (const char *[]){ 1090 "gcc_usb30_sec_master_clk_src", 1091 }, 1092 .num_parents = 1, 1093 .flags = CLK_SET_RATE_PARENT, 1094 .ops = &clk_branch2_ops, 1095 }, 1096 }, 1097 }; 1098 1099 static struct clk_branch gcc_apc_vs_clk = { 1100 .halt_reg = 0x7a050, 1101 .halt_check = BRANCH_HALT, 1102 .clkr = { 1103 .enable_reg = 0x7a050, 1104 .enable_mask = BIT(0), 1105 .hw.init = &(struct clk_init_data){ 1106 .name = "gcc_apc_vs_clk", 1107 .parent_names = (const char *[]){ 1108 "gcc_vsensor_clk_src", 1109 }, 1110 .num_parents = 1, 1111 .flags = CLK_SET_RATE_PARENT, 1112 .ops = &clk_branch2_ops, 1113 }, 1114 }, 1115 }; 1116 1117 static struct clk_branch gcc_boot_rom_ahb_clk = { 1118 .halt_reg = 0x38004, 1119 .halt_check = BRANCH_HALT_VOTED, 1120 .hwcg_reg = 0x38004, 1121 .hwcg_bit = 1, 1122 .clkr = { 1123 .enable_reg = 0x52004, 1124 .enable_mask = BIT(10), 1125 .hw.init = &(struct clk_init_data){ 1126 .name = "gcc_boot_rom_ahb_clk", 1127 .ops = &clk_branch2_ops, 1128 }, 1129 }, 1130 }; 1131 1132 static struct clk_branch gcc_camera_ahb_clk = { 1133 .halt_reg = 0xb008, 1134 .halt_check = BRANCH_HALT, 1135 .hwcg_reg = 0xb008, 1136 .hwcg_bit = 1, 1137 .clkr = { 1138 .enable_reg = 0xb008, 1139 .enable_mask = BIT(0), 1140 .hw.init = &(struct clk_init_data){ 1141 .name = "gcc_camera_ahb_clk", 1142 .flags = CLK_IS_CRITICAL, 1143 .ops = &clk_branch2_ops, 1144 }, 1145 }, 1146 }; 1147 1148 static struct clk_branch gcc_camera_axi_clk = { 1149 .halt_reg = 0xb020, 1150 .halt_check = BRANCH_VOTED, 1151 .clkr = { 1152 .enable_reg = 0xb020, 1153 .enable_mask = BIT(0), 1154 .hw.init = &(struct clk_init_data){ 1155 .name = "gcc_camera_axi_clk", 1156 .ops = &clk_branch2_ops, 1157 }, 1158 }, 1159 }; 1160 1161 static struct clk_branch gcc_camera_xo_clk = { 1162 .halt_reg = 0xb02c, 1163 .halt_check = BRANCH_HALT, 1164 .clkr = { 1165 .enable_reg = 0xb02c, 1166 .enable_mask = BIT(0), 1167 .hw.init = &(struct clk_init_data){ 1168 .name = "gcc_camera_xo_clk", 1169 .flags = CLK_IS_CRITICAL, 1170 .ops = &clk_branch2_ops, 1171 }, 1172 }, 1173 }; 1174 1175 static struct clk_branch gcc_ce1_ahb_clk = { 1176 .halt_reg = 0x4100c, 1177 .halt_check = BRANCH_HALT_VOTED, 1178 .hwcg_reg = 0x4100c, 1179 .hwcg_bit = 1, 1180 .clkr = { 1181 .enable_reg = 0x52004, 1182 .enable_mask = BIT(3), 1183 .hw.init = &(struct clk_init_data){ 1184 .name = "gcc_ce1_ahb_clk", 1185 .ops = &clk_branch2_ops, 1186 }, 1187 }, 1188 }; 1189 1190 static struct clk_branch gcc_ce1_axi_clk = { 1191 .halt_reg = 0x41008, 1192 .halt_check = BRANCH_HALT_VOTED, 1193 .clkr = { 1194 .enable_reg = 0x52004, 1195 .enable_mask = BIT(4), 1196 .hw.init = &(struct clk_init_data){ 1197 .name = "gcc_ce1_axi_clk", 1198 .ops = &clk_branch2_ops, 1199 }, 1200 }, 1201 }; 1202 1203 static struct clk_branch gcc_ce1_clk = { 1204 .halt_reg = 0x41004, 1205 .halt_check = BRANCH_HALT_VOTED, 1206 .clkr = { 1207 .enable_reg = 0x52004, 1208 .enable_mask = BIT(5), 1209 .hw.init = &(struct clk_init_data){ 1210 .name = "gcc_ce1_clk", 1211 .ops = &clk_branch2_ops, 1212 }, 1213 }, 1214 }; 1215 1216 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1217 .halt_reg = 0x502c, 1218 .halt_check = BRANCH_HALT, 1219 .clkr = { 1220 .enable_reg = 0x502c, 1221 .enable_mask = BIT(0), 1222 .hw.init = &(struct clk_init_data){ 1223 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1224 .parent_names = (const char *[]){ 1225 "gcc_usb30_prim_master_clk_src", 1226 }, 1227 .num_parents = 1, 1228 .flags = CLK_SET_RATE_PARENT, 1229 .ops = &clk_branch2_ops, 1230 }, 1231 }, 1232 }; 1233 1234 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { 1235 .halt_reg = 0x5030, 1236 .halt_check = BRANCH_HALT, 1237 .clkr = { 1238 .enable_reg = 0x5030, 1239 .enable_mask = BIT(0), 1240 .hw.init = &(struct clk_init_data){ 1241 .name = "gcc_cfg_noc_usb3_sec_axi_clk", 1242 .parent_names = (const char *[]){ 1243 "gcc_usb30_sec_master_clk_src", 1244 }, 1245 .num_parents = 1, 1246 .flags = CLK_SET_RATE_PARENT, 1247 .ops = &clk_branch2_ops, 1248 }, 1249 }, 1250 }; 1251 1252 static struct clk_branch gcc_cpuss_ahb_clk = { 1253 .halt_reg = 0x48000, 1254 .halt_check = BRANCH_HALT_VOTED, 1255 .clkr = { 1256 .enable_reg = 0x52004, 1257 .enable_mask = BIT(21), 1258 .hw.init = &(struct clk_init_data){ 1259 .name = "gcc_cpuss_ahb_clk", 1260 .parent_names = (const char *[]){ 1261 "gcc_cpuss_ahb_clk_src", 1262 }, 1263 .num_parents = 1, 1264 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1265 .ops = &clk_branch2_ops, 1266 }, 1267 }, 1268 }; 1269 1270 static struct clk_branch gcc_cpuss_rbcpr_clk = { 1271 .halt_reg = 0x48008, 1272 .halt_check = BRANCH_HALT, 1273 .clkr = { 1274 .enable_reg = 0x48008, 1275 .enable_mask = BIT(0), 1276 .hw.init = &(struct clk_init_data){ 1277 .name = "gcc_cpuss_rbcpr_clk", 1278 .parent_names = (const char *[]){ 1279 "gcc_cpuss_rbcpr_clk_src", 1280 }, 1281 .num_parents = 1, 1282 .flags = CLK_SET_RATE_PARENT, 1283 .ops = &clk_branch2_ops, 1284 }, 1285 }, 1286 }; 1287 1288 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1289 .halt_reg = 0x44038, 1290 .halt_check = BRANCH_VOTED, 1291 .clkr = { 1292 .enable_reg = 0x44038, 1293 .enable_mask = BIT(0), 1294 .hw.init = &(struct clk_init_data){ 1295 .name = "gcc_ddrss_gpu_axi_clk", 1296 .ops = &clk_branch2_ops, 1297 }, 1298 }, 1299 }; 1300 1301 static struct clk_branch gcc_disp_ahb_clk = { 1302 .halt_reg = 0xb00c, 1303 .halt_check = BRANCH_HALT, 1304 .hwcg_reg = 0xb00c, 1305 .hwcg_bit = 1, 1306 .clkr = { 1307 .enable_reg = 0xb00c, 1308 .enable_mask = BIT(0), 1309 .hw.init = &(struct clk_init_data){ 1310 .name = "gcc_disp_ahb_clk", 1311 .flags = CLK_IS_CRITICAL, 1312 .ops = &clk_branch2_ops, 1313 }, 1314 }, 1315 }; 1316 1317 static struct clk_branch gcc_disp_axi_clk = { 1318 .halt_reg = 0xb024, 1319 .halt_check = BRANCH_VOTED, 1320 .clkr = { 1321 .enable_reg = 0xb024, 1322 .enable_mask = BIT(0), 1323 .hw.init = &(struct clk_init_data){ 1324 .name = "gcc_disp_axi_clk", 1325 .ops = &clk_branch2_ops, 1326 }, 1327 }, 1328 }; 1329 1330 static struct clk_branch gcc_disp_gpll0_clk_src = { 1331 .halt_check = BRANCH_HALT_DELAY, 1332 .clkr = { 1333 .enable_reg = 0x52004, 1334 .enable_mask = BIT(18), 1335 .hw.init = &(struct clk_init_data){ 1336 .name = "gcc_disp_gpll0_clk_src", 1337 .parent_names = (const char *[]){ 1338 "gpll0", 1339 }, 1340 .num_parents = 1, 1341 .ops = &clk_branch2_ops, 1342 }, 1343 }, 1344 }; 1345 1346 static struct clk_branch gcc_disp_gpll0_div_clk_src = { 1347 .halt_check = BRANCH_HALT_DELAY, 1348 .clkr = { 1349 .enable_reg = 0x52004, 1350 .enable_mask = BIT(19), 1351 .hw.init = &(struct clk_init_data){ 1352 .name = "gcc_disp_gpll0_div_clk_src", 1353 .parent_names = (const char *[]){ 1354 "gpll0_out_even", 1355 }, 1356 .num_parents = 1, 1357 .ops = &clk_branch2_ops, 1358 }, 1359 }, 1360 }; 1361 1362 static struct clk_branch gcc_disp_xo_clk = { 1363 .halt_reg = 0xb030, 1364 .halt_check = BRANCH_HALT, 1365 .clkr = { 1366 .enable_reg = 0xb030, 1367 .enable_mask = BIT(0), 1368 .hw.init = &(struct clk_init_data){ 1369 .name = "gcc_disp_xo_clk", 1370 .flags = CLK_IS_CRITICAL, 1371 .ops = &clk_branch2_ops, 1372 }, 1373 }, 1374 }; 1375 1376 static struct clk_branch gcc_gp1_clk = { 1377 .halt_reg = 0x64000, 1378 .halt_check = BRANCH_HALT, 1379 .clkr = { 1380 .enable_reg = 0x64000, 1381 .enable_mask = BIT(0), 1382 .hw.init = &(struct clk_init_data){ 1383 .name = "gcc_gp1_clk", 1384 .parent_names = (const char *[]){ 1385 "gcc_gp1_clk_src", 1386 }, 1387 .num_parents = 1, 1388 .flags = CLK_SET_RATE_PARENT, 1389 .ops = &clk_branch2_ops, 1390 }, 1391 }, 1392 }; 1393 1394 static struct clk_branch gcc_gp2_clk = { 1395 .halt_reg = 0x65000, 1396 .halt_check = BRANCH_HALT, 1397 .clkr = { 1398 .enable_reg = 0x65000, 1399 .enable_mask = BIT(0), 1400 .hw.init = &(struct clk_init_data){ 1401 .name = "gcc_gp2_clk", 1402 .parent_names = (const char *[]){ 1403 "gcc_gp2_clk_src", 1404 }, 1405 .num_parents = 1, 1406 .flags = CLK_SET_RATE_PARENT, 1407 .ops = &clk_branch2_ops, 1408 }, 1409 }, 1410 }; 1411 1412 static struct clk_branch gcc_gp3_clk = { 1413 .halt_reg = 0x66000, 1414 .halt_check = BRANCH_HALT, 1415 .clkr = { 1416 .enable_reg = 0x66000, 1417 .enable_mask = BIT(0), 1418 .hw.init = &(struct clk_init_data){ 1419 .name = "gcc_gp3_clk", 1420 .parent_names = (const char *[]){ 1421 "gcc_gp3_clk_src", 1422 }, 1423 .num_parents = 1, 1424 .flags = CLK_SET_RATE_PARENT, 1425 .ops = &clk_branch2_ops, 1426 }, 1427 }, 1428 }; 1429 1430 static struct clk_branch gcc_gpu_cfg_ahb_clk = { 1431 .halt_reg = 0x71004, 1432 .halt_check = BRANCH_HALT, 1433 .hwcg_reg = 0x71004, 1434 .hwcg_bit = 1, 1435 .clkr = { 1436 .enable_reg = 0x71004, 1437 .enable_mask = BIT(0), 1438 .hw.init = &(struct clk_init_data){ 1439 .name = "gcc_gpu_cfg_ahb_clk", 1440 .flags = CLK_IS_CRITICAL, 1441 .ops = &clk_branch2_ops, 1442 }, 1443 }, 1444 }; 1445 1446 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1447 .halt_check = BRANCH_HALT_DELAY, 1448 .clkr = { 1449 .enable_reg = 0x52004, 1450 .enable_mask = BIT(15), 1451 .hw.init = &(struct clk_init_data){ 1452 .name = "gcc_gpu_gpll0_clk_src", 1453 .parent_names = (const char *[]){ 1454 "gpll0", 1455 }, 1456 .num_parents = 1, 1457 .ops = &clk_branch2_ops, 1458 }, 1459 }, 1460 }; 1461 1462 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1463 .halt_check = BRANCH_HALT_DELAY, 1464 .clkr = { 1465 .enable_reg = 0x52004, 1466 .enable_mask = BIT(16), 1467 .hw.init = &(struct clk_init_data){ 1468 .name = "gcc_gpu_gpll0_div_clk_src", 1469 .parent_names = (const char *[]){ 1470 "gpll0_out_even", 1471 }, 1472 .num_parents = 1, 1473 .ops = &clk_branch2_ops, 1474 }, 1475 }, 1476 }; 1477 1478 static struct clk_branch gcc_gpu_iref_clk = { 1479 .halt_reg = 0x8c010, 1480 .halt_check = BRANCH_HALT, 1481 .clkr = { 1482 .enable_reg = 0x8c010, 1483 .enable_mask = BIT(0), 1484 .hw.init = &(struct clk_init_data){ 1485 .name = "gcc_gpu_iref_clk", 1486 .ops = &clk_branch2_ops, 1487 }, 1488 }, 1489 }; 1490 1491 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1492 .halt_reg = 0x7100c, 1493 .halt_check = BRANCH_VOTED, 1494 .clkr = { 1495 .enable_reg = 0x7100c, 1496 .enable_mask = BIT(0), 1497 .hw.init = &(struct clk_init_data){ 1498 .name = "gcc_gpu_memnoc_gfx_clk", 1499 .ops = &clk_branch2_ops, 1500 }, 1501 }, 1502 }; 1503 1504 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1505 .halt_reg = 0x71018, 1506 .halt_check = BRANCH_HALT, 1507 .clkr = { 1508 .enable_reg = 0x71018, 1509 .enable_mask = BIT(0), 1510 .hw.init = &(struct clk_init_data){ 1511 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1512 .ops = &clk_branch2_ops, 1513 }, 1514 }, 1515 }; 1516 1517 static struct clk_branch gcc_gpu_vs_clk = { 1518 .halt_reg = 0x7a04c, 1519 .halt_check = BRANCH_HALT, 1520 .clkr = { 1521 .enable_reg = 0x7a04c, 1522 .enable_mask = BIT(0), 1523 .hw.init = &(struct clk_init_data){ 1524 .name = "gcc_gpu_vs_clk", 1525 .parent_names = (const char *[]){ 1526 "gcc_vsensor_clk_src", 1527 }, 1528 .num_parents = 1, 1529 .flags = CLK_SET_RATE_PARENT, 1530 .ops = &clk_branch2_ops, 1531 }, 1532 }, 1533 }; 1534 1535 static struct clk_branch gcc_mss_axis2_clk = { 1536 .halt_reg = 0x8a008, 1537 .halt_check = BRANCH_HALT, 1538 .clkr = { 1539 .enable_reg = 0x8a008, 1540 .enable_mask = BIT(0), 1541 .hw.init = &(struct clk_init_data){ 1542 .name = "gcc_mss_axis2_clk", 1543 .ops = &clk_branch2_ops, 1544 }, 1545 }, 1546 }; 1547 1548 static struct clk_branch gcc_mss_cfg_ahb_clk = { 1549 .halt_reg = 0x8a000, 1550 .halt_check = BRANCH_HALT, 1551 .hwcg_reg = 0x8a000, 1552 .hwcg_bit = 1, 1553 .clkr = { 1554 .enable_reg = 0x8a000, 1555 .enable_mask = BIT(0), 1556 .hw.init = &(struct clk_init_data){ 1557 .name = "gcc_mss_cfg_ahb_clk", 1558 .ops = &clk_branch2_ops, 1559 }, 1560 }, 1561 }; 1562 1563 static struct clk_branch gcc_mss_gpll0_div_clk_src = { 1564 .halt_check = BRANCH_HALT_DELAY, 1565 .clkr = { 1566 .enable_reg = 0x52004, 1567 .enable_mask = BIT(17), 1568 .hw.init = &(struct clk_init_data){ 1569 .name = "gcc_mss_gpll0_div_clk_src", 1570 .ops = &clk_branch2_ops, 1571 }, 1572 }, 1573 }; 1574 1575 static struct clk_branch gcc_mss_mfab_axis_clk = { 1576 .halt_reg = 0x8a004, 1577 .halt_check = BRANCH_VOTED, 1578 .hwcg_reg = 0x8a004, 1579 .hwcg_bit = 1, 1580 .clkr = { 1581 .enable_reg = 0x8a004, 1582 .enable_mask = BIT(0), 1583 .hw.init = &(struct clk_init_data){ 1584 .name = "gcc_mss_mfab_axis_clk", 1585 .ops = &clk_branch2_ops, 1586 }, 1587 }, 1588 }; 1589 1590 static struct clk_branch gcc_mss_q6_memnoc_axi_clk = { 1591 .halt_reg = 0x8a154, 1592 .halt_check = BRANCH_VOTED, 1593 .clkr = { 1594 .enable_reg = 0x8a154, 1595 .enable_mask = BIT(0), 1596 .hw.init = &(struct clk_init_data){ 1597 .name = "gcc_mss_q6_memnoc_axi_clk", 1598 .ops = &clk_branch2_ops, 1599 }, 1600 }, 1601 }; 1602 1603 static struct clk_branch gcc_mss_snoc_axi_clk = { 1604 .halt_reg = 0x8a150, 1605 .halt_check = BRANCH_HALT, 1606 .clkr = { 1607 .enable_reg = 0x8a150, 1608 .enable_mask = BIT(0), 1609 .hw.init = &(struct clk_init_data){ 1610 .name = "gcc_mss_snoc_axi_clk", 1611 .ops = &clk_branch2_ops, 1612 }, 1613 }, 1614 }; 1615 1616 static struct clk_branch gcc_mss_vs_clk = { 1617 .halt_reg = 0x7a048, 1618 .halt_check = BRANCH_HALT, 1619 .clkr = { 1620 .enable_reg = 0x7a048, 1621 .enable_mask = BIT(0), 1622 .hw.init = &(struct clk_init_data){ 1623 .name = "gcc_mss_vs_clk", 1624 .parent_names = (const char *[]){ 1625 "gcc_vsensor_clk_src", 1626 }, 1627 .num_parents = 1, 1628 .flags = CLK_SET_RATE_PARENT, 1629 .ops = &clk_branch2_ops, 1630 }, 1631 }, 1632 }; 1633 1634 static struct clk_branch gcc_pcie_0_aux_clk = { 1635 .halt_reg = 0x6b01c, 1636 .halt_check = BRANCH_HALT_VOTED, 1637 .clkr = { 1638 .enable_reg = 0x5200c, 1639 .enable_mask = BIT(3), 1640 .hw.init = &(struct clk_init_data){ 1641 .name = "gcc_pcie_0_aux_clk", 1642 .parent_names = (const char *[]){ 1643 "gcc_pcie_0_aux_clk_src", 1644 }, 1645 .num_parents = 1, 1646 .flags = CLK_SET_RATE_PARENT, 1647 .ops = &clk_branch2_ops, 1648 }, 1649 }, 1650 }; 1651 1652 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1653 .halt_reg = 0x6b018, 1654 .halt_check = BRANCH_HALT_VOTED, 1655 .hwcg_reg = 0x6b018, 1656 .hwcg_bit = 1, 1657 .clkr = { 1658 .enable_reg = 0x5200c, 1659 .enable_mask = BIT(2), 1660 .hw.init = &(struct clk_init_data){ 1661 .name = "gcc_pcie_0_cfg_ahb_clk", 1662 .ops = &clk_branch2_ops, 1663 }, 1664 }, 1665 }; 1666 1667 static struct clk_branch gcc_pcie_0_clkref_clk = { 1668 .halt_reg = 0x8c00c, 1669 .halt_check = BRANCH_HALT, 1670 .clkr = { 1671 .enable_reg = 0x8c00c, 1672 .enable_mask = BIT(0), 1673 .hw.init = &(struct clk_init_data){ 1674 .name = "gcc_pcie_0_clkref_clk", 1675 .ops = &clk_branch2_ops, 1676 }, 1677 }, 1678 }; 1679 1680 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1681 .halt_reg = 0x6b014, 1682 .halt_check = BRANCH_HALT_VOTED, 1683 .clkr = { 1684 .enable_reg = 0x5200c, 1685 .enable_mask = BIT(1), 1686 .hw.init = &(struct clk_init_data){ 1687 .name = "gcc_pcie_0_mstr_axi_clk", 1688 .ops = &clk_branch2_ops, 1689 }, 1690 }, 1691 }; 1692 1693 static struct clk_branch gcc_pcie_0_pipe_clk = { 1694 .halt_check = BRANCH_HALT_SKIP, 1695 .clkr = { 1696 .enable_reg = 0x5200c, 1697 .enable_mask = BIT(4), 1698 .hw.init = &(struct clk_init_data){ 1699 .name = "gcc_pcie_0_pipe_clk", 1700 .ops = &clk_branch2_ops, 1701 }, 1702 }, 1703 }; 1704 1705 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1706 .halt_reg = 0x6b010, 1707 .halt_check = BRANCH_HALT_VOTED, 1708 .hwcg_reg = 0x6b010, 1709 .hwcg_bit = 1, 1710 .clkr = { 1711 .enable_reg = 0x5200c, 1712 .enable_mask = BIT(0), 1713 .hw.init = &(struct clk_init_data){ 1714 .name = "gcc_pcie_0_slv_axi_clk", 1715 .ops = &clk_branch2_ops, 1716 }, 1717 }, 1718 }; 1719 1720 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1721 .halt_reg = 0x6b00c, 1722 .halt_check = BRANCH_HALT_VOTED, 1723 .clkr = { 1724 .enable_reg = 0x5200c, 1725 .enable_mask = BIT(5), 1726 .hw.init = &(struct clk_init_data){ 1727 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1728 .ops = &clk_branch2_ops, 1729 }, 1730 }, 1731 }; 1732 1733 static struct clk_branch gcc_pcie_1_aux_clk = { 1734 .halt_reg = 0x8d01c, 1735 .halt_check = BRANCH_HALT_VOTED, 1736 .clkr = { 1737 .enable_reg = 0x52004, 1738 .enable_mask = BIT(29), 1739 .hw.init = &(struct clk_init_data){ 1740 .name = "gcc_pcie_1_aux_clk", 1741 .parent_names = (const char *[]){ 1742 "gcc_pcie_1_aux_clk_src", 1743 }, 1744 .num_parents = 1, 1745 .flags = CLK_SET_RATE_PARENT, 1746 .ops = &clk_branch2_ops, 1747 }, 1748 }, 1749 }; 1750 1751 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1752 .halt_reg = 0x8d018, 1753 .halt_check = BRANCH_HALT_VOTED, 1754 .hwcg_reg = 0x8d018, 1755 .hwcg_bit = 1, 1756 .clkr = { 1757 .enable_reg = 0x52004, 1758 .enable_mask = BIT(28), 1759 .hw.init = &(struct clk_init_data){ 1760 .name = "gcc_pcie_1_cfg_ahb_clk", 1761 .ops = &clk_branch2_ops, 1762 }, 1763 }, 1764 }; 1765 1766 static struct clk_branch gcc_pcie_1_clkref_clk = { 1767 .halt_reg = 0x8c02c, 1768 .halt_check = BRANCH_HALT, 1769 .clkr = { 1770 .enable_reg = 0x8c02c, 1771 .enable_mask = BIT(0), 1772 .hw.init = &(struct clk_init_data){ 1773 .name = "gcc_pcie_1_clkref_clk", 1774 .ops = &clk_branch2_ops, 1775 }, 1776 }, 1777 }; 1778 1779 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1780 .halt_reg = 0x8d014, 1781 .halt_check = BRANCH_HALT_VOTED, 1782 .clkr = { 1783 .enable_reg = 0x52004, 1784 .enable_mask = BIT(27), 1785 .hw.init = &(struct clk_init_data){ 1786 .name = "gcc_pcie_1_mstr_axi_clk", 1787 .ops = &clk_branch2_ops, 1788 }, 1789 }, 1790 }; 1791 1792 static struct clk_branch gcc_pcie_1_pipe_clk = { 1793 .halt_check = BRANCH_HALT_SKIP, 1794 .clkr = { 1795 .enable_reg = 0x52004, 1796 .enable_mask = BIT(30), 1797 .hw.init = &(struct clk_init_data){ 1798 .name = "gcc_pcie_1_pipe_clk", 1799 .ops = &clk_branch2_ops, 1800 }, 1801 }, 1802 }; 1803 1804 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1805 .halt_reg = 0x8d010, 1806 .halt_check = BRANCH_HALT_VOTED, 1807 .hwcg_reg = 0x8d010, 1808 .hwcg_bit = 1, 1809 .clkr = { 1810 .enable_reg = 0x52004, 1811 .enable_mask = BIT(26), 1812 .hw.init = &(struct clk_init_data){ 1813 .name = "gcc_pcie_1_slv_axi_clk", 1814 .ops = &clk_branch2_ops, 1815 }, 1816 }, 1817 }; 1818 1819 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 1820 .halt_reg = 0x8d00c, 1821 .halt_check = BRANCH_HALT_VOTED, 1822 .clkr = { 1823 .enable_reg = 0x52004, 1824 .enable_mask = BIT(25), 1825 .hw.init = &(struct clk_init_data){ 1826 .name = "gcc_pcie_1_slv_q2a_axi_clk", 1827 .ops = &clk_branch2_ops, 1828 }, 1829 }, 1830 }; 1831 1832 static struct clk_branch gcc_pcie_phy_aux_clk = { 1833 .halt_reg = 0x6f004, 1834 .halt_check = BRANCH_HALT, 1835 .clkr = { 1836 .enable_reg = 0x6f004, 1837 .enable_mask = BIT(0), 1838 .hw.init = &(struct clk_init_data){ 1839 .name = "gcc_pcie_phy_aux_clk", 1840 .parent_names = (const char *[]){ 1841 "gcc_pcie_0_aux_clk_src", 1842 }, 1843 .num_parents = 1, 1844 .flags = CLK_SET_RATE_PARENT, 1845 .ops = &clk_branch2_ops, 1846 }, 1847 }, 1848 }; 1849 1850 static struct clk_branch gcc_pcie_phy_refgen_clk = { 1851 .halt_reg = 0x6f02c, 1852 .halt_check = BRANCH_HALT, 1853 .clkr = { 1854 .enable_reg = 0x6f02c, 1855 .enable_mask = BIT(0), 1856 .hw.init = &(struct clk_init_data){ 1857 .name = "gcc_pcie_phy_refgen_clk", 1858 .parent_names = (const char *[]){ 1859 "gcc_pcie_phy_refgen_clk_src", 1860 }, 1861 .num_parents = 1, 1862 .flags = CLK_SET_RATE_PARENT, 1863 .ops = &clk_branch2_ops, 1864 }, 1865 }, 1866 }; 1867 1868 static struct clk_branch gcc_pdm2_clk = { 1869 .halt_reg = 0x3300c, 1870 .halt_check = BRANCH_HALT, 1871 .clkr = { 1872 .enable_reg = 0x3300c, 1873 .enable_mask = BIT(0), 1874 .hw.init = &(struct clk_init_data){ 1875 .name = "gcc_pdm2_clk", 1876 .parent_names = (const char *[]){ 1877 "gcc_pdm2_clk_src", 1878 }, 1879 .num_parents = 1, 1880 .flags = CLK_SET_RATE_PARENT, 1881 .ops = &clk_branch2_ops, 1882 }, 1883 }, 1884 }; 1885 1886 static struct clk_branch gcc_pdm_ahb_clk = { 1887 .halt_reg = 0x33004, 1888 .halt_check = BRANCH_HALT, 1889 .hwcg_reg = 0x33004, 1890 .hwcg_bit = 1, 1891 .clkr = { 1892 .enable_reg = 0x33004, 1893 .enable_mask = BIT(0), 1894 .hw.init = &(struct clk_init_data){ 1895 .name = "gcc_pdm_ahb_clk", 1896 .ops = &clk_branch2_ops, 1897 }, 1898 }, 1899 }; 1900 1901 static struct clk_branch gcc_pdm_xo4_clk = { 1902 .halt_reg = 0x33008, 1903 .halt_check = BRANCH_HALT, 1904 .clkr = { 1905 .enable_reg = 0x33008, 1906 .enable_mask = BIT(0), 1907 .hw.init = &(struct clk_init_data){ 1908 .name = "gcc_pdm_xo4_clk", 1909 .ops = &clk_branch2_ops, 1910 }, 1911 }, 1912 }; 1913 1914 static struct clk_branch gcc_prng_ahb_clk = { 1915 .halt_reg = 0x34004, 1916 .halt_check = BRANCH_HALT_VOTED, 1917 .hwcg_reg = 0x34004, 1918 .hwcg_bit = 1, 1919 .clkr = { 1920 .enable_reg = 0x52004, 1921 .enable_mask = BIT(13), 1922 .hw.init = &(struct clk_init_data){ 1923 .name = "gcc_prng_ahb_clk", 1924 .ops = &clk_branch2_ops, 1925 }, 1926 }, 1927 }; 1928 1929 static struct clk_branch gcc_qmip_camera_ahb_clk = { 1930 .halt_reg = 0xb014, 1931 .halt_check = BRANCH_HALT, 1932 .hwcg_reg = 0xb014, 1933 .hwcg_bit = 1, 1934 .clkr = { 1935 .enable_reg = 0xb014, 1936 .enable_mask = BIT(0), 1937 .hw.init = &(struct clk_init_data){ 1938 .name = "gcc_qmip_camera_ahb_clk", 1939 .ops = &clk_branch2_ops, 1940 }, 1941 }, 1942 }; 1943 1944 static struct clk_branch gcc_qmip_disp_ahb_clk = { 1945 .halt_reg = 0xb018, 1946 .halt_check = BRANCH_HALT, 1947 .hwcg_reg = 0xb018, 1948 .hwcg_bit = 1, 1949 .clkr = { 1950 .enable_reg = 0xb018, 1951 .enable_mask = BIT(0), 1952 .hw.init = &(struct clk_init_data){ 1953 .name = "gcc_qmip_disp_ahb_clk", 1954 .ops = &clk_branch2_ops, 1955 }, 1956 }, 1957 }; 1958 1959 static struct clk_branch gcc_qmip_video_ahb_clk = { 1960 .halt_reg = 0xb010, 1961 .halt_check = BRANCH_HALT, 1962 .hwcg_reg = 0xb010, 1963 .hwcg_bit = 1, 1964 .clkr = { 1965 .enable_reg = 0xb010, 1966 .enable_mask = BIT(0), 1967 .hw.init = &(struct clk_init_data){ 1968 .name = "gcc_qmip_video_ahb_clk", 1969 .ops = &clk_branch2_ops, 1970 }, 1971 }, 1972 }; 1973 1974 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = { 1975 .halt_reg = 0x4b000, 1976 .halt_check = BRANCH_HALT, 1977 .clkr = { 1978 .enable_reg = 0x4b000, 1979 .enable_mask = BIT(0), 1980 .hw.init = &(struct clk_init_data){ 1981 .name = "gcc_qspi_cnoc_periph_ahb_clk", 1982 .ops = &clk_branch2_ops, 1983 }, 1984 }, 1985 }; 1986 1987 static struct clk_branch gcc_qspi_core_clk = { 1988 .halt_reg = 0x4b004, 1989 .halt_check = BRANCH_HALT, 1990 .clkr = { 1991 .enable_reg = 0x4b004, 1992 .enable_mask = BIT(0), 1993 .hw.init = &(struct clk_init_data){ 1994 .name = "gcc_qspi_core_clk", 1995 .parent_names = (const char *[]){ 1996 "gcc_qspi_core_clk_src", 1997 }, 1998 .num_parents = 1, 1999 .flags = CLK_SET_RATE_PARENT, 2000 .ops = &clk_branch2_ops, 2001 }, 2002 }, 2003 }; 2004 2005 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2006 .halt_reg = 0x17030, 2007 .halt_check = BRANCH_HALT_VOTED, 2008 .clkr = { 2009 .enable_reg = 0x5200c, 2010 .enable_mask = BIT(10), 2011 .hw.init = &(struct clk_init_data){ 2012 .name = "gcc_qupv3_wrap0_s0_clk", 2013 .parent_names = (const char *[]){ 2014 "gcc_qupv3_wrap0_s0_clk_src", 2015 }, 2016 .num_parents = 1, 2017 .flags = CLK_SET_RATE_PARENT, 2018 .ops = &clk_branch2_ops, 2019 }, 2020 }, 2021 }; 2022 2023 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2024 .halt_reg = 0x17160, 2025 .halt_check = BRANCH_HALT_VOTED, 2026 .clkr = { 2027 .enable_reg = 0x5200c, 2028 .enable_mask = BIT(11), 2029 .hw.init = &(struct clk_init_data){ 2030 .name = "gcc_qupv3_wrap0_s1_clk", 2031 .parent_names = (const char *[]){ 2032 "gcc_qupv3_wrap0_s1_clk_src", 2033 }, 2034 .num_parents = 1, 2035 .flags = CLK_SET_RATE_PARENT, 2036 .ops = &clk_branch2_ops, 2037 }, 2038 }, 2039 }; 2040 2041 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2042 .halt_reg = 0x17290, 2043 .halt_check = BRANCH_HALT_VOTED, 2044 .clkr = { 2045 .enable_reg = 0x5200c, 2046 .enable_mask = BIT(12), 2047 .hw.init = &(struct clk_init_data){ 2048 .name = "gcc_qupv3_wrap0_s2_clk", 2049 .parent_names = (const char *[]){ 2050 "gcc_qupv3_wrap0_s2_clk_src", 2051 }, 2052 .num_parents = 1, 2053 .flags = CLK_SET_RATE_PARENT, 2054 .ops = &clk_branch2_ops, 2055 }, 2056 }, 2057 }; 2058 2059 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2060 .halt_reg = 0x173c0, 2061 .halt_check = BRANCH_HALT_VOTED, 2062 .clkr = { 2063 .enable_reg = 0x5200c, 2064 .enable_mask = BIT(13), 2065 .hw.init = &(struct clk_init_data){ 2066 .name = "gcc_qupv3_wrap0_s3_clk", 2067 .parent_names = (const char *[]){ 2068 "gcc_qupv3_wrap0_s3_clk_src", 2069 }, 2070 .num_parents = 1, 2071 .flags = CLK_SET_RATE_PARENT, 2072 .ops = &clk_branch2_ops, 2073 }, 2074 }, 2075 }; 2076 2077 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2078 .halt_reg = 0x174f0, 2079 .halt_check = BRANCH_HALT_VOTED, 2080 .clkr = { 2081 .enable_reg = 0x5200c, 2082 .enable_mask = BIT(14), 2083 .hw.init = &(struct clk_init_data){ 2084 .name = "gcc_qupv3_wrap0_s4_clk", 2085 .parent_names = (const char *[]){ 2086 "gcc_qupv3_wrap0_s4_clk_src", 2087 }, 2088 .num_parents = 1, 2089 .flags = CLK_SET_RATE_PARENT, 2090 .ops = &clk_branch2_ops, 2091 }, 2092 }, 2093 }; 2094 2095 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2096 .halt_reg = 0x17620, 2097 .halt_check = BRANCH_HALT_VOTED, 2098 .clkr = { 2099 .enable_reg = 0x5200c, 2100 .enable_mask = BIT(15), 2101 .hw.init = &(struct clk_init_data){ 2102 .name = "gcc_qupv3_wrap0_s5_clk", 2103 .parent_names = (const char *[]){ 2104 "gcc_qupv3_wrap0_s5_clk_src", 2105 }, 2106 .num_parents = 1, 2107 .flags = CLK_SET_RATE_PARENT, 2108 .ops = &clk_branch2_ops, 2109 }, 2110 }, 2111 }; 2112 2113 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 2114 .halt_reg = 0x17750, 2115 .halt_check = BRANCH_HALT_VOTED, 2116 .clkr = { 2117 .enable_reg = 0x5200c, 2118 .enable_mask = BIT(16), 2119 .hw.init = &(struct clk_init_data){ 2120 .name = "gcc_qupv3_wrap0_s6_clk", 2121 .parent_names = (const char *[]){ 2122 "gcc_qupv3_wrap0_s6_clk_src", 2123 }, 2124 .num_parents = 1, 2125 .flags = CLK_SET_RATE_PARENT, 2126 .ops = &clk_branch2_ops, 2127 }, 2128 }, 2129 }; 2130 2131 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 2132 .halt_reg = 0x17880, 2133 .halt_check = BRANCH_HALT_VOTED, 2134 .clkr = { 2135 .enable_reg = 0x5200c, 2136 .enable_mask = BIT(17), 2137 .hw.init = &(struct clk_init_data){ 2138 .name = "gcc_qupv3_wrap0_s7_clk", 2139 .parent_names = (const char *[]){ 2140 "gcc_qupv3_wrap0_s7_clk_src", 2141 }, 2142 .num_parents = 1, 2143 .flags = CLK_SET_RATE_PARENT, 2144 .ops = &clk_branch2_ops, 2145 }, 2146 }, 2147 }; 2148 2149 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2150 .halt_reg = 0x18014, 2151 .halt_check = BRANCH_HALT_VOTED, 2152 .clkr = { 2153 .enable_reg = 0x5200c, 2154 .enable_mask = BIT(22), 2155 .hw.init = &(struct clk_init_data){ 2156 .name = "gcc_qupv3_wrap1_s0_clk", 2157 .parent_names = (const char *[]){ 2158 "gcc_qupv3_wrap1_s0_clk_src", 2159 }, 2160 .num_parents = 1, 2161 .flags = CLK_SET_RATE_PARENT, 2162 .ops = &clk_branch2_ops, 2163 }, 2164 }, 2165 }; 2166 2167 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2168 .halt_reg = 0x18144, 2169 .halt_check = BRANCH_HALT_VOTED, 2170 .clkr = { 2171 .enable_reg = 0x5200c, 2172 .enable_mask = BIT(23), 2173 .hw.init = &(struct clk_init_data){ 2174 .name = "gcc_qupv3_wrap1_s1_clk", 2175 .parent_names = (const char *[]){ 2176 "gcc_qupv3_wrap1_s1_clk_src", 2177 }, 2178 .num_parents = 1, 2179 .flags = CLK_SET_RATE_PARENT, 2180 .ops = &clk_branch2_ops, 2181 }, 2182 }, 2183 }; 2184 2185 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2186 .halt_reg = 0x18274, 2187 .halt_check = BRANCH_HALT_VOTED, 2188 .clkr = { 2189 .enable_reg = 0x5200c, 2190 .enable_mask = BIT(24), 2191 .hw.init = &(struct clk_init_data){ 2192 .name = "gcc_qupv3_wrap1_s2_clk", 2193 .parent_names = (const char *[]){ 2194 "gcc_qupv3_wrap1_s2_clk_src", 2195 }, 2196 .num_parents = 1, 2197 .flags = CLK_SET_RATE_PARENT, 2198 .ops = &clk_branch2_ops, 2199 }, 2200 }, 2201 }; 2202 2203 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2204 .halt_reg = 0x183a4, 2205 .halt_check = BRANCH_HALT_VOTED, 2206 .clkr = { 2207 .enable_reg = 0x5200c, 2208 .enable_mask = BIT(25), 2209 .hw.init = &(struct clk_init_data){ 2210 .name = "gcc_qupv3_wrap1_s3_clk", 2211 .parent_names = (const char *[]){ 2212 "gcc_qupv3_wrap1_s3_clk_src", 2213 }, 2214 .num_parents = 1, 2215 .flags = CLK_SET_RATE_PARENT, 2216 .ops = &clk_branch2_ops, 2217 }, 2218 }, 2219 }; 2220 2221 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2222 .halt_reg = 0x184d4, 2223 .halt_check = BRANCH_HALT_VOTED, 2224 .clkr = { 2225 .enable_reg = 0x5200c, 2226 .enable_mask = BIT(26), 2227 .hw.init = &(struct clk_init_data){ 2228 .name = "gcc_qupv3_wrap1_s4_clk", 2229 .parent_names = (const char *[]){ 2230 "gcc_qupv3_wrap1_s4_clk_src", 2231 }, 2232 .num_parents = 1, 2233 .flags = CLK_SET_RATE_PARENT, 2234 .ops = &clk_branch2_ops, 2235 }, 2236 }, 2237 }; 2238 2239 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2240 .halt_reg = 0x18604, 2241 .halt_check = BRANCH_HALT_VOTED, 2242 .clkr = { 2243 .enable_reg = 0x5200c, 2244 .enable_mask = BIT(27), 2245 .hw.init = &(struct clk_init_data){ 2246 .name = "gcc_qupv3_wrap1_s5_clk", 2247 .parent_names = (const char *[]){ 2248 "gcc_qupv3_wrap1_s5_clk_src", 2249 }, 2250 .num_parents = 1, 2251 .flags = CLK_SET_RATE_PARENT, 2252 .ops = &clk_branch2_ops, 2253 }, 2254 }, 2255 }; 2256 2257 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 2258 .halt_reg = 0x18734, 2259 .halt_check = BRANCH_HALT_VOTED, 2260 .clkr = { 2261 .enable_reg = 0x5200c, 2262 .enable_mask = BIT(28), 2263 .hw.init = &(struct clk_init_data){ 2264 .name = "gcc_qupv3_wrap1_s6_clk", 2265 .parent_names = (const char *[]){ 2266 "gcc_qupv3_wrap1_s6_clk_src", 2267 }, 2268 .num_parents = 1, 2269 .flags = CLK_SET_RATE_PARENT, 2270 .ops = &clk_branch2_ops, 2271 }, 2272 }, 2273 }; 2274 2275 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 2276 .halt_reg = 0x18864, 2277 .halt_check = BRANCH_HALT_VOTED, 2278 .clkr = { 2279 .enable_reg = 0x5200c, 2280 .enable_mask = BIT(29), 2281 .hw.init = &(struct clk_init_data){ 2282 .name = "gcc_qupv3_wrap1_s7_clk", 2283 .parent_names = (const char *[]){ 2284 "gcc_qupv3_wrap1_s7_clk_src", 2285 }, 2286 .num_parents = 1, 2287 .flags = CLK_SET_RATE_PARENT, 2288 .ops = &clk_branch2_ops, 2289 }, 2290 }, 2291 }; 2292 2293 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2294 .halt_reg = 0x17004, 2295 .halt_check = BRANCH_HALT_VOTED, 2296 .clkr = { 2297 .enable_reg = 0x5200c, 2298 .enable_mask = BIT(6), 2299 .hw.init = &(struct clk_init_data){ 2300 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2301 .ops = &clk_branch2_ops, 2302 }, 2303 }, 2304 }; 2305 2306 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2307 .halt_reg = 0x17008, 2308 .halt_check = BRANCH_HALT_VOTED, 2309 .hwcg_reg = 0x17008, 2310 .hwcg_bit = 1, 2311 .clkr = { 2312 .enable_reg = 0x5200c, 2313 .enable_mask = BIT(7), 2314 .hw.init = &(struct clk_init_data){ 2315 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2316 .ops = &clk_branch2_ops, 2317 }, 2318 }, 2319 }; 2320 2321 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2322 .halt_reg = 0x1800c, 2323 .halt_check = BRANCH_HALT_VOTED, 2324 .clkr = { 2325 .enable_reg = 0x5200c, 2326 .enable_mask = BIT(20), 2327 .hw.init = &(struct clk_init_data){ 2328 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2329 .ops = &clk_branch2_ops, 2330 }, 2331 }, 2332 }; 2333 2334 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2335 .halt_reg = 0x18010, 2336 .halt_check = BRANCH_HALT_VOTED, 2337 .hwcg_reg = 0x18010, 2338 .hwcg_bit = 1, 2339 .clkr = { 2340 .enable_reg = 0x5200c, 2341 .enable_mask = BIT(21), 2342 .hw.init = &(struct clk_init_data){ 2343 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2344 .ops = &clk_branch2_ops, 2345 }, 2346 }, 2347 }; 2348 2349 static struct clk_branch gcc_sdcc2_ahb_clk = { 2350 .halt_reg = 0x14008, 2351 .halt_check = BRANCH_HALT, 2352 .clkr = { 2353 .enable_reg = 0x14008, 2354 .enable_mask = BIT(0), 2355 .hw.init = &(struct clk_init_data){ 2356 .name = "gcc_sdcc2_ahb_clk", 2357 .ops = &clk_branch2_ops, 2358 }, 2359 }, 2360 }; 2361 2362 static struct clk_branch gcc_sdcc2_apps_clk = { 2363 .halt_reg = 0x14004, 2364 .halt_check = BRANCH_HALT, 2365 .clkr = { 2366 .enable_reg = 0x14004, 2367 .enable_mask = BIT(0), 2368 .hw.init = &(struct clk_init_data){ 2369 .name = "gcc_sdcc2_apps_clk", 2370 .parent_names = (const char *[]){ 2371 "gcc_sdcc2_apps_clk_src", 2372 }, 2373 .num_parents = 1, 2374 .flags = CLK_SET_RATE_PARENT, 2375 .ops = &clk_branch2_ops, 2376 }, 2377 }, 2378 }; 2379 2380 static struct clk_branch gcc_sdcc4_ahb_clk = { 2381 .halt_reg = 0x16008, 2382 .halt_check = BRANCH_HALT, 2383 .clkr = { 2384 .enable_reg = 0x16008, 2385 .enable_mask = BIT(0), 2386 .hw.init = &(struct clk_init_data){ 2387 .name = "gcc_sdcc4_ahb_clk", 2388 .ops = &clk_branch2_ops, 2389 }, 2390 }, 2391 }; 2392 2393 static struct clk_branch gcc_sdcc4_apps_clk = { 2394 .halt_reg = 0x16004, 2395 .halt_check = BRANCH_HALT, 2396 .clkr = { 2397 .enable_reg = 0x16004, 2398 .enable_mask = BIT(0), 2399 .hw.init = &(struct clk_init_data){ 2400 .name = "gcc_sdcc4_apps_clk", 2401 .parent_names = (const char *[]){ 2402 "gcc_sdcc4_apps_clk_src", 2403 }, 2404 .num_parents = 1, 2405 .flags = CLK_SET_RATE_PARENT, 2406 .ops = &clk_branch2_ops, 2407 }, 2408 }, 2409 }; 2410 2411 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 2412 .halt_reg = 0x414c, 2413 .halt_check = BRANCH_HALT_VOTED, 2414 .clkr = { 2415 .enable_reg = 0x52004, 2416 .enable_mask = BIT(0), 2417 .hw.init = &(struct clk_init_data){ 2418 .name = "gcc_sys_noc_cpuss_ahb_clk", 2419 .parent_names = (const char *[]){ 2420 "gcc_cpuss_ahb_clk_src", 2421 }, 2422 .num_parents = 1, 2423 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 2424 .ops = &clk_branch2_ops, 2425 }, 2426 }, 2427 }; 2428 2429 static struct clk_branch gcc_tsif_ahb_clk = { 2430 .halt_reg = 0x36004, 2431 .halt_check = BRANCH_HALT, 2432 .clkr = { 2433 .enable_reg = 0x36004, 2434 .enable_mask = BIT(0), 2435 .hw.init = &(struct clk_init_data){ 2436 .name = "gcc_tsif_ahb_clk", 2437 .ops = &clk_branch2_ops, 2438 }, 2439 }, 2440 }; 2441 2442 static struct clk_branch gcc_tsif_inactivity_timers_clk = { 2443 .halt_reg = 0x3600c, 2444 .halt_check = BRANCH_HALT, 2445 .clkr = { 2446 .enable_reg = 0x3600c, 2447 .enable_mask = BIT(0), 2448 .hw.init = &(struct clk_init_data){ 2449 .name = "gcc_tsif_inactivity_timers_clk", 2450 .ops = &clk_branch2_ops, 2451 }, 2452 }, 2453 }; 2454 2455 static struct clk_branch gcc_tsif_ref_clk = { 2456 .halt_reg = 0x36008, 2457 .halt_check = BRANCH_HALT, 2458 .clkr = { 2459 .enable_reg = 0x36008, 2460 .enable_mask = BIT(0), 2461 .hw.init = &(struct clk_init_data){ 2462 .name = "gcc_tsif_ref_clk", 2463 .parent_names = (const char *[]){ 2464 "gcc_tsif_ref_clk_src", 2465 }, 2466 .num_parents = 1, 2467 .flags = CLK_SET_RATE_PARENT, 2468 .ops = &clk_branch2_ops, 2469 }, 2470 }, 2471 }; 2472 2473 static struct clk_branch gcc_ufs_card_ahb_clk = { 2474 .halt_reg = 0x75010, 2475 .halt_check = BRANCH_HALT, 2476 .hwcg_reg = 0x75010, 2477 .hwcg_bit = 1, 2478 .clkr = { 2479 .enable_reg = 0x75010, 2480 .enable_mask = BIT(0), 2481 .hw.init = &(struct clk_init_data){ 2482 .name = "gcc_ufs_card_ahb_clk", 2483 .ops = &clk_branch2_ops, 2484 }, 2485 }, 2486 }; 2487 2488 static struct clk_branch gcc_ufs_card_axi_clk = { 2489 .halt_reg = 0x7500c, 2490 .halt_check = BRANCH_HALT, 2491 .hwcg_reg = 0x7500c, 2492 .hwcg_bit = 1, 2493 .clkr = { 2494 .enable_reg = 0x7500c, 2495 .enable_mask = BIT(0), 2496 .hw.init = &(struct clk_init_data){ 2497 .name = "gcc_ufs_card_axi_clk", 2498 .parent_names = (const char *[]){ 2499 "gcc_ufs_card_axi_clk_src", 2500 }, 2501 .num_parents = 1, 2502 .flags = CLK_SET_RATE_PARENT, 2503 .ops = &clk_branch2_ops, 2504 }, 2505 }, 2506 }; 2507 2508 static struct clk_branch gcc_ufs_card_clkref_clk = { 2509 .halt_reg = 0x8c004, 2510 .halt_check = BRANCH_HALT, 2511 .clkr = { 2512 .enable_reg = 0x8c004, 2513 .enable_mask = BIT(0), 2514 .hw.init = &(struct clk_init_data){ 2515 .name = "gcc_ufs_card_clkref_clk", 2516 .ops = &clk_branch2_ops, 2517 }, 2518 }, 2519 }; 2520 2521 static struct clk_branch gcc_ufs_card_ice_core_clk = { 2522 .halt_reg = 0x75058, 2523 .halt_check = BRANCH_HALT, 2524 .hwcg_reg = 0x75058, 2525 .hwcg_bit = 1, 2526 .clkr = { 2527 .enable_reg = 0x75058, 2528 .enable_mask = BIT(0), 2529 .hw.init = &(struct clk_init_data){ 2530 .name = "gcc_ufs_card_ice_core_clk", 2531 .parent_names = (const char *[]){ 2532 "gcc_ufs_card_ice_core_clk_src", 2533 }, 2534 .num_parents = 1, 2535 .flags = CLK_SET_RATE_PARENT, 2536 .ops = &clk_branch2_ops, 2537 }, 2538 }, 2539 }; 2540 2541 static struct clk_branch gcc_ufs_card_phy_aux_clk = { 2542 .halt_reg = 0x7508c, 2543 .halt_check = BRANCH_HALT, 2544 .hwcg_reg = 0x7508c, 2545 .hwcg_bit = 1, 2546 .clkr = { 2547 .enable_reg = 0x7508c, 2548 .enable_mask = BIT(0), 2549 .hw.init = &(struct clk_init_data){ 2550 .name = "gcc_ufs_card_phy_aux_clk", 2551 .parent_names = (const char *[]){ 2552 "gcc_ufs_card_phy_aux_clk_src", 2553 }, 2554 .num_parents = 1, 2555 .flags = CLK_SET_RATE_PARENT, 2556 .ops = &clk_branch2_ops, 2557 }, 2558 }, 2559 }; 2560 2561 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { 2562 .halt_check = BRANCH_HALT_SKIP, 2563 .clkr = { 2564 .enable_reg = 0x75018, 2565 .enable_mask = BIT(0), 2566 .hw.init = &(struct clk_init_data){ 2567 .name = "gcc_ufs_card_rx_symbol_0_clk", 2568 .ops = &clk_branch2_ops, 2569 }, 2570 }, 2571 }; 2572 2573 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = { 2574 .halt_check = BRANCH_HALT_SKIP, 2575 .clkr = { 2576 .enable_reg = 0x750a8, 2577 .enable_mask = BIT(0), 2578 .hw.init = &(struct clk_init_data){ 2579 .name = "gcc_ufs_card_rx_symbol_1_clk", 2580 .ops = &clk_branch2_ops, 2581 }, 2582 }, 2583 }; 2584 2585 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = { 2586 .halt_check = BRANCH_HALT_SKIP, 2587 .clkr = { 2588 .enable_reg = 0x75014, 2589 .enable_mask = BIT(0), 2590 .hw.init = &(struct clk_init_data){ 2591 .name = "gcc_ufs_card_tx_symbol_0_clk", 2592 .ops = &clk_branch2_ops, 2593 }, 2594 }, 2595 }; 2596 2597 static struct clk_branch gcc_ufs_card_unipro_core_clk = { 2598 .halt_reg = 0x75054, 2599 .halt_check = BRANCH_HALT, 2600 .hwcg_reg = 0x75054, 2601 .hwcg_bit = 1, 2602 .clkr = { 2603 .enable_reg = 0x75054, 2604 .enable_mask = BIT(0), 2605 .hw.init = &(struct clk_init_data){ 2606 .name = "gcc_ufs_card_unipro_core_clk", 2607 .parent_names = (const char *[]){ 2608 "gcc_ufs_card_unipro_core_clk_src", 2609 }, 2610 .num_parents = 1, 2611 .flags = CLK_SET_RATE_PARENT, 2612 .ops = &clk_branch2_ops, 2613 }, 2614 }, 2615 }; 2616 2617 static struct clk_branch gcc_ufs_mem_clkref_clk = { 2618 .halt_reg = 0x8c000, 2619 .halt_check = BRANCH_HALT, 2620 .clkr = { 2621 .enable_reg = 0x8c000, 2622 .enable_mask = BIT(0), 2623 .hw.init = &(struct clk_init_data){ 2624 .name = "gcc_ufs_mem_clkref_clk", 2625 .ops = &clk_branch2_ops, 2626 }, 2627 }, 2628 }; 2629 2630 static struct clk_branch gcc_ufs_phy_ahb_clk = { 2631 .halt_reg = 0x77010, 2632 .halt_check = BRANCH_HALT, 2633 .hwcg_reg = 0x77010, 2634 .hwcg_bit = 1, 2635 .clkr = { 2636 .enable_reg = 0x77010, 2637 .enable_mask = BIT(0), 2638 .hw.init = &(struct clk_init_data){ 2639 .name = "gcc_ufs_phy_ahb_clk", 2640 .ops = &clk_branch2_ops, 2641 }, 2642 }, 2643 }; 2644 2645 static struct clk_branch gcc_ufs_phy_axi_clk = { 2646 .halt_reg = 0x7700c, 2647 .halt_check = BRANCH_HALT, 2648 .hwcg_reg = 0x7700c, 2649 .hwcg_bit = 1, 2650 .clkr = { 2651 .enable_reg = 0x7700c, 2652 .enable_mask = BIT(0), 2653 .hw.init = &(struct clk_init_data){ 2654 .name = "gcc_ufs_phy_axi_clk", 2655 .parent_names = (const char *[]){ 2656 "gcc_ufs_phy_axi_clk_src", 2657 }, 2658 .num_parents = 1, 2659 .flags = CLK_SET_RATE_PARENT, 2660 .ops = &clk_branch2_ops, 2661 }, 2662 }, 2663 }; 2664 2665 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2666 .halt_reg = 0x77058, 2667 .halt_check = BRANCH_HALT, 2668 .hwcg_reg = 0x77058, 2669 .hwcg_bit = 1, 2670 .clkr = { 2671 .enable_reg = 0x77058, 2672 .enable_mask = BIT(0), 2673 .hw.init = &(struct clk_init_data){ 2674 .name = "gcc_ufs_phy_ice_core_clk", 2675 .parent_names = (const char *[]){ 2676 "gcc_ufs_phy_ice_core_clk_src", 2677 }, 2678 .num_parents = 1, 2679 .flags = CLK_SET_RATE_PARENT, 2680 .ops = &clk_branch2_ops, 2681 }, 2682 }, 2683 }; 2684 2685 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2686 .halt_reg = 0x7708c, 2687 .halt_check = BRANCH_HALT, 2688 .hwcg_reg = 0x7708c, 2689 .hwcg_bit = 1, 2690 .clkr = { 2691 .enable_reg = 0x7708c, 2692 .enable_mask = BIT(0), 2693 .hw.init = &(struct clk_init_data){ 2694 .name = "gcc_ufs_phy_phy_aux_clk", 2695 .parent_names = (const char *[]){ 2696 "gcc_ufs_phy_phy_aux_clk_src", 2697 }, 2698 .num_parents = 1, 2699 .flags = CLK_SET_RATE_PARENT, 2700 .ops = &clk_branch2_ops, 2701 }, 2702 }, 2703 }; 2704 2705 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2706 .halt_check = BRANCH_HALT_SKIP, 2707 .clkr = { 2708 .enable_reg = 0x77018, 2709 .enable_mask = BIT(0), 2710 .hw.init = &(struct clk_init_data){ 2711 .name = "gcc_ufs_phy_rx_symbol_0_clk", 2712 .ops = &clk_branch2_ops, 2713 }, 2714 }, 2715 }; 2716 2717 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 2718 .halt_check = BRANCH_HALT_SKIP, 2719 .clkr = { 2720 .enable_reg = 0x770a8, 2721 .enable_mask = BIT(0), 2722 .hw.init = &(struct clk_init_data){ 2723 .name = "gcc_ufs_phy_rx_symbol_1_clk", 2724 .ops = &clk_branch2_ops, 2725 }, 2726 }, 2727 }; 2728 2729 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2730 .halt_check = BRANCH_HALT_SKIP, 2731 .clkr = { 2732 .enable_reg = 0x77014, 2733 .enable_mask = BIT(0), 2734 .hw.init = &(struct clk_init_data){ 2735 .name = "gcc_ufs_phy_tx_symbol_0_clk", 2736 .ops = &clk_branch2_ops, 2737 }, 2738 }, 2739 }; 2740 2741 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2742 .halt_reg = 0x77054, 2743 .halt_check = BRANCH_HALT, 2744 .hwcg_reg = 0x77054, 2745 .hwcg_bit = 1, 2746 .clkr = { 2747 .enable_reg = 0x77054, 2748 .enable_mask = BIT(0), 2749 .hw.init = &(struct clk_init_data){ 2750 .name = "gcc_ufs_phy_unipro_core_clk", 2751 .parent_names = (const char *[]){ 2752 "gcc_ufs_phy_unipro_core_clk_src", 2753 }, 2754 .num_parents = 1, 2755 .flags = CLK_SET_RATE_PARENT, 2756 .ops = &clk_branch2_ops, 2757 }, 2758 }, 2759 }; 2760 2761 static struct clk_branch gcc_usb30_prim_master_clk = { 2762 .halt_reg = 0xf00c, 2763 .halt_check = BRANCH_HALT, 2764 .clkr = { 2765 .enable_reg = 0xf00c, 2766 .enable_mask = BIT(0), 2767 .hw.init = &(struct clk_init_data){ 2768 .name = "gcc_usb30_prim_master_clk", 2769 .parent_names = (const char *[]){ 2770 "gcc_usb30_prim_master_clk_src", 2771 }, 2772 .num_parents = 1, 2773 .flags = CLK_SET_RATE_PARENT, 2774 .ops = &clk_branch2_ops, 2775 }, 2776 }, 2777 }; 2778 2779 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2780 .halt_reg = 0xf014, 2781 .halt_check = BRANCH_HALT, 2782 .clkr = { 2783 .enable_reg = 0xf014, 2784 .enable_mask = BIT(0), 2785 .hw.init = &(struct clk_init_data){ 2786 .name = "gcc_usb30_prim_mock_utmi_clk", 2787 .parent_names = (const char *[]){ 2788 "gcc_usb30_prim_mock_utmi_clk_src", 2789 }, 2790 .num_parents = 1, 2791 .flags = CLK_SET_RATE_PARENT, 2792 .ops = &clk_branch2_ops, 2793 }, 2794 }, 2795 }; 2796 2797 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2798 .halt_reg = 0xf010, 2799 .halt_check = BRANCH_HALT, 2800 .clkr = { 2801 .enable_reg = 0xf010, 2802 .enable_mask = BIT(0), 2803 .hw.init = &(struct clk_init_data){ 2804 .name = "gcc_usb30_prim_sleep_clk", 2805 .ops = &clk_branch2_ops, 2806 }, 2807 }, 2808 }; 2809 2810 static struct clk_branch gcc_usb30_sec_master_clk = { 2811 .halt_reg = 0x1000c, 2812 .halt_check = BRANCH_HALT, 2813 .clkr = { 2814 .enable_reg = 0x1000c, 2815 .enable_mask = BIT(0), 2816 .hw.init = &(struct clk_init_data){ 2817 .name = "gcc_usb30_sec_master_clk", 2818 .parent_names = (const char *[]){ 2819 "gcc_usb30_sec_master_clk_src", 2820 }, 2821 .num_parents = 1, 2822 .flags = CLK_SET_RATE_PARENT, 2823 .ops = &clk_branch2_ops, 2824 }, 2825 }, 2826 }; 2827 2828 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { 2829 .halt_reg = 0x10014, 2830 .halt_check = BRANCH_HALT, 2831 .clkr = { 2832 .enable_reg = 0x10014, 2833 .enable_mask = BIT(0), 2834 .hw.init = &(struct clk_init_data){ 2835 .name = "gcc_usb30_sec_mock_utmi_clk", 2836 .parent_names = (const char *[]){ 2837 "gcc_usb30_sec_mock_utmi_clk_src", 2838 }, 2839 .num_parents = 1, 2840 .flags = CLK_SET_RATE_PARENT, 2841 .ops = &clk_branch2_ops, 2842 }, 2843 }, 2844 }; 2845 2846 static struct clk_branch gcc_usb30_sec_sleep_clk = { 2847 .halt_reg = 0x10010, 2848 .halt_check = BRANCH_HALT, 2849 .clkr = { 2850 .enable_reg = 0x10010, 2851 .enable_mask = BIT(0), 2852 .hw.init = &(struct clk_init_data){ 2853 .name = "gcc_usb30_sec_sleep_clk", 2854 .ops = &clk_branch2_ops, 2855 }, 2856 }, 2857 }; 2858 2859 static struct clk_branch gcc_usb3_prim_clkref_clk = { 2860 .halt_reg = 0x8c008, 2861 .halt_check = BRANCH_HALT, 2862 .clkr = { 2863 .enable_reg = 0x8c008, 2864 .enable_mask = BIT(0), 2865 .hw.init = &(struct clk_init_data){ 2866 .name = "gcc_usb3_prim_clkref_clk", 2867 .ops = &clk_branch2_ops, 2868 }, 2869 }, 2870 }; 2871 2872 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2873 .halt_reg = 0xf04c, 2874 .halt_check = BRANCH_HALT, 2875 .clkr = { 2876 .enable_reg = 0xf04c, 2877 .enable_mask = BIT(0), 2878 .hw.init = &(struct clk_init_data){ 2879 .name = "gcc_usb3_prim_phy_aux_clk", 2880 .parent_names = (const char *[]){ 2881 "gcc_usb3_prim_phy_aux_clk_src", 2882 }, 2883 .num_parents = 1, 2884 .flags = CLK_SET_RATE_PARENT, 2885 .ops = &clk_branch2_ops, 2886 }, 2887 }, 2888 }; 2889 2890 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2891 .halt_reg = 0xf050, 2892 .halt_check = BRANCH_HALT, 2893 .clkr = { 2894 .enable_reg = 0xf050, 2895 .enable_mask = BIT(0), 2896 .hw.init = &(struct clk_init_data){ 2897 .name = "gcc_usb3_prim_phy_com_aux_clk", 2898 .parent_names = (const char *[]){ 2899 "gcc_usb3_prim_phy_aux_clk_src", 2900 }, 2901 .num_parents = 1, 2902 .flags = CLK_SET_RATE_PARENT, 2903 .ops = &clk_branch2_ops, 2904 }, 2905 }, 2906 }; 2907 2908 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2909 .halt_check = BRANCH_HALT_SKIP, 2910 .clkr = { 2911 .enable_reg = 0xf054, 2912 .enable_mask = BIT(0), 2913 .hw.init = &(struct clk_init_data){ 2914 .name = "gcc_usb3_prim_phy_pipe_clk", 2915 .ops = &clk_branch2_ops, 2916 }, 2917 }, 2918 }; 2919 2920 static struct clk_branch gcc_usb3_sec_clkref_clk = { 2921 .halt_reg = 0x8c028, 2922 .halt_check = BRANCH_HALT, 2923 .clkr = { 2924 .enable_reg = 0x8c028, 2925 .enable_mask = BIT(0), 2926 .hw.init = &(struct clk_init_data){ 2927 .name = "gcc_usb3_sec_clkref_clk", 2928 .ops = &clk_branch2_ops, 2929 }, 2930 }, 2931 }; 2932 2933 static struct clk_branch gcc_usb3_sec_phy_aux_clk = { 2934 .halt_reg = 0x1004c, 2935 .halt_check = BRANCH_HALT, 2936 .clkr = { 2937 .enable_reg = 0x1004c, 2938 .enable_mask = BIT(0), 2939 .hw.init = &(struct clk_init_data){ 2940 .name = "gcc_usb3_sec_phy_aux_clk", 2941 .parent_names = (const char *[]){ 2942 "gcc_usb3_sec_phy_aux_clk_src", 2943 }, 2944 .num_parents = 1, 2945 .flags = CLK_SET_RATE_PARENT, 2946 .ops = &clk_branch2_ops, 2947 }, 2948 }, 2949 }; 2950 2951 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { 2952 .halt_reg = 0x10050, 2953 .halt_check = BRANCH_HALT, 2954 .clkr = { 2955 .enable_reg = 0x10050, 2956 .enable_mask = BIT(0), 2957 .hw.init = &(struct clk_init_data){ 2958 .name = "gcc_usb3_sec_phy_com_aux_clk", 2959 .parent_names = (const char *[]){ 2960 "gcc_usb3_sec_phy_aux_clk_src", 2961 }, 2962 .num_parents = 1, 2963 .flags = CLK_SET_RATE_PARENT, 2964 .ops = &clk_branch2_ops, 2965 }, 2966 }, 2967 }; 2968 2969 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { 2970 .halt_check = BRANCH_HALT_SKIP, 2971 .clkr = { 2972 .enable_reg = 0x10054, 2973 .enable_mask = BIT(0), 2974 .hw.init = &(struct clk_init_data){ 2975 .name = "gcc_usb3_sec_phy_pipe_clk", 2976 .ops = &clk_branch2_ops, 2977 }, 2978 }, 2979 }; 2980 2981 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { 2982 .halt_reg = 0x6a004, 2983 .halt_check = BRANCH_HALT, 2984 .hwcg_reg = 0x6a004, 2985 .hwcg_bit = 1, 2986 .clkr = { 2987 .enable_reg = 0x6a004, 2988 .enable_mask = BIT(0), 2989 .hw.init = &(struct clk_init_data){ 2990 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 2991 .ops = &clk_branch2_ops, 2992 }, 2993 }, 2994 }; 2995 2996 static struct clk_branch gcc_vdda_vs_clk = { 2997 .halt_reg = 0x7a00c, 2998 .halt_check = BRANCH_HALT, 2999 .clkr = { 3000 .enable_reg = 0x7a00c, 3001 .enable_mask = BIT(0), 3002 .hw.init = &(struct clk_init_data){ 3003 .name = "gcc_vdda_vs_clk", 3004 .parent_names = (const char *[]){ 3005 "gcc_vsensor_clk_src", 3006 }, 3007 .num_parents = 1, 3008 .flags = CLK_SET_RATE_PARENT, 3009 .ops = &clk_branch2_ops, 3010 }, 3011 }, 3012 }; 3013 3014 static struct clk_branch gcc_vddcx_vs_clk = { 3015 .halt_reg = 0x7a004, 3016 .halt_check = BRANCH_HALT, 3017 .clkr = { 3018 .enable_reg = 0x7a004, 3019 .enable_mask = BIT(0), 3020 .hw.init = &(struct clk_init_data){ 3021 .name = "gcc_vddcx_vs_clk", 3022 .parent_names = (const char *[]){ 3023 "gcc_vsensor_clk_src", 3024 }, 3025 .num_parents = 1, 3026 .flags = CLK_SET_RATE_PARENT, 3027 .ops = &clk_branch2_ops, 3028 }, 3029 }, 3030 }; 3031 3032 static struct clk_branch gcc_vddmx_vs_clk = { 3033 .halt_reg = 0x7a008, 3034 .halt_check = BRANCH_HALT, 3035 .clkr = { 3036 .enable_reg = 0x7a008, 3037 .enable_mask = BIT(0), 3038 .hw.init = &(struct clk_init_data){ 3039 .name = "gcc_vddmx_vs_clk", 3040 .parent_names = (const char *[]){ 3041 "gcc_vsensor_clk_src", 3042 }, 3043 .num_parents = 1, 3044 .flags = CLK_SET_RATE_PARENT, 3045 .ops = &clk_branch2_ops, 3046 }, 3047 }, 3048 }; 3049 3050 static struct clk_branch gcc_video_ahb_clk = { 3051 .halt_reg = 0xb004, 3052 .halt_check = BRANCH_HALT, 3053 .hwcg_reg = 0xb004, 3054 .hwcg_bit = 1, 3055 .clkr = { 3056 .enable_reg = 0xb004, 3057 .enable_mask = BIT(0), 3058 .hw.init = &(struct clk_init_data){ 3059 .name = "gcc_video_ahb_clk", 3060 .flags = CLK_IS_CRITICAL, 3061 .ops = &clk_branch2_ops, 3062 }, 3063 }, 3064 }; 3065 3066 static struct clk_branch gcc_video_axi_clk = { 3067 .halt_reg = 0xb01c, 3068 .halt_check = BRANCH_VOTED, 3069 .clkr = { 3070 .enable_reg = 0xb01c, 3071 .enable_mask = BIT(0), 3072 .hw.init = &(struct clk_init_data){ 3073 .name = "gcc_video_axi_clk", 3074 .ops = &clk_branch2_ops, 3075 }, 3076 }, 3077 }; 3078 3079 static struct clk_branch gcc_video_xo_clk = { 3080 .halt_reg = 0xb028, 3081 .halt_check = BRANCH_HALT, 3082 .clkr = { 3083 .enable_reg = 0xb028, 3084 .enable_mask = BIT(0), 3085 .hw.init = &(struct clk_init_data){ 3086 .name = "gcc_video_xo_clk", 3087 .flags = CLK_IS_CRITICAL, 3088 .ops = &clk_branch2_ops, 3089 }, 3090 }, 3091 }; 3092 3093 static struct clk_branch gcc_vs_ctrl_ahb_clk = { 3094 .halt_reg = 0x7a014, 3095 .halt_check = BRANCH_HALT, 3096 .hwcg_reg = 0x7a014, 3097 .hwcg_bit = 1, 3098 .clkr = { 3099 .enable_reg = 0x7a014, 3100 .enable_mask = BIT(0), 3101 .hw.init = &(struct clk_init_data){ 3102 .name = "gcc_vs_ctrl_ahb_clk", 3103 .ops = &clk_branch2_ops, 3104 }, 3105 }, 3106 }; 3107 3108 static struct clk_branch gcc_vs_ctrl_clk = { 3109 .halt_reg = 0x7a010, 3110 .halt_check = BRANCH_HALT, 3111 .clkr = { 3112 .enable_reg = 0x7a010, 3113 .enable_mask = BIT(0), 3114 .hw.init = &(struct clk_init_data){ 3115 .name = "gcc_vs_ctrl_clk", 3116 .parent_names = (const char *[]){ 3117 "gcc_vs_ctrl_clk_src", 3118 }, 3119 .num_parents = 1, 3120 .flags = CLK_SET_RATE_PARENT, 3121 .ops = &clk_branch2_ops, 3122 }, 3123 }, 3124 }; 3125 3126 static struct clk_branch gcc_cpuss_dvm_bus_clk = { 3127 .halt_reg = 0x48190, 3128 .halt_check = BRANCH_HALT, 3129 .clkr = { 3130 .enable_reg = 0x48190, 3131 .enable_mask = BIT(0), 3132 .hw.init = &(struct clk_init_data){ 3133 .name = "gcc_cpuss_dvm_bus_clk", 3134 .flags = CLK_IS_CRITICAL, 3135 .ops = &clk_branch2_ops, 3136 }, 3137 }, 3138 }; 3139 3140 static struct clk_branch gcc_cpuss_gnoc_clk = { 3141 .halt_reg = 0x48004, 3142 .halt_check = BRANCH_HALT_VOTED, 3143 .hwcg_reg = 0x48004, 3144 .hwcg_bit = 1, 3145 .clkr = { 3146 .enable_reg = 0x52004, 3147 .enable_mask = BIT(22), 3148 .hw.init = &(struct clk_init_data){ 3149 .name = "gcc_cpuss_gnoc_clk", 3150 .flags = CLK_IS_CRITICAL, 3151 .ops = &clk_branch2_ops, 3152 }, 3153 }, 3154 }; 3155 3156 /* TODO: Remove after DTS updated to protect these */ 3157 #ifdef CONFIG_SDM_LPASSCC_845 3158 static struct clk_branch gcc_lpass_q6_axi_clk = { 3159 .halt_reg = 0x47000, 3160 .halt_check = BRANCH_HALT, 3161 .clkr = { 3162 .enable_reg = 0x47000, 3163 .enable_mask = BIT(0), 3164 .hw.init = &(struct clk_init_data){ 3165 .name = "gcc_lpass_q6_axi_clk", 3166 .flags = CLK_IS_CRITICAL, 3167 .ops = &clk_branch2_ops, 3168 }, 3169 }, 3170 }; 3171 3172 static struct clk_branch gcc_lpass_sway_clk = { 3173 .halt_reg = 0x47008, 3174 .halt_check = BRANCH_HALT, 3175 .clkr = { 3176 .enable_reg = 0x47008, 3177 .enable_mask = BIT(0), 3178 .hw.init = &(struct clk_init_data){ 3179 .name = "gcc_lpass_sway_clk", 3180 .flags = CLK_IS_CRITICAL, 3181 .ops = &clk_branch2_ops, 3182 }, 3183 }, 3184 }; 3185 #endif 3186 3187 static struct gdsc pcie_0_gdsc = { 3188 .gdscr = 0x6b004, 3189 .pd = { 3190 .name = "pcie_0_gdsc", 3191 }, 3192 .pwrsts = PWRSTS_OFF_ON, 3193 .flags = POLL_CFG_GDSCR, 3194 }; 3195 3196 static struct gdsc pcie_1_gdsc = { 3197 .gdscr = 0x8d004, 3198 .pd = { 3199 .name = "pcie_1_gdsc", 3200 }, 3201 .pwrsts = PWRSTS_OFF_ON, 3202 .flags = POLL_CFG_GDSCR, 3203 }; 3204 3205 static struct gdsc ufs_card_gdsc = { 3206 .gdscr = 0x75004, 3207 .pd = { 3208 .name = "ufs_card_gdsc", 3209 }, 3210 .pwrsts = PWRSTS_OFF_ON, 3211 .flags = POLL_CFG_GDSCR, 3212 }; 3213 3214 static struct gdsc ufs_phy_gdsc = { 3215 .gdscr = 0x77004, 3216 .pd = { 3217 .name = "ufs_phy_gdsc", 3218 }, 3219 .pwrsts = PWRSTS_OFF_ON, 3220 .flags = POLL_CFG_GDSCR, 3221 }; 3222 3223 static struct gdsc usb30_prim_gdsc = { 3224 .gdscr = 0xf004, 3225 .pd = { 3226 .name = "usb30_prim_gdsc", 3227 }, 3228 .pwrsts = PWRSTS_OFF_ON, 3229 .flags = POLL_CFG_GDSCR, 3230 }; 3231 3232 static struct gdsc usb30_sec_gdsc = { 3233 .gdscr = 0x10004, 3234 .pd = { 3235 .name = "usb30_sec_gdsc", 3236 }, 3237 .pwrsts = PWRSTS_OFF_ON, 3238 .flags = POLL_CFG_GDSCR, 3239 }; 3240 3241 static struct gdsc hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = { 3242 .gdscr = 0x7d030, 3243 .pd = { 3244 .name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc", 3245 }, 3246 .pwrsts = PWRSTS_OFF_ON, 3247 }; 3248 3249 static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = { 3250 .gdscr = 0x7d03c, 3251 .pd = { 3252 .name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc", 3253 }, 3254 .pwrsts = PWRSTS_OFF_ON, 3255 }; 3256 3257 static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = { 3258 .gdscr = 0x7d034, 3259 .pd = { 3260 .name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc", 3261 }, 3262 .pwrsts = PWRSTS_OFF_ON, 3263 }; 3264 3265 static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = { 3266 .gdscr = 0x7d038, 3267 .pd = { 3268 .name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc", 3269 }, 3270 .pwrsts = PWRSTS_OFF_ON, 3271 }; 3272 3273 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = { 3274 .gdscr = 0x7d040, 3275 .pd = { 3276 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", 3277 }, 3278 .pwrsts = PWRSTS_OFF_ON, 3279 }; 3280 3281 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = { 3282 .gdscr = 0x7d048, 3283 .pd = { 3284 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", 3285 }, 3286 .pwrsts = PWRSTS_OFF_ON, 3287 }; 3288 3289 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = { 3290 .gdscr = 0x7d044, 3291 .pd = { 3292 .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc", 3293 }, 3294 .pwrsts = PWRSTS_OFF_ON, 3295 }; 3296 3297 static struct clk_regmap *gcc_sdm845_clocks[] = { 3298 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, 3299 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, 3300 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 3301 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 3302 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, 3303 [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr, 3304 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3305 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, 3306 [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr, 3307 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, 3308 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, 3309 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, 3310 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, 3311 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3312 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, 3313 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, 3314 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, 3315 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, 3316 [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr, 3317 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 3318 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, 3319 [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr, 3320 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, 3321 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, 3322 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, 3323 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3324 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3325 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3326 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3327 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3328 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3329 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 3330 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3331 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3332 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, 3333 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3334 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3335 [GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr, 3336 [GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr, 3337 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 3338 [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr, 3339 [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr, 3340 [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr, 3341 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, 3342 [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr, 3343 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 3344 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 3345 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 3346 [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr, 3347 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 3348 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 3349 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 3350 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 3351 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 3352 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 3353 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 3354 [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr, 3355 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 3356 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 3357 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 3358 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 3359 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, 3360 [GCC_PCIE_PHY_REFGEN_CLK] = &gcc_pcie_phy_refgen_clk.clkr, 3361 [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr, 3362 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3363 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3364 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3365 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3366 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3367 [GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr, 3368 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3369 [GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr, 3370 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3371 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3372 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3373 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3374 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3375 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3376 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3377 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3378 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3379 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3380 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3381 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3382 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 3383 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 3384 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 3385 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 3386 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3387 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3388 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3389 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3390 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3391 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3392 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3393 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3394 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3395 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3396 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3397 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3398 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 3399 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 3400 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 3401 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 3402 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3403 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3404 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 3405 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3406 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3407 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3408 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3409 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 3410 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 3411 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 3412 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 3413 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 3414 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = 3415 &gcc_tsif_inactivity_timers_clk.clkr, 3416 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 3417 [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr, 3418 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, 3419 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, 3420 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, 3421 [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr, 3422 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr, 3423 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr, 3424 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr, 3425 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr, 3426 [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr, 3427 [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr, 3428 [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr, 3429 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, 3430 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = 3431 &gcc_ufs_card_unipro_core_clk_src.clkr, 3432 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, 3433 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3434 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3435 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3436 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3437 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3438 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3439 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3440 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3441 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 3442 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3443 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3444 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = 3445 &gcc_ufs_phy_unipro_core_clk_src.clkr, 3446 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3447 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3448 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3449 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 3450 &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3451 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3452 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, 3453 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, 3454 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, 3455 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = 3456 &gcc_usb30_sec_mock_utmi_clk_src.clkr, 3457 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, 3458 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 3459 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 3460 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3461 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3462 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3463 [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr, 3464 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, 3465 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, 3466 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, 3467 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, 3468 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, 3469 [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr, 3470 [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr, 3471 [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr, 3472 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, 3473 [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr, 3474 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 3475 [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr, 3476 [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr, 3477 [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr, 3478 [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr, 3479 [GPLL0] = &gpll0.clkr, 3480 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 3481 [GPLL4] = &gpll4.clkr, 3482 [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr, 3483 [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, 3484 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, 3485 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, 3486 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, 3487 #ifdef CONFIG_SDM_LPASSCC_845 3488 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, 3489 [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr, 3490 #endif 3491 }; 3492 3493 static const struct qcom_reset_map gcc_sdm845_resets[] = { 3494 [GCC_MMSS_BCR] = { 0xb000 }, 3495 [GCC_PCIE_0_BCR] = { 0x6b000 }, 3496 [GCC_PCIE_1_BCR] = { 0x8d000 }, 3497 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 3498 [GCC_PDM_BCR] = { 0x33000 }, 3499 [GCC_PRNG_BCR] = { 0x34000 }, 3500 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, 3501 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, 3502 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 3503 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 3504 [GCC_SDCC2_BCR] = { 0x14000 }, 3505 [GCC_SDCC4_BCR] = { 0x16000 }, 3506 [GCC_TSIF_BCR] = { 0x36000 }, 3507 [GCC_UFS_CARD_BCR] = { 0x75000 }, 3508 [GCC_UFS_PHY_BCR] = { 0x77000 }, 3509 [GCC_USB30_PRIM_BCR] = { 0xf000 }, 3510 [GCC_USB30_SEC_BCR] = { 0x10000 }, 3511 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 3512 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 3513 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 3514 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 3515 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 3516 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, 3517 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 3518 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 3519 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, 3520 }; 3521 3522 static struct gdsc *gcc_sdm845_gdscs[] = { 3523 [PCIE_0_GDSC] = &pcie_0_gdsc, 3524 [PCIE_1_GDSC] = &pcie_1_gdsc, 3525 [UFS_CARD_GDSC] = &ufs_card_gdsc, 3526 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 3527 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 3528 [USB30_SEC_GDSC] = &usb30_sec_gdsc, 3529 [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = 3530 &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc, 3531 [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = 3532 &hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc, 3533 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = 3534 &hlos1_vote_aggre_noc_mmu_tbu1_gdsc, 3535 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = 3536 &hlos1_vote_aggre_noc_mmu_tbu2_gdsc, 3537 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = 3538 &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, 3539 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = 3540 &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc, 3541 [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc, 3542 }; 3543 3544 static const struct regmap_config gcc_sdm845_regmap_config = { 3545 .reg_bits = 32, 3546 .reg_stride = 4, 3547 .val_bits = 32, 3548 .max_register = 0x182090, 3549 .fast_io = true, 3550 }; 3551 3552 static const struct qcom_cc_desc gcc_sdm845_desc = { 3553 .config = &gcc_sdm845_regmap_config, 3554 .clks = gcc_sdm845_clocks, 3555 .num_clks = ARRAY_SIZE(gcc_sdm845_clocks), 3556 .resets = gcc_sdm845_resets, 3557 .num_resets = ARRAY_SIZE(gcc_sdm845_resets), 3558 .gdscs = gcc_sdm845_gdscs, 3559 .num_gdscs = ARRAY_SIZE(gcc_sdm845_gdscs), 3560 }; 3561 3562 static const struct of_device_id gcc_sdm845_match_table[] = { 3563 { .compatible = "qcom,gcc-sdm845" }, 3564 { } 3565 }; 3566 MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table); 3567 3568 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3569 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk), 3570 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk), 3571 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk), 3572 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk), 3573 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk), 3574 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk), 3575 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk), 3576 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk), 3577 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk), 3578 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk), 3579 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk), 3580 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk), 3581 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk), 3582 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk), 3583 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk), 3584 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk), 3585 }; 3586 3587 static int gcc_sdm845_probe(struct platform_device *pdev) 3588 { 3589 struct regmap *regmap; 3590 int ret; 3591 3592 regmap = qcom_cc_map(pdev, &gcc_sdm845_desc); 3593 if (IS_ERR(regmap)) 3594 return PTR_ERR(regmap); 3595 3596 /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */ 3597 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3); 3598 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); 3599 3600 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3601 ARRAY_SIZE(gcc_dfs_clocks)); 3602 if (ret) 3603 return ret; 3604 3605 return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap); 3606 } 3607 3608 static struct platform_driver gcc_sdm845_driver = { 3609 .probe = gcc_sdm845_probe, 3610 .driver = { 3611 .name = "gcc-sdm845", 3612 .of_match_table = gcc_sdm845_match_table, 3613 }, 3614 }; 3615 3616 static int __init gcc_sdm845_init(void) 3617 { 3618 return platform_driver_register(&gcc_sdm845_driver); 3619 } 3620 subsys_initcall(gcc_sdm845_init); 3621 3622 static void __exit gcc_sdm845_exit(void) 3623 { 3624 platform_driver_unregister(&gcc_sdm845_driver); 3625 } 3626 module_exit(gcc_sdm845_exit); 3627 3628 MODULE_DESCRIPTION("QTI GCC SDM845 Driver"); 3629 MODULE_LICENSE("GPL v2"); 3630 MODULE_ALIAS("platform:gcc-sdm845"); 3631