1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/err.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_device.h> 12 #include <linux/regmap.h> 13 14 #include <dt-bindings/clock/qcom,gcc-sc7180.h> 15 16 #include "clk-alpha-pll.h" 17 #include "clk-branch.h" 18 #include "clk-rcg.h" 19 #include "clk-regmap.h" 20 #include "common.h" 21 #include "gdsc.h" 22 #include "reset.h" 23 24 enum { 25 P_BI_TCXO, 26 P_CORE_BI_PLL_TEST_SE, 27 P_GPLL0_OUT_EVEN, 28 P_GPLL0_OUT_MAIN, 29 P_GPLL1_OUT_MAIN, 30 P_GPLL4_OUT_MAIN, 31 P_GPLL6_OUT_MAIN, 32 P_GPLL7_OUT_MAIN, 33 P_SLEEP_CLK, 34 }; 35 36 static struct clk_alpha_pll gpll0 = { 37 .offset = 0x0, 38 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 39 .clkr = { 40 .enable_reg = 0x52010, 41 .enable_mask = BIT(0), 42 .hw.init = &(struct clk_init_data){ 43 .name = "gpll0", 44 .parent_data = &(const struct clk_parent_data){ 45 .fw_name = "bi_tcxo", 46 .name = "bi_tcxo", 47 }, 48 .num_parents = 1, 49 .ops = &clk_alpha_pll_fixed_fabia_ops, 50 }, 51 }, 52 }; 53 54 static const struct clk_div_table post_div_table_gpll0_out_even[] = { 55 { 0x1, 2 }, 56 { } 57 }; 58 59 static struct clk_alpha_pll_postdiv gpll0_out_even = { 60 .offset = 0x0, 61 .post_div_shift = 8, 62 .post_div_table = post_div_table_gpll0_out_even, 63 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even), 64 .width = 4, 65 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 66 .clkr.hw.init = &(struct clk_init_data){ 67 .name = "gpll0_out_even", 68 .parent_data = &(const struct clk_parent_data){ 69 .hw = &gpll0.clkr.hw, 70 }, 71 .num_parents = 1, 72 .ops = &clk_alpha_pll_postdiv_fabia_ops, 73 }, 74 }; 75 76 static struct clk_fixed_factor gcc_pll0_main_div_cdiv = { 77 .mult = 1, 78 .div = 2, 79 .hw.init = &(struct clk_init_data){ 80 .name = "gcc_pll0_main_div_cdiv", 81 .parent_data = &(const struct clk_parent_data){ 82 .hw = &gpll0.clkr.hw, 83 }, 84 .num_parents = 1, 85 .ops = &clk_fixed_factor_ops, 86 }, 87 }; 88 89 static struct clk_alpha_pll gpll1 = { 90 .offset = 0x01000, 91 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 92 .clkr = { 93 .enable_reg = 0x52010, 94 .enable_mask = BIT(1), 95 .hw.init = &(struct clk_init_data){ 96 .name = "gpll1", 97 .parent_data = &(const struct clk_parent_data){ 98 .fw_name = "bi_tcxo", 99 .name = "bi_tcxo", 100 }, 101 .num_parents = 1, 102 .ops = &clk_alpha_pll_fixed_fabia_ops, 103 }, 104 }, 105 }; 106 107 static struct clk_alpha_pll gpll4 = { 108 .offset = 0x76000, 109 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 110 .clkr = { 111 .enable_reg = 0x52010, 112 .enable_mask = BIT(4), 113 .hw.init = &(struct clk_init_data){ 114 .name = "gpll4", 115 .parent_data = &(const struct clk_parent_data){ 116 .fw_name = "bi_tcxo", 117 .name = "bi_tcxo", 118 }, 119 .num_parents = 1, 120 .ops = &clk_alpha_pll_fixed_fabia_ops, 121 }, 122 }, 123 }; 124 125 static struct clk_alpha_pll gpll6 = { 126 .offset = 0x13000, 127 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 128 .clkr = { 129 .enable_reg = 0x52010, 130 .enable_mask = BIT(6), 131 .hw.init = &(struct clk_init_data){ 132 .name = "gpll6", 133 .parent_data = &(const struct clk_parent_data){ 134 .fw_name = "bi_tcxo", 135 .name = "bi_tcxo", 136 }, 137 .num_parents = 1, 138 .ops = &clk_alpha_pll_fixed_fabia_ops, 139 }, 140 }, 141 }; 142 143 static struct clk_alpha_pll gpll7 = { 144 .offset = 0x27000, 145 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 146 .clkr = { 147 .enable_reg = 0x52010, 148 .enable_mask = BIT(7), 149 .hw.init = &(struct clk_init_data){ 150 .name = "gpll7", 151 .parent_data = &(const struct clk_parent_data){ 152 .fw_name = "bi_tcxo", 153 .name = "bi_tcxo", 154 }, 155 .num_parents = 1, 156 .ops = &clk_alpha_pll_fixed_fabia_ops, 157 }, 158 }, 159 }; 160 161 static const struct parent_map gcc_parent_map_0[] = { 162 { P_BI_TCXO, 0 }, 163 { P_GPLL0_OUT_MAIN, 1 }, 164 { P_GPLL0_OUT_EVEN, 6 }, 165 { P_CORE_BI_PLL_TEST_SE, 7 }, 166 }; 167 168 static const struct clk_parent_data gcc_parent_data_0[] = { 169 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 170 { .hw = &gpll0.clkr.hw }, 171 { .hw = &gpll0_out_even.clkr.hw }, 172 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 173 }; 174 175 static const struct clk_parent_data gcc_parent_data_0_ao[] = { 176 { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" }, 177 { .hw = &gpll0.clkr.hw }, 178 { .hw = &gpll0_out_even.clkr.hw }, 179 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 180 }; 181 182 static const struct parent_map gcc_parent_map_1[] = { 183 { P_BI_TCXO, 0 }, 184 { P_GPLL0_OUT_MAIN, 1 }, 185 { P_GPLL6_OUT_MAIN, 2 }, 186 { P_GPLL0_OUT_EVEN, 6 }, 187 { P_CORE_BI_PLL_TEST_SE, 7 }, 188 }; 189 190 static const struct clk_parent_data gcc_parent_data_1[] = { 191 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 192 { .hw = &gpll0.clkr.hw }, 193 { .hw = &gpll6.clkr.hw }, 194 { .hw = &gpll0_out_even.clkr.hw }, 195 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 196 }; 197 198 static const struct parent_map gcc_parent_map_2[] = { 199 { P_BI_TCXO, 0 }, 200 { P_GPLL0_OUT_MAIN, 1 }, 201 { P_GPLL1_OUT_MAIN, 4 }, 202 { P_GPLL4_OUT_MAIN, 5 }, 203 { P_GPLL0_OUT_EVEN, 6 }, 204 { P_CORE_BI_PLL_TEST_SE, 7 }, 205 }; 206 207 static const struct clk_parent_data gcc_parent_data_2[] = { 208 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 209 { .hw = &gpll0.clkr.hw }, 210 { .hw = &gpll1.clkr.hw }, 211 { .hw = &gpll4.clkr.hw }, 212 { .hw = &gpll0_out_even.clkr.hw }, 213 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 214 }; 215 216 static const struct parent_map gcc_parent_map_3[] = { 217 { P_BI_TCXO, 0 }, 218 { P_GPLL0_OUT_MAIN, 1 }, 219 { P_CORE_BI_PLL_TEST_SE, 7 }, 220 }; 221 222 static const struct clk_parent_data gcc_parent_data_3[] = { 223 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 224 { .hw = &gpll0.clkr.hw }, 225 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 226 }; 227 228 static const struct parent_map gcc_parent_map_4[] = { 229 { P_BI_TCXO, 0 }, 230 { P_GPLL0_OUT_MAIN, 1 }, 231 { P_SLEEP_CLK, 5 }, 232 { P_GPLL0_OUT_EVEN, 6 }, 233 { P_CORE_BI_PLL_TEST_SE, 7 }, 234 }; 235 236 static const struct clk_parent_data gcc_parent_data_4[] = { 237 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 238 { .hw = &gpll0.clkr.hw }, 239 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 240 { .hw = &gpll0_out_even.clkr.hw }, 241 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 242 }; 243 244 static const struct parent_map gcc_parent_map_5[] = { 245 { P_BI_TCXO, 0 }, 246 { P_GPLL0_OUT_MAIN, 1 }, 247 { P_GPLL7_OUT_MAIN, 3 }, 248 { P_GPLL0_OUT_EVEN, 6 }, 249 { P_CORE_BI_PLL_TEST_SE, 7 }, 250 }; 251 252 static const struct clk_parent_data gcc_parent_data_5[] = { 253 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 254 { .hw = &gpll0.clkr.hw }, 255 { .hw = &gpll7.clkr.hw }, 256 { .hw = &gpll0_out_even.clkr.hw }, 257 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 258 }; 259 260 static const struct parent_map gcc_parent_map_6[] = { 261 { P_BI_TCXO, 0 }, 262 { P_GPLL0_OUT_MAIN, 1 }, 263 { P_SLEEP_CLK, 5 }, 264 { P_CORE_BI_PLL_TEST_SE, 7 }, 265 }; 266 267 static const struct clk_parent_data gcc_parent_data_6[] = { 268 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 269 { .hw = &gpll0.clkr.hw }, 270 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 271 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 272 }; 273 274 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { 275 F(19200000, P_BI_TCXO, 1, 0, 0), 276 { } 277 }; 278 279 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { 280 .cmd_rcgr = 0x48014, 281 .mnd_width = 0, 282 .hid_width = 5, 283 .parent_map = gcc_parent_map_0, 284 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, 285 .clkr.hw.init = &(struct clk_init_data){ 286 .name = "gcc_cpuss_ahb_clk_src", 287 .parent_data = gcc_parent_data_0_ao, 288 .num_parents = 4, 289 .flags = CLK_SET_RATE_PARENT, 290 .ops = &clk_rcg2_ops, 291 }, 292 }; 293 294 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 295 F(19200000, P_BI_TCXO, 1, 0, 0), 296 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 297 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 298 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 299 F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0), 300 { } 301 }; 302 303 static struct clk_rcg2 gcc_gp1_clk_src = { 304 .cmd_rcgr = 0x64004, 305 .mnd_width = 8, 306 .hid_width = 5, 307 .parent_map = gcc_parent_map_4, 308 .freq_tbl = ftbl_gcc_gp1_clk_src, 309 .clkr.hw.init = &(struct clk_init_data){ 310 .name = "gcc_gp1_clk_src", 311 .parent_data = gcc_parent_data_4, 312 .num_parents = 5, 313 .ops = &clk_rcg2_ops, 314 }, 315 }; 316 317 static struct clk_rcg2 gcc_gp2_clk_src = { 318 .cmd_rcgr = 0x65004, 319 .mnd_width = 8, 320 .hid_width = 5, 321 .parent_map = gcc_parent_map_4, 322 .freq_tbl = ftbl_gcc_gp1_clk_src, 323 .clkr.hw.init = &(struct clk_init_data){ 324 .name = "gcc_gp2_clk_src", 325 .parent_data = gcc_parent_data_4, 326 .num_parents = 5, 327 .ops = &clk_rcg2_ops, 328 }, 329 }; 330 331 static struct clk_rcg2 gcc_gp3_clk_src = { 332 .cmd_rcgr = 0x66004, 333 .mnd_width = 8, 334 .hid_width = 5, 335 .parent_map = gcc_parent_map_4, 336 .freq_tbl = ftbl_gcc_gp1_clk_src, 337 .clkr.hw.init = &(struct clk_init_data){ 338 .name = "gcc_gp3_clk_src", 339 .parent_data = gcc_parent_data_4, 340 .num_parents = 5, 341 .ops = &clk_rcg2_ops, 342 }, 343 }; 344 345 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 346 F(19200000, P_BI_TCXO, 1, 0, 0), 347 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0), 348 { } 349 }; 350 351 static struct clk_rcg2 gcc_pdm2_clk_src = { 352 .cmd_rcgr = 0x33010, 353 .mnd_width = 0, 354 .hid_width = 5, 355 .parent_map = gcc_parent_map_0, 356 .freq_tbl = ftbl_gcc_pdm2_clk_src, 357 .clkr.hw.init = &(struct clk_init_data){ 358 .name = "gcc_pdm2_clk_src", 359 .parent_data = gcc_parent_data_0, 360 .num_parents = 4, 361 .ops = &clk_rcg2_ops, 362 }, 363 }; 364 365 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = { 366 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 367 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 368 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 369 { } 370 }; 371 372 static struct clk_rcg2 gcc_qspi_core_clk_src = { 373 .cmd_rcgr = 0x4b00c, 374 .mnd_width = 0, 375 .hid_width = 5, 376 .parent_map = gcc_parent_map_2, 377 .freq_tbl = ftbl_gcc_qspi_core_clk_src, 378 .clkr.hw.init = &(struct clk_init_data){ 379 .name = "gcc_qspi_core_clk_src", 380 .parent_data = gcc_parent_data_2, 381 .num_parents = 6, 382 .ops = &clk_rcg2_ops, 383 }, 384 }; 385 386 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 387 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), 388 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), 389 F(19200000, P_BI_TCXO, 1, 0, 0), 390 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), 391 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), 392 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), 393 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), 394 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 395 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), 396 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), 397 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 398 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), 399 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), 400 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), 401 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), 402 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0), 403 { } 404 }; 405 406 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 407 .name = "gcc_qupv3_wrap0_s0_clk_src", 408 .parent_data = gcc_parent_data_0, 409 .num_parents = 4, 410 .ops = &clk_rcg2_ops, 411 }; 412 413 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 414 .cmd_rcgr = 0x17034, 415 .mnd_width = 16, 416 .hid_width = 5, 417 .parent_map = gcc_parent_map_0, 418 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 419 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 420 }; 421 422 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 423 .name = "gcc_qupv3_wrap0_s1_clk_src", 424 .parent_data = gcc_parent_data_0, 425 .num_parents = 4, 426 .ops = &clk_rcg2_ops, 427 }; 428 429 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 430 .cmd_rcgr = 0x17164, 431 .mnd_width = 16, 432 .hid_width = 5, 433 .parent_map = gcc_parent_map_0, 434 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 435 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 436 }; 437 438 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 439 .name = "gcc_qupv3_wrap0_s2_clk_src", 440 .parent_data = gcc_parent_data_0, 441 .num_parents = 4, 442 .ops = &clk_rcg2_ops, 443 }; 444 445 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 446 .cmd_rcgr = 0x17294, 447 .mnd_width = 16, 448 .hid_width = 5, 449 .parent_map = gcc_parent_map_0, 450 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 451 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 452 }; 453 454 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 455 .name = "gcc_qupv3_wrap0_s3_clk_src", 456 .parent_data = gcc_parent_data_0, 457 .num_parents = 4, 458 .ops = &clk_rcg2_ops, 459 }; 460 461 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 462 .cmd_rcgr = 0x173c4, 463 .mnd_width = 16, 464 .hid_width = 5, 465 .parent_map = gcc_parent_map_0, 466 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 467 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 468 }; 469 470 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 471 .name = "gcc_qupv3_wrap0_s4_clk_src", 472 .parent_data = gcc_parent_data_0, 473 .num_parents = 4, 474 .ops = &clk_rcg2_ops, 475 }; 476 477 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 478 .cmd_rcgr = 0x174f4, 479 .mnd_width = 16, 480 .hid_width = 5, 481 .parent_map = gcc_parent_map_0, 482 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 483 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 484 }; 485 486 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 487 .name = "gcc_qupv3_wrap0_s5_clk_src", 488 .parent_data = gcc_parent_data_0, 489 .num_parents = 4, 490 .ops = &clk_rcg2_ops, 491 }; 492 493 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 494 .cmd_rcgr = 0x17624, 495 .mnd_width = 16, 496 .hid_width = 5, 497 .parent_map = gcc_parent_map_0, 498 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 499 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 500 }; 501 502 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 503 .name = "gcc_qupv3_wrap1_s0_clk_src", 504 .parent_data = gcc_parent_data_0, 505 .num_parents = 4, 506 .ops = &clk_rcg2_ops, 507 }; 508 509 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 510 .cmd_rcgr = 0x18018, 511 .mnd_width = 16, 512 .hid_width = 5, 513 .parent_map = gcc_parent_map_0, 514 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 515 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 516 }; 517 518 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 519 .name = "gcc_qupv3_wrap1_s1_clk_src", 520 .parent_data = gcc_parent_data_0, 521 .num_parents = 4, 522 .ops = &clk_rcg2_ops, 523 }; 524 525 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 526 .cmd_rcgr = 0x18148, 527 .mnd_width = 16, 528 .hid_width = 5, 529 .parent_map = gcc_parent_map_0, 530 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 531 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 532 }; 533 534 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 535 .name = "gcc_qupv3_wrap1_s2_clk_src", 536 .parent_data = gcc_parent_data_0, 537 .num_parents = 4, 538 .ops = &clk_rcg2_ops, 539 }; 540 541 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 542 .cmd_rcgr = 0x18278, 543 .mnd_width = 16, 544 .hid_width = 5, 545 .parent_map = gcc_parent_map_0, 546 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 547 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 548 }; 549 550 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 551 .name = "gcc_qupv3_wrap1_s3_clk_src", 552 .parent_data = gcc_parent_data_0, 553 .num_parents = 4, 554 .ops = &clk_rcg2_ops, 555 }; 556 557 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 558 .cmd_rcgr = 0x183a8, 559 .mnd_width = 16, 560 .hid_width = 5, 561 .parent_map = gcc_parent_map_0, 562 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 563 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 564 }; 565 566 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 567 .name = "gcc_qupv3_wrap1_s4_clk_src", 568 .parent_data = gcc_parent_data_0, 569 .num_parents = 4, 570 .ops = &clk_rcg2_ops, 571 }; 572 573 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 574 .cmd_rcgr = 0x184d8, 575 .mnd_width = 16, 576 .hid_width = 5, 577 .parent_map = gcc_parent_map_0, 578 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 579 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 580 }; 581 582 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 583 .name = "gcc_qupv3_wrap1_s5_clk_src", 584 .parent_data = gcc_parent_data_0, 585 .num_parents = 4, 586 .ops = &clk_rcg2_ops, 587 }; 588 589 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 590 .cmd_rcgr = 0x18608, 591 .mnd_width = 16, 592 .hid_width = 5, 593 .parent_map = gcc_parent_map_0, 594 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 595 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 596 }; 597 598 599 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 600 F(144000, P_BI_TCXO, 16, 3, 25), 601 F(400000, P_BI_TCXO, 12, 1, 4), 602 F(19200000, P_BI_TCXO, 1, 0, 0), 603 F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3), 604 F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), 605 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 606 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 607 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 608 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 609 { } 610 }; 611 612 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 613 .cmd_rcgr = 0x12028, 614 .mnd_width = 8, 615 .hid_width = 5, 616 .parent_map = gcc_parent_map_1, 617 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 618 .clkr.hw.init = &(struct clk_init_data){ 619 .name = "gcc_sdcc1_apps_clk_src", 620 .parent_data = gcc_parent_data_1, 621 .num_parents = 5, 622 .ops = &clk_rcg2_ops, 623 }, 624 }; 625 626 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 627 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 628 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 629 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 630 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 631 { } 632 }; 633 634 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 635 .cmd_rcgr = 0x12010, 636 .mnd_width = 0, 637 .hid_width = 5, 638 .parent_map = gcc_parent_map_0, 639 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 640 .clkr.hw.init = &(struct clk_init_data){ 641 .name = "gcc_sdcc1_ice_core_clk_src", 642 .parent_data = gcc_parent_data_0, 643 .num_parents = 4, 644 .ops = &clk_rcg2_ops, 645 }, 646 }; 647 648 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 649 F(400000, P_BI_TCXO, 12, 1, 4), 650 F(9600000, P_BI_TCXO, 2, 0, 0), 651 F(19200000, P_BI_TCXO, 1, 0, 0), 652 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 653 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 654 F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0), 655 { } 656 }; 657 658 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 659 .cmd_rcgr = 0x1400c, 660 .mnd_width = 8, 661 .hid_width = 5, 662 .parent_map = gcc_parent_map_5, 663 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 664 .clkr.hw.init = &(struct clk_init_data){ 665 .name = "gcc_sdcc2_apps_clk_src", 666 .parent_data = gcc_parent_data_5, 667 .num_parents = 5, 668 .ops = &clk_rcg2_ops, 669 }, 670 }; 671 672 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 673 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 674 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 675 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 676 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 677 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 678 { } 679 }; 680 681 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 682 .cmd_rcgr = 0x77020, 683 .mnd_width = 8, 684 .hid_width = 5, 685 .parent_map = gcc_parent_map_0, 686 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 687 .clkr.hw.init = &(struct clk_init_data){ 688 .name = "gcc_ufs_phy_axi_clk_src", 689 .parent_data = gcc_parent_data_0, 690 .num_parents = 4, 691 .ops = &clk_rcg2_ops, 692 }, 693 }; 694 695 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 696 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 697 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 698 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 699 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 700 { } 701 }; 702 703 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 704 .cmd_rcgr = 0x77048, 705 .mnd_width = 0, 706 .hid_width = 5, 707 .parent_map = gcc_parent_map_0, 708 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 709 .clkr.hw.init = &(struct clk_init_data){ 710 .name = "gcc_ufs_phy_ice_core_clk_src", 711 .parent_data = gcc_parent_data_0, 712 .num_parents = 4, 713 .ops = &clk_rcg2_ops, 714 }, 715 }; 716 717 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 718 F(9600000, P_BI_TCXO, 2, 0, 0), 719 F(19200000, P_BI_TCXO, 1, 0, 0), 720 { } 721 }; 722 723 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 724 .cmd_rcgr = 0x77098, 725 .mnd_width = 0, 726 .hid_width = 5, 727 .parent_map = gcc_parent_map_3, 728 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 729 .clkr.hw.init = &(struct clk_init_data){ 730 .name = "gcc_ufs_phy_phy_aux_clk_src", 731 .parent_data = gcc_parent_data_3, 732 .num_parents = 3, 733 .ops = &clk_rcg2_ops, 734 }, 735 }; 736 737 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { 738 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 739 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 740 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 741 { } 742 }; 743 744 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 745 .cmd_rcgr = 0x77060, 746 .mnd_width = 0, 747 .hid_width = 5, 748 .parent_map = gcc_parent_map_0, 749 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, 750 .clkr.hw.init = &(struct clk_init_data){ 751 .name = "gcc_ufs_phy_unipro_core_clk_src", 752 .parent_data = gcc_parent_data_0, 753 .num_parents = 4, 754 .ops = &clk_rcg2_ops, 755 }, 756 }; 757 758 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 759 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), 760 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 761 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 762 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 763 { } 764 }; 765 766 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 767 .cmd_rcgr = 0xf01c, 768 .mnd_width = 8, 769 .hid_width = 5, 770 .parent_map = gcc_parent_map_0, 771 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 772 .clkr.hw.init = &(struct clk_init_data){ 773 .name = "gcc_usb30_prim_master_clk_src", 774 .parent_data = gcc_parent_data_0, 775 .num_parents = 4, 776 .ops = &clk_rcg2_ops, 777 }, 778 }; 779 780 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 781 F(19200000, P_BI_TCXO, 1, 0, 0), 782 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0), 783 { } 784 }; 785 786 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 787 .cmd_rcgr = 0xf034, 788 .mnd_width = 0, 789 .hid_width = 5, 790 .parent_map = gcc_parent_map_0, 791 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 792 .clkr.hw.init = &(struct clk_init_data){ 793 .name = "gcc_usb30_prim_mock_utmi_clk_src", 794 .parent_data = gcc_parent_data_0, 795 .num_parents = 4, 796 .ops = &clk_rcg2_ops, 797 }, 798 }; 799 800 static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = { 801 F(19200000, P_BI_TCXO, 1, 0, 0), 802 { } 803 }; 804 805 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 806 .cmd_rcgr = 0xf060, 807 .mnd_width = 0, 808 .hid_width = 5, 809 .parent_map = gcc_parent_map_6, 810 .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src, 811 .clkr.hw.init = &(struct clk_init_data){ 812 .name = "gcc_usb3_prim_phy_aux_clk_src", 813 .parent_data = gcc_parent_data_6, 814 .num_parents = 4, 815 .ops = &clk_rcg2_ops, 816 }, 817 }; 818 819 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 820 .halt_reg = 0x82024, 821 .halt_check = BRANCH_HALT_DELAY, 822 .hwcg_reg = 0x82024, 823 .hwcg_bit = 1, 824 .clkr = { 825 .enable_reg = 0x82024, 826 .enable_mask = BIT(0), 827 .hw.init = &(struct clk_init_data){ 828 .name = "gcc_aggre_ufs_phy_axi_clk", 829 .parent_data = &(const struct clk_parent_data){ 830 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 831 }, 832 .num_parents = 1, 833 .flags = CLK_SET_RATE_PARENT, 834 .ops = &clk_branch2_ops, 835 }, 836 }, 837 }; 838 839 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 840 .halt_reg = 0x8201c, 841 .halt_check = BRANCH_HALT, 842 .clkr = { 843 .enable_reg = 0x8201c, 844 .enable_mask = BIT(0), 845 .hw.init = &(struct clk_init_data){ 846 .name = "gcc_aggre_usb3_prim_axi_clk", 847 .parent_data = &(const struct clk_parent_data){ 848 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 849 }, 850 .num_parents = 1, 851 .flags = CLK_SET_RATE_PARENT, 852 .ops = &clk_branch2_ops, 853 }, 854 }, 855 }; 856 857 static struct clk_branch gcc_boot_rom_ahb_clk = { 858 .halt_reg = 0x38004, 859 .halt_check = BRANCH_HALT_VOTED, 860 .hwcg_reg = 0x38004, 861 .hwcg_bit = 1, 862 .clkr = { 863 .enable_reg = 0x52000, 864 .enable_mask = BIT(10), 865 .hw.init = &(struct clk_init_data){ 866 .name = "gcc_boot_rom_ahb_clk", 867 .ops = &clk_branch2_ops, 868 }, 869 }, 870 }; 871 872 static struct clk_branch gcc_camera_ahb_clk = { 873 .halt_reg = 0xb008, 874 .halt_check = BRANCH_HALT, 875 .hwcg_reg = 0xb008, 876 .hwcg_bit = 1, 877 .clkr = { 878 .enable_reg = 0xb008, 879 .enable_mask = BIT(0), 880 .hw.init = &(struct clk_init_data){ 881 .name = "gcc_camera_ahb_clk", 882 .ops = &clk_branch2_ops, 883 }, 884 }, 885 }; 886 887 static struct clk_branch gcc_camera_hf_axi_clk = { 888 .halt_reg = 0xb020, 889 .halt_check = BRANCH_HALT, 890 .clkr = { 891 .enable_reg = 0xb020, 892 .enable_mask = BIT(0), 893 .hw.init = &(struct clk_init_data){ 894 .name = "gcc_camera_hf_axi_clk", 895 .ops = &clk_branch2_ops, 896 }, 897 }, 898 }; 899 900 static struct clk_branch gcc_camera_throttle_hf_axi_clk = { 901 .halt_reg = 0xb080, 902 .halt_check = BRANCH_HALT, 903 .hwcg_reg = 0xb080, 904 .hwcg_bit = 1, 905 .clkr = { 906 .enable_reg = 0xb080, 907 .enable_mask = BIT(0), 908 .hw.init = &(struct clk_init_data){ 909 .name = "gcc_camera_throttle_hf_axi_clk", 910 .ops = &clk_branch2_ops, 911 }, 912 }, 913 }; 914 915 static struct clk_branch gcc_camera_xo_clk = { 916 .halt_reg = 0xb02c, 917 .halt_check = BRANCH_HALT, 918 .clkr = { 919 .enable_reg = 0xb02c, 920 .enable_mask = BIT(0), 921 .hw.init = &(struct clk_init_data){ 922 .name = "gcc_camera_xo_clk", 923 .ops = &clk_branch2_ops, 924 }, 925 }, 926 }; 927 928 static struct clk_branch gcc_ce1_ahb_clk = { 929 .halt_reg = 0x4100c, 930 .halt_check = BRANCH_HALT_VOTED, 931 .hwcg_reg = 0x4100c, 932 .hwcg_bit = 1, 933 .clkr = { 934 .enable_reg = 0x52000, 935 .enable_mask = BIT(3), 936 .hw.init = &(struct clk_init_data){ 937 .name = "gcc_ce1_ahb_clk", 938 .ops = &clk_branch2_ops, 939 }, 940 }, 941 }; 942 943 static struct clk_branch gcc_ce1_axi_clk = { 944 .halt_reg = 0x41008, 945 .halt_check = BRANCH_HALT_VOTED, 946 .clkr = { 947 .enable_reg = 0x52000, 948 .enable_mask = BIT(4), 949 .hw.init = &(struct clk_init_data){ 950 .name = "gcc_ce1_axi_clk", 951 .ops = &clk_branch2_ops, 952 }, 953 }, 954 }; 955 956 static struct clk_branch gcc_ce1_clk = { 957 .halt_reg = 0x41004, 958 .halt_check = BRANCH_HALT_VOTED, 959 .clkr = { 960 .enable_reg = 0x52000, 961 .enable_mask = BIT(5), 962 .hw.init = &(struct clk_init_data){ 963 .name = "gcc_ce1_clk", 964 .ops = &clk_branch2_ops, 965 }, 966 }, 967 }; 968 969 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 970 .halt_reg = 0x502c, 971 .halt_check = BRANCH_HALT, 972 .clkr = { 973 .enable_reg = 0x502c, 974 .enable_mask = BIT(0), 975 .hw.init = &(struct clk_init_data){ 976 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 977 .parent_data = &(const struct clk_parent_data){ 978 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 979 }, 980 .num_parents = 1, 981 .flags = CLK_SET_RATE_PARENT, 982 .ops = &clk_branch2_ops, 983 }, 984 }, 985 }; 986 987 /* For CPUSS functionality the AHB clock needs to be left enabled */ 988 static struct clk_branch gcc_cpuss_ahb_clk = { 989 .halt_reg = 0x48000, 990 .halt_check = BRANCH_HALT_VOTED, 991 .clkr = { 992 .enable_reg = 0x52000, 993 .enable_mask = BIT(21), 994 .hw.init = &(struct clk_init_data){ 995 .name = "gcc_cpuss_ahb_clk", 996 .parent_data = &(const struct clk_parent_data){ 997 .hw = &gcc_cpuss_ahb_clk_src.clkr.hw, 998 }, 999 .num_parents = 1, 1000 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 1001 .ops = &clk_branch2_ops, 1002 }, 1003 }, 1004 }; 1005 1006 static struct clk_branch gcc_cpuss_rbcpr_clk = { 1007 .halt_reg = 0x48008, 1008 .halt_check = BRANCH_HALT, 1009 .clkr = { 1010 .enable_reg = 0x48008, 1011 .enable_mask = BIT(0), 1012 .hw.init = &(struct clk_init_data){ 1013 .name = "gcc_cpuss_rbcpr_clk", 1014 .ops = &clk_branch2_ops, 1015 }, 1016 }, 1017 }; 1018 1019 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1020 .halt_reg = 0x4452c, 1021 .halt_check = BRANCH_VOTED, 1022 .clkr = { 1023 .enable_reg = 0x4452c, 1024 .enable_mask = BIT(0), 1025 .hw.init = &(struct clk_init_data){ 1026 .name = "gcc_ddrss_gpu_axi_clk", 1027 .ops = &clk_branch2_ops, 1028 }, 1029 }, 1030 }; 1031 1032 static struct clk_branch gcc_disp_gpll0_clk_src = { 1033 .halt_check = BRANCH_HALT_DELAY, 1034 .clkr = { 1035 .enable_reg = 0x52000, 1036 .enable_mask = BIT(18), 1037 .hw.init = &(struct clk_init_data){ 1038 .name = "gcc_disp_gpll0_clk_src", 1039 .parent_data = &(const struct clk_parent_data){ 1040 .hw = &gpll0.clkr.hw, 1041 }, 1042 .num_parents = 1, 1043 .ops = &clk_branch2_ops, 1044 }, 1045 }, 1046 }; 1047 1048 static struct clk_branch gcc_disp_gpll0_div_clk_src = { 1049 .halt_check = BRANCH_HALT_DELAY, 1050 .clkr = { 1051 .enable_reg = 0x52000, 1052 .enable_mask = BIT(19), 1053 .hw.init = &(struct clk_init_data){ 1054 .name = "gcc_disp_gpll0_div_clk_src", 1055 .parent_data = &(const struct clk_parent_data){ 1056 .hw = &gcc_pll0_main_div_cdiv.hw, 1057 }, 1058 .num_parents = 1, 1059 .ops = &clk_branch2_ops, 1060 }, 1061 }, 1062 }; 1063 1064 static struct clk_branch gcc_disp_hf_axi_clk = { 1065 .halt_reg = 0xb024, 1066 .halt_check = BRANCH_HALT, 1067 .clkr = { 1068 .enable_reg = 0xb024, 1069 .enable_mask = BIT(0), 1070 .hw.init = &(struct clk_init_data){ 1071 .name = "gcc_disp_hf_axi_clk", 1072 .ops = &clk_branch2_ops, 1073 }, 1074 }, 1075 }; 1076 1077 static struct clk_branch gcc_disp_throttle_hf_axi_clk = { 1078 .halt_reg = 0xb084, 1079 .halt_check = BRANCH_HALT, 1080 .hwcg_reg = 0xb084, 1081 .hwcg_bit = 1, 1082 .clkr = { 1083 .enable_reg = 0xb084, 1084 .enable_mask = BIT(0), 1085 .hw.init = &(struct clk_init_data){ 1086 .name = "gcc_disp_throttle_hf_axi_clk", 1087 .ops = &clk_branch2_ops, 1088 }, 1089 }, 1090 }; 1091 1092 static struct clk_branch gcc_disp_xo_clk = { 1093 .halt_reg = 0xb030, 1094 .halt_check = BRANCH_HALT, 1095 .clkr = { 1096 .enable_reg = 0xb030, 1097 .enable_mask = BIT(0), 1098 .hw.init = &(struct clk_init_data){ 1099 .name = "gcc_disp_xo_clk", 1100 .ops = &clk_branch2_ops, 1101 }, 1102 }, 1103 }; 1104 1105 static struct clk_branch gcc_gp1_clk = { 1106 .halt_reg = 0x64000, 1107 .halt_check = BRANCH_HALT, 1108 .clkr = { 1109 .enable_reg = 0x64000, 1110 .enable_mask = BIT(0), 1111 .hw.init = &(struct clk_init_data){ 1112 .name = "gcc_gp1_clk", 1113 .parent_data = &(const struct clk_parent_data){ 1114 .hw = &gcc_gp1_clk_src.clkr.hw, 1115 }, 1116 .num_parents = 1, 1117 .flags = CLK_SET_RATE_PARENT, 1118 .ops = &clk_branch2_ops, 1119 }, 1120 }, 1121 }; 1122 1123 static struct clk_branch gcc_gp2_clk = { 1124 .halt_reg = 0x65000, 1125 .halt_check = BRANCH_HALT, 1126 .clkr = { 1127 .enable_reg = 0x65000, 1128 .enable_mask = BIT(0), 1129 .hw.init = &(struct clk_init_data){ 1130 .name = "gcc_gp2_clk", 1131 .parent_data = &(const struct clk_parent_data){ 1132 .hw = &gcc_gp2_clk_src.clkr.hw, 1133 }, 1134 .num_parents = 1, 1135 .flags = CLK_SET_RATE_PARENT, 1136 .ops = &clk_branch2_ops, 1137 }, 1138 }, 1139 }; 1140 1141 static struct clk_branch gcc_gp3_clk = { 1142 .halt_reg = 0x66000, 1143 .halt_check = BRANCH_HALT, 1144 .clkr = { 1145 .enable_reg = 0x66000, 1146 .enable_mask = BIT(0), 1147 .hw.init = &(struct clk_init_data){ 1148 .name = "gcc_gp3_clk", 1149 .parent_data = &(const struct clk_parent_data){ 1150 .hw = &gcc_gp3_clk_src.clkr.hw, 1151 }, 1152 .num_parents = 1, 1153 .flags = CLK_SET_RATE_PARENT, 1154 .ops = &clk_branch2_ops, 1155 }, 1156 }, 1157 }; 1158 1159 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1160 .halt_check = BRANCH_HALT_DELAY, 1161 .clkr = { 1162 .enable_reg = 0x52000, 1163 .enable_mask = BIT(15), 1164 .hw.init = &(struct clk_init_data){ 1165 .name = "gcc_gpu_gpll0_clk_src", 1166 .parent_data = &(const struct clk_parent_data){ 1167 .hw = &gpll0.clkr.hw, 1168 }, 1169 .num_parents = 1, 1170 .ops = &clk_branch2_ops, 1171 }, 1172 }, 1173 }; 1174 1175 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1176 .halt_check = BRANCH_HALT_DELAY, 1177 .clkr = { 1178 .enable_reg = 0x52000, 1179 .enable_mask = BIT(16), 1180 .hw.init = &(struct clk_init_data){ 1181 .name = "gcc_gpu_gpll0_div_clk_src", 1182 .parent_data = &(const struct clk_parent_data){ 1183 .hw = &gcc_pll0_main_div_cdiv.hw, 1184 }, 1185 .num_parents = 1, 1186 .ops = &clk_branch2_ops, 1187 }, 1188 }, 1189 }; 1190 1191 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1192 .halt_reg = 0x7100c, 1193 .halt_check = BRANCH_VOTED, 1194 .clkr = { 1195 .enable_reg = 0x7100c, 1196 .enable_mask = BIT(0), 1197 .hw.init = &(struct clk_init_data){ 1198 .name = "gcc_gpu_memnoc_gfx_clk", 1199 .ops = &clk_branch2_ops, 1200 }, 1201 }, 1202 }; 1203 1204 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1205 .halt_reg = 0x71018, 1206 .halt_check = BRANCH_HALT, 1207 .clkr = { 1208 .enable_reg = 0x71018, 1209 .enable_mask = BIT(0), 1210 .hw.init = &(struct clk_init_data){ 1211 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1212 .ops = &clk_branch2_ops, 1213 }, 1214 }, 1215 }; 1216 1217 static struct clk_branch gcc_npu_axi_clk = { 1218 .halt_reg = 0x4d008, 1219 .halt_check = BRANCH_HALT, 1220 .clkr = { 1221 .enable_reg = 0x4d008, 1222 .enable_mask = BIT(0), 1223 .hw.init = &(struct clk_init_data){ 1224 .name = "gcc_npu_axi_clk", 1225 .ops = &clk_branch2_ops, 1226 }, 1227 }, 1228 }; 1229 1230 static struct clk_branch gcc_npu_bwmon_axi_clk = { 1231 .halt_reg = 0x73008, 1232 .halt_check = BRANCH_HALT, 1233 .clkr = { 1234 .enable_reg = 0x73008, 1235 .enable_mask = BIT(0), 1236 .hw.init = &(struct clk_init_data){ 1237 .name = "gcc_npu_bwmon_axi_clk", 1238 .ops = &clk_branch2_ops, 1239 }, 1240 }, 1241 }; 1242 1243 static struct clk_branch gcc_npu_bwmon_dma_cfg_ahb_clk = { 1244 .halt_reg = 0x73018, 1245 .halt_check = BRANCH_HALT, 1246 .clkr = { 1247 .enable_reg = 0x73018, 1248 .enable_mask = BIT(0), 1249 .hw.init = &(struct clk_init_data){ 1250 .name = "gcc_npu_bwmon_dma_cfg_ahb_clk", 1251 .ops = &clk_branch2_ops, 1252 }, 1253 }, 1254 }; 1255 1256 static struct clk_branch gcc_npu_bwmon_dsp_cfg_ahb_clk = { 1257 .halt_reg = 0x7301c, 1258 .halt_check = BRANCH_HALT, 1259 .clkr = { 1260 .enable_reg = 0x7301c, 1261 .enable_mask = BIT(0), 1262 .hw.init = &(struct clk_init_data){ 1263 .name = "gcc_npu_bwmon_dsp_cfg_ahb_clk", 1264 .ops = &clk_branch2_ops, 1265 }, 1266 }, 1267 }; 1268 1269 static struct clk_branch gcc_npu_cfg_ahb_clk = { 1270 .halt_reg = 0x4d004, 1271 .halt_check = BRANCH_HALT, 1272 .hwcg_reg = 0x4d004, 1273 .hwcg_bit = 1, 1274 .clkr = { 1275 .enable_reg = 0x4d004, 1276 .enable_mask = BIT(0), 1277 .hw.init = &(struct clk_init_data){ 1278 .name = "gcc_npu_cfg_ahb_clk", 1279 .ops = &clk_branch2_ops, 1280 }, 1281 }, 1282 }; 1283 1284 static struct clk_branch gcc_npu_dma_clk = { 1285 .halt_reg = 0x4d1a0, 1286 .halt_check = BRANCH_HALT, 1287 .hwcg_reg = 0x4d1a0, 1288 .hwcg_bit = 1, 1289 .clkr = { 1290 .enable_reg = 0x4d1a0, 1291 .enable_mask = BIT(0), 1292 .hw.init = &(struct clk_init_data){ 1293 .name = "gcc_npu_dma_clk", 1294 .ops = &clk_branch2_ops, 1295 }, 1296 }, 1297 }; 1298 1299 static struct clk_branch gcc_npu_gpll0_clk_src = { 1300 .halt_check = BRANCH_HALT_DELAY, 1301 .clkr = { 1302 .enable_reg = 0x52000, 1303 .enable_mask = BIT(25), 1304 .hw.init = &(struct clk_init_data){ 1305 .name = "gcc_npu_gpll0_clk_src", 1306 .parent_data = &(const struct clk_parent_data){ 1307 .hw = &gpll0.clkr.hw, 1308 }, 1309 .num_parents = 1, 1310 .ops = &clk_branch2_ops, 1311 }, 1312 }, 1313 }; 1314 1315 static struct clk_branch gcc_npu_gpll0_div_clk_src = { 1316 .halt_check = BRANCH_HALT_DELAY, 1317 .clkr = { 1318 .enable_reg = 0x52000, 1319 .enable_mask = BIT(26), 1320 .hw.init = &(struct clk_init_data){ 1321 .name = "gcc_npu_gpll0_div_clk_src", 1322 .parent_data = &(const struct clk_parent_data){ 1323 .hw = &gcc_pll0_main_div_cdiv.hw, 1324 }, 1325 .num_parents = 1, 1326 .flags = CLK_SET_RATE_PARENT, 1327 .ops = &clk_branch2_ops, 1328 }, 1329 }, 1330 }; 1331 1332 static struct clk_branch gcc_pdm2_clk = { 1333 .halt_reg = 0x3300c, 1334 .halt_check = BRANCH_HALT, 1335 .clkr = { 1336 .enable_reg = 0x3300c, 1337 .enable_mask = BIT(0), 1338 .hw.init = &(struct clk_init_data){ 1339 .name = "gcc_pdm2_clk", 1340 .parent_data = &(const struct clk_parent_data){ 1341 .hw = &gcc_pdm2_clk_src.clkr.hw, 1342 }, 1343 .num_parents = 1, 1344 .flags = CLK_SET_RATE_PARENT, 1345 .ops = &clk_branch2_ops, 1346 }, 1347 }, 1348 }; 1349 1350 static struct clk_branch gcc_pdm_ahb_clk = { 1351 .halt_reg = 0x33004, 1352 .halt_check = BRANCH_HALT, 1353 .hwcg_reg = 0x33004, 1354 .hwcg_bit = 1, 1355 .clkr = { 1356 .enable_reg = 0x33004, 1357 .enable_mask = BIT(0), 1358 .hw.init = &(struct clk_init_data){ 1359 .name = "gcc_pdm_ahb_clk", 1360 .ops = &clk_branch2_ops, 1361 }, 1362 }, 1363 }; 1364 1365 static struct clk_branch gcc_pdm_xo4_clk = { 1366 .halt_reg = 0x33008, 1367 .halt_check = BRANCH_HALT, 1368 .clkr = { 1369 .enable_reg = 0x33008, 1370 .enable_mask = BIT(0), 1371 .hw.init = &(struct clk_init_data){ 1372 .name = "gcc_pdm_xo4_clk", 1373 .ops = &clk_branch2_ops, 1374 }, 1375 }, 1376 }; 1377 1378 static struct clk_branch gcc_prng_ahb_clk = { 1379 .halt_reg = 0x34004, 1380 .halt_check = BRANCH_HALT_VOTED, 1381 .hwcg_reg = 0x34004, 1382 .hwcg_bit = 1, 1383 .clkr = { 1384 .enable_reg = 0x52000, 1385 .enable_mask = BIT(13), 1386 .hw.init = &(struct clk_init_data){ 1387 .name = "gcc_prng_ahb_clk", 1388 .ops = &clk_branch2_ops, 1389 }, 1390 }, 1391 }; 1392 1393 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = { 1394 .halt_reg = 0x4b004, 1395 .halt_check = BRANCH_HALT, 1396 .hwcg_reg = 0x4b004, 1397 .hwcg_bit = 1, 1398 .clkr = { 1399 .enable_reg = 0x4b004, 1400 .enable_mask = BIT(0), 1401 .hw.init = &(struct clk_init_data){ 1402 .name = "gcc_qspi_cnoc_periph_ahb_clk", 1403 .ops = &clk_branch2_ops, 1404 }, 1405 }, 1406 }; 1407 1408 static struct clk_branch gcc_qspi_core_clk = { 1409 .halt_reg = 0x4b008, 1410 .halt_check = BRANCH_HALT, 1411 .clkr = { 1412 .enable_reg = 0x4b008, 1413 .enable_mask = BIT(0), 1414 .hw.init = &(struct clk_init_data){ 1415 .name = "gcc_qspi_core_clk", 1416 .parent_data = &(const struct clk_parent_data){ 1417 .hw = &gcc_qspi_core_clk_src.clkr.hw, 1418 }, 1419 .num_parents = 1, 1420 .flags = CLK_SET_RATE_PARENT, 1421 .ops = &clk_branch2_ops, 1422 }, 1423 }, 1424 }; 1425 1426 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 1427 .halt_reg = 0x17014, 1428 .halt_check = BRANCH_HALT_VOTED, 1429 .clkr = { 1430 .enable_reg = 0x52008, 1431 .enable_mask = BIT(9), 1432 .hw.init = &(struct clk_init_data){ 1433 .name = "gcc_qupv3_wrap0_core_2x_clk", 1434 .ops = &clk_branch2_ops, 1435 }, 1436 }, 1437 }; 1438 1439 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 1440 .halt_reg = 0x1700c, 1441 .halt_check = BRANCH_HALT_VOTED, 1442 .clkr = { 1443 .enable_reg = 0x52008, 1444 .enable_mask = BIT(8), 1445 .hw.init = &(struct clk_init_data){ 1446 .name = "gcc_qupv3_wrap0_core_clk", 1447 .ops = &clk_branch2_ops, 1448 }, 1449 }, 1450 }; 1451 1452 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 1453 .halt_reg = 0x17030, 1454 .halt_check = BRANCH_HALT_VOTED, 1455 .clkr = { 1456 .enable_reg = 0x52008, 1457 .enable_mask = BIT(10), 1458 .hw.init = &(struct clk_init_data){ 1459 .name = "gcc_qupv3_wrap0_s0_clk", 1460 .parent_data = &(const struct clk_parent_data){ 1461 .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 1462 }, 1463 .num_parents = 1, 1464 .flags = CLK_SET_RATE_PARENT, 1465 .ops = &clk_branch2_ops, 1466 }, 1467 }, 1468 }; 1469 1470 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 1471 .halt_reg = 0x17160, 1472 .halt_check = BRANCH_HALT_VOTED, 1473 .clkr = { 1474 .enable_reg = 0x52008, 1475 .enable_mask = BIT(11), 1476 .hw.init = &(struct clk_init_data){ 1477 .name = "gcc_qupv3_wrap0_s1_clk", 1478 .parent_data = &(const struct clk_parent_data){ 1479 .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 1480 }, 1481 .num_parents = 1, 1482 .flags = CLK_SET_RATE_PARENT, 1483 .ops = &clk_branch2_ops, 1484 }, 1485 }, 1486 }; 1487 1488 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 1489 .halt_reg = 0x17290, 1490 .halt_check = BRANCH_HALT_VOTED, 1491 .clkr = { 1492 .enable_reg = 0x52008, 1493 .enable_mask = BIT(12), 1494 .hw.init = &(struct clk_init_data){ 1495 .name = "gcc_qupv3_wrap0_s2_clk", 1496 .parent_data = &(const struct clk_parent_data){ 1497 .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 1498 }, 1499 .num_parents = 1, 1500 .flags = CLK_SET_RATE_PARENT, 1501 .ops = &clk_branch2_ops, 1502 }, 1503 }, 1504 }; 1505 1506 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 1507 .halt_reg = 0x173c0, 1508 .halt_check = BRANCH_HALT_VOTED, 1509 .clkr = { 1510 .enable_reg = 0x52008, 1511 .enable_mask = BIT(13), 1512 .hw.init = &(struct clk_init_data){ 1513 .name = "gcc_qupv3_wrap0_s3_clk", 1514 .parent_data = &(const struct clk_parent_data){ 1515 .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 1516 }, 1517 .num_parents = 1, 1518 .flags = CLK_SET_RATE_PARENT, 1519 .ops = &clk_branch2_ops, 1520 }, 1521 }, 1522 }; 1523 1524 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 1525 .halt_reg = 0x174f0, 1526 .halt_check = BRANCH_HALT_VOTED, 1527 .clkr = { 1528 .enable_reg = 0x52008, 1529 .enable_mask = BIT(14), 1530 .hw.init = &(struct clk_init_data){ 1531 .name = "gcc_qupv3_wrap0_s4_clk", 1532 .parent_data = &(const struct clk_parent_data){ 1533 .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 1534 }, 1535 .num_parents = 1, 1536 .flags = CLK_SET_RATE_PARENT, 1537 .ops = &clk_branch2_ops, 1538 }, 1539 }, 1540 }; 1541 1542 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 1543 .halt_reg = 0x17620, 1544 .halt_check = BRANCH_HALT_VOTED, 1545 .clkr = { 1546 .enable_reg = 0x52008, 1547 .enable_mask = BIT(15), 1548 .hw.init = &(struct clk_init_data){ 1549 .name = "gcc_qupv3_wrap0_s5_clk", 1550 .parent_data = &(const struct clk_parent_data){ 1551 .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 1552 }, 1553 .num_parents = 1, 1554 .flags = CLK_SET_RATE_PARENT, 1555 .ops = &clk_branch2_ops, 1556 }, 1557 }, 1558 }; 1559 1560 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 1561 .halt_reg = 0x18004, 1562 .halt_check = BRANCH_HALT_VOTED, 1563 .clkr = { 1564 .enable_reg = 0x52008, 1565 .enable_mask = BIT(18), 1566 .hw.init = &(struct clk_init_data){ 1567 .name = "gcc_qupv3_wrap1_core_2x_clk", 1568 .ops = &clk_branch2_ops, 1569 }, 1570 }, 1571 }; 1572 1573 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 1574 .halt_reg = 0x18008, 1575 .halt_check = BRANCH_HALT_VOTED, 1576 .clkr = { 1577 .enable_reg = 0x52008, 1578 .enable_mask = BIT(19), 1579 .hw.init = &(struct clk_init_data){ 1580 .name = "gcc_qupv3_wrap1_core_clk", 1581 .ops = &clk_branch2_ops, 1582 }, 1583 }, 1584 }; 1585 1586 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 1587 .halt_reg = 0x18014, 1588 .halt_check = BRANCH_HALT_VOTED, 1589 .clkr = { 1590 .enable_reg = 0x52008, 1591 .enable_mask = BIT(22), 1592 .hw.init = &(struct clk_init_data){ 1593 .name = "gcc_qupv3_wrap1_s0_clk", 1594 .parent_data = &(const struct clk_parent_data){ 1595 .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 1596 }, 1597 .num_parents = 1, 1598 .flags = CLK_SET_RATE_PARENT, 1599 .ops = &clk_branch2_ops, 1600 }, 1601 }, 1602 }; 1603 1604 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 1605 .halt_reg = 0x18144, 1606 .halt_check = BRANCH_HALT_VOTED, 1607 .clkr = { 1608 .enable_reg = 0x52008, 1609 .enable_mask = BIT(23), 1610 .hw.init = &(struct clk_init_data){ 1611 .name = "gcc_qupv3_wrap1_s1_clk", 1612 .parent_data = &(const struct clk_parent_data){ 1613 .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 1614 }, 1615 .num_parents = 1, 1616 .flags = CLK_SET_RATE_PARENT, 1617 .ops = &clk_branch2_ops, 1618 }, 1619 }, 1620 }; 1621 1622 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 1623 .halt_reg = 0x18274, 1624 .halt_check = BRANCH_HALT_VOTED, 1625 .clkr = { 1626 .enable_reg = 0x52008, 1627 .enable_mask = BIT(24), 1628 .hw.init = &(struct clk_init_data){ 1629 .name = "gcc_qupv3_wrap1_s2_clk", 1630 .parent_data = &(const struct clk_parent_data){ 1631 .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 1632 }, 1633 .num_parents = 1, 1634 .flags = CLK_SET_RATE_PARENT, 1635 .ops = &clk_branch2_ops, 1636 }, 1637 }, 1638 }; 1639 1640 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 1641 .halt_reg = 0x183a4, 1642 .halt_check = BRANCH_HALT_VOTED, 1643 .clkr = { 1644 .enable_reg = 0x52008, 1645 .enable_mask = BIT(25), 1646 .hw.init = &(struct clk_init_data){ 1647 .name = "gcc_qupv3_wrap1_s3_clk", 1648 .parent_data = &(const struct clk_parent_data){ 1649 .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 1650 }, 1651 .num_parents = 1, 1652 .flags = CLK_SET_RATE_PARENT, 1653 .ops = &clk_branch2_ops, 1654 }, 1655 }, 1656 }; 1657 1658 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 1659 .halt_reg = 0x184d4, 1660 .halt_check = BRANCH_HALT_VOTED, 1661 .clkr = { 1662 .enable_reg = 0x52008, 1663 .enable_mask = BIT(26), 1664 .hw.init = &(struct clk_init_data){ 1665 .name = "gcc_qupv3_wrap1_s4_clk", 1666 .parent_data = &(const struct clk_parent_data){ 1667 .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 1668 }, 1669 .num_parents = 1, 1670 .flags = CLK_SET_RATE_PARENT, 1671 .ops = &clk_branch2_ops, 1672 }, 1673 }, 1674 }; 1675 1676 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 1677 .halt_reg = 0x18604, 1678 .halt_check = BRANCH_HALT_VOTED, 1679 .clkr = { 1680 .enable_reg = 0x52008, 1681 .enable_mask = BIT(27), 1682 .hw.init = &(struct clk_init_data){ 1683 .name = "gcc_qupv3_wrap1_s5_clk", 1684 .parent_data = &(const struct clk_parent_data){ 1685 .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 1686 }, 1687 .num_parents = 1, 1688 .flags = CLK_SET_RATE_PARENT, 1689 .ops = &clk_branch2_ops, 1690 }, 1691 }, 1692 }; 1693 1694 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 1695 .halt_reg = 0x17004, 1696 .halt_check = BRANCH_HALT_VOTED, 1697 .clkr = { 1698 .enable_reg = 0x52008, 1699 .enable_mask = BIT(6), 1700 .hw.init = &(struct clk_init_data){ 1701 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 1702 .ops = &clk_branch2_ops, 1703 }, 1704 }, 1705 }; 1706 1707 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 1708 .halt_reg = 0x17008, 1709 .halt_check = BRANCH_HALT_VOTED, 1710 .hwcg_reg = 0x17008, 1711 .hwcg_bit = 1, 1712 .clkr = { 1713 .enable_reg = 0x52008, 1714 .enable_mask = BIT(7), 1715 .hw.init = &(struct clk_init_data){ 1716 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 1717 .ops = &clk_branch2_ops, 1718 }, 1719 }, 1720 }; 1721 1722 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 1723 .halt_reg = 0x1800c, 1724 .halt_check = BRANCH_HALT_VOTED, 1725 .clkr = { 1726 .enable_reg = 0x52008, 1727 .enable_mask = BIT(20), 1728 .hw.init = &(struct clk_init_data){ 1729 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 1730 .ops = &clk_branch2_ops, 1731 }, 1732 }, 1733 }; 1734 1735 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 1736 .halt_reg = 0x18010, 1737 .halt_check = BRANCH_HALT_VOTED, 1738 .hwcg_reg = 0x18010, 1739 .hwcg_bit = 1, 1740 .clkr = { 1741 .enable_reg = 0x52008, 1742 .enable_mask = BIT(21), 1743 .hw.init = &(struct clk_init_data){ 1744 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 1745 .ops = &clk_branch2_ops, 1746 }, 1747 }, 1748 }; 1749 1750 static struct clk_branch gcc_sdcc1_ahb_clk = { 1751 .halt_reg = 0x12008, 1752 .halt_check = BRANCH_HALT, 1753 .clkr = { 1754 .enable_reg = 0x12008, 1755 .enable_mask = BIT(0), 1756 .hw.init = &(struct clk_init_data){ 1757 .name = "gcc_sdcc1_ahb_clk", 1758 .ops = &clk_branch2_ops, 1759 }, 1760 }, 1761 }; 1762 1763 static struct clk_branch gcc_sdcc1_apps_clk = { 1764 .halt_reg = 0x1200c, 1765 .halt_check = BRANCH_HALT, 1766 .clkr = { 1767 .enable_reg = 0x1200c, 1768 .enable_mask = BIT(0), 1769 .hw.init = &(struct clk_init_data){ 1770 .name = "gcc_sdcc1_apps_clk", 1771 .parent_data = &(const struct clk_parent_data){ 1772 .hw = &gcc_sdcc1_apps_clk_src.clkr.hw, 1773 }, 1774 .num_parents = 1, 1775 .flags = CLK_SET_RATE_PARENT, 1776 .ops = &clk_branch2_ops, 1777 }, 1778 }, 1779 }; 1780 1781 static struct clk_branch gcc_sdcc1_ice_core_clk = { 1782 .halt_reg = 0x12040, 1783 .halt_check = BRANCH_HALT, 1784 .clkr = { 1785 .enable_reg = 0x12040, 1786 .enable_mask = BIT(0), 1787 .hw.init = &(struct clk_init_data){ 1788 .name = "gcc_sdcc1_ice_core_clk", 1789 .parent_data = &(const struct clk_parent_data){ 1790 .hw = &gcc_sdcc1_ice_core_clk_src.clkr.hw, 1791 }, 1792 .num_parents = 1, 1793 .flags = CLK_SET_RATE_PARENT, 1794 .ops = &clk_branch2_ops, 1795 }, 1796 }, 1797 }; 1798 1799 static struct clk_branch gcc_sdcc2_ahb_clk = { 1800 .halt_reg = 0x14008, 1801 .halt_check = BRANCH_HALT, 1802 .clkr = { 1803 .enable_reg = 0x14008, 1804 .enable_mask = BIT(0), 1805 .hw.init = &(struct clk_init_data){ 1806 .name = "gcc_sdcc2_ahb_clk", 1807 .ops = &clk_branch2_ops, 1808 }, 1809 }, 1810 }; 1811 1812 static struct clk_branch gcc_sdcc2_apps_clk = { 1813 .halt_reg = 0x14004, 1814 .halt_check = BRANCH_HALT, 1815 .clkr = { 1816 .enable_reg = 0x14004, 1817 .enable_mask = BIT(0), 1818 .hw.init = &(struct clk_init_data){ 1819 .name = "gcc_sdcc2_apps_clk", 1820 .parent_data = &(const struct clk_parent_data){ 1821 .hw = &gcc_sdcc2_apps_clk_src.clkr.hw, 1822 }, 1823 .num_parents = 1, 1824 .flags = CLK_SET_RATE_PARENT, 1825 .ops = &clk_branch2_ops, 1826 }, 1827 }, 1828 }; 1829 1830 /* For CPUSS functionality the SYS NOC clock needs to be left enabled */ 1831 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 1832 .halt_reg = 0x4144, 1833 .halt_check = BRANCH_HALT_VOTED, 1834 .clkr = { 1835 .enable_reg = 0x52000, 1836 .enable_mask = BIT(0), 1837 .hw.init = &(struct clk_init_data){ 1838 .name = "gcc_sys_noc_cpuss_ahb_clk", 1839 .parent_data = &(const struct clk_parent_data){ 1840 .hw = &gcc_cpuss_ahb_clk_src.clkr.hw, 1841 }, 1842 .num_parents = 1, 1843 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 1844 .ops = &clk_branch2_ops, 1845 }, 1846 }, 1847 }; 1848 1849 static struct clk_branch gcc_ufs_mem_clkref_clk = { 1850 .halt_reg = 0x8c000, 1851 .halt_check = BRANCH_HALT, 1852 .clkr = { 1853 .enable_reg = 0x8c000, 1854 .enable_mask = BIT(0), 1855 .hw.init = &(struct clk_init_data){ 1856 .name = "gcc_ufs_mem_clkref_clk", 1857 .ops = &clk_branch2_ops, 1858 }, 1859 }, 1860 }; 1861 1862 static struct clk_branch gcc_ufs_phy_ahb_clk = { 1863 .halt_reg = 0x77014, 1864 .halt_check = BRANCH_HALT, 1865 .hwcg_reg = 0x77014, 1866 .hwcg_bit = 1, 1867 .clkr = { 1868 .enable_reg = 0x77014, 1869 .enable_mask = BIT(0), 1870 .hw.init = &(struct clk_init_data){ 1871 .name = "gcc_ufs_phy_ahb_clk", 1872 .ops = &clk_branch2_ops, 1873 }, 1874 }, 1875 }; 1876 1877 static struct clk_branch gcc_ufs_phy_axi_clk = { 1878 .halt_reg = 0x77038, 1879 .halt_check = BRANCH_HALT, 1880 .hwcg_reg = 0x77038, 1881 .hwcg_bit = 1, 1882 .clkr = { 1883 .enable_reg = 0x77038, 1884 .enable_mask = BIT(0), 1885 .hw.init = &(struct clk_init_data){ 1886 .name = "gcc_ufs_phy_axi_clk", 1887 .parent_data = &(const struct clk_parent_data){ 1888 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 1889 }, 1890 .num_parents = 1, 1891 .flags = CLK_SET_RATE_PARENT, 1892 .ops = &clk_branch2_ops, 1893 }, 1894 }, 1895 }; 1896 1897 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 1898 .halt_reg = 0x77090, 1899 .halt_check = BRANCH_HALT, 1900 .hwcg_reg = 0x77090, 1901 .hwcg_bit = 1, 1902 .clkr = { 1903 .enable_reg = 0x77090, 1904 .enable_mask = BIT(0), 1905 .hw.init = &(struct clk_init_data){ 1906 .name = "gcc_ufs_phy_ice_core_clk", 1907 .parent_data = &(const struct clk_parent_data){ 1908 .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 1909 }, 1910 .num_parents = 1, 1911 .flags = CLK_SET_RATE_PARENT, 1912 .ops = &clk_branch2_ops, 1913 }, 1914 }, 1915 }; 1916 1917 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 1918 .halt_reg = 0x77094, 1919 .halt_check = BRANCH_HALT, 1920 .hwcg_reg = 0x77094, 1921 .hwcg_bit = 1, 1922 .clkr = { 1923 .enable_reg = 0x77094, 1924 .enable_mask = BIT(0), 1925 .hw.init = &(struct clk_init_data){ 1926 .name = "gcc_ufs_phy_phy_aux_clk", 1927 .parent_data = &(const struct clk_parent_data){ 1928 .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 1929 }, 1930 .num_parents = 1, 1931 .flags = CLK_SET_RATE_PARENT, 1932 .ops = &clk_branch2_ops, 1933 }, 1934 }, 1935 }; 1936 1937 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 1938 .halt_reg = 0x7701c, 1939 .halt_check = BRANCH_HALT_SKIP, 1940 .clkr = { 1941 .enable_reg = 0x7701c, 1942 .enable_mask = BIT(0), 1943 .hw.init = &(struct clk_init_data){ 1944 .name = "gcc_ufs_phy_rx_symbol_0_clk", 1945 .ops = &clk_branch2_ops, 1946 }, 1947 }, 1948 }; 1949 1950 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 1951 .halt_reg = 0x77018, 1952 .halt_check = BRANCH_HALT_SKIP, 1953 .clkr = { 1954 .enable_reg = 0x77018, 1955 .enable_mask = BIT(0), 1956 .hw.init = &(struct clk_init_data){ 1957 .name = "gcc_ufs_phy_tx_symbol_0_clk", 1958 .ops = &clk_branch2_ops, 1959 }, 1960 }, 1961 }; 1962 1963 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 1964 .halt_reg = 0x7708c, 1965 .halt_check = BRANCH_HALT, 1966 .hwcg_reg = 0x7708c, 1967 .hwcg_bit = 1, 1968 .clkr = { 1969 .enable_reg = 0x7708c, 1970 .enable_mask = BIT(0), 1971 .hw.init = &(struct clk_init_data){ 1972 .name = "gcc_ufs_phy_unipro_core_clk", 1973 .parent_data = &(const struct clk_parent_data){ 1974 .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 1975 }, 1976 .num_parents = 1, 1977 .flags = CLK_SET_RATE_PARENT, 1978 .ops = &clk_branch2_ops, 1979 }, 1980 }, 1981 }; 1982 1983 static struct clk_branch gcc_usb30_prim_master_clk = { 1984 .halt_reg = 0xf010, 1985 .halt_check = BRANCH_HALT, 1986 .clkr = { 1987 .enable_reg = 0xf010, 1988 .enable_mask = BIT(0), 1989 .hw.init = &(struct clk_init_data){ 1990 .name = "gcc_usb30_prim_master_clk", 1991 .parent_data = &(const struct clk_parent_data){ 1992 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 1993 }, 1994 .num_parents = 1, 1995 .flags = CLK_SET_RATE_PARENT, 1996 .ops = &clk_branch2_ops, 1997 }, 1998 }, 1999 }; 2000 2001 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2002 .halt_reg = 0xf018, 2003 .halt_check = BRANCH_HALT, 2004 .clkr = { 2005 .enable_reg = 0xf018, 2006 .enable_mask = BIT(0), 2007 .hw.init = &(struct clk_init_data){ 2008 .name = "gcc_usb30_prim_mock_utmi_clk", 2009 .parent_data = &(const struct clk_parent_data){ 2010 .hw = 2011 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 2012 }, 2013 .num_parents = 1, 2014 .flags = CLK_SET_RATE_PARENT, 2015 .ops = &clk_branch2_ops, 2016 }, 2017 }, 2018 }; 2019 2020 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2021 .halt_reg = 0xf014, 2022 .halt_check = BRANCH_HALT, 2023 .clkr = { 2024 .enable_reg = 0xf014, 2025 .enable_mask = BIT(0), 2026 .hw.init = &(struct clk_init_data){ 2027 .name = "gcc_usb30_prim_sleep_clk", 2028 .ops = &clk_branch2_ops, 2029 }, 2030 }, 2031 }; 2032 2033 static struct clk_branch gcc_usb3_prim_clkref_clk = { 2034 .halt_reg = 0x8c010, 2035 .halt_check = BRANCH_HALT, 2036 .clkr = { 2037 .enable_reg = 0x8c010, 2038 .enable_mask = BIT(0), 2039 .hw.init = &(struct clk_init_data){ 2040 .name = "gcc_usb3_prim_clkref_clk", 2041 .ops = &clk_branch2_ops, 2042 }, 2043 }, 2044 }; 2045 2046 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2047 .halt_reg = 0xf050, 2048 .halt_check = BRANCH_HALT, 2049 .clkr = { 2050 .enable_reg = 0xf050, 2051 .enable_mask = BIT(0), 2052 .hw.init = &(struct clk_init_data){ 2053 .name = "gcc_usb3_prim_phy_aux_clk", 2054 .parent_data = &(const struct clk_parent_data){ 2055 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2056 }, 2057 .num_parents = 1, 2058 .flags = CLK_SET_RATE_PARENT, 2059 .ops = &clk_branch2_ops, 2060 }, 2061 }, 2062 }; 2063 2064 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2065 .halt_reg = 0xf054, 2066 .halt_check = BRANCH_HALT, 2067 .clkr = { 2068 .enable_reg = 0xf054, 2069 .enable_mask = BIT(0), 2070 .hw.init = &(struct clk_init_data){ 2071 .name = "gcc_usb3_prim_phy_com_aux_clk", 2072 .parent_data = &(const struct clk_parent_data){ 2073 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2074 }, 2075 .num_parents = 1, 2076 .flags = CLK_SET_RATE_PARENT, 2077 .ops = &clk_branch2_ops, 2078 }, 2079 }, 2080 }; 2081 2082 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2083 .halt_reg = 0xf058, 2084 .halt_check = BRANCH_HALT_SKIP, 2085 .clkr = { 2086 .enable_reg = 0xf058, 2087 .enable_mask = BIT(0), 2088 .hw.init = &(struct clk_init_data){ 2089 .name = "gcc_usb3_prim_phy_pipe_clk", 2090 .ops = &clk_branch2_ops, 2091 }, 2092 }, 2093 }; 2094 2095 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { 2096 .halt_reg = 0x6a004, 2097 .halt_check = BRANCH_HALT, 2098 .hwcg_reg = 0x6a004, 2099 .hwcg_bit = 1, 2100 .clkr = { 2101 .enable_reg = 0x6a004, 2102 .enable_mask = BIT(0), 2103 .hw.init = &(struct clk_init_data){ 2104 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 2105 .ops = &clk_branch2_ops, 2106 }, 2107 }, 2108 }; 2109 2110 static struct clk_branch gcc_video_axi_clk = { 2111 .halt_reg = 0xb01c, 2112 .halt_check = BRANCH_HALT, 2113 .clkr = { 2114 .enable_reg = 0xb01c, 2115 .enable_mask = BIT(0), 2116 .hw.init = &(struct clk_init_data){ 2117 .name = "gcc_video_axi_clk", 2118 .ops = &clk_branch2_ops, 2119 }, 2120 }, 2121 }; 2122 2123 static struct clk_branch gcc_video_gpll0_div_clk_src = { 2124 .halt_check = BRANCH_HALT_DELAY, 2125 .clkr = { 2126 .enable_reg = 0x52000, 2127 .enable_mask = BIT(20), 2128 .hw.init = &(struct clk_init_data){ 2129 .name = "gcc_video_gpll0_div_clk_src", 2130 .parent_data = &(const struct clk_parent_data){ 2131 .hw = &gcc_pll0_main_div_cdiv.hw, 2132 }, 2133 .num_parents = 1, 2134 .flags = CLK_SET_RATE_PARENT, 2135 .ops = &clk_branch2_ops, 2136 }, 2137 }, 2138 }; 2139 2140 static struct clk_branch gcc_video_throttle_axi_clk = { 2141 .halt_reg = 0xb07c, 2142 .halt_check = BRANCH_HALT, 2143 .hwcg_reg = 0xb07c, 2144 .hwcg_bit = 1, 2145 .clkr = { 2146 .enable_reg = 0xb07c, 2147 .enable_mask = BIT(0), 2148 .hw.init = &(struct clk_init_data){ 2149 .name = "gcc_video_throttle_axi_clk", 2150 .ops = &clk_branch2_ops, 2151 }, 2152 }, 2153 }; 2154 2155 static struct clk_branch gcc_video_xo_clk = { 2156 .halt_reg = 0xb028, 2157 .halt_check = BRANCH_HALT, 2158 .clkr = { 2159 .enable_reg = 0xb028, 2160 .enable_mask = BIT(0), 2161 .hw.init = &(struct clk_init_data){ 2162 .name = "gcc_video_xo_clk", 2163 .ops = &clk_branch2_ops, 2164 }, 2165 }, 2166 }; 2167 2168 static struct gdsc ufs_phy_gdsc = { 2169 .gdscr = 0x77004, 2170 .pd = { 2171 .name = "ufs_phy_gdsc", 2172 }, 2173 .pwrsts = PWRSTS_OFF_ON, 2174 }; 2175 2176 static struct gdsc usb30_prim_gdsc = { 2177 .gdscr = 0x0f004, 2178 .pd = { 2179 .name = "usb30_prim_gdsc", 2180 }, 2181 .pwrsts = PWRSTS_OFF_ON, 2182 }; 2183 2184 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = { 2185 .gdscr = 0x7d040, 2186 .pd = { 2187 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", 2188 }, 2189 .pwrsts = PWRSTS_OFF_ON | VOTABLE, 2190 }; 2191 2192 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = { 2193 .gdscr = 0x7d044, 2194 .pd = { 2195 .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc", 2196 }, 2197 .pwrsts = PWRSTS_OFF_ON | VOTABLE, 2198 }; 2199 2200 static struct gdsc *gcc_sc7180_gdscs[] = { 2201 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 2202 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 2203 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = 2204 &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, 2205 [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = 2206 &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc, 2207 }; 2208 2209 2210 static struct clk_hw *gcc_sc7180_hws[] = { 2211 [GCC_GPLL0_MAIN_DIV_CDIV] = &gcc_pll0_main_div_cdiv.hw, 2212 }; 2213 2214 static struct clk_regmap *gcc_sc7180_clocks[] = { 2215 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 2216 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 2217 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2218 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, 2219 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 2220 [GCC_CAMERA_THROTTLE_HF_AXI_CLK] = &gcc_camera_throttle_hf_axi_clk.clkr, 2221 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, 2222 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, 2223 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, 2224 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, 2225 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 2226 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, 2227 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, 2228 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, 2229 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 2230 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, 2231 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, 2232 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 2233 [GCC_DISP_THROTTLE_HF_AXI_CLK] = &gcc_disp_throttle_hf_axi_clk.clkr, 2234 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, 2235 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2236 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 2237 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2238 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 2239 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2240 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 2241 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 2242 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 2243 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 2244 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 2245 [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr, 2246 [GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr, 2247 [GCC_NPU_BWMON_DMA_CFG_AHB_CLK] = &gcc_npu_bwmon_dma_cfg_ahb_clk.clkr, 2248 [GCC_NPU_BWMON_DSP_CFG_AHB_CLK] = &gcc_npu_bwmon_dsp_cfg_ahb_clk.clkr, 2249 [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr, 2250 [GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr, 2251 [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr, 2252 [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr, 2253 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2254 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 2255 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2256 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 2257 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 2258 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, 2259 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, 2260 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, 2261 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 2262 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 2263 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 2264 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 2265 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 2266 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 2267 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 2268 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 2269 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 2270 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 2271 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 2272 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 2273 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 2274 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 2275 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 2276 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 2277 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 2278 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 2279 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 2280 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 2281 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 2282 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 2283 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 2284 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 2285 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 2286 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 2287 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 2288 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 2289 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 2290 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 2291 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 2292 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 2293 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2294 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2295 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 2296 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 2297 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 2298 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2299 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2300 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 2301 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 2302 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, 2303 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 2304 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 2305 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 2306 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 2307 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 2308 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 2309 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 2310 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 2311 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 2312 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 2313 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = 2314 &gcc_ufs_phy_unipro_core_clk_src.clkr, 2315 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 2316 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 2317 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 2318 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 2319 &gcc_usb30_prim_mock_utmi_clk_src.clkr, 2320 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 2321 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 2322 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 2323 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 2324 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 2325 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 2326 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, 2327 [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr, 2328 [GCC_VIDEO_GPLL0_DIV_CLK_SRC] = &gcc_video_gpll0_div_clk_src.clkr, 2329 [GCC_VIDEO_THROTTLE_AXI_CLK] = &gcc_video_throttle_axi_clk.clkr, 2330 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 2331 [GPLL0] = &gpll0.clkr, 2332 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 2333 [GPLL6] = &gpll6.clkr, 2334 [GPLL7] = &gpll7.clkr, 2335 [GPLL4] = &gpll4.clkr, 2336 [GPLL1] = &gpll1.clkr, 2337 }; 2338 2339 static const struct qcom_reset_map gcc_sc7180_resets[] = { 2340 [GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 }, 2341 [GCC_QUSB2PHY_SEC_BCR] = { 0x26004 }, 2342 [GCC_UFS_PHY_BCR] = { 0x77000 }, 2343 [GCC_USB30_PRIM_BCR] = { 0xf000 }, 2344 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 2345 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 2346 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 2347 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 2348 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 2349 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, 2350 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 2351 }; 2352 2353 static struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 2354 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 2355 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 2356 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 2357 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 2358 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 2359 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 2360 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 2361 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 2362 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 2363 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 2364 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 2365 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 2366 }; 2367 2368 static const struct regmap_config gcc_sc7180_regmap_config = { 2369 .reg_bits = 32, 2370 .reg_stride = 4, 2371 .val_bits = 32, 2372 .max_register = 0x18208c, 2373 .fast_io = true, 2374 }; 2375 2376 static const struct qcom_cc_desc gcc_sc7180_desc = { 2377 .config = &gcc_sc7180_regmap_config, 2378 .clk_hws = gcc_sc7180_hws, 2379 .num_clk_hws = ARRAY_SIZE(gcc_sc7180_hws), 2380 .clks = gcc_sc7180_clocks, 2381 .num_clks = ARRAY_SIZE(gcc_sc7180_clocks), 2382 .resets = gcc_sc7180_resets, 2383 .num_resets = ARRAY_SIZE(gcc_sc7180_resets), 2384 .gdscs = gcc_sc7180_gdscs, 2385 .num_gdscs = ARRAY_SIZE(gcc_sc7180_gdscs), 2386 }; 2387 2388 static const struct of_device_id gcc_sc7180_match_table[] = { 2389 { .compatible = "qcom,gcc-sc7180" }, 2390 { } 2391 }; 2392 MODULE_DEVICE_TABLE(of, gcc_sc7180_match_table); 2393 2394 static int gcc_sc7180_probe(struct platform_device *pdev) 2395 { 2396 struct regmap *regmap; 2397 int ret; 2398 2399 regmap = qcom_cc_map(pdev, &gcc_sc7180_desc); 2400 if (IS_ERR(regmap)) 2401 return PTR_ERR(regmap); 2402 2403 /* 2404 * Disable the GPLL0 active input to MM blocks, NPU 2405 * and GPU via MISC registers. 2406 */ 2407 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3); 2408 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); 2409 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); 2410 2411 /* 2412 * Keep the clocks always-ON 2413 * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_DISP_AHB_CLK 2414 * GCC_GPU_CFG_AHB_CLK 2415 */ 2416 regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); 2417 regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); 2418 regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); 2419 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 2420 2421 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 2422 ARRAY_SIZE(gcc_dfs_clocks)); 2423 if (ret) 2424 return ret; 2425 2426 return qcom_cc_really_probe(pdev, &gcc_sc7180_desc, regmap); 2427 } 2428 2429 static struct platform_driver gcc_sc7180_driver = { 2430 .probe = gcc_sc7180_probe, 2431 .driver = { 2432 .name = "gcc-sc7180", 2433 .of_match_table = gcc_sc7180_match_table, 2434 }, 2435 }; 2436 2437 static int __init gcc_sc7180_init(void) 2438 { 2439 return platform_driver_register(&gcc_sc7180_driver); 2440 } 2441 core_initcall(gcc_sc7180_init); 2442 2443 static void __exit gcc_sc7180_exit(void) 2444 { 2445 platform_driver_unregister(&gcc_sc7180_driver); 2446 } 2447 module_exit(gcc_sc7180_exit); 2448 2449 MODULE_DESCRIPTION("QTI GCC SC7180 Driver"); 2450 MODULE_LICENSE("GPL v2"); 2451