1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/err.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_device.h> 12 #include <linux/regmap.h> 13 14 #include <dt-bindings/clock/qcom,gcc-sc7180.h> 15 16 #include "clk-alpha-pll.h" 17 #include "clk-branch.h" 18 #include "clk-rcg.h" 19 #include "clk-regmap.h" 20 #include "common.h" 21 #include "gdsc.h" 22 #include "reset.h" 23 24 enum { 25 P_BI_TCXO, 26 P_CORE_BI_PLL_TEST_SE, 27 P_GPLL0_OUT_EVEN, 28 P_GPLL0_OUT_MAIN, 29 P_GPLL1_OUT_MAIN, 30 P_GPLL4_OUT_MAIN, 31 P_GPLL6_OUT_MAIN, 32 P_GPLL7_OUT_MAIN, 33 P_SLEEP_CLK, 34 }; 35 36 static struct clk_alpha_pll gpll0 = { 37 .offset = 0x0, 38 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 39 .clkr = { 40 .enable_reg = 0x52010, 41 .enable_mask = BIT(0), 42 .hw.init = &(struct clk_init_data){ 43 .name = "gpll0", 44 .parent_data = &(const struct clk_parent_data){ 45 .fw_name = "bi_tcxo", 46 .name = "bi_tcxo", 47 }, 48 .num_parents = 1, 49 .ops = &clk_alpha_pll_fixed_fabia_ops, 50 }, 51 }, 52 }; 53 54 static const struct clk_div_table post_div_table_gpll0_out_even[] = { 55 { 0x1, 2 }, 56 { } 57 }; 58 59 static struct clk_alpha_pll_postdiv gpll0_out_even = { 60 .offset = 0x0, 61 .post_div_shift = 8, 62 .post_div_table = post_div_table_gpll0_out_even, 63 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even), 64 .width = 4, 65 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 66 .clkr.hw.init = &(struct clk_init_data){ 67 .name = "gpll0_out_even", 68 .parent_data = &(const struct clk_parent_data){ 69 .hw = &gpll0.clkr.hw, 70 }, 71 .num_parents = 1, 72 .ops = &clk_alpha_pll_postdiv_fabia_ops, 73 }, 74 }; 75 76 static struct clk_fixed_factor gcc_pll0_main_div_cdiv = { 77 .mult = 1, 78 .div = 2, 79 .hw.init = &(struct clk_init_data){ 80 .name = "gcc_pll0_main_div_cdiv", 81 .parent_data = &(const struct clk_parent_data){ 82 .hw = &gpll0.clkr.hw, 83 }, 84 .num_parents = 1, 85 .ops = &clk_fixed_factor_ops, 86 }, 87 }; 88 89 static struct clk_alpha_pll gpll1 = { 90 .offset = 0x01000, 91 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 92 .clkr = { 93 .enable_reg = 0x52010, 94 .enable_mask = BIT(1), 95 .hw.init = &(struct clk_init_data){ 96 .name = "gpll1", 97 .parent_data = &(const struct clk_parent_data){ 98 .fw_name = "bi_tcxo", 99 .name = "bi_tcxo", 100 }, 101 .num_parents = 1, 102 .ops = &clk_alpha_pll_fixed_fabia_ops, 103 }, 104 }, 105 }; 106 107 static struct clk_alpha_pll gpll4 = { 108 .offset = 0x76000, 109 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 110 .clkr = { 111 .enable_reg = 0x52010, 112 .enable_mask = BIT(4), 113 .hw.init = &(struct clk_init_data){ 114 .name = "gpll4", 115 .parent_data = &(const struct clk_parent_data){ 116 .fw_name = "bi_tcxo", 117 .name = "bi_tcxo", 118 }, 119 .num_parents = 1, 120 .ops = &clk_alpha_pll_fixed_fabia_ops, 121 }, 122 }, 123 }; 124 125 static struct clk_alpha_pll gpll6 = { 126 .offset = 0x13000, 127 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 128 .clkr = { 129 .enable_reg = 0x52010, 130 .enable_mask = BIT(6), 131 .hw.init = &(struct clk_init_data){ 132 .name = "gpll6", 133 .parent_data = &(const struct clk_parent_data){ 134 .fw_name = "bi_tcxo", 135 .name = "bi_tcxo", 136 }, 137 .num_parents = 1, 138 .ops = &clk_alpha_pll_fixed_fabia_ops, 139 }, 140 }, 141 }; 142 143 static struct clk_alpha_pll gpll7 = { 144 .offset = 0x27000, 145 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 146 .clkr = { 147 .enable_reg = 0x52010, 148 .enable_mask = BIT(7), 149 .hw.init = &(struct clk_init_data){ 150 .name = "gpll7", 151 .parent_data = &(const struct clk_parent_data){ 152 .fw_name = "bi_tcxo", 153 .name = "bi_tcxo", 154 }, 155 .num_parents = 1, 156 .ops = &clk_alpha_pll_fixed_fabia_ops, 157 }, 158 }, 159 }; 160 161 static const struct parent_map gcc_parent_map_0[] = { 162 { P_BI_TCXO, 0 }, 163 { P_GPLL0_OUT_MAIN, 1 }, 164 { P_GPLL0_OUT_EVEN, 6 }, 165 { P_CORE_BI_PLL_TEST_SE, 7 }, 166 }; 167 168 static const struct clk_parent_data gcc_parent_data_0[] = { 169 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 170 { .hw = &gpll0.clkr.hw }, 171 { .hw = &gpll0_out_even.clkr.hw }, 172 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 173 }; 174 175 static const struct clk_parent_data gcc_parent_data_0_ao[] = { 176 { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" }, 177 { .hw = &gpll0.clkr.hw }, 178 { .hw = &gpll0_out_even.clkr.hw }, 179 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 180 }; 181 182 static const struct parent_map gcc_parent_map_1[] = { 183 { P_BI_TCXO, 0 }, 184 { P_GPLL0_OUT_MAIN, 1 }, 185 { P_GPLL6_OUT_MAIN, 2 }, 186 { P_GPLL0_OUT_EVEN, 6 }, 187 { P_CORE_BI_PLL_TEST_SE, 7 }, 188 }; 189 190 static const struct clk_parent_data gcc_parent_data_1[] = { 191 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 192 { .hw = &gpll0.clkr.hw }, 193 { .hw = &gpll6.clkr.hw }, 194 { .hw = &gpll0_out_even.clkr.hw }, 195 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 196 }; 197 198 static const struct parent_map gcc_parent_map_2[] = { 199 { P_BI_TCXO, 0 }, 200 { P_GPLL0_OUT_MAIN, 1 }, 201 { P_GPLL1_OUT_MAIN, 4 }, 202 { P_GPLL4_OUT_MAIN, 5 }, 203 { P_GPLL0_OUT_EVEN, 6 }, 204 { P_CORE_BI_PLL_TEST_SE, 7 }, 205 }; 206 207 static const struct clk_parent_data gcc_parent_data_2[] = { 208 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 209 { .hw = &gpll0.clkr.hw }, 210 { .hw = &gpll1.clkr.hw }, 211 { .hw = &gpll4.clkr.hw }, 212 { .hw = &gpll0_out_even.clkr.hw }, 213 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 214 }; 215 216 static const struct parent_map gcc_parent_map_3[] = { 217 { P_BI_TCXO, 0 }, 218 { P_GPLL0_OUT_MAIN, 1 }, 219 { P_CORE_BI_PLL_TEST_SE, 7 }, 220 }; 221 222 static const struct clk_parent_data gcc_parent_data_3[] = { 223 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 224 { .hw = &gpll0.clkr.hw }, 225 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 226 }; 227 228 static const struct parent_map gcc_parent_map_4[] = { 229 { P_BI_TCXO, 0 }, 230 { P_GPLL0_OUT_MAIN, 1 }, 231 { P_SLEEP_CLK, 5 }, 232 { P_GPLL0_OUT_EVEN, 6 }, 233 { P_CORE_BI_PLL_TEST_SE, 7 }, 234 }; 235 236 static const struct clk_parent_data gcc_parent_data_4[] = { 237 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 238 { .hw = &gpll0.clkr.hw }, 239 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 240 { .hw = &gpll0_out_even.clkr.hw }, 241 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 242 }; 243 244 static const struct parent_map gcc_parent_map_5[] = { 245 { P_BI_TCXO, 0 }, 246 { P_GPLL0_OUT_MAIN, 1 }, 247 { P_GPLL7_OUT_MAIN, 3 }, 248 { P_GPLL0_OUT_EVEN, 6 }, 249 { P_CORE_BI_PLL_TEST_SE, 7 }, 250 }; 251 252 static const struct clk_parent_data gcc_parent_data_5[] = { 253 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 254 { .hw = &gpll0.clkr.hw }, 255 { .hw = &gpll7.clkr.hw }, 256 { .hw = &gpll0_out_even.clkr.hw }, 257 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 258 }; 259 260 static const struct parent_map gcc_parent_map_6[] = { 261 { P_BI_TCXO, 0 }, 262 { P_GPLL0_OUT_MAIN, 1 }, 263 { P_SLEEP_CLK, 5 }, 264 { P_CORE_BI_PLL_TEST_SE, 7 }, 265 }; 266 267 static const struct clk_parent_data gcc_parent_data_6[] = { 268 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 269 { .hw = &gpll0.clkr.hw }, 270 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 271 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 272 }; 273 274 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { 275 F(19200000, P_BI_TCXO, 1, 0, 0), 276 { } 277 }; 278 279 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { 280 .cmd_rcgr = 0x48014, 281 .mnd_width = 0, 282 .hid_width = 5, 283 .parent_map = gcc_parent_map_0, 284 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, 285 .clkr.hw.init = &(struct clk_init_data){ 286 .name = "gcc_cpuss_ahb_clk_src", 287 .parent_data = gcc_parent_data_0_ao, 288 .num_parents = 4, 289 .flags = CLK_SET_RATE_PARENT, 290 .ops = &clk_rcg2_ops, 291 }, 292 }; 293 294 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 295 F(19200000, P_BI_TCXO, 1, 0, 0), 296 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 297 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 298 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 299 F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0), 300 { } 301 }; 302 303 static struct clk_rcg2 gcc_gp1_clk_src = { 304 .cmd_rcgr = 0x64004, 305 .mnd_width = 8, 306 .hid_width = 5, 307 .parent_map = gcc_parent_map_4, 308 .freq_tbl = ftbl_gcc_gp1_clk_src, 309 .clkr.hw.init = &(struct clk_init_data){ 310 .name = "gcc_gp1_clk_src", 311 .parent_data = gcc_parent_data_4, 312 .num_parents = 5, 313 .ops = &clk_rcg2_ops, 314 }, 315 }; 316 317 static struct clk_rcg2 gcc_gp2_clk_src = { 318 .cmd_rcgr = 0x65004, 319 .mnd_width = 8, 320 .hid_width = 5, 321 .parent_map = gcc_parent_map_4, 322 .freq_tbl = ftbl_gcc_gp1_clk_src, 323 .clkr.hw.init = &(struct clk_init_data){ 324 .name = "gcc_gp2_clk_src", 325 .parent_data = gcc_parent_data_4, 326 .num_parents = 5, 327 .ops = &clk_rcg2_ops, 328 }, 329 }; 330 331 static struct clk_rcg2 gcc_gp3_clk_src = { 332 .cmd_rcgr = 0x66004, 333 .mnd_width = 8, 334 .hid_width = 5, 335 .parent_map = gcc_parent_map_4, 336 .freq_tbl = ftbl_gcc_gp1_clk_src, 337 .clkr.hw.init = &(struct clk_init_data){ 338 .name = "gcc_gp3_clk_src", 339 .parent_data = gcc_parent_data_4, 340 .num_parents = 5, 341 .ops = &clk_rcg2_ops, 342 }, 343 }; 344 345 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 346 F(19200000, P_BI_TCXO, 1, 0, 0), 347 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0), 348 { } 349 }; 350 351 static struct clk_rcg2 gcc_pdm2_clk_src = { 352 .cmd_rcgr = 0x33010, 353 .mnd_width = 0, 354 .hid_width = 5, 355 .parent_map = gcc_parent_map_0, 356 .freq_tbl = ftbl_gcc_pdm2_clk_src, 357 .clkr.hw.init = &(struct clk_init_data){ 358 .name = "gcc_pdm2_clk_src", 359 .parent_data = gcc_parent_data_0, 360 .num_parents = 4, 361 .ops = &clk_rcg2_ops, 362 }, 363 }; 364 365 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = { 366 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 367 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 368 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 369 { } 370 }; 371 372 static struct clk_rcg2 gcc_qspi_core_clk_src = { 373 .cmd_rcgr = 0x4b00c, 374 .mnd_width = 0, 375 .hid_width = 5, 376 .parent_map = gcc_parent_map_2, 377 .freq_tbl = ftbl_gcc_qspi_core_clk_src, 378 .clkr.hw.init = &(struct clk_init_data){ 379 .name = "gcc_qspi_core_clk_src", 380 .parent_data = gcc_parent_data_2, 381 .num_parents = 6, 382 .ops = &clk_rcg2_ops, 383 }, 384 }; 385 386 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 387 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), 388 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), 389 F(19200000, P_BI_TCXO, 1, 0, 0), 390 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), 391 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), 392 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), 393 F(51200000, P_GPLL6_OUT_MAIN, 7.5, 0, 0), 394 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), 395 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 396 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), 397 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), 398 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 399 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), 400 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), 401 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), 402 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), 403 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0), 404 { } 405 }; 406 407 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 408 .name = "gcc_qupv3_wrap0_s0_clk_src", 409 .parent_data = gcc_parent_data_1, 410 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 411 .ops = &clk_rcg2_ops, 412 }; 413 414 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 415 .cmd_rcgr = 0x17034, 416 .mnd_width = 16, 417 .hid_width = 5, 418 .parent_map = gcc_parent_map_1, 419 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 420 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 421 }; 422 423 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 424 .name = "gcc_qupv3_wrap0_s1_clk_src", 425 .parent_data = gcc_parent_data_1, 426 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 427 .ops = &clk_rcg2_ops, 428 }; 429 430 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 431 .cmd_rcgr = 0x17164, 432 .mnd_width = 16, 433 .hid_width = 5, 434 .parent_map = gcc_parent_map_1, 435 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 436 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 437 }; 438 439 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 440 .name = "gcc_qupv3_wrap0_s2_clk_src", 441 .parent_data = gcc_parent_data_1, 442 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 443 .ops = &clk_rcg2_ops, 444 }; 445 446 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 447 .cmd_rcgr = 0x17294, 448 .mnd_width = 16, 449 .hid_width = 5, 450 .parent_map = gcc_parent_map_1, 451 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 452 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 453 }; 454 455 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 456 .name = "gcc_qupv3_wrap0_s3_clk_src", 457 .parent_data = gcc_parent_data_1, 458 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 459 .ops = &clk_rcg2_ops, 460 }; 461 462 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 463 .cmd_rcgr = 0x173c4, 464 .mnd_width = 16, 465 .hid_width = 5, 466 .parent_map = gcc_parent_map_1, 467 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 468 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 469 }; 470 471 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 472 .name = "gcc_qupv3_wrap0_s4_clk_src", 473 .parent_data = gcc_parent_data_1, 474 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 475 .ops = &clk_rcg2_ops, 476 }; 477 478 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 479 .cmd_rcgr = 0x174f4, 480 .mnd_width = 16, 481 .hid_width = 5, 482 .parent_map = gcc_parent_map_1, 483 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 484 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 485 }; 486 487 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 488 .name = "gcc_qupv3_wrap0_s5_clk_src", 489 .parent_data = gcc_parent_data_1, 490 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 491 .ops = &clk_rcg2_ops, 492 }; 493 494 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 495 .cmd_rcgr = 0x17624, 496 .mnd_width = 16, 497 .hid_width = 5, 498 .parent_map = gcc_parent_map_1, 499 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 500 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 501 }; 502 503 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 504 .name = "gcc_qupv3_wrap1_s0_clk_src", 505 .parent_data = gcc_parent_data_1, 506 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 507 .ops = &clk_rcg2_ops, 508 }; 509 510 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 511 .cmd_rcgr = 0x18018, 512 .mnd_width = 16, 513 .hid_width = 5, 514 .parent_map = gcc_parent_map_1, 515 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 516 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 517 }; 518 519 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 520 .name = "gcc_qupv3_wrap1_s1_clk_src", 521 .parent_data = gcc_parent_data_1, 522 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 523 .ops = &clk_rcg2_ops, 524 }; 525 526 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 527 .cmd_rcgr = 0x18148, 528 .mnd_width = 16, 529 .hid_width = 5, 530 .parent_map = gcc_parent_map_1, 531 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 532 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 533 }; 534 535 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 536 .name = "gcc_qupv3_wrap1_s2_clk_src", 537 .parent_data = gcc_parent_data_1, 538 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 539 .ops = &clk_rcg2_ops, 540 }; 541 542 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 543 .cmd_rcgr = 0x18278, 544 .mnd_width = 16, 545 .hid_width = 5, 546 .parent_map = gcc_parent_map_1, 547 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 548 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 549 }; 550 551 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 552 .name = "gcc_qupv3_wrap1_s3_clk_src", 553 .parent_data = gcc_parent_data_1, 554 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 555 .ops = &clk_rcg2_ops, 556 }; 557 558 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 559 .cmd_rcgr = 0x183a8, 560 .mnd_width = 16, 561 .hid_width = 5, 562 .parent_map = gcc_parent_map_1, 563 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 564 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 565 }; 566 567 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 568 .name = "gcc_qupv3_wrap1_s4_clk_src", 569 .parent_data = gcc_parent_data_1, 570 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 571 .ops = &clk_rcg2_ops, 572 }; 573 574 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 575 .cmd_rcgr = 0x184d8, 576 .mnd_width = 16, 577 .hid_width = 5, 578 .parent_map = gcc_parent_map_1, 579 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 580 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 581 }; 582 583 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 584 .name = "gcc_qupv3_wrap1_s5_clk_src", 585 .parent_data = gcc_parent_data_1, 586 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 587 .ops = &clk_rcg2_ops, 588 }; 589 590 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 591 .cmd_rcgr = 0x18608, 592 .mnd_width = 16, 593 .hid_width = 5, 594 .parent_map = gcc_parent_map_1, 595 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 596 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 597 }; 598 599 600 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 601 F(144000, P_BI_TCXO, 16, 3, 25), 602 F(400000, P_BI_TCXO, 12, 1, 4), 603 F(19200000, P_BI_TCXO, 1, 0, 0), 604 F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3), 605 F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), 606 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 607 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 608 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 609 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 610 { } 611 }; 612 613 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 614 .cmd_rcgr = 0x12028, 615 .mnd_width = 8, 616 .hid_width = 5, 617 .parent_map = gcc_parent_map_1, 618 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 619 .clkr.hw.init = &(struct clk_init_data){ 620 .name = "gcc_sdcc1_apps_clk_src", 621 .parent_data = gcc_parent_data_1, 622 .num_parents = 5, 623 .ops = &clk_rcg2_ops, 624 }, 625 }; 626 627 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 628 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 629 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 630 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 631 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 632 { } 633 }; 634 635 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 636 .cmd_rcgr = 0x12010, 637 .mnd_width = 0, 638 .hid_width = 5, 639 .parent_map = gcc_parent_map_0, 640 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 641 .clkr.hw.init = &(struct clk_init_data){ 642 .name = "gcc_sdcc1_ice_core_clk_src", 643 .parent_data = gcc_parent_data_0, 644 .num_parents = 4, 645 .ops = &clk_rcg2_ops, 646 }, 647 }; 648 649 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 650 F(400000, P_BI_TCXO, 12, 1, 4), 651 F(9600000, P_BI_TCXO, 2, 0, 0), 652 F(19200000, P_BI_TCXO, 1, 0, 0), 653 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 654 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 655 F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0), 656 { } 657 }; 658 659 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 660 .cmd_rcgr = 0x1400c, 661 .mnd_width = 8, 662 .hid_width = 5, 663 .parent_map = gcc_parent_map_5, 664 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 665 .clkr.hw.init = &(struct clk_init_data){ 666 .name = "gcc_sdcc2_apps_clk_src", 667 .parent_data = gcc_parent_data_5, 668 .num_parents = 5, 669 .ops = &clk_rcg2_ops, 670 }, 671 }; 672 673 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 674 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 675 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 676 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 677 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 678 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 679 { } 680 }; 681 682 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 683 .cmd_rcgr = 0x77020, 684 .mnd_width = 8, 685 .hid_width = 5, 686 .parent_map = gcc_parent_map_0, 687 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 688 .clkr.hw.init = &(struct clk_init_data){ 689 .name = "gcc_ufs_phy_axi_clk_src", 690 .parent_data = gcc_parent_data_0, 691 .num_parents = 4, 692 .ops = &clk_rcg2_ops, 693 }, 694 }; 695 696 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 697 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 698 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 699 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 700 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), 701 { } 702 }; 703 704 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 705 .cmd_rcgr = 0x77048, 706 .mnd_width = 0, 707 .hid_width = 5, 708 .parent_map = gcc_parent_map_0, 709 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 710 .clkr.hw.init = &(struct clk_init_data){ 711 .name = "gcc_ufs_phy_ice_core_clk_src", 712 .parent_data = gcc_parent_data_0, 713 .num_parents = 4, 714 .ops = &clk_rcg2_ops, 715 }, 716 }; 717 718 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 719 F(9600000, P_BI_TCXO, 2, 0, 0), 720 F(19200000, P_BI_TCXO, 1, 0, 0), 721 { } 722 }; 723 724 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 725 .cmd_rcgr = 0x77098, 726 .mnd_width = 0, 727 .hid_width = 5, 728 .parent_map = gcc_parent_map_3, 729 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 730 .clkr.hw.init = &(struct clk_init_data){ 731 .name = "gcc_ufs_phy_phy_aux_clk_src", 732 .parent_data = gcc_parent_data_3, 733 .num_parents = 3, 734 .ops = &clk_rcg2_ops, 735 }, 736 }; 737 738 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { 739 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 740 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 741 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), 742 { } 743 }; 744 745 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 746 .cmd_rcgr = 0x77060, 747 .mnd_width = 0, 748 .hid_width = 5, 749 .parent_map = gcc_parent_map_0, 750 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, 751 .clkr.hw.init = &(struct clk_init_data){ 752 .name = "gcc_ufs_phy_unipro_core_clk_src", 753 .parent_data = gcc_parent_data_0, 754 .num_parents = 4, 755 .ops = &clk_rcg2_ops, 756 }, 757 }; 758 759 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 760 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), 761 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 762 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 763 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 764 { } 765 }; 766 767 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 768 .cmd_rcgr = 0xf01c, 769 .mnd_width = 8, 770 .hid_width = 5, 771 .parent_map = gcc_parent_map_0, 772 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 773 .clkr.hw.init = &(struct clk_init_data){ 774 .name = "gcc_usb30_prim_master_clk_src", 775 .parent_data = gcc_parent_data_0, 776 .num_parents = 4, 777 .ops = &clk_rcg2_ops, 778 }, 779 }; 780 781 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 782 F(19200000, P_BI_TCXO, 1, 0, 0), 783 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0), 784 { } 785 }; 786 787 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 788 .cmd_rcgr = 0xf034, 789 .mnd_width = 0, 790 .hid_width = 5, 791 .parent_map = gcc_parent_map_0, 792 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 793 .clkr.hw.init = &(struct clk_init_data){ 794 .name = "gcc_usb30_prim_mock_utmi_clk_src", 795 .parent_data = gcc_parent_data_0, 796 .num_parents = 4, 797 .ops = &clk_rcg2_ops, 798 }, 799 }; 800 801 static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = { 802 F(19200000, P_BI_TCXO, 1, 0, 0), 803 { } 804 }; 805 806 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 807 .cmd_rcgr = 0xf060, 808 .mnd_width = 0, 809 .hid_width = 5, 810 .parent_map = gcc_parent_map_6, 811 .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src, 812 .clkr.hw.init = &(struct clk_init_data){ 813 .name = "gcc_usb3_prim_phy_aux_clk_src", 814 .parent_data = gcc_parent_data_6, 815 .num_parents = 4, 816 .ops = &clk_rcg2_ops, 817 }, 818 }; 819 820 static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = { 821 F(4800000, P_BI_TCXO, 4, 0, 0), 822 F(19200000, P_BI_TCXO, 1, 0, 0), 823 { } 824 }; 825 826 static struct clk_rcg2 gcc_sec_ctrl_clk_src = { 827 .cmd_rcgr = 0x3d030, 828 .mnd_width = 0, 829 .hid_width = 5, 830 .parent_map = gcc_parent_map_3, 831 .freq_tbl = ftbl_gcc_sec_ctrl_clk_src, 832 .clkr.hw.init = &(struct clk_init_data){ 833 .name = "gcc_sec_ctrl_clk_src", 834 .parent_data = gcc_parent_data_3, 835 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 836 .ops = &clk_rcg2_ops, 837 }, 838 }; 839 840 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 841 .halt_reg = 0x82024, 842 .halt_check = BRANCH_HALT_DELAY, 843 .hwcg_reg = 0x82024, 844 .hwcg_bit = 1, 845 .clkr = { 846 .enable_reg = 0x82024, 847 .enable_mask = BIT(0), 848 .hw.init = &(struct clk_init_data){ 849 .name = "gcc_aggre_ufs_phy_axi_clk", 850 .parent_data = &(const struct clk_parent_data){ 851 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 852 }, 853 .num_parents = 1, 854 .flags = CLK_SET_RATE_PARENT, 855 .ops = &clk_branch2_ops, 856 }, 857 }, 858 }; 859 860 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 861 .halt_reg = 0x8201c, 862 .halt_check = BRANCH_HALT, 863 .clkr = { 864 .enable_reg = 0x8201c, 865 .enable_mask = BIT(0), 866 .hw.init = &(struct clk_init_data){ 867 .name = "gcc_aggre_usb3_prim_axi_clk", 868 .parent_data = &(const struct clk_parent_data){ 869 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 870 }, 871 .num_parents = 1, 872 .flags = CLK_SET_RATE_PARENT, 873 .ops = &clk_branch2_ops, 874 }, 875 }, 876 }; 877 878 static struct clk_branch gcc_boot_rom_ahb_clk = { 879 .halt_reg = 0x38004, 880 .halt_check = BRANCH_HALT_VOTED, 881 .hwcg_reg = 0x38004, 882 .hwcg_bit = 1, 883 .clkr = { 884 .enable_reg = 0x52000, 885 .enable_mask = BIT(10), 886 .hw.init = &(struct clk_init_data){ 887 .name = "gcc_boot_rom_ahb_clk", 888 .ops = &clk_branch2_ops, 889 }, 890 }, 891 }; 892 893 static struct clk_branch gcc_camera_ahb_clk = { 894 .halt_reg = 0xb008, 895 .halt_check = BRANCH_HALT, 896 .hwcg_reg = 0xb008, 897 .hwcg_bit = 1, 898 .clkr = { 899 .enable_reg = 0xb008, 900 .enable_mask = BIT(0), 901 .hw.init = &(struct clk_init_data){ 902 .name = "gcc_camera_ahb_clk", 903 .ops = &clk_branch2_ops, 904 }, 905 }, 906 }; 907 908 static struct clk_branch gcc_camera_hf_axi_clk = { 909 .halt_reg = 0xb020, 910 .halt_check = BRANCH_HALT, 911 .clkr = { 912 .enable_reg = 0xb020, 913 .enable_mask = BIT(0), 914 .hw.init = &(struct clk_init_data){ 915 .name = "gcc_camera_hf_axi_clk", 916 .ops = &clk_branch2_ops, 917 }, 918 }, 919 }; 920 921 static struct clk_branch gcc_camera_throttle_hf_axi_clk = { 922 .halt_reg = 0xb080, 923 .halt_check = BRANCH_HALT, 924 .hwcg_reg = 0xb080, 925 .hwcg_bit = 1, 926 .clkr = { 927 .enable_reg = 0xb080, 928 .enable_mask = BIT(0), 929 .hw.init = &(struct clk_init_data){ 930 .name = "gcc_camera_throttle_hf_axi_clk", 931 .ops = &clk_branch2_ops, 932 }, 933 }, 934 }; 935 936 static struct clk_branch gcc_camera_xo_clk = { 937 .halt_reg = 0xb02c, 938 .halt_check = BRANCH_HALT, 939 .clkr = { 940 .enable_reg = 0xb02c, 941 .enable_mask = BIT(0), 942 .hw.init = &(struct clk_init_data){ 943 .name = "gcc_camera_xo_clk", 944 .ops = &clk_branch2_ops, 945 }, 946 }, 947 }; 948 949 static struct clk_branch gcc_ce1_ahb_clk = { 950 .halt_reg = 0x4100c, 951 .halt_check = BRANCH_HALT_VOTED, 952 .hwcg_reg = 0x4100c, 953 .hwcg_bit = 1, 954 .clkr = { 955 .enable_reg = 0x52000, 956 .enable_mask = BIT(3), 957 .hw.init = &(struct clk_init_data){ 958 .name = "gcc_ce1_ahb_clk", 959 .ops = &clk_branch2_ops, 960 }, 961 }, 962 }; 963 964 static struct clk_branch gcc_ce1_axi_clk = { 965 .halt_reg = 0x41008, 966 .halt_check = BRANCH_HALT_VOTED, 967 .clkr = { 968 .enable_reg = 0x52000, 969 .enable_mask = BIT(4), 970 .hw.init = &(struct clk_init_data){ 971 .name = "gcc_ce1_axi_clk", 972 .ops = &clk_branch2_ops, 973 }, 974 }, 975 }; 976 977 static struct clk_branch gcc_ce1_clk = { 978 .halt_reg = 0x41004, 979 .halt_check = BRANCH_HALT_VOTED, 980 .clkr = { 981 .enable_reg = 0x52000, 982 .enable_mask = BIT(5), 983 .hw.init = &(struct clk_init_data){ 984 .name = "gcc_ce1_clk", 985 .ops = &clk_branch2_ops, 986 }, 987 }, 988 }; 989 990 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 991 .halt_reg = 0x502c, 992 .halt_check = BRANCH_HALT, 993 .clkr = { 994 .enable_reg = 0x502c, 995 .enable_mask = BIT(0), 996 .hw.init = &(struct clk_init_data){ 997 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 998 .parent_data = &(const struct clk_parent_data){ 999 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 1000 }, 1001 .num_parents = 1, 1002 .flags = CLK_SET_RATE_PARENT, 1003 .ops = &clk_branch2_ops, 1004 }, 1005 }, 1006 }; 1007 1008 /* For CPUSS functionality the AHB clock needs to be left enabled */ 1009 static struct clk_branch gcc_cpuss_ahb_clk = { 1010 .halt_reg = 0x48000, 1011 .halt_check = BRANCH_HALT_VOTED, 1012 .clkr = { 1013 .enable_reg = 0x52000, 1014 .enable_mask = BIT(21), 1015 .hw.init = &(struct clk_init_data){ 1016 .name = "gcc_cpuss_ahb_clk", 1017 .parent_data = &(const struct clk_parent_data){ 1018 .hw = &gcc_cpuss_ahb_clk_src.clkr.hw, 1019 }, 1020 .num_parents = 1, 1021 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 1022 .ops = &clk_branch2_ops, 1023 }, 1024 }, 1025 }; 1026 1027 static struct clk_branch gcc_cpuss_rbcpr_clk = { 1028 .halt_reg = 0x48008, 1029 .halt_check = BRANCH_HALT, 1030 .clkr = { 1031 .enable_reg = 0x48008, 1032 .enable_mask = BIT(0), 1033 .hw.init = &(struct clk_init_data){ 1034 .name = "gcc_cpuss_rbcpr_clk", 1035 .ops = &clk_branch2_ops, 1036 }, 1037 }, 1038 }; 1039 1040 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1041 .halt_reg = 0x4452c, 1042 .halt_check = BRANCH_VOTED, 1043 .clkr = { 1044 .enable_reg = 0x4452c, 1045 .enable_mask = BIT(0), 1046 .hw.init = &(struct clk_init_data){ 1047 .name = "gcc_ddrss_gpu_axi_clk", 1048 .ops = &clk_branch2_ops, 1049 }, 1050 }, 1051 }; 1052 1053 static struct clk_branch gcc_disp_gpll0_clk_src = { 1054 .halt_check = BRANCH_HALT_DELAY, 1055 .clkr = { 1056 .enable_reg = 0x52000, 1057 .enable_mask = BIT(18), 1058 .hw.init = &(struct clk_init_data){ 1059 .name = "gcc_disp_gpll0_clk_src", 1060 .parent_data = &(const struct clk_parent_data){ 1061 .hw = &gpll0.clkr.hw, 1062 }, 1063 .num_parents = 1, 1064 .ops = &clk_branch2_aon_ops, 1065 }, 1066 }, 1067 }; 1068 1069 static struct clk_branch gcc_disp_gpll0_div_clk_src = { 1070 .halt_check = BRANCH_HALT_DELAY, 1071 .clkr = { 1072 .enable_reg = 0x52000, 1073 .enable_mask = BIT(19), 1074 .hw.init = &(struct clk_init_data){ 1075 .name = "gcc_disp_gpll0_div_clk_src", 1076 .parent_data = &(const struct clk_parent_data){ 1077 .hw = &gcc_pll0_main_div_cdiv.hw, 1078 }, 1079 .num_parents = 1, 1080 .ops = &clk_branch2_ops, 1081 }, 1082 }, 1083 }; 1084 1085 static struct clk_branch gcc_disp_hf_axi_clk = { 1086 .halt_reg = 0xb024, 1087 .halt_check = BRANCH_HALT, 1088 .clkr = { 1089 .enable_reg = 0xb024, 1090 .enable_mask = BIT(0), 1091 .hw.init = &(struct clk_init_data){ 1092 .name = "gcc_disp_hf_axi_clk", 1093 .ops = &clk_branch2_ops, 1094 }, 1095 }, 1096 }; 1097 1098 static struct clk_branch gcc_disp_throttle_hf_axi_clk = { 1099 .halt_reg = 0xb084, 1100 .halt_check = BRANCH_HALT, 1101 .hwcg_reg = 0xb084, 1102 .hwcg_bit = 1, 1103 .clkr = { 1104 .enable_reg = 0xb084, 1105 .enable_mask = BIT(0), 1106 .hw.init = &(struct clk_init_data){ 1107 .name = "gcc_disp_throttle_hf_axi_clk", 1108 .ops = &clk_branch2_ops, 1109 }, 1110 }, 1111 }; 1112 1113 static struct clk_branch gcc_disp_xo_clk = { 1114 .halt_reg = 0xb030, 1115 .halt_check = BRANCH_HALT, 1116 .clkr = { 1117 .enable_reg = 0xb030, 1118 .enable_mask = BIT(0), 1119 .hw.init = &(struct clk_init_data){ 1120 .name = "gcc_disp_xo_clk", 1121 .ops = &clk_branch2_ops, 1122 }, 1123 }, 1124 }; 1125 1126 static struct clk_branch gcc_gp1_clk = { 1127 .halt_reg = 0x64000, 1128 .halt_check = BRANCH_HALT, 1129 .clkr = { 1130 .enable_reg = 0x64000, 1131 .enable_mask = BIT(0), 1132 .hw.init = &(struct clk_init_data){ 1133 .name = "gcc_gp1_clk", 1134 .parent_data = &(const struct clk_parent_data){ 1135 .hw = &gcc_gp1_clk_src.clkr.hw, 1136 }, 1137 .num_parents = 1, 1138 .flags = CLK_SET_RATE_PARENT, 1139 .ops = &clk_branch2_ops, 1140 }, 1141 }, 1142 }; 1143 1144 static struct clk_branch gcc_gp2_clk = { 1145 .halt_reg = 0x65000, 1146 .halt_check = BRANCH_HALT, 1147 .clkr = { 1148 .enable_reg = 0x65000, 1149 .enable_mask = BIT(0), 1150 .hw.init = &(struct clk_init_data){ 1151 .name = "gcc_gp2_clk", 1152 .parent_data = &(const struct clk_parent_data){ 1153 .hw = &gcc_gp2_clk_src.clkr.hw, 1154 }, 1155 .num_parents = 1, 1156 .flags = CLK_SET_RATE_PARENT, 1157 .ops = &clk_branch2_ops, 1158 }, 1159 }, 1160 }; 1161 1162 static struct clk_branch gcc_gp3_clk = { 1163 .halt_reg = 0x66000, 1164 .halt_check = BRANCH_HALT, 1165 .clkr = { 1166 .enable_reg = 0x66000, 1167 .enable_mask = BIT(0), 1168 .hw.init = &(struct clk_init_data){ 1169 .name = "gcc_gp3_clk", 1170 .parent_data = &(const struct clk_parent_data){ 1171 .hw = &gcc_gp3_clk_src.clkr.hw, 1172 }, 1173 .num_parents = 1, 1174 .flags = CLK_SET_RATE_PARENT, 1175 .ops = &clk_branch2_ops, 1176 }, 1177 }, 1178 }; 1179 1180 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1181 .halt_check = BRANCH_HALT_DELAY, 1182 .clkr = { 1183 .enable_reg = 0x52000, 1184 .enable_mask = BIT(15), 1185 .hw.init = &(struct clk_init_data){ 1186 .name = "gcc_gpu_gpll0_clk_src", 1187 .parent_data = &(const struct clk_parent_data){ 1188 .hw = &gpll0.clkr.hw, 1189 }, 1190 .num_parents = 1, 1191 .ops = &clk_branch2_ops, 1192 }, 1193 }, 1194 }; 1195 1196 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1197 .halt_check = BRANCH_HALT_DELAY, 1198 .clkr = { 1199 .enable_reg = 0x52000, 1200 .enable_mask = BIT(16), 1201 .hw.init = &(struct clk_init_data){ 1202 .name = "gcc_gpu_gpll0_div_clk_src", 1203 .parent_data = &(const struct clk_parent_data){ 1204 .hw = &gcc_pll0_main_div_cdiv.hw, 1205 }, 1206 .num_parents = 1, 1207 .ops = &clk_branch2_ops, 1208 }, 1209 }, 1210 }; 1211 1212 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1213 .halt_reg = 0x7100c, 1214 .halt_check = BRANCH_VOTED, 1215 .clkr = { 1216 .enable_reg = 0x7100c, 1217 .enable_mask = BIT(0), 1218 .hw.init = &(struct clk_init_data){ 1219 .name = "gcc_gpu_memnoc_gfx_clk", 1220 .ops = &clk_branch2_ops, 1221 }, 1222 }, 1223 }; 1224 1225 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1226 .halt_reg = 0x71018, 1227 .halt_check = BRANCH_HALT, 1228 .clkr = { 1229 .enable_reg = 0x71018, 1230 .enable_mask = BIT(0), 1231 .hw.init = &(struct clk_init_data){ 1232 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1233 .ops = &clk_branch2_ops, 1234 }, 1235 }, 1236 }; 1237 1238 static struct clk_branch gcc_npu_axi_clk = { 1239 .halt_reg = 0x4d008, 1240 .halt_check = BRANCH_HALT, 1241 .clkr = { 1242 .enable_reg = 0x4d008, 1243 .enable_mask = BIT(0), 1244 .hw.init = &(struct clk_init_data){ 1245 .name = "gcc_npu_axi_clk", 1246 .ops = &clk_branch2_ops, 1247 }, 1248 }, 1249 }; 1250 1251 static struct clk_branch gcc_npu_bwmon_axi_clk = { 1252 .halt_reg = 0x73008, 1253 .halt_check = BRANCH_HALT, 1254 .clkr = { 1255 .enable_reg = 0x73008, 1256 .enable_mask = BIT(0), 1257 .hw.init = &(struct clk_init_data){ 1258 .name = "gcc_npu_bwmon_axi_clk", 1259 .ops = &clk_branch2_ops, 1260 }, 1261 }, 1262 }; 1263 1264 static struct clk_branch gcc_npu_bwmon_dma_cfg_ahb_clk = { 1265 .halt_reg = 0x73018, 1266 .halt_check = BRANCH_HALT, 1267 .clkr = { 1268 .enable_reg = 0x73018, 1269 .enable_mask = BIT(0), 1270 .hw.init = &(struct clk_init_data){ 1271 .name = "gcc_npu_bwmon_dma_cfg_ahb_clk", 1272 .ops = &clk_branch2_ops, 1273 }, 1274 }, 1275 }; 1276 1277 static struct clk_branch gcc_npu_bwmon_dsp_cfg_ahb_clk = { 1278 .halt_reg = 0x7301c, 1279 .halt_check = BRANCH_HALT, 1280 .clkr = { 1281 .enable_reg = 0x7301c, 1282 .enable_mask = BIT(0), 1283 .hw.init = &(struct clk_init_data){ 1284 .name = "gcc_npu_bwmon_dsp_cfg_ahb_clk", 1285 .ops = &clk_branch2_ops, 1286 }, 1287 }, 1288 }; 1289 1290 static struct clk_branch gcc_npu_cfg_ahb_clk = { 1291 .halt_reg = 0x4d004, 1292 .halt_check = BRANCH_HALT, 1293 .hwcg_reg = 0x4d004, 1294 .hwcg_bit = 1, 1295 .clkr = { 1296 .enable_reg = 0x4d004, 1297 .enable_mask = BIT(0), 1298 .hw.init = &(struct clk_init_data){ 1299 .name = "gcc_npu_cfg_ahb_clk", 1300 .ops = &clk_branch2_ops, 1301 }, 1302 }, 1303 }; 1304 1305 static struct clk_branch gcc_npu_dma_clk = { 1306 .halt_reg = 0x4d1a0, 1307 .halt_check = BRANCH_HALT, 1308 .hwcg_reg = 0x4d1a0, 1309 .hwcg_bit = 1, 1310 .clkr = { 1311 .enable_reg = 0x4d1a0, 1312 .enable_mask = BIT(0), 1313 .hw.init = &(struct clk_init_data){ 1314 .name = "gcc_npu_dma_clk", 1315 .ops = &clk_branch2_ops, 1316 }, 1317 }, 1318 }; 1319 1320 static struct clk_branch gcc_npu_gpll0_clk_src = { 1321 .halt_check = BRANCH_HALT_DELAY, 1322 .clkr = { 1323 .enable_reg = 0x52000, 1324 .enable_mask = BIT(25), 1325 .hw.init = &(struct clk_init_data){ 1326 .name = "gcc_npu_gpll0_clk_src", 1327 .parent_data = &(const struct clk_parent_data){ 1328 .hw = &gpll0.clkr.hw, 1329 }, 1330 .num_parents = 1, 1331 .ops = &clk_branch2_ops, 1332 }, 1333 }, 1334 }; 1335 1336 static struct clk_branch gcc_npu_gpll0_div_clk_src = { 1337 .halt_check = BRANCH_HALT_DELAY, 1338 .clkr = { 1339 .enable_reg = 0x52000, 1340 .enable_mask = BIT(26), 1341 .hw.init = &(struct clk_init_data){ 1342 .name = "gcc_npu_gpll0_div_clk_src", 1343 .parent_data = &(const struct clk_parent_data){ 1344 .hw = &gcc_pll0_main_div_cdiv.hw, 1345 }, 1346 .num_parents = 1, 1347 .flags = CLK_SET_RATE_PARENT, 1348 .ops = &clk_branch2_ops, 1349 }, 1350 }, 1351 }; 1352 1353 static struct clk_branch gcc_pdm2_clk = { 1354 .halt_reg = 0x3300c, 1355 .halt_check = BRANCH_HALT, 1356 .clkr = { 1357 .enable_reg = 0x3300c, 1358 .enable_mask = BIT(0), 1359 .hw.init = &(struct clk_init_data){ 1360 .name = "gcc_pdm2_clk", 1361 .parent_data = &(const struct clk_parent_data){ 1362 .hw = &gcc_pdm2_clk_src.clkr.hw, 1363 }, 1364 .num_parents = 1, 1365 .flags = CLK_SET_RATE_PARENT, 1366 .ops = &clk_branch2_ops, 1367 }, 1368 }, 1369 }; 1370 1371 static struct clk_branch gcc_pdm_ahb_clk = { 1372 .halt_reg = 0x33004, 1373 .halt_check = BRANCH_HALT, 1374 .hwcg_reg = 0x33004, 1375 .hwcg_bit = 1, 1376 .clkr = { 1377 .enable_reg = 0x33004, 1378 .enable_mask = BIT(0), 1379 .hw.init = &(struct clk_init_data){ 1380 .name = "gcc_pdm_ahb_clk", 1381 .ops = &clk_branch2_ops, 1382 }, 1383 }, 1384 }; 1385 1386 static struct clk_branch gcc_pdm_xo4_clk = { 1387 .halt_reg = 0x33008, 1388 .halt_check = BRANCH_HALT, 1389 .clkr = { 1390 .enable_reg = 0x33008, 1391 .enable_mask = BIT(0), 1392 .hw.init = &(struct clk_init_data){ 1393 .name = "gcc_pdm_xo4_clk", 1394 .ops = &clk_branch2_ops, 1395 }, 1396 }, 1397 }; 1398 1399 static struct clk_branch gcc_prng_ahb_clk = { 1400 .halt_reg = 0x34004, 1401 .halt_check = BRANCH_HALT_VOTED, 1402 .hwcg_reg = 0x34004, 1403 .hwcg_bit = 1, 1404 .clkr = { 1405 .enable_reg = 0x52000, 1406 .enable_mask = BIT(13), 1407 .hw.init = &(struct clk_init_data){ 1408 .name = "gcc_prng_ahb_clk", 1409 .ops = &clk_branch2_ops, 1410 }, 1411 }, 1412 }; 1413 1414 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = { 1415 .halt_reg = 0x4b004, 1416 .halt_check = BRANCH_HALT, 1417 .hwcg_reg = 0x4b004, 1418 .hwcg_bit = 1, 1419 .clkr = { 1420 .enable_reg = 0x4b004, 1421 .enable_mask = BIT(0), 1422 .hw.init = &(struct clk_init_data){ 1423 .name = "gcc_qspi_cnoc_periph_ahb_clk", 1424 .ops = &clk_branch2_ops, 1425 }, 1426 }, 1427 }; 1428 1429 static struct clk_branch gcc_qspi_core_clk = { 1430 .halt_reg = 0x4b008, 1431 .halt_check = BRANCH_HALT, 1432 .clkr = { 1433 .enable_reg = 0x4b008, 1434 .enable_mask = BIT(0), 1435 .hw.init = &(struct clk_init_data){ 1436 .name = "gcc_qspi_core_clk", 1437 .parent_data = &(const struct clk_parent_data){ 1438 .hw = &gcc_qspi_core_clk_src.clkr.hw, 1439 }, 1440 .num_parents = 1, 1441 .flags = CLK_SET_RATE_PARENT, 1442 .ops = &clk_branch2_ops, 1443 }, 1444 }, 1445 }; 1446 1447 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 1448 .halt_reg = 0x17014, 1449 .halt_check = BRANCH_HALT_VOTED, 1450 .clkr = { 1451 .enable_reg = 0x52008, 1452 .enable_mask = BIT(9), 1453 .hw.init = &(struct clk_init_data){ 1454 .name = "gcc_qupv3_wrap0_core_2x_clk", 1455 .ops = &clk_branch2_ops, 1456 }, 1457 }, 1458 }; 1459 1460 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 1461 .halt_reg = 0x1700c, 1462 .halt_check = BRANCH_HALT_VOTED, 1463 .clkr = { 1464 .enable_reg = 0x52008, 1465 .enable_mask = BIT(8), 1466 .hw.init = &(struct clk_init_data){ 1467 .name = "gcc_qupv3_wrap0_core_clk", 1468 .ops = &clk_branch2_ops, 1469 }, 1470 }, 1471 }; 1472 1473 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 1474 .halt_reg = 0x17030, 1475 .halt_check = BRANCH_HALT_VOTED, 1476 .clkr = { 1477 .enable_reg = 0x52008, 1478 .enable_mask = BIT(10), 1479 .hw.init = &(struct clk_init_data){ 1480 .name = "gcc_qupv3_wrap0_s0_clk", 1481 .parent_data = &(const struct clk_parent_data){ 1482 .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 1483 }, 1484 .num_parents = 1, 1485 .flags = CLK_SET_RATE_PARENT, 1486 .ops = &clk_branch2_ops, 1487 }, 1488 }, 1489 }; 1490 1491 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 1492 .halt_reg = 0x17160, 1493 .halt_check = BRANCH_HALT_VOTED, 1494 .clkr = { 1495 .enable_reg = 0x52008, 1496 .enable_mask = BIT(11), 1497 .hw.init = &(struct clk_init_data){ 1498 .name = "gcc_qupv3_wrap0_s1_clk", 1499 .parent_data = &(const struct clk_parent_data){ 1500 .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 1501 }, 1502 .num_parents = 1, 1503 .flags = CLK_SET_RATE_PARENT, 1504 .ops = &clk_branch2_ops, 1505 }, 1506 }, 1507 }; 1508 1509 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 1510 .halt_reg = 0x17290, 1511 .halt_check = BRANCH_HALT_VOTED, 1512 .clkr = { 1513 .enable_reg = 0x52008, 1514 .enable_mask = BIT(12), 1515 .hw.init = &(struct clk_init_data){ 1516 .name = "gcc_qupv3_wrap0_s2_clk", 1517 .parent_data = &(const struct clk_parent_data){ 1518 .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 1519 }, 1520 .num_parents = 1, 1521 .flags = CLK_SET_RATE_PARENT, 1522 .ops = &clk_branch2_ops, 1523 }, 1524 }, 1525 }; 1526 1527 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 1528 .halt_reg = 0x173c0, 1529 .halt_check = BRANCH_HALT_VOTED, 1530 .clkr = { 1531 .enable_reg = 0x52008, 1532 .enable_mask = BIT(13), 1533 .hw.init = &(struct clk_init_data){ 1534 .name = "gcc_qupv3_wrap0_s3_clk", 1535 .parent_data = &(const struct clk_parent_data){ 1536 .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 1537 }, 1538 .num_parents = 1, 1539 .flags = CLK_SET_RATE_PARENT, 1540 .ops = &clk_branch2_ops, 1541 }, 1542 }, 1543 }; 1544 1545 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 1546 .halt_reg = 0x174f0, 1547 .halt_check = BRANCH_HALT_VOTED, 1548 .clkr = { 1549 .enable_reg = 0x52008, 1550 .enable_mask = BIT(14), 1551 .hw.init = &(struct clk_init_data){ 1552 .name = "gcc_qupv3_wrap0_s4_clk", 1553 .parent_data = &(const struct clk_parent_data){ 1554 .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 1555 }, 1556 .num_parents = 1, 1557 .flags = CLK_SET_RATE_PARENT, 1558 .ops = &clk_branch2_ops, 1559 }, 1560 }, 1561 }; 1562 1563 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 1564 .halt_reg = 0x17620, 1565 .halt_check = BRANCH_HALT_VOTED, 1566 .clkr = { 1567 .enable_reg = 0x52008, 1568 .enable_mask = BIT(15), 1569 .hw.init = &(struct clk_init_data){ 1570 .name = "gcc_qupv3_wrap0_s5_clk", 1571 .parent_data = &(const struct clk_parent_data){ 1572 .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 1573 }, 1574 .num_parents = 1, 1575 .flags = CLK_SET_RATE_PARENT, 1576 .ops = &clk_branch2_ops, 1577 }, 1578 }, 1579 }; 1580 1581 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 1582 .halt_reg = 0x18004, 1583 .halt_check = BRANCH_HALT_VOTED, 1584 .clkr = { 1585 .enable_reg = 0x52008, 1586 .enable_mask = BIT(18), 1587 .hw.init = &(struct clk_init_data){ 1588 .name = "gcc_qupv3_wrap1_core_2x_clk", 1589 .ops = &clk_branch2_ops, 1590 }, 1591 }, 1592 }; 1593 1594 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 1595 .halt_reg = 0x18008, 1596 .halt_check = BRANCH_HALT_VOTED, 1597 .clkr = { 1598 .enable_reg = 0x52008, 1599 .enable_mask = BIT(19), 1600 .hw.init = &(struct clk_init_data){ 1601 .name = "gcc_qupv3_wrap1_core_clk", 1602 .ops = &clk_branch2_ops, 1603 }, 1604 }, 1605 }; 1606 1607 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 1608 .halt_reg = 0x18014, 1609 .halt_check = BRANCH_HALT_VOTED, 1610 .clkr = { 1611 .enable_reg = 0x52008, 1612 .enable_mask = BIT(22), 1613 .hw.init = &(struct clk_init_data){ 1614 .name = "gcc_qupv3_wrap1_s0_clk", 1615 .parent_data = &(const struct clk_parent_data){ 1616 .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 1617 }, 1618 .num_parents = 1, 1619 .flags = CLK_SET_RATE_PARENT, 1620 .ops = &clk_branch2_ops, 1621 }, 1622 }, 1623 }; 1624 1625 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 1626 .halt_reg = 0x18144, 1627 .halt_check = BRANCH_HALT_VOTED, 1628 .clkr = { 1629 .enable_reg = 0x52008, 1630 .enable_mask = BIT(23), 1631 .hw.init = &(struct clk_init_data){ 1632 .name = "gcc_qupv3_wrap1_s1_clk", 1633 .parent_data = &(const struct clk_parent_data){ 1634 .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 1635 }, 1636 .num_parents = 1, 1637 .flags = CLK_SET_RATE_PARENT, 1638 .ops = &clk_branch2_ops, 1639 }, 1640 }, 1641 }; 1642 1643 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 1644 .halt_reg = 0x18274, 1645 .halt_check = BRANCH_HALT_VOTED, 1646 .clkr = { 1647 .enable_reg = 0x52008, 1648 .enable_mask = BIT(24), 1649 .hw.init = &(struct clk_init_data){ 1650 .name = "gcc_qupv3_wrap1_s2_clk", 1651 .parent_data = &(const struct clk_parent_data){ 1652 .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 1653 }, 1654 .num_parents = 1, 1655 .flags = CLK_SET_RATE_PARENT, 1656 .ops = &clk_branch2_ops, 1657 }, 1658 }, 1659 }; 1660 1661 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 1662 .halt_reg = 0x183a4, 1663 .halt_check = BRANCH_HALT_VOTED, 1664 .clkr = { 1665 .enable_reg = 0x52008, 1666 .enable_mask = BIT(25), 1667 .hw.init = &(struct clk_init_data){ 1668 .name = "gcc_qupv3_wrap1_s3_clk", 1669 .parent_data = &(const struct clk_parent_data){ 1670 .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 1671 }, 1672 .num_parents = 1, 1673 .flags = CLK_SET_RATE_PARENT, 1674 .ops = &clk_branch2_ops, 1675 }, 1676 }, 1677 }; 1678 1679 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 1680 .halt_reg = 0x184d4, 1681 .halt_check = BRANCH_HALT_VOTED, 1682 .clkr = { 1683 .enable_reg = 0x52008, 1684 .enable_mask = BIT(26), 1685 .hw.init = &(struct clk_init_data){ 1686 .name = "gcc_qupv3_wrap1_s4_clk", 1687 .parent_data = &(const struct clk_parent_data){ 1688 .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 1689 }, 1690 .num_parents = 1, 1691 .flags = CLK_SET_RATE_PARENT, 1692 .ops = &clk_branch2_ops, 1693 }, 1694 }, 1695 }; 1696 1697 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 1698 .halt_reg = 0x18604, 1699 .halt_check = BRANCH_HALT_VOTED, 1700 .clkr = { 1701 .enable_reg = 0x52008, 1702 .enable_mask = BIT(27), 1703 .hw.init = &(struct clk_init_data){ 1704 .name = "gcc_qupv3_wrap1_s5_clk", 1705 .parent_data = &(const struct clk_parent_data){ 1706 .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 1707 }, 1708 .num_parents = 1, 1709 .flags = CLK_SET_RATE_PARENT, 1710 .ops = &clk_branch2_ops, 1711 }, 1712 }, 1713 }; 1714 1715 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 1716 .halt_reg = 0x17004, 1717 .halt_check = BRANCH_HALT_VOTED, 1718 .clkr = { 1719 .enable_reg = 0x52008, 1720 .enable_mask = BIT(6), 1721 .hw.init = &(struct clk_init_data){ 1722 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 1723 .ops = &clk_branch2_ops, 1724 }, 1725 }, 1726 }; 1727 1728 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 1729 .halt_reg = 0x17008, 1730 .halt_check = BRANCH_HALT_VOTED, 1731 .hwcg_reg = 0x17008, 1732 .hwcg_bit = 1, 1733 .clkr = { 1734 .enable_reg = 0x52008, 1735 .enable_mask = BIT(7), 1736 .hw.init = &(struct clk_init_data){ 1737 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 1738 .ops = &clk_branch2_ops, 1739 }, 1740 }, 1741 }; 1742 1743 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 1744 .halt_reg = 0x1800c, 1745 .halt_check = BRANCH_HALT_VOTED, 1746 .clkr = { 1747 .enable_reg = 0x52008, 1748 .enable_mask = BIT(20), 1749 .hw.init = &(struct clk_init_data){ 1750 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 1751 .ops = &clk_branch2_ops, 1752 }, 1753 }, 1754 }; 1755 1756 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 1757 .halt_reg = 0x18010, 1758 .halt_check = BRANCH_HALT_VOTED, 1759 .hwcg_reg = 0x18010, 1760 .hwcg_bit = 1, 1761 .clkr = { 1762 .enable_reg = 0x52008, 1763 .enable_mask = BIT(21), 1764 .hw.init = &(struct clk_init_data){ 1765 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 1766 .ops = &clk_branch2_ops, 1767 }, 1768 }, 1769 }; 1770 1771 static struct clk_branch gcc_sdcc1_ahb_clk = { 1772 .halt_reg = 0x12008, 1773 .halt_check = BRANCH_HALT, 1774 .clkr = { 1775 .enable_reg = 0x12008, 1776 .enable_mask = BIT(0), 1777 .hw.init = &(struct clk_init_data){ 1778 .name = "gcc_sdcc1_ahb_clk", 1779 .ops = &clk_branch2_ops, 1780 }, 1781 }, 1782 }; 1783 1784 static struct clk_branch gcc_sdcc1_apps_clk = { 1785 .halt_reg = 0x1200c, 1786 .halt_check = BRANCH_HALT, 1787 .clkr = { 1788 .enable_reg = 0x1200c, 1789 .enable_mask = BIT(0), 1790 .hw.init = &(struct clk_init_data){ 1791 .name = "gcc_sdcc1_apps_clk", 1792 .parent_data = &(const struct clk_parent_data){ 1793 .hw = &gcc_sdcc1_apps_clk_src.clkr.hw, 1794 }, 1795 .num_parents = 1, 1796 .flags = CLK_SET_RATE_PARENT, 1797 .ops = &clk_branch2_ops, 1798 }, 1799 }, 1800 }; 1801 1802 static struct clk_branch gcc_sdcc1_ice_core_clk = { 1803 .halt_reg = 0x12040, 1804 .halt_check = BRANCH_HALT, 1805 .clkr = { 1806 .enable_reg = 0x12040, 1807 .enable_mask = BIT(0), 1808 .hw.init = &(struct clk_init_data){ 1809 .name = "gcc_sdcc1_ice_core_clk", 1810 .parent_data = &(const struct clk_parent_data){ 1811 .hw = &gcc_sdcc1_ice_core_clk_src.clkr.hw, 1812 }, 1813 .num_parents = 1, 1814 .flags = CLK_SET_RATE_PARENT, 1815 .ops = &clk_branch2_ops, 1816 }, 1817 }, 1818 }; 1819 1820 static struct clk_branch gcc_sdcc2_ahb_clk = { 1821 .halt_reg = 0x14008, 1822 .halt_check = BRANCH_HALT, 1823 .clkr = { 1824 .enable_reg = 0x14008, 1825 .enable_mask = BIT(0), 1826 .hw.init = &(struct clk_init_data){ 1827 .name = "gcc_sdcc2_ahb_clk", 1828 .ops = &clk_branch2_ops, 1829 }, 1830 }, 1831 }; 1832 1833 static struct clk_branch gcc_sdcc2_apps_clk = { 1834 .halt_reg = 0x14004, 1835 .halt_check = BRANCH_HALT, 1836 .clkr = { 1837 .enable_reg = 0x14004, 1838 .enable_mask = BIT(0), 1839 .hw.init = &(struct clk_init_data){ 1840 .name = "gcc_sdcc2_apps_clk", 1841 .parent_data = &(const struct clk_parent_data){ 1842 .hw = &gcc_sdcc2_apps_clk_src.clkr.hw, 1843 }, 1844 .num_parents = 1, 1845 .flags = CLK_SET_RATE_PARENT, 1846 .ops = &clk_branch2_ops, 1847 }, 1848 }, 1849 }; 1850 1851 /* For CPUSS functionality the SYS NOC clock needs to be left enabled */ 1852 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 1853 .halt_reg = 0x4144, 1854 .halt_check = BRANCH_HALT_VOTED, 1855 .clkr = { 1856 .enable_reg = 0x52000, 1857 .enable_mask = BIT(0), 1858 .hw.init = &(struct clk_init_data){ 1859 .name = "gcc_sys_noc_cpuss_ahb_clk", 1860 .parent_data = &(const struct clk_parent_data){ 1861 .hw = &gcc_cpuss_ahb_clk_src.clkr.hw, 1862 }, 1863 .num_parents = 1, 1864 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 1865 .ops = &clk_branch2_ops, 1866 }, 1867 }, 1868 }; 1869 1870 static struct clk_branch gcc_ufs_mem_clkref_clk = { 1871 .halt_reg = 0x8c000, 1872 .halt_check = BRANCH_HALT, 1873 .clkr = { 1874 .enable_reg = 0x8c000, 1875 .enable_mask = BIT(0), 1876 .hw.init = &(struct clk_init_data){ 1877 .name = "gcc_ufs_mem_clkref_clk", 1878 .ops = &clk_branch2_ops, 1879 }, 1880 }, 1881 }; 1882 1883 static struct clk_branch gcc_ufs_phy_ahb_clk = { 1884 .halt_reg = 0x77014, 1885 .halt_check = BRANCH_HALT, 1886 .hwcg_reg = 0x77014, 1887 .hwcg_bit = 1, 1888 .clkr = { 1889 .enable_reg = 0x77014, 1890 .enable_mask = BIT(0), 1891 .hw.init = &(struct clk_init_data){ 1892 .name = "gcc_ufs_phy_ahb_clk", 1893 .ops = &clk_branch2_ops, 1894 }, 1895 }, 1896 }; 1897 1898 static struct clk_branch gcc_ufs_phy_axi_clk = { 1899 .halt_reg = 0x77038, 1900 .halt_check = BRANCH_HALT, 1901 .hwcg_reg = 0x77038, 1902 .hwcg_bit = 1, 1903 .clkr = { 1904 .enable_reg = 0x77038, 1905 .enable_mask = BIT(0), 1906 .hw.init = &(struct clk_init_data){ 1907 .name = "gcc_ufs_phy_axi_clk", 1908 .parent_data = &(const struct clk_parent_data){ 1909 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, 1910 }, 1911 .num_parents = 1, 1912 .flags = CLK_SET_RATE_PARENT, 1913 .ops = &clk_branch2_ops, 1914 }, 1915 }, 1916 }; 1917 1918 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 1919 .halt_reg = 0x77090, 1920 .halt_check = BRANCH_HALT, 1921 .hwcg_reg = 0x77090, 1922 .hwcg_bit = 1, 1923 .clkr = { 1924 .enable_reg = 0x77090, 1925 .enable_mask = BIT(0), 1926 .hw.init = &(struct clk_init_data){ 1927 .name = "gcc_ufs_phy_ice_core_clk", 1928 .parent_data = &(const struct clk_parent_data){ 1929 .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 1930 }, 1931 .num_parents = 1, 1932 .flags = CLK_SET_RATE_PARENT, 1933 .ops = &clk_branch2_ops, 1934 }, 1935 }, 1936 }; 1937 1938 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 1939 .halt_reg = 0x77094, 1940 .halt_check = BRANCH_HALT, 1941 .hwcg_reg = 0x77094, 1942 .hwcg_bit = 1, 1943 .clkr = { 1944 .enable_reg = 0x77094, 1945 .enable_mask = BIT(0), 1946 .hw.init = &(struct clk_init_data){ 1947 .name = "gcc_ufs_phy_phy_aux_clk", 1948 .parent_data = &(const struct clk_parent_data){ 1949 .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 1950 }, 1951 .num_parents = 1, 1952 .flags = CLK_SET_RATE_PARENT, 1953 .ops = &clk_branch2_ops, 1954 }, 1955 }, 1956 }; 1957 1958 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 1959 .halt_reg = 0x7701c, 1960 .halt_check = BRANCH_HALT_SKIP, 1961 .clkr = { 1962 .enable_reg = 0x7701c, 1963 .enable_mask = BIT(0), 1964 .hw.init = &(struct clk_init_data){ 1965 .name = "gcc_ufs_phy_rx_symbol_0_clk", 1966 .ops = &clk_branch2_ops, 1967 }, 1968 }, 1969 }; 1970 1971 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 1972 .halt_reg = 0x77018, 1973 .halt_check = BRANCH_HALT_SKIP, 1974 .clkr = { 1975 .enable_reg = 0x77018, 1976 .enable_mask = BIT(0), 1977 .hw.init = &(struct clk_init_data){ 1978 .name = "gcc_ufs_phy_tx_symbol_0_clk", 1979 .ops = &clk_branch2_ops, 1980 }, 1981 }, 1982 }; 1983 1984 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 1985 .halt_reg = 0x7708c, 1986 .halt_check = BRANCH_HALT, 1987 .hwcg_reg = 0x7708c, 1988 .hwcg_bit = 1, 1989 .clkr = { 1990 .enable_reg = 0x7708c, 1991 .enable_mask = BIT(0), 1992 .hw.init = &(struct clk_init_data){ 1993 .name = "gcc_ufs_phy_unipro_core_clk", 1994 .parent_data = &(const struct clk_parent_data){ 1995 .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 1996 }, 1997 .num_parents = 1, 1998 .flags = CLK_SET_RATE_PARENT, 1999 .ops = &clk_branch2_ops, 2000 }, 2001 }, 2002 }; 2003 2004 static struct clk_branch gcc_usb30_prim_master_clk = { 2005 .halt_reg = 0xf010, 2006 .halt_check = BRANCH_HALT, 2007 .clkr = { 2008 .enable_reg = 0xf010, 2009 .enable_mask = BIT(0), 2010 .hw.init = &(struct clk_init_data){ 2011 .name = "gcc_usb30_prim_master_clk", 2012 .parent_data = &(const struct clk_parent_data){ 2013 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, 2014 }, 2015 .num_parents = 1, 2016 .flags = CLK_SET_RATE_PARENT, 2017 .ops = &clk_branch2_ops, 2018 }, 2019 }, 2020 }; 2021 2022 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2023 .halt_reg = 0xf018, 2024 .halt_check = BRANCH_HALT, 2025 .clkr = { 2026 .enable_reg = 0xf018, 2027 .enable_mask = BIT(0), 2028 .hw.init = &(struct clk_init_data){ 2029 .name = "gcc_usb30_prim_mock_utmi_clk", 2030 .parent_data = &(const struct clk_parent_data){ 2031 .hw = 2032 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 2033 }, 2034 .num_parents = 1, 2035 .flags = CLK_SET_RATE_PARENT, 2036 .ops = &clk_branch2_ops, 2037 }, 2038 }, 2039 }; 2040 2041 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2042 .halt_reg = 0xf014, 2043 .halt_check = BRANCH_HALT, 2044 .clkr = { 2045 .enable_reg = 0xf014, 2046 .enable_mask = BIT(0), 2047 .hw.init = &(struct clk_init_data){ 2048 .name = "gcc_usb30_prim_sleep_clk", 2049 .ops = &clk_branch2_ops, 2050 }, 2051 }, 2052 }; 2053 2054 static struct clk_branch gcc_usb3_prim_clkref_clk = { 2055 .halt_reg = 0x8c010, 2056 .halt_check = BRANCH_HALT, 2057 .clkr = { 2058 .enable_reg = 0x8c010, 2059 .enable_mask = BIT(0), 2060 .hw.init = &(struct clk_init_data){ 2061 .name = "gcc_usb3_prim_clkref_clk", 2062 .ops = &clk_branch2_ops, 2063 }, 2064 }, 2065 }; 2066 2067 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2068 .halt_reg = 0xf050, 2069 .halt_check = BRANCH_HALT, 2070 .clkr = { 2071 .enable_reg = 0xf050, 2072 .enable_mask = BIT(0), 2073 .hw.init = &(struct clk_init_data){ 2074 .name = "gcc_usb3_prim_phy_aux_clk", 2075 .parent_data = &(const struct clk_parent_data){ 2076 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2077 }, 2078 .num_parents = 1, 2079 .flags = CLK_SET_RATE_PARENT, 2080 .ops = &clk_branch2_ops, 2081 }, 2082 }, 2083 }; 2084 2085 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2086 .halt_reg = 0xf054, 2087 .halt_check = BRANCH_HALT, 2088 .clkr = { 2089 .enable_reg = 0xf054, 2090 .enable_mask = BIT(0), 2091 .hw.init = &(struct clk_init_data){ 2092 .name = "gcc_usb3_prim_phy_com_aux_clk", 2093 .parent_data = &(const struct clk_parent_data){ 2094 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2095 }, 2096 .num_parents = 1, 2097 .flags = CLK_SET_RATE_PARENT, 2098 .ops = &clk_branch2_ops, 2099 }, 2100 }, 2101 }; 2102 2103 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2104 .halt_reg = 0xf058, 2105 .halt_check = BRANCH_HALT_SKIP, 2106 .clkr = { 2107 .enable_reg = 0xf058, 2108 .enable_mask = BIT(0), 2109 .hw.init = &(struct clk_init_data){ 2110 .name = "gcc_usb3_prim_phy_pipe_clk", 2111 .ops = &clk_branch2_ops, 2112 }, 2113 }, 2114 }; 2115 2116 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { 2117 .halt_reg = 0x6a004, 2118 .halt_check = BRANCH_HALT, 2119 .hwcg_reg = 0x6a004, 2120 .hwcg_bit = 1, 2121 .clkr = { 2122 .enable_reg = 0x6a004, 2123 .enable_mask = BIT(0), 2124 .hw.init = &(struct clk_init_data){ 2125 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 2126 .ops = &clk_branch2_ops, 2127 }, 2128 }, 2129 }; 2130 2131 static struct clk_branch gcc_video_axi_clk = { 2132 .halt_reg = 0xb01c, 2133 .halt_check = BRANCH_HALT, 2134 .clkr = { 2135 .enable_reg = 0xb01c, 2136 .enable_mask = BIT(0), 2137 .hw.init = &(struct clk_init_data){ 2138 .name = "gcc_video_axi_clk", 2139 .ops = &clk_branch2_ops, 2140 }, 2141 }, 2142 }; 2143 2144 static struct clk_branch gcc_video_gpll0_div_clk_src = { 2145 .halt_check = BRANCH_HALT_DELAY, 2146 .clkr = { 2147 .enable_reg = 0x52000, 2148 .enable_mask = BIT(20), 2149 .hw.init = &(struct clk_init_data){ 2150 .name = "gcc_video_gpll0_div_clk_src", 2151 .parent_data = &(const struct clk_parent_data){ 2152 .hw = &gcc_pll0_main_div_cdiv.hw, 2153 }, 2154 .num_parents = 1, 2155 .flags = CLK_SET_RATE_PARENT, 2156 .ops = &clk_branch2_ops, 2157 }, 2158 }, 2159 }; 2160 2161 static struct clk_branch gcc_video_throttle_axi_clk = { 2162 .halt_reg = 0xb07c, 2163 .halt_check = BRANCH_HALT, 2164 .hwcg_reg = 0xb07c, 2165 .hwcg_bit = 1, 2166 .clkr = { 2167 .enable_reg = 0xb07c, 2168 .enable_mask = BIT(0), 2169 .hw.init = &(struct clk_init_data){ 2170 .name = "gcc_video_throttle_axi_clk", 2171 .ops = &clk_branch2_ops, 2172 }, 2173 }, 2174 }; 2175 2176 static struct clk_branch gcc_video_xo_clk = { 2177 .halt_reg = 0xb028, 2178 .halt_check = BRANCH_HALT, 2179 .clkr = { 2180 .enable_reg = 0xb028, 2181 .enable_mask = BIT(0), 2182 .hw.init = &(struct clk_init_data){ 2183 .name = "gcc_video_xo_clk", 2184 .ops = &clk_branch2_ops, 2185 }, 2186 }, 2187 }; 2188 2189 static struct clk_branch gcc_mss_cfg_ahb_clk = { 2190 .halt_reg = 0x8a000, 2191 .halt_check = BRANCH_HALT, 2192 .clkr = { 2193 .enable_reg = 0x8a000, 2194 .enable_mask = BIT(0), 2195 .hw.init = &(struct clk_init_data){ 2196 .name = "gcc_mss_cfg_ahb_clk", 2197 .ops = &clk_branch2_ops, 2198 }, 2199 }, 2200 }; 2201 2202 static struct clk_branch gcc_mss_mfab_axis_clk = { 2203 .halt_reg = 0x8a004, 2204 .halt_check = BRANCH_HALT_VOTED, 2205 .clkr = { 2206 .enable_reg = 0x8a004, 2207 .enable_mask = BIT(0), 2208 .hw.init = &(struct clk_init_data){ 2209 .name = "gcc_mss_mfab_axis_clk", 2210 .ops = &clk_branch2_ops, 2211 }, 2212 }, 2213 }; 2214 2215 static struct clk_branch gcc_mss_nav_axi_clk = { 2216 .halt_reg = 0x8a00c, 2217 .halt_check = BRANCH_HALT_VOTED, 2218 .clkr = { 2219 .enable_reg = 0x8a00c, 2220 .enable_mask = BIT(0), 2221 .hw.init = &(struct clk_init_data){ 2222 .name = "gcc_mss_nav_axi_clk", 2223 .ops = &clk_branch2_ops, 2224 }, 2225 }, 2226 }; 2227 2228 static struct clk_branch gcc_mss_snoc_axi_clk = { 2229 .halt_reg = 0x8a150, 2230 .halt_check = BRANCH_HALT, 2231 .clkr = { 2232 .enable_reg = 0x8a150, 2233 .enable_mask = BIT(0), 2234 .hw.init = &(struct clk_init_data){ 2235 .name = "gcc_mss_snoc_axi_clk", 2236 .ops = &clk_branch2_ops, 2237 }, 2238 }, 2239 }; 2240 2241 static struct clk_branch gcc_mss_q6_memnoc_axi_clk = { 2242 .halt_reg = 0x8a154, 2243 .halt_check = BRANCH_HALT, 2244 .clkr = { 2245 .enable_reg = 0x8a154, 2246 .enable_mask = BIT(0), 2247 .hw.init = &(struct clk_init_data){ 2248 .name = "gcc_mss_q6_memnoc_axi_clk", 2249 .ops = &clk_branch2_ops, 2250 }, 2251 }, 2252 }; 2253 2254 static struct clk_branch gcc_lpass_cfg_noc_sway_clk = { 2255 .halt_reg = 0x47018, 2256 .halt_check = BRANCH_HALT_DELAY, 2257 .clkr = { 2258 .enable_reg = 0x47018, 2259 .enable_mask = BIT(0), 2260 .hw.init = &(struct clk_init_data){ 2261 .name = "gcc_lpass_cfg_noc_sway_clk", 2262 .ops = &clk_branch2_ops, 2263 }, 2264 }, 2265 }; 2266 2267 static struct gdsc ufs_phy_gdsc = { 2268 .gdscr = 0x77004, 2269 .pd = { 2270 .name = "ufs_phy_gdsc", 2271 }, 2272 .pwrsts = PWRSTS_OFF_ON, 2273 }; 2274 2275 static struct gdsc usb30_prim_gdsc = { 2276 .gdscr = 0x0f004, 2277 .pd = { 2278 .name = "usb30_prim_gdsc", 2279 }, 2280 .pwrsts = PWRSTS_OFF_ON, 2281 }; 2282 2283 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = { 2284 .gdscr = 0x7d040, 2285 .pd = { 2286 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", 2287 }, 2288 .pwrsts = PWRSTS_OFF_ON, 2289 .flags = VOTABLE, 2290 }; 2291 2292 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = { 2293 .gdscr = 0x7d044, 2294 .pd = { 2295 .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc", 2296 }, 2297 .pwrsts = PWRSTS_OFF_ON, 2298 .flags = VOTABLE, 2299 }; 2300 2301 static struct gdsc *gcc_sc7180_gdscs[] = { 2302 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 2303 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 2304 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = 2305 &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, 2306 [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = 2307 &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc, 2308 }; 2309 2310 2311 static struct clk_hw *gcc_sc7180_hws[] = { 2312 [GCC_GPLL0_MAIN_DIV_CDIV] = &gcc_pll0_main_div_cdiv.hw, 2313 }; 2314 2315 static struct clk_regmap *gcc_sc7180_clocks[] = { 2316 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 2317 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 2318 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2319 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, 2320 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 2321 [GCC_CAMERA_THROTTLE_HF_AXI_CLK] = &gcc_camera_throttle_hf_axi_clk.clkr, 2322 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, 2323 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, 2324 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, 2325 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, 2326 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 2327 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, 2328 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, 2329 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, 2330 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 2331 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, 2332 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, 2333 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 2334 [GCC_DISP_THROTTLE_HF_AXI_CLK] = &gcc_disp_throttle_hf_axi_clk.clkr, 2335 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, 2336 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2337 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 2338 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2339 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 2340 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2341 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 2342 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 2343 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 2344 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 2345 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 2346 [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr, 2347 [GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr, 2348 [GCC_NPU_BWMON_DMA_CFG_AHB_CLK] = &gcc_npu_bwmon_dma_cfg_ahb_clk.clkr, 2349 [GCC_NPU_BWMON_DSP_CFG_AHB_CLK] = &gcc_npu_bwmon_dsp_cfg_ahb_clk.clkr, 2350 [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr, 2351 [GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr, 2352 [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr, 2353 [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr, 2354 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2355 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 2356 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2357 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 2358 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 2359 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, 2360 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, 2361 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, 2362 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 2363 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 2364 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 2365 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 2366 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 2367 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 2368 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 2369 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 2370 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 2371 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 2372 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 2373 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 2374 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 2375 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 2376 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 2377 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 2378 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 2379 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 2380 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 2381 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 2382 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 2383 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 2384 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 2385 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 2386 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 2387 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 2388 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 2389 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 2390 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 2391 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 2392 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 2393 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 2394 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2395 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2396 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 2397 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 2398 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 2399 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2400 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2401 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 2402 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 2403 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, 2404 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 2405 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 2406 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 2407 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 2408 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 2409 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 2410 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 2411 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 2412 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 2413 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 2414 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = 2415 &gcc_ufs_phy_unipro_core_clk_src.clkr, 2416 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 2417 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 2418 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 2419 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 2420 &gcc_usb30_prim_mock_utmi_clk_src.clkr, 2421 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 2422 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 2423 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 2424 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 2425 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 2426 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 2427 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, 2428 [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr, 2429 [GCC_VIDEO_GPLL0_DIV_CLK_SRC] = &gcc_video_gpll0_div_clk_src.clkr, 2430 [GCC_VIDEO_THROTTLE_AXI_CLK] = &gcc_video_throttle_axi_clk.clkr, 2431 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 2432 [GPLL0] = &gpll0.clkr, 2433 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 2434 [GPLL6] = &gpll6.clkr, 2435 [GPLL7] = &gpll7.clkr, 2436 [GPLL4] = &gpll4.clkr, 2437 [GPLL1] = &gpll1.clkr, 2438 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 2439 [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr, 2440 [GCC_MSS_NAV_AXI_CLK] = &gcc_mss_nav_axi_clk.clkr, 2441 [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr, 2442 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, 2443 [GCC_SEC_CTRL_CLK_SRC] = &gcc_sec_ctrl_clk_src.clkr, 2444 [GCC_LPASS_CFG_NOC_SWAY_CLK] = &gcc_lpass_cfg_noc_sway_clk.clkr, 2445 }; 2446 2447 static const struct qcom_reset_map gcc_sc7180_resets[] = { 2448 [GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 }, 2449 [GCC_QUSB2PHY_SEC_BCR] = { 0x26004 }, 2450 [GCC_UFS_PHY_BCR] = { 0x77000 }, 2451 [GCC_USB30_PRIM_BCR] = { 0xf000 }, 2452 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 2453 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 2454 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 2455 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 2456 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 2457 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, 2458 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 2459 }; 2460 2461 static struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 2462 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 2463 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 2464 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 2465 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 2466 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 2467 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 2468 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 2469 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 2470 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 2471 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 2472 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 2473 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 2474 }; 2475 2476 static const struct regmap_config gcc_sc7180_regmap_config = { 2477 .reg_bits = 32, 2478 .reg_stride = 4, 2479 .val_bits = 32, 2480 .max_register = 0x18208c, 2481 .fast_io = true, 2482 }; 2483 2484 static const struct qcom_cc_desc gcc_sc7180_desc = { 2485 .config = &gcc_sc7180_regmap_config, 2486 .clk_hws = gcc_sc7180_hws, 2487 .num_clk_hws = ARRAY_SIZE(gcc_sc7180_hws), 2488 .clks = gcc_sc7180_clocks, 2489 .num_clks = ARRAY_SIZE(gcc_sc7180_clocks), 2490 .resets = gcc_sc7180_resets, 2491 .num_resets = ARRAY_SIZE(gcc_sc7180_resets), 2492 .gdscs = gcc_sc7180_gdscs, 2493 .num_gdscs = ARRAY_SIZE(gcc_sc7180_gdscs), 2494 }; 2495 2496 static const struct of_device_id gcc_sc7180_match_table[] = { 2497 { .compatible = "qcom,gcc-sc7180" }, 2498 { } 2499 }; 2500 MODULE_DEVICE_TABLE(of, gcc_sc7180_match_table); 2501 2502 static int gcc_sc7180_probe(struct platform_device *pdev) 2503 { 2504 struct regmap *regmap; 2505 int ret; 2506 2507 regmap = qcom_cc_map(pdev, &gcc_sc7180_desc); 2508 if (IS_ERR(regmap)) 2509 return PTR_ERR(regmap); 2510 2511 /* 2512 * Disable the GPLL0 active input to MM blocks, NPU 2513 * and GPU via MISC registers. 2514 */ 2515 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3); 2516 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); 2517 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); 2518 2519 /* 2520 * Keep the clocks always-ON 2521 * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_DISP_AHB_CLK 2522 * GCC_GPU_CFG_AHB_CLK 2523 */ 2524 regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); 2525 regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); 2526 regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); 2527 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 2528 2529 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 2530 ARRAY_SIZE(gcc_dfs_clocks)); 2531 if (ret) 2532 return ret; 2533 2534 return qcom_cc_really_probe(pdev, &gcc_sc7180_desc, regmap); 2535 } 2536 2537 static struct platform_driver gcc_sc7180_driver = { 2538 .probe = gcc_sc7180_probe, 2539 .driver = { 2540 .name = "gcc-sc7180", 2541 .of_match_table = gcc_sc7180_match_table, 2542 }, 2543 }; 2544 2545 static int __init gcc_sc7180_init(void) 2546 { 2547 return platform_driver_register(&gcc_sc7180_driver); 2548 } 2549 core_initcall(gcc_sc7180_init); 2550 2551 static void __exit gcc_sc7180_exit(void) 2552 { 2553 platform_driver_unregister(&gcc_sc7180_driver); 2554 } 2555 module_exit(gcc_sc7180_exit); 2556 2557 MODULE_DESCRIPTION("QTI GCC SC7180 Driver"); 2558 MODULE_LICENSE("GPL v2"); 2559