1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021-2022, 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2023, Linaro Limited 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 13 #include <dt-bindings/clock/qcom,sa8775p-gcc.h> 14 15 #include "clk-alpha-pll.h" 16 #include "clk-branch.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "clk-regmap-divider.h" 20 #include "clk-regmap-mux.h" 21 #include "clk-regmap-phy-mux.h" 22 #include "common.h" 23 #include "gdsc.h" 24 #include "reset.h" 25 26 /* Need to match the order of clocks in DT binding */ 27 enum { 28 DT_BI_TCXO, 29 DT_SLEEP_CLK, 30 DT_UFS_PHY_RX_SYMBOL_0_CLK, 31 DT_UFS_PHY_RX_SYMBOL_1_CLK, 32 DT_UFS_PHY_TX_SYMBOL_0_CLK, 33 DT_UFS_CARD_RX_SYMBOL_0_CLK, 34 DT_UFS_CARD_RX_SYMBOL_1_CLK, 35 DT_UFS_CARD_TX_SYMBOL_0_CLK, 36 DT_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK, 37 DT_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK, 38 DT_PCIE_0_PIPE_CLK, 39 DT_PCIE_1_PIPE_CLK, 40 DT_PCIE_PHY_AUX_CLK, 41 DT_RXC0_REF_CLK, 42 DT_RXC1_REF_CLK, 43 }; 44 45 enum { 46 P_BI_TCXO, 47 P_GCC_GPLL0_OUT_EVEN, 48 P_GCC_GPLL0_OUT_MAIN, 49 P_GCC_GPLL1_OUT_MAIN, 50 P_GCC_GPLL4_OUT_MAIN, 51 P_GCC_GPLL5_OUT_MAIN, 52 P_GCC_GPLL7_OUT_MAIN, 53 P_GCC_GPLL9_OUT_MAIN, 54 P_PCIE_0_PIPE_CLK, 55 P_PCIE_1_PIPE_CLK, 56 P_PCIE_PHY_AUX_CLK, 57 P_RXC0_REF_CLK, 58 P_RXC1_REF_CLK, 59 P_SLEEP_CLK, 60 P_UFS_CARD_RX_SYMBOL_0_CLK, 61 P_UFS_CARD_RX_SYMBOL_1_CLK, 62 P_UFS_CARD_TX_SYMBOL_0_CLK, 63 P_UFS_PHY_RX_SYMBOL_0_CLK, 64 P_UFS_PHY_RX_SYMBOL_1_CLK, 65 P_UFS_PHY_TX_SYMBOL_0_CLK, 66 P_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK, 67 P_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK, 68 }; 69 70 static const struct clk_parent_data gcc_parent_data_tcxo = { .index = DT_BI_TCXO }; 71 72 static struct clk_alpha_pll gcc_gpll0 = { 73 .offset = 0x0, 74 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 75 .clkr = { 76 .enable_reg = 0x4b028, 77 .enable_mask = BIT(0), 78 .hw.init = &(const struct clk_init_data){ 79 .name = "gcc_gpll0", 80 .parent_data = &gcc_parent_data_tcxo, 81 .num_parents = 1, 82 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 83 }, 84 }, 85 }; 86 87 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 88 { 0x1, 2 }, 89 { } 90 }; 91 92 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 93 .offset = 0x0, 94 .post_div_shift = 10, 95 .post_div_table = post_div_table_gcc_gpll0_out_even, 96 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 97 .width = 4, 98 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 99 .clkr.hw.init = &(const struct clk_init_data){ 100 .name = "gcc_gpll0_out_even", 101 .parent_hws = (const struct clk_hw*[]){ 102 &gcc_gpll0.clkr.hw, 103 }, 104 .num_parents = 1, 105 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 106 }, 107 }; 108 109 static struct clk_alpha_pll gcc_gpll1 = { 110 .offset = 0x1000, 111 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 112 .clkr = { 113 .enable_reg = 0x4b028, 114 .enable_mask = BIT(1), 115 .hw.init = &(const struct clk_init_data){ 116 .name = "gcc_gpll1", 117 .parent_data = &gcc_parent_data_tcxo, 118 .num_parents = 1, 119 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 120 }, 121 }, 122 }; 123 124 static struct clk_alpha_pll gcc_gpll4 = { 125 .offset = 0x4000, 126 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 127 .clkr = { 128 .enable_reg = 0x4b028, 129 .enable_mask = BIT(4), 130 .hw.init = &(const struct clk_init_data){ 131 .name = "gcc_gpll4", 132 .parent_data = &gcc_parent_data_tcxo, 133 .num_parents = 1, 134 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 135 }, 136 }, 137 }; 138 139 static struct clk_alpha_pll gcc_gpll5 = { 140 .offset = 0x5000, 141 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 142 .clkr = { 143 .enable_reg = 0x4b028, 144 .enable_mask = BIT(5), 145 .hw.init = &(const struct clk_init_data){ 146 .name = "gcc_gpll5", 147 .parent_data = &gcc_parent_data_tcxo, 148 .num_parents = 1, 149 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 150 }, 151 }, 152 }; 153 154 static struct clk_alpha_pll gcc_gpll7 = { 155 .offset = 0x7000, 156 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 157 .clkr = { 158 .enable_reg = 0x4b028, 159 .enable_mask = BIT(7), 160 .hw.init = &(const struct clk_init_data){ 161 .name = "gcc_gpll7", 162 .parent_data = &gcc_parent_data_tcxo, 163 .num_parents = 1, 164 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 165 }, 166 }, 167 }; 168 169 static struct clk_alpha_pll gcc_gpll9 = { 170 .offset = 0x9000, 171 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 172 .clkr = { 173 .enable_reg = 0x4b028, 174 .enable_mask = BIT(9), 175 .hw.init = &(const struct clk_init_data){ 176 .name = "gcc_gpll9", 177 .parent_data = &gcc_parent_data_tcxo, 178 .num_parents = 1, 179 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 180 }, 181 }, 182 }; 183 184 static const struct parent_map gcc_parent_map_0[] = { 185 { P_BI_TCXO, 0 }, 186 { P_GCC_GPLL0_OUT_MAIN, 1 }, 187 { P_GCC_GPLL0_OUT_EVEN, 6 }, 188 }; 189 190 static const struct clk_parent_data gcc_parent_data_0[] = { 191 { .index = DT_BI_TCXO }, 192 { .hw = &gcc_gpll0.clkr.hw }, 193 { .hw = &gcc_gpll0_out_even.clkr.hw }, 194 }; 195 196 static const struct parent_map gcc_parent_map_1[] = { 197 { P_BI_TCXO, 0 }, 198 { P_GCC_GPLL0_OUT_MAIN, 1 }, 199 { P_GCC_GPLL4_OUT_MAIN, 5 }, 200 { P_GCC_GPLL0_OUT_EVEN, 6 }, 201 }; 202 203 static const struct clk_parent_data gcc_parent_data_1[] = { 204 { .index = DT_BI_TCXO }, 205 { .hw = &gcc_gpll0.clkr.hw }, 206 { .hw = &gcc_gpll4.clkr.hw }, 207 { .hw = &gcc_gpll0_out_even.clkr.hw }, 208 }; 209 210 static const struct parent_map gcc_parent_map_2[] = { 211 { P_BI_TCXO, 0 }, 212 { P_GCC_GPLL0_OUT_MAIN, 1 }, 213 { P_SLEEP_CLK, 5 }, 214 { P_GCC_GPLL0_OUT_EVEN, 6 }, 215 }; 216 217 static const struct clk_parent_data gcc_parent_data_2[] = { 218 { .index = DT_BI_TCXO }, 219 { .hw = &gcc_gpll0.clkr.hw }, 220 { .index = DT_SLEEP_CLK }, 221 { .hw = &gcc_gpll0_out_even.clkr.hw }, 222 }; 223 224 static const struct parent_map gcc_parent_map_3[] = { 225 { P_BI_TCXO, 0 }, 226 { P_SLEEP_CLK, 5 }, 227 }; 228 229 static const struct clk_parent_data gcc_parent_data_3[] = { 230 { .index = DT_BI_TCXO }, 231 { .index = DT_SLEEP_CLK }, 232 }; 233 234 static const struct parent_map gcc_parent_map_4[] = { 235 { P_BI_TCXO, 0 }, 236 { P_GCC_GPLL0_OUT_MAIN, 1 }, 237 { P_GCC_GPLL1_OUT_MAIN, 4 }, 238 { P_GCC_GPLL4_OUT_MAIN, 5 }, 239 { P_GCC_GPLL0_OUT_EVEN, 6 }, 240 }; 241 242 static const struct clk_parent_data gcc_parent_data_4[] = { 243 { .index = DT_BI_TCXO }, 244 { .hw = &gcc_gpll0.clkr.hw }, 245 { .hw = &gcc_gpll1.clkr.hw }, 246 { .hw = &gcc_gpll4.clkr.hw }, 247 { .hw = &gcc_gpll0_out_even.clkr.hw }, 248 }; 249 250 static const struct parent_map gcc_parent_map_5[] = { 251 { P_BI_TCXO, 0 }, 252 }; 253 254 static const struct clk_parent_data gcc_parent_data_5[] = { 255 { .index = DT_BI_TCXO }, 256 }; 257 258 static const struct parent_map gcc_parent_map_6[] = { 259 { P_BI_TCXO, 0 }, 260 { P_GCC_GPLL7_OUT_MAIN, 2 }, 261 { P_GCC_GPLL4_OUT_MAIN, 5 }, 262 { P_GCC_GPLL0_OUT_EVEN, 6 }, 263 }; 264 265 static const struct clk_parent_data gcc_parent_data_6[] = { 266 { .index = DT_BI_TCXO }, 267 { .hw = &gcc_gpll7.clkr.hw }, 268 { .hw = &gcc_gpll4.clkr.hw }, 269 { .hw = &gcc_gpll0_out_even.clkr.hw }, 270 }; 271 272 static const struct parent_map gcc_parent_map_7[] = { 273 { P_BI_TCXO, 0 }, 274 { P_GCC_GPLL7_OUT_MAIN, 2 }, 275 { P_RXC0_REF_CLK, 3 }, 276 { P_GCC_GPLL0_OUT_EVEN, 6 }, 277 }; 278 279 static const struct clk_parent_data gcc_parent_data_7[] = { 280 { .index = DT_BI_TCXO }, 281 { .hw = &gcc_gpll7.clkr.hw }, 282 { .index = DT_RXC0_REF_CLK }, 283 { .hw = &gcc_gpll0_out_even.clkr.hw }, 284 }; 285 286 static const struct parent_map gcc_parent_map_8[] = { 287 { P_BI_TCXO, 0 }, 288 { P_GCC_GPLL7_OUT_MAIN, 2 }, 289 { P_RXC1_REF_CLK, 3 }, 290 { P_GCC_GPLL0_OUT_EVEN, 6 }, 291 }; 292 293 static const struct clk_parent_data gcc_parent_data_8[] = { 294 { .index = DT_BI_TCXO }, 295 { .hw = &gcc_gpll7.clkr.hw }, 296 { .index = DT_RXC1_REF_CLK }, 297 { .hw = &gcc_gpll0_out_even.clkr.hw }, 298 }; 299 300 static const struct parent_map gcc_parent_map_9[] = { 301 { P_PCIE_PHY_AUX_CLK, 1 }, 302 { P_BI_TCXO, 2 }, 303 }; 304 305 static const struct clk_parent_data gcc_parent_data_9[] = { 306 { .index = DT_PCIE_PHY_AUX_CLK }, 307 { .index = DT_BI_TCXO }, 308 }; 309 310 static const struct parent_map gcc_parent_map_11[] = { 311 { P_PCIE_PHY_AUX_CLK, 1 }, 312 { P_BI_TCXO, 2 }, 313 }; 314 315 static const struct clk_parent_data gcc_parent_data_11[] = { 316 { .index = DT_PCIE_PHY_AUX_CLK }, 317 { .index = DT_BI_TCXO }, 318 }; 319 320 static const struct parent_map gcc_parent_map_13[] = { 321 { P_BI_TCXO, 0 }, 322 { P_GCC_GPLL0_OUT_MAIN, 1 }, 323 { P_GCC_GPLL9_OUT_MAIN, 2 }, 324 { P_GCC_GPLL4_OUT_MAIN, 5 }, 325 { P_GCC_GPLL0_OUT_EVEN, 6 }, 326 }; 327 328 static const struct clk_parent_data gcc_parent_data_13[] = { 329 { .index = DT_BI_TCXO }, 330 { .hw = &gcc_gpll0.clkr.hw }, 331 { .hw = &gcc_gpll9.clkr.hw }, 332 { .hw = &gcc_gpll4.clkr.hw }, 333 { .hw = &gcc_gpll0_out_even.clkr.hw }, 334 }; 335 336 static const struct parent_map gcc_parent_map_14[] = { 337 { P_BI_TCXO, 0 }, 338 { P_GCC_GPLL0_OUT_MAIN, 1 }, 339 }; 340 341 static const struct clk_parent_data gcc_parent_data_14[] = { 342 { .index = DT_BI_TCXO }, 343 { .hw = &gcc_gpll0.clkr.hw }, 344 }; 345 346 static const struct parent_map gcc_parent_map_15[] = { 347 { P_BI_TCXO, 0 }, 348 { P_GCC_GPLL7_OUT_MAIN, 2 }, 349 { P_GCC_GPLL5_OUT_MAIN, 3 }, 350 { P_GCC_GPLL4_OUT_MAIN, 5 }, 351 { P_GCC_GPLL0_OUT_EVEN, 6 }, 352 }; 353 354 static const struct clk_parent_data gcc_parent_data_15[] = { 355 { .index = DT_BI_TCXO }, 356 { .hw = &gcc_gpll7.clkr.hw }, 357 { .hw = &gcc_gpll5.clkr.hw }, 358 { .hw = &gcc_gpll4.clkr.hw }, 359 { .hw = &gcc_gpll0_out_even.clkr.hw }, 360 }; 361 362 static const struct parent_map gcc_parent_map_16[] = { 363 { P_UFS_CARD_RX_SYMBOL_0_CLK, 0 }, 364 { P_BI_TCXO, 2 }, 365 }; 366 367 static const struct clk_parent_data gcc_parent_data_16[] = { 368 { .index = DT_UFS_CARD_RX_SYMBOL_0_CLK }, 369 { .index = DT_BI_TCXO }, 370 }; 371 372 static const struct parent_map gcc_parent_map_17[] = { 373 { P_UFS_CARD_RX_SYMBOL_1_CLK, 0 }, 374 { P_BI_TCXO, 2 }, 375 }; 376 377 static const struct clk_parent_data gcc_parent_data_17[] = { 378 { .index = DT_UFS_CARD_RX_SYMBOL_1_CLK }, 379 { .index = DT_BI_TCXO }, 380 }; 381 382 static const struct parent_map gcc_parent_map_18[] = { 383 { P_UFS_CARD_TX_SYMBOL_0_CLK, 0 }, 384 { P_BI_TCXO, 2 }, 385 }; 386 387 static const struct clk_parent_data gcc_parent_data_18[] = { 388 { .index = DT_UFS_CARD_TX_SYMBOL_0_CLK }, 389 { .index = DT_BI_TCXO }, 390 }; 391 392 static const struct parent_map gcc_parent_map_19[] = { 393 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 }, 394 { P_BI_TCXO, 2 }, 395 }; 396 397 static const struct clk_parent_data gcc_parent_data_19[] = { 398 { .index = DT_UFS_PHY_RX_SYMBOL_0_CLK }, 399 { .index = DT_BI_TCXO }, 400 }; 401 402 static const struct parent_map gcc_parent_map_20[] = { 403 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 }, 404 { P_BI_TCXO, 2 }, 405 }; 406 407 static const struct clk_parent_data gcc_parent_data_20[] = { 408 { .index = DT_UFS_PHY_RX_SYMBOL_1_CLK }, 409 { .index = DT_BI_TCXO }, 410 }; 411 412 static const struct parent_map gcc_parent_map_21[] = { 413 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 }, 414 { P_BI_TCXO, 2 }, 415 }; 416 417 static const struct clk_parent_data gcc_parent_data_21[] = { 418 { .index = DT_UFS_PHY_TX_SYMBOL_0_CLK }, 419 { .index = DT_BI_TCXO }, 420 }; 421 422 static const struct parent_map gcc_parent_map_22[] = { 423 { P_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK, 0 }, 424 { P_BI_TCXO, 2 }, 425 }; 426 427 static const struct clk_parent_data gcc_parent_data_22[] = { 428 { .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK }, 429 { .index = DT_BI_TCXO }, 430 }; 431 432 static const struct parent_map gcc_parent_map_23[] = { 433 { P_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK, 0 }, 434 { P_BI_TCXO, 2 }, 435 }; 436 437 static const struct clk_parent_data gcc_parent_data_23[] = { 438 { .index = DT_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK }, 439 { .index = DT_BI_TCXO }, 440 }; 441 442 static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = { 443 .reg = 0xa9074, 444 .shift = 0, 445 .width = 2, 446 .parent_map = gcc_parent_map_9, 447 .clkr = { 448 .hw.init = &(const struct clk_init_data){ 449 .name = "gcc_pcie_0_phy_aux_clk_src", 450 .parent_data = gcc_parent_data_9, 451 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 452 .ops = &clk_regmap_mux_closest_ops, 453 }, 454 }, 455 }; 456 457 static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { 458 .reg = 0xa906c, 459 .clkr = { 460 .hw.init = &(const struct clk_init_data){ 461 .name = "gcc_pcie_0_pipe_clk_src", 462 .parent_data = &(const struct clk_parent_data){ 463 .index = DT_PCIE_0_PIPE_CLK, 464 }, 465 .num_parents = 1, 466 .ops = &clk_regmap_phy_mux_ops, 467 }, 468 }, 469 }; 470 471 static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = { 472 .reg = 0x77074, 473 .shift = 0, 474 .width = 2, 475 .parent_map = gcc_parent_map_11, 476 .clkr = { 477 .hw.init = &(const struct clk_init_data){ 478 .name = "gcc_pcie_1_phy_aux_clk_src", 479 .parent_data = gcc_parent_data_11, 480 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 481 .ops = &clk_regmap_mux_closest_ops, 482 }, 483 }, 484 }; 485 486 static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = { 487 .reg = 0x7706c, 488 .clkr = { 489 .hw.init = &(const struct clk_init_data){ 490 .name = "gcc_pcie_1_pipe_clk_src", 491 .parent_data = &(const struct clk_parent_data) { 492 .index = DT_PCIE_1_PIPE_CLK, 493 }, 494 .num_parents = 1, 495 .ops = &clk_regmap_phy_mux_ops, 496 }, 497 }, 498 }; 499 500 static struct clk_regmap_mux gcc_ufs_card_rx_symbol_0_clk_src = { 501 .reg = 0x81060, 502 .shift = 0, 503 .width = 2, 504 .parent_map = gcc_parent_map_16, 505 .clkr = { 506 .hw.init = &(const struct clk_init_data){ 507 .name = "gcc_ufs_card_rx_symbol_0_clk_src", 508 .parent_data = gcc_parent_data_16, 509 .num_parents = ARRAY_SIZE(gcc_parent_data_16), 510 .ops = &clk_regmap_mux_closest_ops, 511 }, 512 }, 513 }; 514 515 static struct clk_regmap_mux gcc_ufs_card_rx_symbol_1_clk_src = { 516 .reg = 0x810d0, 517 .shift = 0, 518 .width = 2, 519 .parent_map = gcc_parent_map_17, 520 .clkr = { 521 .hw.init = &(const struct clk_init_data){ 522 .name = "gcc_ufs_card_rx_symbol_1_clk_src", 523 .parent_data = gcc_parent_data_17, 524 .num_parents = ARRAY_SIZE(gcc_parent_data_17), 525 .ops = &clk_regmap_mux_closest_ops, 526 }, 527 }, 528 }; 529 530 static struct clk_regmap_mux gcc_ufs_card_tx_symbol_0_clk_src = { 531 .reg = 0x81050, 532 .shift = 0, 533 .width = 2, 534 .parent_map = gcc_parent_map_18, 535 .clkr = { 536 .hw.init = &(const struct clk_init_data){ 537 .name = "gcc_ufs_card_tx_symbol_0_clk_src", 538 .parent_data = gcc_parent_data_18, 539 .num_parents = ARRAY_SIZE(gcc_parent_data_18), 540 .ops = &clk_regmap_mux_closest_ops, 541 }, 542 }, 543 }; 544 545 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = { 546 .reg = 0x83060, 547 .shift = 0, 548 .width = 2, 549 .parent_map = gcc_parent_map_19, 550 .clkr = { 551 .hw.init = &(const struct clk_init_data){ 552 .name = "gcc_ufs_phy_rx_symbol_0_clk_src", 553 .parent_data = gcc_parent_data_19, 554 .num_parents = ARRAY_SIZE(gcc_parent_data_19), 555 .ops = &clk_regmap_mux_closest_ops, 556 }, 557 }, 558 }; 559 560 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = { 561 .reg = 0x830d0, 562 .shift = 0, 563 .width = 2, 564 .parent_map = gcc_parent_map_20, 565 .clkr = { 566 .hw.init = &(const struct clk_init_data){ 567 .name = "gcc_ufs_phy_rx_symbol_1_clk_src", 568 .parent_data = gcc_parent_data_20, 569 .num_parents = ARRAY_SIZE(gcc_parent_data_20), 570 .ops = &clk_regmap_mux_closest_ops, 571 }, 572 }, 573 }; 574 575 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = { 576 .reg = 0x83050, 577 .shift = 0, 578 .width = 2, 579 .parent_map = gcc_parent_map_21, 580 .clkr = { 581 .hw.init = &(const struct clk_init_data){ 582 .name = "gcc_ufs_phy_tx_symbol_0_clk_src", 583 .parent_data = gcc_parent_data_21, 584 .num_parents = ARRAY_SIZE(gcc_parent_data_21), 585 .ops = &clk_regmap_mux_closest_ops, 586 }, 587 }, 588 }; 589 590 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 591 .reg = 0x1b068, 592 .shift = 0, 593 .width = 2, 594 .parent_map = gcc_parent_map_22, 595 .clkr = { 596 .hw.init = &(const struct clk_init_data){ 597 .name = "gcc_usb3_prim_phy_pipe_clk_src", 598 .parent_data = gcc_parent_data_22, 599 .num_parents = ARRAY_SIZE(gcc_parent_data_22), 600 .ops = &clk_regmap_mux_closest_ops, 601 }, 602 }, 603 }; 604 605 static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = { 606 .reg = 0x2f068, 607 .shift = 0, 608 .width = 2, 609 .parent_map = gcc_parent_map_23, 610 .clkr = { 611 .hw.init = &(const struct clk_init_data){ 612 .name = "gcc_usb3_sec_phy_pipe_clk_src", 613 .parent_data = gcc_parent_data_23, 614 .num_parents = ARRAY_SIZE(gcc_parent_data_23), 615 .ops = &clk_regmap_mux_closest_ops, 616 }, 617 }, 618 }; 619 620 static const struct freq_tbl ftbl_gcc_emac0_phy_aux_clk_src[] = { 621 F(19200000, P_BI_TCXO, 1, 0, 0), 622 { } 623 }; 624 625 static struct clk_rcg2 gcc_emac0_phy_aux_clk_src = { 626 .cmd_rcgr = 0xb6028, 627 .mnd_width = 0, 628 .hid_width = 5, 629 .parent_map = gcc_parent_map_3, 630 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 631 .clkr.hw.init = &(const struct clk_init_data){ 632 .name = "gcc_emac0_phy_aux_clk_src", 633 .parent_data = gcc_parent_data_3, 634 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 635 .ops = &clk_rcg2_shared_ops, 636 }, 637 }; 638 639 static const struct freq_tbl ftbl_gcc_emac0_ptp_clk_src[] = { 640 F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0), 641 F(230400000, P_GCC_GPLL4_OUT_MAIN, 3.5, 0, 0), 642 { } 643 }; 644 645 static struct clk_rcg2 gcc_emac0_ptp_clk_src = { 646 .cmd_rcgr = 0xb6060, 647 .mnd_width = 16, 648 .hid_width = 5, 649 .parent_map = gcc_parent_map_6, 650 .freq_tbl = ftbl_gcc_emac0_ptp_clk_src, 651 .clkr.hw.init = &(const struct clk_init_data){ 652 .name = "gcc_emac0_ptp_clk_src", 653 .parent_data = gcc_parent_data_6, 654 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 655 .ops = &clk_rcg2_shared_ops, 656 }, 657 }; 658 659 static const struct freq_tbl ftbl_gcc_emac0_rgmii_clk_src[] = { 660 F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0), 661 F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0), 662 { } 663 }; 664 665 static struct clk_rcg2 gcc_emac0_rgmii_clk_src = { 666 .cmd_rcgr = 0xb6048, 667 .mnd_width = 16, 668 .hid_width = 5, 669 .parent_map = gcc_parent_map_7, 670 .freq_tbl = ftbl_gcc_emac0_rgmii_clk_src, 671 .clkr.hw.init = &(const struct clk_init_data){ 672 .name = "gcc_emac0_rgmii_clk_src", 673 .parent_data = gcc_parent_data_7, 674 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 675 .ops = &clk_rcg2_shared_ops, 676 }, 677 }; 678 679 static struct clk_rcg2 gcc_emac1_phy_aux_clk_src = { 680 .cmd_rcgr = 0xb4028, 681 .mnd_width = 0, 682 .hid_width = 5, 683 .parent_map = gcc_parent_map_3, 684 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 685 .clkr.hw.init = &(const struct clk_init_data){ 686 .name = "gcc_emac1_phy_aux_clk_src", 687 .parent_data = gcc_parent_data_3, 688 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 689 .ops = &clk_rcg2_shared_ops, 690 }, 691 }; 692 693 static struct clk_rcg2 gcc_emac1_ptp_clk_src = { 694 .cmd_rcgr = 0xb4060, 695 .mnd_width = 16, 696 .hid_width = 5, 697 .parent_map = gcc_parent_map_6, 698 .freq_tbl = ftbl_gcc_emac0_ptp_clk_src, 699 .clkr.hw.init = &(const struct clk_init_data){ 700 .name = "gcc_emac1_ptp_clk_src", 701 .parent_data = gcc_parent_data_6, 702 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 703 .ops = &clk_rcg2_shared_ops, 704 }, 705 }; 706 707 static struct clk_rcg2 gcc_emac1_rgmii_clk_src = { 708 .cmd_rcgr = 0xb4048, 709 .mnd_width = 16, 710 .hid_width = 5, 711 .parent_map = gcc_parent_map_8, 712 .freq_tbl = ftbl_gcc_emac0_rgmii_clk_src, 713 .clkr.hw.init = &(const struct clk_init_data){ 714 .name = "gcc_emac1_rgmii_clk_src", 715 .parent_data = gcc_parent_data_8, 716 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 717 .ops = &clk_rcg2_shared_ops, 718 }, 719 }; 720 721 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 722 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 723 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 724 { } 725 }; 726 727 static struct clk_rcg2 gcc_gp1_clk_src = { 728 .cmd_rcgr = 0x70004, 729 .mnd_width = 16, 730 .hid_width = 5, 731 .parent_map = gcc_parent_map_2, 732 .freq_tbl = ftbl_gcc_gp1_clk_src, 733 .clkr.hw.init = &(const struct clk_init_data){ 734 .name = "gcc_gp1_clk_src", 735 .parent_data = gcc_parent_data_2, 736 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 737 .ops = &clk_rcg2_shared_ops, 738 }, 739 }; 740 741 static struct clk_rcg2 gcc_gp2_clk_src = { 742 .cmd_rcgr = 0x71004, 743 .mnd_width = 16, 744 .hid_width = 5, 745 .parent_map = gcc_parent_map_2, 746 .freq_tbl = ftbl_gcc_gp1_clk_src, 747 .clkr.hw.init = &(const struct clk_init_data){ 748 .name = "gcc_gp2_clk_src", 749 .parent_data = gcc_parent_data_2, 750 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 751 .ops = &clk_rcg2_shared_ops, 752 }, 753 }; 754 755 static struct clk_rcg2 gcc_gp3_clk_src = { 756 .cmd_rcgr = 0x62004, 757 .mnd_width = 16, 758 .hid_width = 5, 759 .parent_map = gcc_parent_map_2, 760 .freq_tbl = ftbl_gcc_gp1_clk_src, 761 .clkr.hw.init = &(const struct clk_init_data){ 762 .name = "gcc_gp3_clk_src", 763 .parent_data = gcc_parent_data_2, 764 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 765 .ops = &clk_rcg2_shared_ops, 766 }, 767 }; 768 769 static struct clk_rcg2 gcc_gp4_clk_src = { 770 .cmd_rcgr = 0x1e004, 771 .mnd_width = 16, 772 .hid_width = 5, 773 .parent_map = gcc_parent_map_2, 774 .freq_tbl = ftbl_gcc_gp1_clk_src, 775 .clkr.hw.init = &(const struct clk_init_data){ 776 .name = "gcc_gp4_clk_src", 777 .parent_data = gcc_parent_data_2, 778 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 779 .ops = &clk_rcg2_shared_ops, 780 }, 781 }; 782 783 static struct clk_rcg2 gcc_gp5_clk_src = { 784 .cmd_rcgr = 0x1f004, 785 .mnd_width = 16, 786 .hid_width = 5, 787 .parent_map = gcc_parent_map_2, 788 .freq_tbl = ftbl_gcc_gp1_clk_src, 789 .clkr.hw.init = &(const struct clk_init_data){ 790 .name = "gcc_gp5_clk_src", 791 .parent_data = gcc_parent_data_2, 792 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 793 .ops = &clk_rcg2_shared_ops, 794 }, 795 }; 796 797 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 798 .cmd_rcgr = 0xa9078, 799 .mnd_width = 16, 800 .hid_width = 5, 801 .parent_map = gcc_parent_map_3, 802 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 803 .clkr.hw.init = &(const struct clk_init_data){ 804 .name = "gcc_pcie_0_aux_clk_src", 805 .parent_data = gcc_parent_data_3, 806 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 807 .ops = &clk_rcg2_shared_ops, 808 }, 809 }; 810 811 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 812 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 813 { } 814 }; 815 816 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 817 .cmd_rcgr = 0xa9054, 818 .mnd_width = 0, 819 .hid_width = 5, 820 .parent_map = gcc_parent_map_0, 821 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 822 .clkr.hw.init = &(const struct clk_init_data){ 823 .name = "gcc_pcie_0_phy_rchng_clk_src", 824 .parent_data = gcc_parent_data_0, 825 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 826 .ops = &clk_rcg2_shared_ops, 827 }, 828 }; 829 830 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 831 .cmd_rcgr = 0x77078, 832 .mnd_width = 16, 833 .hid_width = 5, 834 .parent_map = gcc_parent_map_3, 835 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 836 .clkr.hw.init = &(const struct clk_init_data){ 837 .name = "gcc_pcie_1_aux_clk_src", 838 .parent_data = gcc_parent_data_3, 839 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 840 .ops = &clk_rcg2_shared_ops, 841 }, 842 }; 843 844 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { 845 .cmd_rcgr = 0x77054, 846 .mnd_width = 0, 847 .hid_width = 5, 848 .parent_map = gcc_parent_map_0, 849 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 850 .clkr.hw.init = &(const struct clk_init_data){ 851 .name = "gcc_pcie_1_phy_rchng_clk_src", 852 .parent_data = gcc_parent_data_0, 853 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 854 .ops = &clk_rcg2_shared_ops, 855 }, 856 }; 857 858 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 859 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 860 { } 861 }; 862 863 static struct clk_rcg2 gcc_pdm2_clk_src = { 864 .cmd_rcgr = 0x3f010, 865 .mnd_width = 0, 866 .hid_width = 5, 867 .parent_map = gcc_parent_map_0, 868 .freq_tbl = ftbl_gcc_pdm2_clk_src, 869 .clkr.hw.init = &(const struct clk_init_data){ 870 .name = "gcc_pdm2_clk_src", 871 .parent_data = gcc_parent_data_0, 872 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 873 .ops = &clk_rcg2_shared_ops, 874 }, 875 }; 876 877 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 878 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 879 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 880 F(19200000, P_BI_TCXO, 1, 0, 0), 881 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 882 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 883 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 884 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 885 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 886 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 887 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 888 { } 889 }; 890 891 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 892 .name = "gcc_qupv3_wrap0_s0_clk_src", 893 .parent_data = gcc_parent_data_0, 894 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 895 .ops = &clk_rcg2_shared_ops, 896 }; 897 898 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 899 .cmd_rcgr = 0x23154, 900 .mnd_width = 16, 901 .hid_width = 5, 902 .parent_map = gcc_parent_map_0, 903 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 904 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 905 }; 906 907 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 908 .name = "gcc_qupv3_wrap0_s1_clk_src", 909 .parent_data = gcc_parent_data_0, 910 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 911 .ops = &clk_rcg2_shared_ops, 912 }; 913 914 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 915 .cmd_rcgr = 0x23288, 916 .mnd_width = 16, 917 .hid_width = 5, 918 .parent_map = gcc_parent_map_0, 919 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 920 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 921 }; 922 923 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = { 924 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 925 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 926 F(19200000, P_BI_TCXO, 1, 0, 0), 927 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 928 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 929 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 930 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 931 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 932 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 933 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 934 { } 935 }; 936 937 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 938 .name = "gcc_qupv3_wrap0_s2_clk_src", 939 .parent_data = gcc_parent_data_0, 940 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 941 .ops = &clk_rcg2_shared_ops, 942 }; 943 944 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 945 .cmd_rcgr = 0x233bc, 946 .mnd_width = 16, 947 .hid_width = 5, 948 .parent_map = gcc_parent_map_0, 949 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 950 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 951 }; 952 953 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 954 .name = "gcc_qupv3_wrap0_s3_clk_src", 955 .parent_data = gcc_parent_data_0, 956 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 957 .ops = &clk_rcg2_shared_ops, 958 }; 959 960 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 961 .cmd_rcgr = 0x234f0, 962 .mnd_width = 16, 963 .hid_width = 5, 964 .parent_map = gcc_parent_map_0, 965 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 966 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 967 }; 968 969 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 970 .name = "gcc_qupv3_wrap0_s4_clk_src", 971 .parent_data = gcc_parent_data_1, 972 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 973 .ops = &clk_rcg2_shared_ops, 974 }; 975 976 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 977 .cmd_rcgr = 0x23624, 978 .mnd_width = 16, 979 .hid_width = 5, 980 .parent_map = gcc_parent_map_1, 981 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 982 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 983 }; 984 985 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 986 .name = "gcc_qupv3_wrap0_s5_clk_src", 987 .parent_data = gcc_parent_data_0, 988 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 989 .ops = &clk_rcg2_shared_ops, 990 }; 991 992 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 993 .cmd_rcgr = 0x23758, 994 .mnd_width = 16, 995 .hid_width = 5, 996 .parent_map = gcc_parent_map_0, 997 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 998 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 999 }; 1000 1001 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 1002 .name = "gcc_qupv3_wrap0_s6_clk_src", 1003 .parent_data = gcc_parent_data_0, 1004 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1005 .ops = &clk_rcg2_shared_ops, 1006 }; 1007 1008 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 1009 .cmd_rcgr = 0x2388c, 1010 .mnd_width = 16, 1011 .hid_width = 5, 1012 .parent_map = gcc_parent_map_0, 1013 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1014 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 1015 }; 1016 1017 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 1018 .name = "gcc_qupv3_wrap1_s0_clk_src", 1019 .parent_data = gcc_parent_data_0, 1020 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1021 .ops = &clk_rcg2_shared_ops, 1022 }; 1023 1024 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 1025 .cmd_rcgr = 0x24154, 1026 .mnd_width = 16, 1027 .hid_width = 5, 1028 .parent_map = gcc_parent_map_0, 1029 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1030 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 1031 }; 1032 1033 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 1034 .name = "gcc_qupv3_wrap1_s1_clk_src", 1035 .parent_data = gcc_parent_data_0, 1036 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1037 .ops = &clk_rcg2_shared_ops, 1038 }; 1039 1040 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 1041 .cmd_rcgr = 0x24288, 1042 .mnd_width = 16, 1043 .hid_width = 5, 1044 .parent_map = gcc_parent_map_0, 1045 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1046 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 1047 }; 1048 1049 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 1050 .name = "gcc_qupv3_wrap1_s2_clk_src", 1051 .parent_data = gcc_parent_data_0, 1052 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1053 .ops = &clk_rcg2_shared_ops, 1054 }; 1055 1056 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 1057 .cmd_rcgr = 0x243bc, 1058 .mnd_width = 16, 1059 .hid_width = 5, 1060 .parent_map = gcc_parent_map_0, 1061 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1062 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 1063 }; 1064 1065 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 1066 .name = "gcc_qupv3_wrap1_s3_clk_src", 1067 .parent_data = gcc_parent_data_0, 1068 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1069 .ops = &clk_rcg2_shared_ops, 1070 }; 1071 1072 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 1073 .cmd_rcgr = 0x244f0, 1074 .mnd_width = 16, 1075 .hid_width = 5, 1076 .parent_map = gcc_parent_map_0, 1077 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1078 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 1079 }; 1080 1081 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 1082 .name = "gcc_qupv3_wrap1_s4_clk_src", 1083 .parent_data = gcc_parent_data_1, 1084 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1085 .ops = &clk_rcg2_shared_ops, 1086 }; 1087 1088 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 1089 .cmd_rcgr = 0x24624, 1090 .mnd_width = 16, 1091 .hid_width = 5, 1092 .parent_map = gcc_parent_map_1, 1093 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1094 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 1095 }; 1096 1097 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 1098 .name = "gcc_qupv3_wrap1_s5_clk_src", 1099 .parent_data = gcc_parent_data_0, 1100 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1101 .ops = &clk_rcg2_shared_ops, 1102 }; 1103 1104 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 1105 .cmd_rcgr = 0x24758, 1106 .mnd_width = 16, 1107 .hid_width = 5, 1108 .parent_map = gcc_parent_map_0, 1109 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1110 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 1111 }; 1112 1113 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 1114 .name = "gcc_qupv3_wrap1_s6_clk_src", 1115 .parent_data = gcc_parent_data_0, 1116 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1117 .ops = &clk_rcg2_shared_ops, 1118 }; 1119 1120 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 1121 .cmd_rcgr = 0x2488c, 1122 .mnd_width = 16, 1123 .hid_width = 5, 1124 .parent_map = gcc_parent_map_0, 1125 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1126 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 1127 }; 1128 1129 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 1130 .name = "gcc_qupv3_wrap2_s0_clk_src", 1131 .parent_data = gcc_parent_data_1, 1132 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1133 .ops = &clk_rcg2_shared_ops, 1134 }; 1135 1136 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 1137 .cmd_rcgr = 0x2a154, 1138 .mnd_width = 16, 1139 .hid_width = 5, 1140 .parent_map = gcc_parent_map_1, 1141 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1142 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 1143 }; 1144 1145 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 1146 .name = "gcc_qupv3_wrap2_s1_clk_src", 1147 .parent_data = gcc_parent_data_1, 1148 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1149 .ops = &clk_rcg2_shared_ops, 1150 }; 1151 1152 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 1153 .cmd_rcgr = 0x2a288, 1154 .mnd_width = 16, 1155 .hid_width = 5, 1156 .parent_map = gcc_parent_map_1, 1157 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1158 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 1159 }; 1160 1161 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 1162 .name = "gcc_qupv3_wrap2_s2_clk_src", 1163 .parent_data = gcc_parent_data_1, 1164 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1165 .ops = &clk_rcg2_shared_ops, 1166 }; 1167 1168 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 1169 .cmd_rcgr = 0x2a3bc, 1170 .mnd_width = 16, 1171 .hid_width = 5, 1172 .parent_map = gcc_parent_map_1, 1173 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1174 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, 1175 }; 1176 1177 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 1178 .name = "gcc_qupv3_wrap2_s3_clk_src", 1179 .parent_data = gcc_parent_data_1, 1180 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1181 .ops = &clk_rcg2_shared_ops, 1182 }; 1183 1184 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 1185 .cmd_rcgr = 0x2a4f0, 1186 .mnd_width = 16, 1187 .hid_width = 5, 1188 .parent_map = gcc_parent_map_1, 1189 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1190 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, 1191 }; 1192 1193 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 1194 .name = "gcc_qupv3_wrap2_s4_clk_src", 1195 .parent_data = gcc_parent_data_1, 1196 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1197 .ops = &clk_rcg2_shared_ops, 1198 }; 1199 1200 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 1201 .cmd_rcgr = 0x2a624, 1202 .mnd_width = 16, 1203 .hid_width = 5, 1204 .parent_map = gcc_parent_map_1, 1205 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1206 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 1207 }; 1208 1209 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { 1210 .name = "gcc_qupv3_wrap2_s5_clk_src", 1211 .parent_data = gcc_parent_data_1, 1212 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1213 .ops = &clk_rcg2_shared_ops, 1214 }; 1215 1216 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { 1217 .cmd_rcgr = 0x2a758, 1218 .mnd_width = 16, 1219 .hid_width = 5, 1220 .parent_map = gcc_parent_map_1, 1221 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1222 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, 1223 }; 1224 1225 static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = { 1226 .name = "gcc_qupv3_wrap2_s6_clk_src", 1227 .parent_data = gcc_parent_data_1, 1228 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1229 .ops = &clk_rcg2_shared_ops, 1230 }; 1231 1232 static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { 1233 .cmd_rcgr = 0x2a88c, 1234 .mnd_width = 16, 1235 .hid_width = 5, 1236 .parent_map = gcc_parent_map_1, 1237 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1238 .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init, 1239 }; 1240 1241 static const struct freq_tbl ftbl_gcc_qupv3_wrap3_s0_clk_src[] = { 1242 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 1243 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 1244 F(19200000, P_BI_TCXO, 1, 0, 0), 1245 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 1246 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 1247 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 1248 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 1249 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1250 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 1251 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 1252 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 1253 F(403200000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 1254 { } 1255 }; 1256 1257 static struct clk_init_data gcc_qupv3_wrap3_s0_clk_src_init = { 1258 .name = "gcc_qupv3_wrap3_s0_clk_src", 1259 .parent_data = gcc_parent_data_4, 1260 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1261 .ops = &clk_rcg2_shared_ops, 1262 }; 1263 1264 static struct clk_rcg2 gcc_qupv3_wrap3_s0_clk_src = { 1265 .cmd_rcgr = 0xc4154, 1266 .mnd_width = 16, 1267 .hid_width = 5, 1268 .parent_map = gcc_parent_map_4, 1269 .freq_tbl = ftbl_gcc_qupv3_wrap3_s0_clk_src, 1270 .clkr.hw.init = &gcc_qupv3_wrap3_s0_clk_src_init, 1271 }; 1272 1273 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 1274 F(144000, P_BI_TCXO, 16, 3, 25), 1275 F(400000, P_BI_TCXO, 12, 1, 4), 1276 F(19200000, P_BI_TCXO, 1, 0, 0), 1277 F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3), 1278 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1279 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 1280 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1281 F(192000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), 1282 F(384000000, P_GCC_GPLL9_OUT_MAIN, 2, 0, 0), 1283 { } 1284 }; 1285 1286 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 1287 .cmd_rcgr = 0x20014, 1288 .mnd_width = 8, 1289 .hid_width = 5, 1290 .parent_map = gcc_parent_map_13, 1291 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 1292 .clkr.hw.init = &(const struct clk_init_data){ 1293 .name = "gcc_sdcc1_apps_clk_src", 1294 .parent_data = gcc_parent_data_13, 1295 .num_parents = ARRAY_SIZE(gcc_parent_data_13), 1296 .ops = &clk_rcg2_floor_ops, 1297 }, 1298 }; 1299 1300 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 1301 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 1302 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 1303 { } 1304 }; 1305 1306 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 1307 .cmd_rcgr = 0x2002c, 1308 .mnd_width = 0, 1309 .hid_width = 5, 1310 .parent_map = gcc_parent_map_14, 1311 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 1312 .clkr.hw.init = &(const struct clk_init_data){ 1313 .name = "gcc_sdcc1_ice_core_clk_src", 1314 .parent_data = gcc_parent_data_14, 1315 .num_parents = ARRAY_SIZE(gcc_parent_data_14), 1316 .ops = &clk_rcg2_floor_ops, 1317 }, 1318 }; 1319 1320 static const struct freq_tbl ftbl_gcc_tscss_cntr_clk_src[] = { 1321 F(15625000, P_GCC_GPLL7_OUT_MAIN, 16, 1, 4), 1322 { } 1323 }; 1324 1325 static struct clk_rcg2 gcc_tscss_cntr_clk_src = { 1326 .cmd_rcgr = 0x21008, 1327 .mnd_width = 16, 1328 .hid_width = 5, 1329 .parent_map = gcc_parent_map_15, 1330 .freq_tbl = ftbl_gcc_tscss_cntr_clk_src, 1331 .clkr.hw.init = &(const struct clk_init_data){ 1332 .name = "gcc_tscss_cntr_clk_src", 1333 .parent_data = gcc_parent_data_15, 1334 .num_parents = ARRAY_SIZE(gcc_parent_data_15), 1335 .ops = &clk_rcg2_shared_ops, 1336 }, 1337 }; 1338 1339 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { 1340 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1341 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1342 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 1343 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 1344 F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0), 1345 { } 1346 }; 1347 1348 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { 1349 .cmd_rcgr = 0x8102c, 1350 .mnd_width = 8, 1351 .hid_width = 5, 1352 .parent_map = gcc_parent_map_0, 1353 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, 1354 .clkr.hw.init = &(const struct clk_init_data){ 1355 .name = "gcc_ufs_card_axi_clk_src", 1356 .parent_data = gcc_parent_data_0, 1357 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1358 .ops = &clk_rcg2_shared_ops, 1359 }, 1360 }; 1361 1362 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { 1363 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1364 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 1365 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 1366 F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0), 1367 { } 1368 }; 1369 1370 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { 1371 .cmd_rcgr = 0x81074, 1372 .mnd_width = 0, 1373 .hid_width = 5, 1374 .parent_map = gcc_parent_map_0, 1375 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 1376 .clkr.hw.init = &(const struct clk_init_data){ 1377 .name = "gcc_ufs_card_ice_core_clk_src", 1378 .parent_data = gcc_parent_data_0, 1379 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1380 .ops = &clk_rcg2_shared_ops, 1381 }, 1382 }; 1383 1384 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { 1385 .cmd_rcgr = 0x810a8, 1386 .mnd_width = 0, 1387 .hid_width = 5, 1388 .parent_map = gcc_parent_map_5, 1389 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 1390 .clkr.hw.init = &(const struct clk_init_data){ 1391 .name = "gcc_ufs_card_phy_aux_clk_src", 1392 .parent_data = gcc_parent_data_5, 1393 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1394 .ops = &clk_rcg2_shared_ops, 1395 }, 1396 }; 1397 1398 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { 1399 .cmd_rcgr = 0x8108c, 1400 .mnd_width = 0, 1401 .hid_width = 5, 1402 .parent_map = gcc_parent_map_0, 1403 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 1404 .clkr.hw.init = &(const struct clk_init_data){ 1405 .name = "gcc_ufs_card_unipro_core_clk_src", 1406 .parent_data = gcc_parent_data_0, 1407 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1408 .ops = &clk_rcg2_shared_ops, 1409 }, 1410 }; 1411 1412 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1413 .cmd_rcgr = 0x8302c, 1414 .mnd_width = 8, 1415 .hid_width = 5, 1416 .parent_map = gcc_parent_map_0, 1417 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, 1418 .clkr.hw.init = &(const struct clk_init_data){ 1419 .name = "gcc_ufs_phy_axi_clk_src", 1420 .parent_data = gcc_parent_data_0, 1421 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1422 .ops = &clk_rcg2_shared_ops, 1423 }, 1424 }; 1425 1426 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1427 .cmd_rcgr = 0x83074, 1428 .mnd_width = 0, 1429 .hid_width = 5, 1430 .parent_map = gcc_parent_map_0, 1431 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 1432 .clkr.hw.init = &(const struct clk_init_data){ 1433 .name = "gcc_ufs_phy_ice_core_clk_src", 1434 .parent_data = gcc_parent_data_0, 1435 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1436 .ops = &clk_rcg2_shared_ops, 1437 }, 1438 }; 1439 1440 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1441 .cmd_rcgr = 0x830a8, 1442 .mnd_width = 0, 1443 .hid_width = 5, 1444 .parent_map = gcc_parent_map_5, 1445 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 1446 .clkr.hw.init = &(const struct clk_init_data){ 1447 .name = "gcc_ufs_phy_phy_aux_clk_src", 1448 .parent_data = gcc_parent_data_5, 1449 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1450 .ops = &clk_rcg2_shared_ops, 1451 }, 1452 }; 1453 1454 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1455 .cmd_rcgr = 0x8308c, 1456 .mnd_width = 0, 1457 .hid_width = 5, 1458 .parent_map = gcc_parent_map_0, 1459 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 1460 .clkr.hw.init = &(const struct clk_init_data){ 1461 .name = "gcc_ufs_phy_unipro_core_clk_src", 1462 .parent_data = gcc_parent_data_0, 1463 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1464 .ops = &clk_rcg2_shared_ops, 1465 }, 1466 }; 1467 1468 static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = { 1469 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 1470 { } 1471 }; 1472 1473 static struct clk_rcg2 gcc_usb20_master_clk_src = { 1474 .cmd_rcgr = 0x1c028, 1475 .mnd_width = 8, 1476 .hid_width = 5, 1477 .parent_map = gcc_parent_map_0, 1478 .freq_tbl = ftbl_gcc_usb20_master_clk_src, 1479 .clkr.hw.init = &(const struct clk_init_data){ 1480 .name = "gcc_usb20_master_clk_src", 1481 .parent_data = gcc_parent_data_0, 1482 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1483 .ops = &clk_rcg2_shared_ops, 1484 }, 1485 }; 1486 1487 static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = { 1488 .cmd_rcgr = 0x1c040, 1489 .mnd_width = 0, 1490 .hid_width = 5, 1491 .parent_map = gcc_parent_map_0, 1492 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 1493 .clkr.hw.init = &(const struct clk_init_data){ 1494 .name = "gcc_usb20_mock_utmi_clk_src", 1495 .parent_data = gcc_parent_data_0, 1496 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1497 .ops = &clk_rcg2_shared_ops, 1498 }, 1499 }; 1500 1501 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1502 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 1503 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1504 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 1505 { } 1506 }; 1507 1508 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1509 .cmd_rcgr = 0x1b028, 1510 .mnd_width = 8, 1511 .hid_width = 5, 1512 .parent_map = gcc_parent_map_0, 1513 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1514 .clkr.hw.init = &(const struct clk_init_data){ 1515 .name = "gcc_usb30_prim_master_clk_src", 1516 .parent_data = gcc_parent_data_0, 1517 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1518 .ops = &clk_rcg2_shared_ops, 1519 }, 1520 }; 1521 1522 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1523 .cmd_rcgr = 0x1b040, 1524 .mnd_width = 0, 1525 .hid_width = 5, 1526 .parent_map = gcc_parent_map_0, 1527 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 1528 .clkr.hw.init = &(const struct clk_init_data){ 1529 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1530 .parent_data = gcc_parent_data_0, 1531 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1532 .ops = &clk_rcg2_shared_ops, 1533 }, 1534 }; 1535 1536 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { 1537 .cmd_rcgr = 0x2f028, 1538 .mnd_width = 8, 1539 .hid_width = 5, 1540 .parent_map = gcc_parent_map_0, 1541 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1542 .clkr.hw.init = &(const struct clk_init_data){ 1543 .name = "gcc_usb30_sec_master_clk_src", 1544 .parent_data = gcc_parent_data_0, 1545 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1546 .ops = &clk_rcg2_shared_ops, 1547 }, 1548 }; 1549 1550 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { 1551 .cmd_rcgr = 0x2f040, 1552 .mnd_width = 0, 1553 .hid_width = 5, 1554 .parent_map = gcc_parent_map_0, 1555 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 1556 .clkr.hw.init = &(const struct clk_init_data){ 1557 .name = "gcc_usb30_sec_mock_utmi_clk_src", 1558 .parent_data = gcc_parent_data_0, 1559 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1560 .ops = &clk_rcg2_shared_ops, 1561 }, 1562 }; 1563 1564 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1565 .cmd_rcgr = 0x1b06c, 1566 .mnd_width = 0, 1567 .hid_width = 5, 1568 .parent_map = gcc_parent_map_3, 1569 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 1570 .clkr.hw.init = &(const struct clk_init_data){ 1571 .name = "gcc_usb3_prim_phy_aux_clk_src", 1572 .parent_data = gcc_parent_data_3, 1573 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1574 .ops = &clk_rcg2_shared_ops, 1575 }, 1576 }; 1577 1578 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { 1579 .cmd_rcgr = 0x2f06c, 1580 .mnd_width = 0, 1581 .hid_width = 5, 1582 .parent_map = gcc_parent_map_3, 1583 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 1584 .clkr.hw.init = &(const struct clk_init_data){ 1585 .name = "gcc_usb3_sec_phy_aux_clk_src", 1586 .parent_data = gcc_parent_data_3, 1587 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1588 .ops = &clk_rcg2_shared_ops, 1589 }, 1590 }; 1591 1592 static struct clk_regmap_div gcc_pcie_0_pipe_div_clk_src = { 1593 .reg = 0xa9070, 1594 .shift = 0, 1595 .width = 4, 1596 .clkr.hw.init = &(const struct clk_init_data) { 1597 .name = "gcc_pcie_0_pipe_div_clk_src", 1598 .parent_hws = (const struct clk_hw*[]){ 1599 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1600 }, 1601 .num_parents = 1, 1602 .flags = CLK_SET_RATE_PARENT, 1603 .ops = &clk_regmap_div_ro_ops, 1604 }, 1605 }; 1606 1607 static struct clk_regmap_div gcc_pcie_1_pipe_div_clk_src = { 1608 .reg = 0x77070, 1609 .shift = 0, 1610 .width = 4, 1611 .clkr.hw.init = &(const struct clk_init_data) { 1612 .name = "gcc_pcie_1_pipe_div_clk_src", 1613 .parent_hws = (const struct clk_hw*[]){ 1614 &gcc_pcie_1_pipe_clk_src.clkr.hw, 1615 }, 1616 .num_parents = 1, 1617 .flags = CLK_SET_RATE_PARENT, 1618 .ops = &clk_regmap_div_ro_ops, 1619 }, 1620 }; 1621 1622 static struct clk_regmap_div gcc_qupv3_wrap3_s0_div_clk_src = { 1623 .reg = 0xc4284, 1624 .shift = 0, 1625 .width = 4, 1626 .clkr.hw.init = &(const struct clk_init_data) { 1627 .name = "gcc_qupv3_wrap3_s0_div_clk_src", 1628 .parent_hws = (const struct clk_hw*[]){ 1629 &gcc_qupv3_wrap3_s0_clk_src.clkr.hw, 1630 }, 1631 .num_parents = 1, 1632 .flags = CLK_SET_RATE_PARENT, 1633 .ops = &clk_regmap_div_ro_ops, 1634 }, 1635 }; 1636 1637 static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src = { 1638 .reg = 0x1c058, 1639 .shift = 0, 1640 .width = 4, 1641 .clkr.hw.init = &(const struct clk_init_data) { 1642 .name = "gcc_usb20_mock_utmi_postdiv_clk_src", 1643 .parent_hws = (const struct clk_hw*[]){ 1644 &gcc_usb20_mock_utmi_clk_src.clkr.hw, 1645 }, 1646 .num_parents = 1, 1647 .flags = CLK_SET_RATE_PARENT, 1648 .ops = &clk_regmap_div_ro_ops, 1649 }, 1650 }; 1651 1652 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1653 .reg = 0x1b058, 1654 .shift = 0, 1655 .width = 4, 1656 .clkr.hw.init = &(const struct clk_init_data) { 1657 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1658 .parent_hws = (const struct clk_hw*[]){ 1659 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1660 }, 1661 .num_parents = 1, 1662 .flags = CLK_SET_RATE_PARENT, 1663 .ops = &clk_regmap_div_ro_ops, 1664 }, 1665 }; 1666 1667 static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = { 1668 .reg = 0x2f058, 1669 .shift = 0, 1670 .width = 4, 1671 .clkr.hw.init = &(const struct clk_init_data) { 1672 .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src", 1673 .parent_hws = (const struct clk_hw*[]){ 1674 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, 1675 }, 1676 .num_parents = 1, 1677 .flags = CLK_SET_RATE_PARENT, 1678 .ops = &clk_regmap_div_ro_ops, 1679 }, 1680 }; 1681 1682 static struct clk_branch gcc_aggre_noc_qupv3_axi_clk = { 1683 .halt_reg = 0x8e200, 1684 .halt_check = BRANCH_HALT_VOTED, 1685 .hwcg_reg = 0x8e200, 1686 .hwcg_bit = 1, 1687 .clkr = { 1688 .enable_reg = 0x4b000, 1689 .enable_mask = BIT(28), 1690 .hw.init = &(const struct clk_init_data){ 1691 .name = "gcc_aggre_noc_qupv3_axi_clk", 1692 .ops = &clk_branch2_ops, 1693 }, 1694 }, 1695 }; 1696 1697 static struct clk_branch gcc_aggre_ufs_card_axi_clk = { 1698 .halt_reg = 0x810d4, 1699 .halt_check = BRANCH_HALT_VOTED, 1700 .hwcg_reg = 0x810d4, 1701 .hwcg_bit = 1, 1702 .clkr = { 1703 .enable_reg = 0x810d4, 1704 .enable_mask = BIT(0), 1705 .hw.init = &(const struct clk_init_data){ 1706 .name = "gcc_aggre_ufs_card_axi_clk", 1707 .parent_hws = (const struct clk_hw*[]){ 1708 &gcc_ufs_card_axi_clk_src.clkr.hw, 1709 }, 1710 .num_parents = 1, 1711 .flags = CLK_SET_RATE_PARENT, 1712 .ops = &clk_branch2_ops, 1713 }, 1714 }, 1715 }; 1716 1717 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1718 .halt_reg = 0x830d4, 1719 .halt_check = BRANCH_HALT_VOTED, 1720 .hwcg_reg = 0x830d4, 1721 .hwcg_bit = 1, 1722 .clkr = { 1723 .enable_reg = 0x830d4, 1724 .enable_mask = BIT(0), 1725 .hw.init = &(const struct clk_init_data){ 1726 .name = "gcc_aggre_ufs_phy_axi_clk", 1727 .parent_hws = (const struct clk_hw*[]){ 1728 &gcc_ufs_phy_axi_clk_src.clkr.hw, 1729 }, 1730 .num_parents = 1, 1731 .flags = CLK_SET_RATE_PARENT, 1732 .ops = &clk_branch2_ops, 1733 }, 1734 }, 1735 }; 1736 1737 static struct clk_branch gcc_aggre_usb2_prim_axi_clk = { 1738 .halt_reg = 0x1c05c, 1739 .halt_check = BRANCH_HALT_VOTED, 1740 .hwcg_reg = 0x1c05c, 1741 .hwcg_bit = 1, 1742 .clkr = { 1743 .enable_reg = 0x1c05c, 1744 .enable_mask = BIT(0), 1745 .hw.init = &(const struct clk_init_data){ 1746 .name = "gcc_aggre_usb2_prim_axi_clk", 1747 .parent_hws = (const struct clk_hw*[]){ 1748 &gcc_usb20_master_clk_src.clkr.hw, 1749 }, 1750 .num_parents = 1, 1751 .flags = CLK_SET_RATE_PARENT, 1752 .ops = &clk_branch2_ops, 1753 }, 1754 }, 1755 }; 1756 1757 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1758 .halt_reg = 0x1b084, 1759 .halt_check = BRANCH_HALT_VOTED, 1760 .hwcg_reg = 0x1b084, 1761 .hwcg_bit = 1, 1762 .clkr = { 1763 .enable_reg = 0x1b084, 1764 .enable_mask = BIT(0), 1765 .hw.init = &(const struct clk_init_data){ 1766 .name = "gcc_aggre_usb3_prim_axi_clk", 1767 .parent_hws = (const struct clk_hw*[]){ 1768 &gcc_usb30_prim_master_clk_src.clkr.hw, 1769 }, 1770 .num_parents = 1, 1771 .flags = CLK_SET_RATE_PARENT, 1772 .ops = &clk_branch2_ops, 1773 }, 1774 }, 1775 }; 1776 1777 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { 1778 .halt_reg = 0x2f088, 1779 .halt_check = BRANCH_HALT_VOTED, 1780 .hwcg_reg = 0x2f088, 1781 .hwcg_bit = 1, 1782 .clkr = { 1783 .enable_reg = 0x2f088, 1784 .enable_mask = BIT(0), 1785 .hw.init = &(const struct clk_init_data){ 1786 .name = "gcc_aggre_usb3_sec_axi_clk", 1787 .parent_hws = (const struct clk_hw*[]){ 1788 &gcc_usb30_sec_master_clk_src.clkr.hw, 1789 }, 1790 .num_parents = 1, 1791 .flags = CLK_SET_RATE_PARENT, 1792 .ops = &clk_branch2_ops, 1793 }, 1794 }, 1795 }; 1796 1797 static struct clk_branch gcc_ahb2phy0_clk = { 1798 .halt_reg = 0x76004, 1799 .halt_check = BRANCH_HALT_VOTED, 1800 .hwcg_reg = 0x76004, 1801 .hwcg_bit = 1, 1802 .clkr = { 1803 .enable_reg = 0x76004, 1804 .enable_mask = BIT(0), 1805 .hw.init = &(const struct clk_init_data){ 1806 .name = "gcc_ahb2phy0_clk", 1807 .ops = &clk_branch2_ops, 1808 }, 1809 }, 1810 }; 1811 1812 static struct clk_branch gcc_ahb2phy2_clk = { 1813 .halt_reg = 0x76008, 1814 .halt_check = BRANCH_HALT_VOTED, 1815 .hwcg_reg = 0x76008, 1816 .hwcg_bit = 1, 1817 .clkr = { 1818 .enable_reg = 0x76008, 1819 .enable_mask = BIT(0), 1820 .hw.init = &(const struct clk_init_data){ 1821 .name = "gcc_ahb2phy2_clk", 1822 .ops = &clk_branch2_ops, 1823 }, 1824 }, 1825 }; 1826 1827 static struct clk_branch gcc_ahb2phy3_clk = { 1828 .halt_reg = 0x7600c, 1829 .halt_check = BRANCH_HALT_VOTED, 1830 .hwcg_reg = 0x7600c, 1831 .hwcg_bit = 1, 1832 .clkr = { 1833 .enable_reg = 0x7600c, 1834 .enable_mask = BIT(0), 1835 .hw.init = &(const struct clk_init_data){ 1836 .name = "gcc_ahb2phy3_clk", 1837 .ops = &clk_branch2_ops, 1838 }, 1839 }, 1840 }; 1841 1842 static struct clk_branch gcc_boot_rom_ahb_clk = { 1843 .halt_reg = 0x44004, 1844 .halt_check = BRANCH_HALT_VOTED, 1845 .hwcg_reg = 0x44004, 1846 .hwcg_bit = 1, 1847 .clkr = { 1848 .enable_reg = 0x4b000, 1849 .enable_mask = BIT(10), 1850 .hw.init = &(const struct clk_init_data){ 1851 .name = "gcc_boot_rom_ahb_clk", 1852 .ops = &clk_branch2_ops, 1853 }, 1854 }, 1855 }; 1856 1857 static struct clk_branch gcc_camera_hf_axi_clk = { 1858 .halt_reg = 0x32010, 1859 .halt_check = BRANCH_HALT_SKIP, 1860 .hwcg_reg = 0x32010, 1861 .hwcg_bit = 1, 1862 .clkr = { 1863 .enable_reg = 0x32010, 1864 .enable_mask = BIT(0), 1865 .hw.init = &(const struct clk_init_data){ 1866 .name = "gcc_camera_hf_axi_clk", 1867 .ops = &clk_branch2_ops, 1868 }, 1869 }, 1870 }; 1871 1872 static struct clk_branch gcc_camera_sf_axi_clk = { 1873 .halt_reg = 0x32018, 1874 .halt_check = BRANCH_HALT_SKIP, 1875 .hwcg_reg = 0x32018, 1876 .hwcg_bit = 1, 1877 .clkr = { 1878 .enable_reg = 0x32018, 1879 .enable_mask = BIT(0), 1880 .hw.init = &(const struct clk_init_data){ 1881 .name = "gcc_camera_sf_axi_clk", 1882 .ops = &clk_branch2_ops, 1883 }, 1884 }, 1885 }; 1886 1887 static struct clk_branch gcc_camera_throttle_xo_clk = { 1888 .halt_reg = 0x32024, 1889 .halt_check = BRANCH_HALT, 1890 .clkr = { 1891 .enable_reg = 0x32024, 1892 .enable_mask = BIT(0), 1893 .hw.init = &(const struct clk_init_data){ 1894 .name = "gcc_camera_throttle_xo_clk", 1895 .ops = &clk_branch2_ops, 1896 }, 1897 }, 1898 }; 1899 1900 static struct clk_branch gcc_cfg_noc_usb2_prim_axi_clk = { 1901 .halt_reg = 0x1c060, 1902 .halt_check = BRANCH_HALT_VOTED, 1903 .hwcg_reg = 0x1c060, 1904 .hwcg_bit = 1, 1905 .clkr = { 1906 .enable_reg = 0x1c060, 1907 .enable_mask = BIT(0), 1908 .hw.init = &(const struct clk_init_data){ 1909 .name = "gcc_cfg_noc_usb2_prim_axi_clk", 1910 .parent_hws = (const struct clk_hw*[]){ 1911 &gcc_usb20_master_clk_src.clkr.hw, 1912 }, 1913 .num_parents = 1, 1914 .flags = CLK_SET_RATE_PARENT, 1915 .ops = &clk_branch2_ops, 1916 }, 1917 }, 1918 }; 1919 1920 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1921 .halt_reg = 0x1b088, 1922 .halt_check = BRANCH_HALT_VOTED, 1923 .hwcg_reg = 0x1b088, 1924 .hwcg_bit = 1, 1925 .clkr = { 1926 .enable_reg = 0x1b088, 1927 .enable_mask = BIT(0), 1928 .hw.init = &(const struct clk_init_data){ 1929 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1930 .parent_hws = (const struct clk_hw*[]){ 1931 &gcc_usb30_prim_master_clk_src.clkr.hw, 1932 }, 1933 .num_parents = 1, 1934 .flags = CLK_SET_RATE_PARENT, 1935 .ops = &clk_branch2_ops, 1936 }, 1937 }, 1938 }; 1939 1940 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { 1941 .halt_reg = 0x2f084, 1942 .halt_check = BRANCH_HALT_VOTED, 1943 .hwcg_reg = 0x2f084, 1944 .hwcg_bit = 1, 1945 .clkr = { 1946 .enable_reg = 0x2f084, 1947 .enable_mask = BIT(0), 1948 .hw.init = &(const struct clk_init_data){ 1949 .name = "gcc_cfg_noc_usb3_sec_axi_clk", 1950 .parent_hws = (const struct clk_hw*[]){ 1951 &gcc_usb30_sec_master_clk_src.clkr.hw, 1952 }, 1953 .num_parents = 1, 1954 .flags = CLK_SET_RATE_PARENT, 1955 .ops = &clk_branch2_ops, 1956 }, 1957 }, 1958 }; 1959 1960 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1961 .halt_reg = 0x7d164, 1962 .halt_check = BRANCH_HALT_VOTED, 1963 .hwcg_reg = 0x7d164, 1964 .hwcg_bit = 1, 1965 .clkr = { 1966 .enable_reg = 0x7d164, 1967 .enable_mask = BIT(0), 1968 .hw.init = &(const struct clk_init_data){ 1969 .name = "gcc_ddrss_gpu_axi_clk", 1970 .ops = &clk_branch2_aon_ops, 1971 }, 1972 }, 1973 }; 1974 1975 static struct clk_branch gcc_disp1_hf_axi_clk = { 1976 .halt_reg = 0xc7010, 1977 .halt_check = BRANCH_HALT_VOTED, 1978 .hwcg_reg = 0xc7010, 1979 .hwcg_bit = 1, 1980 .clkr = { 1981 .enable_reg = 0xc7010, 1982 .enable_mask = BIT(0), 1983 .hw.init = &(const struct clk_init_data){ 1984 .name = "gcc_disp1_hf_axi_clk", 1985 .ops = &clk_branch2_ops, 1986 }, 1987 }, 1988 }; 1989 1990 static struct clk_branch gcc_disp_hf_axi_clk = { 1991 .halt_reg = 0x33010, 1992 .halt_check = BRANCH_HALT_VOTED, 1993 .hwcg_reg = 0x33010, 1994 .hwcg_bit = 1, 1995 .clkr = { 1996 .enable_reg = 0x33010, 1997 .enable_mask = BIT(0), 1998 .hw.init = &(const struct clk_init_data){ 1999 .name = "gcc_disp_hf_axi_clk", 2000 .ops = &clk_branch2_ops, 2001 }, 2002 }, 2003 }; 2004 2005 static struct clk_branch gcc_edp_ref_clkref_en = { 2006 .halt_reg = 0x97448, 2007 .halt_check = BRANCH_HALT_DELAY, 2008 .clkr = { 2009 .enable_reg = 0x97448, 2010 .enable_mask = BIT(0), 2011 .hw.init = &(const struct clk_init_data){ 2012 .name = "gcc_edp_ref_clkref_en", 2013 .ops = &clk_branch2_ops, 2014 }, 2015 }, 2016 }; 2017 2018 static struct clk_branch gcc_emac0_axi_clk = { 2019 .halt_reg = 0xb6018, 2020 .halt_check = BRANCH_HALT_VOTED, 2021 .hwcg_reg = 0xb6018, 2022 .hwcg_bit = 1, 2023 .clkr = { 2024 .enable_reg = 0xb6018, 2025 .enable_mask = BIT(0), 2026 .hw.init = &(const struct clk_init_data){ 2027 .name = "gcc_emac0_axi_clk", 2028 .ops = &clk_branch2_ops, 2029 }, 2030 }, 2031 }; 2032 2033 static struct clk_branch gcc_emac0_phy_aux_clk = { 2034 .halt_reg = 0xb6024, 2035 .halt_check = BRANCH_HALT, 2036 .clkr = { 2037 .enable_reg = 0xb6024, 2038 .enable_mask = BIT(0), 2039 .hw.init = &(const struct clk_init_data){ 2040 .name = "gcc_emac0_phy_aux_clk", 2041 .parent_hws = (const struct clk_hw*[]){ 2042 &gcc_emac0_phy_aux_clk_src.clkr.hw, 2043 }, 2044 .num_parents = 1, 2045 .flags = CLK_SET_RATE_PARENT, 2046 .ops = &clk_branch2_ops, 2047 }, 2048 }, 2049 }; 2050 2051 static struct clk_branch gcc_emac0_ptp_clk = { 2052 .halt_reg = 0xb6040, 2053 .halt_check = BRANCH_HALT, 2054 .clkr = { 2055 .enable_reg = 0xb6040, 2056 .enable_mask = BIT(0), 2057 .hw.init = &(const struct clk_init_data){ 2058 .name = "gcc_emac0_ptp_clk", 2059 .parent_hws = (const struct clk_hw*[]){ 2060 &gcc_emac0_ptp_clk_src.clkr.hw, 2061 }, 2062 .num_parents = 1, 2063 .flags = CLK_SET_RATE_PARENT, 2064 .ops = &clk_branch2_ops, 2065 }, 2066 }, 2067 }; 2068 2069 static struct clk_branch gcc_emac0_rgmii_clk = { 2070 .halt_reg = 0xb6044, 2071 .halt_check = BRANCH_HALT, 2072 .clkr = { 2073 .enable_reg = 0xb6044, 2074 .enable_mask = BIT(0), 2075 .hw.init = &(const struct clk_init_data){ 2076 .name = "gcc_emac0_rgmii_clk", 2077 .parent_hws = (const struct clk_hw*[]){ 2078 &gcc_emac0_rgmii_clk_src.clkr.hw, 2079 }, 2080 .num_parents = 1, 2081 .flags = CLK_SET_RATE_PARENT, 2082 .ops = &clk_branch2_ops, 2083 }, 2084 }, 2085 }; 2086 2087 static struct clk_branch gcc_emac0_slv_ahb_clk = { 2088 .halt_reg = 0xb6020, 2089 .halt_check = BRANCH_HALT_VOTED, 2090 .hwcg_reg = 0xb6020, 2091 .hwcg_bit = 1, 2092 .clkr = { 2093 .enable_reg = 0xb6020, 2094 .enable_mask = BIT(0), 2095 .hw.init = &(const struct clk_init_data){ 2096 .name = "gcc_emac0_slv_ahb_clk", 2097 .ops = &clk_branch2_ops, 2098 }, 2099 }, 2100 }; 2101 2102 static struct clk_branch gcc_emac1_axi_clk = { 2103 .halt_reg = 0xb4018, 2104 .halt_check = BRANCH_HALT_VOTED, 2105 .hwcg_reg = 0xb4018, 2106 .hwcg_bit = 1, 2107 .clkr = { 2108 .enable_reg = 0xb4018, 2109 .enable_mask = BIT(0), 2110 .hw.init = &(const struct clk_init_data){ 2111 .name = "gcc_emac1_axi_clk", 2112 .ops = &clk_branch2_ops, 2113 }, 2114 }, 2115 }; 2116 2117 static struct clk_branch gcc_emac1_phy_aux_clk = { 2118 .halt_reg = 0xb4024, 2119 .halt_check = BRANCH_HALT, 2120 .clkr = { 2121 .enable_reg = 0xb4024, 2122 .enable_mask = BIT(0), 2123 .hw.init = &(const struct clk_init_data){ 2124 .name = "gcc_emac1_phy_aux_clk", 2125 .parent_hws = (const struct clk_hw*[]){ 2126 &gcc_emac1_phy_aux_clk_src.clkr.hw, 2127 }, 2128 .num_parents = 1, 2129 .flags = CLK_SET_RATE_PARENT, 2130 .ops = &clk_branch2_ops, 2131 }, 2132 }, 2133 }; 2134 2135 static struct clk_branch gcc_emac1_ptp_clk = { 2136 .halt_reg = 0xb4040, 2137 .halt_check = BRANCH_HALT, 2138 .clkr = { 2139 .enable_reg = 0xb4040, 2140 .enable_mask = BIT(0), 2141 .hw.init = &(const struct clk_init_data){ 2142 .name = "gcc_emac1_ptp_clk", 2143 .parent_hws = (const struct clk_hw*[]){ 2144 &gcc_emac1_ptp_clk_src.clkr.hw, 2145 }, 2146 .num_parents = 1, 2147 .flags = CLK_SET_RATE_PARENT, 2148 .ops = &clk_branch2_ops, 2149 }, 2150 }, 2151 }; 2152 2153 static struct clk_branch gcc_emac1_rgmii_clk = { 2154 .halt_reg = 0xb4044, 2155 .halt_check = BRANCH_HALT, 2156 .clkr = { 2157 .enable_reg = 0xb4044, 2158 .enable_mask = BIT(0), 2159 .hw.init = &(const struct clk_init_data){ 2160 .name = "gcc_emac1_rgmii_clk", 2161 .parent_hws = (const struct clk_hw*[]){ 2162 &gcc_emac1_rgmii_clk_src.clkr.hw, 2163 }, 2164 .num_parents = 1, 2165 .flags = CLK_SET_RATE_PARENT, 2166 .ops = &clk_branch2_ops, 2167 }, 2168 }, 2169 }; 2170 2171 static struct clk_branch gcc_emac1_slv_ahb_clk = { 2172 .halt_reg = 0xb4020, 2173 .halt_check = BRANCH_HALT_VOTED, 2174 .hwcg_reg = 0xb4020, 2175 .hwcg_bit = 1, 2176 .clkr = { 2177 .enable_reg = 0xb4020, 2178 .enable_mask = BIT(0), 2179 .hw.init = &(const struct clk_init_data){ 2180 .name = "gcc_emac1_slv_ahb_clk", 2181 .ops = &clk_branch2_ops, 2182 }, 2183 }, 2184 }; 2185 2186 static struct clk_branch gcc_gp1_clk = { 2187 .halt_reg = 0x70000, 2188 .halt_check = BRANCH_HALT, 2189 .clkr = { 2190 .enable_reg = 0x70000, 2191 .enable_mask = BIT(0), 2192 .hw.init = &(const struct clk_init_data){ 2193 .name = "gcc_gp1_clk", 2194 .parent_hws = (const struct clk_hw*[]){ 2195 &gcc_gp1_clk_src.clkr.hw, 2196 }, 2197 .num_parents = 1, 2198 .flags = CLK_SET_RATE_PARENT, 2199 .ops = &clk_branch2_ops, 2200 }, 2201 }, 2202 }; 2203 2204 static struct clk_branch gcc_gp2_clk = { 2205 .halt_reg = 0x71000, 2206 .halt_check = BRANCH_HALT, 2207 .clkr = { 2208 .enable_reg = 0x71000, 2209 .enable_mask = BIT(0), 2210 .hw.init = &(const struct clk_init_data){ 2211 .name = "gcc_gp2_clk", 2212 .parent_hws = (const struct clk_hw*[]){ 2213 &gcc_gp2_clk_src.clkr.hw, 2214 }, 2215 .num_parents = 1, 2216 .flags = CLK_SET_RATE_PARENT, 2217 .ops = &clk_branch2_ops, 2218 }, 2219 }, 2220 }; 2221 2222 static struct clk_branch gcc_gp3_clk = { 2223 .halt_reg = 0x62000, 2224 .halt_check = BRANCH_HALT, 2225 .clkr = { 2226 .enable_reg = 0x62000, 2227 .enable_mask = BIT(0), 2228 .hw.init = &(const struct clk_init_data){ 2229 .name = "gcc_gp3_clk", 2230 .parent_hws = (const struct clk_hw*[]){ 2231 &gcc_gp3_clk_src.clkr.hw, 2232 }, 2233 .num_parents = 1, 2234 .flags = CLK_SET_RATE_PARENT, 2235 .ops = &clk_branch2_ops, 2236 }, 2237 }, 2238 }; 2239 2240 static struct clk_branch gcc_gp4_clk = { 2241 .halt_reg = 0x1e000, 2242 .halt_check = BRANCH_HALT, 2243 .clkr = { 2244 .enable_reg = 0x1e000, 2245 .enable_mask = BIT(0), 2246 .hw.init = &(const struct clk_init_data){ 2247 .name = "gcc_gp4_clk", 2248 .parent_hws = (const struct clk_hw*[]){ 2249 &gcc_gp4_clk_src.clkr.hw, 2250 }, 2251 .num_parents = 1, 2252 .flags = CLK_SET_RATE_PARENT, 2253 .ops = &clk_branch2_ops, 2254 }, 2255 }, 2256 }; 2257 2258 static struct clk_branch gcc_gp5_clk = { 2259 .halt_reg = 0x1f000, 2260 .halt_check = BRANCH_HALT, 2261 .clkr = { 2262 .enable_reg = 0x1f000, 2263 .enable_mask = BIT(0), 2264 .hw.init = &(const struct clk_init_data){ 2265 .name = "gcc_gp5_clk", 2266 .parent_hws = (const struct clk_hw*[]){ 2267 &gcc_gp5_clk_src.clkr.hw, 2268 }, 2269 .num_parents = 1, 2270 .flags = CLK_SET_RATE_PARENT, 2271 .ops = &clk_branch2_ops, 2272 }, 2273 }, 2274 }; 2275 2276 static struct clk_branch gcc_gpu_gpll0_clk_src = { 2277 .halt_check = BRANCH_HALT_DELAY, 2278 .clkr = { 2279 .enable_reg = 0x4b000, 2280 .enable_mask = BIT(15), 2281 .hw.init = &(const struct clk_init_data){ 2282 .name = "gcc_gpu_gpll0_clk_src", 2283 .parent_hws = (const struct clk_hw*[]){ 2284 &gcc_gpll0.clkr.hw, 2285 }, 2286 .num_parents = 1, 2287 .flags = CLK_SET_RATE_PARENT, 2288 .ops = &clk_branch2_ops, 2289 }, 2290 }, 2291 }; 2292 2293 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 2294 .halt_check = BRANCH_HALT_DELAY, 2295 .clkr = { 2296 .enable_reg = 0x4b000, 2297 .enable_mask = BIT(16), 2298 .hw.init = &(const struct clk_init_data){ 2299 .name = "gcc_gpu_gpll0_div_clk_src", 2300 .parent_hws = (const struct clk_hw*[]){ 2301 &gcc_gpll0_out_even.clkr.hw, 2302 }, 2303 .num_parents = 1, 2304 .flags = CLK_SET_RATE_PARENT, 2305 .ops = &clk_branch2_ops, 2306 }, 2307 }, 2308 }; 2309 2310 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 2311 .halt_reg = 0x7d010, 2312 .halt_check = BRANCH_HALT_VOTED, 2313 .hwcg_reg = 0x7d010, 2314 .hwcg_bit = 1, 2315 .clkr = { 2316 .enable_reg = 0x7d010, 2317 .enable_mask = BIT(0), 2318 .hw.init = &(const struct clk_init_data){ 2319 .name = "gcc_gpu_memnoc_gfx_clk", 2320 .ops = &clk_branch2_aon_ops, 2321 }, 2322 }, 2323 }; 2324 2325 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 2326 .halt_reg = 0x7d01c, 2327 .halt_check = BRANCH_HALT_DELAY, 2328 .clkr = { 2329 .enable_reg = 0x7d01c, 2330 .enable_mask = BIT(0), 2331 .hw.init = &(const struct clk_init_data){ 2332 .name = "gcc_gpu_snoc_dvm_gfx_clk", 2333 .ops = &clk_branch2_aon_ops, 2334 }, 2335 }, 2336 }; 2337 2338 static struct clk_branch gcc_gpu_tcu_throttle_ahb_clk = { 2339 .halt_reg = 0x7d008, 2340 .halt_check = BRANCH_HALT_VOTED, 2341 .hwcg_reg = 0x7d008, 2342 .hwcg_bit = 1, 2343 .clkr = { 2344 .enable_reg = 0x7d008, 2345 .enable_mask = BIT(0), 2346 .hw.init = &(const struct clk_init_data){ 2347 .name = "gcc_gpu_tcu_throttle_ahb_clk", 2348 .ops = &clk_branch2_ops, 2349 }, 2350 }, 2351 }; 2352 2353 static struct clk_branch gcc_gpu_tcu_throttle_clk = { 2354 .halt_reg = 0x7d014, 2355 .halt_check = BRANCH_HALT_VOTED, 2356 .hwcg_reg = 0x7d014, 2357 .hwcg_bit = 1, 2358 .clkr = { 2359 .enable_reg = 0x7d014, 2360 .enable_mask = BIT(0), 2361 .hw.init = &(const struct clk_init_data){ 2362 .name = "gcc_gpu_tcu_throttle_clk", 2363 .ops = &clk_branch2_ops, 2364 }, 2365 }, 2366 }; 2367 2368 static struct clk_branch gcc_pcie_0_aux_clk = { 2369 .halt_reg = 0xa9038, 2370 .halt_check = BRANCH_HALT_VOTED, 2371 .clkr = { 2372 .enable_reg = 0x4b010, 2373 .enable_mask = BIT(16), 2374 .hw.init = &(const struct clk_init_data){ 2375 .name = "gcc_pcie_0_aux_clk", 2376 .parent_hws = (const struct clk_hw*[]){ 2377 &gcc_pcie_0_aux_clk_src.clkr.hw, 2378 }, 2379 .num_parents = 1, 2380 .flags = CLK_SET_RATE_PARENT, 2381 .ops = &clk_branch2_ops, 2382 }, 2383 }, 2384 }; 2385 2386 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 2387 .halt_reg = 0xa902c, 2388 .halt_check = BRANCH_HALT_VOTED, 2389 .hwcg_reg = 0xa902c, 2390 .hwcg_bit = 1, 2391 .clkr = { 2392 .enable_reg = 0x4b010, 2393 .enable_mask = BIT(12), 2394 .hw.init = &(const struct clk_init_data){ 2395 .name = "gcc_pcie_0_cfg_ahb_clk", 2396 .ops = &clk_branch2_ops, 2397 }, 2398 }, 2399 }; 2400 2401 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 2402 .halt_reg = 0xa9024, 2403 .halt_check = BRANCH_HALT_VOTED, 2404 .clkr = { 2405 .enable_reg = 0x4b010, 2406 .enable_mask = BIT(11), 2407 .hw.init = &(const struct clk_init_data){ 2408 .name = "gcc_pcie_0_mstr_axi_clk", 2409 .ops = &clk_branch2_ops, 2410 }, 2411 }, 2412 }; 2413 2414 static struct clk_branch gcc_pcie_0_phy_aux_clk = { 2415 .halt_reg = 0xa9030, 2416 .halt_check = BRANCH_HALT_VOTED, 2417 .clkr = { 2418 .enable_reg = 0x4b010, 2419 .enable_mask = BIT(13), 2420 .hw.init = &(const struct clk_init_data){ 2421 .name = "gcc_pcie_0_phy_aux_clk", 2422 .parent_hws = (const struct clk_hw*[]){ 2423 &gcc_pcie_0_phy_aux_clk_src.clkr.hw, 2424 }, 2425 .num_parents = 1, 2426 .flags = CLK_SET_RATE_PARENT, 2427 .ops = &clk_branch2_ops, 2428 }, 2429 }, 2430 }; 2431 2432 static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 2433 .halt_reg = 0xa9050, 2434 .halt_check = BRANCH_HALT_VOTED, 2435 .clkr = { 2436 .enable_reg = 0x4b010, 2437 .enable_mask = BIT(15), 2438 .hw.init = &(const struct clk_init_data){ 2439 .name = "gcc_pcie_0_phy_rchng_clk", 2440 .parent_hws = (const struct clk_hw*[]){ 2441 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 2442 }, 2443 .num_parents = 1, 2444 .flags = CLK_SET_RATE_PARENT, 2445 .ops = &clk_branch2_ops, 2446 }, 2447 }, 2448 }; 2449 2450 static struct clk_branch gcc_pcie_0_pipe_clk = { 2451 .halt_reg = 0xa9040, 2452 .halt_check = BRANCH_HALT_SKIP, 2453 .clkr = { 2454 .enable_reg = 0x4b010, 2455 .enable_mask = BIT(14), 2456 .hw.init = &(const struct clk_init_data){ 2457 .name = "gcc_pcie_0_pipe_clk", 2458 .parent_hws = (const struct clk_hw*[]){ 2459 &gcc_pcie_0_pipe_clk_src.clkr.hw, 2460 }, 2461 .num_parents = 1, 2462 .flags = CLK_SET_RATE_PARENT, 2463 .ops = &clk_branch2_ops, 2464 }, 2465 }, 2466 }; 2467 2468 static struct clk_branch gcc_pcie_0_pipediv2_clk = { 2469 .halt_reg = 0xa9048, 2470 .halt_check = BRANCH_HALT_SKIP, 2471 .clkr = { 2472 .enable_reg = 0x4b018, 2473 .enable_mask = BIT(22), 2474 .hw.init = &(const struct clk_init_data){ 2475 .name = "gcc_pcie_0_pipediv2_clk", 2476 .parent_hws = (const struct clk_hw*[]){ 2477 &gcc_pcie_0_pipe_div_clk_src.clkr.hw, 2478 }, 2479 .num_parents = 1, 2480 .flags = CLK_SET_RATE_PARENT, 2481 .ops = &clk_branch2_ops, 2482 }, 2483 }, 2484 }; 2485 2486 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 2487 .halt_reg = 0xa901c, 2488 .halt_check = BRANCH_HALT_VOTED, 2489 .clkr = { 2490 .enable_reg = 0x4b010, 2491 .enable_mask = BIT(10), 2492 .hw.init = &(const struct clk_init_data){ 2493 .name = "gcc_pcie_0_slv_axi_clk", 2494 .ops = &clk_branch2_ops, 2495 }, 2496 }, 2497 }; 2498 2499 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 2500 .halt_reg = 0xa9018, 2501 .halt_check = BRANCH_HALT_VOTED, 2502 .clkr = { 2503 .enable_reg = 0x4b018, 2504 .enable_mask = BIT(12), 2505 .hw.init = &(const struct clk_init_data){ 2506 .name = "gcc_pcie_0_slv_q2a_axi_clk", 2507 .ops = &clk_branch2_ops, 2508 }, 2509 }, 2510 }; 2511 2512 static struct clk_branch gcc_pcie_1_aux_clk = { 2513 .halt_reg = 0x77038, 2514 .halt_check = BRANCH_HALT_VOTED, 2515 .clkr = { 2516 .enable_reg = 0x4b000, 2517 .enable_mask = BIT(31), 2518 .hw.init = &(const struct clk_init_data){ 2519 .name = "gcc_pcie_1_aux_clk", 2520 .parent_hws = (const struct clk_hw*[]){ 2521 &gcc_pcie_1_aux_clk_src.clkr.hw, 2522 }, 2523 .num_parents = 1, 2524 .flags = CLK_SET_RATE_PARENT, 2525 .ops = &clk_branch2_ops, 2526 }, 2527 }, 2528 }; 2529 2530 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 2531 .halt_reg = 0x7702c, 2532 .halt_check = BRANCH_HALT_VOTED, 2533 .hwcg_reg = 0x7702c, 2534 .hwcg_bit = 1, 2535 .clkr = { 2536 .enable_reg = 0x4b008, 2537 .enable_mask = BIT(2), 2538 .hw.init = &(const struct clk_init_data){ 2539 .name = "gcc_pcie_1_cfg_ahb_clk", 2540 .ops = &clk_branch2_ops, 2541 }, 2542 }, 2543 }; 2544 2545 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 2546 .halt_reg = 0x77024, 2547 .halt_check = BRANCH_HALT_VOTED, 2548 .clkr = { 2549 .enable_reg = 0x4b008, 2550 .enable_mask = BIT(1), 2551 .hw.init = &(const struct clk_init_data){ 2552 .name = "gcc_pcie_1_mstr_axi_clk", 2553 .ops = &clk_branch2_ops, 2554 }, 2555 }, 2556 }; 2557 2558 static struct clk_branch gcc_pcie_1_phy_aux_clk = { 2559 .halt_reg = 0x77030, 2560 .halt_check = BRANCH_HALT_VOTED, 2561 .clkr = { 2562 .enable_reg = 0x4b008, 2563 .enable_mask = BIT(3), 2564 .hw.init = &(const struct clk_init_data){ 2565 .name = "gcc_pcie_1_phy_aux_clk", 2566 .parent_hws = (const struct clk_hw*[]){ 2567 &gcc_pcie_1_phy_aux_clk_src.clkr.hw, 2568 }, 2569 .num_parents = 1, 2570 .flags = CLK_SET_RATE_PARENT, 2571 .ops = &clk_branch2_ops, 2572 }, 2573 }, 2574 }; 2575 2576 static struct clk_branch gcc_pcie_1_phy_rchng_clk = { 2577 .halt_reg = 0x77050, 2578 .halt_check = BRANCH_HALT_VOTED, 2579 .clkr = { 2580 .enable_reg = 0x4b000, 2581 .enable_mask = BIT(22), 2582 .hw.init = &(const struct clk_init_data){ 2583 .name = "gcc_pcie_1_phy_rchng_clk", 2584 .parent_hws = (const struct clk_hw*[]){ 2585 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, 2586 }, 2587 .num_parents = 1, 2588 .flags = CLK_SET_RATE_PARENT, 2589 .ops = &clk_branch2_ops, 2590 }, 2591 }, 2592 }; 2593 2594 static struct clk_branch gcc_pcie_1_pipe_clk = { 2595 .halt_reg = 0x77040, 2596 .halt_check = BRANCH_HALT_SKIP, 2597 .clkr = { 2598 .enable_reg = 0x4b008, 2599 .enable_mask = BIT(4), 2600 .hw.init = &(const struct clk_init_data){ 2601 .name = "gcc_pcie_1_pipe_clk", 2602 .parent_hws = (const struct clk_hw*[]){ 2603 &gcc_pcie_1_pipe_clk_src.clkr.hw, 2604 }, 2605 .num_parents = 1, 2606 .flags = CLK_SET_RATE_PARENT, 2607 .ops = &clk_branch2_ops, 2608 }, 2609 }, 2610 }; 2611 2612 static struct clk_branch gcc_pcie_1_pipediv2_clk = { 2613 .halt_reg = 0x77048, 2614 .halt_check = BRANCH_HALT_SKIP, 2615 .clkr = { 2616 .enable_reg = 0x4b018, 2617 .enable_mask = BIT(16), 2618 .hw.init = &(const struct clk_init_data){ 2619 .name = "gcc_pcie_1_pipediv2_clk", 2620 .parent_hws = (const struct clk_hw*[]){ 2621 &gcc_pcie_1_pipe_div_clk_src.clkr.hw, 2622 }, 2623 .num_parents = 1, 2624 .flags = CLK_SET_RATE_PARENT, 2625 .ops = &clk_branch2_ops, 2626 }, 2627 }, 2628 }; 2629 2630 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 2631 .halt_reg = 0x7701c, 2632 .halt_check = BRANCH_HALT_VOTED, 2633 .clkr = { 2634 .enable_reg = 0x4b008, 2635 .enable_mask = BIT(0), 2636 .hw.init = &(const struct clk_init_data){ 2637 .name = "gcc_pcie_1_slv_axi_clk", 2638 .ops = &clk_branch2_ops, 2639 }, 2640 }, 2641 }; 2642 2643 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 2644 .halt_reg = 0x77018, 2645 .halt_check = BRANCH_HALT_VOTED, 2646 .clkr = { 2647 .enable_reg = 0x4b008, 2648 .enable_mask = BIT(5), 2649 .hw.init = &(const struct clk_init_data){ 2650 .name = "gcc_pcie_1_slv_q2a_axi_clk", 2651 .ops = &clk_branch2_ops, 2652 }, 2653 }, 2654 }; 2655 2656 static struct clk_branch gcc_pcie_clkref_en = { 2657 .halt_reg = 0x9746c, 2658 .halt_check = BRANCH_HALT_DELAY, 2659 .clkr = { 2660 .enable_reg = 0x9746c, 2661 .enable_mask = BIT(0), 2662 .hw.init = &(const struct clk_init_data){ 2663 .name = "gcc_pcie_clkref_en", 2664 .ops = &clk_branch2_ops, 2665 }, 2666 }, 2667 }; 2668 2669 static struct clk_branch gcc_pcie_throttle_cfg_clk = { 2670 .halt_reg = 0xb2034, 2671 .halt_check = BRANCH_HALT_VOTED, 2672 .clkr = { 2673 .enable_reg = 0x4b020, 2674 .enable_mask = BIT(15), 2675 .hw.init = &(const struct clk_init_data){ 2676 .name = "gcc_pcie_throttle_cfg_clk", 2677 .ops = &clk_branch2_ops, 2678 }, 2679 }, 2680 }; 2681 2682 static struct clk_branch gcc_pdm2_clk = { 2683 .halt_reg = 0x3f00c, 2684 .halt_check = BRANCH_HALT, 2685 .clkr = { 2686 .enable_reg = 0x3f00c, 2687 .enable_mask = BIT(0), 2688 .hw.init = &(const struct clk_init_data){ 2689 .name = "gcc_pdm2_clk", 2690 .parent_hws = (const struct clk_hw*[]){ 2691 &gcc_pdm2_clk_src.clkr.hw, 2692 }, 2693 .num_parents = 1, 2694 .flags = CLK_SET_RATE_PARENT, 2695 .ops = &clk_branch2_ops, 2696 }, 2697 }, 2698 }; 2699 2700 static struct clk_branch gcc_pdm_ahb_clk = { 2701 .halt_reg = 0x3f004, 2702 .halt_check = BRANCH_HALT_VOTED, 2703 .hwcg_reg = 0x3f004, 2704 .hwcg_bit = 1, 2705 .clkr = { 2706 .enable_reg = 0x3f004, 2707 .enable_mask = BIT(0), 2708 .hw.init = &(const struct clk_init_data){ 2709 .name = "gcc_pdm_ahb_clk", 2710 .ops = &clk_branch2_ops, 2711 }, 2712 }, 2713 }; 2714 2715 static struct clk_branch gcc_pdm_xo4_clk = { 2716 .halt_reg = 0x3f008, 2717 .halt_check = BRANCH_HALT, 2718 .clkr = { 2719 .enable_reg = 0x3f008, 2720 .enable_mask = BIT(0), 2721 .hw.init = &(const struct clk_init_data){ 2722 .name = "gcc_pdm_xo4_clk", 2723 .ops = &clk_branch2_ops, 2724 }, 2725 }, 2726 }; 2727 2728 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 2729 .halt_reg = 0x32008, 2730 .halt_check = BRANCH_HALT_VOTED, 2731 .hwcg_reg = 0x32008, 2732 .hwcg_bit = 1, 2733 .clkr = { 2734 .enable_reg = 0x32008, 2735 .enable_mask = BIT(0), 2736 .hw.init = &(const struct clk_init_data){ 2737 .name = "gcc_qmip_camera_nrt_ahb_clk", 2738 .ops = &clk_branch2_ops, 2739 }, 2740 }, 2741 }; 2742 2743 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 2744 .halt_reg = 0x3200c, 2745 .halt_check = BRANCH_HALT_VOTED, 2746 .hwcg_reg = 0x3200c, 2747 .hwcg_bit = 1, 2748 .clkr = { 2749 .enable_reg = 0x3200c, 2750 .enable_mask = BIT(0), 2751 .hw.init = &(const struct clk_init_data){ 2752 .name = "gcc_qmip_camera_rt_ahb_clk", 2753 .ops = &clk_branch2_ops, 2754 }, 2755 }, 2756 }; 2757 2758 static struct clk_branch gcc_qmip_disp1_ahb_clk = { 2759 .halt_reg = 0xc7008, 2760 .halt_check = BRANCH_HALT_VOTED, 2761 .hwcg_reg = 0xc7008, 2762 .hwcg_bit = 1, 2763 .clkr = { 2764 .enable_reg = 0xc7008, 2765 .enable_mask = BIT(0), 2766 .hw.init = &(const struct clk_init_data){ 2767 .name = "gcc_qmip_disp1_ahb_clk", 2768 .ops = &clk_branch2_ops, 2769 }, 2770 }, 2771 }; 2772 2773 static struct clk_branch gcc_qmip_disp1_rot_ahb_clk = { 2774 .halt_reg = 0xc700c, 2775 .halt_check = BRANCH_HALT_VOTED, 2776 .clkr = { 2777 .enable_reg = 0xc700c, 2778 .enable_mask = BIT(0), 2779 .hw.init = &(const struct clk_init_data){ 2780 .name = "gcc_qmip_disp1_rot_ahb_clk", 2781 .ops = &clk_branch2_ops, 2782 }, 2783 }, 2784 }; 2785 2786 static struct clk_branch gcc_qmip_disp_ahb_clk = { 2787 .halt_reg = 0x33008, 2788 .halt_check = BRANCH_HALT_VOTED, 2789 .hwcg_reg = 0x33008, 2790 .hwcg_bit = 1, 2791 .clkr = { 2792 .enable_reg = 0x33008, 2793 .enable_mask = BIT(0), 2794 .hw.init = &(const struct clk_init_data){ 2795 .name = "gcc_qmip_disp_ahb_clk", 2796 .ops = &clk_branch2_ops, 2797 }, 2798 }, 2799 }; 2800 2801 static struct clk_branch gcc_qmip_disp_rot_ahb_clk = { 2802 .halt_reg = 0x3300c, 2803 .halt_check = BRANCH_HALT_VOTED, 2804 .clkr = { 2805 .enable_reg = 0x3300c, 2806 .enable_mask = BIT(0), 2807 .hw.init = &(const struct clk_init_data){ 2808 .name = "gcc_qmip_disp_rot_ahb_clk", 2809 .ops = &clk_branch2_ops, 2810 }, 2811 }, 2812 }; 2813 2814 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 2815 .halt_reg = 0x34008, 2816 .halt_check = BRANCH_HALT_VOTED, 2817 .hwcg_reg = 0x34008, 2818 .hwcg_bit = 1, 2819 .clkr = { 2820 .enable_reg = 0x34008, 2821 .enable_mask = BIT(0), 2822 .hw.init = &(const struct clk_init_data){ 2823 .name = "gcc_qmip_video_cvp_ahb_clk", 2824 .ops = &clk_branch2_ops, 2825 }, 2826 }, 2827 }; 2828 2829 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 2830 .halt_reg = 0x3400c, 2831 .halt_check = BRANCH_HALT_VOTED, 2832 .hwcg_reg = 0x3400c, 2833 .hwcg_bit = 1, 2834 .clkr = { 2835 .enable_reg = 0x3400c, 2836 .enable_mask = BIT(0), 2837 .hw.init = &(const struct clk_init_data){ 2838 .name = "gcc_qmip_video_vcodec_ahb_clk", 2839 .ops = &clk_branch2_ops, 2840 }, 2841 }, 2842 }; 2843 2844 static struct clk_branch gcc_qmip_video_vcpu_ahb_clk = { 2845 .halt_reg = 0x34010, 2846 .halt_check = BRANCH_HALT_VOTED, 2847 .hwcg_reg = 0x34010, 2848 .hwcg_bit = 1, 2849 .clkr = { 2850 .enable_reg = 0x34010, 2851 .enable_mask = BIT(0), 2852 .hw.init = &(const struct clk_init_data){ 2853 .name = "gcc_qmip_video_vcpu_ahb_clk", 2854 .ops = &clk_branch2_ops, 2855 }, 2856 }, 2857 }; 2858 2859 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 2860 .halt_reg = 0x23018, 2861 .halt_check = BRANCH_HALT_VOTED, 2862 .clkr = { 2863 .enable_reg = 0x4b008, 2864 .enable_mask = BIT(9), 2865 .hw.init = &(const struct clk_init_data){ 2866 .name = "gcc_qupv3_wrap0_core_2x_clk", 2867 .ops = &clk_branch2_ops, 2868 }, 2869 }, 2870 }; 2871 2872 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 2873 .halt_reg = 0x2300c, 2874 .halt_check = BRANCH_HALT_VOTED, 2875 .clkr = { 2876 .enable_reg = 0x4b008, 2877 .enable_mask = BIT(8), 2878 .hw.init = &(const struct clk_init_data){ 2879 .name = "gcc_qupv3_wrap0_core_clk", 2880 .ops = &clk_branch2_ops, 2881 }, 2882 }, 2883 }; 2884 2885 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2886 .halt_reg = 0x2314c, 2887 .halt_check = BRANCH_HALT_VOTED, 2888 .clkr = { 2889 .enable_reg = 0x4b008, 2890 .enable_mask = BIT(10), 2891 .hw.init = &(const struct clk_init_data){ 2892 .name = "gcc_qupv3_wrap0_s0_clk", 2893 .parent_hws = (const struct clk_hw*[]){ 2894 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 2895 }, 2896 .num_parents = 1, 2897 .flags = CLK_SET_RATE_PARENT, 2898 .ops = &clk_branch2_ops, 2899 }, 2900 }, 2901 }; 2902 2903 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2904 .halt_reg = 0x23280, 2905 .halt_check = BRANCH_HALT_VOTED, 2906 .clkr = { 2907 .enable_reg = 0x4b008, 2908 .enable_mask = BIT(11), 2909 .hw.init = &(const struct clk_init_data){ 2910 .name = "gcc_qupv3_wrap0_s1_clk", 2911 .parent_hws = (const struct clk_hw*[]){ 2912 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 2913 }, 2914 .num_parents = 1, 2915 .flags = CLK_SET_RATE_PARENT, 2916 .ops = &clk_branch2_ops, 2917 }, 2918 }, 2919 }; 2920 2921 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2922 .halt_reg = 0x233b4, 2923 .halt_check = BRANCH_HALT_VOTED, 2924 .clkr = { 2925 .enable_reg = 0x4b008, 2926 .enable_mask = BIT(12), 2927 .hw.init = &(const struct clk_init_data){ 2928 .name = "gcc_qupv3_wrap0_s2_clk", 2929 .parent_hws = (const struct clk_hw*[]){ 2930 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 2931 }, 2932 .num_parents = 1, 2933 .flags = CLK_SET_RATE_PARENT, 2934 .ops = &clk_branch2_ops, 2935 }, 2936 }, 2937 }; 2938 2939 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2940 .halt_reg = 0x234e8, 2941 .halt_check = BRANCH_HALT_VOTED, 2942 .clkr = { 2943 .enable_reg = 0x4b008, 2944 .enable_mask = BIT(13), 2945 .hw.init = &(const struct clk_init_data){ 2946 .name = "gcc_qupv3_wrap0_s3_clk", 2947 .parent_hws = (const struct clk_hw*[]){ 2948 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 2949 }, 2950 .num_parents = 1, 2951 .flags = CLK_SET_RATE_PARENT, 2952 .ops = &clk_branch2_ops, 2953 }, 2954 }, 2955 }; 2956 2957 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2958 .halt_reg = 0x2361c, 2959 .halt_check = BRANCH_HALT_VOTED, 2960 .clkr = { 2961 .enable_reg = 0x4b008, 2962 .enable_mask = BIT(14), 2963 .hw.init = &(const struct clk_init_data){ 2964 .name = "gcc_qupv3_wrap0_s4_clk", 2965 .parent_hws = (const struct clk_hw*[]){ 2966 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 2967 }, 2968 .num_parents = 1, 2969 .flags = CLK_SET_RATE_PARENT, 2970 .ops = &clk_branch2_ops, 2971 }, 2972 }, 2973 }; 2974 2975 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2976 .halt_reg = 0x23750, 2977 .halt_check = BRANCH_HALT_VOTED, 2978 .clkr = { 2979 .enable_reg = 0x4b008, 2980 .enable_mask = BIT(15), 2981 .hw.init = &(const struct clk_init_data){ 2982 .name = "gcc_qupv3_wrap0_s5_clk", 2983 .parent_hws = (const struct clk_hw*[]){ 2984 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 2985 }, 2986 .num_parents = 1, 2987 .flags = CLK_SET_RATE_PARENT, 2988 .ops = &clk_branch2_ops, 2989 }, 2990 }, 2991 }; 2992 2993 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 2994 .halt_reg = 0x23884, 2995 .halt_check = BRANCH_HALT_VOTED, 2996 .clkr = { 2997 .enable_reg = 0x4b008, 2998 .enable_mask = BIT(16), 2999 .hw.init = &(const struct clk_init_data){ 3000 .name = "gcc_qupv3_wrap0_s6_clk", 3001 .parent_hws = (const struct clk_hw*[]){ 3002 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 3003 }, 3004 .num_parents = 1, 3005 .flags = CLK_SET_RATE_PARENT, 3006 .ops = &clk_branch2_ops, 3007 }, 3008 }, 3009 }; 3010 3011 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 3012 .halt_reg = 0x24018, 3013 .halt_check = BRANCH_HALT_VOTED, 3014 .clkr = { 3015 .enable_reg = 0x4b008, 3016 .enable_mask = BIT(18), 3017 .hw.init = &(const struct clk_init_data){ 3018 .name = "gcc_qupv3_wrap1_core_2x_clk", 3019 .ops = &clk_branch2_ops, 3020 }, 3021 }, 3022 }; 3023 3024 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 3025 .halt_reg = 0x2400c, 3026 .halt_check = BRANCH_HALT_VOTED, 3027 .clkr = { 3028 .enable_reg = 0x4b008, 3029 .enable_mask = BIT(19), 3030 .hw.init = &(const struct clk_init_data){ 3031 .name = "gcc_qupv3_wrap1_core_clk", 3032 .ops = &clk_branch2_ops, 3033 }, 3034 }, 3035 }; 3036 3037 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 3038 .halt_reg = 0x2414c, 3039 .halt_check = BRANCH_HALT_VOTED, 3040 .clkr = { 3041 .enable_reg = 0x4b008, 3042 .enable_mask = BIT(22), 3043 .hw.init = &(const struct clk_init_data){ 3044 .name = "gcc_qupv3_wrap1_s0_clk", 3045 .parent_hws = (const struct clk_hw*[]){ 3046 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 3047 }, 3048 .num_parents = 1, 3049 .flags = CLK_SET_RATE_PARENT, 3050 .ops = &clk_branch2_ops, 3051 }, 3052 }, 3053 }; 3054 3055 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 3056 .halt_reg = 0x24280, 3057 .halt_check = BRANCH_HALT_VOTED, 3058 .clkr = { 3059 .enable_reg = 0x4b008, 3060 .enable_mask = BIT(23), 3061 .hw.init = &(const struct clk_init_data){ 3062 .name = "gcc_qupv3_wrap1_s1_clk", 3063 .parent_hws = (const struct clk_hw*[]){ 3064 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 3065 }, 3066 .num_parents = 1, 3067 .flags = CLK_SET_RATE_PARENT, 3068 .ops = &clk_branch2_ops, 3069 }, 3070 }, 3071 }; 3072 3073 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 3074 .halt_reg = 0x243b4, 3075 .halt_check = BRANCH_HALT_VOTED, 3076 .clkr = { 3077 .enable_reg = 0x4b008, 3078 .enable_mask = BIT(24), 3079 .hw.init = &(const struct clk_init_data){ 3080 .name = "gcc_qupv3_wrap1_s2_clk", 3081 .parent_hws = (const struct clk_hw*[]){ 3082 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 3083 }, 3084 .num_parents = 1, 3085 .flags = CLK_SET_RATE_PARENT, 3086 .ops = &clk_branch2_ops, 3087 }, 3088 }, 3089 }; 3090 3091 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 3092 .halt_reg = 0x244e8, 3093 .halt_check = BRANCH_HALT_VOTED, 3094 .clkr = { 3095 .enable_reg = 0x4b008, 3096 .enable_mask = BIT(25), 3097 .hw.init = &(const struct clk_init_data){ 3098 .name = "gcc_qupv3_wrap1_s3_clk", 3099 .parent_hws = (const struct clk_hw*[]){ 3100 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 3101 }, 3102 .num_parents = 1, 3103 .flags = CLK_SET_RATE_PARENT, 3104 .ops = &clk_branch2_ops, 3105 }, 3106 }, 3107 }; 3108 3109 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 3110 .halt_reg = 0x2461c, 3111 .halt_check = BRANCH_HALT_VOTED, 3112 .clkr = { 3113 .enable_reg = 0x4b008, 3114 .enable_mask = BIT(26), 3115 .hw.init = &(const struct clk_init_data){ 3116 .name = "gcc_qupv3_wrap1_s4_clk", 3117 .parent_hws = (const struct clk_hw*[]){ 3118 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 3119 }, 3120 .num_parents = 1, 3121 .flags = CLK_SET_RATE_PARENT, 3122 .ops = &clk_branch2_ops, 3123 }, 3124 }, 3125 }; 3126 3127 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 3128 .halt_reg = 0x24750, 3129 .halt_check = BRANCH_HALT_VOTED, 3130 .clkr = { 3131 .enable_reg = 0x4b008, 3132 .enable_mask = BIT(27), 3133 .hw.init = &(const struct clk_init_data){ 3134 .name = "gcc_qupv3_wrap1_s5_clk", 3135 .parent_hws = (const struct clk_hw*[]){ 3136 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 3137 }, 3138 .num_parents = 1, 3139 .flags = CLK_SET_RATE_PARENT, 3140 .ops = &clk_branch2_ops, 3141 }, 3142 }, 3143 }; 3144 3145 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 3146 .halt_reg = 0x24884, 3147 .halt_check = BRANCH_HALT_VOTED, 3148 .clkr = { 3149 .enable_reg = 0x4b018, 3150 .enable_mask = BIT(27), 3151 .hw.init = &(const struct clk_init_data){ 3152 .name = "gcc_qupv3_wrap1_s6_clk", 3153 .parent_hws = (const struct clk_hw*[]){ 3154 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 3155 }, 3156 .num_parents = 1, 3157 .flags = CLK_SET_RATE_PARENT, 3158 .ops = &clk_branch2_ops, 3159 }, 3160 }, 3161 }; 3162 3163 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { 3164 .halt_reg = 0x2a018, 3165 .halt_check = BRANCH_HALT_VOTED, 3166 .clkr = { 3167 .enable_reg = 0x4b010, 3168 .enable_mask = BIT(3), 3169 .hw.init = &(const struct clk_init_data){ 3170 .name = "gcc_qupv3_wrap2_core_2x_clk", 3171 .ops = &clk_branch2_ops, 3172 }, 3173 }, 3174 }; 3175 3176 static struct clk_branch gcc_qupv3_wrap2_core_clk = { 3177 .halt_reg = 0x2a00c, 3178 .halt_check = BRANCH_HALT_VOTED, 3179 .clkr = { 3180 .enable_reg = 0x4b010, 3181 .enable_mask = BIT(0), 3182 .hw.init = &(const struct clk_init_data){ 3183 .name = "gcc_qupv3_wrap2_core_clk", 3184 .ops = &clk_branch2_ops, 3185 }, 3186 }, 3187 }; 3188 3189 static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 3190 .halt_reg = 0x2a14c, 3191 .halt_check = BRANCH_HALT_VOTED, 3192 .clkr = { 3193 .enable_reg = 0x4b010, 3194 .enable_mask = BIT(4), 3195 .hw.init = &(const struct clk_init_data){ 3196 .name = "gcc_qupv3_wrap2_s0_clk", 3197 .parent_hws = (const struct clk_hw*[]){ 3198 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 3199 }, 3200 .num_parents = 1, 3201 .flags = CLK_SET_RATE_PARENT, 3202 .ops = &clk_branch2_ops, 3203 }, 3204 }, 3205 }; 3206 3207 static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 3208 .halt_reg = 0x2a280, 3209 .halt_check = BRANCH_HALT_VOTED, 3210 .clkr = { 3211 .enable_reg = 0x4b010, 3212 .enable_mask = BIT(5), 3213 .hw.init = &(const struct clk_init_data){ 3214 .name = "gcc_qupv3_wrap2_s1_clk", 3215 .parent_hws = (const struct clk_hw*[]){ 3216 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 3217 }, 3218 .num_parents = 1, 3219 .flags = CLK_SET_RATE_PARENT, 3220 .ops = &clk_branch2_ops, 3221 }, 3222 }, 3223 }; 3224 3225 static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 3226 .halt_reg = 0x2a3b4, 3227 .halt_check = BRANCH_HALT_VOTED, 3228 .clkr = { 3229 .enable_reg = 0x4b010, 3230 .enable_mask = BIT(6), 3231 .hw.init = &(const struct clk_init_data){ 3232 .name = "gcc_qupv3_wrap2_s2_clk", 3233 .parent_hws = (const struct clk_hw*[]){ 3234 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 3235 }, 3236 .num_parents = 1, 3237 .flags = CLK_SET_RATE_PARENT, 3238 .ops = &clk_branch2_ops, 3239 }, 3240 }, 3241 }; 3242 3243 static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 3244 .halt_reg = 0x2a4e8, 3245 .halt_check = BRANCH_HALT_VOTED, 3246 .clkr = { 3247 .enable_reg = 0x4b010, 3248 .enable_mask = BIT(7), 3249 .hw.init = &(const struct clk_init_data){ 3250 .name = "gcc_qupv3_wrap2_s3_clk", 3251 .parent_hws = (const struct clk_hw*[]){ 3252 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 3253 }, 3254 .num_parents = 1, 3255 .flags = CLK_SET_RATE_PARENT, 3256 .ops = &clk_branch2_ops, 3257 }, 3258 }, 3259 }; 3260 3261 static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 3262 .halt_reg = 0x2a61c, 3263 .halt_check = BRANCH_HALT_VOTED, 3264 .clkr = { 3265 .enable_reg = 0x4b010, 3266 .enable_mask = BIT(8), 3267 .hw.init = &(const struct clk_init_data){ 3268 .name = "gcc_qupv3_wrap2_s4_clk", 3269 .parent_hws = (const struct clk_hw*[]){ 3270 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 3271 }, 3272 .num_parents = 1, 3273 .flags = CLK_SET_RATE_PARENT, 3274 .ops = &clk_branch2_ops, 3275 }, 3276 }, 3277 }; 3278 3279 static struct clk_branch gcc_qupv3_wrap2_s5_clk = { 3280 .halt_reg = 0x2a750, 3281 .halt_check = BRANCH_HALT_VOTED, 3282 .clkr = { 3283 .enable_reg = 0x4b010, 3284 .enable_mask = BIT(9), 3285 .hw.init = &(const struct clk_init_data){ 3286 .name = "gcc_qupv3_wrap2_s5_clk", 3287 .parent_hws = (const struct clk_hw*[]){ 3288 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, 3289 }, 3290 .num_parents = 1, 3291 .flags = CLK_SET_RATE_PARENT, 3292 .ops = &clk_branch2_ops, 3293 }, 3294 }, 3295 }; 3296 3297 static struct clk_branch gcc_qupv3_wrap2_s6_clk = { 3298 .halt_reg = 0x2a884, 3299 .halt_check = BRANCH_HALT_VOTED, 3300 .clkr = { 3301 .enable_reg = 0x4b018, 3302 .enable_mask = BIT(29), 3303 .hw.init = &(const struct clk_init_data){ 3304 .name = "gcc_qupv3_wrap2_s6_clk", 3305 .parent_hws = (const struct clk_hw*[]){ 3306 &gcc_qupv3_wrap2_s6_clk_src.clkr.hw, 3307 }, 3308 .num_parents = 1, 3309 .flags = CLK_SET_RATE_PARENT, 3310 .ops = &clk_branch2_ops, 3311 }, 3312 }, 3313 }; 3314 3315 static struct clk_branch gcc_qupv3_wrap3_core_2x_clk = { 3316 .halt_reg = 0xc4018, 3317 .halt_check = BRANCH_HALT_VOTED, 3318 .clkr = { 3319 .enable_reg = 0x4b000, 3320 .enable_mask = BIT(24), 3321 .hw.init = &(const struct clk_init_data){ 3322 .name = "gcc_qupv3_wrap3_core_2x_clk", 3323 .ops = &clk_branch2_ops, 3324 }, 3325 }, 3326 }; 3327 3328 static struct clk_branch gcc_qupv3_wrap3_core_clk = { 3329 .halt_reg = 0xc400c, 3330 .halt_check = BRANCH_HALT_VOTED, 3331 .clkr = { 3332 .enable_reg = 0x4b000, 3333 .enable_mask = BIT(23), 3334 .hw.init = &(const struct clk_init_data){ 3335 .name = "gcc_qupv3_wrap3_core_clk", 3336 .ops = &clk_branch2_ops, 3337 }, 3338 }, 3339 }; 3340 3341 static struct clk_branch gcc_qupv3_wrap3_qspi_clk = { 3342 .halt_reg = 0xc4280, 3343 .halt_check = BRANCH_HALT_VOTED, 3344 .clkr = { 3345 .enable_reg = 0x4b000, 3346 .enable_mask = BIT(26), 3347 .hw.init = &(const struct clk_init_data){ 3348 .name = "gcc_qupv3_wrap3_qspi_clk", 3349 .parent_hws = (const struct clk_hw*[]){ 3350 &gcc_qupv3_wrap3_s0_clk_src.clkr.hw, 3351 }, 3352 .num_parents = 1, 3353 .flags = CLK_SET_RATE_PARENT, 3354 .ops = &clk_branch2_ops, 3355 }, 3356 }, 3357 }; 3358 3359 static struct clk_branch gcc_qupv3_wrap3_s0_clk = { 3360 .halt_reg = 0xc414c, 3361 .halt_check = BRANCH_HALT_VOTED, 3362 .clkr = { 3363 .enable_reg = 0x4b000, 3364 .enable_mask = BIT(25), 3365 .hw.init = &(const struct clk_init_data){ 3366 .name = "gcc_qupv3_wrap3_s0_clk", 3367 .parent_hws = (const struct clk_hw*[]){ 3368 &gcc_qupv3_wrap3_s0_div_clk_src.clkr.hw, 3369 }, 3370 .num_parents = 1, 3371 .flags = CLK_SET_RATE_PARENT, 3372 .ops = &clk_branch2_ops, 3373 }, 3374 }, 3375 }; 3376 3377 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 3378 .halt_reg = 0x23004, 3379 .halt_check = BRANCH_HALT_VOTED, 3380 .hwcg_reg = 0x23004, 3381 .hwcg_bit = 1, 3382 .clkr = { 3383 .enable_reg = 0x4b008, 3384 .enable_mask = BIT(6), 3385 .hw.init = &(const struct clk_init_data){ 3386 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 3387 .ops = &clk_branch2_ops, 3388 }, 3389 }, 3390 }; 3391 3392 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 3393 .halt_reg = 0x23008, 3394 .halt_check = BRANCH_HALT_VOTED, 3395 .hwcg_reg = 0x23008, 3396 .hwcg_bit = 1, 3397 .clkr = { 3398 .enable_reg = 0x4b008, 3399 .enable_mask = BIT(7), 3400 .hw.init = &(const struct clk_init_data){ 3401 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 3402 .ops = &clk_branch2_ops, 3403 }, 3404 }, 3405 }; 3406 3407 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 3408 .halt_reg = 0x24004, 3409 .halt_check = BRANCH_HALT_VOTED, 3410 .hwcg_reg = 0x24004, 3411 .hwcg_bit = 1, 3412 .clkr = { 3413 .enable_reg = 0x4b008, 3414 .enable_mask = BIT(20), 3415 .hw.init = &(const struct clk_init_data){ 3416 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 3417 .ops = &clk_branch2_ops, 3418 }, 3419 }, 3420 }; 3421 3422 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 3423 .halt_reg = 0x24008, 3424 .halt_check = BRANCH_HALT_VOTED, 3425 .hwcg_reg = 0x24008, 3426 .hwcg_bit = 1, 3427 .clkr = { 3428 .enable_reg = 0x4b008, 3429 .enable_mask = BIT(21), 3430 .hw.init = &(const struct clk_init_data){ 3431 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 3432 .ops = &clk_branch2_ops, 3433 }, 3434 }, 3435 }; 3436 3437 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 3438 .halt_reg = 0x2a004, 3439 .halt_check = BRANCH_HALT_VOTED, 3440 .hwcg_reg = 0x2a004, 3441 .hwcg_bit = 1, 3442 .clkr = { 3443 .enable_reg = 0x4b010, 3444 .enable_mask = BIT(2), 3445 .hw.init = &(const struct clk_init_data){ 3446 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 3447 .ops = &clk_branch2_ops, 3448 }, 3449 }, 3450 }; 3451 3452 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 3453 .halt_reg = 0x2a008, 3454 .halt_check = BRANCH_HALT_VOTED, 3455 .hwcg_reg = 0x2a008, 3456 .hwcg_bit = 1, 3457 .clkr = { 3458 .enable_reg = 0x4b010, 3459 .enable_mask = BIT(1), 3460 .hw.init = &(const struct clk_init_data){ 3461 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 3462 .ops = &clk_branch2_ops, 3463 }, 3464 }, 3465 }; 3466 3467 static struct clk_branch gcc_qupv3_wrap_3_m_ahb_clk = { 3468 .halt_reg = 0xc4004, 3469 .halt_check = BRANCH_HALT_VOTED, 3470 .hwcg_reg = 0xc4004, 3471 .hwcg_bit = 1, 3472 .clkr = { 3473 .enable_reg = 0x4b000, 3474 .enable_mask = BIT(27), 3475 .hw.init = &(const struct clk_init_data){ 3476 .name = "gcc_qupv3_wrap_3_m_ahb_clk", 3477 .ops = &clk_branch2_ops, 3478 }, 3479 }, 3480 }; 3481 3482 static struct clk_branch gcc_qupv3_wrap_3_s_ahb_clk = { 3483 .halt_reg = 0xc4008, 3484 .halt_check = BRANCH_HALT_VOTED, 3485 .hwcg_reg = 0xc4008, 3486 .hwcg_bit = 1, 3487 .clkr = { 3488 .enable_reg = 0x4b000, 3489 .enable_mask = BIT(20), 3490 .hw.init = &(const struct clk_init_data){ 3491 .name = "gcc_qupv3_wrap_3_s_ahb_clk", 3492 .ops = &clk_branch2_ops, 3493 }, 3494 }, 3495 }; 3496 3497 static struct clk_branch gcc_sdcc1_ahb_clk = { 3498 .halt_reg = 0x2000c, 3499 .halt_check = BRANCH_HALT, 3500 .clkr = { 3501 .enable_reg = 0x2000c, 3502 .enable_mask = BIT(0), 3503 .hw.init = &(const struct clk_init_data){ 3504 .name = "gcc_sdcc1_ahb_clk", 3505 .ops = &clk_branch2_ops, 3506 }, 3507 }, 3508 }; 3509 3510 static struct clk_branch gcc_sdcc1_apps_clk = { 3511 .halt_reg = 0x20004, 3512 .halt_check = BRANCH_HALT, 3513 .clkr = { 3514 .enable_reg = 0x20004, 3515 .enable_mask = BIT(0), 3516 .hw.init = &(const struct clk_init_data){ 3517 .name = "gcc_sdcc1_apps_clk", 3518 .parent_hws = (const struct clk_hw*[]){ 3519 &gcc_sdcc1_apps_clk_src.clkr.hw, 3520 }, 3521 .num_parents = 1, 3522 .flags = CLK_SET_RATE_PARENT, 3523 .ops = &clk_branch2_ops, 3524 }, 3525 }, 3526 }; 3527 3528 static struct clk_branch gcc_sdcc1_ice_core_clk = { 3529 .halt_reg = 0x20044, 3530 .halt_check = BRANCH_HALT_VOTED, 3531 .hwcg_reg = 0x20044, 3532 .hwcg_bit = 1, 3533 .clkr = { 3534 .enable_reg = 0x20044, 3535 .enable_mask = BIT(0), 3536 .hw.init = &(const struct clk_init_data){ 3537 .name = "gcc_sdcc1_ice_core_clk", 3538 .parent_hws = (const struct clk_hw*[]){ 3539 &gcc_sdcc1_ice_core_clk_src.clkr.hw, 3540 }, 3541 .num_parents = 1, 3542 .flags = CLK_SET_RATE_PARENT, 3543 .ops = &clk_branch2_ops, 3544 }, 3545 }, 3546 }; 3547 3548 static struct clk_branch gcc_sgmi_clkref_en = { 3549 .halt_reg = 0x9c034, 3550 .halt_check = BRANCH_HALT_DELAY, 3551 .clkr = { 3552 .enable_reg = 0x9c034, 3553 .enable_mask = BIT(0), 3554 .hw.init = &(const struct clk_init_data){ 3555 .name = "gcc_sgmi_clkref_en", 3556 .ops = &clk_branch2_ops, 3557 }, 3558 }, 3559 }; 3560 3561 static struct clk_branch gcc_tscss_ahb_clk = { 3562 .halt_reg = 0x21024, 3563 .halt_check = BRANCH_HALT, 3564 .clkr = { 3565 .enable_reg = 0x21024, 3566 .enable_mask = BIT(0), 3567 .hw.init = &(const struct clk_init_data){ 3568 .name = "gcc_tscss_ahb_clk", 3569 .ops = &clk_branch2_ops, 3570 }, 3571 }, 3572 }; 3573 3574 static struct clk_branch gcc_tscss_etu_clk = { 3575 .halt_reg = 0x21020, 3576 .halt_check = BRANCH_HALT, 3577 .clkr = { 3578 .enable_reg = 0x21020, 3579 .enable_mask = BIT(0), 3580 .hw.init = &(const struct clk_init_data){ 3581 .name = "gcc_tscss_etu_clk", 3582 .ops = &clk_branch2_ops, 3583 }, 3584 }, 3585 }; 3586 3587 static struct clk_branch gcc_tscss_global_cntr_clk = { 3588 .halt_reg = 0x21004, 3589 .halt_check = BRANCH_HALT_VOTED, 3590 .clkr = { 3591 .enable_reg = 0x21004, 3592 .enable_mask = BIT(0), 3593 .hw.init = &(const struct clk_init_data){ 3594 .name = "gcc_tscss_global_cntr_clk", 3595 .parent_hws = (const struct clk_hw*[]){ 3596 &gcc_tscss_cntr_clk_src.clkr.hw, 3597 }, 3598 .num_parents = 1, 3599 .flags = CLK_SET_RATE_PARENT, 3600 .ops = &clk_branch2_ops, 3601 }, 3602 }, 3603 }; 3604 3605 static struct clk_branch gcc_ufs_card_ahb_clk = { 3606 .halt_reg = 0x81020, 3607 .halt_check = BRANCH_HALT_VOTED, 3608 .hwcg_reg = 0x81020, 3609 .hwcg_bit = 1, 3610 .clkr = { 3611 .enable_reg = 0x81020, 3612 .enable_mask = BIT(0), 3613 .hw.init = &(const struct clk_init_data){ 3614 .name = "gcc_ufs_card_ahb_clk", 3615 .ops = &clk_branch2_ops, 3616 }, 3617 }, 3618 }; 3619 3620 static struct clk_branch gcc_ufs_card_axi_clk = { 3621 .halt_reg = 0x81018, 3622 .halt_check = BRANCH_HALT_VOTED, 3623 .hwcg_reg = 0x81018, 3624 .hwcg_bit = 1, 3625 .clkr = { 3626 .enable_reg = 0x81018, 3627 .enable_mask = BIT(0), 3628 .hw.init = &(const struct clk_init_data){ 3629 .name = "gcc_ufs_card_axi_clk", 3630 .parent_hws = (const struct clk_hw*[]){ 3631 &gcc_ufs_card_axi_clk_src.clkr.hw, 3632 }, 3633 .num_parents = 1, 3634 .flags = CLK_SET_RATE_PARENT, 3635 .ops = &clk_branch2_ops, 3636 }, 3637 }, 3638 }; 3639 3640 static struct clk_branch gcc_ufs_card_ice_core_clk = { 3641 .halt_reg = 0x8106c, 3642 .halt_check = BRANCH_HALT_VOTED, 3643 .hwcg_reg = 0x8106c, 3644 .hwcg_bit = 1, 3645 .clkr = { 3646 .enable_reg = 0x8106c, 3647 .enable_mask = BIT(0), 3648 .hw.init = &(const struct clk_init_data){ 3649 .name = "gcc_ufs_card_ice_core_clk", 3650 .parent_hws = (const struct clk_hw*[]){ 3651 &gcc_ufs_card_ice_core_clk_src.clkr.hw, 3652 }, 3653 .num_parents = 1, 3654 .flags = CLK_SET_RATE_PARENT, 3655 .ops = &clk_branch2_ops, 3656 }, 3657 }, 3658 }; 3659 3660 static struct clk_branch gcc_ufs_card_phy_aux_clk = { 3661 .halt_reg = 0x810a4, 3662 .halt_check = BRANCH_HALT_VOTED, 3663 .hwcg_reg = 0x810a4, 3664 .hwcg_bit = 1, 3665 .clkr = { 3666 .enable_reg = 0x810a4, 3667 .enable_mask = BIT(0), 3668 .hw.init = &(const struct clk_init_data){ 3669 .name = "gcc_ufs_card_phy_aux_clk", 3670 .parent_hws = (const struct clk_hw*[]){ 3671 &gcc_ufs_card_phy_aux_clk_src.clkr.hw, 3672 }, 3673 .num_parents = 1, 3674 .flags = CLK_SET_RATE_PARENT, 3675 .ops = &clk_branch2_ops, 3676 }, 3677 }, 3678 }; 3679 3680 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { 3681 .halt_reg = 0x81028, 3682 .halt_check = BRANCH_HALT_DELAY, 3683 .clkr = { 3684 .enable_reg = 0x81028, 3685 .enable_mask = BIT(0), 3686 .hw.init = &(const struct clk_init_data){ 3687 .name = "gcc_ufs_card_rx_symbol_0_clk", 3688 .parent_hws = (const struct clk_hw*[]){ 3689 &gcc_ufs_card_rx_symbol_0_clk_src.clkr.hw, 3690 }, 3691 .num_parents = 1, 3692 .flags = CLK_SET_RATE_PARENT, 3693 .ops = &clk_branch2_ops, 3694 }, 3695 }, 3696 }; 3697 3698 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = { 3699 .halt_reg = 0x810c0, 3700 .halt_check = BRANCH_HALT_DELAY, 3701 .clkr = { 3702 .enable_reg = 0x810c0, 3703 .enable_mask = BIT(0), 3704 .hw.init = &(const struct clk_init_data){ 3705 .name = "gcc_ufs_card_rx_symbol_1_clk", 3706 .parent_hws = (const struct clk_hw*[]){ 3707 &gcc_ufs_card_rx_symbol_1_clk_src.clkr.hw, 3708 }, 3709 .num_parents = 1, 3710 .flags = CLK_SET_RATE_PARENT, 3711 .ops = &clk_branch2_ops, 3712 }, 3713 }, 3714 }; 3715 3716 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = { 3717 .halt_reg = 0x81024, 3718 .halt_check = BRANCH_HALT_DELAY, 3719 .clkr = { 3720 .enable_reg = 0x81024, 3721 .enable_mask = BIT(0), 3722 .hw.init = &(const struct clk_init_data){ 3723 .name = "gcc_ufs_card_tx_symbol_0_clk", 3724 .parent_hws = (const struct clk_hw*[]){ 3725 &gcc_ufs_card_tx_symbol_0_clk_src.clkr.hw, 3726 }, 3727 .num_parents = 1, 3728 .flags = CLK_SET_RATE_PARENT, 3729 .ops = &clk_branch2_ops, 3730 }, 3731 }, 3732 }; 3733 3734 static struct clk_branch gcc_ufs_card_unipro_core_clk = { 3735 .halt_reg = 0x81064, 3736 .halt_check = BRANCH_HALT_VOTED, 3737 .hwcg_reg = 0x81064, 3738 .hwcg_bit = 1, 3739 .clkr = { 3740 .enable_reg = 0x81064, 3741 .enable_mask = BIT(0), 3742 .hw.init = &(const struct clk_init_data){ 3743 .name = "gcc_ufs_card_unipro_core_clk", 3744 .parent_hws = (const struct clk_hw*[]){ 3745 &gcc_ufs_card_unipro_core_clk_src.clkr.hw, 3746 }, 3747 .num_parents = 1, 3748 .flags = CLK_SET_RATE_PARENT, 3749 .ops = &clk_branch2_ops, 3750 }, 3751 }, 3752 }; 3753 3754 static struct clk_branch gcc_ufs_phy_ahb_clk = { 3755 .halt_reg = 0x83020, 3756 .halt_check = BRANCH_HALT_VOTED, 3757 .hwcg_reg = 0x83020, 3758 .hwcg_bit = 1, 3759 .clkr = { 3760 .enable_reg = 0x83020, 3761 .enable_mask = BIT(0), 3762 .hw.init = &(const struct clk_init_data){ 3763 .name = "gcc_ufs_phy_ahb_clk", 3764 .ops = &clk_branch2_ops, 3765 }, 3766 }, 3767 }; 3768 3769 static struct clk_branch gcc_ufs_phy_axi_clk = { 3770 .halt_reg = 0x83018, 3771 .halt_check = BRANCH_HALT_VOTED, 3772 .hwcg_reg = 0x83018, 3773 .hwcg_bit = 1, 3774 .clkr = { 3775 .enable_reg = 0x83018, 3776 .enable_mask = BIT(0), 3777 .hw.init = &(const struct clk_init_data){ 3778 .name = "gcc_ufs_phy_axi_clk", 3779 .parent_hws = (const struct clk_hw*[]){ 3780 &gcc_ufs_phy_axi_clk_src.clkr.hw, 3781 }, 3782 .num_parents = 1, 3783 .flags = CLK_SET_RATE_PARENT, 3784 .ops = &clk_branch2_ops, 3785 }, 3786 }, 3787 }; 3788 3789 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 3790 .halt_reg = 0x8306c, 3791 .halt_check = BRANCH_HALT_VOTED, 3792 .hwcg_reg = 0x8306c, 3793 .hwcg_bit = 1, 3794 .clkr = { 3795 .enable_reg = 0x8306c, 3796 .enable_mask = BIT(0), 3797 .hw.init = &(const struct clk_init_data){ 3798 .name = "gcc_ufs_phy_ice_core_clk", 3799 .parent_hws = (const struct clk_hw*[]){ 3800 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 3801 }, 3802 .num_parents = 1, 3803 .flags = CLK_SET_RATE_PARENT, 3804 .ops = &clk_branch2_ops, 3805 }, 3806 }, 3807 }; 3808 3809 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 3810 .halt_reg = 0x830a4, 3811 .halt_check = BRANCH_HALT_VOTED, 3812 .hwcg_reg = 0x830a4, 3813 .hwcg_bit = 1, 3814 .clkr = { 3815 .enable_reg = 0x830a4, 3816 .enable_mask = BIT(0), 3817 .hw.init = &(const struct clk_init_data){ 3818 .name = "gcc_ufs_phy_phy_aux_clk", 3819 .parent_hws = (const struct clk_hw*[]){ 3820 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 3821 }, 3822 .num_parents = 1, 3823 .flags = CLK_SET_RATE_PARENT, 3824 .ops = &clk_branch2_ops, 3825 }, 3826 }, 3827 }; 3828 3829 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 3830 .halt_reg = 0x83028, 3831 .halt_check = BRANCH_HALT_DELAY, 3832 .clkr = { 3833 .enable_reg = 0x83028, 3834 .enable_mask = BIT(0), 3835 .hw.init = &(const struct clk_init_data){ 3836 .name = "gcc_ufs_phy_rx_symbol_0_clk", 3837 .parent_hws = (const struct clk_hw*[]){ 3838 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, 3839 }, 3840 .num_parents = 1, 3841 .flags = CLK_SET_RATE_PARENT, 3842 .ops = &clk_branch2_ops, 3843 }, 3844 }, 3845 }; 3846 3847 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 3848 .halt_reg = 0x830c0, 3849 .halt_check = BRANCH_HALT_DELAY, 3850 .clkr = { 3851 .enable_reg = 0x830c0, 3852 .enable_mask = BIT(0), 3853 .hw.init = &(const struct clk_init_data){ 3854 .name = "gcc_ufs_phy_rx_symbol_1_clk", 3855 .parent_hws = (const struct clk_hw*[]){ 3856 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, 3857 }, 3858 .num_parents = 1, 3859 .flags = CLK_SET_RATE_PARENT, 3860 .ops = &clk_branch2_ops, 3861 }, 3862 }, 3863 }; 3864 3865 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 3866 .halt_reg = 0x83024, 3867 .halt_check = BRANCH_HALT_DELAY, 3868 .clkr = { 3869 .enable_reg = 0x83024, 3870 .enable_mask = BIT(0), 3871 .hw.init = &(const struct clk_init_data){ 3872 .name = "gcc_ufs_phy_tx_symbol_0_clk", 3873 .parent_hws = (const struct clk_hw*[]){ 3874 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, 3875 }, 3876 .num_parents = 1, 3877 .flags = CLK_SET_RATE_PARENT, 3878 .ops = &clk_branch2_ops, 3879 }, 3880 }, 3881 }; 3882 3883 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 3884 .halt_reg = 0x83064, 3885 .halt_check = BRANCH_HALT_VOTED, 3886 .hwcg_reg = 0x83064, 3887 .hwcg_bit = 1, 3888 .clkr = { 3889 .enable_reg = 0x83064, 3890 .enable_mask = BIT(0), 3891 .hw.init = &(const struct clk_init_data){ 3892 .name = "gcc_ufs_phy_unipro_core_clk", 3893 .parent_hws = (const struct clk_hw*[]){ 3894 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 3895 }, 3896 .num_parents = 1, 3897 .flags = CLK_SET_RATE_PARENT, 3898 .ops = &clk_branch2_ops, 3899 }, 3900 }, 3901 }; 3902 3903 static struct clk_branch gcc_usb20_master_clk = { 3904 .halt_reg = 0x1c018, 3905 .halt_check = BRANCH_HALT, 3906 .clkr = { 3907 .enable_reg = 0x1c018, 3908 .enable_mask = BIT(0), 3909 .hw.init = &(const struct clk_init_data){ 3910 .name = "gcc_usb20_master_clk", 3911 .parent_hws = (const struct clk_hw*[]){ 3912 &gcc_usb20_master_clk_src.clkr.hw, 3913 }, 3914 .num_parents = 1, 3915 .flags = CLK_SET_RATE_PARENT, 3916 .ops = &clk_branch2_ops, 3917 }, 3918 }, 3919 }; 3920 3921 static struct clk_branch gcc_usb20_mock_utmi_clk = { 3922 .halt_reg = 0x1c024, 3923 .halt_check = BRANCH_HALT, 3924 .clkr = { 3925 .enable_reg = 0x1c024, 3926 .enable_mask = BIT(0), 3927 .hw.init = &(const struct clk_init_data){ 3928 .name = "gcc_usb20_mock_utmi_clk", 3929 .parent_hws = (const struct clk_hw*[]){ 3930 &gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw, 3931 }, 3932 .num_parents = 1, 3933 .flags = CLK_SET_RATE_PARENT, 3934 .ops = &clk_branch2_ops, 3935 }, 3936 }, 3937 }; 3938 3939 static struct clk_branch gcc_usb20_sleep_clk = { 3940 .halt_reg = 0x1c020, 3941 .halt_check = BRANCH_HALT, 3942 .clkr = { 3943 .enable_reg = 0x1c020, 3944 .enable_mask = BIT(0), 3945 .hw.init = &(const struct clk_init_data){ 3946 .name = "gcc_usb20_sleep_clk", 3947 .ops = &clk_branch2_ops, 3948 }, 3949 }, 3950 }; 3951 3952 static struct clk_branch gcc_usb30_prim_master_clk = { 3953 .halt_reg = 0x1b018, 3954 .halt_check = BRANCH_HALT, 3955 .clkr = { 3956 .enable_reg = 0x1b018, 3957 .enable_mask = BIT(0), 3958 .hw.init = &(const struct clk_init_data){ 3959 .name = "gcc_usb30_prim_master_clk", 3960 .parent_hws = (const struct clk_hw*[]){ 3961 &gcc_usb30_prim_master_clk_src.clkr.hw, 3962 }, 3963 .num_parents = 1, 3964 .flags = CLK_SET_RATE_PARENT, 3965 .ops = &clk_branch2_ops, 3966 }, 3967 }, 3968 }; 3969 3970 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 3971 .halt_reg = 0x1b024, 3972 .halt_check = BRANCH_HALT, 3973 .clkr = { 3974 .enable_reg = 0x1b024, 3975 .enable_mask = BIT(0), 3976 .hw.init = &(const struct clk_init_data){ 3977 .name = "gcc_usb30_prim_mock_utmi_clk", 3978 .parent_hws = (const struct clk_hw*[]){ 3979 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 3980 }, 3981 .num_parents = 1, 3982 .flags = CLK_SET_RATE_PARENT, 3983 .ops = &clk_branch2_ops, 3984 }, 3985 }, 3986 }; 3987 3988 static struct clk_branch gcc_usb30_prim_sleep_clk = { 3989 .halt_reg = 0x1b020, 3990 .halt_check = BRANCH_HALT, 3991 .clkr = { 3992 .enable_reg = 0x1b020, 3993 .enable_mask = BIT(0), 3994 .hw.init = &(const struct clk_init_data){ 3995 .name = "gcc_usb30_prim_sleep_clk", 3996 .ops = &clk_branch2_ops, 3997 }, 3998 }, 3999 }; 4000 4001 static struct clk_branch gcc_usb30_sec_master_clk = { 4002 .halt_reg = 0x2f018, 4003 .halt_check = BRANCH_HALT, 4004 .clkr = { 4005 .enable_reg = 0x2f018, 4006 .enable_mask = BIT(0), 4007 .hw.init = &(const struct clk_init_data){ 4008 .name = "gcc_usb30_sec_master_clk", 4009 .parent_hws = (const struct clk_hw*[]){ 4010 &gcc_usb30_sec_master_clk_src.clkr.hw, 4011 }, 4012 .num_parents = 1, 4013 .flags = CLK_SET_RATE_PARENT, 4014 .ops = &clk_branch2_ops, 4015 }, 4016 }, 4017 }; 4018 4019 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { 4020 .halt_reg = 0x2f024, 4021 .halt_check = BRANCH_HALT, 4022 .clkr = { 4023 .enable_reg = 0x2f024, 4024 .enable_mask = BIT(0), 4025 .hw.init = &(const struct clk_init_data){ 4026 .name = "gcc_usb30_sec_mock_utmi_clk", 4027 .parent_hws = (const struct clk_hw*[]){ 4028 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw, 4029 }, 4030 .num_parents = 1, 4031 .flags = CLK_SET_RATE_PARENT, 4032 .ops = &clk_branch2_ops, 4033 }, 4034 }, 4035 }; 4036 4037 static struct clk_branch gcc_usb30_sec_sleep_clk = { 4038 .halt_reg = 0x2f020, 4039 .halt_check = BRANCH_HALT, 4040 .clkr = { 4041 .enable_reg = 0x2f020, 4042 .enable_mask = BIT(0), 4043 .hw.init = &(const struct clk_init_data){ 4044 .name = "gcc_usb30_sec_sleep_clk", 4045 .ops = &clk_branch2_ops, 4046 }, 4047 }, 4048 }; 4049 4050 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 4051 .halt_reg = 0x1b05c, 4052 .halt_check = BRANCH_HALT, 4053 .clkr = { 4054 .enable_reg = 0x1b05c, 4055 .enable_mask = BIT(0), 4056 .hw.init = &(const struct clk_init_data){ 4057 .name = "gcc_usb3_prim_phy_aux_clk", 4058 .parent_hws = (const struct clk_hw*[]){ 4059 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 4060 }, 4061 .num_parents = 1, 4062 .flags = CLK_SET_RATE_PARENT, 4063 .ops = &clk_branch2_ops, 4064 }, 4065 }, 4066 }; 4067 4068 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 4069 .halt_reg = 0x1b060, 4070 .halt_check = BRANCH_HALT, 4071 .clkr = { 4072 .enable_reg = 0x1b060, 4073 .enable_mask = BIT(0), 4074 .hw.init = &(const struct clk_init_data){ 4075 .name = "gcc_usb3_prim_phy_com_aux_clk", 4076 .parent_hws = (const struct clk_hw*[]){ 4077 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 4078 }, 4079 .num_parents = 1, 4080 .flags = CLK_SET_RATE_PARENT, 4081 .ops = &clk_branch2_ops, 4082 }, 4083 }, 4084 }; 4085 4086 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 4087 .halt_reg = 0x1b064, 4088 .halt_check = BRANCH_HALT_DELAY, 4089 .hwcg_reg = 0x1b064, 4090 .hwcg_bit = 1, 4091 .clkr = { 4092 .enable_reg = 0x1b064, 4093 .enable_mask = BIT(0), 4094 .hw.init = &(const struct clk_init_data){ 4095 .name = "gcc_usb3_prim_phy_pipe_clk", 4096 .parent_hws = (const struct clk_hw*[]){ 4097 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 4098 }, 4099 .num_parents = 1, 4100 .flags = CLK_SET_RATE_PARENT, 4101 .ops = &clk_branch2_ops, 4102 }, 4103 }, 4104 }; 4105 4106 static struct clk_branch gcc_usb3_sec_phy_aux_clk = { 4107 .halt_reg = 0x2f05c, 4108 .halt_check = BRANCH_HALT, 4109 .clkr = { 4110 .enable_reg = 0x2f05c, 4111 .enable_mask = BIT(0), 4112 .hw.init = &(const struct clk_init_data){ 4113 .name = "gcc_usb3_sec_phy_aux_clk", 4114 .parent_hws = (const struct clk_hw*[]){ 4115 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 4116 }, 4117 .num_parents = 1, 4118 .flags = CLK_SET_RATE_PARENT, 4119 .ops = &clk_branch2_ops, 4120 }, 4121 }, 4122 }; 4123 4124 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { 4125 .halt_reg = 0x2f060, 4126 .halt_check = BRANCH_HALT, 4127 .clkr = { 4128 .enable_reg = 0x2f060, 4129 .enable_mask = BIT(0), 4130 .hw.init = &(const struct clk_init_data){ 4131 .name = "gcc_usb3_sec_phy_com_aux_clk", 4132 .parent_hws = (const struct clk_hw*[]){ 4133 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 4134 }, 4135 .num_parents = 1, 4136 .flags = CLK_SET_RATE_PARENT, 4137 .ops = &clk_branch2_ops, 4138 }, 4139 }, 4140 }; 4141 4142 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { 4143 .halt_reg = 0x2f064, 4144 .halt_check = BRANCH_HALT_DELAY, 4145 .clkr = { 4146 .enable_reg = 0x2f064, 4147 .enable_mask = BIT(0), 4148 .hw.init = &(const struct clk_init_data){ 4149 .name = "gcc_usb3_sec_phy_pipe_clk", 4150 .parent_hws = (const struct clk_hw*[]){ 4151 &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw, 4152 }, 4153 .num_parents = 1, 4154 .flags = CLK_SET_RATE_PARENT, 4155 .ops = &clk_branch2_ops, 4156 }, 4157 }, 4158 }; 4159 4160 static struct clk_branch gcc_usb_clkref_en = { 4161 .halt_reg = 0x97468, 4162 .halt_check = BRANCH_HALT_DELAY, 4163 .clkr = { 4164 .enable_reg = 0x97468, 4165 .enable_mask = BIT(0), 4166 .hw.init = &(const struct clk_init_data){ 4167 .name = "gcc_usb_clkref_en", 4168 .ops = &clk_branch2_ops, 4169 }, 4170 }, 4171 }; 4172 4173 static struct clk_branch gcc_video_axi0_clk = { 4174 .halt_reg = 0x34014, 4175 .halt_check = BRANCH_HALT_VOTED, 4176 .hwcg_reg = 0x34014, 4177 .hwcg_bit = 1, 4178 .clkr = { 4179 .enable_reg = 0x34014, 4180 .enable_mask = BIT(0), 4181 .hw.init = &(const struct clk_init_data){ 4182 .name = "gcc_video_axi0_clk", 4183 .ops = &clk_branch2_ops, 4184 }, 4185 }, 4186 }; 4187 4188 static struct clk_branch gcc_video_axi1_clk = { 4189 .halt_reg = 0x3401c, 4190 .halt_check = BRANCH_HALT_VOTED, 4191 .hwcg_reg = 0x3401c, 4192 .hwcg_bit = 1, 4193 .clkr = { 4194 .enable_reg = 0x3401c, 4195 .enable_mask = BIT(0), 4196 .hw.init = &(const struct clk_init_data){ 4197 .name = "gcc_video_axi1_clk", 4198 .ops = &clk_branch2_ops, 4199 }, 4200 }, 4201 }; 4202 4203 static struct gdsc pcie_0_gdsc = { 4204 .gdscr = 0xa9004, 4205 .collapse_ctrl = 0x4b104, 4206 .collapse_mask = BIT(0), 4207 .en_rest_wait_val = 0x2, 4208 .en_few_wait_val = 0x2, 4209 .clk_dis_wait_val = 0xf, 4210 .pd = { 4211 .name = "pcie_0_gdsc", 4212 }, 4213 .pwrsts = PWRSTS_OFF_ON, 4214 .flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4215 }; 4216 4217 static struct gdsc pcie_1_gdsc = { 4218 .gdscr = 0x77004, 4219 .collapse_ctrl = 0x4b104, 4220 .collapse_mask = BIT(1), 4221 .en_rest_wait_val = 0x2, 4222 .en_few_wait_val = 0x2, 4223 .clk_dis_wait_val = 0xf, 4224 .pd = { 4225 .name = "pcie_1_gdsc", 4226 }, 4227 .pwrsts = PWRSTS_OFF_ON, 4228 .flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4229 }; 4230 4231 static struct gdsc ufs_card_gdsc = { 4232 .gdscr = 0x81004, 4233 .en_rest_wait_val = 0x2, 4234 .en_few_wait_val = 0x2, 4235 .clk_dis_wait_val = 0xf, 4236 .pd = { 4237 .name = "ufs_card_gdsc", 4238 }, 4239 .pwrsts = PWRSTS_OFF_ON, 4240 .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4241 }; 4242 4243 static struct gdsc ufs_phy_gdsc = { 4244 .gdscr = 0x83004, 4245 .en_rest_wait_val = 0x2, 4246 .en_few_wait_val = 0x2, 4247 .clk_dis_wait_val = 0xf, 4248 .pd = { 4249 .name = "ufs_phy_gdsc", 4250 }, 4251 .pwrsts = PWRSTS_OFF_ON, 4252 .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4253 }; 4254 4255 static struct gdsc usb20_prim_gdsc = { 4256 .gdscr = 0x1c004, 4257 .en_rest_wait_val = 0x2, 4258 .en_few_wait_val = 0x2, 4259 .clk_dis_wait_val = 0xf, 4260 .pd = { 4261 .name = "usb20_prim_gdsc", 4262 }, 4263 .pwrsts = PWRSTS_OFF_ON, 4264 .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4265 }; 4266 4267 static struct gdsc usb30_prim_gdsc = { 4268 .gdscr = 0x1b004, 4269 .en_rest_wait_val = 0x2, 4270 .en_few_wait_val = 0x2, 4271 .clk_dis_wait_val = 0xf, 4272 .pd = { 4273 .name = "usb30_prim_gdsc", 4274 }, 4275 .pwrsts = PWRSTS_OFF_ON, 4276 .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4277 }; 4278 4279 static struct gdsc usb30_sec_gdsc = { 4280 .gdscr = 0x2f004, 4281 .en_rest_wait_val = 0x2, 4282 .en_few_wait_val = 0x2, 4283 .clk_dis_wait_val = 0xf, 4284 .pd = { 4285 .name = "usb30_sec_gdsc", 4286 }, 4287 .pwrsts = PWRSTS_OFF_ON, 4288 .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4289 }; 4290 4291 static struct gdsc emac0_gdsc = { 4292 .gdscr = 0xb6004, 4293 .en_rest_wait_val = 0x2, 4294 .en_few_wait_val = 0x2, 4295 .clk_dis_wait_val = 0xf, 4296 .pd = { 4297 .name = "emac0_gdsc", 4298 }, 4299 .pwrsts = PWRSTS_OFF_ON, 4300 .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4301 }; 4302 4303 static struct gdsc emac1_gdsc = { 4304 .gdscr = 0xb4004, 4305 .en_rest_wait_val = 0x2, 4306 .en_few_wait_val = 0x2, 4307 .clk_dis_wait_val = 0xf, 4308 .pd = { 4309 .name = "emac1_gdsc", 4310 }, 4311 .pwrsts = PWRSTS_OFF_ON, 4312 .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4313 }; 4314 4315 static struct clk_regmap *gcc_sa8775p_clocks[] = { 4316 [GCC_AGGRE_NOC_QUPV3_AXI_CLK] = &gcc_aggre_noc_qupv3_axi_clk.clkr, 4317 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, 4318 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 4319 [GCC_AGGRE_USB2_PRIM_AXI_CLK] = &gcc_aggre_usb2_prim_axi_clk.clkr, 4320 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 4321 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, 4322 [GCC_AHB2PHY0_CLK] = &gcc_ahb2phy0_clk.clkr, 4323 [GCC_AHB2PHY2_CLK] = &gcc_ahb2phy2_clk.clkr, 4324 [GCC_AHB2PHY3_CLK] = &gcc_ahb2phy3_clk.clkr, 4325 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 4326 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 4327 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 4328 [GCC_CAMERA_THROTTLE_XO_CLK] = &gcc_camera_throttle_xo_clk.clkr, 4329 [GCC_CFG_NOC_USB2_PRIM_AXI_CLK] = &gcc_cfg_noc_usb2_prim_axi_clk.clkr, 4330 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 4331 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, 4332 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 4333 [GCC_DISP1_HF_AXI_CLK] = &gcc_disp1_hf_axi_clk.clkr, 4334 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 4335 [GCC_EDP_REF_CLKREF_EN] = &gcc_edp_ref_clkref_en.clkr, 4336 [GCC_EMAC0_AXI_CLK] = &gcc_emac0_axi_clk.clkr, 4337 [GCC_EMAC0_PHY_AUX_CLK] = &gcc_emac0_phy_aux_clk.clkr, 4338 [GCC_EMAC0_PHY_AUX_CLK_SRC] = &gcc_emac0_phy_aux_clk_src.clkr, 4339 [GCC_EMAC0_PTP_CLK] = &gcc_emac0_ptp_clk.clkr, 4340 [GCC_EMAC0_PTP_CLK_SRC] = &gcc_emac0_ptp_clk_src.clkr, 4341 [GCC_EMAC0_RGMII_CLK] = &gcc_emac0_rgmii_clk.clkr, 4342 [GCC_EMAC0_RGMII_CLK_SRC] = &gcc_emac0_rgmii_clk_src.clkr, 4343 [GCC_EMAC0_SLV_AHB_CLK] = &gcc_emac0_slv_ahb_clk.clkr, 4344 [GCC_EMAC1_AXI_CLK] = &gcc_emac1_axi_clk.clkr, 4345 [GCC_EMAC1_PHY_AUX_CLK] = &gcc_emac1_phy_aux_clk.clkr, 4346 [GCC_EMAC1_PHY_AUX_CLK_SRC] = &gcc_emac1_phy_aux_clk_src.clkr, 4347 [GCC_EMAC1_PTP_CLK] = &gcc_emac1_ptp_clk.clkr, 4348 [GCC_EMAC1_PTP_CLK_SRC] = &gcc_emac1_ptp_clk_src.clkr, 4349 [GCC_EMAC1_RGMII_CLK] = &gcc_emac1_rgmii_clk.clkr, 4350 [GCC_EMAC1_RGMII_CLK_SRC] = &gcc_emac1_rgmii_clk_src.clkr, 4351 [GCC_EMAC1_SLV_AHB_CLK] = &gcc_emac1_slv_ahb_clk.clkr, 4352 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 4353 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 4354 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 4355 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 4356 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 4357 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 4358 [GCC_GP4_CLK] = &gcc_gp4_clk.clkr, 4359 [GCC_GP4_CLK_SRC] = &gcc_gp4_clk_src.clkr, 4360 [GCC_GP5_CLK] = &gcc_gp5_clk.clkr, 4361 [GCC_GP5_CLK_SRC] = &gcc_gp5_clk_src.clkr, 4362 [GCC_GPLL0] = &gcc_gpll0.clkr, 4363 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 4364 [GCC_GPLL1] = &gcc_gpll1.clkr, 4365 [GCC_GPLL4] = &gcc_gpll4.clkr, 4366 [GCC_GPLL5] = &gcc_gpll5.clkr, 4367 [GCC_GPLL7] = &gcc_gpll7.clkr, 4368 [GCC_GPLL9] = &gcc_gpll9.clkr, 4369 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 4370 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 4371 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 4372 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 4373 [GCC_GPU_TCU_THROTTLE_AHB_CLK] = &gcc_gpu_tcu_throttle_ahb_clk.clkr, 4374 [GCC_GPU_TCU_THROTTLE_CLK] = &gcc_gpu_tcu_throttle_clk.clkr, 4375 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 4376 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 4377 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 4378 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 4379 [GCC_PCIE_0_PHY_AUX_CLK] = &gcc_pcie_0_phy_aux_clk.clkr, 4380 [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, 4381 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 4382 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 4383 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 4384 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 4385 [GCC_PCIE_0_PIPE_DIV_CLK_SRC] = &gcc_pcie_0_pipe_div_clk_src.clkr, 4386 [GCC_PCIE_0_PIPEDIV2_CLK] = &gcc_pcie_0_pipediv2_clk.clkr, 4387 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 4388 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 4389 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 4390 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 4391 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 4392 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 4393 [GCC_PCIE_1_PHY_AUX_CLK] = &gcc_pcie_1_phy_aux_clk.clkr, 4394 [GCC_PCIE_1_PHY_AUX_CLK_SRC] = &gcc_pcie_1_phy_aux_clk_src.clkr, 4395 [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr, 4396 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, 4397 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 4398 [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr, 4399 [GCC_PCIE_1_PIPE_DIV_CLK_SRC] = &gcc_pcie_1_pipe_div_clk_src.clkr, 4400 [GCC_PCIE_1_PIPEDIV2_CLK] = &gcc_pcie_1_pipediv2_clk.clkr, 4401 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 4402 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 4403 [GCC_PCIE_CLKREF_EN] = &gcc_pcie_clkref_en.clkr, 4404 [GCC_PCIE_THROTTLE_CFG_CLK] = &gcc_pcie_throttle_cfg_clk.clkr, 4405 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 4406 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 4407 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 4408 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 4409 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 4410 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 4411 [GCC_QMIP_DISP1_AHB_CLK] = &gcc_qmip_disp1_ahb_clk.clkr, 4412 [GCC_QMIP_DISP1_ROT_AHB_CLK] = &gcc_qmip_disp1_rot_ahb_clk.clkr, 4413 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 4414 [GCC_QMIP_DISP_ROT_AHB_CLK] = &gcc_qmip_disp_rot_ahb_clk.clkr, 4415 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 4416 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 4417 [GCC_QMIP_VIDEO_VCPU_AHB_CLK] = &gcc_qmip_video_vcpu_ahb_clk.clkr, 4418 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 4419 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 4420 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 4421 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 4422 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 4423 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 4424 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 4425 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 4426 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 4427 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 4428 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 4429 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 4430 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 4431 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 4432 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 4433 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 4434 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 4435 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 4436 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 4437 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 4438 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 4439 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 4440 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 4441 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 4442 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 4443 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 4444 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 4445 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 4446 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 4447 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 4448 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 4449 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 4450 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, 4451 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, 4452 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 4453 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 4454 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 4455 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 4456 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 4457 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 4458 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 4459 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 4460 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 4461 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 4462 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, 4463 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, 4464 [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr, 4465 [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr, 4466 [GCC_QUPV3_WRAP3_CORE_2X_CLK] = &gcc_qupv3_wrap3_core_2x_clk.clkr, 4467 [GCC_QUPV3_WRAP3_CORE_CLK] = &gcc_qupv3_wrap3_core_clk.clkr, 4468 [GCC_QUPV3_WRAP3_QSPI_CLK] = &gcc_qupv3_wrap3_qspi_clk.clkr, 4469 [GCC_QUPV3_WRAP3_S0_CLK] = &gcc_qupv3_wrap3_s0_clk.clkr, 4470 [GCC_QUPV3_WRAP3_S0_CLK_SRC] = &gcc_qupv3_wrap3_s0_clk_src.clkr, 4471 [GCC_QUPV3_WRAP3_S0_DIV_CLK_SRC] = &gcc_qupv3_wrap3_s0_div_clk_src.clkr, 4472 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 4473 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 4474 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 4475 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 4476 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 4477 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 4478 [GCC_QUPV3_WRAP_3_M_AHB_CLK] = &gcc_qupv3_wrap_3_m_ahb_clk.clkr, 4479 [GCC_QUPV3_WRAP_3_S_AHB_CLK] = &gcc_qupv3_wrap_3_s_ahb_clk.clkr, 4480 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 4481 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 4482 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 4483 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 4484 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 4485 [GCC_SGMI_CLKREF_EN] = &gcc_sgmi_clkref_en.clkr, 4486 [GCC_TSCSS_AHB_CLK] = &gcc_tscss_ahb_clk.clkr, 4487 [GCC_TSCSS_CNTR_CLK_SRC] = &gcc_tscss_cntr_clk_src.clkr, 4488 [GCC_TSCSS_ETU_CLK] = &gcc_tscss_etu_clk.clkr, 4489 [GCC_TSCSS_GLOBAL_CNTR_CLK] = &gcc_tscss_global_cntr_clk.clkr, 4490 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, 4491 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, 4492 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, 4493 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr, 4494 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr, 4495 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr, 4496 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr, 4497 [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr, 4498 [GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_rx_symbol_0_clk_src.clkr, 4499 [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr, 4500 [GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_card_rx_symbol_1_clk_src.clkr, 4501 [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr, 4502 [GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_tx_symbol_0_clk_src.clkr, 4503 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, 4504 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr, 4505 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 4506 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 4507 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 4508 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 4509 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 4510 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 4511 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 4512 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 4513 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr, 4514 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 4515 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr, 4516 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 4517 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr, 4518 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 4519 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 4520 [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr, 4521 [GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr, 4522 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr, 4523 [GCC_USB20_MOCK_UTMI_CLK_SRC] = &gcc_usb20_mock_utmi_clk_src.clkr, 4524 [GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb20_mock_utmi_postdiv_clk_src.clkr, 4525 [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr, 4526 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 4527 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 4528 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 4529 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 4530 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 4531 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 4532 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, 4533 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, 4534 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, 4535 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr, 4536 [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr, 4537 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, 4538 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 4539 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 4540 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 4541 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 4542 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 4543 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, 4544 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, 4545 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, 4546 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, 4547 [GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr, 4548 [GCC_USB_CLKREF_EN] = &gcc_usb_clkref_en.clkr, 4549 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 4550 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 4551 }; 4552 4553 static const struct qcom_reset_map gcc_sa8775p_resets[] = { 4554 [GCC_CAMERA_BCR] = { 0x32000 }, 4555 [GCC_DISPLAY1_BCR] = { 0xc7000 }, 4556 [GCC_DISPLAY_BCR] = { 0x33000 }, 4557 [GCC_EMAC0_BCR] = { 0xb6000 }, 4558 [GCC_EMAC1_BCR] = { 0xb4000 }, 4559 [GCC_GPU_BCR] = { 0x7d000 }, 4560 [GCC_MMSS_BCR] = { 0x17000 }, 4561 [GCC_PCIE_0_BCR] = { 0xa9000 }, 4562 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0xbf000 }, 4563 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0xbf008 }, 4564 [GCC_PCIE_0_PHY_BCR] = { 0xad144 }, 4565 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0xbf00c }, 4566 [GCC_PCIE_1_BCR] = { 0x77000 }, 4567 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0xae084 }, 4568 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0xae090 }, 4569 [GCC_PCIE_1_PHY_BCR] = { 0xae08c }, 4570 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0xae094 }, 4571 [GCC_PDM_BCR] = { 0x3f000 }, 4572 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x23000 }, 4573 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x24000 }, 4574 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x2a000 }, 4575 [GCC_QUPV3_WRAPPER_3_BCR] = { 0xc4000 }, 4576 [GCC_SDCC1_BCR] = { 0x20000 }, 4577 [GCC_TSCSS_BCR] = { 0x21000 }, 4578 [GCC_UFS_CARD_BCR] = { 0x81000 }, 4579 [GCC_UFS_PHY_BCR] = { 0x83000 }, 4580 [GCC_USB20_PRIM_BCR] = { 0x1c000 }, 4581 [GCC_USB2_PHY_PRIM_BCR] = { 0x5c028 }, 4582 [GCC_USB2_PHY_SEC_BCR] = { 0x5c02c }, 4583 [GCC_USB30_PRIM_BCR] = { 0x1b000 }, 4584 [GCC_USB30_SEC_BCR] = { 0x2f000 }, 4585 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x5c008 }, 4586 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x5c014 }, 4587 [GCC_USB3_PHY_PRIM_BCR] = { 0x5c000 }, 4588 [GCC_USB3_PHY_SEC_BCR] = { 0x5c00c }, 4589 [GCC_USB3_PHY_TERT_BCR] = { 0x5c030 }, 4590 [GCC_USB3_UNIPHY_MP0_BCR] = { 0x5c018 }, 4591 [GCC_USB3_UNIPHY_MP1_BCR] = { 0x5c01c }, 4592 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x5c004 }, 4593 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x5c010 }, 4594 [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x5c020 }, 4595 [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x5c024 }, 4596 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x76000 }, 4597 [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x34014, .bit = 2, .udelay = 400 }, 4598 [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x3401c, .bit = 2, .udelay = 400 }, 4599 [GCC_VIDEO_BCR] = { 0x34000 }, 4600 }; 4601 4602 static struct gdsc *gcc_sa8775p_gdscs[] = { 4603 [PCIE_0_GDSC] = &pcie_0_gdsc, 4604 [PCIE_1_GDSC] = &pcie_1_gdsc, 4605 [UFS_CARD_GDSC] = &ufs_card_gdsc, 4606 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 4607 [USB20_PRIM_GDSC] = &usb20_prim_gdsc, 4608 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 4609 [USB30_SEC_GDSC] = &usb30_sec_gdsc, 4610 [EMAC0_GDSC] = &emac0_gdsc, 4611 [EMAC1_GDSC] = &emac1_gdsc, 4612 }; 4613 4614 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 4615 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 4616 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 4617 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 4618 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 4619 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 4620 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 4621 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 4622 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 4623 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 4624 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 4625 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 4626 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 4627 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 4628 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 4629 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 4630 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 4631 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), 4632 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), 4633 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 4634 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), 4635 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src), 4636 DEFINE_RCG_DFS(gcc_qupv3_wrap3_s0_clk_src), 4637 }; 4638 4639 static const struct regmap_config gcc_sa8775p_regmap_config = { 4640 .reg_bits = 32, 4641 .reg_stride = 4, 4642 .val_bits = 32, 4643 .max_register = 0xc7018, 4644 .fast_io = true, 4645 }; 4646 4647 static const struct qcom_cc_desc gcc_sa8775p_desc = { 4648 .config = &gcc_sa8775p_regmap_config, 4649 .clks = gcc_sa8775p_clocks, 4650 .num_clks = ARRAY_SIZE(gcc_sa8775p_clocks), 4651 .resets = gcc_sa8775p_resets, 4652 .num_resets = ARRAY_SIZE(gcc_sa8775p_resets), 4653 .gdscs = gcc_sa8775p_gdscs, 4654 .num_gdscs = ARRAY_SIZE(gcc_sa8775p_gdscs), 4655 }; 4656 4657 static const struct of_device_id gcc_sa8775p_match_table[] = { 4658 { .compatible = "qcom,sa8775p-gcc" }, 4659 { } 4660 }; 4661 MODULE_DEVICE_TABLE(of, gcc_sa8775p_match_table); 4662 4663 static int gcc_sa8775p_probe(struct platform_device *pdev) 4664 { 4665 struct regmap *regmap; 4666 int ret; 4667 4668 regmap = qcom_cc_map(pdev, &gcc_sa8775p_desc); 4669 if (IS_ERR(regmap)) 4670 return PTR_ERR(regmap); 4671 4672 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 4673 ARRAY_SIZE(gcc_dfs_clocks)); 4674 if (ret) 4675 return ret; 4676 4677 /* Keep some clocks always-on */ 4678 qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_CAMERA_AHB_CLK */ 4679 qcom_branch_set_clk_en(regmap, 0x32020); /* GCC_CAMERA_XO_CLK */ 4680 qcom_branch_set_clk_en(regmap, 0xc7004); /* GCC_DISP1_AHB_CLK */ 4681 qcom_branch_set_clk_en(regmap, 0xc7018); /* GCC_DISP1_XO_CLK */ 4682 qcom_branch_set_clk_en(regmap, 0x33004); /* GCC_DISP_AHB_CLK */ 4683 qcom_branch_set_clk_en(regmap, 0x33018); /* GCC_DISP_XO_CLK */ 4684 qcom_branch_set_clk_en(regmap, 0x7d004); /* GCC_GPU_CFG_AHB_CLK */ 4685 qcom_branch_set_clk_en(regmap, 0x34004); /* GCC_VIDEO_AHB_CLK */ 4686 qcom_branch_set_clk_en(regmap, 0x34024); /* GCC_VIDEO_XO_CLK */ 4687 4688 /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ 4689 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); 4690 4691 return qcom_cc_really_probe(&pdev->dev, &gcc_sa8775p_desc, regmap); 4692 } 4693 4694 static struct platform_driver gcc_sa8775p_driver = { 4695 .probe = gcc_sa8775p_probe, 4696 .driver = { 4697 .name = "sa8775p-gcc", 4698 .of_match_table = gcc_sa8775p_match_table, 4699 }, 4700 }; 4701 4702 static int __init gcc_sa8775p_init(void) 4703 { 4704 return platform_driver_register(&gcc_sa8775p_driver); 4705 } 4706 core_initcall(gcc_sa8775p_init); 4707 4708 static void __exit gcc_sa8775p_exit(void) 4709 { 4710 platform_driver_unregister(&gcc_sa8775p_driver); 4711 } 4712 module_exit(gcc_sa8775p_exit); 4713 4714 MODULE_DESCRIPTION("Qualcomm SA8775P GCC driver"); 4715 MODULE_LICENSE("GPL"); 4716