1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/of.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,qcs8300-gcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-pll.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "clk-regmap-divider.h" 20 #include "clk-regmap-mux.h" 21 #include "clk-regmap-phy-mux.h" 22 #include "common.h" 23 #include "gdsc.h" 24 #include "reset.h" 25 26 enum { 27 DT_BI_TCXO, 28 DT_SLEEP_CLK, 29 DT_PCIE_0_PIPE_CLK, 30 DT_PCIE_1_PIPE_CLK, 31 DT_PCIE_PHY_AUX_CLK, 32 DT_RXC0_REF_CLK, 33 DT_UFS_PHY_RX_SYMBOL_0_CLK, 34 DT_UFS_PHY_RX_SYMBOL_1_CLK, 35 DT_UFS_PHY_TX_SYMBOL_0_CLK, 36 DT_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK, 37 }; 38 39 enum { 40 P_BI_TCXO, 41 P_GCC_GPLL0_OUT_EVEN, 42 P_GCC_GPLL0_OUT_MAIN, 43 P_GCC_GPLL1_OUT_MAIN, 44 P_GCC_GPLL4_OUT_MAIN, 45 P_GCC_GPLL7_OUT_MAIN, 46 P_GCC_GPLL9_OUT_MAIN, 47 P_PCIE_0_PIPE_CLK, 48 P_PCIE_1_PIPE_CLK, 49 P_PCIE_PHY_AUX_CLK, 50 P_RXC0_REF_CLK, 51 P_SLEEP_CLK, 52 P_UFS_PHY_RX_SYMBOL_0_CLK, 53 P_UFS_PHY_RX_SYMBOL_1_CLK, 54 P_UFS_PHY_TX_SYMBOL_0_CLK, 55 P_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK, 56 }; 57 58 static struct clk_alpha_pll gcc_gpll0 = { 59 .offset = 0x0, 60 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 61 .clkr = { 62 .enable_reg = 0x4b028, 63 .enable_mask = BIT(0), 64 .hw.init = &(const struct clk_init_data) { 65 .name = "gcc_gpll0", 66 .parent_data = &(const struct clk_parent_data) { 67 .index = DT_BI_TCXO, 68 }, 69 .num_parents = 1, 70 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 71 }, 72 }, 73 }; 74 75 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 76 { 0x1, 2 }, 77 { } 78 }; 79 80 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 81 .offset = 0x0, 82 .post_div_shift = 10, 83 .post_div_table = post_div_table_gcc_gpll0_out_even, 84 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 85 .width = 4, 86 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 87 .clkr.hw.init = &(const struct clk_init_data) { 88 .name = "gcc_gpll0_out_even", 89 .parent_hws = (const struct clk_hw*[]) { 90 &gcc_gpll0.clkr.hw, 91 }, 92 .num_parents = 1, 93 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, 94 }, 95 }; 96 97 static struct clk_alpha_pll gcc_gpll1 = { 98 .offset = 0x1000, 99 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 100 .clkr = { 101 .enable_reg = 0x4b028, 102 .enable_mask = BIT(1), 103 .hw.init = &(const struct clk_init_data) { 104 .name = "gcc_gpll1", 105 .parent_data = &(const struct clk_parent_data) { 106 .index = DT_BI_TCXO, 107 }, 108 .num_parents = 1, 109 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 110 }, 111 }, 112 }; 113 114 static struct clk_alpha_pll gcc_gpll4 = { 115 .offset = 0x4000, 116 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 117 .clkr = { 118 .enable_reg = 0x4b028, 119 .enable_mask = BIT(4), 120 .hw.init = &(const struct clk_init_data) { 121 .name = "gcc_gpll4", 122 .parent_data = &(const struct clk_parent_data) { 123 .index = DT_BI_TCXO, 124 }, 125 .num_parents = 1, 126 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 127 }, 128 }, 129 }; 130 131 static struct clk_alpha_pll gcc_gpll7 = { 132 .offset = 0x7000, 133 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 134 .clkr = { 135 .enable_reg = 0x4b028, 136 .enable_mask = BIT(7), 137 .hw.init = &(const struct clk_init_data) { 138 .name = "gcc_gpll7", 139 .parent_data = &(const struct clk_parent_data) { 140 .index = DT_BI_TCXO, 141 }, 142 .num_parents = 1, 143 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 144 }, 145 }, 146 }; 147 148 static struct clk_alpha_pll gcc_gpll9 = { 149 .offset = 0x9000, 150 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 151 .clkr = { 152 .enable_reg = 0x4b028, 153 .enable_mask = BIT(9), 154 .hw.init = &(const struct clk_init_data) { 155 .name = "gcc_gpll9", 156 .parent_data = &(const struct clk_parent_data) { 157 .index = DT_BI_TCXO, 158 }, 159 .num_parents = 1, 160 .ops = &clk_alpha_pll_fixed_lucid_evo_ops, 161 }, 162 }, 163 }; 164 165 static const struct parent_map gcc_parent_map_0[] = { 166 { P_BI_TCXO, 0 }, 167 { P_GCC_GPLL0_OUT_MAIN, 1 }, 168 { P_GCC_GPLL0_OUT_EVEN, 6 }, 169 }; 170 171 static const struct clk_parent_data gcc_parent_data_0[] = { 172 { .index = DT_BI_TCXO }, 173 { .hw = &gcc_gpll0.clkr.hw }, 174 { .hw = &gcc_gpll0_out_even.clkr.hw }, 175 }; 176 177 static const struct parent_map gcc_parent_map_1[] = { 178 { P_BI_TCXO, 0 }, 179 { P_GCC_GPLL0_OUT_MAIN, 1 }, 180 { P_SLEEP_CLK, 5 }, 181 { P_GCC_GPLL0_OUT_EVEN, 6 }, 182 }; 183 184 static const struct clk_parent_data gcc_parent_data_1[] = { 185 { .index = DT_BI_TCXO }, 186 { .hw = &gcc_gpll0.clkr.hw }, 187 { .index = DT_SLEEP_CLK }, 188 { .hw = &gcc_gpll0_out_even.clkr.hw }, 189 }; 190 191 static const struct parent_map gcc_parent_map_2[] = { 192 { P_BI_TCXO, 0 }, 193 { P_SLEEP_CLK, 5 }, 194 }; 195 196 static const struct clk_parent_data gcc_parent_data_2[] = { 197 { .index = DT_BI_TCXO }, 198 { .index = DT_SLEEP_CLK }, 199 }; 200 201 static const struct parent_map gcc_parent_map_3[] = { 202 { P_BI_TCXO, 0 }, 203 { P_GCC_GPLL0_OUT_MAIN, 1 }, 204 { P_GCC_GPLL1_OUT_MAIN, 4 }, 205 { P_GCC_GPLL4_OUT_MAIN, 5 }, 206 { P_GCC_GPLL0_OUT_EVEN, 6 }, 207 }; 208 209 static const struct clk_parent_data gcc_parent_data_3[] = { 210 { .index = DT_BI_TCXO }, 211 { .hw = &gcc_gpll0.clkr.hw }, 212 { .hw = &gcc_gpll1.clkr.hw }, 213 { .hw = &gcc_gpll4.clkr.hw }, 214 { .hw = &gcc_gpll0_out_even.clkr.hw }, 215 }; 216 217 static const struct parent_map gcc_parent_map_4[] = { 218 { P_BI_TCXO, 0 }, 219 { P_GCC_GPLL0_OUT_MAIN, 1 }, 220 { P_GCC_GPLL4_OUT_MAIN, 5 }, 221 { P_GCC_GPLL0_OUT_EVEN, 6 }, 222 }; 223 224 static const struct clk_parent_data gcc_parent_data_4[] = { 225 { .index = DT_BI_TCXO }, 226 { .hw = &gcc_gpll0.clkr.hw }, 227 { .hw = &gcc_gpll4.clkr.hw }, 228 { .hw = &gcc_gpll0_out_even.clkr.hw }, 229 }; 230 231 static const struct parent_map gcc_parent_map_5[] = { 232 { P_BI_TCXO, 0 }, 233 }; 234 235 static const struct clk_parent_data gcc_parent_data_5[] = { 236 { .index = DT_BI_TCXO }, 237 }; 238 239 static const struct parent_map gcc_parent_map_6[] = { 240 { P_BI_TCXO, 0 }, 241 { P_GCC_GPLL7_OUT_MAIN, 2 }, 242 { P_GCC_GPLL4_OUT_MAIN, 5 }, 243 { P_GCC_GPLL0_OUT_EVEN, 6 }, 244 }; 245 246 static const struct clk_parent_data gcc_parent_data_6[] = { 247 { .index = DT_BI_TCXO }, 248 { .hw = &gcc_gpll7.clkr.hw }, 249 { .hw = &gcc_gpll4.clkr.hw }, 250 { .hw = &gcc_gpll0_out_even.clkr.hw }, 251 }; 252 253 static const struct parent_map gcc_parent_map_7[] = { 254 { P_BI_TCXO, 0 }, 255 { P_GCC_GPLL7_OUT_MAIN, 2 }, 256 { P_RXC0_REF_CLK, 3 }, 257 { P_GCC_GPLL0_OUT_EVEN, 6 }, 258 }; 259 260 static const struct clk_parent_data gcc_parent_data_7[] = { 261 { .index = DT_BI_TCXO }, 262 { .hw = &gcc_gpll7.clkr.hw }, 263 { .index = DT_RXC0_REF_CLK }, 264 { .hw = &gcc_gpll0_out_even.clkr.hw }, 265 }; 266 267 static const struct parent_map gcc_parent_map_8[] = { 268 { P_PCIE_PHY_AUX_CLK, 1 }, 269 { P_BI_TCXO, 2 }, 270 }; 271 272 static const struct clk_parent_data gcc_parent_data_8[] = { 273 { .index = DT_PCIE_PHY_AUX_CLK }, 274 { .index = DT_BI_TCXO }, 275 }; 276 277 static const struct parent_map gcc_parent_map_10[] = { 278 { P_PCIE_PHY_AUX_CLK, 1 }, 279 { P_BI_TCXO, 2 }, 280 }; 281 282 static const struct clk_parent_data gcc_parent_data_10[] = { 283 { .index = DT_PCIE_PHY_AUX_CLK }, 284 { .index = DT_BI_TCXO }, 285 }; 286 287 static const struct parent_map gcc_parent_map_12[] = { 288 { P_BI_TCXO, 0 }, 289 { P_GCC_GPLL0_OUT_MAIN, 1 }, 290 { P_GCC_GPLL9_OUT_MAIN, 2 }, 291 { P_GCC_GPLL4_OUT_MAIN, 5 }, 292 { P_GCC_GPLL0_OUT_EVEN, 6 }, 293 }; 294 295 static const struct clk_parent_data gcc_parent_data_12[] = { 296 { .index = DT_BI_TCXO }, 297 { .hw = &gcc_gpll0.clkr.hw }, 298 { .hw = &gcc_gpll9.clkr.hw }, 299 { .hw = &gcc_gpll4.clkr.hw }, 300 { .hw = &gcc_gpll0_out_even.clkr.hw }, 301 }; 302 303 static const struct parent_map gcc_parent_map_13[] = { 304 { P_BI_TCXO, 0 }, 305 { P_GCC_GPLL0_OUT_MAIN, 1 }, 306 }; 307 308 static const struct clk_parent_data gcc_parent_data_13[] = { 309 { .index = DT_BI_TCXO }, 310 { .hw = &gcc_gpll0.clkr.hw }, 311 }; 312 313 static const struct parent_map gcc_parent_map_14[] = { 314 { P_BI_TCXO, 0 }, 315 { P_GCC_GPLL0_OUT_MAIN, 1 }, 316 { P_GCC_GPLL4_OUT_MAIN, 3 }, 317 { P_GCC_GPLL0_OUT_EVEN, 6 }, 318 }; 319 320 static const struct clk_parent_data gcc_parent_data_14[] = { 321 { .index = DT_BI_TCXO }, 322 { .hw = &gcc_gpll0.clkr.hw }, 323 { .hw = &gcc_gpll4.clkr.hw }, 324 { .hw = &gcc_gpll0_out_even.clkr.hw }, 325 }; 326 327 static const struct parent_map gcc_parent_map_15[] = { 328 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 }, 329 { P_BI_TCXO, 2 }, 330 }; 331 332 static const struct clk_parent_data gcc_parent_data_15[] = { 333 { .index = DT_UFS_PHY_RX_SYMBOL_0_CLK }, 334 { .index = DT_BI_TCXO }, 335 }; 336 337 static const struct parent_map gcc_parent_map_16[] = { 338 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 }, 339 { P_BI_TCXO, 2 }, 340 }; 341 342 static const struct clk_parent_data gcc_parent_data_16[] = { 343 { .index = DT_UFS_PHY_RX_SYMBOL_1_CLK }, 344 { .index = DT_BI_TCXO }, 345 }; 346 347 static const struct parent_map gcc_parent_map_17[] = { 348 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 }, 349 { P_BI_TCXO, 2 }, 350 }; 351 352 static const struct clk_parent_data gcc_parent_data_17[] = { 353 { .index = DT_UFS_PHY_TX_SYMBOL_0_CLK }, 354 { .index = DT_BI_TCXO }, 355 }; 356 357 static const struct parent_map gcc_parent_map_18[] = { 358 { P_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK, 0 }, 359 { P_BI_TCXO, 2 }, 360 }; 361 362 static const struct clk_parent_data gcc_parent_data_18[] = { 363 { .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK }, 364 { .index = DT_BI_TCXO }, 365 }; 366 367 static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = { 368 .reg = 0xa9074, 369 .shift = 0, 370 .width = 2, 371 .parent_map = gcc_parent_map_8, 372 .clkr = { 373 .hw.init = &(const struct clk_init_data) { 374 .name = "gcc_pcie_0_phy_aux_clk_src", 375 .parent_data = gcc_parent_data_8, 376 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 377 .ops = &clk_regmap_mux_closest_ops, 378 }, 379 }, 380 }; 381 382 static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { 383 .reg = 0xa906c, 384 .clkr = { 385 .hw.init = &(const struct clk_init_data) { 386 .name = "gcc_pcie_0_pipe_clk_src", 387 .parent_data = &(const struct clk_parent_data) { 388 .index = DT_PCIE_0_PIPE_CLK, 389 }, 390 .num_parents = 1, 391 .ops = &clk_regmap_phy_mux_ops, 392 }, 393 }, 394 }; 395 396 static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = { 397 .reg = 0x77074, 398 .shift = 0, 399 .width = 2, 400 .parent_map = gcc_parent_map_10, 401 .clkr = { 402 .hw.init = &(const struct clk_init_data) { 403 .name = "gcc_pcie_1_phy_aux_clk_src", 404 .parent_data = gcc_parent_data_10, 405 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 406 .ops = &clk_regmap_mux_closest_ops, 407 }, 408 }, 409 }; 410 411 static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = { 412 .reg = 0x7706c, 413 .clkr = { 414 .hw.init = &(const struct clk_init_data) { 415 .name = "gcc_pcie_1_pipe_clk_src", 416 .parent_data = &(const struct clk_parent_data) { 417 .index = DT_PCIE_1_PIPE_CLK, 418 }, 419 .num_parents = 1, 420 .ops = &clk_regmap_phy_mux_ops, 421 }, 422 }, 423 }; 424 425 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = { 426 .reg = 0x83060, 427 .shift = 0, 428 .width = 2, 429 .parent_map = gcc_parent_map_15, 430 .clkr = { 431 .hw.init = &(const struct clk_init_data) { 432 .name = "gcc_ufs_phy_rx_symbol_0_clk_src", 433 .parent_data = gcc_parent_data_15, 434 .num_parents = ARRAY_SIZE(gcc_parent_data_15), 435 .ops = &clk_regmap_mux_closest_ops, 436 }, 437 }, 438 }; 439 440 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = { 441 .reg = 0x830d0, 442 .shift = 0, 443 .width = 2, 444 .parent_map = gcc_parent_map_16, 445 .clkr = { 446 .hw.init = &(const struct clk_init_data) { 447 .name = "gcc_ufs_phy_rx_symbol_1_clk_src", 448 .parent_data = gcc_parent_data_16, 449 .num_parents = ARRAY_SIZE(gcc_parent_data_16), 450 .ops = &clk_regmap_mux_closest_ops, 451 }, 452 }, 453 }; 454 455 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = { 456 .reg = 0x83050, 457 .shift = 0, 458 .width = 2, 459 .parent_map = gcc_parent_map_17, 460 .clkr = { 461 .hw.init = &(const struct clk_init_data) { 462 .name = "gcc_ufs_phy_tx_symbol_0_clk_src", 463 .parent_data = gcc_parent_data_17, 464 .num_parents = ARRAY_SIZE(gcc_parent_data_17), 465 .ops = &clk_regmap_mux_closest_ops, 466 }, 467 }, 468 }; 469 470 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 471 .reg = 0x1b068, 472 .shift = 0, 473 .width = 2, 474 .parent_map = gcc_parent_map_18, 475 .clkr = { 476 .hw.init = &(const struct clk_init_data) { 477 .name = "gcc_usb3_prim_phy_pipe_clk_src", 478 .parent_data = gcc_parent_data_18, 479 .num_parents = ARRAY_SIZE(gcc_parent_data_18), 480 .ops = &clk_regmap_mux_closest_ops, 481 }, 482 }, 483 }; 484 485 static const struct freq_tbl ftbl_gcc_emac0_phy_aux_clk_src[] = { 486 F(19200000, P_BI_TCXO, 1, 0, 0), 487 { } 488 }; 489 490 static struct clk_rcg2 gcc_emac0_phy_aux_clk_src = { 491 .cmd_rcgr = 0xb6028, 492 .mnd_width = 0, 493 .hid_width = 5, 494 .parent_map = gcc_parent_map_2, 495 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 496 .clkr.hw.init = &(const struct clk_init_data) { 497 .name = "gcc_emac0_phy_aux_clk_src", 498 .parent_data = gcc_parent_data_2, 499 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 500 .flags = CLK_SET_RATE_PARENT, 501 .ops = &clk_rcg2_shared_ops, 502 }, 503 }; 504 505 static const struct freq_tbl ftbl_gcc_emac0_ptp_clk_src[] = { 506 F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0), 507 F(230400000, P_GCC_GPLL4_OUT_MAIN, 3.5, 0, 0), 508 { } 509 }; 510 511 static struct clk_rcg2 gcc_emac0_ptp_clk_src = { 512 .cmd_rcgr = 0xb6060, 513 .mnd_width = 16, 514 .hid_width = 5, 515 .parent_map = gcc_parent_map_6, 516 .freq_tbl = ftbl_gcc_emac0_ptp_clk_src, 517 .clkr.hw.init = &(const struct clk_init_data) { 518 .name = "gcc_emac0_ptp_clk_src", 519 .parent_data = gcc_parent_data_6, 520 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 521 .flags = CLK_SET_RATE_PARENT, 522 .ops = &clk_rcg2_shared_ops, 523 }, 524 }; 525 526 static const struct freq_tbl ftbl_gcc_emac0_rgmii_clk_src[] = { 527 F(5000000, P_GCC_GPLL0_OUT_EVEN, 10, 1, 6), 528 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 529 F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0), 530 F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0), 531 { } 532 }; 533 534 static struct clk_rcg2 gcc_emac0_rgmii_clk_src = { 535 .cmd_rcgr = 0xb6048, 536 .mnd_width = 16, 537 .hid_width = 5, 538 .parent_map = gcc_parent_map_7, 539 .freq_tbl = ftbl_gcc_emac0_rgmii_clk_src, 540 .clkr.hw.init = &(const struct clk_init_data) { 541 .name = "gcc_emac0_rgmii_clk_src", 542 .parent_data = gcc_parent_data_7, 543 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 544 .flags = CLK_SET_RATE_PARENT, 545 .ops = &clk_rcg2_shared_ops, 546 }, 547 }; 548 549 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 550 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 551 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 552 { } 553 }; 554 555 static struct clk_rcg2 gcc_gp1_clk_src = { 556 .cmd_rcgr = 0x70004, 557 .mnd_width = 16, 558 .hid_width = 5, 559 .parent_map = gcc_parent_map_1, 560 .freq_tbl = ftbl_gcc_gp1_clk_src, 561 .clkr.hw.init = &(const struct clk_init_data) { 562 .name = "gcc_gp1_clk_src", 563 .parent_data = gcc_parent_data_1, 564 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 565 .flags = CLK_SET_RATE_PARENT, 566 .ops = &clk_rcg2_shared_ops, 567 }, 568 }; 569 570 static struct clk_rcg2 gcc_gp2_clk_src = { 571 .cmd_rcgr = 0x71004, 572 .mnd_width = 16, 573 .hid_width = 5, 574 .parent_map = gcc_parent_map_1, 575 .freq_tbl = ftbl_gcc_gp1_clk_src, 576 .clkr.hw.init = &(const struct clk_init_data) { 577 .name = "gcc_gp2_clk_src", 578 .parent_data = gcc_parent_data_1, 579 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 580 .flags = CLK_SET_RATE_PARENT, 581 .ops = &clk_rcg2_shared_ops, 582 }, 583 }; 584 585 static struct clk_rcg2 gcc_gp3_clk_src = { 586 .cmd_rcgr = 0x62004, 587 .mnd_width = 16, 588 .hid_width = 5, 589 .parent_map = gcc_parent_map_1, 590 .freq_tbl = ftbl_gcc_gp1_clk_src, 591 .clkr.hw.init = &(const struct clk_init_data) { 592 .name = "gcc_gp3_clk_src", 593 .parent_data = gcc_parent_data_1, 594 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 595 .flags = CLK_SET_RATE_PARENT, 596 .ops = &clk_rcg2_shared_ops, 597 }, 598 }; 599 600 static struct clk_rcg2 gcc_gp4_clk_src = { 601 .cmd_rcgr = 0x1e004, 602 .mnd_width = 16, 603 .hid_width = 5, 604 .parent_map = gcc_parent_map_1, 605 .freq_tbl = ftbl_gcc_gp1_clk_src, 606 .clkr.hw.init = &(const struct clk_init_data) { 607 .name = "gcc_gp4_clk_src", 608 .parent_data = gcc_parent_data_1, 609 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 610 .flags = CLK_SET_RATE_PARENT, 611 .ops = &clk_rcg2_shared_ops, 612 }, 613 }; 614 615 static struct clk_rcg2 gcc_gp5_clk_src = { 616 .cmd_rcgr = 0x1f004, 617 .mnd_width = 16, 618 .hid_width = 5, 619 .parent_map = gcc_parent_map_1, 620 .freq_tbl = ftbl_gcc_gp1_clk_src, 621 .clkr.hw.init = &(const struct clk_init_data) { 622 .name = "gcc_gp5_clk_src", 623 .parent_data = gcc_parent_data_1, 624 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 625 .flags = CLK_SET_RATE_PARENT, 626 .ops = &clk_rcg2_shared_ops, 627 }, 628 }; 629 630 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 631 .cmd_rcgr = 0xa9078, 632 .mnd_width = 16, 633 .hid_width = 5, 634 .parent_map = gcc_parent_map_2, 635 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 636 .clkr.hw.init = &(const struct clk_init_data) { 637 .name = "gcc_pcie_0_aux_clk_src", 638 .parent_data = gcc_parent_data_2, 639 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 640 .flags = CLK_SET_RATE_PARENT, 641 .ops = &clk_rcg2_shared_ops, 642 }, 643 }; 644 645 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 646 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 647 { } 648 }; 649 650 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 651 .cmd_rcgr = 0xa9054, 652 .mnd_width = 0, 653 .hid_width = 5, 654 .parent_map = gcc_parent_map_0, 655 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 656 .clkr.hw.init = &(const struct clk_init_data) { 657 .name = "gcc_pcie_0_phy_rchng_clk_src", 658 .parent_data = gcc_parent_data_0, 659 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 660 .flags = CLK_SET_RATE_PARENT, 661 .ops = &clk_rcg2_shared_ops, 662 }, 663 }; 664 665 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 666 .cmd_rcgr = 0x77078, 667 .mnd_width = 16, 668 .hid_width = 5, 669 .parent_map = gcc_parent_map_2, 670 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 671 .clkr.hw.init = &(const struct clk_init_data) { 672 .name = "gcc_pcie_1_aux_clk_src", 673 .parent_data = gcc_parent_data_2, 674 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 675 .flags = CLK_SET_RATE_PARENT, 676 .ops = &clk_rcg2_shared_ops, 677 }, 678 }; 679 680 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { 681 .cmd_rcgr = 0x77054, 682 .mnd_width = 0, 683 .hid_width = 5, 684 .parent_map = gcc_parent_map_0, 685 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 686 .clkr.hw.init = &(const struct clk_init_data) { 687 .name = "gcc_pcie_1_phy_rchng_clk_src", 688 .parent_data = gcc_parent_data_0, 689 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 690 .flags = CLK_SET_RATE_PARENT, 691 .ops = &clk_rcg2_shared_ops, 692 }, 693 }; 694 695 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 696 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 697 { } 698 }; 699 700 static struct clk_rcg2 gcc_pdm2_clk_src = { 701 .cmd_rcgr = 0x3f010, 702 .mnd_width = 0, 703 .hid_width = 5, 704 .parent_map = gcc_parent_map_0, 705 .freq_tbl = ftbl_gcc_pdm2_clk_src, 706 .clkr.hw.init = &(const struct clk_init_data) { 707 .name = "gcc_pdm2_clk_src", 708 .parent_data = gcc_parent_data_0, 709 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 710 .flags = CLK_SET_RATE_PARENT, 711 .ops = &clk_rcg2_shared_ops, 712 }, 713 }; 714 715 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 716 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 717 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 718 F(19200000, P_BI_TCXO, 1, 0, 0), 719 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 720 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 721 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 722 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 723 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 724 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 725 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 726 { } 727 }; 728 729 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 730 .name = "gcc_qupv3_wrap0_s0_clk_src", 731 .parent_data = gcc_parent_data_0, 732 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 733 .flags = CLK_SET_RATE_PARENT, 734 .ops = &clk_rcg2_shared_ops, 735 }; 736 737 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 738 .cmd_rcgr = 0x23154, 739 .mnd_width = 16, 740 .hid_width = 5, 741 .parent_map = gcc_parent_map_0, 742 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 743 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 744 }; 745 746 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 747 .name = "gcc_qupv3_wrap0_s1_clk_src", 748 .parent_data = gcc_parent_data_0, 749 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 750 .flags = CLK_SET_RATE_PARENT, 751 .ops = &clk_rcg2_shared_ops, 752 }; 753 754 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 755 .cmd_rcgr = 0x23288, 756 .mnd_width = 16, 757 .hid_width = 5, 758 .parent_map = gcc_parent_map_0, 759 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 760 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 761 }; 762 763 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = { 764 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 765 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 766 F(19200000, P_BI_TCXO, 1, 0, 0), 767 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 768 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 769 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 770 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 771 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 772 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 773 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 774 { } 775 }; 776 777 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 778 .name = "gcc_qupv3_wrap0_s2_clk_src", 779 .parent_data = gcc_parent_data_0, 780 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 781 .flags = CLK_SET_RATE_PARENT, 782 .ops = &clk_rcg2_shared_ops, 783 }; 784 785 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 786 .cmd_rcgr = 0x233bc, 787 .mnd_width = 16, 788 .hid_width = 5, 789 .parent_map = gcc_parent_map_0, 790 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 791 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 792 }; 793 794 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 795 .name = "gcc_qupv3_wrap0_s3_clk_src", 796 .parent_data = gcc_parent_data_0, 797 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 798 .flags = CLK_SET_RATE_PARENT, 799 .ops = &clk_rcg2_shared_ops, 800 }; 801 802 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 803 .cmd_rcgr = 0x234f0, 804 .mnd_width = 16, 805 .hid_width = 5, 806 .parent_map = gcc_parent_map_0, 807 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 808 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 809 }; 810 811 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 812 .name = "gcc_qupv3_wrap0_s4_clk_src", 813 .parent_data = gcc_parent_data_4, 814 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 815 .flags = CLK_SET_RATE_PARENT, 816 .ops = &clk_rcg2_shared_ops, 817 }; 818 819 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 820 .cmd_rcgr = 0x23624, 821 .mnd_width = 16, 822 .hid_width = 5, 823 .parent_map = gcc_parent_map_4, 824 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 825 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 826 }; 827 828 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 829 .name = "gcc_qupv3_wrap0_s5_clk_src", 830 .parent_data = gcc_parent_data_0, 831 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 832 .flags = CLK_SET_RATE_PARENT, 833 .ops = &clk_rcg2_shared_ops, 834 }; 835 836 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 837 .cmd_rcgr = 0x23758, 838 .mnd_width = 16, 839 .hid_width = 5, 840 .parent_map = gcc_parent_map_0, 841 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 842 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 843 }; 844 845 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 846 .name = "gcc_qupv3_wrap0_s6_clk_src", 847 .parent_data = gcc_parent_data_0, 848 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 849 .flags = CLK_SET_RATE_PARENT, 850 .ops = &clk_rcg2_shared_ops, 851 }; 852 853 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 854 .cmd_rcgr = 0x2388c, 855 .mnd_width = 16, 856 .hid_width = 5, 857 .parent_map = gcc_parent_map_0, 858 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 859 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 860 }; 861 862 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 863 .name = "gcc_qupv3_wrap0_s7_clk_src", 864 .parent_data = gcc_parent_data_0, 865 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 866 .flags = CLK_SET_RATE_PARENT, 867 .ops = &clk_rcg2_shared_ops, 868 }; 869 870 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 871 .cmd_rcgr = 0x239c0, 872 .mnd_width = 16, 873 .hid_width = 5, 874 .parent_map = gcc_parent_map_0, 875 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 876 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 877 }; 878 879 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 880 .name = "gcc_qupv3_wrap1_s0_clk_src", 881 .parent_data = gcc_parent_data_0, 882 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 883 .flags = CLK_SET_RATE_PARENT, 884 .ops = &clk_rcg2_shared_ops, 885 }; 886 887 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 888 .cmd_rcgr = 0x24154, 889 .mnd_width = 16, 890 .hid_width = 5, 891 .parent_map = gcc_parent_map_0, 892 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 893 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 894 }; 895 896 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 897 .name = "gcc_qupv3_wrap1_s1_clk_src", 898 .parent_data = gcc_parent_data_0, 899 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 900 .flags = CLK_SET_RATE_PARENT, 901 .ops = &clk_rcg2_shared_ops, 902 }; 903 904 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 905 .cmd_rcgr = 0x24288, 906 .mnd_width = 16, 907 .hid_width = 5, 908 .parent_map = gcc_parent_map_0, 909 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 910 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 911 }; 912 913 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 914 .name = "gcc_qupv3_wrap1_s2_clk_src", 915 .parent_data = gcc_parent_data_0, 916 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 917 .flags = CLK_SET_RATE_PARENT, 918 .ops = &clk_rcg2_shared_ops, 919 }; 920 921 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 922 .cmd_rcgr = 0x243bc, 923 .mnd_width = 16, 924 .hid_width = 5, 925 .parent_map = gcc_parent_map_0, 926 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 927 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 928 }; 929 930 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 931 .name = "gcc_qupv3_wrap1_s3_clk_src", 932 .parent_data = gcc_parent_data_0, 933 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 934 .flags = CLK_SET_RATE_PARENT, 935 .ops = &clk_rcg2_shared_ops, 936 }; 937 938 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 939 .cmd_rcgr = 0x244f0, 940 .mnd_width = 16, 941 .hid_width = 5, 942 .parent_map = gcc_parent_map_0, 943 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 944 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 945 }; 946 947 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 948 .name = "gcc_qupv3_wrap1_s4_clk_src", 949 .parent_data = gcc_parent_data_4, 950 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 951 .flags = CLK_SET_RATE_PARENT, 952 .ops = &clk_rcg2_shared_ops, 953 }; 954 955 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 956 .cmd_rcgr = 0x24624, 957 .mnd_width = 16, 958 .hid_width = 5, 959 .parent_map = gcc_parent_map_4, 960 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 961 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 962 }; 963 964 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 965 .name = "gcc_qupv3_wrap1_s5_clk_src", 966 .parent_data = gcc_parent_data_0, 967 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 968 .flags = CLK_SET_RATE_PARENT, 969 .ops = &clk_rcg2_shared_ops, 970 }; 971 972 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 973 .cmd_rcgr = 0x24758, 974 .mnd_width = 16, 975 .hid_width = 5, 976 .parent_map = gcc_parent_map_0, 977 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 978 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 979 }; 980 981 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 982 .name = "gcc_qupv3_wrap1_s6_clk_src", 983 .parent_data = gcc_parent_data_0, 984 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 985 .flags = CLK_SET_RATE_PARENT, 986 .ops = &clk_rcg2_shared_ops, 987 }; 988 989 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 990 .cmd_rcgr = 0x2488c, 991 .mnd_width = 16, 992 .hid_width = 5, 993 .parent_map = gcc_parent_map_0, 994 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 995 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 996 }; 997 998 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 999 .name = "gcc_qupv3_wrap1_s7_clk_src", 1000 .parent_data = gcc_parent_data_0, 1001 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1002 .flags = CLK_SET_RATE_PARENT, 1003 .ops = &clk_rcg2_shared_ops, 1004 }; 1005 1006 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 1007 .cmd_rcgr = 0x249c0, 1008 .mnd_width = 16, 1009 .hid_width = 5, 1010 .parent_map = gcc_parent_map_0, 1011 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, 1012 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 1013 }; 1014 1015 static const struct freq_tbl ftbl_gcc_qupv3_wrap3_s0_clk_src[] = { 1016 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 1017 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 1018 F(19200000, P_BI_TCXO, 1, 0, 0), 1019 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 1020 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 1021 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 1022 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 1023 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1024 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 1025 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 1026 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 1027 F(403200000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 1028 { } 1029 }; 1030 1031 static struct clk_init_data gcc_qupv3_wrap3_s0_clk_src_init = { 1032 .name = "gcc_qupv3_wrap3_s0_clk_src", 1033 .parent_data = gcc_parent_data_3, 1034 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1035 .flags = CLK_SET_RATE_PARENT, 1036 .ops = &clk_rcg2_shared_ops, 1037 }; 1038 1039 static struct clk_rcg2 gcc_qupv3_wrap3_s0_clk_src = { 1040 .cmd_rcgr = 0xc4158, 1041 .mnd_width = 16, 1042 .hid_width = 5, 1043 .parent_map = gcc_parent_map_3, 1044 .freq_tbl = ftbl_gcc_qupv3_wrap3_s0_clk_src, 1045 .clkr.hw.init = &gcc_qupv3_wrap3_s0_clk_src_init, 1046 }; 1047 1048 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 1049 F(144000, P_BI_TCXO, 16, 3, 25), 1050 F(400000, P_BI_TCXO, 12, 1, 4), 1051 F(19200000, P_BI_TCXO, 1, 0, 0), 1052 F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3), 1053 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1054 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 1055 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1056 F(192000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), 1057 F(384000000, P_GCC_GPLL9_OUT_MAIN, 2, 0, 0), 1058 { } 1059 }; 1060 1061 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 1062 .cmd_rcgr = 0x20014, 1063 .mnd_width = 8, 1064 .hid_width = 5, 1065 .parent_map = gcc_parent_map_12, 1066 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 1067 .clkr.hw.init = &(const struct clk_init_data) { 1068 .name = "gcc_sdcc1_apps_clk_src", 1069 .parent_data = gcc_parent_data_12, 1070 .num_parents = ARRAY_SIZE(gcc_parent_data_12), 1071 .flags = CLK_SET_RATE_PARENT, 1072 .ops = &clk_rcg2_floor_ops, 1073 }, 1074 }; 1075 1076 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 1077 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 1078 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 1079 { } 1080 }; 1081 1082 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 1083 .cmd_rcgr = 0x2002c, 1084 .mnd_width = 0, 1085 .hid_width = 5, 1086 .parent_map = gcc_parent_map_13, 1087 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 1088 .clkr.hw.init = &(const struct clk_init_data) { 1089 .name = "gcc_sdcc1_ice_core_clk_src", 1090 .parent_data = gcc_parent_data_13, 1091 .num_parents = ARRAY_SIZE(gcc_parent_data_13), 1092 .flags = CLK_SET_RATE_PARENT, 1093 .ops = &clk_rcg2_floor_ops, 1094 }, 1095 }; 1096 1097 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 1098 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1099 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1100 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 1101 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 1102 { } 1103 }; 1104 1105 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1106 .cmd_rcgr = 0x8302c, 1107 .mnd_width = 8, 1108 .hid_width = 5, 1109 .parent_map = gcc_parent_map_0, 1110 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 1111 .clkr.hw.init = &(const struct clk_init_data) { 1112 .name = "gcc_ufs_phy_axi_clk_src", 1113 .parent_data = gcc_parent_data_0, 1114 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1115 .flags = CLK_SET_RATE_PARENT, 1116 .ops = &clk_rcg2_shared_ops, 1117 }, 1118 }; 1119 1120 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1121 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1122 F(201600000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), 1123 F(403200000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 1124 { } 1125 }; 1126 1127 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1128 .cmd_rcgr = 0x83074, 1129 .mnd_width = 0, 1130 .hid_width = 5, 1131 .parent_map = gcc_parent_map_14, 1132 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1133 .clkr.hw.init = &(const struct clk_init_data) { 1134 .name = "gcc_ufs_phy_ice_core_clk_src", 1135 .parent_data = gcc_parent_data_14, 1136 .num_parents = ARRAY_SIZE(gcc_parent_data_14), 1137 .flags = CLK_SET_RATE_PARENT, 1138 .ops = &clk_rcg2_shared_ops, 1139 }, 1140 }; 1141 1142 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1143 .cmd_rcgr = 0x830a8, 1144 .mnd_width = 0, 1145 .hid_width = 5, 1146 .parent_map = gcc_parent_map_5, 1147 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 1148 .clkr.hw.init = &(const struct clk_init_data) { 1149 .name = "gcc_ufs_phy_phy_aux_clk_src", 1150 .parent_data = gcc_parent_data_5, 1151 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1152 .flags = CLK_SET_RATE_PARENT, 1153 .ops = &clk_rcg2_shared_ops, 1154 }, 1155 }; 1156 1157 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { 1158 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1159 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 1160 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 1161 { } 1162 }; 1163 1164 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1165 .cmd_rcgr = 0x8308c, 1166 .mnd_width = 0, 1167 .hid_width = 5, 1168 .parent_map = gcc_parent_map_0, 1169 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, 1170 .clkr.hw.init = &(const struct clk_init_data) { 1171 .name = "gcc_ufs_phy_unipro_core_clk_src", 1172 .parent_data = gcc_parent_data_0, 1173 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1174 .flags = CLK_SET_RATE_PARENT, 1175 .ops = &clk_rcg2_shared_ops, 1176 }, 1177 }; 1178 1179 static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = { 1180 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 1181 { } 1182 }; 1183 1184 static struct clk_rcg2 gcc_usb20_master_clk_src = { 1185 .cmd_rcgr = 0x1c028, 1186 .mnd_width = 8, 1187 .hid_width = 5, 1188 .parent_map = gcc_parent_map_0, 1189 .freq_tbl = ftbl_gcc_usb20_master_clk_src, 1190 .clkr.hw.init = &(const struct clk_init_data) { 1191 .name = "gcc_usb20_master_clk_src", 1192 .parent_data = gcc_parent_data_0, 1193 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1194 .flags = CLK_SET_RATE_PARENT, 1195 .ops = &clk_rcg2_shared_ops, 1196 }, 1197 }; 1198 1199 static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = { 1200 .cmd_rcgr = 0x1c040, 1201 .mnd_width = 0, 1202 .hid_width = 5, 1203 .parent_map = gcc_parent_map_0, 1204 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 1205 .clkr.hw.init = &(const struct clk_init_data) { 1206 .name = "gcc_usb20_mock_utmi_clk_src", 1207 .parent_data = gcc_parent_data_0, 1208 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1209 .flags = CLK_SET_RATE_PARENT, 1210 .ops = &clk_rcg2_shared_ops, 1211 }, 1212 }; 1213 1214 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1215 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 1216 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1217 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 1218 { } 1219 }; 1220 1221 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1222 .cmd_rcgr = 0x1b028, 1223 .mnd_width = 8, 1224 .hid_width = 5, 1225 .parent_map = gcc_parent_map_0, 1226 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1227 .clkr.hw.init = &(const struct clk_init_data) { 1228 .name = "gcc_usb30_prim_master_clk_src", 1229 .parent_data = gcc_parent_data_0, 1230 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1231 .flags = CLK_SET_RATE_PARENT, 1232 .ops = &clk_rcg2_shared_ops, 1233 }, 1234 }; 1235 1236 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1237 .cmd_rcgr = 0x1b040, 1238 .mnd_width = 0, 1239 .hid_width = 5, 1240 .parent_map = gcc_parent_map_0, 1241 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 1242 .clkr.hw.init = &(const struct clk_init_data) { 1243 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1244 .parent_data = gcc_parent_data_0, 1245 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1246 .flags = CLK_SET_RATE_PARENT, 1247 .ops = &clk_rcg2_shared_ops, 1248 }, 1249 }; 1250 1251 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1252 .cmd_rcgr = 0x1b06c, 1253 .mnd_width = 0, 1254 .hid_width = 5, 1255 .parent_map = gcc_parent_map_2, 1256 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src, 1257 .clkr.hw.init = &(const struct clk_init_data) { 1258 .name = "gcc_usb3_prim_phy_aux_clk_src", 1259 .parent_data = gcc_parent_data_2, 1260 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1261 .flags = CLK_SET_RATE_PARENT, 1262 .ops = &clk_rcg2_shared_ops, 1263 }, 1264 }; 1265 1266 static struct clk_regmap_div gcc_pcie_0_pipe_div_clk_src = { 1267 .reg = 0xa9070, 1268 .shift = 0, 1269 .width = 4, 1270 .clkr.hw.init = &(const struct clk_init_data) { 1271 .name = "gcc_pcie_0_pipe_div_clk_src", 1272 .parent_hws = (const struct clk_hw*[]) { 1273 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1274 }, 1275 .num_parents = 1, 1276 .flags = CLK_SET_RATE_PARENT, 1277 .ops = &clk_regmap_div_ro_ops, 1278 }, 1279 }; 1280 1281 static struct clk_regmap_div gcc_pcie_1_pipe_div_clk_src = { 1282 .reg = 0x77070, 1283 .shift = 0, 1284 .width = 4, 1285 .clkr.hw.init = &(const struct clk_init_data) { 1286 .name = "gcc_pcie_1_pipe_div_clk_src", 1287 .parent_hws = (const struct clk_hw*[]) { 1288 &gcc_pcie_1_pipe_clk_src.clkr.hw, 1289 }, 1290 .num_parents = 1, 1291 .flags = CLK_SET_RATE_PARENT, 1292 .ops = &clk_regmap_div_ro_ops, 1293 }, 1294 }; 1295 1296 static struct clk_regmap_div gcc_qupv3_wrap3_s0_div_clk_src = { 1297 .reg = 0xc4288, 1298 .shift = 0, 1299 .width = 4, 1300 .clkr.hw.init = &(const struct clk_init_data) { 1301 .name = "gcc_qupv3_wrap3_s0_div_clk_src", 1302 .parent_hws = (const struct clk_hw*[]) { 1303 &gcc_qupv3_wrap3_s0_clk_src.clkr.hw, 1304 }, 1305 .num_parents = 1, 1306 .flags = CLK_SET_RATE_PARENT, 1307 .ops = &clk_regmap_div_ro_ops, 1308 }, 1309 }; 1310 1311 static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src = { 1312 .reg = 0x1c058, 1313 .shift = 0, 1314 .width = 4, 1315 .clkr.hw.init = &(const struct clk_init_data) { 1316 .name = "gcc_usb20_mock_utmi_postdiv_clk_src", 1317 .parent_hws = (const struct clk_hw*[]) { 1318 &gcc_usb20_mock_utmi_clk_src.clkr.hw, 1319 }, 1320 .num_parents = 1, 1321 .flags = CLK_SET_RATE_PARENT, 1322 .ops = &clk_regmap_div_ro_ops, 1323 }, 1324 }; 1325 1326 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1327 .reg = 0x1b058, 1328 .shift = 0, 1329 .width = 4, 1330 .clkr.hw.init = &(const struct clk_init_data) { 1331 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1332 .parent_hws = (const struct clk_hw*[]) { 1333 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1334 }, 1335 .num_parents = 1, 1336 .flags = CLK_SET_RATE_PARENT, 1337 .ops = &clk_regmap_div_ro_ops, 1338 }, 1339 }; 1340 1341 static struct clk_branch gcc_aggre_noc_qupv3_axi_clk = { 1342 .halt_reg = 0x8e200, 1343 .halt_check = BRANCH_HALT_VOTED, 1344 .hwcg_reg = 0x8e200, 1345 .hwcg_bit = 1, 1346 .clkr = { 1347 .enable_reg = 0x4b000, 1348 .enable_mask = BIT(28), 1349 .hw.init = &(const struct clk_init_data) { 1350 .name = "gcc_aggre_noc_qupv3_axi_clk", 1351 .ops = &clk_branch2_ops, 1352 }, 1353 }, 1354 }; 1355 1356 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1357 .halt_reg = 0x830d4, 1358 .halt_check = BRANCH_HALT_VOTED, 1359 .hwcg_reg = 0x830d4, 1360 .hwcg_bit = 1, 1361 .clkr = { 1362 .enable_reg = 0x830d4, 1363 .enable_mask = BIT(0), 1364 .hw.init = &(const struct clk_init_data) { 1365 .name = "gcc_aggre_ufs_phy_axi_clk", 1366 .parent_hws = (const struct clk_hw*[]) { 1367 &gcc_ufs_phy_axi_clk_src.clkr.hw, 1368 }, 1369 .num_parents = 1, 1370 .flags = CLK_SET_RATE_PARENT, 1371 .ops = &clk_branch2_ops, 1372 }, 1373 }, 1374 }; 1375 1376 static struct clk_branch gcc_aggre_usb2_prim_axi_clk = { 1377 .halt_reg = 0x1c05c, 1378 .halt_check = BRANCH_HALT_VOTED, 1379 .hwcg_reg = 0x1c05c, 1380 .hwcg_bit = 1, 1381 .clkr = { 1382 .enable_reg = 0x1c05c, 1383 .enable_mask = BIT(0), 1384 .hw.init = &(const struct clk_init_data) { 1385 .name = "gcc_aggre_usb2_prim_axi_clk", 1386 .parent_hws = (const struct clk_hw*[]) { 1387 &gcc_usb20_master_clk_src.clkr.hw, 1388 }, 1389 .num_parents = 1, 1390 .flags = CLK_SET_RATE_PARENT, 1391 .ops = &clk_branch2_ops, 1392 }, 1393 }, 1394 }; 1395 1396 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1397 .halt_reg = 0x1b084, 1398 .halt_check = BRANCH_HALT_VOTED, 1399 .hwcg_reg = 0x1b084, 1400 .hwcg_bit = 1, 1401 .clkr = { 1402 .enable_reg = 0x1b084, 1403 .enable_mask = BIT(0), 1404 .hw.init = &(const struct clk_init_data) { 1405 .name = "gcc_aggre_usb3_prim_axi_clk", 1406 .parent_hws = (const struct clk_hw*[]) { 1407 &gcc_usb30_prim_master_clk_src.clkr.hw, 1408 }, 1409 .num_parents = 1, 1410 .flags = CLK_SET_RATE_PARENT, 1411 .ops = &clk_branch2_ops, 1412 }, 1413 }, 1414 }; 1415 1416 static struct clk_branch gcc_ahb2phy0_clk = { 1417 .halt_reg = 0x76004, 1418 .halt_check = BRANCH_HALT_VOTED, 1419 .hwcg_reg = 0x76004, 1420 .hwcg_bit = 1, 1421 .clkr = { 1422 .enable_reg = 0x76004, 1423 .enable_mask = BIT(0), 1424 .hw.init = &(const struct clk_init_data) { 1425 .name = "gcc_ahb2phy0_clk", 1426 .ops = &clk_branch2_ops, 1427 }, 1428 }, 1429 }; 1430 1431 static struct clk_branch gcc_ahb2phy2_clk = { 1432 .halt_reg = 0x76008, 1433 .halt_check = BRANCH_HALT_VOTED, 1434 .hwcg_reg = 0x76008, 1435 .hwcg_bit = 1, 1436 .clkr = { 1437 .enable_reg = 0x76008, 1438 .enable_mask = BIT(0), 1439 .hw.init = &(const struct clk_init_data) { 1440 .name = "gcc_ahb2phy2_clk", 1441 .ops = &clk_branch2_ops, 1442 }, 1443 }, 1444 }; 1445 1446 static struct clk_branch gcc_ahb2phy3_clk = { 1447 .halt_reg = 0x7600c, 1448 .halt_check = BRANCH_HALT_VOTED, 1449 .hwcg_reg = 0x7600c, 1450 .hwcg_bit = 1, 1451 .clkr = { 1452 .enable_reg = 0x7600c, 1453 .enable_mask = BIT(0), 1454 .hw.init = &(const struct clk_init_data) { 1455 .name = "gcc_ahb2phy3_clk", 1456 .ops = &clk_branch2_ops, 1457 }, 1458 }, 1459 }; 1460 1461 static struct clk_branch gcc_boot_rom_ahb_clk = { 1462 .halt_reg = 0x44004, 1463 .halt_check = BRANCH_HALT_VOTED, 1464 .hwcg_reg = 0x44004, 1465 .hwcg_bit = 1, 1466 .clkr = { 1467 .enable_reg = 0x4b000, 1468 .enable_mask = BIT(10), 1469 .hw.init = &(const struct clk_init_data) { 1470 .name = "gcc_boot_rom_ahb_clk", 1471 .ops = &clk_branch2_ops, 1472 }, 1473 }, 1474 }; 1475 1476 static struct clk_branch gcc_camera_hf_axi_clk = { 1477 .halt_reg = 0x32010, 1478 .halt_check = BRANCH_HALT_SKIP, 1479 .hwcg_reg = 0x32010, 1480 .hwcg_bit = 1, 1481 .clkr = { 1482 .enable_reg = 0x32010, 1483 .enable_mask = BIT(0), 1484 .hw.init = &(const struct clk_init_data) { 1485 .name = "gcc_camera_hf_axi_clk", 1486 .ops = &clk_branch2_ops, 1487 }, 1488 }, 1489 }; 1490 1491 static struct clk_branch gcc_camera_sf_axi_clk = { 1492 .halt_reg = 0x32018, 1493 .halt_check = BRANCH_HALT_SKIP, 1494 .hwcg_reg = 0x32018, 1495 .hwcg_bit = 1, 1496 .clkr = { 1497 .enable_reg = 0x32018, 1498 .enable_mask = BIT(0), 1499 .hw.init = &(const struct clk_init_data) { 1500 .name = "gcc_camera_sf_axi_clk", 1501 .ops = &clk_branch2_ops, 1502 }, 1503 }, 1504 }; 1505 1506 static struct clk_branch gcc_camera_throttle_xo_clk = { 1507 .halt_reg = 0x32024, 1508 .halt_check = BRANCH_HALT, 1509 .clkr = { 1510 .enable_reg = 0x32024, 1511 .enable_mask = BIT(0), 1512 .hw.init = &(const struct clk_init_data) { 1513 .name = "gcc_camera_throttle_xo_clk", 1514 .ops = &clk_branch2_ops, 1515 }, 1516 }, 1517 }; 1518 1519 static struct clk_branch gcc_cfg_noc_usb2_prim_axi_clk = { 1520 .halt_reg = 0x1c060, 1521 .halt_check = BRANCH_HALT_VOTED, 1522 .hwcg_reg = 0x1c060, 1523 .hwcg_bit = 1, 1524 .clkr = { 1525 .enable_reg = 0x1c060, 1526 .enable_mask = BIT(0), 1527 .hw.init = &(const struct clk_init_data) { 1528 .name = "gcc_cfg_noc_usb2_prim_axi_clk", 1529 .parent_hws = (const struct clk_hw*[]) { 1530 &gcc_usb20_master_clk_src.clkr.hw, 1531 }, 1532 .num_parents = 1, 1533 .flags = CLK_SET_RATE_PARENT, 1534 .ops = &clk_branch2_ops, 1535 }, 1536 }, 1537 }; 1538 1539 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1540 .halt_reg = 0x1b088, 1541 .halt_check = BRANCH_HALT_VOTED, 1542 .hwcg_reg = 0x1b088, 1543 .hwcg_bit = 1, 1544 .clkr = { 1545 .enable_reg = 0x1b088, 1546 .enable_mask = BIT(0), 1547 .hw.init = &(const struct clk_init_data) { 1548 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1549 .parent_hws = (const struct clk_hw*[]) { 1550 &gcc_usb30_prim_master_clk_src.clkr.hw, 1551 }, 1552 .num_parents = 1, 1553 .flags = CLK_SET_RATE_PARENT, 1554 .ops = &clk_branch2_ops, 1555 }, 1556 }, 1557 }; 1558 1559 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1560 .halt_reg = 0x7d164, 1561 .halt_check = BRANCH_HALT_VOTED, 1562 .hwcg_reg = 0x7d164, 1563 .hwcg_bit = 1, 1564 .clkr = { 1565 .enable_reg = 0x7d164, 1566 .enable_mask = BIT(0), 1567 .hw.init = &(const struct clk_init_data) { 1568 .name = "gcc_ddrss_gpu_axi_clk", 1569 .ops = &clk_branch2_aon_ops, 1570 }, 1571 }, 1572 }; 1573 1574 static struct clk_branch gcc_disp_hf_axi_clk = { 1575 .halt_reg = 0x33010, 1576 .halt_check = BRANCH_HALT_VOTED, 1577 .hwcg_reg = 0x33010, 1578 .hwcg_bit = 1, 1579 .clkr = { 1580 .enable_reg = 0x33010, 1581 .enable_mask = BIT(0), 1582 .hw.init = &(const struct clk_init_data) { 1583 .name = "gcc_disp_hf_axi_clk", 1584 .ops = &clk_branch2_ops, 1585 }, 1586 }, 1587 }; 1588 1589 static struct clk_branch gcc_edp_ref_clkref_en = { 1590 .halt_reg = 0x97448, 1591 .halt_check = BRANCH_HALT_DELAY, 1592 .clkr = { 1593 .enable_reg = 0x97448, 1594 .enable_mask = BIT(0), 1595 .hw.init = &(const struct clk_init_data) { 1596 .name = "gcc_edp_ref_clkref_en", 1597 .ops = &clk_branch2_ops, 1598 }, 1599 }, 1600 }; 1601 1602 static struct clk_branch gcc_emac0_axi_clk = { 1603 .halt_reg = 0xb6018, 1604 .halt_check = BRANCH_HALT_VOTED, 1605 .hwcg_reg = 0xb6018, 1606 .hwcg_bit = 1, 1607 .clkr = { 1608 .enable_reg = 0xb6018, 1609 .enable_mask = BIT(0), 1610 .hw.init = &(const struct clk_init_data) { 1611 .name = "gcc_emac0_axi_clk", 1612 .ops = &clk_branch2_ops, 1613 }, 1614 }, 1615 }; 1616 1617 static struct clk_branch gcc_emac0_phy_aux_clk = { 1618 .halt_reg = 0xb6024, 1619 .halt_check = BRANCH_HALT, 1620 .clkr = { 1621 .enable_reg = 0xb6024, 1622 .enable_mask = BIT(0), 1623 .hw.init = &(const struct clk_init_data) { 1624 .name = "gcc_emac0_phy_aux_clk", 1625 .parent_hws = (const struct clk_hw*[]) { 1626 &gcc_emac0_phy_aux_clk_src.clkr.hw, 1627 }, 1628 .num_parents = 1, 1629 .flags = CLK_SET_RATE_PARENT, 1630 .ops = &clk_branch2_ops, 1631 }, 1632 }, 1633 }; 1634 1635 static struct clk_branch gcc_emac0_ptp_clk = { 1636 .halt_reg = 0xb6040, 1637 .halt_check = BRANCH_HALT, 1638 .clkr = { 1639 .enable_reg = 0xb6040, 1640 .enable_mask = BIT(0), 1641 .hw.init = &(const struct clk_init_data) { 1642 .name = "gcc_emac0_ptp_clk", 1643 .parent_hws = (const struct clk_hw*[]) { 1644 &gcc_emac0_ptp_clk_src.clkr.hw, 1645 }, 1646 .num_parents = 1, 1647 .flags = CLK_SET_RATE_PARENT, 1648 .ops = &clk_branch2_ops, 1649 }, 1650 }, 1651 }; 1652 1653 static struct clk_branch gcc_emac0_rgmii_clk = { 1654 .halt_reg = 0xb6044, 1655 .halt_check = BRANCH_HALT, 1656 .clkr = { 1657 .enable_reg = 0xb6044, 1658 .enable_mask = BIT(0), 1659 .hw.init = &(const struct clk_init_data) { 1660 .name = "gcc_emac0_rgmii_clk", 1661 .parent_hws = (const struct clk_hw*[]) { 1662 &gcc_emac0_rgmii_clk_src.clkr.hw, 1663 }, 1664 .num_parents = 1, 1665 .flags = CLK_SET_RATE_PARENT, 1666 .ops = &clk_branch2_ops, 1667 }, 1668 }, 1669 }; 1670 1671 static struct clk_branch gcc_emac0_slv_ahb_clk = { 1672 .halt_reg = 0xb6020, 1673 .halt_check = BRANCH_HALT_VOTED, 1674 .hwcg_reg = 0xb6020, 1675 .hwcg_bit = 1, 1676 .clkr = { 1677 .enable_reg = 0xb6020, 1678 .enable_mask = BIT(0), 1679 .hw.init = &(const struct clk_init_data) { 1680 .name = "gcc_emac0_slv_ahb_clk", 1681 .ops = &clk_branch2_ops, 1682 }, 1683 }, 1684 }; 1685 1686 static struct clk_branch gcc_gp1_clk = { 1687 .halt_reg = 0x70000, 1688 .halt_check = BRANCH_HALT, 1689 .clkr = { 1690 .enable_reg = 0x70000, 1691 .enable_mask = BIT(0), 1692 .hw.init = &(const struct clk_init_data) { 1693 .name = "gcc_gp1_clk", 1694 .parent_hws = (const struct clk_hw*[]) { 1695 &gcc_gp1_clk_src.clkr.hw, 1696 }, 1697 .num_parents = 1, 1698 .flags = CLK_SET_RATE_PARENT, 1699 .ops = &clk_branch2_ops, 1700 }, 1701 }, 1702 }; 1703 1704 static struct clk_branch gcc_gp2_clk = { 1705 .halt_reg = 0x71000, 1706 .halt_check = BRANCH_HALT, 1707 .clkr = { 1708 .enable_reg = 0x71000, 1709 .enable_mask = BIT(0), 1710 .hw.init = &(const struct clk_init_data) { 1711 .name = "gcc_gp2_clk", 1712 .parent_hws = (const struct clk_hw*[]) { 1713 &gcc_gp2_clk_src.clkr.hw, 1714 }, 1715 .num_parents = 1, 1716 .flags = CLK_SET_RATE_PARENT, 1717 .ops = &clk_branch2_ops, 1718 }, 1719 }, 1720 }; 1721 1722 static struct clk_branch gcc_gp3_clk = { 1723 .halt_reg = 0x62000, 1724 .halt_check = BRANCH_HALT, 1725 .clkr = { 1726 .enable_reg = 0x62000, 1727 .enable_mask = BIT(0), 1728 .hw.init = &(const struct clk_init_data) { 1729 .name = "gcc_gp3_clk", 1730 .parent_hws = (const struct clk_hw*[]) { 1731 &gcc_gp3_clk_src.clkr.hw, 1732 }, 1733 .num_parents = 1, 1734 .flags = CLK_SET_RATE_PARENT, 1735 .ops = &clk_branch2_ops, 1736 }, 1737 }, 1738 }; 1739 1740 static struct clk_branch gcc_gp4_clk = { 1741 .halt_reg = 0x1e000, 1742 .halt_check = BRANCH_HALT, 1743 .clkr = { 1744 .enable_reg = 0x1e000, 1745 .enable_mask = BIT(0), 1746 .hw.init = &(const struct clk_init_data) { 1747 .name = "gcc_gp4_clk", 1748 .parent_hws = (const struct clk_hw*[]) { 1749 &gcc_gp4_clk_src.clkr.hw, 1750 }, 1751 .num_parents = 1, 1752 .flags = CLK_SET_RATE_PARENT, 1753 .ops = &clk_branch2_ops, 1754 }, 1755 }, 1756 }; 1757 1758 static struct clk_branch gcc_gp5_clk = { 1759 .halt_reg = 0x1f000, 1760 .halt_check = BRANCH_HALT, 1761 .clkr = { 1762 .enable_reg = 0x1f000, 1763 .enable_mask = BIT(0), 1764 .hw.init = &(const struct clk_init_data) { 1765 .name = "gcc_gp5_clk", 1766 .parent_hws = (const struct clk_hw*[]) { 1767 &gcc_gp5_clk_src.clkr.hw, 1768 }, 1769 .num_parents = 1, 1770 .flags = CLK_SET_RATE_PARENT, 1771 .ops = &clk_branch2_ops, 1772 }, 1773 }, 1774 }; 1775 1776 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1777 .halt_check = BRANCH_HALT_DELAY, 1778 .clkr = { 1779 .enable_reg = 0x4b000, 1780 .enable_mask = BIT(15), 1781 .hw.init = &(const struct clk_init_data) { 1782 .name = "gcc_gpu_gpll0_clk_src", 1783 .parent_hws = (const struct clk_hw*[]) { 1784 &gcc_gpll0.clkr.hw, 1785 }, 1786 .num_parents = 1, 1787 .flags = CLK_SET_RATE_PARENT, 1788 .ops = &clk_branch2_ops, 1789 }, 1790 }, 1791 }; 1792 1793 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1794 .halt_check = BRANCH_HALT_DELAY, 1795 .clkr = { 1796 .enable_reg = 0x4b000, 1797 .enable_mask = BIT(16), 1798 .hw.init = &(const struct clk_init_data) { 1799 .name = "gcc_gpu_gpll0_div_clk_src", 1800 .parent_hws = (const struct clk_hw*[]) { 1801 &gcc_gpll0_out_even.clkr.hw, 1802 }, 1803 .num_parents = 1, 1804 .flags = CLK_SET_RATE_PARENT, 1805 .ops = &clk_branch2_ops, 1806 }, 1807 }, 1808 }; 1809 1810 static struct clk_branch gcc_gpu_memnoc_gfx_center_pipeline_clk = { 1811 .halt_reg = 0x7d160, 1812 .halt_check = BRANCH_HALT_VOTED, 1813 .hwcg_reg = 0x7d160, 1814 .hwcg_bit = 1, 1815 .clkr = { 1816 .enable_reg = 0x7d160, 1817 .enable_mask = BIT(0), 1818 .hw.init = &(const struct clk_init_data) { 1819 .name = "gcc_gpu_memnoc_gfx_center_pipeline_clk", 1820 .ops = &clk_branch2_ops, 1821 }, 1822 }, 1823 }; 1824 1825 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1826 .halt_reg = 0x7d010, 1827 .halt_check = BRANCH_HALT_VOTED, 1828 .hwcg_reg = 0x7d010, 1829 .hwcg_bit = 1, 1830 .clkr = { 1831 .enable_reg = 0x7d010, 1832 .enable_mask = BIT(0), 1833 .hw.init = &(const struct clk_init_data) { 1834 .name = "gcc_gpu_memnoc_gfx_clk", 1835 .ops = &clk_branch2_aon_ops, 1836 }, 1837 }, 1838 }; 1839 1840 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1841 .halt_reg = 0x7d01c, 1842 .halt_check = BRANCH_HALT_DELAY, 1843 .clkr = { 1844 .enable_reg = 0x7d01c, 1845 .enable_mask = BIT(0), 1846 .hw.init = &(const struct clk_init_data) { 1847 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1848 .ops = &clk_branch2_aon_ops, 1849 }, 1850 }, 1851 }; 1852 1853 static struct clk_branch gcc_gpu_tcu_throttle_ahb_clk = { 1854 .halt_reg = 0x7d008, 1855 .halt_check = BRANCH_HALT_VOTED, 1856 .hwcg_reg = 0x7d008, 1857 .hwcg_bit = 1, 1858 .clkr = { 1859 .enable_reg = 0x7d008, 1860 .enable_mask = BIT(0), 1861 .hw.init = &(const struct clk_init_data) { 1862 .name = "gcc_gpu_tcu_throttle_ahb_clk", 1863 .ops = &clk_branch2_ops, 1864 }, 1865 }, 1866 }; 1867 1868 static struct clk_branch gcc_gpu_tcu_throttle_clk = { 1869 .halt_reg = 0x7d014, 1870 .halt_check = BRANCH_HALT_VOTED, 1871 .hwcg_reg = 0x7d014, 1872 .hwcg_bit = 1, 1873 .clkr = { 1874 .enable_reg = 0x7d014, 1875 .enable_mask = BIT(0), 1876 .hw.init = &(const struct clk_init_data) { 1877 .name = "gcc_gpu_tcu_throttle_clk", 1878 .ops = &clk_branch2_ops, 1879 }, 1880 }, 1881 }; 1882 1883 static struct clk_branch gcc_pcie_0_aux_clk = { 1884 .halt_reg = 0xa9038, 1885 .halt_check = BRANCH_HALT_VOTED, 1886 .clkr = { 1887 .enable_reg = 0x4b010, 1888 .enable_mask = BIT(16), 1889 .hw.init = &(const struct clk_init_data) { 1890 .name = "gcc_pcie_0_aux_clk", 1891 .parent_hws = (const struct clk_hw*[]) { 1892 &gcc_pcie_0_aux_clk_src.clkr.hw, 1893 }, 1894 .num_parents = 1, 1895 .flags = CLK_SET_RATE_PARENT, 1896 .ops = &clk_branch2_ops, 1897 }, 1898 }, 1899 }; 1900 1901 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1902 .halt_reg = 0xa902c, 1903 .halt_check = BRANCH_HALT_VOTED, 1904 .hwcg_reg = 0xa902c, 1905 .hwcg_bit = 1, 1906 .clkr = { 1907 .enable_reg = 0x4b010, 1908 .enable_mask = BIT(12), 1909 .hw.init = &(const struct clk_init_data) { 1910 .name = "gcc_pcie_0_cfg_ahb_clk", 1911 .ops = &clk_branch2_ops, 1912 }, 1913 }, 1914 }; 1915 1916 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1917 .halt_reg = 0xa9024, 1918 .halt_check = BRANCH_HALT_VOTED, 1919 .clkr = { 1920 .enable_reg = 0x4b010, 1921 .enable_mask = BIT(11), 1922 .hw.init = &(const struct clk_init_data) { 1923 .name = "gcc_pcie_0_mstr_axi_clk", 1924 .ops = &clk_branch2_ops, 1925 }, 1926 }, 1927 }; 1928 1929 static struct clk_branch gcc_pcie_0_phy_aux_clk = { 1930 .halt_reg = 0xa9030, 1931 .halt_check = BRANCH_HALT_VOTED, 1932 .clkr = { 1933 .enable_reg = 0x4b010, 1934 .enable_mask = BIT(13), 1935 .hw.init = &(const struct clk_init_data) { 1936 .name = "gcc_pcie_0_phy_aux_clk", 1937 .parent_hws = (const struct clk_hw*[]) { 1938 &gcc_pcie_0_phy_aux_clk_src.clkr.hw, 1939 }, 1940 .num_parents = 1, 1941 .flags = CLK_SET_RATE_PARENT, 1942 .ops = &clk_branch2_ops, 1943 }, 1944 }, 1945 }; 1946 1947 static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 1948 .halt_reg = 0xa9050, 1949 .halt_check = BRANCH_HALT_VOTED, 1950 .clkr = { 1951 .enable_reg = 0x4b010, 1952 .enable_mask = BIT(15), 1953 .hw.init = &(const struct clk_init_data) { 1954 .name = "gcc_pcie_0_phy_rchng_clk", 1955 .parent_hws = (const struct clk_hw*[]) { 1956 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 1957 }, 1958 .num_parents = 1, 1959 .flags = CLK_SET_RATE_PARENT, 1960 .ops = &clk_branch2_ops, 1961 }, 1962 }, 1963 }; 1964 1965 static struct clk_branch gcc_pcie_0_pipe_clk = { 1966 .halt_reg = 0xa9040, 1967 .halt_check = BRANCH_HALT_SKIP, 1968 .clkr = { 1969 .enable_reg = 0x4b010, 1970 .enable_mask = BIT(14), 1971 .hw.init = &(const struct clk_init_data) { 1972 .name = "gcc_pcie_0_pipe_clk", 1973 .parent_hws = (const struct clk_hw*[]) { 1974 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1975 }, 1976 .num_parents = 1, 1977 .flags = CLK_SET_RATE_PARENT, 1978 .ops = &clk_branch2_ops, 1979 }, 1980 }, 1981 }; 1982 1983 static struct clk_branch gcc_pcie_0_pipediv2_clk = { 1984 .halt_reg = 0xa9048, 1985 .halt_check = BRANCH_HALT_SKIP, 1986 .clkr = { 1987 .enable_reg = 0x4b018, 1988 .enable_mask = BIT(22), 1989 .hw.init = &(const struct clk_init_data) { 1990 .name = "gcc_pcie_0_pipediv2_clk", 1991 .parent_hws = (const struct clk_hw*[]) { 1992 &gcc_pcie_0_pipe_div_clk_src.clkr.hw, 1993 }, 1994 .num_parents = 1, 1995 .flags = CLK_SET_RATE_PARENT, 1996 .ops = &clk_branch2_ops, 1997 }, 1998 }, 1999 }; 2000 2001 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 2002 .halt_reg = 0xa901c, 2003 .halt_check = BRANCH_HALT_VOTED, 2004 .clkr = { 2005 .enable_reg = 0x4b010, 2006 .enable_mask = BIT(10), 2007 .hw.init = &(const struct clk_init_data) { 2008 .name = "gcc_pcie_0_slv_axi_clk", 2009 .ops = &clk_branch2_ops, 2010 }, 2011 }, 2012 }; 2013 2014 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 2015 .halt_reg = 0xa9018, 2016 .halt_check = BRANCH_HALT_VOTED, 2017 .clkr = { 2018 .enable_reg = 0x4b018, 2019 .enable_mask = BIT(12), 2020 .hw.init = &(const struct clk_init_data) { 2021 .name = "gcc_pcie_0_slv_q2a_axi_clk", 2022 .ops = &clk_branch2_ops, 2023 }, 2024 }, 2025 }; 2026 2027 static struct clk_branch gcc_pcie_1_aux_clk = { 2028 .halt_reg = 0x77038, 2029 .halt_check = BRANCH_HALT_VOTED, 2030 .clkr = { 2031 .enable_reg = 0x4b000, 2032 .enable_mask = BIT(31), 2033 .hw.init = &(const struct clk_init_data) { 2034 .name = "gcc_pcie_1_aux_clk", 2035 .parent_hws = (const struct clk_hw*[]) { 2036 &gcc_pcie_1_aux_clk_src.clkr.hw, 2037 }, 2038 .num_parents = 1, 2039 .flags = CLK_SET_RATE_PARENT, 2040 .ops = &clk_branch2_ops, 2041 }, 2042 }, 2043 }; 2044 2045 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 2046 .halt_reg = 0x7702c, 2047 .halt_check = BRANCH_HALT_VOTED, 2048 .hwcg_reg = 0x7702c, 2049 .hwcg_bit = 1, 2050 .clkr = { 2051 .enable_reg = 0x4b008, 2052 .enable_mask = BIT(2), 2053 .hw.init = &(const struct clk_init_data) { 2054 .name = "gcc_pcie_1_cfg_ahb_clk", 2055 .ops = &clk_branch2_ops, 2056 }, 2057 }, 2058 }; 2059 2060 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 2061 .halt_reg = 0x77024, 2062 .halt_check = BRANCH_HALT_VOTED, 2063 .clkr = { 2064 .enable_reg = 0x4b008, 2065 .enable_mask = BIT(1), 2066 .hw.init = &(const struct clk_init_data) { 2067 .name = "gcc_pcie_1_mstr_axi_clk", 2068 .ops = &clk_branch2_ops, 2069 }, 2070 }, 2071 }; 2072 2073 static struct clk_branch gcc_pcie_1_phy_aux_clk = { 2074 .halt_reg = 0x77030, 2075 .halt_check = BRANCH_HALT_VOTED, 2076 .clkr = { 2077 .enable_reg = 0x4b008, 2078 .enable_mask = BIT(3), 2079 .hw.init = &(const struct clk_init_data) { 2080 .name = "gcc_pcie_1_phy_aux_clk", 2081 .parent_hws = (const struct clk_hw*[]) { 2082 &gcc_pcie_1_phy_aux_clk_src.clkr.hw, 2083 }, 2084 .num_parents = 1, 2085 .flags = CLK_SET_RATE_PARENT, 2086 .ops = &clk_branch2_ops, 2087 }, 2088 }, 2089 }; 2090 2091 static struct clk_branch gcc_pcie_1_phy_rchng_clk = { 2092 .halt_reg = 0x77050, 2093 .halt_check = BRANCH_HALT_VOTED, 2094 .clkr = { 2095 .enable_reg = 0x4b000, 2096 .enable_mask = BIT(22), 2097 .hw.init = &(const struct clk_init_data) { 2098 .name = "gcc_pcie_1_phy_rchng_clk", 2099 .parent_hws = (const struct clk_hw*[]) { 2100 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, 2101 }, 2102 .num_parents = 1, 2103 .flags = CLK_SET_RATE_PARENT, 2104 .ops = &clk_branch2_ops, 2105 }, 2106 }, 2107 }; 2108 2109 static struct clk_branch gcc_pcie_1_pipe_clk = { 2110 .halt_reg = 0x77040, 2111 .halt_check = BRANCH_HALT_SKIP, 2112 .clkr = { 2113 .enable_reg = 0x4b008, 2114 .enable_mask = BIT(4), 2115 .hw.init = &(const struct clk_init_data) { 2116 .name = "gcc_pcie_1_pipe_clk", 2117 .parent_hws = (const struct clk_hw*[]) { 2118 &gcc_pcie_1_pipe_clk_src.clkr.hw, 2119 }, 2120 .num_parents = 1, 2121 .flags = CLK_SET_RATE_PARENT, 2122 .ops = &clk_branch2_ops, 2123 }, 2124 }, 2125 }; 2126 2127 static struct clk_branch gcc_pcie_1_pipediv2_clk = { 2128 .halt_reg = 0x77048, 2129 .halt_check = BRANCH_HALT_SKIP, 2130 .clkr = { 2131 .enable_reg = 0x4b018, 2132 .enable_mask = BIT(16), 2133 .hw.init = &(const struct clk_init_data) { 2134 .name = "gcc_pcie_1_pipediv2_clk", 2135 .parent_hws = (const struct clk_hw*[]) { 2136 &gcc_pcie_1_pipe_div_clk_src.clkr.hw, 2137 }, 2138 .num_parents = 1, 2139 .flags = CLK_SET_RATE_PARENT, 2140 .ops = &clk_branch2_ops, 2141 }, 2142 }, 2143 }; 2144 2145 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 2146 .halt_reg = 0x7701c, 2147 .halt_check = BRANCH_HALT_VOTED, 2148 .clkr = { 2149 .enable_reg = 0x4b008, 2150 .enable_mask = BIT(0), 2151 .hw.init = &(const struct clk_init_data) { 2152 .name = "gcc_pcie_1_slv_axi_clk", 2153 .ops = &clk_branch2_ops, 2154 }, 2155 }, 2156 }; 2157 2158 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 2159 .halt_reg = 0x77018, 2160 .halt_check = BRANCH_HALT_VOTED, 2161 .clkr = { 2162 .enable_reg = 0x4b008, 2163 .enable_mask = BIT(5), 2164 .hw.init = &(const struct clk_init_data) { 2165 .name = "gcc_pcie_1_slv_q2a_axi_clk", 2166 .ops = &clk_branch2_ops, 2167 }, 2168 }, 2169 }; 2170 2171 static struct clk_branch gcc_pcie_clkref_en = { 2172 .halt_reg = 0x9746c, 2173 .halt_check = BRANCH_HALT_DELAY, 2174 .clkr = { 2175 .enable_reg = 0x9746c, 2176 .enable_mask = BIT(0), 2177 .hw.init = &(const struct clk_init_data) { 2178 .name = "gcc_pcie_clkref_en", 2179 .ops = &clk_branch2_ops, 2180 }, 2181 }, 2182 }; 2183 2184 static struct clk_branch gcc_pcie_throttle_cfg_clk = { 2185 .halt_reg = 0xb2034, 2186 .halt_check = BRANCH_HALT_VOTED, 2187 .clkr = { 2188 .enable_reg = 0x4b020, 2189 .enable_mask = BIT(15), 2190 .hw.init = &(const struct clk_init_data) { 2191 .name = "gcc_pcie_throttle_cfg_clk", 2192 .ops = &clk_branch2_ops, 2193 }, 2194 }, 2195 }; 2196 2197 static struct clk_branch gcc_pdm2_clk = { 2198 .halt_reg = 0x3f00c, 2199 .halt_check = BRANCH_HALT, 2200 .clkr = { 2201 .enable_reg = 0x3f00c, 2202 .enable_mask = BIT(0), 2203 .hw.init = &(const struct clk_init_data) { 2204 .name = "gcc_pdm2_clk", 2205 .parent_hws = (const struct clk_hw*[]) { 2206 &gcc_pdm2_clk_src.clkr.hw, 2207 }, 2208 .num_parents = 1, 2209 .flags = CLK_SET_RATE_PARENT, 2210 .ops = &clk_branch2_ops, 2211 }, 2212 }, 2213 }; 2214 2215 static struct clk_branch gcc_pdm_ahb_clk = { 2216 .halt_reg = 0x3f004, 2217 .halt_check = BRANCH_HALT_VOTED, 2218 .hwcg_reg = 0x3f004, 2219 .hwcg_bit = 1, 2220 .clkr = { 2221 .enable_reg = 0x3f004, 2222 .enable_mask = BIT(0), 2223 .hw.init = &(const struct clk_init_data) { 2224 .name = "gcc_pdm_ahb_clk", 2225 .ops = &clk_branch2_ops, 2226 }, 2227 }, 2228 }; 2229 2230 static struct clk_branch gcc_pdm_xo4_clk = { 2231 .halt_reg = 0x3f008, 2232 .halt_check = BRANCH_HALT, 2233 .clkr = { 2234 .enable_reg = 0x3f008, 2235 .enable_mask = BIT(0), 2236 .hw.init = &(const struct clk_init_data) { 2237 .name = "gcc_pdm_xo4_clk", 2238 .ops = &clk_branch2_ops, 2239 }, 2240 }, 2241 }; 2242 2243 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 2244 .halt_reg = 0x32008, 2245 .halt_check = BRANCH_HALT_VOTED, 2246 .hwcg_reg = 0x32008, 2247 .hwcg_bit = 1, 2248 .clkr = { 2249 .enable_reg = 0x32008, 2250 .enable_mask = BIT(0), 2251 .hw.init = &(const struct clk_init_data) { 2252 .name = "gcc_qmip_camera_nrt_ahb_clk", 2253 .ops = &clk_branch2_ops, 2254 }, 2255 }, 2256 }; 2257 2258 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 2259 .halt_reg = 0x3200c, 2260 .halt_check = BRANCH_HALT_VOTED, 2261 .hwcg_reg = 0x3200c, 2262 .hwcg_bit = 1, 2263 .clkr = { 2264 .enable_reg = 0x3200c, 2265 .enable_mask = BIT(0), 2266 .hw.init = &(const struct clk_init_data) { 2267 .name = "gcc_qmip_camera_rt_ahb_clk", 2268 .ops = &clk_branch2_ops, 2269 }, 2270 }, 2271 }; 2272 2273 static struct clk_branch gcc_qmip_disp_ahb_clk = { 2274 .halt_reg = 0x33008, 2275 .halt_check = BRANCH_HALT_VOTED, 2276 .hwcg_reg = 0x33008, 2277 .hwcg_bit = 1, 2278 .clkr = { 2279 .enable_reg = 0x33008, 2280 .enable_mask = BIT(0), 2281 .hw.init = &(const struct clk_init_data) { 2282 .name = "gcc_qmip_disp_ahb_clk", 2283 .ops = &clk_branch2_ops, 2284 }, 2285 }, 2286 }; 2287 2288 static struct clk_branch gcc_qmip_disp_rot_ahb_clk = { 2289 .halt_reg = 0x3300c, 2290 .halt_check = BRANCH_HALT_VOTED, 2291 .clkr = { 2292 .enable_reg = 0x3300c, 2293 .enable_mask = BIT(0), 2294 .hw.init = &(const struct clk_init_data) { 2295 .name = "gcc_qmip_disp_rot_ahb_clk", 2296 .ops = &clk_branch2_ops, 2297 }, 2298 }, 2299 }; 2300 2301 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 2302 .halt_reg = 0x34008, 2303 .halt_check = BRANCH_HALT_VOTED, 2304 .hwcg_reg = 0x34008, 2305 .hwcg_bit = 1, 2306 .clkr = { 2307 .enable_reg = 0x34008, 2308 .enable_mask = BIT(0), 2309 .hw.init = &(const struct clk_init_data) { 2310 .name = "gcc_qmip_video_cvp_ahb_clk", 2311 .ops = &clk_branch2_ops, 2312 }, 2313 }, 2314 }; 2315 2316 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 2317 .halt_reg = 0x3400c, 2318 .halt_check = BRANCH_HALT_VOTED, 2319 .hwcg_reg = 0x3400c, 2320 .hwcg_bit = 1, 2321 .clkr = { 2322 .enable_reg = 0x3400c, 2323 .enable_mask = BIT(0), 2324 .hw.init = &(const struct clk_init_data) { 2325 .name = "gcc_qmip_video_vcodec_ahb_clk", 2326 .ops = &clk_branch2_ops, 2327 }, 2328 }, 2329 }; 2330 2331 static struct clk_branch gcc_qmip_video_vcpu_ahb_clk = { 2332 .halt_reg = 0x34010, 2333 .halt_check = BRANCH_HALT_VOTED, 2334 .hwcg_reg = 0x34010, 2335 .hwcg_bit = 1, 2336 .clkr = { 2337 .enable_reg = 0x34010, 2338 .enable_mask = BIT(0), 2339 .hw.init = &(const struct clk_init_data) { 2340 .name = "gcc_qmip_video_vcpu_ahb_clk", 2341 .ops = &clk_branch2_ops, 2342 }, 2343 }, 2344 }; 2345 2346 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 2347 .halt_reg = 0x23018, 2348 .halt_check = BRANCH_HALT_VOTED, 2349 .clkr = { 2350 .enable_reg = 0x4b008, 2351 .enable_mask = BIT(9), 2352 .hw.init = &(const struct clk_init_data) { 2353 .name = "gcc_qupv3_wrap0_core_2x_clk", 2354 .ops = &clk_branch2_ops, 2355 }, 2356 }, 2357 }; 2358 2359 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 2360 .halt_reg = 0x2300c, 2361 .halt_check = BRANCH_HALT_VOTED, 2362 .clkr = { 2363 .enable_reg = 0x4b008, 2364 .enable_mask = BIT(8), 2365 .hw.init = &(const struct clk_init_data) { 2366 .name = "gcc_qupv3_wrap0_core_clk", 2367 .ops = &clk_branch2_ops, 2368 }, 2369 }, 2370 }; 2371 2372 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2373 .halt_reg = 0x2314c, 2374 .halt_check = BRANCH_HALT_VOTED, 2375 .clkr = { 2376 .enable_reg = 0x4b008, 2377 .enable_mask = BIT(10), 2378 .hw.init = &(const struct clk_init_data) { 2379 .name = "gcc_qupv3_wrap0_s0_clk", 2380 .parent_hws = (const struct clk_hw*[]) { 2381 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 2382 }, 2383 .num_parents = 1, 2384 .flags = CLK_SET_RATE_PARENT, 2385 .ops = &clk_branch2_ops, 2386 }, 2387 }, 2388 }; 2389 2390 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2391 .halt_reg = 0x23280, 2392 .halt_check = BRANCH_HALT_VOTED, 2393 .clkr = { 2394 .enable_reg = 0x4b008, 2395 .enable_mask = BIT(11), 2396 .hw.init = &(const struct clk_init_data) { 2397 .name = "gcc_qupv3_wrap0_s1_clk", 2398 .parent_hws = (const struct clk_hw*[]) { 2399 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 2400 }, 2401 .num_parents = 1, 2402 .flags = CLK_SET_RATE_PARENT, 2403 .ops = &clk_branch2_ops, 2404 }, 2405 }, 2406 }; 2407 2408 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2409 .halt_reg = 0x233b4, 2410 .halt_check = BRANCH_HALT_VOTED, 2411 .clkr = { 2412 .enable_reg = 0x4b008, 2413 .enable_mask = BIT(12), 2414 .hw.init = &(const struct clk_init_data) { 2415 .name = "gcc_qupv3_wrap0_s2_clk", 2416 .parent_hws = (const struct clk_hw*[]) { 2417 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 2418 }, 2419 .num_parents = 1, 2420 .flags = CLK_SET_RATE_PARENT, 2421 .ops = &clk_branch2_ops, 2422 }, 2423 }, 2424 }; 2425 2426 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2427 .halt_reg = 0x234e8, 2428 .halt_check = BRANCH_HALT_VOTED, 2429 .clkr = { 2430 .enable_reg = 0x4b008, 2431 .enable_mask = BIT(13), 2432 .hw.init = &(const struct clk_init_data) { 2433 .name = "gcc_qupv3_wrap0_s3_clk", 2434 .parent_hws = (const struct clk_hw*[]) { 2435 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 2436 }, 2437 .num_parents = 1, 2438 .flags = CLK_SET_RATE_PARENT, 2439 .ops = &clk_branch2_ops, 2440 }, 2441 }, 2442 }; 2443 2444 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2445 .halt_reg = 0x2361c, 2446 .halt_check = BRANCH_HALT_VOTED, 2447 .clkr = { 2448 .enable_reg = 0x4b008, 2449 .enable_mask = BIT(14), 2450 .hw.init = &(const struct clk_init_data) { 2451 .name = "gcc_qupv3_wrap0_s4_clk", 2452 .parent_hws = (const struct clk_hw*[]) { 2453 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 2454 }, 2455 .num_parents = 1, 2456 .flags = CLK_SET_RATE_PARENT, 2457 .ops = &clk_branch2_ops, 2458 }, 2459 }, 2460 }; 2461 2462 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2463 .halt_reg = 0x23750, 2464 .halt_check = BRANCH_HALT_VOTED, 2465 .clkr = { 2466 .enable_reg = 0x4b008, 2467 .enable_mask = BIT(15), 2468 .hw.init = &(const struct clk_init_data) { 2469 .name = "gcc_qupv3_wrap0_s5_clk", 2470 .parent_hws = (const struct clk_hw*[]) { 2471 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 2472 }, 2473 .num_parents = 1, 2474 .flags = CLK_SET_RATE_PARENT, 2475 .ops = &clk_branch2_ops, 2476 }, 2477 }, 2478 }; 2479 2480 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 2481 .halt_reg = 0x23884, 2482 .halt_check = BRANCH_HALT_VOTED, 2483 .clkr = { 2484 .enable_reg = 0x4b008, 2485 .enable_mask = BIT(16), 2486 .hw.init = &(const struct clk_init_data) { 2487 .name = "gcc_qupv3_wrap0_s6_clk", 2488 .parent_hws = (const struct clk_hw*[]) { 2489 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 2490 }, 2491 .num_parents = 1, 2492 .flags = CLK_SET_RATE_PARENT, 2493 .ops = &clk_branch2_ops, 2494 }, 2495 }, 2496 }; 2497 2498 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 2499 .halt_reg = 0x239b8, 2500 .halt_check = BRANCH_HALT_VOTED, 2501 .clkr = { 2502 .enable_reg = 0x4b008, 2503 .enable_mask = BIT(17), 2504 .hw.init = &(const struct clk_init_data) { 2505 .name = "gcc_qupv3_wrap0_s7_clk", 2506 .parent_hws = (const struct clk_hw*[]) { 2507 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, 2508 }, 2509 .num_parents = 1, 2510 .flags = CLK_SET_RATE_PARENT, 2511 .ops = &clk_branch2_ops, 2512 }, 2513 }, 2514 }; 2515 2516 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 2517 .halt_reg = 0x24018, 2518 .halt_check = BRANCH_HALT_VOTED, 2519 .clkr = { 2520 .enable_reg = 0x4b008, 2521 .enable_mask = BIT(18), 2522 .hw.init = &(const struct clk_init_data) { 2523 .name = "gcc_qupv3_wrap1_core_2x_clk", 2524 .ops = &clk_branch2_ops, 2525 }, 2526 }, 2527 }; 2528 2529 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 2530 .halt_reg = 0x2400c, 2531 .halt_check = BRANCH_HALT_VOTED, 2532 .clkr = { 2533 .enable_reg = 0x4b008, 2534 .enable_mask = BIT(19), 2535 .hw.init = &(const struct clk_init_data) { 2536 .name = "gcc_qupv3_wrap1_core_clk", 2537 .ops = &clk_branch2_ops, 2538 }, 2539 }, 2540 }; 2541 2542 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2543 .halt_reg = 0x2414c, 2544 .halt_check = BRANCH_HALT_VOTED, 2545 .clkr = { 2546 .enable_reg = 0x4b008, 2547 .enable_mask = BIT(22), 2548 .hw.init = &(const struct clk_init_data) { 2549 .name = "gcc_qupv3_wrap1_s0_clk", 2550 .parent_hws = (const struct clk_hw*[]) { 2551 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 2552 }, 2553 .num_parents = 1, 2554 .flags = CLK_SET_RATE_PARENT, 2555 .ops = &clk_branch2_ops, 2556 }, 2557 }, 2558 }; 2559 2560 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2561 .halt_reg = 0x24280, 2562 .halt_check = BRANCH_HALT_VOTED, 2563 .clkr = { 2564 .enable_reg = 0x4b008, 2565 .enable_mask = BIT(23), 2566 .hw.init = &(const struct clk_init_data) { 2567 .name = "gcc_qupv3_wrap1_s1_clk", 2568 .parent_hws = (const struct clk_hw*[]) { 2569 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 2570 }, 2571 .num_parents = 1, 2572 .flags = CLK_SET_RATE_PARENT, 2573 .ops = &clk_branch2_ops, 2574 }, 2575 }, 2576 }; 2577 2578 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2579 .halt_reg = 0x243b4, 2580 .halt_check = BRANCH_HALT_VOTED, 2581 .clkr = { 2582 .enable_reg = 0x4b008, 2583 .enable_mask = BIT(24), 2584 .hw.init = &(const struct clk_init_data) { 2585 .name = "gcc_qupv3_wrap1_s2_clk", 2586 .parent_hws = (const struct clk_hw*[]) { 2587 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 2588 }, 2589 .num_parents = 1, 2590 .flags = CLK_SET_RATE_PARENT, 2591 .ops = &clk_branch2_ops, 2592 }, 2593 }, 2594 }; 2595 2596 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2597 .halt_reg = 0x244e8, 2598 .halt_check = BRANCH_HALT_VOTED, 2599 .clkr = { 2600 .enable_reg = 0x4b008, 2601 .enable_mask = BIT(25), 2602 .hw.init = &(const struct clk_init_data) { 2603 .name = "gcc_qupv3_wrap1_s3_clk", 2604 .parent_hws = (const struct clk_hw*[]) { 2605 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2606 }, 2607 .num_parents = 1, 2608 .flags = CLK_SET_RATE_PARENT, 2609 .ops = &clk_branch2_ops, 2610 }, 2611 }, 2612 }; 2613 2614 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2615 .halt_reg = 0x2461c, 2616 .halt_check = BRANCH_HALT_VOTED, 2617 .clkr = { 2618 .enable_reg = 0x4b008, 2619 .enable_mask = BIT(26), 2620 .hw.init = &(const struct clk_init_data) { 2621 .name = "gcc_qupv3_wrap1_s4_clk", 2622 .parent_hws = (const struct clk_hw*[]) { 2623 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2624 }, 2625 .num_parents = 1, 2626 .flags = CLK_SET_RATE_PARENT, 2627 .ops = &clk_branch2_ops, 2628 }, 2629 }, 2630 }; 2631 2632 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2633 .halt_reg = 0x24750, 2634 .halt_check = BRANCH_HALT_VOTED, 2635 .clkr = { 2636 .enable_reg = 0x4b008, 2637 .enable_mask = BIT(27), 2638 .hw.init = &(const struct clk_init_data) { 2639 .name = "gcc_qupv3_wrap1_s5_clk", 2640 .parent_hws = (const struct clk_hw*[]) { 2641 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 2642 }, 2643 .num_parents = 1, 2644 .flags = CLK_SET_RATE_PARENT, 2645 .ops = &clk_branch2_ops, 2646 }, 2647 }, 2648 }; 2649 2650 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 2651 .halt_reg = 0x24884, 2652 .halt_check = BRANCH_HALT_VOTED, 2653 .clkr = { 2654 .enable_reg = 0x4b018, 2655 .enable_mask = BIT(27), 2656 .hw.init = &(const struct clk_init_data) { 2657 .name = "gcc_qupv3_wrap1_s6_clk", 2658 .parent_hws = (const struct clk_hw*[]) { 2659 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 2660 }, 2661 .num_parents = 1, 2662 .flags = CLK_SET_RATE_PARENT, 2663 .ops = &clk_branch2_ops, 2664 }, 2665 }, 2666 }; 2667 2668 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 2669 .halt_reg = 0x249b8, 2670 .halt_check = BRANCH_HALT_VOTED, 2671 .clkr = { 2672 .enable_reg = 0x4b018, 2673 .enable_mask = BIT(28), 2674 .hw.init = &(const struct clk_init_data) { 2675 .name = "gcc_qupv3_wrap1_s7_clk", 2676 .parent_hws = (const struct clk_hw*[]) { 2677 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 2678 }, 2679 .num_parents = 1, 2680 .flags = CLK_SET_RATE_PARENT, 2681 .ops = &clk_branch2_ops, 2682 }, 2683 }, 2684 }; 2685 2686 static struct clk_branch gcc_qupv3_wrap3_core_2x_clk = { 2687 .halt_reg = 0xc4018, 2688 .halt_check = BRANCH_HALT_VOTED, 2689 .clkr = { 2690 .enable_reg = 0x4b000, 2691 .enable_mask = BIT(24), 2692 .hw.init = &(const struct clk_init_data) { 2693 .name = "gcc_qupv3_wrap3_core_2x_clk", 2694 .ops = &clk_branch2_ops, 2695 }, 2696 }, 2697 }; 2698 2699 static struct clk_branch gcc_qupv3_wrap3_core_clk = { 2700 .halt_reg = 0xc400c, 2701 .halt_check = BRANCH_HALT_VOTED, 2702 .clkr = { 2703 .enable_reg = 0x4b000, 2704 .enable_mask = BIT(23), 2705 .hw.init = &(const struct clk_init_data) { 2706 .name = "gcc_qupv3_wrap3_core_clk", 2707 .ops = &clk_branch2_ops, 2708 }, 2709 }, 2710 }; 2711 2712 static struct clk_branch gcc_qupv3_wrap3_qspi_clk = { 2713 .halt_reg = 0xc4284, 2714 .halt_check = BRANCH_HALT_VOTED, 2715 .clkr = { 2716 .enable_reg = 0x4b000, 2717 .enable_mask = BIT(26), 2718 .hw.init = &(const struct clk_init_data) { 2719 .name = "gcc_qupv3_wrap3_qspi_clk", 2720 .parent_hws = (const struct clk_hw*[]) { 2721 &gcc_qupv3_wrap3_s0_clk_src.clkr.hw, 2722 }, 2723 .num_parents = 1, 2724 .flags = CLK_SET_RATE_PARENT, 2725 .ops = &clk_branch2_ops, 2726 }, 2727 }, 2728 }; 2729 2730 static struct clk_branch gcc_qupv3_wrap3_s0_clk = { 2731 .halt_reg = 0xc4150, 2732 .halt_check = BRANCH_HALT_VOTED, 2733 .clkr = { 2734 .enable_reg = 0x4b000, 2735 .enable_mask = BIT(25), 2736 .hw.init = &(const struct clk_init_data) { 2737 .name = "gcc_qupv3_wrap3_s0_clk", 2738 .parent_hws = (const struct clk_hw*[]) { 2739 &gcc_qupv3_wrap3_s0_div_clk_src.clkr.hw, 2740 }, 2741 .num_parents = 1, 2742 .flags = CLK_SET_RATE_PARENT, 2743 .ops = &clk_branch2_ops, 2744 }, 2745 }, 2746 }; 2747 2748 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2749 .halt_reg = 0x23004, 2750 .halt_check = BRANCH_HALT_VOTED, 2751 .hwcg_reg = 0x23004, 2752 .hwcg_bit = 1, 2753 .clkr = { 2754 .enable_reg = 0x4b008, 2755 .enable_mask = BIT(6), 2756 .hw.init = &(const struct clk_init_data) { 2757 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2758 .ops = &clk_branch2_ops, 2759 }, 2760 }, 2761 }; 2762 2763 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2764 .halt_reg = 0x23008, 2765 .halt_check = BRANCH_HALT_VOTED, 2766 .hwcg_reg = 0x23008, 2767 .hwcg_bit = 1, 2768 .clkr = { 2769 .enable_reg = 0x4b008, 2770 .enable_mask = BIT(7), 2771 .hw.init = &(const struct clk_init_data) { 2772 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2773 .ops = &clk_branch2_ops, 2774 }, 2775 }, 2776 }; 2777 2778 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2779 .halt_reg = 0x24004, 2780 .halt_check = BRANCH_HALT_VOTED, 2781 .hwcg_reg = 0x24004, 2782 .hwcg_bit = 1, 2783 .clkr = { 2784 .enable_reg = 0x4b008, 2785 .enable_mask = BIT(20), 2786 .hw.init = &(const struct clk_init_data) { 2787 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2788 .ops = &clk_branch2_ops, 2789 }, 2790 }, 2791 }; 2792 2793 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2794 .halt_reg = 0x24008, 2795 .halt_check = BRANCH_HALT_VOTED, 2796 .hwcg_reg = 0x24008, 2797 .hwcg_bit = 1, 2798 .clkr = { 2799 .enable_reg = 0x4b008, 2800 .enable_mask = BIT(21), 2801 .hw.init = &(const struct clk_init_data) { 2802 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2803 .ops = &clk_branch2_ops, 2804 }, 2805 }, 2806 }; 2807 2808 static struct clk_branch gcc_qupv3_wrap_3_m_ahb_clk = { 2809 .halt_reg = 0xc4004, 2810 .halt_check = BRANCH_HALT_VOTED, 2811 .hwcg_reg = 0xc4004, 2812 .hwcg_bit = 1, 2813 .clkr = { 2814 .enable_reg = 0x4b000, 2815 .enable_mask = BIT(27), 2816 .hw.init = &(const struct clk_init_data) { 2817 .name = "gcc_qupv3_wrap_3_m_ahb_clk", 2818 .ops = &clk_branch2_ops, 2819 }, 2820 }, 2821 }; 2822 2823 static struct clk_branch gcc_qupv3_wrap_3_s_ahb_clk = { 2824 .halt_reg = 0xc4008, 2825 .halt_check = BRANCH_HALT_VOTED, 2826 .hwcg_reg = 0xc4008, 2827 .hwcg_bit = 1, 2828 .clkr = { 2829 .enable_reg = 0x4b000, 2830 .enable_mask = BIT(20), 2831 .hw.init = &(const struct clk_init_data) { 2832 .name = "gcc_qupv3_wrap_3_s_ahb_clk", 2833 .ops = &clk_branch2_ops, 2834 }, 2835 }, 2836 }; 2837 2838 static struct clk_branch gcc_sdcc1_ahb_clk = { 2839 .halt_reg = 0x2000c, 2840 .halt_check = BRANCH_HALT, 2841 .clkr = { 2842 .enable_reg = 0x2000c, 2843 .enable_mask = BIT(0), 2844 .hw.init = &(const struct clk_init_data) { 2845 .name = "gcc_sdcc1_ahb_clk", 2846 .ops = &clk_branch2_ops, 2847 }, 2848 }, 2849 }; 2850 2851 static struct clk_branch gcc_sdcc1_apps_clk = { 2852 .halt_reg = 0x20004, 2853 .halt_check = BRANCH_HALT, 2854 .clkr = { 2855 .enable_reg = 0x20004, 2856 .enable_mask = BIT(0), 2857 .hw.init = &(const struct clk_init_data) { 2858 .name = "gcc_sdcc1_apps_clk", 2859 .parent_hws = (const struct clk_hw*[]) { 2860 &gcc_sdcc1_apps_clk_src.clkr.hw, 2861 }, 2862 .num_parents = 1, 2863 .flags = CLK_SET_RATE_PARENT, 2864 .ops = &clk_branch2_ops, 2865 }, 2866 }, 2867 }; 2868 2869 static struct clk_branch gcc_sdcc1_ice_core_clk = { 2870 .halt_reg = 0x20044, 2871 .halt_check = BRANCH_HALT_VOTED, 2872 .hwcg_reg = 0x20044, 2873 .hwcg_bit = 1, 2874 .clkr = { 2875 .enable_reg = 0x20044, 2876 .enable_mask = BIT(0), 2877 .hw.init = &(const struct clk_init_data) { 2878 .name = "gcc_sdcc1_ice_core_clk", 2879 .parent_hws = (const struct clk_hw*[]) { 2880 &gcc_sdcc1_ice_core_clk_src.clkr.hw, 2881 }, 2882 .num_parents = 1, 2883 .flags = CLK_SET_RATE_PARENT, 2884 .ops = &clk_branch2_ops, 2885 }, 2886 }, 2887 }; 2888 2889 static struct clk_branch gcc_sgmi_clkref_en = { 2890 .halt_reg = 0x97034, 2891 .halt_check = BRANCH_HALT_DELAY, 2892 .clkr = { 2893 .enable_reg = 0x97034, 2894 .enable_mask = BIT(0), 2895 .hw.init = &(const struct clk_init_data) { 2896 .name = "gcc_sgmi_clkref_en", 2897 .ops = &clk_branch2_ops, 2898 }, 2899 }, 2900 }; 2901 2902 static struct clk_branch gcc_ufs_phy_ahb_clk = { 2903 .halt_reg = 0x83020, 2904 .halt_check = BRANCH_HALT_VOTED, 2905 .hwcg_reg = 0x83020, 2906 .hwcg_bit = 1, 2907 .clkr = { 2908 .enable_reg = 0x83020, 2909 .enable_mask = BIT(0), 2910 .hw.init = &(const struct clk_init_data) { 2911 .name = "gcc_ufs_phy_ahb_clk", 2912 .ops = &clk_branch2_ops, 2913 }, 2914 }, 2915 }; 2916 2917 static struct clk_branch gcc_ufs_phy_axi_clk = { 2918 .halt_reg = 0x83018, 2919 .halt_check = BRANCH_HALT_VOTED, 2920 .hwcg_reg = 0x83018, 2921 .hwcg_bit = 1, 2922 .clkr = { 2923 .enable_reg = 0x83018, 2924 .enable_mask = BIT(0), 2925 .hw.init = &(const struct clk_init_data) { 2926 .name = "gcc_ufs_phy_axi_clk", 2927 .parent_hws = (const struct clk_hw*[]) { 2928 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2929 }, 2930 .num_parents = 1, 2931 .flags = CLK_SET_RATE_PARENT, 2932 .ops = &clk_branch2_ops, 2933 }, 2934 }, 2935 }; 2936 2937 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2938 .halt_reg = 0x8306c, 2939 .halt_check = BRANCH_HALT_VOTED, 2940 .hwcg_reg = 0x8306c, 2941 .hwcg_bit = 1, 2942 .clkr = { 2943 .enable_reg = 0x8306c, 2944 .enable_mask = BIT(0), 2945 .hw.init = &(const struct clk_init_data) { 2946 .name = "gcc_ufs_phy_ice_core_clk", 2947 .parent_hws = (const struct clk_hw*[]) { 2948 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2949 }, 2950 .num_parents = 1, 2951 .flags = CLK_SET_RATE_PARENT, 2952 .ops = &clk_branch2_ops, 2953 }, 2954 }, 2955 }; 2956 2957 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2958 .halt_reg = 0x830a4, 2959 .halt_check = BRANCH_HALT_VOTED, 2960 .hwcg_reg = 0x830a4, 2961 .hwcg_bit = 1, 2962 .clkr = { 2963 .enable_reg = 0x830a4, 2964 .enable_mask = BIT(0), 2965 .hw.init = &(const struct clk_init_data) { 2966 .name = "gcc_ufs_phy_phy_aux_clk", 2967 .parent_hws = (const struct clk_hw*[]) { 2968 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2969 }, 2970 .num_parents = 1, 2971 .flags = CLK_SET_RATE_PARENT, 2972 .ops = &clk_branch2_ops, 2973 }, 2974 }, 2975 }; 2976 2977 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2978 .halt_reg = 0x83028, 2979 .halt_check = BRANCH_HALT_DELAY, 2980 .clkr = { 2981 .enable_reg = 0x83028, 2982 .enable_mask = BIT(0), 2983 .hw.init = &(const struct clk_init_data) { 2984 .name = "gcc_ufs_phy_rx_symbol_0_clk", 2985 .parent_hws = (const struct clk_hw*[]) { 2986 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, 2987 }, 2988 .num_parents = 1, 2989 .flags = CLK_SET_RATE_PARENT, 2990 .ops = &clk_branch2_ops, 2991 }, 2992 }, 2993 }; 2994 2995 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 2996 .halt_reg = 0x830c0, 2997 .halt_check = BRANCH_HALT_DELAY, 2998 .clkr = { 2999 .enable_reg = 0x830c0, 3000 .enable_mask = BIT(0), 3001 .hw.init = &(const struct clk_init_data) { 3002 .name = "gcc_ufs_phy_rx_symbol_1_clk", 3003 .parent_hws = (const struct clk_hw*[]) { 3004 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, 3005 }, 3006 .num_parents = 1, 3007 .flags = CLK_SET_RATE_PARENT, 3008 .ops = &clk_branch2_ops, 3009 }, 3010 }, 3011 }; 3012 3013 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 3014 .halt_reg = 0x83024, 3015 .halt_check = BRANCH_HALT_DELAY, 3016 .clkr = { 3017 .enable_reg = 0x83024, 3018 .enable_mask = BIT(0), 3019 .hw.init = &(const struct clk_init_data) { 3020 .name = "gcc_ufs_phy_tx_symbol_0_clk", 3021 .parent_hws = (const struct clk_hw*[]) { 3022 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, 3023 }, 3024 .num_parents = 1, 3025 .flags = CLK_SET_RATE_PARENT, 3026 .ops = &clk_branch2_ops, 3027 }, 3028 }, 3029 }; 3030 3031 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 3032 .halt_reg = 0x83064, 3033 .halt_check = BRANCH_HALT_VOTED, 3034 .hwcg_reg = 0x83064, 3035 .hwcg_bit = 1, 3036 .clkr = { 3037 .enable_reg = 0x83064, 3038 .enable_mask = BIT(0), 3039 .hw.init = &(const struct clk_init_data) { 3040 .name = "gcc_ufs_phy_unipro_core_clk", 3041 .parent_hws = (const struct clk_hw*[]) { 3042 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 3043 }, 3044 .num_parents = 1, 3045 .flags = CLK_SET_RATE_PARENT, 3046 .ops = &clk_branch2_ops, 3047 }, 3048 }, 3049 }; 3050 3051 static struct clk_branch gcc_usb20_master_clk = { 3052 .halt_reg = 0x1c018, 3053 .halt_check = BRANCH_HALT, 3054 .clkr = { 3055 .enable_reg = 0x1c018, 3056 .enable_mask = BIT(0), 3057 .hw.init = &(const struct clk_init_data) { 3058 .name = "gcc_usb20_master_clk", 3059 .parent_hws = (const struct clk_hw*[]) { 3060 &gcc_usb20_master_clk_src.clkr.hw, 3061 }, 3062 .num_parents = 1, 3063 .flags = CLK_SET_RATE_PARENT, 3064 .ops = &clk_branch2_ops, 3065 }, 3066 }, 3067 }; 3068 3069 static struct clk_branch gcc_usb20_mock_utmi_clk = { 3070 .halt_reg = 0x1c024, 3071 .halt_check = BRANCH_HALT, 3072 .clkr = { 3073 .enable_reg = 0x1c024, 3074 .enable_mask = BIT(0), 3075 .hw.init = &(const struct clk_init_data) { 3076 .name = "gcc_usb20_mock_utmi_clk", 3077 .parent_hws = (const struct clk_hw*[]) { 3078 &gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw, 3079 }, 3080 .num_parents = 1, 3081 .flags = CLK_SET_RATE_PARENT, 3082 .ops = &clk_branch2_ops, 3083 }, 3084 }, 3085 }; 3086 3087 static struct clk_branch gcc_usb20_sleep_clk = { 3088 .halt_reg = 0x1c020, 3089 .halt_check = BRANCH_HALT, 3090 .clkr = { 3091 .enable_reg = 0x1c020, 3092 .enable_mask = BIT(0), 3093 .hw.init = &(const struct clk_init_data) { 3094 .name = "gcc_usb20_sleep_clk", 3095 .ops = &clk_branch2_ops, 3096 }, 3097 }, 3098 }; 3099 3100 static struct clk_branch gcc_usb30_prim_master_clk = { 3101 .halt_reg = 0x1b018, 3102 .halt_check = BRANCH_HALT, 3103 .clkr = { 3104 .enable_reg = 0x1b018, 3105 .enable_mask = BIT(0), 3106 .hw.init = &(const struct clk_init_data) { 3107 .name = "gcc_usb30_prim_master_clk", 3108 .parent_hws = (const struct clk_hw*[]) { 3109 &gcc_usb30_prim_master_clk_src.clkr.hw, 3110 }, 3111 .num_parents = 1, 3112 .flags = CLK_SET_RATE_PARENT, 3113 .ops = &clk_branch2_ops, 3114 }, 3115 }, 3116 }; 3117 3118 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 3119 .halt_reg = 0x1b024, 3120 .halt_check = BRANCH_HALT, 3121 .clkr = { 3122 .enable_reg = 0x1b024, 3123 .enable_mask = BIT(0), 3124 .hw.init = &(const struct clk_init_data) { 3125 .name = "gcc_usb30_prim_mock_utmi_clk", 3126 .parent_hws = (const struct clk_hw*[]) { 3127 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 3128 }, 3129 .num_parents = 1, 3130 .flags = CLK_SET_RATE_PARENT, 3131 .ops = &clk_branch2_ops, 3132 }, 3133 }, 3134 }; 3135 3136 static struct clk_branch gcc_usb30_prim_sleep_clk = { 3137 .halt_reg = 0x1b020, 3138 .halt_check = BRANCH_HALT, 3139 .clkr = { 3140 .enable_reg = 0x1b020, 3141 .enable_mask = BIT(0), 3142 .hw.init = &(const struct clk_init_data) { 3143 .name = "gcc_usb30_prim_sleep_clk", 3144 .ops = &clk_branch2_ops, 3145 }, 3146 }, 3147 }; 3148 3149 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 3150 .halt_reg = 0x1b05c, 3151 .halt_check = BRANCH_HALT, 3152 .clkr = { 3153 .enable_reg = 0x1b05c, 3154 .enable_mask = BIT(0), 3155 .hw.init = &(const struct clk_init_data) { 3156 .name = "gcc_usb3_prim_phy_aux_clk", 3157 .parent_hws = (const struct clk_hw*[]) { 3158 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3159 }, 3160 .num_parents = 1, 3161 .flags = CLK_SET_RATE_PARENT, 3162 .ops = &clk_branch2_ops, 3163 }, 3164 }, 3165 }; 3166 3167 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 3168 .halt_reg = 0x1b060, 3169 .halt_check = BRANCH_HALT, 3170 .clkr = { 3171 .enable_reg = 0x1b060, 3172 .enable_mask = BIT(0), 3173 .hw.init = &(const struct clk_init_data) { 3174 .name = "gcc_usb3_prim_phy_com_aux_clk", 3175 .parent_hws = (const struct clk_hw*[]) { 3176 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3177 }, 3178 .num_parents = 1, 3179 .flags = CLK_SET_RATE_PARENT, 3180 .ops = &clk_branch2_ops, 3181 }, 3182 }, 3183 }; 3184 3185 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 3186 .halt_reg = 0x1b064, 3187 .halt_check = BRANCH_HALT_DELAY, 3188 .hwcg_reg = 0x1b064, 3189 .hwcg_bit = 1, 3190 .clkr = { 3191 .enable_reg = 0x1b064, 3192 .enable_mask = BIT(0), 3193 .hw.init = &(const struct clk_init_data) { 3194 .name = "gcc_usb3_prim_phy_pipe_clk", 3195 .parent_hws = (const struct clk_hw*[]) { 3196 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 3197 }, 3198 .num_parents = 1, 3199 .flags = CLK_SET_RATE_PARENT, 3200 .ops = &clk_branch2_ops, 3201 }, 3202 }, 3203 }; 3204 3205 static struct clk_branch gcc_usb_clkref_en = { 3206 .halt_reg = 0x97468, 3207 .halt_check = BRANCH_HALT_DELAY, 3208 .clkr = { 3209 .enable_reg = 0x97468, 3210 .enable_mask = BIT(0), 3211 .hw.init = &(const struct clk_init_data) { 3212 .name = "gcc_usb_clkref_en", 3213 .ops = &clk_branch2_ops, 3214 }, 3215 }, 3216 }; 3217 3218 static struct clk_branch gcc_video_axi0_clk = { 3219 .halt_reg = 0x34014, 3220 .halt_check = BRANCH_HALT_VOTED, 3221 .hwcg_reg = 0x34014, 3222 .hwcg_bit = 1, 3223 .clkr = { 3224 .enable_reg = 0x34014, 3225 .enable_mask = BIT(0), 3226 .hw.init = &(const struct clk_init_data) { 3227 .name = "gcc_video_axi0_clk", 3228 .ops = &clk_branch2_ops, 3229 }, 3230 }, 3231 }; 3232 3233 static struct clk_branch gcc_video_axi1_clk = { 3234 .halt_reg = 0x3401c, 3235 .halt_check = BRANCH_HALT_VOTED, 3236 .hwcg_reg = 0x3401c, 3237 .hwcg_bit = 1, 3238 .clkr = { 3239 .enable_reg = 0x3401c, 3240 .enable_mask = BIT(0), 3241 .hw.init = &(const struct clk_init_data) { 3242 .name = "gcc_video_axi1_clk", 3243 .ops = &clk_branch2_ops, 3244 }, 3245 }, 3246 }; 3247 3248 static struct gdsc gcc_emac0_gdsc = { 3249 .gdscr = 0xb6004, 3250 .en_rest_wait_val = 0x2, 3251 .en_few_wait_val = 0x2, 3252 .clk_dis_wait_val = 0xf, 3253 .pd = { 3254 .name = "gcc_emac0_gdsc", 3255 }, 3256 .pwrsts = PWRSTS_OFF_ON, 3257 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3258 }; 3259 3260 static struct gdsc gcc_pcie_0_gdsc = { 3261 .gdscr = 0xa9004, 3262 .collapse_ctrl = 0x4b104, 3263 .collapse_mask = BIT(0), 3264 .en_rest_wait_val = 0x2, 3265 .en_few_wait_val = 0x2, 3266 .clk_dis_wait_val = 0xf, 3267 .pd = { 3268 .name = "gcc_pcie_0_gdsc", 3269 }, 3270 .pwrsts = PWRSTS_RET_ON, 3271 .flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 3272 }; 3273 3274 static struct gdsc gcc_pcie_1_gdsc = { 3275 .gdscr = 0x77004, 3276 .collapse_ctrl = 0x4b104, 3277 .collapse_mask = BIT(1), 3278 .en_rest_wait_val = 0x2, 3279 .en_few_wait_val = 0x2, 3280 .clk_dis_wait_val = 0xf, 3281 .pd = { 3282 .name = "gcc_pcie_1_gdsc", 3283 }, 3284 .pwrsts = PWRSTS_RET_ON, 3285 .flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 3286 }; 3287 3288 static struct gdsc gcc_ufs_phy_gdsc = { 3289 .gdscr = 0x83004, 3290 .en_rest_wait_val = 0x2, 3291 .en_few_wait_val = 0x2, 3292 .clk_dis_wait_val = 0xf, 3293 .pd = { 3294 .name = "gcc_ufs_phy_gdsc", 3295 }, 3296 .pwrsts = PWRSTS_OFF_ON, 3297 .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 3298 }; 3299 3300 static struct gdsc gcc_usb20_prim_gdsc = { 3301 .gdscr = 0x1c004, 3302 .en_rest_wait_val = 0x2, 3303 .en_few_wait_val = 0x2, 3304 .clk_dis_wait_val = 0xf, 3305 .pd = { 3306 .name = "gcc_usb20_prim_gdsc", 3307 }, 3308 .pwrsts = PWRSTS_RET_ON, 3309 .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 3310 }; 3311 3312 static struct gdsc gcc_usb30_prim_gdsc = { 3313 .gdscr = 0x1b004, 3314 .en_rest_wait_val = 0x2, 3315 .en_few_wait_val = 0x2, 3316 .clk_dis_wait_val = 0xf, 3317 .pd = { 3318 .name = "gcc_usb30_prim_gdsc", 3319 }, 3320 .pwrsts = PWRSTS_RET_ON, 3321 .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 3322 }; 3323 3324 static struct clk_regmap *gcc_qcs8300_clocks[] = { 3325 [GCC_AGGRE_NOC_QUPV3_AXI_CLK] = &gcc_aggre_noc_qupv3_axi_clk.clkr, 3326 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 3327 [GCC_AGGRE_USB2_PRIM_AXI_CLK] = &gcc_aggre_usb2_prim_axi_clk.clkr, 3328 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 3329 [GCC_AHB2PHY0_CLK] = &gcc_ahb2phy0_clk.clkr, 3330 [GCC_AHB2PHY2_CLK] = &gcc_ahb2phy2_clk.clkr, 3331 [GCC_AHB2PHY3_CLK] = &gcc_ahb2phy3_clk.clkr, 3332 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3333 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 3334 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 3335 [GCC_CAMERA_THROTTLE_XO_CLK] = &gcc_camera_throttle_xo_clk.clkr, 3336 [GCC_CFG_NOC_USB2_PRIM_AXI_CLK] = &gcc_cfg_noc_usb2_prim_axi_clk.clkr, 3337 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3338 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 3339 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3340 [GCC_EDP_REF_CLKREF_EN] = &gcc_edp_ref_clkref_en.clkr, 3341 [GCC_EMAC0_AXI_CLK] = &gcc_emac0_axi_clk.clkr, 3342 [GCC_EMAC0_PHY_AUX_CLK] = &gcc_emac0_phy_aux_clk.clkr, 3343 [GCC_EMAC0_PHY_AUX_CLK_SRC] = &gcc_emac0_phy_aux_clk_src.clkr, 3344 [GCC_EMAC0_PTP_CLK] = &gcc_emac0_ptp_clk.clkr, 3345 [GCC_EMAC0_PTP_CLK_SRC] = &gcc_emac0_ptp_clk_src.clkr, 3346 [GCC_EMAC0_RGMII_CLK] = &gcc_emac0_rgmii_clk.clkr, 3347 [GCC_EMAC0_RGMII_CLK_SRC] = &gcc_emac0_rgmii_clk_src.clkr, 3348 [GCC_EMAC0_SLV_AHB_CLK] = &gcc_emac0_slv_ahb_clk.clkr, 3349 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3350 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3351 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3352 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3353 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3354 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3355 [GCC_GP4_CLK] = &gcc_gp4_clk.clkr, 3356 [GCC_GP4_CLK_SRC] = &gcc_gp4_clk_src.clkr, 3357 [GCC_GP5_CLK] = &gcc_gp5_clk.clkr, 3358 [GCC_GP5_CLK_SRC] = &gcc_gp5_clk_src.clkr, 3359 [GCC_GPLL0] = &gcc_gpll0.clkr, 3360 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 3361 [GCC_GPLL1] = &gcc_gpll1.clkr, 3362 [GCC_GPLL4] = &gcc_gpll4.clkr, 3363 [GCC_GPLL7] = &gcc_gpll7.clkr, 3364 [GCC_GPLL9] = &gcc_gpll9.clkr, 3365 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3366 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3367 [GCC_GPU_MEMNOC_GFX_CENTER_PIPELINE_CLK] = &gcc_gpu_memnoc_gfx_center_pipeline_clk.clkr, 3368 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3369 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3370 [GCC_GPU_TCU_THROTTLE_AHB_CLK] = &gcc_gpu_tcu_throttle_ahb_clk.clkr, 3371 [GCC_GPU_TCU_THROTTLE_CLK] = &gcc_gpu_tcu_throttle_clk.clkr, 3372 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 3373 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 3374 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 3375 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 3376 [GCC_PCIE_0_PHY_AUX_CLK] = &gcc_pcie_0_phy_aux_clk.clkr, 3377 [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, 3378 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 3379 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 3380 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 3381 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 3382 [GCC_PCIE_0_PIPE_DIV_CLK_SRC] = &gcc_pcie_0_pipe_div_clk_src.clkr, 3383 [GCC_PCIE_0_PIPEDIV2_CLK] = &gcc_pcie_0_pipediv2_clk.clkr, 3384 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 3385 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 3386 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 3387 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 3388 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 3389 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 3390 [GCC_PCIE_1_PHY_AUX_CLK] = &gcc_pcie_1_phy_aux_clk.clkr, 3391 [GCC_PCIE_1_PHY_AUX_CLK_SRC] = &gcc_pcie_1_phy_aux_clk_src.clkr, 3392 [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr, 3393 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, 3394 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 3395 [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr, 3396 [GCC_PCIE_1_PIPE_DIV_CLK_SRC] = &gcc_pcie_1_pipe_div_clk_src.clkr, 3397 [GCC_PCIE_1_PIPEDIV2_CLK] = &gcc_pcie_1_pipediv2_clk.clkr, 3398 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 3399 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 3400 [GCC_PCIE_CLKREF_EN] = &gcc_pcie_clkref_en.clkr, 3401 [GCC_PCIE_THROTTLE_CFG_CLK] = &gcc_pcie_throttle_cfg_clk.clkr, 3402 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3403 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3404 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3405 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3406 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3407 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3408 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3409 [GCC_QMIP_DISP_ROT_AHB_CLK] = &gcc_qmip_disp_rot_ahb_clk.clkr, 3410 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 3411 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3412 [GCC_QMIP_VIDEO_VCPU_AHB_CLK] = &gcc_qmip_video_vcpu_ahb_clk.clkr, 3413 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 3414 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 3415 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3416 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3417 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3418 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3419 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3420 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3421 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3422 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3423 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3424 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3425 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3426 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3427 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 3428 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 3429 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 3430 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 3431 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 3432 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 3433 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3434 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3435 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3436 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3437 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3438 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3439 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3440 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3441 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3442 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3443 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3444 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3445 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 3446 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 3447 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 3448 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 3449 [GCC_QUPV3_WRAP3_CORE_2X_CLK] = &gcc_qupv3_wrap3_core_2x_clk.clkr, 3450 [GCC_QUPV3_WRAP3_CORE_CLK] = &gcc_qupv3_wrap3_core_clk.clkr, 3451 [GCC_QUPV3_WRAP3_QSPI_CLK] = &gcc_qupv3_wrap3_qspi_clk.clkr, 3452 [GCC_QUPV3_WRAP3_S0_CLK] = &gcc_qupv3_wrap3_s0_clk.clkr, 3453 [GCC_QUPV3_WRAP3_S0_CLK_SRC] = &gcc_qupv3_wrap3_s0_clk_src.clkr, 3454 [GCC_QUPV3_WRAP3_S0_DIV_CLK_SRC] = &gcc_qupv3_wrap3_s0_div_clk_src.clkr, 3455 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3456 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3457 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 3458 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3459 [GCC_QUPV3_WRAP_3_M_AHB_CLK] = &gcc_qupv3_wrap_3_m_ahb_clk.clkr, 3460 [GCC_QUPV3_WRAP_3_S_AHB_CLK] = &gcc_qupv3_wrap_3_s_ahb_clk.clkr, 3461 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 3462 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 3463 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 3464 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 3465 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 3466 [GCC_SGMI_CLKREF_EN] = &gcc_sgmi_clkref_en.clkr, 3467 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3468 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3469 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3470 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3471 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3472 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3473 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3474 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3475 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr, 3476 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 3477 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr, 3478 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3479 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr, 3480 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3481 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 3482 [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr, 3483 [GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr, 3484 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr, 3485 [GCC_USB20_MOCK_UTMI_CLK_SRC] = &gcc_usb20_mock_utmi_clk_src.clkr, 3486 [GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb20_mock_utmi_postdiv_clk_src.clkr, 3487 [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr, 3488 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3489 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3490 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3491 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3492 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3493 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3494 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 3495 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3496 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3497 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3498 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 3499 [GCC_USB_CLKREF_EN] = &gcc_usb_clkref_en.clkr, 3500 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3501 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 3502 }; 3503 3504 static struct gdsc *gcc_qcs8300_gdscs[] = { 3505 [GCC_EMAC0_GDSC] = &gcc_emac0_gdsc, 3506 [GCC_PCIE_0_GDSC] = &gcc_pcie_0_gdsc, 3507 [GCC_PCIE_1_GDSC] = &gcc_pcie_1_gdsc, 3508 [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc, 3509 [GCC_USB20_PRIM_GDSC] = &gcc_usb20_prim_gdsc, 3510 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, 3511 }; 3512 3513 static const struct qcom_reset_map gcc_qcs8300_resets[] = { 3514 [GCC_EMAC0_BCR] = { 0xb6000 }, 3515 [GCC_PCIE_0_BCR] = { 0xa9000 }, 3516 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0xbf000 }, 3517 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0xbf008 }, 3518 [GCC_PCIE_0_PHY_BCR] = { 0xa9144 }, 3519 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0xbf00c }, 3520 [GCC_PCIE_1_BCR] = { 0x77000 }, 3521 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0xae084 }, 3522 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0xae090 }, 3523 [GCC_PCIE_1_PHY_BCR] = { 0xae08c }, 3524 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0xae094 }, 3525 [GCC_SDCC1_BCR] = { 0x20000 }, 3526 [GCC_UFS_PHY_BCR] = { 0x83000 }, 3527 [GCC_USB20_PRIM_BCR] = { 0x1c000 }, 3528 [GCC_USB2_PHY_PRIM_BCR] = { 0x5c01c }, 3529 [GCC_USB2_PHY_SEC_BCR] = { 0x5c020 }, 3530 [GCC_USB30_PRIM_BCR] = { 0x1b000 }, 3531 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x5c008 }, 3532 [GCC_USB3_PHY_PRIM_BCR] = { 0x5c000 }, 3533 [GCC_USB3_PHY_TERT_BCR] = { 0x5c024 }, 3534 [GCC_USB3_UNIPHY_MP0_BCR] = { 0x5c00c }, 3535 [GCC_USB3_UNIPHY_MP1_BCR] = { 0x5c010 }, 3536 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x5c004 }, 3537 [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x5c014 }, 3538 [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x5c018 }, 3539 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x76000 }, 3540 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x34014, 2 }, 3541 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x3401c, 2 }, 3542 [GCC_VIDEO_BCR] = { 0x34000 }, 3543 }; 3544 3545 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3546 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 3547 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 3548 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 3549 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 3550 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 3551 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 3552 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 3553 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 3554 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3555 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3556 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 3557 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3558 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3559 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3560 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 3561 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 3562 DEFINE_RCG_DFS(gcc_qupv3_wrap3_s0_clk_src), 3563 }; 3564 3565 static const struct regmap_config gcc_qcs8300_regmap_config = { 3566 .reg_bits = 32, 3567 .reg_stride = 4, 3568 .val_bits = 32, 3569 .max_register = 0x472cffc, 3570 .fast_io = true, 3571 }; 3572 3573 static const struct qcom_cc_desc gcc_qcs8300_desc = { 3574 .config = &gcc_qcs8300_regmap_config, 3575 .clks = gcc_qcs8300_clocks, 3576 .num_clks = ARRAY_SIZE(gcc_qcs8300_clocks), 3577 .resets = gcc_qcs8300_resets, 3578 .num_resets = ARRAY_SIZE(gcc_qcs8300_resets), 3579 .gdscs = gcc_qcs8300_gdscs, 3580 .num_gdscs = ARRAY_SIZE(gcc_qcs8300_gdscs), 3581 }; 3582 3583 static const struct of_device_id gcc_qcs8300_match_table[] = { 3584 { .compatible = "qcom,qcs8300-gcc" }, 3585 { } 3586 }; 3587 MODULE_DEVICE_TABLE(of, gcc_qcs8300_match_table); 3588 3589 static int gcc_qcs8300_probe(struct platform_device *pdev) 3590 { 3591 struct regmap *regmap; 3592 int ret; 3593 3594 regmap = qcom_cc_map(pdev, &gcc_qcs8300_desc); 3595 if (IS_ERR(regmap)) 3596 return PTR_ERR(regmap); 3597 3598 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3599 ARRAY_SIZE(gcc_dfs_clocks)); 3600 if (ret) 3601 return ret; 3602 3603 /* Keep some clocks always enabled */ 3604 qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_CAMERA_AHB_CLK */ 3605 qcom_branch_set_clk_en(regmap, 0x32020); /* GCC_CAMERA_XO_CLK */ 3606 qcom_branch_set_clk_en(regmap, 0x33004); /* GCC_DISP_AHB_CLK */ 3607 qcom_branch_set_clk_en(regmap, 0x33018); /* GCC_DISP_XO_CLK */ 3608 qcom_branch_set_clk_en(regmap, 0x7d004); /* GCC_GPU_CFG_AHB_CLK */ 3609 qcom_branch_set_clk_en(regmap, 0x34004); /* GCC_VIDEO_AHB_CLK */ 3610 qcom_branch_set_clk_en(regmap, 0x34024); /* GCC_VIDEO_XO_CLK */ 3611 3612 /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ 3613 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); 3614 3615 return qcom_cc_really_probe(&pdev->dev, &gcc_qcs8300_desc, regmap); 3616 } 3617 3618 static struct platform_driver gcc_qcs8300_driver = { 3619 .probe = gcc_qcs8300_probe, 3620 .driver = { 3621 .name = "gcc-qcs8300", 3622 .of_match_table = gcc_qcs8300_match_table, 3623 }, 3624 }; 3625 3626 static int __init gcc_qcs8300_init(void) 3627 { 3628 return platform_driver_register(&gcc_qcs8300_driver); 3629 } 3630 subsys_initcall(gcc_qcs8300_init); 3631 3632 static void __exit gcc_qcs8300_exit(void) 3633 { 3634 platform_driver_unregister(&gcc_qcs8300_driver); 3635 } 3636 module_exit(gcc_qcs8300_exit); 3637 3638 MODULE_DESCRIPTION("QTI GCC QCS8300 Driver"); 3639 MODULE_LICENSE("GPL"); 3640