1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/of.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,qcs615-gcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "clk-regmap-divider.h" 19 #include "clk-regmap-mux.h" 20 #include "common.h" 21 #include "gdsc.h" 22 #include "reset.h" 23 24 enum { 25 DT_BI_TCXO, 26 DT_BI_TCXO_AO, 27 DT_SLEEP_CLK, 28 }; 29 30 enum { 31 P_BI_TCXO, 32 P_GPLL0_OUT_AUX2_DIV, 33 P_GPLL0_OUT_MAIN, 34 P_GPLL3_OUT_MAIN, 35 P_GPLL3_OUT_MAIN_DIV, 36 P_GPLL4_OUT_MAIN, 37 P_GPLL6_OUT_MAIN, 38 P_GPLL7_OUT_MAIN, 39 P_GPLL8_OUT_MAIN, 40 P_SLEEP_CLK, 41 }; 42 43 static struct clk_alpha_pll gpll0 = { 44 .offset = 0x0, 45 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 46 .clkr = { 47 .enable_reg = 0x52000, 48 .enable_mask = BIT(0), 49 .hw.init = &(const struct clk_init_data) { 50 .name = "gpll0", 51 .parent_data = &(const struct clk_parent_data) { 52 .index = DT_BI_TCXO, 53 }, 54 .num_parents = 1, 55 .ops = &clk_alpha_pll_ops, 56 }, 57 }, 58 }; 59 60 /* Fixed divider clock of GPLL0 instead of PLL normal postdiv */ 61 static struct clk_fixed_factor gpll0_out_aux2_div = { 62 .mult = 1, 63 .div = 2, 64 .hw.init = &(struct clk_init_data) { 65 .name = "gpll0_out_aux2_div", 66 .parent_data = &(const struct clk_parent_data) { 67 .hw = &gpll0.clkr.hw, 68 }, 69 .num_parents = 1, 70 .ops = &clk_fixed_factor_ops, 71 }, 72 }; 73 74 static struct clk_alpha_pll gpll3 = { 75 .offset = 0x3000, 76 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 77 .clkr = { 78 .enable_reg = 0x52000, 79 .enable_mask = BIT(3), 80 .hw.init = &(const struct clk_init_data) { 81 .name = "gpll3", 82 .parent_data = &(const struct clk_parent_data) { 83 .index = DT_BI_TCXO, 84 }, 85 .num_parents = 1, 86 .ops = &clk_alpha_pll_ops, 87 }, 88 }, 89 }; 90 91 /* Fixed divider clock of GPLL3 instead of PLL normal postdiv */ 92 static struct clk_fixed_factor gpll3_out_aux2_div = { 93 .mult = 1, 94 .div = 2, 95 .hw.init = &(struct clk_init_data) { 96 .name = "gpll3_out_aux2_div", 97 .parent_data = &(const struct clk_parent_data) { 98 .hw = &gpll3.clkr.hw, 99 }, 100 .num_parents = 1, 101 .ops = &clk_fixed_factor_ops, 102 }, 103 }; 104 105 static struct clk_alpha_pll gpll4 = { 106 .offset = 0x76000, 107 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 108 .clkr = { 109 .enable_reg = 0x52000, 110 .enable_mask = BIT(4), 111 .hw.init = &(const struct clk_init_data) { 112 .name = "gpll4", 113 .parent_data = &(const struct clk_parent_data) { 114 .index = DT_BI_TCXO, 115 }, 116 .num_parents = 1, 117 .ops = &clk_alpha_pll_ops, 118 }, 119 }, 120 }; 121 122 static struct clk_alpha_pll gpll6 = { 123 .offset = 0x13000, 124 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 125 .clkr = { 126 .enable_reg = 0x52000, 127 .enable_mask = BIT(6), 128 .hw.init = &(const struct clk_init_data) { 129 .name = "gpll6", 130 .parent_data = &(const struct clk_parent_data) { 131 .index = DT_BI_TCXO, 132 }, 133 .num_parents = 1, 134 .ops = &clk_alpha_pll_ops, 135 }, 136 }, 137 }; 138 139 static const struct clk_div_table post_div_table_gpll6_out_main[] = { 140 { 0x1, 2 }, 141 { } 142 }; 143 144 static struct clk_alpha_pll_postdiv gpll6_out_main = { 145 .offset = 0x13000, 146 .post_div_shift = 8, 147 .post_div_table = post_div_table_gpll6_out_main, 148 .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main), 149 .width = 4, 150 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 151 .clkr.hw.init = &(const struct clk_init_data) { 152 .name = "gpll6_out_main", 153 .parent_hws = (const struct clk_hw*[]) { 154 &gpll6.clkr.hw, 155 }, 156 .num_parents = 1, 157 .ops = &clk_alpha_pll_postdiv_ops, 158 }, 159 }; 160 161 static struct clk_alpha_pll gpll7 = { 162 .offset = 0x1a000, 163 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 164 .clkr = { 165 .enable_reg = 0x52000, 166 .enable_mask = BIT(7), 167 .hw.init = &(const struct clk_init_data) { 168 .name = "gpll7", 169 .parent_data = &(const struct clk_parent_data) { 170 .index = DT_BI_TCXO, 171 }, 172 .num_parents = 1, 173 .ops = &clk_alpha_pll_ops, 174 }, 175 }, 176 }; 177 178 static struct clk_alpha_pll gpll8 = { 179 .offset = 0x1b000, 180 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 181 .clkr = { 182 .enable_reg = 0x52000, 183 .enable_mask = BIT(8), 184 .hw.init = &(const struct clk_init_data) { 185 .name = "gpll8", 186 .parent_data = &(const struct clk_parent_data) { 187 .index = DT_BI_TCXO, 188 }, 189 .num_parents = 1, 190 .ops = &clk_alpha_pll_ops, 191 }, 192 }, 193 }; 194 195 static const struct clk_div_table post_div_table_gpll8_out_main[] = { 196 { 0x1, 2 }, 197 { } 198 }; 199 200 static struct clk_alpha_pll_postdiv gpll8_out_main = { 201 .offset = 0x1b000, 202 .post_div_shift = 8, 203 .post_div_table = post_div_table_gpll8_out_main, 204 .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main), 205 .width = 4, 206 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 207 .clkr.hw.init = &(const struct clk_init_data) { 208 .name = "gpll8_out_main", 209 .parent_hws = (const struct clk_hw*[]) { 210 &gpll8.clkr.hw, 211 }, 212 .num_parents = 1, 213 .ops = &clk_alpha_pll_postdiv_ops, 214 }, 215 }; 216 217 static const struct parent_map gcc_parent_map_0[] = { 218 { P_BI_TCXO, 0 }, 219 { P_GPLL0_OUT_MAIN, 1 }, 220 { P_GPLL0_OUT_AUX2_DIV, 6 }, 221 }; 222 223 static const struct clk_parent_data gcc_parent_data_0[] = { 224 { .index = DT_BI_TCXO }, 225 { .hw = &gpll0.clkr.hw }, 226 { .hw = &gpll0_out_aux2_div.hw }, 227 }; 228 229 static const struct clk_parent_data gcc_parent_data_0_ao[] = { 230 { .index = DT_BI_TCXO_AO }, 231 { .hw = &gpll0.clkr.hw }, 232 { .hw = &gpll0.clkr.hw }, 233 }; 234 235 static const struct parent_map gcc_parent_map_1[] = { 236 { P_BI_TCXO, 0 }, 237 { P_GPLL0_OUT_MAIN, 1 }, 238 { P_GPLL6_OUT_MAIN, 2 }, 239 { P_GPLL0_OUT_AUX2_DIV, 6 }, 240 }; 241 242 static const struct clk_parent_data gcc_parent_data_1[] = { 243 { .index = DT_BI_TCXO }, 244 { .hw = &gpll0.clkr.hw }, 245 { .hw = &gpll6_out_main.clkr.hw }, 246 { .hw = &gpll0_out_aux2_div.hw }, 247 }; 248 249 static const struct parent_map gcc_parent_map_2[] = { 250 { P_BI_TCXO, 0 }, 251 { P_GPLL0_OUT_MAIN, 1 }, 252 { P_SLEEP_CLK, 5 }, 253 { P_GPLL0_OUT_AUX2_DIV, 6 }, 254 }; 255 256 static const struct clk_parent_data gcc_parent_data_2[] = { 257 { .index = DT_BI_TCXO }, 258 { .hw = &gpll0.clkr.hw }, 259 { .index = DT_SLEEP_CLK }, 260 { .hw = &gpll0_out_aux2_div.hw }, 261 }; 262 263 static const struct parent_map gcc_parent_map_3[] = { 264 { P_BI_TCXO, 0 }, 265 { P_SLEEP_CLK, 5 }, 266 }; 267 268 static const struct clk_parent_data gcc_parent_data_3[] = { 269 { .index = DT_BI_TCXO }, 270 { .index = DT_SLEEP_CLK }, 271 }; 272 273 static const struct parent_map gcc_parent_map_4[] = { 274 { P_BI_TCXO, 0 }, 275 }; 276 277 static const struct clk_parent_data gcc_parent_data_4[] = { 278 { .index = DT_BI_TCXO }, 279 }; 280 281 static const struct parent_map gcc_parent_map_5[] = { 282 { P_BI_TCXO, 0 }, 283 { P_GPLL0_OUT_MAIN, 1 }, 284 { P_GPLL7_OUT_MAIN, 3 }, 285 { P_GPLL4_OUT_MAIN, 5 }, 286 { P_GPLL0_OUT_AUX2_DIV, 6 }, 287 }; 288 289 static const struct clk_parent_data gcc_parent_data_5[] = { 290 { .index = DT_BI_TCXO }, 291 { .hw = &gpll0.clkr.hw }, 292 { .hw = &gpll7.clkr.hw }, 293 { .hw = &gpll4.clkr.hw }, 294 { .hw = &gpll0_out_aux2_div.hw }, 295 }; 296 297 static const struct parent_map gcc_parent_map_6[] = { 298 { P_BI_TCXO, 0 }, 299 { P_GPLL0_OUT_MAIN, 1 }, 300 { P_GPLL7_OUT_MAIN, 3 }, 301 { P_GPLL0_OUT_AUX2_DIV, 6 }, 302 }; 303 304 static const struct clk_parent_data gcc_parent_data_6[] = { 305 { .index = DT_BI_TCXO }, 306 { .hw = &gpll0.clkr.hw }, 307 { .hw = &gpll7.clkr.hw }, 308 { .hw = &gpll0_out_aux2_div.hw }, 309 }; 310 311 static const struct parent_map gcc_parent_map_7[] = { 312 { P_BI_TCXO, 0 }, 313 { P_GPLL0_OUT_MAIN, 1 }, 314 { P_GPLL3_OUT_MAIN_DIV, 4 }, 315 { P_GPLL0_OUT_AUX2_DIV, 6 }, 316 }; 317 318 static const struct clk_parent_data gcc_parent_data_7[] = { 319 { .index = DT_BI_TCXO }, 320 { .hw = &gpll0.clkr.hw }, 321 { .hw = &gpll3_out_aux2_div.hw }, 322 { .hw = &gpll0_out_aux2_div.hw }, 323 }; 324 325 static const struct parent_map gcc_parent_map_8[] = { 326 { P_BI_TCXO, 0 }, 327 { P_GPLL0_OUT_MAIN, 1 }, 328 { P_GPLL8_OUT_MAIN, 2 }, 329 { P_GPLL4_OUT_MAIN, 5 }, 330 { P_GPLL0_OUT_AUX2_DIV, 6 }, 331 }; 332 333 static const struct clk_parent_data gcc_parent_data_8[] = { 334 { .index = DT_BI_TCXO }, 335 { .hw = &gpll0.clkr.hw }, 336 { .hw = &gpll8_out_main.clkr.hw }, 337 { .hw = &gpll4.clkr.hw }, 338 { .hw = &gpll0_out_aux2_div.hw }, 339 }; 340 341 static const struct parent_map gcc_parent_map_9[] = { 342 { P_BI_TCXO, 0 }, 343 { P_GPLL0_OUT_MAIN, 1 }, 344 { P_GPLL3_OUT_MAIN, 4 }, 345 }; 346 347 static const struct clk_parent_data gcc_parent_data_9[] = { 348 { .index = DT_BI_TCXO }, 349 { .hw = &gpll0.clkr.hw }, 350 { .hw = &gpll3.clkr.hw }, 351 }; 352 353 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { 354 F(19200000, P_BI_TCXO, 1, 0, 0), 355 { } 356 }; 357 358 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { 359 .cmd_rcgr = 0x48014, 360 .mnd_width = 0, 361 .hid_width = 5, 362 .parent_map = gcc_parent_map_0, 363 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, 364 .clkr.hw.init = &(const struct clk_init_data) { 365 .name = "gcc_cpuss_ahb_clk_src", 366 .parent_data = gcc_parent_data_0_ao, 367 .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao), 368 .ops = &clk_rcg2_ops, 369 }, 370 }; 371 372 static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = { 373 F(19200000, P_BI_TCXO, 1, 0, 0), 374 F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0), 375 F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0), 376 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0), 377 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0), 378 { } 379 }; 380 381 static struct clk_rcg2 gcc_emac_ptp_clk_src = { 382 .cmd_rcgr = 0x6038, 383 .mnd_width = 0, 384 .hid_width = 5, 385 .parent_map = gcc_parent_map_5, 386 .freq_tbl = ftbl_gcc_emac_ptp_clk_src, 387 .clkr.hw.init = &(const struct clk_init_data) { 388 .name = "gcc_emac_ptp_clk_src", 389 .parent_data = gcc_parent_data_5, 390 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 391 .ops = &clk_rcg2_ops, 392 }, 393 }; 394 395 static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = { 396 F(2500000, P_BI_TCXO, 1, 25, 192), 397 F(5000000, P_BI_TCXO, 1, 25, 96), 398 F(19200000, P_BI_TCXO, 1, 0, 0), 399 F(25000000, P_GPLL0_OUT_AUX2_DIV, 12, 0, 0), 400 F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0), 401 F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0), 402 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0), 403 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0), 404 { } 405 }; 406 407 static struct clk_rcg2 gcc_emac_rgmii_clk_src = { 408 .cmd_rcgr = 0x601c, 409 .mnd_width = 8, 410 .hid_width = 5, 411 .parent_map = gcc_parent_map_6, 412 .freq_tbl = ftbl_gcc_emac_rgmii_clk_src, 413 .clkr.hw.init = &(const struct clk_init_data) { 414 .name = "gcc_emac_rgmii_clk_src", 415 .parent_data = gcc_parent_data_6, 416 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 417 .ops = &clk_rcg2_ops, 418 }, 419 }; 420 421 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 422 F(25000000, P_GPLL0_OUT_AUX2_DIV, 12, 0, 0), 423 F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0), 424 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 425 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 426 { } 427 }; 428 429 static struct clk_rcg2 gcc_gp1_clk_src = { 430 .cmd_rcgr = 0x64004, 431 .mnd_width = 8, 432 .hid_width = 5, 433 .parent_map = gcc_parent_map_2, 434 .freq_tbl = ftbl_gcc_gp1_clk_src, 435 .clkr.hw.init = &(const struct clk_init_data) { 436 .name = "gcc_gp1_clk_src", 437 .parent_data = gcc_parent_data_2, 438 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 439 .ops = &clk_rcg2_ops, 440 }, 441 }; 442 443 static struct clk_rcg2 gcc_gp2_clk_src = { 444 .cmd_rcgr = 0x65004, 445 .mnd_width = 8, 446 .hid_width = 5, 447 .parent_map = gcc_parent_map_2, 448 .freq_tbl = ftbl_gcc_gp1_clk_src, 449 .clkr.hw.init = &(const struct clk_init_data) { 450 .name = "gcc_gp2_clk_src", 451 .parent_data = gcc_parent_data_2, 452 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 453 .ops = &clk_rcg2_ops, 454 }, 455 }; 456 457 static struct clk_rcg2 gcc_gp3_clk_src = { 458 .cmd_rcgr = 0x66004, 459 .mnd_width = 8, 460 .hid_width = 5, 461 .parent_map = gcc_parent_map_2, 462 .freq_tbl = ftbl_gcc_gp1_clk_src, 463 .clkr.hw.init = &(const struct clk_init_data) { 464 .name = "gcc_gp3_clk_src", 465 .parent_data = gcc_parent_data_2, 466 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 467 .ops = &clk_rcg2_ops, 468 }, 469 }; 470 471 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 472 F(9600000, P_BI_TCXO, 2, 0, 0), 473 F(19200000, P_BI_TCXO, 1, 0, 0), 474 { } 475 }; 476 477 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 478 .cmd_rcgr = 0x6b02c, 479 .mnd_width = 16, 480 .hid_width = 5, 481 .parent_map = gcc_parent_map_3, 482 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 483 .clkr.hw.init = &(const struct clk_init_data) { 484 .name = "gcc_pcie_0_aux_clk_src", 485 .parent_data = gcc_parent_data_3, 486 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 487 .ops = &clk_rcg2_shared_ops, 488 }, 489 }; 490 491 static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = { 492 F(19200000, P_BI_TCXO, 1, 0, 0), 493 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 494 { } 495 }; 496 497 static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { 498 .cmd_rcgr = 0x6f014, 499 .mnd_width = 0, 500 .hid_width = 5, 501 .parent_map = gcc_parent_map_0, 502 .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, 503 .clkr.hw.init = &(const struct clk_init_data) { 504 .name = "gcc_pcie_phy_refgen_clk_src", 505 .parent_data = gcc_parent_data_0, 506 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 507 .ops = &clk_rcg2_ops, 508 }, 509 }; 510 511 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 512 F(19200000, P_BI_TCXO, 1, 0, 0), 513 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 514 { } 515 }; 516 517 static struct clk_rcg2 gcc_pdm2_clk_src = { 518 .cmd_rcgr = 0x33010, 519 .mnd_width = 0, 520 .hid_width = 5, 521 .parent_map = gcc_parent_map_0, 522 .freq_tbl = ftbl_gcc_pdm2_clk_src, 523 .clkr.hw.init = &(const struct clk_init_data) { 524 .name = "gcc_pdm2_clk_src", 525 .parent_data = gcc_parent_data_0, 526 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 527 .ops = &clk_rcg2_ops, 528 }, 529 }; 530 531 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = { 532 F(60000000, P_GPLL0_OUT_AUX2_DIV, 5, 0, 0), 533 F(133250000, P_GPLL3_OUT_MAIN_DIV, 4, 0, 0), 534 F(266500000, P_GPLL3_OUT_MAIN_DIV, 2, 0, 0), 535 { } 536 }; 537 538 static struct clk_rcg2 gcc_qspi_core_clk_src = { 539 .cmd_rcgr = 0x4b008, 540 .mnd_width = 0, 541 .hid_width = 5, 542 .parent_map = gcc_parent_map_7, 543 .freq_tbl = ftbl_gcc_qspi_core_clk_src, 544 .clkr.hw.init = &(const struct clk_init_data) { 545 .name = "gcc_qspi_core_clk_src", 546 .parent_data = gcc_parent_data_7, 547 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 548 .ops = &clk_rcg2_ops, 549 }, 550 }; 551 552 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 553 F(7372800, P_GPLL0_OUT_AUX2_DIV, 1, 384, 15625), 554 F(14745600, P_GPLL0_OUT_AUX2_DIV, 1, 768, 15625), 555 F(19200000, P_BI_TCXO, 1, 0, 0), 556 F(29491200, P_GPLL0_OUT_AUX2_DIV, 1, 1536, 15625), 557 F(32000000, P_GPLL0_OUT_AUX2_DIV, 1, 8, 75), 558 F(48000000, P_GPLL0_OUT_AUX2_DIV, 1, 4, 25), 559 F(64000000, P_GPLL0_OUT_AUX2_DIV, 1, 16, 75), 560 F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0), 561 F(80000000, P_GPLL0_OUT_AUX2_DIV, 1, 4, 15), 562 F(96000000, P_GPLL0_OUT_AUX2_DIV, 1, 8, 25), 563 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 564 F(102400000, P_GPLL0_OUT_AUX2_DIV, 1, 128, 375), 565 F(112000000, P_GPLL0_OUT_AUX2_DIV, 1, 28, 75), 566 F(117964800, P_GPLL0_OUT_AUX2_DIV, 1, 6144, 15625), 567 F(120000000, P_GPLL0_OUT_AUX2_DIV, 2.5, 0, 0), 568 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0), 569 { } 570 }; 571 572 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 573 .name = "gcc_qupv3_wrap0_s0_clk_src", 574 .parent_data = gcc_parent_data_1, 575 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 576 .ops = &clk_rcg2_ops, 577 }; 578 579 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 580 .cmd_rcgr = 0x17148, 581 .mnd_width = 16, 582 .hid_width = 5, 583 .parent_map = gcc_parent_map_1, 584 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 585 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 586 }; 587 588 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 589 .name = "gcc_qupv3_wrap0_s1_clk_src", 590 .parent_data = gcc_parent_data_1, 591 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 592 .ops = &clk_rcg2_ops, 593 }; 594 595 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 596 .cmd_rcgr = 0x17278, 597 .mnd_width = 16, 598 .hid_width = 5, 599 .parent_map = gcc_parent_map_1, 600 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 601 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 602 }; 603 604 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 605 .name = "gcc_qupv3_wrap0_s2_clk_src", 606 .parent_data = gcc_parent_data_1, 607 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 608 .ops = &clk_rcg2_ops, 609 }; 610 611 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 612 .cmd_rcgr = 0x173a8, 613 .mnd_width = 16, 614 .hid_width = 5, 615 .parent_map = gcc_parent_map_1, 616 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 617 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 618 }; 619 620 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 621 .name = "gcc_qupv3_wrap0_s3_clk_src", 622 .parent_data = gcc_parent_data_1, 623 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 624 .ops = &clk_rcg2_ops, 625 }; 626 627 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 628 .cmd_rcgr = 0x174d8, 629 .mnd_width = 16, 630 .hid_width = 5, 631 .parent_map = gcc_parent_map_1, 632 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 633 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 634 }; 635 636 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 637 .name = "gcc_qupv3_wrap0_s4_clk_src", 638 .parent_data = gcc_parent_data_1, 639 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 640 .ops = &clk_rcg2_ops, 641 }; 642 643 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 644 .cmd_rcgr = 0x17608, 645 .mnd_width = 16, 646 .hid_width = 5, 647 .parent_map = gcc_parent_map_1, 648 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 649 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 650 }; 651 652 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 653 .name = "gcc_qupv3_wrap0_s5_clk_src", 654 .parent_data = gcc_parent_data_1, 655 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 656 .ops = &clk_rcg2_ops, 657 }; 658 659 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 660 .cmd_rcgr = 0x17738, 661 .mnd_width = 16, 662 .hid_width = 5, 663 .parent_map = gcc_parent_map_1, 664 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 665 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 666 }; 667 668 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 669 .name = "gcc_qupv3_wrap1_s0_clk_src", 670 .parent_data = gcc_parent_data_1, 671 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 672 .ops = &clk_rcg2_ops, 673 }; 674 675 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 676 .cmd_rcgr = 0x18148, 677 .mnd_width = 16, 678 .hid_width = 5, 679 .parent_map = gcc_parent_map_1, 680 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 681 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 682 }; 683 684 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 685 .name = "gcc_qupv3_wrap1_s1_clk_src", 686 .parent_data = gcc_parent_data_1, 687 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 688 .ops = &clk_rcg2_ops, 689 }; 690 691 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 692 .cmd_rcgr = 0x18278, 693 .mnd_width = 16, 694 .hid_width = 5, 695 .parent_map = gcc_parent_map_1, 696 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 697 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 698 }; 699 700 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 701 .name = "gcc_qupv3_wrap1_s2_clk_src", 702 .parent_data = gcc_parent_data_1, 703 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 704 .ops = &clk_rcg2_ops, 705 }; 706 707 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 708 .cmd_rcgr = 0x183a8, 709 .mnd_width = 16, 710 .hid_width = 5, 711 .parent_map = gcc_parent_map_1, 712 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 713 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 714 }; 715 716 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 717 .name = "gcc_qupv3_wrap1_s3_clk_src", 718 .parent_data = gcc_parent_data_1, 719 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 720 .ops = &clk_rcg2_ops, 721 }; 722 723 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 724 .cmd_rcgr = 0x184d8, 725 .mnd_width = 16, 726 .hid_width = 5, 727 .parent_map = gcc_parent_map_1, 728 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 729 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 730 }; 731 732 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 733 .name = "gcc_qupv3_wrap1_s4_clk_src", 734 .parent_data = gcc_parent_data_1, 735 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 736 .ops = &clk_rcg2_ops, 737 }; 738 739 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 740 .cmd_rcgr = 0x18608, 741 .mnd_width = 16, 742 .hid_width = 5, 743 .parent_map = gcc_parent_map_1, 744 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 745 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 746 }; 747 748 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 749 .name = "gcc_qupv3_wrap1_s5_clk_src", 750 .parent_data = gcc_parent_data_1, 751 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 752 .ops = &clk_rcg2_ops, 753 }; 754 755 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 756 .cmd_rcgr = 0x18738, 757 .mnd_width = 16, 758 .hid_width = 5, 759 .parent_map = gcc_parent_map_1, 760 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 761 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 762 }; 763 764 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 765 F(144000, P_BI_TCXO, 16, 3, 25), 766 F(400000, P_BI_TCXO, 12, 1, 4), 767 F(20000000, P_GPLL0_OUT_AUX2_DIV, 5, 1, 3), 768 F(25000000, P_GPLL0_OUT_AUX2_DIV, 6, 1, 2), 769 F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0), 770 F(100000000, P_GPLL0_OUT_AUX2_DIV, 3, 0, 0), 771 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 772 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 773 { } 774 }; 775 776 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 777 .cmd_rcgr = 0x12028, 778 .mnd_width = 8, 779 .hid_width = 5, 780 .parent_map = gcc_parent_map_1, 781 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 782 .clkr.hw.init = &(const struct clk_init_data) { 783 .name = "gcc_sdcc1_apps_clk_src", 784 .parent_data = gcc_parent_data_1, 785 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 786 .ops = &clk_rcg2_shared_floor_ops, 787 }, 788 }; 789 790 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 791 F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0), 792 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 793 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 794 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 795 { } 796 }; 797 798 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 799 .cmd_rcgr = 0x12010, 800 .mnd_width = 0, 801 .hid_width = 5, 802 .parent_map = gcc_parent_map_0, 803 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 804 .clkr.hw.init = &(const struct clk_init_data) { 805 .name = "gcc_sdcc1_ice_core_clk_src", 806 .parent_data = gcc_parent_data_0, 807 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 808 .ops = &clk_rcg2_shared_floor_ops, 809 }, 810 }; 811 812 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 813 F(400000, P_BI_TCXO, 12, 1, 4), 814 F(19200000, P_BI_TCXO, 1, 0, 0), 815 F(25000000, P_GPLL0_OUT_AUX2_DIV, 12, 0, 0), 816 F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0), 817 F(100000000, P_GPLL0_OUT_AUX2_DIV, 3, 0, 0), 818 F(202000000, P_GPLL8_OUT_MAIN, 2, 0, 0), 819 { } 820 }; 821 822 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 823 .cmd_rcgr = 0x1400c, 824 .mnd_width = 8, 825 .hid_width = 5, 826 .parent_map = gcc_parent_map_8, 827 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 828 .clkr.hw.init = &(const struct clk_init_data) { 829 .name = "gcc_sdcc2_apps_clk_src", 830 .parent_data = gcc_parent_data_8, 831 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 832 .ops = &clk_rcg2_shared_floor_ops, 833 }, 834 }; 835 836 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 837 F(25000000, P_GPLL0_OUT_AUX2_DIV, 12, 0, 0), 838 F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0), 839 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 840 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 841 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 842 { } 843 }; 844 845 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 846 .cmd_rcgr = 0x77020, 847 .mnd_width = 8, 848 .hid_width = 5, 849 .parent_map = gcc_parent_map_0, 850 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 851 .clkr.hw.init = &(const struct clk_init_data) { 852 .name = "gcc_ufs_phy_axi_clk_src", 853 .parent_data = gcc_parent_data_0, 854 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 855 .ops = &clk_rcg2_ops, 856 }, 857 }; 858 859 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 860 F(37500000, P_GPLL0_OUT_AUX2_DIV, 8, 0, 0), 861 F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0), 862 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 863 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 864 { } 865 }; 866 867 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 868 .cmd_rcgr = 0x77048, 869 .mnd_width = 0, 870 .hid_width = 5, 871 .parent_map = gcc_parent_map_0, 872 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 873 .clkr.hw.init = &(const struct clk_init_data) { 874 .name = "gcc_ufs_phy_ice_core_clk_src", 875 .parent_data = gcc_parent_data_0, 876 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 877 .ops = &clk_rcg2_ops, 878 }, 879 }; 880 881 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 882 .cmd_rcgr = 0x7707c, 883 .mnd_width = 0, 884 .hid_width = 5, 885 .parent_map = gcc_parent_map_4, 886 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 887 .clkr.hw.init = &(const struct clk_init_data) { 888 .name = "gcc_ufs_phy_phy_aux_clk_src", 889 .parent_data = gcc_parent_data_4, 890 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 891 .ops = &clk_rcg2_ops, 892 }, 893 }; 894 895 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { 896 F(37500000, P_GPLL0_OUT_AUX2_DIV, 8, 0, 0), 897 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 898 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 899 { } 900 }; 901 902 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 903 .cmd_rcgr = 0x77060, 904 .mnd_width = 0, 905 .hid_width = 5, 906 .parent_map = gcc_parent_map_0, 907 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, 908 .clkr.hw.init = &(const struct clk_init_data) { 909 .name = "gcc_ufs_phy_unipro_core_clk_src", 910 .parent_data = gcc_parent_data_0, 911 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 912 .ops = &clk_rcg2_ops, 913 }, 914 }; 915 916 static const struct freq_tbl ftbl_gcc_usb20_sec_master_clk_src[] = { 917 F(19200000, P_BI_TCXO, 1, 0, 0), 918 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 919 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), 920 { } 921 }; 922 923 static struct clk_rcg2 gcc_usb20_sec_master_clk_src = { 924 .cmd_rcgr = 0xa601c, 925 .mnd_width = 8, 926 .hid_width = 5, 927 .parent_map = gcc_parent_map_0, 928 .freq_tbl = ftbl_gcc_usb20_sec_master_clk_src, 929 .clkr.hw.init = &(const struct clk_init_data) { 930 .name = "gcc_usb20_sec_master_clk_src", 931 .parent_data = gcc_parent_data_0, 932 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 933 .ops = &clk_rcg2_ops, 934 }, 935 }; 936 937 static struct clk_rcg2 gcc_usb20_sec_mock_utmi_clk_src = { 938 .cmd_rcgr = 0xa6034, 939 .mnd_width = 0, 940 .hid_width = 5, 941 .parent_map = gcc_parent_map_0, 942 .freq_tbl = ftbl_gcc_pdm2_clk_src, 943 .clkr.hw.init = &(const struct clk_init_data) { 944 .name = "gcc_usb20_sec_mock_utmi_clk_src", 945 .parent_data = gcc_parent_data_0, 946 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 947 .ops = &clk_rcg2_ops, 948 }, 949 }; 950 951 static const struct freq_tbl ftbl_gcc_usb2_sec_phy_aux_clk_src[] = { 952 F(19200000, P_BI_TCXO, 1, 0, 0), 953 { } 954 }; 955 956 static struct clk_rcg2 gcc_usb2_sec_phy_aux_clk_src = { 957 .cmd_rcgr = 0xa6060, 958 .mnd_width = 0, 959 .hid_width = 5, 960 .parent_map = gcc_parent_map_3, 961 .freq_tbl = ftbl_gcc_usb2_sec_phy_aux_clk_src, 962 .clkr.hw.init = &(const struct clk_init_data) { 963 .name = "gcc_usb2_sec_phy_aux_clk_src", 964 .parent_data = gcc_parent_data_3, 965 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 966 .ops = &clk_rcg2_ops, 967 }, 968 }; 969 970 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 971 F(66666667, P_GPLL0_OUT_AUX2_DIV, 4.5, 0, 0), 972 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 973 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 974 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 975 { } 976 }; 977 978 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 979 .cmd_rcgr = 0xf01c, 980 .mnd_width = 8, 981 .hid_width = 5, 982 .parent_map = gcc_parent_map_0, 983 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 984 .clkr.hw.init = &(const struct clk_init_data) { 985 .name = "gcc_usb30_prim_master_clk_src", 986 .parent_data = gcc_parent_data_0, 987 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 988 .ops = &clk_rcg2_ops, 989 }, 990 }; 991 992 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 993 F(19200000, P_BI_TCXO, 1, 0, 0), 994 F(20000000, P_GPLL0_OUT_AUX2_DIV, 15, 0, 0), 995 F(40000000, P_GPLL0_OUT_AUX2_DIV, 7.5, 0, 0), 996 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 997 { } 998 }; 999 1000 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1001 .cmd_rcgr = 0xf034, 1002 .mnd_width = 0, 1003 .hid_width = 5, 1004 .parent_map = gcc_parent_map_0, 1005 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1006 .clkr.hw.init = &(const struct clk_init_data) { 1007 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1008 .parent_data = gcc_parent_data_0, 1009 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1010 .ops = &clk_rcg2_ops, 1011 }, 1012 }; 1013 1014 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1015 .cmd_rcgr = 0xf060, 1016 .mnd_width = 0, 1017 .hid_width = 5, 1018 .parent_map = gcc_parent_map_3, 1019 .freq_tbl = ftbl_gcc_usb2_sec_phy_aux_clk_src, 1020 .clkr.hw.init = &(const struct clk_init_data) { 1021 .name = "gcc_usb3_prim_phy_aux_clk_src", 1022 .parent_data = gcc_parent_data_3, 1023 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1024 .ops = &clk_rcg2_ops, 1025 }, 1026 }; 1027 1028 static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = { 1029 F(19200000, P_BI_TCXO, 1, 0, 0), 1030 F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0), 1031 { } 1032 }; 1033 1034 static struct clk_rcg2 gcc_vsensor_clk_src = { 1035 .cmd_rcgr = 0x7a018, 1036 .mnd_width = 0, 1037 .hid_width = 5, 1038 .parent_map = gcc_parent_map_9, 1039 .freq_tbl = ftbl_gcc_vsensor_clk_src, 1040 .clkr.hw.init = &(const struct clk_init_data) { 1041 .name = "gcc_vsensor_clk_src", 1042 .parent_data = gcc_parent_data_9, 1043 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 1044 .ops = &clk_rcg2_ops, 1045 }, 1046 }; 1047 1048 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1049 .halt_reg = 0x770c0, 1050 .halt_check = BRANCH_HALT_VOTED, 1051 .hwcg_reg = 0x770c0, 1052 .hwcg_bit = 1, 1053 .clkr = { 1054 .enable_reg = 0x770c0, 1055 .enable_mask = BIT(0), 1056 .hw.init = &(const struct clk_init_data) { 1057 .name = "gcc_aggre_ufs_phy_axi_clk", 1058 .parent_hws = (const struct clk_hw*[]) { 1059 &gcc_ufs_phy_axi_clk_src.clkr.hw, 1060 }, 1061 .num_parents = 1, 1062 .flags = CLK_SET_RATE_PARENT, 1063 .ops = &clk_branch2_ops, 1064 }, 1065 }, 1066 }; 1067 1068 static struct clk_branch gcc_aggre_usb2_sec_axi_clk = { 1069 .halt_reg = 0xa6084, 1070 .halt_check = BRANCH_HALT_VOTED, 1071 .clkr = { 1072 .enable_reg = 0xa6084, 1073 .enable_mask = BIT(0), 1074 .hw.init = &(const struct clk_init_data) { 1075 .name = "gcc_aggre_usb2_sec_axi_clk", 1076 .parent_hws = (const struct clk_hw*[]) { 1077 &gcc_usb20_sec_master_clk_src.clkr.hw, 1078 }, 1079 .num_parents = 1, 1080 .flags = CLK_SET_RATE_PARENT, 1081 .ops = &clk_branch2_ops, 1082 }, 1083 }, 1084 }; 1085 1086 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1087 .halt_reg = 0xf07c, 1088 .halt_check = BRANCH_HALT_VOTED, 1089 .clkr = { 1090 .enable_reg = 0xf07c, 1091 .enable_mask = BIT(0), 1092 .hw.init = &(const struct clk_init_data) { 1093 .name = "gcc_aggre_usb3_prim_axi_clk", 1094 .parent_hws = (const struct clk_hw*[]) { 1095 &gcc_usb30_prim_master_clk_src.clkr.hw, 1096 }, 1097 .num_parents = 1, 1098 .flags = CLK_SET_RATE_PARENT, 1099 .ops = &clk_branch2_ops, 1100 }, 1101 }, 1102 }; 1103 1104 static struct clk_branch gcc_ahb2phy_east_clk = { 1105 .halt_reg = 0x6a008, 1106 .halt_check = BRANCH_HALT_VOTED, 1107 .hwcg_reg = 0x6a008, 1108 .hwcg_bit = 1, 1109 .clkr = { 1110 .enable_reg = 0x6a008, 1111 .enable_mask = BIT(0), 1112 .hw.init = &(const struct clk_init_data) { 1113 .name = "gcc_ahb2phy_east_clk", 1114 .ops = &clk_branch2_ops, 1115 }, 1116 }, 1117 }; 1118 1119 static struct clk_branch gcc_ahb2phy_west_clk = { 1120 .halt_reg = 0x6a004, 1121 .halt_check = BRANCH_HALT_VOTED, 1122 .hwcg_reg = 0x6a004, 1123 .hwcg_bit = 1, 1124 .clkr = { 1125 .enable_reg = 0x6a004, 1126 .enable_mask = BIT(0), 1127 .hw.init = &(const struct clk_init_data) { 1128 .name = "gcc_ahb2phy_west_clk", 1129 .ops = &clk_branch2_ops, 1130 }, 1131 }, 1132 }; 1133 1134 static struct clk_branch gcc_boot_rom_ahb_clk = { 1135 .halt_reg = 0x38004, 1136 .halt_check = BRANCH_HALT_VOTED, 1137 .hwcg_reg = 0x38004, 1138 .hwcg_bit = 1, 1139 .clkr = { 1140 .enable_reg = 0x52004, 1141 .enable_mask = BIT(10), 1142 .hw.init = &(const struct clk_init_data) { 1143 .name = "gcc_boot_rom_ahb_clk", 1144 .ops = &clk_branch2_ops, 1145 }, 1146 }, 1147 }; 1148 1149 static struct clk_branch gcc_camera_hf_axi_clk = { 1150 .halt_reg = 0xb030, 1151 .halt_check = BRANCH_HALT_VOTED, 1152 .clkr = { 1153 .enable_reg = 0xb030, 1154 .enable_mask = BIT(0), 1155 .hw.init = &(const struct clk_init_data) { 1156 .name = "gcc_camera_hf_axi_clk", 1157 .ops = &clk_branch2_ops, 1158 }, 1159 }, 1160 }; 1161 1162 static struct clk_branch gcc_ce1_ahb_clk = { 1163 .halt_reg = 0x4100c, 1164 .halt_check = BRANCH_HALT_VOTED, 1165 .hwcg_reg = 0x4100c, 1166 .hwcg_bit = 1, 1167 .clkr = { 1168 .enable_reg = 0x52004, 1169 .enable_mask = BIT(3), 1170 .hw.init = &(const struct clk_init_data) { 1171 .name = "gcc_ce1_ahb_clk", 1172 .ops = &clk_branch2_ops, 1173 }, 1174 }, 1175 }; 1176 1177 static struct clk_branch gcc_ce1_axi_clk = { 1178 .halt_reg = 0x41008, 1179 .halt_check = BRANCH_HALT_VOTED, 1180 .clkr = { 1181 .enable_reg = 0x52004, 1182 .enable_mask = BIT(4), 1183 .hw.init = &(const struct clk_init_data) { 1184 .name = "gcc_ce1_axi_clk", 1185 .ops = &clk_branch2_ops, 1186 }, 1187 }, 1188 }; 1189 1190 static struct clk_branch gcc_ce1_clk = { 1191 .halt_reg = 0x41004, 1192 .halt_check = BRANCH_HALT_VOTED, 1193 .clkr = { 1194 .enable_reg = 0x52004, 1195 .enable_mask = BIT(5), 1196 .hw.init = &(const struct clk_init_data) { 1197 .name = "gcc_ce1_clk", 1198 .ops = &clk_branch2_ops, 1199 }, 1200 }, 1201 }; 1202 1203 static struct clk_branch gcc_cfg_noc_usb2_sec_axi_clk = { 1204 .halt_reg = 0xa609c, 1205 .halt_check = BRANCH_HALT_VOTED, 1206 .clkr = { 1207 .enable_reg = 0xa609c, 1208 .enable_mask = BIT(0), 1209 .hw.init = &(const struct clk_init_data) { 1210 .name = "gcc_cfg_noc_usb2_sec_axi_clk", 1211 .parent_hws = (const struct clk_hw*[]) { 1212 &gcc_usb20_sec_master_clk_src.clkr.hw, 1213 }, 1214 .num_parents = 1, 1215 .flags = CLK_SET_RATE_PARENT, 1216 .ops = &clk_branch2_ops, 1217 }, 1218 }, 1219 }; 1220 1221 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1222 .halt_reg = 0xf078, 1223 .halt_check = BRANCH_HALT_VOTED, 1224 .clkr = { 1225 .enable_reg = 0xf078, 1226 .enable_mask = BIT(0), 1227 .hw.init = &(const struct clk_init_data) { 1228 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1229 .parent_hws = (const struct clk_hw*[]) { 1230 &gcc_usb30_prim_master_clk_src.clkr.hw, 1231 }, 1232 .num_parents = 1, 1233 .flags = CLK_SET_RATE_PARENT, 1234 .ops = &clk_branch2_ops, 1235 }, 1236 }, 1237 }; 1238 1239 static struct clk_branch gcc_cpuss_ahb_clk = { 1240 .halt_reg = 0x48000, 1241 .halt_check = BRANCH_HALT_VOTED, 1242 .clkr = { 1243 .enable_reg = 0x52004, 1244 .enable_mask = BIT(21), 1245 .hw.init = &(const struct clk_init_data) { 1246 .name = "gcc_cpuss_ahb_clk", 1247 .parent_hws = (const struct clk_hw*[]) { 1248 &gcc_cpuss_ahb_clk_src.clkr.hw, 1249 }, 1250 .num_parents = 1, 1251 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 1252 .ops = &clk_branch2_ops, 1253 }, 1254 }, 1255 }; 1256 1257 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1258 .halt_reg = 0x71154, 1259 .halt_check = BRANCH_HALT_VOTED, 1260 .clkr = { 1261 .enable_reg = 0x71154, 1262 .enable_mask = BIT(0), 1263 .hw.init = &(const struct clk_init_data) { 1264 .name = "gcc_ddrss_gpu_axi_clk", 1265 .ops = &clk_branch2_ops, 1266 }, 1267 }, 1268 }; 1269 1270 static struct clk_branch gcc_disp_gpll0_div_clk_src = { 1271 .halt_check = BRANCH_HALT_DELAY, 1272 .clkr = { 1273 .enable_reg = 0x52004, 1274 .enable_mask = BIT(20), 1275 .hw.init = &(const struct clk_init_data) { 1276 .name = "gcc_disp_gpll0_div_clk_src", 1277 .parent_hws = (const struct clk_hw*[]) { 1278 &gpll0_out_aux2_div.hw, 1279 }, 1280 .num_parents = 1, 1281 .ops = &clk_branch2_ops, 1282 }, 1283 }, 1284 }; 1285 1286 static struct clk_branch gcc_disp_hf_axi_clk = { 1287 .halt_reg = 0xb038, 1288 .halt_check = BRANCH_HALT_VOTED, 1289 .clkr = { 1290 .enable_reg = 0xb038, 1291 .enable_mask = BIT(0), 1292 .hw.init = &(const struct clk_init_data) { 1293 .name = "gcc_disp_hf_axi_clk", 1294 .ops = &clk_branch2_ops, 1295 }, 1296 }, 1297 }; 1298 1299 static struct clk_branch gcc_emac_axi_clk = { 1300 .halt_reg = 0x6010, 1301 .halt_check = BRANCH_HALT, 1302 .clkr = { 1303 .enable_reg = 0x6010, 1304 .enable_mask = BIT(0), 1305 .hw.init = &(const struct clk_init_data) { 1306 .name = "gcc_emac_axi_clk", 1307 .ops = &clk_branch2_ops, 1308 }, 1309 }, 1310 }; 1311 1312 static struct clk_branch gcc_emac_ptp_clk = { 1313 .halt_reg = 0x6034, 1314 .halt_check = BRANCH_HALT, 1315 .clkr = { 1316 .enable_reg = 0x6034, 1317 .enable_mask = BIT(0), 1318 .hw.init = &(const struct clk_init_data) { 1319 .name = "gcc_emac_ptp_clk", 1320 .parent_hws = (const struct clk_hw*[]) { 1321 &gcc_emac_ptp_clk_src.clkr.hw, 1322 }, 1323 .num_parents = 1, 1324 .flags = CLK_SET_RATE_PARENT, 1325 .ops = &clk_branch2_ops, 1326 }, 1327 }, 1328 }; 1329 1330 static struct clk_branch gcc_emac_rgmii_clk = { 1331 .halt_reg = 0x6018, 1332 .halt_check = BRANCH_HALT, 1333 .clkr = { 1334 .enable_reg = 0x6018, 1335 .enable_mask = BIT(0), 1336 .hw.init = &(const struct clk_init_data) { 1337 .name = "gcc_emac_rgmii_clk", 1338 .parent_hws = (const struct clk_hw*[]) { 1339 &gcc_emac_rgmii_clk_src.clkr.hw, 1340 }, 1341 .num_parents = 1, 1342 .flags = CLK_SET_RATE_PARENT, 1343 .ops = &clk_branch2_ops, 1344 }, 1345 }, 1346 }; 1347 1348 static struct clk_branch gcc_emac_slv_ahb_clk = { 1349 .halt_reg = 0x6014, 1350 .halt_check = BRANCH_HALT, 1351 .hwcg_reg = 0x6014, 1352 .hwcg_bit = 1, 1353 .clkr = { 1354 .enable_reg = 0x6014, 1355 .enable_mask = BIT(0), 1356 .hw.init = &(const struct clk_init_data) { 1357 .name = "gcc_emac_slv_ahb_clk", 1358 .ops = &clk_branch2_ops, 1359 }, 1360 }, 1361 }; 1362 1363 static struct clk_branch gcc_gp1_clk = { 1364 .halt_reg = 0x64000, 1365 .halt_check = BRANCH_HALT, 1366 .clkr = { 1367 .enable_reg = 0x64000, 1368 .enable_mask = BIT(0), 1369 .hw.init = &(const struct clk_init_data) { 1370 .name = "gcc_gp1_clk", 1371 .parent_hws = (const struct clk_hw*[]) { 1372 &gcc_gp1_clk_src.clkr.hw, 1373 }, 1374 .num_parents = 1, 1375 .flags = CLK_SET_RATE_PARENT, 1376 .ops = &clk_branch2_ops, 1377 }, 1378 }, 1379 }; 1380 1381 static struct clk_branch gcc_gp2_clk = { 1382 .halt_reg = 0x65000, 1383 .halt_check = BRANCH_HALT, 1384 .clkr = { 1385 .enable_reg = 0x65000, 1386 .enable_mask = BIT(0), 1387 .hw.init = &(const struct clk_init_data) { 1388 .name = "gcc_gp2_clk", 1389 .parent_hws = (const struct clk_hw*[]) { 1390 &gcc_gp2_clk_src.clkr.hw, 1391 }, 1392 .num_parents = 1, 1393 .flags = CLK_SET_RATE_PARENT, 1394 .ops = &clk_branch2_ops, 1395 }, 1396 }, 1397 }; 1398 1399 static struct clk_branch gcc_gp3_clk = { 1400 .halt_reg = 0x66000, 1401 .halt_check = BRANCH_HALT, 1402 .clkr = { 1403 .enable_reg = 0x66000, 1404 .enable_mask = BIT(0), 1405 .hw.init = &(const struct clk_init_data) { 1406 .name = "gcc_gp3_clk", 1407 .parent_hws = (const struct clk_hw*[]) { 1408 &gcc_gp3_clk_src.clkr.hw, 1409 }, 1410 .num_parents = 1, 1411 .flags = CLK_SET_RATE_PARENT, 1412 .ops = &clk_branch2_ops, 1413 }, 1414 }, 1415 }; 1416 1417 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1418 .halt_check = BRANCH_HALT_DELAY, 1419 .clkr = { 1420 .enable_reg = 0x52004, 1421 .enable_mask = BIT(15), 1422 .hw.init = &(const struct clk_init_data) { 1423 .name = "gcc_gpu_gpll0_clk_src", 1424 .parent_hws = (const struct clk_hw*[]) { 1425 &gpll0.clkr.hw, 1426 }, 1427 .num_parents = 1, 1428 .ops = &clk_branch2_ops, 1429 }, 1430 }, 1431 }; 1432 1433 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1434 .halt_check = BRANCH_HALT_DELAY, 1435 .clkr = { 1436 .enable_reg = 0x52004, 1437 .enable_mask = BIT(16), 1438 .hw.init = &(const struct clk_init_data) { 1439 .name = "gcc_gpu_gpll0_div_clk_src", 1440 .parent_hws = (const struct clk_hw*[]) { 1441 &gpll0_out_aux2_div.hw, 1442 }, 1443 .num_parents = 1, 1444 .ops = &clk_branch2_ops, 1445 }, 1446 }, 1447 }; 1448 1449 static struct clk_branch gcc_gpu_iref_clk = { 1450 .halt_reg = 0x8c010, 1451 .halt_check = BRANCH_HALT, 1452 .clkr = { 1453 .enable_reg = 0x8c010, 1454 .enable_mask = BIT(0), 1455 .hw.init = &(const struct clk_init_data) { 1456 .name = "gcc_gpu_iref_clk", 1457 .ops = &clk_branch2_ops, 1458 }, 1459 }, 1460 }; 1461 1462 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1463 .halt_reg = 0x7100c, 1464 .halt_check = BRANCH_HALT_VOTED, 1465 .clkr = { 1466 .enable_reg = 0x7100c, 1467 .enable_mask = BIT(0), 1468 .hw.init = &(const struct clk_init_data) { 1469 .name = "gcc_gpu_memnoc_gfx_clk", 1470 .ops = &clk_branch2_ops, 1471 }, 1472 }, 1473 }; 1474 1475 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1476 .halt_reg = 0x71018, 1477 .halt_check = BRANCH_HALT, 1478 .clkr = { 1479 .enable_reg = 0x71018, 1480 .enable_mask = BIT(0), 1481 .hw.init = &(const struct clk_init_data) { 1482 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1483 .ops = &clk_branch2_ops, 1484 }, 1485 }, 1486 }; 1487 1488 static struct clk_branch gcc_pcie0_phy_refgen_clk = { 1489 .halt_reg = 0x6f02c, 1490 .halt_check = BRANCH_HALT, 1491 .clkr = { 1492 .enable_reg = 0x6f02c, 1493 .enable_mask = BIT(0), 1494 .hw.init = &(const struct clk_init_data) { 1495 .name = "gcc_pcie0_phy_refgen_clk", 1496 .parent_hws = (const struct clk_hw*[]) { 1497 &gcc_pcie_phy_refgen_clk_src.clkr.hw, 1498 }, 1499 .num_parents = 1, 1500 .flags = CLK_SET_RATE_PARENT, 1501 .ops = &clk_branch2_ops, 1502 }, 1503 }, 1504 }; 1505 1506 static struct clk_branch gcc_pcie_0_aux_clk = { 1507 .halt_reg = 0x6b020, 1508 .halt_check = BRANCH_HALT_VOTED, 1509 .clkr = { 1510 .enable_reg = 0x5200c, 1511 .enable_mask = BIT(3), 1512 .hw.init = &(const struct clk_init_data) { 1513 .name = "gcc_pcie_0_aux_clk", 1514 .parent_hws = (const struct clk_hw*[]) { 1515 &gcc_pcie_0_aux_clk_src.clkr.hw, 1516 }, 1517 .num_parents = 1, 1518 .flags = CLK_SET_RATE_PARENT, 1519 .ops = &clk_branch2_ops, 1520 }, 1521 }, 1522 }; 1523 1524 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1525 .halt_reg = 0x6b01c, 1526 .halt_check = BRANCH_HALT_VOTED, 1527 .hwcg_reg = 0x6b01c, 1528 .hwcg_bit = 1, 1529 .clkr = { 1530 .enable_reg = 0x5200c, 1531 .enable_mask = BIT(2), 1532 .hw.init = &(const struct clk_init_data) { 1533 .name = "gcc_pcie_0_cfg_ahb_clk", 1534 .ops = &clk_branch2_ops, 1535 }, 1536 }, 1537 }; 1538 1539 static struct clk_branch gcc_pcie_0_clkref_clk = { 1540 .halt_reg = 0x8c00c, 1541 .halt_check = BRANCH_HALT, 1542 .clkr = { 1543 .enable_reg = 0x8c00c, 1544 .enable_mask = BIT(0), 1545 .hw.init = &(const struct clk_init_data) { 1546 .name = "gcc_pcie_0_clkref_clk", 1547 .ops = &clk_branch2_ops, 1548 }, 1549 }, 1550 }; 1551 1552 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1553 .halt_reg = 0x6b018, 1554 .halt_check = BRANCH_HALT_VOTED, 1555 .clkr = { 1556 .enable_reg = 0x5200c, 1557 .enable_mask = BIT(1), 1558 .hw.init = &(const struct clk_init_data) { 1559 .name = "gcc_pcie_0_mstr_axi_clk", 1560 .ops = &clk_branch2_ops, 1561 }, 1562 }, 1563 }; 1564 1565 static struct clk_branch gcc_pcie_0_pipe_clk = { 1566 .halt_reg = 0x6b024, 1567 .halt_check = BRANCH_HALT_SKIP, 1568 .clkr = { 1569 .enable_reg = 0x5200c, 1570 .enable_mask = BIT(4), 1571 .hw.init = &(const struct clk_init_data) { 1572 .name = "gcc_pcie_0_pipe_clk", 1573 .ops = &clk_branch2_ops, 1574 }, 1575 }, 1576 }; 1577 1578 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1579 .halt_reg = 0x6b014, 1580 .halt_check = BRANCH_HALT_VOTED, 1581 .hwcg_reg = 0x6b014, 1582 .hwcg_bit = 1, 1583 .clkr = { 1584 .enable_reg = 0x5200c, 1585 .enable_mask = BIT(0), 1586 .hw.init = &(const struct clk_init_data) { 1587 .name = "gcc_pcie_0_slv_axi_clk", 1588 .ops = &clk_branch2_ops, 1589 }, 1590 }, 1591 }; 1592 1593 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1594 .halt_reg = 0x6b010, 1595 .halt_check = BRANCH_HALT_VOTED, 1596 .clkr = { 1597 .enable_reg = 0x5200c, 1598 .enable_mask = BIT(5), 1599 .hw.init = &(const struct clk_init_data) { 1600 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1601 .ops = &clk_branch2_ops, 1602 }, 1603 }, 1604 }; 1605 1606 static struct clk_branch gcc_pcie_phy_aux_clk = { 1607 .halt_reg = 0x6f004, 1608 .halt_check = BRANCH_HALT, 1609 .clkr = { 1610 .enable_reg = 0x6f004, 1611 .enable_mask = BIT(0), 1612 .hw.init = &(const struct clk_init_data) { 1613 .name = "gcc_pcie_phy_aux_clk", 1614 .parent_hws = (const struct clk_hw*[]) { 1615 &gcc_pcie_0_aux_clk_src.clkr.hw, 1616 }, 1617 .num_parents = 1, 1618 .flags = CLK_SET_RATE_PARENT, 1619 .ops = &clk_branch2_ops, 1620 }, 1621 }, 1622 }; 1623 1624 static struct clk_branch gcc_pdm2_clk = { 1625 .halt_reg = 0x3300c, 1626 .halt_check = BRANCH_HALT, 1627 .clkr = { 1628 .enable_reg = 0x3300c, 1629 .enable_mask = BIT(0), 1630 .hw.init = &(const struct clk_init_data) { 1631 .name = "gcc_pdm2_clk", 1632 .parent_hws = (const struct clk_hw*[]) { 1633 &gcc_pdm2_clk_src.clkr.hw, 1634 }, 1635 .num_parents = 1, 1636 .flags = CLK_SET_RATE_PARENT, 1637 .ops = &clk_branch2_ops, 1638 }, 1639 }, 1640 }; 1641 1642 static struct clk_branch gcc_pdm_ahb_clk = { 1643 .halt_reg = 0x33004, 1644 .halt_check = BRANCH_HALT, 1645 .hwcg_reg = 0x33004, 1646 .hwcg_bit = 1, 1647 .clkr = { 1648 .enable_reg = 0x33004, 1649 .enable_mask = BIT(0), 1650 .hw.init = &(const struct clk_init_data) { 1651 .name = "gcc_pdm_ahb_clk", 1652 .ops = &clk_branch2_ops, 1653 }, 1654 }, 1655 }; 1656 1657 static struct clk_branch gcc_pdm_xo4_clk = { 1658 .halt_reg = 0x33008, 1659 .halt_check = BRANCH_HALT, 1660 .clkr = { 1661 .enable_reg = 0x33008, 1662 .enable_mask = BIT(0), 1663 .hw.init = &(const struct clk_init_data) { 1664 .name = "gcc_pdm_xo4_clk", 1665 .ops = &clk_branch2_ops, 1666 }, 1667 }, 1668 }; 1669 1670 static struct clk_branch gcc_prng_ahb_clk = { 1671 .halt_reg = 0x34004, 1672 .halt_check = BRANCH_HALT_VOTED, 1673 .hwcg_reg = 0x34004, 1674 .hwcg_bit = 1, 1675 .clkr = { 1676 .enable_reg = 0x52004, 1677 .enable_mask = BIT(13), 1678 .hw.init = &(const struct clk_init_data) { 1679 .name = "gcc_prng_ahb_clk", 1680 .ops = &clk_branch2_ops, 1681 }, 1682 }, 1683 }; 1684 1685 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 1686 .halt_reg = 0xb018, 1687 .halt_check = BRANCH_HALT_VOTED, 1688 .hwcg_reg = 0xb018, 1689 .hwcg_bit = 1, 1690 .clkr = { 1691 .enable_reg = 0xb018, 1692 .enable_mask = BIT(0), 1693 .hw.init = &(const struct clk_init_data) { 1694 .name = "gcc_qmip_camera_nrt_ahb_clk", 1695 .ops = &clk_branch2_ops, 1696 }, 1697 }, 1698 }; 1699 1700 static struct clk_branch gcc_qmip_disp_ahb_clk = { 1701 .halt_reg = 0xb020, 1702 .halt_check = BRANCH_HALT_VOTED, 1703 .hwcg_reg = 0xb020, 1704 .hwcg_bit = 1, 1705 .clkr = { 1706 .enable_reg = 0xb020, 1707 .enable_mask = BIT(0), 1708 .hw.init = &(const struct clk_init_data) { 1709 .name = "gcc_qmip_disp_ahb_clk", 1710 .ops = &clk_branch2_ops, 1711 }, 1712 }, 1713 }; 1714 1715 static struct clk_branch gcc_qmip_pcie_ahb_clk = { 1716 .halt_reg = 0x6b044, 1717 .halt_check = BRANCH_HALT_VOTED, 1718 .hwcg_reg = 0x6b044, 1719 .hwcg_bit = 1, 1720 .clkr = { 1721 .enable_reg = 0x5200c, 1722 .enable_mask = BIT(28), 1723 .hw.init = &(const struct clk_init_data) { 1724 .name = "gcc_qmip_pcie_ahb_clk", 1725 .ops = &clk_branch2_ops, 1726 }, 1727 }, 1728 }; 1729 1730 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 1731 .halt_reg = 0xb014, 1732 .halt_check = BRANCH_HALT_VOTED, 1733 .hwcg_reg = 0xb014, 1734 .hwcg_bit = 1, 1735 .clkr = { 1736 .enable_reg = 0xb014, 1737 .enable_mask = BIT(0), 1738 .hw.init = &(const struct clk_init_data) { 1739 .name = "gcc_qmip_video_vcodec_ahb_clk", 1740 .ops = &clk_branch2_ops, 1741 }, 1742 }, 1743 }; 1744 1745 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = { 1746 .halt_reg = 0x4b000, 1747 .halt_check = BRANCH_HALT_VOTED, 1748 .clkr = { 1749 .enable_reg = 0x4b000, 1750 .enable_mask = BIT(0), 1751 .hw.init = &(const struct clk_init_data) { 1752 .name = "gcc_qspi_cnoc_periph_ahb_clk", 1753 .ops = &clk_branch2_ops, 1754 }, 1755 }, 1756 }; 1757 1758 static struct clk_branch gcc_qspi_core_clk = { 1759 .halt_reg = 0x4b004, 1760 .halt_check = BRANCH_HALT, 1761 .clkr = { 1762 .enable_reg = 0x4b004, 1763 .enable_mask = BIT(0), 1764 .hw.init = &(const struct clk_init_data) { 1765 .name = "gcc_qspi_core_clk", 1766 .parent_hws = (const struct clk_hw*[]) { 1767 &gcc_qspi_core_clk_src.clkr.hw, 1768 }, 1769 .num_parents = 1, 1770 .flags = CLK_SET_RATE_PARENT, 1771 .ops = &clk_branch2_ops, 1772 }, 1773 }, 1774 }; 1775 1776 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 1777 .halt_reg = 0x17014, 1778 .halt_check = BRANCH_HALT_VOTED, 1779 .clkr = { 1780 .enable_reg = 0x5200c, 1781 .enable_mask = BIT(9), 1782 .hw.init = &(const struct clk_init_data) { 1783 .name = "gcc_qupv3_wrap0_core_2x_clk", 1784 .ops = &clk_branch2_ops, 1785 }, 1786 }, 1787 }; 1788 1789 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 1790 .halt_reg = 0x1700c, 1791 .halt_check = BRANCH_HALT_VOTED, 1792 .clkr = { 1793 .enable_reg = 0x5200c, 1794 .enable_mask = BIT(8), 1795 .hw.init = &(const struct clk_init_data) { 1796 .name = "gcc_qupv3_wrap0_core_clk", 1797 .ops = &clk_branch2_ops, 1798 }, 1799 }, 1800 }; 1801 1802 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 1803 .halt_reg = 0x17144, 1804 .halt_check = BRANCH_HALT_VOTED, 1805 .clkr = { 1806 .enable_reg = 0x5200c, 1807 .enable_mask = BIT(10), 1808 .hw.init = &(const struct clk_init_data) { 1809 .name = "gcc_qupv3_wrap0_s0_clk", 1810 .parent_hws = (const struct clk_hw*[]) { 1811 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 1812 }, 1813 .num_parents = 1, 1814 .flags = CLK_SET_RATE_PARENT, 1815 .ops = &clk_branch2_ops, 1816 }, 1817 }, 1818 }; 1819 1820 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 1821 .halt_reg = 0x17274, 1822 .halt_check = BRANCH_HALT_VOTED, 1823 .clkr = { 1824 .enable_reg = 0x5200c, 1825 .enable_mask = BIT(11), 1826 .hw.init = &(const struct clk_init_data) { 1827 .name = "gcc_qupv3_wrap0_s1_clk", 1828 .parent_hws = (const struct clk_hw*[]) { 1829 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 1830 }, 1831 .num_parents = 1, 1832 .flags = CLK_SET_RATE_PARENT, 1833 .ops = &clk_branch2_ops, 1834 }, 1835 }, 1836 }; 1837 1838 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 1839 .halt_reg = 0x173a4, 1840 .halt_check = BRANCH_HALT_VOTED, 1841 .clkr = { 1842 .enable_reg = 0x5200c, 1843 .enable_mask = BIT(12), 1844 .hw.init = &(const struct clk_init_data) { 1845 .name = "gcc_qupv3_wrap0_s2_clk", 1846 .parent_hws = (const struct clk_hw*[]) { 1847 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 1848 }, 1849 .num_parents = 1, 1850 .flags = CLK_SET_RATE_PARENT, 1851 .ops = &clk_branch2_ops, 1852 }, 1853 }, 1854 }; 1855 1856 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 1857 .halt_reg = 0x174d4, 1858 .halt_check = BRANCH_HALT_VOTED, 1859 .clkr = { 1860 .enable_reg = 0x5200c, 1861 .enable_mask = BIT(13), 1862 .hw.init = &(const struct clk_init_data) { 1863 .name = "gcc_qupv3_wrap0_s3_clk", 1864 .parent_hws = (const struct clk_hw*[]) { 1865 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 1866 }, 1867 .num_parents = 1, 1868 .flags = CLK_SET_RATE_PARENT, 1869 .ops = &clk_branch2_ops, 1870 }, 1871 }, 1872 }; 1873 1874 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 1875 .halt_reg = 0x17604, 1876 .halt_check = BRANCH_HALT_VOTED, 1877 .clkr = { 1878 .enable_reg = 0x5200c, 1879 .enable_mask = BIT(14), 1880 .hw.init = &(const struct clk_init_data) { 1881 .name = "gcc_qupv3_wrap0_s4_clk", 1882 .parent_hws = (const struct clk_hw*[]) { 1883 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 1884 }, 1885 .num_parents = 1, 1886 .flags = CLK_SET_RATE_PARENT, 1887 .ops = &clk_branch2_ops, 1888 }, 1889 }, 1890 }; 1891 1892 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 1893 .halt_reg = 0x17734, 1894 .halt_check = BRANCH_HALT_VOTED, 1895 .clkr = { 1896 .enable_reg = 0x5200c, 1897 .enable_mask = BIT(15), 1898 .hw.init = &(const struct clk_init_data) { 1899 .name = "gcc_qupv3_wrap0_s5_clk", 1900 .parent_hws = (const struct clk_hw*[]) { 1901 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 1902 }, 1903 .num_parents = 1, 1904 .flags = CLK_SET_RATE_PARENT, 1905 .ops = &clk_branch2_ops, 1906 }, 1907 }, 1908 }; 1909 1910 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 1911 .halt_reg = 0x18014, 1912 .halt_check = BRANCH_HALT_VOTED, 1913 .clkr = { 1914 .enable_reg = 0x5200c, 1915 .enable_mask = BIT(18), 1916 .hw.init = &(const struct clk_init_data) { 1917 .name = "gcc_qupv3_wrap1_core_2x_clk", 1918 .ops = &clk_branch2_ops, 1919 }, 1920 }, 1921 }; 1922 1923 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 1924 .halt_reg = 0x1800c, 1925 .halt_check = BRANCH_HALT_VOTED, 1926 .clkr = { 1927 .enable_reg = 0x5200c, 1928 .enable_mask = BIT(19), 1929 .hw.init = &(const struct clk_init_data) { 1930 .name = "gcc_qupv3_wrap1_core_clk", 1931 .ops = &clk_branch2_ops, 1932 }, 1933 }, 1934 }; 1935 1936 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 1937 .halt_reg = 0x18144, 1938 .halt_check = BRANCH_HALT_VOTED, 1939 .clkr = { 1940 .enable_reg = 0x5200c, 1941 .enable_mask = BIT(22), 1942 .hw.init = &(const struct clk_init_data) { 1943 .name = "gcc_qupv3_wrap1_s0_clk", 1944 .parent_hws = (const struct clk_hw*[]) { 1945 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 1946 }, 1947 .num_parents = 1, 1948 .flags = CLK_SET_RATE_PARENT, 1949 .ops = &clk_branch2_ops, 1950 }, 1951 }, 1952 }; 1953 1954 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 1955 .halt_reg = 0x18274, 1956 .halt_check = BRANCH_HALT_VOTED, 1957 .clkr = { 1958 .enable_reg = 0x5200c, 1959 .enable_mask = BIT(23), 1960 .hw.init = &(const struct clk_init_data) { 1961 .name = "gcc_qupv3_wrap1_s1_clk", 1962 .parent_hws = (const struct clk_hw*[]) { 1963 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 1964 }, 1965 .num_parents = 1, 1966 .flags = CLK_SET_RATE_PARENT, 1967 .ops = &clk_branch2_ops, 1968 }, 1969 }, 1970 }; 1971 1972 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 1973 .halt_reg = 0x183a4, 1974 .halt_check = BRANCH_HALT_VOTED, 1975 .clkr = { 1976 .enable_reg = 0x5200c, 1977 .enable_mask = BIT(24), 1978 .hw.init = &(const struct clk_init_data) { 1979 .name = "gcc_qupv3_wrap1_s2_clk", 1980 .parent_hws = (const struct clk_hw*[]) { 1981 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 1982 }, 1983 .num_parents = 1, 1984 .flags = CLK_SET_RATE_PARENT, 1985 .ops = &clk_branch2_ops, 1986 }, 1987 }, 1988 }; 1989 1990 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 1991 .halt_reg = 0x184d4, 1992 .halt_check = BRANCH_HALT_VOTED, 1993 .clkr = { 1994 .enable_reg = 0x5200c, 1995 .enable_mask = BIT(25), 1996 .hw.init = &(const struct clk_init_data) { 1997 .name = "gcc_qupv3_wrap1_s3_clk", 1998 .parent_hws = (const struct clk_hw*[]) { 1999 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2000 }, 2001 .num_parents = 1, 2002 .flags = CLK_SET_RATE_PARENT, 2003 .ops = &clk_branch2_ops, 2004 }, 2005 }, 2006 }; 2007 2008 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2009 .halt_reg = 0x18604, 2010 .halt_check = BRANCH_HALT_VOTED, 2011 .clkr = { 2012 .enable_reg = 0x5200c, 2013 .enable_mask = BIT(26), 2014 .hw.init = &(const struct clk_init_data) { 2015 .name = "gcc_qupv3_wrap1_s4_clk", 2016 .parent_hws = (const struct clk_hw*[]) { 2017 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2018 }, 2019 .num_parents = 1, 2020 .flags = CLK_SET_RATE_PARENT, 2021 .ops = &clk_branch2_ops, 2022 }, 2023 }, 2024 }; 2025 2026 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2027 .halt_reg = 0x18734, 2028 .halt_check = BRANCH_HALT_VOTED, 2029 .clkr = { 2030 .enable_reg = 0x5200c, 2031 .enable_mask = BIT(27), 2032 .hw.init = &(const struct clk_init_data) { 2033 .name = "gcc_qupv3_wrap1_s5_clk", 2034 .parent_hws = (const struct clk_hw*[]) { 2035 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 2036 }, 2037 .num_parents = 1, 2038 .flags = CLK_SET_RATE_PARENT, 2039 .ops = &clk_branch2_ops, 2040 }, 2041 }, 2042 }; 2043 2044 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2045 .halt_reg = 0x17004, 2046 .halt_check = BRANCH_HALT_VOTED, 2047 .clkr = { 2048 .enable_reg = 0x5200c, 2049 .enable_mask = BIT(6), 2050 .hw.init = &(const struct clk_init_data) { 2051 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2052 .ops = &clk_branch2_ops, 2053 }, 2054 }, 2055 }; 2056 2057 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2058 .halt_reg = 0x17008, 2059 .halt_check = BRANCH_HALT_VOTED, 2060 .hwcg_reg = 0x17008, 2061 .hwcg_bit = 1, 2062 .clkr = { 2063 .enable_reg = 0x5200c, 2064 .enable_mask = BIT(7), 2065 .hw.init = &(const struct clk_init_data) { 2066 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2067 .ops = &clk_branch2_ops, 2068 }, 2069 }, 2070 }; 2071 2072 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2073 .halt_reg = 0x18004, 2074 .halt_check = BRANCH_HALT_VOTED, 2075 .clkr = { 2076 .enable_reg = 0x5200c, 2077 .enable_mask = BIT(20), 2078 .hw.init = &(const struct clk_init_data) { 2079 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2080 .ops = &clk_branch2_ops, 2081 }, 2082 }, 2083 }; 2084 2085 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2086 .halt_reg = 0x18008, 2087 .halt_check = BRANCH_HALT_VOTED, 2088 .hwcg_reg = 0x18008, 2089 .hwcg_bit = 1, 2090 .clkr = { 2091 .enable_reg = 0x5200c, 2092 .enable_mask = BIT(21), 2093 .hw.init = &(const struct clk_init_data) { 2094 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2095 .ops = &clk_branch2_ops, 2096 }, 2097 }, 2098 }; 2099 2100 static struct clk_branch gcc_rx1_usb2_clkref_clk = { 2101 .halt_reg = 0x8c030, 2102 .halt_check = BRANCH_HALT, 2103 .clkr = { 2104 .enable_reg = 0x8c030, 2105 .enable_mask = BIT(0), 2106 .hw.init = &(const struct clk_init_data) { 2107 .name = "gcc_rx1_usb2_clkref_clk", 2108 .ops = &clk_branch2_ops, 2109 }, 2110 }, 2111 }; 2112 2113 static struct clk_branch gcc_rx3_usb2_clkref_clk = { 2114 .halt_reg = 0x8c038, 2115 .halt_check = BRANCH_HALT_VOTED, 2116 .clkr = { 2117 .enable_reg = 0x8c038, 2118 .enable_mask = BIT(0), 2119 .hw.init = &(const struct clk_init_data) { 2120 .name = "gcc_rx3_usb2_clkref_clk", 2121 .ops = &clk_branch2_ops, 2122 }, 2123 }, 2124 }; 2125 2126 static struct clk_branch gcc_sdcc1_ahb_clk = { 2127 .halt_reg = 0x12008, 2128 .halt_check = BRANCH_HALT, 2129 .clkr = { 2130 .enable_reg = 0x12008, 2131 .enable_mask = BIT(0), 2132 .hw.init = &(const struct clk_init_data) { 2133 .name = "gcc_sdcc1_ahb_clk", 2134 .ops = &clk_branch2_ops, 2135 }, 2136 }, 2137 }; 2138 2139 static struct clk_branch gcc_sdcc1_apps_clk = { 2140 .halt_reg = 0x12004, 2141 .halt_check = BRANCH_HALT, 2142 .clkr = { 2143 .enable_reg = 0x12004, 2144 .enable_mask = BIT(0), 2145 .hw.init = &(const struct clk_init_data) { 2146 .name = "gcc_sdcc1_apps_clk", 2147 .parent_hws = (const struct clk_hw*[]) { 2148 &gcc_sdcc1_apps_clk_src.clkr.hw, 2149 }, 2150 .num_parents = 1, 2151 .flags = CLK_SET_RATE_PARENT, 2152 .ops = &clk_branch2_ops, 2153 }, 2154 }, 2155 }; 2156 2157 static struct clk_branch gcc_sdcc1_ice_core_clk = { 2158 .halt_reg = 0x1200c, 2159 .halt_check = BRANCH_HALT, 2160 .clkr = { 2161 .enable_reg = 0x1200c, 2162 .enable_mask = BIT(0), 2163 .hw.init = &(const struct clk_init_data) { 2164 .name = "gcc_sdcc1_ice_core_clk", 2165 .parent_hws = (const struct clk_hw*[]) { 2166 &gcc_sdcc1_ice_core_clk_src.clkr.hw, 2167 }, 2168 .num_parents = 1, 2169 .flags = CLK_SET_RATE_PARENT, 2170 .ops = &clk_branch2_ops, 2171 }, 2172 }, 2173 }; 2174 2175 static struct clk_branch gcc_sdcc2_ahb_clk = { 2176 .halt_reg = 0x14008, 2177 .halt_check = BRANCH_HALT, 2178 .clkr = { 2179 .enable_reg = 0x14008, 2180 .enable_mask = BIT(0), 2181 .hw.init = &(const struct clk_init_data) { 2182 .name = "gcc_sdcc2_ahb_clk", 2183 .ops = &clk_branch2_ops, 2184 }, 2185 }, 2186 }; 2187 2188 static struct clk_branch gcc_sdcc2_apps_clk = { 2189 .halt_reg = 0x14004, 2190 .halt_check = BRANCH_HALT, 2191 .clkr = { 2192 .enable_reg = 0x14004, 2193 .enable_mask = BIT(0), 2194 .hw.init = &(const struct clk_init_data) { 2195 .name = "gcc_sdcc2_apps_clk", 2196 .parent_hws = (const struct clk_hw*[]) { 2197 &gcc_sdcc2_apps_clk_src.clkr.hw, 2198 }, 2199 .num_parents = 1, 2200 .flags = CLK_SET_RATE_PARENT, 2201 .ops = &clk_branch2_ops, 2202 }, 2203 }, 2204 }; 2205 2206 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 2207 .halt_reg = 0x4819c, 2208 .halt_check = BRANCH_HALT_VOTED, 2209 .clkr = { 2210 .enable_reg = 0x52004, 2211 .enable_mask = BIT(0), 2212 .hw.init = &(struct clk_init_data) { 2213 .name = "gcc_sys_noc_cpuss_ahb_clk", 2214 .parent_data = &(const struct clk_parent_data) { 2215 .hw = &gcc_cpuss_ahb_clk_src.clkr.hw, 2216 }, 2217 .num_parents = 1, 2218 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 2219 .ops = &clk_branch2_ops, 2220 }, 2221 }, 2222 }; 2223 2224 static struct clk_branch gcc_ufs_card_clkref_clk = { 2225 .halt_reg = 0x8c004, 2226 .halt_check = BRANCH_HALT_VOTED, 2227 .clkr = { 2228 .enable_reg = 0x8c004, 2229 .enable_mask = BIT(0), 2230 .hw.init = &(const struct clk_init_data) { 2231 .name = "gcc_ufs_card_clkref_clk", 2232 .ops = &clk_branch2_ops, 2233 }, 2234 }, 2235 }; 2236 2237 static struct clk_branch gcc_ufs_mem_clkref_clk = { 2238 .halt_reg = 0x8c000, 2239 .halt_check = BRANCH_HALT, 2240 .clkr = { 2241 .enable_reg = 0x8c000, 2242 .enable_mask = BIT(0), 2243 .hw.init = &(const struct clk_init_data) { 2244 .name = "gcc_ufs_mem_clkref_clk", 2245 .ops = &clk_branch2_ops, 2246 }, 2247 }, 2248 }; 2249 2250 static struct clk_branch gcc_ufs_phy_ahb_clk = { 2251 .halt_reg = 0x77014, 2252 .halt_check = BRANCH_HALT_VOTED, 2253 .hwcg_reg = 0x77014, 2254 .hwcg_bit = 1, 2255 .clkr = { 2256 .enable_reg = 0x77014, 2257 .enable_mask = BIT(0), 2258 .hw.init = &(const struct clk_init_data) { 2259 .name = "gcc_ufs_phy_ahb_clk", 2260 .ops = &clk_branch2_ops, 2261 }, 2262 }, 2263 }; 2264 2265 static struct clk_branch gcc_ufs_phy_axi_clk = { 2266 .halt_reg = 0x77010, 2267 .halt_check = BRANCH_HALT, 2268 .hwcg_reg = 0x77010, 2269 .hwcg_bit = 1, 2270 .clkr = { 2271 .enable_reg = 0x77010, 2272 .enable_mask = BIT(0), 2273 .hw.init = &(const struct clk_init_data) { 2274 .name = "gcc_ufs_phy_axi_clk", 2275 .parent_hws = (const struct clk_hw*[]) { 2276 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2277 }, 2278 .num_parents = 1, 2279 .flags = CLK_SET_RATE_PARENT, 2280 .ops = &clk_branch2_ops, 2281 }, 2282 }, 2283 }; 2284 2285 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2286 .halt_reg = 0x77044, 2287 .halt_check = BRANCH_HALT, 2288 .hwcg_reg = 0x77044, 2289 .hwcg_bit = 1, 2290 .clkr = { 2291 .enable_reg = 0x77044, 2292 .enable_mask = BIT(0), 2293 .hw.init = &(const struct clk_init_data) { 2294 .name = "gcc_ufs_phy_ice_core_clk", 2295 .parent_hws = (const struct clk_hw*[]) { 2296 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2297 }, 2298 .num_parents = 1, 2299 .flags = CLK_SET_RATE_PARENT, 2300 .ops = &clk_branch2_ops, 2301 }, 2302 }, 2303 }; 2304 2305 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2306 .halt_reg = 0x77078, 2307 .halt_check = BRANCH_HALT, 2308 .hwcg_reg = 0x77078, 2309 .hwcg_bit = 1, 2310 .clkr = { 2311 .enable_reg = 0x77078, 2312 .enable_mask = BIT(0), 2313 .hw.init = &(const struct clk_init_data) { 2314 .name = "gcc_ufs_phy_phy_aux_clk", 2315 .parent_hws = (const struct clk_hw*[]) { 2316 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2317 }, 2318 .num_parents = 1, 2319 .flags = CLK_SET_RATE_PARENT, 2320 .ops = &clk_branch2_ops, 2321 }, 2322 }, 2323 }; 2324 2325 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2326 .halt_reg = 0x7701c, 2327 .halt_check = BRANCH_HALT_DELAY, 2328 .clkr = { 2329 .enable_reg = 0x7701c, 2330 .enable_mask = BIT(0), 2331 .hw.init = &(const struct clk_init_data) { 2332 .name = "gcc_ufs_phy_rx_symbol_0_clk", 2333 .ops = &clk_branch2_ops, 2334 }, 2335 }, 2336 }; 2337 2338 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2339 .halt_reg = 0x77018, 2340 .halt_check = BRANCH_HALT_DELAY, 2341 .clkr = { 2342 .enable_reg = 0x77018, 2343 .enable_mask = BIT(0), 2344 .hw.init = &(const struct clk_init_data) { 2345 .name = "gcc_ufs_phy_tx_symbol_0_clk", 2346 .ops = &clk_branch2_ops, 2347 }, 2348 }, 2349 }; 2350 2351 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2352 .halt_reg = 0x77040, 2353 .halt_check = BRANCH_HALT, 2354 .hwcg_reg = 0x77040, 2355 .hwcg_bit = 1, 2356 .clkr = { 2357 .enable_reg = 0x77040, 2358 .enable_mask = BIT(0), 2359 .hw.init = &(const struct clk_init_data) { 2360 .name = "gcc_ufs_phy_unipro_core_clk", 2361 .parent_hws = (const struct clk_hw*[]) { 2362 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2363 }, 2364 .num_parents = 1, 2365 .flags = CLK_SET_RATE_PARENT, 2366 .ops = &clk_branch2_ops, 2367 }, 2368 }, 2369 }; 2370 2371 static struct clk_branch gcc_usb20_sec_master_clk = { 2372 .halt_reg = 0xa6010, 2373 .halt_check = BRANCH_HALT_VOTED, 2374 .clkr = { 2375 .enable_reg = 0xa6010, 2376 .enable_mask = BIT(0), 2377 .hw.init = &(const struct clk_init_data) { 2378 .name = "gcc_usb20_sec_master_clk", 2379 .parent_hws = (const struct clk_hw*[]) { 2380 &gcc_usb20_sec_master_clk_src.clkr.hw, 2381 }, 2382 .num_parents = 1, 2383 .flags = CLK_SET_RATE_PARENT, 2384 .ops = &clk_branch2_ops, 2385 }, 2386 }, 2387 }; 2388 2389 static struct clk_branch gcc_usb20_sec_mock_utmi_clk = { 2390 .halt_reg = 0xa6018, 2391 .halt_check = BRANCH_HALT, 2392 .clkr = { 2393 .enable_reg = 0xa6018, 2394 .enable_mask = BIT(0), 2395 .hw.init = &(const struct clk_init_data) { 2396 .name = "gcc_usb20_sec_mock_utmi_clk", 2397 .parent_hws = (const struct clk_hw*[]) { 2398 &gcc_usb20_sec_mock_utmi_clk_src.clkr.hw, 2399 }, 2400 .num_parents = 1, 2401 .flags = CLK_SET_RATE_PARENT, 2402 .ops = &clk_branch2_ops, 2403 }, 2404 }, 2405 }; 2406 2407 static struct clk_branch gcc_usb20_sec_sleep_clk = { 2408 .halt_reg = 0xa6014, 2409 .halt_check = BRANCH_HALT, 2410 .clkr = { 2411 .enable_reg = 0xa6014, 2412 .enable_mask = BIT(0), 2413 .hw.init = &(const struct clk_init_data) { 2414 .name = "gcc_usb20_sec_sleep_clk", 2415 .ops = &clk_branch2_ops, 2416 }, 2417 }, 2418 }; 2419 2420 static struct clk_branch gcc_usb2_prim_clkref_clk = { 2421 .halt_reg = 0x8c028, 2422 .halt_check = BRANCH_HALT_VOTED, 2423 .clkr = { 2424 .enable_reg = 0x8c028, 2425 .enable_mask = BIT(0), 2426 .hw.init = &(const struct clk_init_data) { 2427 .name = "gcc_usb2_prim_clkref_clk", 2428 .ops = &clk_branch2_ops, 2429 }, 2430 }, 2431 }; 2432 2433 static struct clk_branch gcc_usb2_sec_clkref_clk = { 2434 .halt_reg = 0x8c018, 2435 .halt_check = BRANCH_HALT_VOTED, 2436 .clkr = { 2437 .enable_reg = 0x8c018, 2438 .enable_mask = BIT(0), 2439 .hw.init = &(const struct clk_init_data) { 2440 .name = "gcc_usb2_sec_clkref_clk", 2441 .ops = &clk_branch2_ops, 2442 }, 2443 }, 2444 }; 2445 2446 static struct clk_branch gcc_usb2_sec_phy_aux_clk = { 2447 .halt_reg = 0xa6050, 2448 .halt_check = BRANCH_HALT, 2449 .clkr = { 2450 .enable_reg = 0xa6050, 2451 .enable_mask = BIT(0), 2452 .hw.init = &(const struct clk_init_data) { 2453 .name = "gcc_usb2_sec_phy_aux_clk", 2454 .parent_hws = (const struct clk_hw*[]) { 2455 &gcc_usb2_sec_phy_aux_clk_src.clkr.hw, 2456 }, 2457 .num_parents = 1, 2458 .flags = CLK_SET_RATE_PARENT, 2459 .ops = &clk_branch2_ops, 2460 }, 2461 }, 2462 }; 2463 2464 static struct clk_branch gcc_usb2_sec_phy_com_aux_clk = { 2465 .halt_reg = 0xa6054, 2466 .halt_check = BRANCH_HALT, 2467 .clkr = { 2468 .enable_reg = 0xa6054, 2469 .enable_mask = BIT(0), 2470 .hw.init = &(const struct clk_init_data) { 2471 .name = "gcc_usb2_sec_phy_com_aux_clk", 2472 .parent_hws = (const struct clk_hw*[]) { 2473 &gcc_usb2_sec_phy_aux_clk_src.clkr.hw, 2474 }, 2475 .num_parents = 1, 2476 .flags = CLK_SET_RATE_PARENT, 2477 .ops = &clk_branch2_ops, 2478 }, 2479 }, 2480 }; 2481 2482 static struct clk_branch gcc_usb2_sec_phy_pipe_clk = { 2483 .halt_reg = 0xa6058, 2484 .halt_check = BRANCH_HALT_SKIP, 2485 .clkr = { 2486 .enable_reg = 0xa6058, 2487 .enable_mask = BIT(0), 2488 .hw.init = &(const struct clk_init_data) { 2489 .name = "gcc_usb2_sec_phy_pipe_clk", 2490 .ops = &clk_branch2_ops, 2491 }, 2492 }, 2493 }; 2494 2495 static struct clk_branch gcc_usb30_prim_master_clk = { 2496 .halt_reg = 0xf010, 2497 .halt_check = BRANCH_HALT_VOTED, 2498 .clkr = { 2499 .enable_reg = 0xf010, 2500 .enable_mask = BIT(0), 2501 .hw.init = &(const struct clk_init_data) { 2502 .name = "gcc_usb30_prim_master_clk", 2503 .parent_hws = (const struct clk_hw*[]) { 2504 &gcc_usb30_prim_master_clk_src.clkr.hw, 2505 }, 2506 .num_parents = 1, 2507 .flags = CLK_SET_RATE_PARENT, 2508 .ops = &clk_branch2_ops, 2509 }, 2510 }, 2511 }; 2512 2513 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2514 .halt_reg = 0xf018, 2515 .halt_check = BRANCH_HALT, 2516 .clkr = { 2517 .enable_reg = 0xf018, 2518 .enable_mask = BIT(0), 2519 .hw.init = &(const struct clk_init_data) { 2520 .name = "gcc_usb30_prim_mock_utmi_clk", 2521 .parent_hws = (const struct clk_hw*[]) { 2522 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 2523 }, 2524 .num_parents = 1, 2525 .flags = CLK_SET_RATE_PARENT, 2526 .ops = &clk_branch2_ops, 2527 }, 2528 }, 2529 }; 2530 2531 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2532 .halt_reg = 0xf014, 2533 .halt_check = BRANCH_HALT, 2534 .clkr = { 2535 .enable_reg = 0xf014, 2536 .enable_mask = BIT(0), 2537 .hw.init = &(const struct clk_init_data) { 2538 .name = "gcc_usb30_prim_sleep_clk", 2539 .ops = &clk_branch2_ops, 2540 }, 2541 }, 2542 }; 2543 2544 static struct clk_branch gcc_usb3_prim_clkref_clk = { 2545 .halt_reg = 0x8c014, 2546 .halt_check = BRANCH_HALT_DELAY, 2547 .clkr = { 2548 .enable_reg = 0x8c014, 2549 .enable_mask = BIT(0), 2550 .hw.init = &(const struct clk_init_data) { 2551 .name = "gcc_usb3_prim_clkref_clk", 2552 .ops = &clk_branch2_ops, 2553 }, 2554 }, 2555 }; 2556 2557 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2558 .halt_reg = 0xf050, 2559 .halt_check = BRANCH_HALT, 2560 .clkr = { 2561 .enable_reg = 0xf050, 2562 .enable_mask = BIT(0), 2563 .hw.init = &(const struct clk_init_data) { 2564 .name = "gcc_usb3_prim_phy_aux_clk", 2565 .parent_hws = (const struct clk_hw*[]) { 2566 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2567 }, 2568 .num_parents = 1, 2569 .flags = CLK_SET_RATE_PARENT, 2570 .ops = &clk_branch2_ops, 2571 }, 2572 }, 2573 }; 2574 2575 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2576 .halt_reg = 0xf054, 2577 .halt_check = BRANCH_HALT, 2578 .clkr = { 2579 .enable_reg = 0xf054, 2580 .enable_mask = BIT(0), 2581 .hw.init = &(const struct clk_init_data) { 2582 .name = "gcc_usb3_prim_phy_com_aux_clk", 2583 .parent_hws = (const struct clk_hw*[]) { 2584 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2585 }, 2586 .num_parents = 1, 2587 .flags = CLK_SET_RATE_PARENT, 2588 .ops = &clk_branch2_ops, 2589 }, 2590 }, 2591 }; 2592 2593 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2594 .halt_reg = 0xf058, 2595 .halt_check = BRANCH_HALT_SKIP, 2596 .clkr = { 2597 .enable_reg = 0xf058, 2598 .enable_mask = BIT(0), 2599 .hw.init = &(const struct clk_init_data) { 2600 .name = "gcc_usb3_prim_phy_pipe_clk", 2601 .ops = &clk_branch2_ops, 2602 }, 2603 }, 2604 }; 2605 2606 static struct clk_branch gcc_usb3_sec_clkref_clk = { 2607 .halt_reg = 0x8c008, 2608 .halt_check = BRANCH_HALT_DELAY, 2609 .clkr = { 2610 .enable_reg = 0x8c008, 2611 .enable_mask = BIT(0), 2612 .hw.init = &(const struct clk_init_data) { 2613 .name = "gcc_usb3_sec_clkref_clk", 2614 .ops = &clk_branch2_ops, 2615 }, 2616 }, 2617 }; 2618 2619 static struct clk_branch gcc_video_axi0_clk = { 2620 .halt_reg = 0xb024, 2621 .halt_check = BRANCH_HALT_VOTED, 2622 .clkr = { 2623 .enable_reg = 0xb024, 2624 .enable_mask = BIT(0), 2625 .hw.init = &(const struct clk_init_data) { 2626 .name = "gcc_video_axi0_clk", 2627 .ops = &clk_branch2_ops, 2628 }, 2629 }, 2630 }; 2631 2632 static struct clk_hw *gcc_qcs615_hws[] = { 2633 [GPLL0_OUT_AUX2_DIV] = &gpll0_out_aux2_div.hw, 2634 [GPLL3_OUT_AUX2_DIV] = &gpll3_out_aux2_div.hw, 2635 }; 2636 2637 static struct gdsc emac_gdsc = { 2638 .gdscr = 0x6004, 2639 .en_rest_wait_val = 0x2, 2640 .en_few_wait_val = 0x2, 2641 .clk_dis_wait_val = 0x2, 2642 .pd = { 2643 .name = "emac_gdsc", 2644 }, 2645 .pwrsts = PWRSTS_OFF_ON, 2646 }; 2647 2648 static struct gdsc pcie_0_gdsc = { 2649 .gdscr = 0x6b004, 2650 .en_rest_wait_val = 0x2, 2651 .en_few_wait_val = 0x2, 2652 .clk_dis_wait_val = 0x2, 2653 .pd = { 2654 .name = "pcie_0_gdsc", 2655 }, 2656 .pwrsts = PWRSTS_OFF_ON, 2657 }; 2658 2659 static struct gdsc ufs_phy_gdsc = { 2660 .gdscr = 0x77004, 2661 .en_rest_wait_val = 0x2, 2662 .en_few_wait_val = 0x2, 2663 .clk_dis_wait_val = 0x2, 2664 .pd = { 2665 .name = "ufs_phy_gdsc", 2666 }, 2667 .pwrsts = PWRSTS_OFF_ON, 2668 }; 2669 2670 static struct gdsc usb20_sec_gdsc = { 2671 .gdscr = 0xa6004, 2672 .en_rest_wait_val = 0x2, 2673 .en_few_wait_val = 0x2, 2674 .clk_dis_wait_val = 0x2, 2675 .pd = { 2676 .name = "usb20_sec_gdsc", 2677 }, 2678 .pwrsts = PWRSTS_OFF_ON, 2679 }; 2680 2681 static struct gdsc usb30_prim_gdsc = { 2682 .gdscr = 0xf004, 2683 .en_rest_wait_val = 0x2, 2684 .en_few_wait_val = 0x2, 2685 .clk_dis_wait_val = 0x2, 2686 .pd = { 2687 .name = "usb30_prim_gdsc", 2688 }, 2689 .pwrsts = PWRSTS_OFF_ON, 2690 }; 2691 2692 static struct gdsc hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = { 2693 .gdscr = 0x7d040, 2694 .pd = { 2695 .name = "hlos1_vote_aggre_noc_mmu_audio_tbu", 2696 }, 2697 .pwrsts = PWRSTS_OFF_ON, 2698 .flags = VOTABLE, 2699 }; 2700 2701 static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = { 2702 .gdscr = 0x7d044, 2703 .pd = { 2704 .name = "hlos1_vote_aggre_noc_mmu_tbu1", 2705 }, 2706 .pwrsts = PWRSTS_OFF_ON, 2707 .flags = VOTABLE, 2708 }; 2709 2710 static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = { 2711 .gdscr = 0x7d048, 2712 .pd = { 2713 .name = "hlos1_vote_aggre_noc_mmu_tbu2", 2714 }, 2715 .pwrsts = PWRSTS_OFF_ON, 2716 .flags = VOTABLE, 2717 }; 2718 2719 static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = { 2720 .gdscr = 0x7d04c, 2721 .pd = { 2722 .name = "hlos1_vote_aggre_noc_mmu_pcie_tbu", 2723 }, 2724 .pwrsts = PWRSTS_OFF_ON, 2725 .flags = VOTABLE, 2726 }; 2727 2728 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = { 2729 .gdscr = 0x7d050, 2730 .pd = { 2731 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", 2732 }, 2733 .pwrsts = PWRSTS_OFF_ON, 2734 .flags = VOTABLE, 2735 }; 2736 2737 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = { 2738 .gdscr = 0x7d054, 2739 .pd = { 2740 .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc", 2741 }, 2742 .pwrsts = PWRSTS_OFF_ON, 2743 .flags = VOTABLE, 2744 }; 2745 2746 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = { 2747 .gdscr = 0x7d058, 2748 .pd = { 2749 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", 2750 }, 2751 .pwrsts = PWRSTS_OFF_ON, 2752 .flags = VOTABLE, 2753 }; 2754 2755 static struct clk_regmap *gcc_qcs615_clocks[] = { 2756 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 2757 [GCC_AGGRE_USB2_SEC_AXI_CLK] = &gcc_aggre_usb2_sec_axi_clk.clkr, 2758 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 2759 [GCC_AHB2PHY_EAST_CLK] = &gcc_ahb2phy_east_clk.clkr, 2760 [GCC_AHB2PHY_WEST_CLK] = &gcc_ahb2phy_west_clk.clkr, 2761 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2762 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 2763 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, 2764 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, 2765 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, 2766 [GCC_CFG_NOC_USB2_SEC_AXI_CLK] = &gcc_cfg_noc_usb2_sec_axi_clk.clkr, 2767 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 2768 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, 2769 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, 2770 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 2771 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, 2772 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 2773 [GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr, 2774 [GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr, 2775 [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr, 2776 [GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr, 2777 [GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr, 2778 [GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr, 2779 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2780 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 2781 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2782 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 2783 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2784 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 2785 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 2786 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 2787 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, 2788 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 2789 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 2790 [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr, 2791 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 2792 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 2793 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 2794 [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr, 2795 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 2796 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 2797 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 2798 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 2799 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, 2800 [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr, 2801 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2802 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 2803 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2804 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 2805 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 2806 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 2807 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 2808 [GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr, 2809 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 2810 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, 2811 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, 2812 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, 2813 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 2814 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 2815 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 2816 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 2817 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 2818 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 2819 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 2820 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 2821 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 2822 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 2823 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 2824 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 2825 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 2826 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 2827 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 2828 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 2829 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 2830 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 2831 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 2832 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 2833 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 2834 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 2835 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 2836 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 2837 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 2838 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 2839 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 2840 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 2841 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 2842 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 2843 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 2844 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 2845 [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr, 2846 [GCC_RX3_USB2_CLKREF_CLK] = &gcc_rx3_usb2_clkref_clk.clkr, 2847 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2848 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2849 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 2850 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 2851 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 2852 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2853 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2854 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 2855 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 2856 [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr, 2857 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, 2858 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 2859 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 2860 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 2861 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 2862 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 2863 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 2864 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 2865 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 2866 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 2867 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 2868 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 2869 [GCC_USB20_SEC_MASTER_CLK] = &gcc_usb20_sec_master_clk.clkr, 2870 [GCC_USB20_SEC_MASTER_CLK_SRC] = &gcc_usb20_sec_master_clk_src.clkr, 2871 [GCC_USB20_SEC_MOCK_UTMI_CLK] = &gcc_usb20_sec_mock_utmi_clk.clkr, 2872 [GCC_USB20_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb20_sec_mock_utmi_clk_src.clkr, 2873 [GCC_USB20_SEC_SLEEP_CLK] = &gcc_usb20_sec_sleep_clk.clkr, 2874 [GCC_USB2_PRIM_CLKREF_CLK] = &gcc_usb2_prim_clkref_clk.clkr, 2875 [GCC_USB2_SEC_CLKREF_CLK] = &gcc_usb2_sec_clkref_clk.clkr, 2876 [GCC_USB2_SEC_PHY_AUX_CLK] = &gcc_usb2_sec_phy_aux_clk.clkr, 2877 [GCC_USB2_SEC_PHY_AUX_CLK_SRC] = &gcc_usb2_sec_phy_aux_clk_src.clkr, 2878 [GCC_USB2_SEC_PHY_COM_AUX_CLK] = &gcc_usb2_sec_phy_com_aux_clk.clkr, 2879 [GCC_USB2_SEC_PHY_PIPE_CLK] = &gcc_usb2_sec_phy_pipe_clk.clkr, 2880 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 2881 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 2882 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 2883 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 2884 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 2885 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 2886 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 2887 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 2888 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 2889 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 2890 [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr, 2891 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 2892 [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr, 2893 [GPLL0] = &gpll0.clkr, 2894 [GPLL3] = &gpll3.clkr, 2895 [GPLL4] = &gpll4.clkr, 2896 [GPLL6] = &gpll6.clkr, 2897 [GPLL6_OUT_MAIN] = &gpll6_out_main.clkr, 2898 [GPLL7] = &gpll7.clkr, 2899 [GPLL8] = &gpll8.clkr, 2900 [GPLL8_OUT_MAIN] = &gpll8_out_main.clkr, 2901 }; 2902 2903 static struct gdsc *gcc_qcs615_gdscs[] = { 2904 [EMAC_GDSC] = &emac_gdsc, 2905 [PCIE_0_GDSC] = &pcie_0_gdsc, 2906 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 2907 [USB20_SEC_GDSC] = &usb20_sec_gdsc, 2908 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 2909 [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc, 2910 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = &hlos1_vote_aggre_noc_mmu_tbu1_gdsc, 2911 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = &hlos1_vote_aggre_noc_mmu_tbu2_gdsc, 2912 [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = &hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc, 2913 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, 2914 [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc, 2915 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc, 2916 }; 2917 2918 static const struct qcom_reset_map gcc_qcs615_resets[] = { 2919 [GCC_EMAC_BCR] = { 0x6000 }, 2920 [GCC_QUSB2PHY_PRIM_BCR] = { 0xd000 }, 2921 [GCC_QUSB2PHY_SEC_BCR] = { 0xd004 }, 2922 [GCC_USB30_PRIM_BCR] = { 0xf000 }, 2923 [GCC_USB2_PHY_SEC_BCR] = { 0x50018 }, 2924 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50020 }, 2925 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x5001c }, 2926 [GCC_PCIE_0_BCR] = { 0x6b000 }, 2927 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 2928 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 2929 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, 2930 [GCC_UFS_PHY_BCR] = { 0x77000 }, 2931 [GCC_USB20_SEC_BCR] = { 0xa6000 }, 2932 [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x50008 }, 2933 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x50000 }, 2934 [GCC_SDCC1_BCR] = { 0x12000 }, 2935 [GCC_SDCC2_BCR] = { 0x14000 }, 2936 }; 2937 2938 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 2939 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 2940 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 2941 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 2942 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 2943 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 2944 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 2945 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 2946 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 2947 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 2948 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 2949 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 2950 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 2951 }; 2952 2953 static const struct regmap_config gcc_qcs615_regmap_config = { 2954 .reg_bits = 32, 2955 .reg_stride = 4, 2956 .val_bits = 32, 2957 .max_register = 0xa609c, 2958 .fast_io = true, 2959 }; 2960 2961 static const struct qcom_cc_desc gcc_qcs615_desc = { 2962 .config = &gcc_qcs615_regmap_config, 2963 .clk_hws = gcc_qcs615_hws, 2964 .num_clk_hws = ARRAY_SIZE(gcc_qcs615_hws), 2965 .clks = gcc_qcs615_clocks, 2966 .num_clks = ARRAY_SIZE(gcc_qcs615_clocks), 2967 .resets = gcc_qcs615_resets, 2968 .num_resets = ARRAY_SIZE(gcc_qcs615_resets), 2969 .gdscs = gcc_qcs615_gdscs, 2970 .num_gdscs = ARRAY_SIZE(gcc_qcs615_gdscs), 2971 }; 2972 2973 static const struct of_device_id gcc_qcs615_match_table[] = { 2974 { .compatible = "qcom,qcs615-gcc" }, 2975 { } 2976 }; 2977 MODULE_DEVICE_TABLE(of, gcc_qcs615_match_table); 2978 2979 static int gcc_qcs615_probe(struct platform_device *pdev) 2980 { 2981 struct regmap *regmap; 2982 int ret; 2983 2984 regmap = qcom_cc_map(pdev, &gcc_qcs615_desc); 2985 if (IS_ERR(regmap)) 2986 return PTR_ERR(regmap); 2987 /* 2988 * Disable the GPLL0 active input to MM blocks and GPU 2989 * via MISC registers. 2990 */ 2991 regmap_update_bits(regmap, 0x0b084, BIT(0), BIT(0)); 2992 regmap_update_bits(regmap, 0x9b000, BIT(0), BIT(0)); 2993 2994 /* Keep some clocks always enabled */ 2995 qcom_branch_set_clk_en(regmap, 0xb008); /* GCC_CAMERA_AHB_CLK */ 2996 qcom_branch_set_clk_en(regmap, 0xb044); /* GCC_CAMERA_XO_CLK */ 2997 qcom_branch_set_clk_en(regmap, 0xb00c); /* GCC_DISP_AHB_CLK */ 2998 qcom_branch_set_clk_en(regmap, 0xb048); /* GCC_DISP_XO_CLK */ 2999 qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ 3000 qcom_branch_set_clk_en(regmap, 0xb004); /* GCC_VIDEO_AHB_CLK */ 3001 qcom_branch_set_clk_en(regmap, 0xb040); /* GCC_VIDEO_XO_CLK */ 3002 qcom_branch_set_clk_en(regmap, 0x480040); /* GCC_CPUSS_GNOC_CLK */ 3003 3004 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3005 ARRAY_SIZE(gcc_dfs_clocks)); 3006 if (ret) 3007 return ret; 3008 3009 return qcom_cc_really_probe(&pdev->dev, &gcc_qcs615_desc, regmap); 3010 } 3011 3012 static struct platform_driver gcc_qcs615_driver = { 3013 .probe = gcc_qcs615_probe, 3014 .driver = { 3015 .name = "gcc-qcs615", 3016 .of_match_table = gcc_qcs615_match_table, 3017 }, 3018 }; 3019 3020 static int __init gcc_qcs615_init(void) 3021 { 3022 return platform_driver_register(&gcc_qcs615_driver); 3023 } 3024 subsys_initcall(gcc_qcs615_init); 3025 3026 static void __exit gcc_qcs615_exit(void) 3027 { 3028 platform_driver_unregister(&gcc_qcs615_driver); 3029 } 3030 module_exit(gcc_qcs615_exit); 3031 3032 MODULE_DESCRIPTION("QTI GCC QCS615 Driver"); 3033 MODULE_LICENSE("GPL"); 3034