1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/err.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 13 #include <dt-bindings/clock/qcom,gcc-qcm2290.h> 14 15 #include "clk-alpha-pll.h" 16 #include "clk-branch.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap-divider.h" 19 #include "common.h" 20 #include "gdsc.h" 21 #include "reset.h" 22 23 enum { 24 P_BI_TCXO, 25 P_GPLL0_OUT_AUX2, 26 P_GPLL0_OUT_EARLY, 27 P_GPLL10_OUT_MAIN, 28 P_GPLL11_OUT_AUX, 29 P_GPLL11_OUT_AUX2, 30 P_GPLL11_OUT_MAIN, 31 P_GPLL3_OUT_EARLY, 32 P_GPLL3_OUT_MAIN, 33 P_GPLL4_OUT_MAIN, 34 P_GPLL5_OUT_MAIN, 35 P_GPLL6_OUT_EARLY, 36 P_GPLL6_OUT_MAIN, 37 P_GPLL7_OUT_MAIN, 38 P_GPLL8_OUT_EARLY, 39 P_GPLL8_OUT_MAIN, 40 P_GPLL9_OUT_EARLY, 41 P_GPLL9_OUT_MAIN, 42 P_SLEEP_CLK, 43 }; 44 45 static const struct pll_vco brammo_vco[] = { 46 { 500000000, 1250000000, 0 }, 47 }; 48 49 static const struct pll_vco default_vco[] = { 50 { 500000000, 1000000000, 2 }, 51 }; 52 53 static const struct pll_vco spark_vco[] = { 54 { 750000000, 1500000000, 1 }, 55 }; 56 57 static struct clk_alpha_pll gpll0 = { 58 .offset = 0x0, 59 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 60 .clkr = { 61 .enable_reg = 0x79000, 62 .enable_mask = BIT(0), 63 .hw.init = &(struct clk_init_data){ 64 .name = "gpll0", 65 .parent_data = &(const struct clk_parent_data){ 66 .fw_name = "bi_tcxo", 67 }, 68 .num_parents = 1, 69 .ops = &clk_alpha_pll_ops, 70 }, 71 }, 72 }; 73 74 static const struct clk_div_table post_div_table_gpll0_out_aux2[] = { 75 { 0x1, 2 }, 76 { } 77 }; 78 79 static struct clk_alpha_pll_postdiv gpll0_out_aux2 = { 80 .offset = 0x0, 81 .post_div_shift = 8, 82 .post_div_table = post_div_table_gpll0_out_aux2, 83 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2), 84 .width = 4, 85 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 86 .clkr.hw.init = &(struct clk_init_data){ 87 .name = "gpll0_out_aux2", 88 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 89 .num_parents = 1, 90 .ops = &clk_alpha_pll_postdiv_ro_ops, 91 }, 92 }; 93 94 static struct clk_alpha_pll gpll1 = { 95 .offset = 0x1000, 96 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 97 .clkr = { 98 .enable_reg = 0x79000, 99 .enable_mask = BIT(1), 100 .hw.init = &(struct clk_init_data){ 101 .name = "gpll1", 102 .parent_data = &(const struct clk_parent_data){ 103 .fw_name = "bi_tcxo", 104 }, 105 .num_parents = 1, 106 .ops = &clk_alpha_pll_ops, 107 }, 108 }, 109 }; 110 111 /* 1152MHz configuration */ 112 static const struct alpha_pll_config gpll10_config = { 113 .l = 0x3c, 114 .alpha = 0x0, 115 .vco_val = 0x1 << 20, 116 .vco_mask = GENMASK(21, 20), 117 .main_output_mask = BIT(0), 118 .config_ctl_val = 0x4001055B, 119 .test_ctl_hi_val = 0x1, 120 }; 121 122 static struct clk_alpha_pll gpll10 = { 123 .offset = 0xa000, 124 .vco_table = spark_vco, 125 .num_vco = ARRAY_SIZE(spark_vco), 126 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 127 .clkr = { 128 .enable_reg = 0x79000, 129 .enable_mask = BIT(10), 130 .hw.init = &(struct clk_init_data){ 131 .name = "gpll10", 132 .parent_data = &(const struct clk_parent_data){ 133 .fw_name = "bi_tcxo", 134 }, 135 .num_parents = 1, 136 .ops = &clk_alpha_pll_ops, 137 }, 138 }, 139 }; 140 141 /* 532MHz configuration */ 142 static const struct alpha_pll_config gpll11_config = { 143 .l = 0x1B, 144 .alpha = 0x55555555, 145 .alpha_hi = 0xB5, 146 .alpha_en_mask = BIT(24), 147 .vco_val = 0x2 << 20, 148 .vco_mask = GENMASK(21, 20), 149 .main_output_mask = BIT(0), 150 .config_ctl_val = 0x4001055B, 151 .test_ctl_hi_val = 0x1, 152 }; 153 154 static struct clk_alpha_pll gpll11 = { 155 .offset = 0xb000, 156 .vco_table = default_vco, 157 .num_vco = ARRAY_SIZE(default_vco), 158 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 159 .flags = SUPPORTS_DYNAMIC_UPDATE, 160 .clkr = { 161 .enable_reg = 0x79000, 162 .enable_mask = BIT(11), 163 .hw.init = &(struct clk_init_data){ 164 .name = "gpll11", 165 .parent_data = &(const struct clk_parent_data){ 166 .fw_name = "bi_tcxo", 167 }, 168 .num_parents = 1, 169 .ops = &clk_alpha_pll_ops, 170 }, 171 }, 172 }; 173 174 static struct clk_alpha_pll gpll3 = { 175 .offset = 0x3000, 176 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 177 .clkr = { 178 .enable_reg = 0x79000, 179 .enable_mask = BIT(3), 180 .hw.init = &(struct clk_init_data){ 181 .name = "gpll3", 182 .parent_data = &(const struct clk_parent_data){ 183 .fw_name = "bi_tcxo", 184 }, 185 .num_parents = 1, 186 .ops = &clk_alpha_pll_ops, 187 }, 188 }, 189 }; 190 191 static const struct clk_div_table post_div_table_gpll3_out_main[] = { 192 { 0x1, 2 }, 193 { } 194 }; 195 196 static struct clk_alpha_pll_postdiv gpll3_out_main = { 197 .offset = 0x3000, 198 .post_div_shift = 8, 199 .post_div_table = post_div_table_gpll3_out_main, 200 .num_post_div = ARRAY_SIZE(post_div_table_gpll3_out_main), 201 .width = 4, 202 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 203 .clkr.hw.init = &(struct clk_init_data){ 204 .name = "gpll3_out_main", 205 .parent_hws = (const struct clk_hw *[]){ &gpll3.clkr.hw }, 206 .num_parents = 1, 207 .ops = &clk_alpha_pll_postdiv_ro_ops, 208 }, 209 }; 210 211 static struct clk_alpha_pll gpll4 = { 212 .offset = 0x4000, 213 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 214 .clkr = { 215 .enable_reg = 0x79000, 216 .enable_mask = BIT(4), 217 .hw.init = &(struct clk_init_data){ 218 .name = "gpll4", 219 .parent_data = &(const struct clk_parent_data){ 220 .fw_name = "bi_tcxo", 221 }, 222 .num_parents = 1, 223 .ops = &clk_alpha_pll_ops, 224 }, 225 }, 226 }; 227 228 static struct clk_alpha_pll gpll5 = { 229 .offset = 0x5000, 230 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 231 .clkr = { 232 .enable_reg = 0x79000, 233 .enable_mask = BIT(5), 234 .hw.init = &(struct clk_init_data){ 235 .name = "gpll5", 236 .parent_data = &(const struct clk_parent_data){ 237 .fw_name = "bi_tcxo", 238 }, 239 .num_parents = 1, 240 .ops = &clk_alpha_pll_ops, 241 }, 242 }, 243 }; 244 245 static struct clk_alpha_pll gpll6 = { 246 .offset = 0x6000, 247 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 248 .clkr = { 249 .enable_reg = 0x79000, 250 .enable_mask = BIT(6), 251 .hw.init = &(struct clk_init_data){ 252 .name = "gpll6", 253 .parent_data = &(const struct clk_parent_data){ 254 .fw_name = "bi_tcxo", 255 }, 256 .num_parents = 1, 257 .ops = &clk_alpha_pll_ops, 258 }, 259 }, 260 }; 261 262 static const struct clk_div_table post_div_table_gpll6_out_main[] = { 263 { 0x1, 2 }, 264 { } 265 }; 266 267 static struct clk_alpha_pll_postdiv gpll6_out_main = { 268 .offset = 0x6000, 269 .post_div_shift = 8, 270 .post_div_table = post_div_table_gpll6_out_main, 271 .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main), 272 .width = 4, 273 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 274 .clkr.hw.init = &(struct clk_init_data){ 275 .name = "gpll6_out_main", 276 .parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw }, 277 .num_parents = 1, 278 .ops = &clk_alpha_pll_postdiv_ro_ops, 279 }, 280 }; 281 282 static struct clk_alpha_pll gpll7 = { 283 .offset = 0x7000, 284 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 285 .clkr = { 286 .enable_reg = 0x79000, 287 .enable_mask = BIT(7), 288 .hw.init = &(struct clk_init_data){ 289 .name = "gpll7", 290 .parent_data = &(const struct clk_parent_data){ 291 .fw_name = "bi_tcxo", 292 }, 293 .num_parents = 1, 294 .ops = &clk_alpha_pll_ops, 295 }, 296 }, 297 }; 298 299 /* 533.2MHz configuration */ 300 static const struct alpha_pll_config gpll8_config = { 301 .l = 0x1B, 302 .alpha = 0x55555555, 303 .alpha_hi = 0xC5, 304 .alpha_en_mask = BIT(24), 305 .vco_val = 0x2 << 20, 306 .vco_mask = GENMASK(21, 20), 307 .main_output_mask = BIT(0), 308 .early_output_mask = BIT(3), 309 .post_div_val = 0x1 << 8, 310 .post_div_mask = GENMASK(11, 8), 311 .config_ctl_val = 0x4001055B, 312 .test_ctl_hi_val = 0x1, 313 }; 314 315 static struct clk_alpha_pll gpll8 = { 316 .offset = 0x8000, 317 .vco_table = default_vco, 318 .num_vco = ARRAY_SIZE(default_vco), 319 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 320 .flags = SUPPORTS_DYNAMIC_UPDATE, 321 .clkr = { 322 .enable_reg = 0x79000, 323 .enable_mask = BIT(8), 324 .hw.init = &(struct clk_init_data){ 325 .name = "gpll8", 326 .parent_data = &(const struct clk_parent_data){ 327 .fw_name = "bi_tcxo", 328 }, 329 .num_parents = 1, 330 .ops = &clk_alpha_pll_ops, 331 }, 332 }, 333 }; 334 335 static const struct clk_div_table post_div_table_gpll8_out_main[] = { 336 { 0x1, 2 }, 337 { } 338 }; 339 340 static struct clk_alpha_pll_postdiv gpll8_out_main = { 341 .offset = 0x8000, 342 .post_div_shift = 8, 343 .post_div_table = post_div_table_gpll8_out_main, 344 .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main), 345 .width = 4, 346 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 347 .clkr.hw.init = &(struct clk_init_data){ 348 .name = "gpll8_out_main", 349 .parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw }, 350 .num_parents = 1, 351 .flags = CLK_SET_RATE_PARENT, 352 .ops = &clk_alpha_pll_postdiv_ro_ops, 353 }, 354 }; 355 356 /* 1152MHz configuration */ 357 static const struct alpha_pll_config gpll9_config = { 358 .l = 0x3C, 359 .alpha = 0x0, 360 .post_div_val = 0x1 << 8, 361 .post_div_mask = GENMASK(9, 8), 362 .main_output_mask = BIT(0), 363 .early_output_mask = BIT(3), 364 .config_ctl_val = 0x00004289, 365 .test_ctl_val = 0x08000000, 366 }; 367 368 static struct clk_alpha_pll gpll9 = { 369 .offset = 0x9000, 370 .vco_table = brammo_vco, 371 .num_vco = ARRAY_SIZE(brammo_vco), 372 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO], 373 .clkr = { 374 .enable_reg = 0x79000, 375 .enable_mask = BIT(9), 376 .hw.init = &(struct clk_init_data){ 377 .name = "gpll9", 378 .parent_data = &(const struct clk_parent_data){ 379 .fw_name = "bi_tcxo", 380 }, 381 .num_parents = 1, 382 .ops = &clk_alpha_pll_ops, 383 }, 384 }, 385 }; 386 387 static const struct clk_div_table post_div_table_gpll9_out_main[] = { 388 { 0x1, 2 }, 389 { } 390 }; 391 392 static struct clk_alpha_pll_postdiv gpll9_out_main = { 393 .offset = 0x9000, 394 .post_div_shift = 8, 395 .post_div_table = post_div_table_gpll9_out_main, 396 .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main), 397 .width = 2, 398 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO], 399 .clkr.hw.init = &(struct clk_init_data){ 400 .name = "gpll9_out_main", 401 .parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw }, 402 .num_parents = 1, 403 .flags = CLK_SET_RATE_PARENT, 404 .ops = &clk_alpha_pll_postdiv_ro_ops, 405 }, 406 }; 407 408 static const struct parent_map gcc_parent_map_0[] = { 409 { P_BI_TCXO, 0 }, 410 { P_GPLL0_OUT_EARLY, 1 }, 411 { P_GPLL0_OUT_AUX2, 2 }, 412 }; 413 414 static const struct clk_parent_data gcc_parents_0[] = { 415 { .fw_name = "bi_tcxo" }, 416 { .hw = &gpll0.clkr.hw }, 417 { .hw = &gpll0_out_aux2.clkr.hw }, 418 }; 419 420 static const struct parent_map gcc_parent_map_1[] = { 421 { P_BI_TCXO, 0 }, 422 { P_GPLL0_OUT_EARLY, 1 }, 423 { P_GPLL0_OUT_AUX2, 2 }, 424 { P_GPLL6_OUT_MAIN, 4 }, 425 }; 426 427 static const struct clk_parent_data gcc_parents_1[] = { 428 { .fw_name = "bi_tcxo" }, 429 { .hw = &gpll0.clkr.hw }, 430 { .hw = &gpll0_out_aux2.clkr.hw }, 431 { .hw = &gpll6_out_main.clkr.hw }, 432 }; 433 434 static const struct parent_map gcc_parent_map_2[] = { 435 { P_BI_TCXO, 0 }, 436 { P_GPLL0_OUT_EARLY, 1 }, 437 { P_GPLL0_OUT_AUX2, 2 }, 438 { P_SLEEP_CLK, 5 }, 439 }; 440 441 static const struct clk_parent_data gcc_parents_2[] = { 442 { .fw_name = "bi_tcxo" }, 443 { .hw = &gpll0.clkr.hw }, 444 { .hw = &gpll0_out_aux2.clkr.hw }, 445 { .fw_name = "sleep_clk" }, 446 }; 447 448 static const struct parent_map gcc_parent_map_3[] = { 449 { P_BI_TCXO, 0 }, 450 { P_GPLL0_OUT_EARLY, 1 }, 451 { P_GPLL9_OUT_EARLY, 2 }, 452 { P_GPLL10_OUT_MAIN, 3 }, 453 { P_GPLL9_OUT_MAIN, 5 }, 454 { P_GPLL3_OUT_MAIN, 6 }, 455 }; 456 457 static const struct clk_parent_data gcc_parents_3[] = { 458 { .fw_name = "bi_tcxo" }, 459 { .hw = &gpll0.clkr.hw }, 460 { .hw = &gpll9.clkr.hw }, 461 { .hw = &gpll10.clkr.hw }, 462 { .hw = &gpll9_out_main.clkr.hw }, 463 { .hw = &gpll3_out_main.clkr.hw }, 464 }; 465 466 static const struct parent_map gcc_parent_map_4[] = { 467 { P_BI_TCXO, 0 }, 468 { P_GPLL0_OUT_EARLY, 1 }, 469 { P_GPLL0_OUT_AUX2, 2 }, 470 { P_GPLL10_OUT_MAIN, 3 }, 471 { P_GPLL4_OUT_MAIN, 5 }, 472 { P_GPLL3_OUT_EARLY, 6 }, 473 }; 474 475 static const struct clk_parent_data gcc_parents_4[] = { 476 { .fw_name = "bi_tcxo" }, 477 { .hw = &gpll0.clkr.hw }, 478 { .hw = &gpll0_out_aux2.clkr.hw }, 479 { .hw = &gpll10.clkr.hw }, 480 { .hw = &gpll4.clkr.hw }, 481 { .hw = &gpll3.clkr.hw }, 482 }; 483 484 static const struct parent_map gcc_parent_map_5[] = { 485 { P_BI_TCXO, 0 }, 486 { P_GPLL0_OUT_EARLY, 1 }, 487 { P_GPLL0_OUT_AUX2, 2 }, 488 { P_GPLL4_OUT_MAIN, 5 }, 489 { P_GPLL3_OUT_MAIN, 6 }, 490 }; 491 492 static const struct clk_parent_data gcc_parents_5[] = { 493 { .fw_name = "bi_tcxo" }, 494 { .hw = &gpll0.clkr.hw }, 495 { .hw = &gpll0_out_aux2.clkr.hw }, 496 { .hw = &gpll4.clkr.hw }, 497 { .hw = &gpll3_out_main.clkr.hw }, 498 }; 499 500 static const struct parent_map gcc_parent_map_6[] = { 501 { P_BI_TCXO, 0 }, 502 { P_GPLL0_OUT_EARLY, 1 }, 503 { P_GPLL8_OUT_EARLY, 2 }, 504 { P_GPLL10_OUT_MAIN, 3 }, 505 { P_GPLL8_OUT_MAIN, 4 }, 506 { P_GPLL9_OUT_MAIN, 5 }, 507 { P_GPLL3_OUT_EARLY, 6 }, 508 }; 509 510 static const struct clk_parent_data gcc_parents_6[] = { 511 { .fw_name = "bi_tcxo" }, 512 { .hw = &gpll0.clkr.hw }, 513 { .hw = &gpll8.clkr.hw }, 514 { .hw = &gpll10.clkr.hw }, 515 { .hw = &gpll8_out_main.clkr.hw }, 516 { .hw = &gpll9_out_main.clkr.hw }, 517 { .hw = &gpll3.clkr.hw }, 518 }; 519 520 static const struct parent_map gcc_parent_map_7[] = { 521 { P_BI_TCXO, 0 }, 522 { P_GPLL0_OUT_EARLY, 1 }, 523 { P_GPLL8_OUT_EARLY, 2 }, 524 { P_GPLL10_OUT_MAIN, 3 }, 525 { P_GPLL8_OUT_MAIN, 4 }, 526 { P_GPLL9_OUT_MAIN, 5 }, 527 { P_GPLL3_OUT_MAIN, 6 }, 528 }; 529 530 static const struct clk_parent_data gcc_parents_7[] = { 531 { .fw_name = "bi_tcxo" }, 532 { .hw = &gpll0.clkr.hw }, 533 { .hw = &gpll8.clkr.hw }, 534 { .hw = &gpll10.clkr.hw }, 535 { .hw = &gpll8_out_main.clkr.hw }, 536 { .hw = &gpll9_out_main.clkr.hw }, 537 { .hw = &gpll3_out_main.clkr.hw }, 538 }; 539 540 static const struct parent_map gcc_parent_map_8[] = { 541 { P_BI_TCXO, 0 }, 542 { P_GPLL0_OUT_EARLY, 1 }, 543 { P_GPLL8_OUT_EARLY, 2 }, 544 { P_GPLL10_OUT_MAIN, 3 }, 545 { P_GPLL6_OUT_MAIN, 4 }, 546 { P_GPLL9_OUT_MAIN, 5 }, 547 { P_GPLL3_OUT_EARLY, 6 }, 548 }; 549 550 static const struct clk_parent_data gcc_parents_8[] = { 551 { .fw_name = "bi_tcxo" }, 552 { .hw = &gpll0.clkr.hw }, 553 { .hw = &gpll8.clkr.hw }, 554 { .hw = &gpll10.clkr.hw }, 555 { .hw = &gpll6_out_main.clkr.hw }, 556 { .hw = &gpll9_out_main.clkr.hw }, 557 { .hw = &gpll3.clkr.hw }, 558 }; 559 560 static const struct parent_map gcc_parent_map_9[] = { 561 { P_BI_TCXO, 0 }, 562 { P_GPLL0_OUT_EARLY, 1 }, 563 { P_GPLL0_OUT_AUX2, 2 }, 564 { P_GPLL10_OUT_MAIN, 3 }, 565 { P_GPLL8_OUT_MAIN, 4 }, 566 { P_GPLL9_OUT_MAIN, 5 }, 567 { P_GPLL3_OUT_EARLY, 6 }, 568 }; 569 570 static const struct clk_parent_data gcc_parents_9[] = { 571 { .fw_name = "bi_tcxo" }, 572 { .hw = &gpll0.clkr.hw }, 573 { .hw = &gpll0_out_aux2.clkr.hw }, 574 { .hw = &gpll10.clkr.hw }, 575 { .hw = &gpll8_out_main.clkr.hw }, 576 { .hw = &gpll9_out_main.clkr.hw }, 577 { .hw = &gpll3.clkr.hw }, 578 }; 579 580 static const struct parent_map gcc_parent_map_10[] = { 581 { P_BI_TCXO, 0 }, 582 { P_GPLL0_OUT_EARLY, 1 }, 583 { P_GPLL8_OUT_EARLY, 2 }, 584 { P_GPLL10_OUT_MAIN, 3 }, 585 { P_GPLL6_OUT_EARLY, 5 }, 586 { P_GPLL3_OUT_MAIN, 6 }, 587 }; 588 589 static const struct clk_parent_data gcc_parents_10[] = { 590 { .fw_name = "bi_tcxo" }, 591 { .hw = &gpll0.clkr.hw }, 592 { .hw = &gpll8.clkr.hw }, 593 { .hw = &gpll10.clkr.hw }, 594 { .hw = &gpll6.clkr.hw }, 595 { .hw = &gpll3_out_main.clkr.hw }, 596 }; 597 598 static const struct parent_map gcc_parent_map_12[] = { 599 { P_BI_TCXO, 0 }, 600 { P_GPLL0_OUT_EARLY, 1 }, 601 { P_GPLL0_OUT_AUX2, 2 }, 602 { P_GPLL7_OUT_MAIN, 3 }, 603 { P_GPLL4_OUT_MAIN, 5 }, 604 }; 605 606 static const struct clk_parent_data gcc_parents_12[] = { 607 { .fw_name = "bi_tcxo" }, 608 { .hw = &gpll0.clkr.hw }, 609 { .hw = &gpll0_out_aux2.clkr.hw }, 610 { .hw = &gpll7.clkr.hw }, 611 { .hw = &gpll4.clkr.hw }, 612 }; 613 614 static const struct parent_map gcc_parent_map_13[] = { 615 { P_BI_TCXO, 0 }, 616 { P_SLEEP_CLK, 5 }, 617 }; 618 619 static const struct clk_parent_data gcc_parents_13[] = { 620 { .fw_name = "bi_tcxo" }, 621 { .fw_name = "sleep_clk" }, 622 }; 623 624 static const struct parent_map gcc_parent_map_14[] = { 625 { P_BI_TCXO, 0 }, 626 { P_GPLL11_OUT_MAIN, 1 }, 627 { P_GPLL11_OUT_AUX, 2 }, 628 { P_GPLL11_OUT_AUX2, 3 }, 629 }; 630 631 static const struct clk_parent_data gcc_parents_14[] = { 632 { .fw_name = "bi_tcxo" }, 633 { .hw = &gpll11.clkr.hw }, 634 { .hw = &gpll11.clkr.hw }, 635 { .hw = &gpll11.clkr.hw }, 636 }; 637 638 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 639 F(19200000, P_BI_TCXO, 1, 0, 0), 640 { } 641 }; 642 643 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 644 .cmd_rcgr = 0x1a034, 645 .mnd_width = 0, 646 .hid_width = 5, 647 .parent_map = gcc_parent_map_0, 648 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 649 .clkr.hw.init = &(struct clk_init_data){ 650 .name = "gcc_usb30_prim_mock_utmi_clk_src", 651 .parent_data = gcc_parents_0, 652 .num_parents = ARRAY_SIZE(gcc_parents_0), 653 .ops = &clk_rcg2_shared_ops, 654 }, 655 }; 656 657 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv = { 658 .reg = 0x1a04c, 659 .shift = 0, 660 .width = 2, 661 .clkr.hw.init = &(struct clk_init_data) { 662 .name = "gcc_usb30_prim_mock_utmi_postdiv", 663 .parent_hws = (const struct clk_hw *[]) 664 { &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw }, 665 .num_parents = 1, 666 .flags = CLK_SET_RATE_PARENT, 667 .ops = &clk_regmap_div_ro_ops, 668 }, 669 }; 670 671 static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = { 672 F(19200000, P_BI_TCXO, 1, 0, 0), 673 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 674 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 675 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 676 { } 677 }; 678 679 static struct clk_rcg2 gcc_camss_axi_clk_src = { 680 .cmd_rcgr = 0x5802c, 681 .mnd_width = 0, 682 .hid_width = 5, 683 .parent_map = gcc_parent_map_4, 684 .freq_tbl = ftbl_gcc_camss_axi_clk_src, 685 .clkr.hw.init = &(struct clk_init_data){ 686 .name = "gcc_camss_axi_clk_src", 687 .parent_data = gcc_parents_4, 688 .num_parents = ARRAY_SIZE(gcc_parents_4), 689 .ops = &clk_rcg2_shared_ops, 690 }, 691 }; 692 693 static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = { 694 F(19200000, P_BI_TCXO, 1, 0, 0), 695 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), 696 { } 697 }; 698 699 static struct clk_rcg2 gcc_camss_cci_clk_src = { 700 .cmd_rcgr = 0x56000, 701 .mnd_width = 0, 702 .hid_width = 5, 703 .parent_map = gcc_parent_map_9, 704 .freq_tbl = ftbl_gcc_camss_cci_clk_src, 705 .clkr.hw.init = &(struct clk_init_data){ 706 .name = "gcc_camss_cci_clk_src", 707 .parent_data = gcc_parents_9, 708 .num_parents = ARRAY_SIZE(gcc_parents_9), 709 .ops = &clk_rcg2_shared_ops, 710 }, 711 }; 712 713 static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = { 714 F(19200000, P_BI_TCXO, 1, 0, 0), 715 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 716 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 717 F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0), 718 { } 719 }; 720 721 static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = { 722 .cmd_rcgr = 0x45000, 723 .mnd_width = 0, 724 .hid_width = 5, 725 .parent_map = gcc_parent_map_5, 726 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 727 .clkr.hw.init = &(struct clk_init_data){ 728 .name = "gcc_camss_csi0phytimer_clk_src", 729 .parent_data = gcc_parents_5, 730 .num_parents = ARRAY_SIZE(gcc_parents_5), 731 .ops = &clk_rcg2_shared_ops, 732 }, 733 }; 734 735 static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = { 736 .cmd_rcgr = 0x4501c, 737 .mnd_width = 0, 738 .hid_width = 5, 739 .parent_map = gcc_parent_map_5, 740 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, 741 .clkr.hw.init = &(struct clk_init_data){ 742 .name = "gcc_camss_csi1phytimer_clk_src", 743 .parent_data = gcc_parents_5, 744 .num_parents = ARRAY_SIZE(gcc_parents_5), 745 .ops = &clk_rcg2_shared_ops, 746 }, 747 }; 748 749 static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = { 750 F(19200000, P_BI_TCXO, 1, 0, 0), 751 F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24), 752 F(64000000, P_GPLL9_OUT_EARLY, 9, 1, 2), 753 { } 754 }; 755 756 static struct clk_rcg2 gcc_camss_mclk0_clk_src = { 757 .cmd_rcgr = 0x51000, 758 .mnd_width = 8, 759 .hid_width = 5, 760 .parent_map = gcc_parent_map_3, 761 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 762 .clkr.hw.init = &(struct clk_init_data){ 763 .name = "gcc_camss_mclk0_clk_src", 764 .parent_data = gcc_parents_3, 765 .num_parents = ARRAY_SIZE(gcc_parents_3), 766 .flags = CLK_OPS_PARENT_ENABLE, 767 .ops = &clk_rcg2_shared_ops, 768 }, 769 }; 770 771 static struct clk_rcg2 gcc_camss_mclk1_clk_src = { 772 .cmd_rcgr = 0x5101c, 773 .mnd_width = 8, 774 .hid_width = 5, 775 .parent_map = gcc_parent_map_3, 776 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 777 .clkr.hw.init = &(struct clk_init_data){ 778 .name = "gcc_camss_mclk1_clk_src", 779 .parent_data = gcc_parents_3, 780 .num_parents = ARRAY_SIZE(gcc_parents_3), 781 .flags = CLK_OPS_PARENT_ENABLE, 782 .ops = &clk_rcg2_shared_ops, 783 }, 784 }; 785 786 static struct clk_rcg2 gcc_camss_mclk2_clk_src = { 787 .cmd_rcgr = 0x51038, 788 .mnd_width = 8, 789 .hid_width = 5, 790 .parent_map = gcc_parent_map_3, 791 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 792 .clkr.hw.init = &(struct clk_init_data){ 793 .name = "gcc_camss_mclk2_clk_src", 794 .parent_data = gcc_parents_3, 795 .num_parents = ARRAY_SIZE(gcc_parents_3), 796 .flags = CLK_OPS_PARENT_ENABLE, 797 .ops = &clk_rcg2_shared_ops, 798 }, 799 }; 800 801 static struct clk_rcg2 gcc_camss_mclk3_clk_src = { 802 .cmd_rcgr = 0x51054, 803 .mnd_width = 8, 804 .hid_width = 5, 805 .parent_map = gcc_parent_map_3, 806 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, 807 .clkr.hw.init = &(struct clk_init_data){ 808 .name = "gcc_camss_mclk3_clk_src", 809 .parent_data = gcc_parents_3, 810 .num_parents = ARRAY_SIZE(gcc_parents_3), 811 .flags = CLK_OPS_PARENT_ENABLE, 812 .ops = &clk_rcg2_shared_ops, 813 }, 814 }; 815 816 static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = { 817 F(19200000, P_BI_TCXO, 1, 0, 0), 818 F(171428571, P_GPLL0_OUT_EARLY, 3.5, 0, 0), 819 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 820 { } 821 }; 822 823 static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = { 824 .cmd_rcgr = 0x55024, 825 .mnd_width = 0, 826 .hid_width = 5, 827 .parent_map = gcc_parent_map_6, 828 .freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src, 829 .clkr.hw.init = &(struct clk_init_data){ 830 .name = "gcc_camss_ope_ahb_clk_src", 831 .parent_data = gcc_parents_6, 832 .num_parents = ARRAY_SIZE(gcc_parents_6), 833 .ops = &clk_rcg2_shared_ops, 834 }, 835 }; 836 837 static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = { 838 F(19200000, P_BI_TCXO, 1, 0, 0), 839 F(200000000, P_GPLL8_OUT_MAIN, 2, 0, 0), 840 F(266600000, P_GPLL8_OUT_MAIN, 1, 0, 0), 841 F(465000000, P_GPLL8_OUT_MAIN, 1, 0, 0), 842 F(580000000, P_GPLL8_OUT_EARLY, 1, 0, 0), 843 { } 844 }; 845 846 static struct clk_rcg2 gcc_camss_ope_clk_src = { 847 .cmd_rcgr = 0x55004, 848 .mnd_width = 0, 849 .hid_width = 5, 850 .parent_map = gcc_parent_map_6, 851 .freq_tbl = ftbl_gcc_camss_ope_clk_src, 852 .clkr.hw.init = &(struct clk_init_data){ 853 .name = "gcc_camss_ope_clk_src", 854 .parent_data = gcc_parents_6, 855 .num_parents = ARRAY_SIZE(gcc_parents_6), 856 .flags = CLK_SET_RATE_PARENT, 857 .ops = &clk_rcg2_shared_ops, 858 }, 859 }; 860 861 static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = { 862 F(19200000, P_BI_TCXO, 1, 0, 0), 863 F(128000000, P_GPLL10_OUT_MAIN, 9, 0, 0), 864 F(135529412, P_GPLL10_OUT_MAIN, 8.5, 0, 0), 865 F(144000000, P_GPLL10_OUT_MAIN, 8, 0, 0), 866 F(153600000, P_GPLL10_OUT_MAIN, 7.5, 0, 0), 867 F(164571429, P_GPLL10_OUT_MAIN, 7, 0, 0), 868 F(177230769, P_GPLL10_OUT_MAIN, 6.5, 0, 0), 869 F(192000000, P_GPLL10_OUT_MAIN, 6, 0, 0), 870 F(209454545, P_GPLL10_OUT_MAIN, 5.5, 0, 0), 871 F(230400000, P_GPLL10_OUT_MAIN, 5, 0, 0), 872 F(256000000, P_GPLL10_OUT_MAIN, 4.5, 0, 0), 873 F(288000000, P_GPLL10_OUT_MAIN, 4, 0, 0), 874 F(329142857, P_GPLL10_OUT_MAIN, 3.5, 0, 0), 875 F(384000000, P_GPLL10_OUT_MAIN, 3, 0, 0), 876 F(460800000, P_GPLL10_OUT_MAIN, 2.5, 0, 0), 877 F(576000000, P_GPLL10_OUT_MAIN, 2, 0, 0), 878 { } 879 }; 880 881 static struct clk_rcg2 gcc_camss_tfe_0_clk_src = { 882 .cmd_rcgr = 0x52004, 883 .mnd_width = 8, 884 .hid_width = 5, 885 .parent_map = gcc_parent_map_7, 886 .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 887 .clkr.hw.init = &(struct clk_init_data){ 888 .name = "gcc_camss_tfe_0_clk_src", 889 .parent_data = gcc_parents_7, 890 .num_parents = ARRAY_SIZE(gcc_parents_7), 891 .ops = &clk_rcg2_shared_ops, 892 }, 893 }; 894 895 static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = { 896 F(19200000, P_BI_TCXO, 1, 0, 0), 897 F(120000000, P_GPLL0_OUT_EARLY, 5, 0, 0), 898 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 899 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 900 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 901 F(426400000, P_GPLL3_OUT_EARLY, 2.5, 0, 0), 902 { } 903 }; 904 905 static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = { 906 .cmd_rcgr = 0x52094, 907 .mnd_width = 0, 908 .hid_width = 5, 909 .parent_map = gcc_parent_map_8, 910 .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 911 .clkr.hw.init = &(struct clk_init_data){ 912 .name = "gcc_camss_tfe_0_csid_clk_src", 913 .parent_data = gcc_parents_8, 914 .num_parents = ARRAY_SIZE(gcc_parents_8), 915 .ops = &clk_rcg2_shared_ops, 916 }, 917 }; 918 919 static struct clk_rcg2 gcc_camss_tfe_1_clk_src = { 920 .cmd_rcgr = 0x52024, 921 .mnd_width = 8, 922 .hid_width = 5, 923 .parent_map = gcc_parent_map_7, 924 .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, 925 .clkr.hw.init = &(struct clk_init_data){ 926 .name = "gcc_camss_tfe_1_clk_src", 927 .parent_data = gcc_parents_7, 928 .num_parents = ARRAY_SIZE(gcc_parents_7), 929 .ops = &clk_rcg2_shared_ops, 930 }, 931 }; 932 933 static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = { 934 .cmd_rcgr = 0x520b4, 935 .mnd_width = 0, 936 .hid_width = 5, 937 .parent_map = gcc_parent_map_8, 938 .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, 939 .clkr.hw.init = &(struct clk_init_data){ 940 .name = "gcc_camss_tfe_1_csid_clk_src", 941 .parent_data = gcc_parents_8, 942 .num_parents = ARRAY_SIZE(gcc_parents_8), 943 .ops = &clk_rcg2_shared_ops, 944 }, 945 }; 946 947 static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = { 948 F(19200000, P_BI_TCXO, 1, 0, 0), 949 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 950 F(341333333, P_GPLL6_OUT_EARLY, 1, 4, 9), 951 F(384000000, P_GPLL6_OUT_EARLY, 2, 0, 0), 952 { } 953 }; 954 955 static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = { 956 .cmd_rcgr = 0x52064, 957 .mnd_width = 16, 958 .hid_width = 5, 959 .parent_map = gcc_parent_map_10, 960 .freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src, 961 .clkr.hw.init = &(struct clk_init_data){ 962 .name = "gcc_camss_tfe_cphy_rx_clk_src", 963 .parent_data = gcc_parents_10, 964 .num_parents = ARRAY_SIZE(gcc_parents_10), 965 .flags = CLK_OPS_PARENT_ENABLE, 966 .ops = &clk_rcg2_shared_ops, 967 }, 968 }; 969 970 static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = { 971 F(19200000, P_BI_TCXO, 1, 0, 0), 972 F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0), 973 F(80000000, P_GPLL0_OUT_EARLY, 7.5, 0, 0), 974 { } 975 }; 976 977 static struct clk_rcg2 gcc_camss_top_ahb_clk_src = { 978 .cmd_rcgr = 0x58010, 979 .mnd_width = 0, 980 .hid_width = 5, 981 .parent_map = gcc_parent_map_4, 982 .freq_tbl = ftbl_gcc_camss_top_ahb_clk_src, 983 .clkr.hw.init = &(struct clk_init_data){ 984 .name = "gcc_camss_top_ahb_clk_src", 985 .parent_data = gcc_parents_4, 986 .num_parents = ARRAY_SIZE(gcc_parents_4), 987 .ops = &clk_rcg2_shared_ops, 988 }, 989 }; 990 991 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 992 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 993 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 994 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 995 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0), 996 { } 997 }; 998 999 static struct clk_rcg2 gcc_gp1_clk_src = { 1000 .cmd_rcgr = 0x4d004, 1001 .mnd_width = 8, 1002 .hid_width = 5, 1003 .parent_map = gcc_parent_map_2, 1004 .freq_tbl = ftbl_gcc_gp1_clk_src, 1005 .clkr.hw.init = &(struct clk_init_data){ 1006 .name = "gcc_gp1_clk_src", 1007 .parent_data = gcc_parents_2, 1008 .num_parents = ARRAY_SIZE(gcc_parents_2), 1009 .ops = &clk_rcg2_shared_ops, 1010 }, 1011 }; 1012 1013 static struct clk_rcg2 gcc_gp2_clk_src = { 1014 .cmd_rcgr = 0x4e004, 1015 .mnd_width = 8, 1016 .hid_width = 5, 1017 .parent_map = gcc_parent_map_2, 1018 .freq_tbl = ftbl_gcc_gp1_clk_src, 1019 .clkr.hw.init = &(struct clk_init_data){ 1020 .name = "gcc_gp2_clk_src", 1021 .parent_data = gcc_parents_2, 1022 .num_parents = ARRAY_SIZE(gcc_parents_2), 1023 .ops = &clk_rcg2_shared_ops, 1024 }, 1025 }; 1026 1027 static struct clk_rcg2 gcc_gp3_clk_src = { 1028 .cmd_rcgr = 0x4f004, 1029 .mnd_width = 8, 1030 .hid_width = 5, 1031 .parent_map = gcc_parent_map_2, 1032 .freq_tbl = ftbl_gcc_gp1_clk_src, 1033 .clkr.hw.init = &(struct clk_init_data){ 1034 .name = "gcc_gp3_clk_src", 1035 .parent_data = gcc_parents_2, 1036 .num_parents = ARRAY_SIZE(gcc_parents_2), 1037 .ops = &clk_rcg2_shared_ops, 1038 }, 1039 }; 1040 1041 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 1042 F(19200000, P_BI_TCXO, 1, 0, 0), 1043 F(60000000, P_GPLL0_OUT_AUX2, 5, 0, 0), 1044 { } 1045 }; 1046 1047 static struct clk_rcg2 gcc_pdm2_clk_src = { 1048 .cmd_rcgr = 0x20010, 1049 .mnd_width = 0, 1050 .hid_width = 5, 1051 .parent_map = gcc_parent_map_0, 1052 .freq_tbl = ftbl_gcc_pdm2_clk_src, 1053 .clkr.hw.init = &(struct clk_init_data){ 1054 .name = "gcc_pdm2_clk_src", 1055 .parent_data = gcc_parents_0, 1056 .num_parents = ARRAY_SIZE(gcc_parents_0), 1057 .ops = &clk_rcg2_shared_ops, 1058 }, 1059 }; 1060 1061 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 1062 F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625), 1063 F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625), 1064 F(19200000, P_BI_TCXO, 1, 0, 0), 1065 F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625), 1066 F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75), 1067 F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25), 1068 F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75), 1069 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1070 F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15), 1071 F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25), 1072 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1073 F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375), 1074 F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75), 1075 F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625), 1076 F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0), 1077 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0), 1078 { } 1079 }; 1080 1081 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 1082 .name = "gcc_qupv3_wrap0_s0_clk_src", 1083 .parent_data = gcc_parents_1, 1084 .num_parents = ARRAY_SIZE(gcc_parents_1), 1085 .ops = &clk_rcg2_shared_no_init_park_ops, 1086 }; 1087 1088 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 1089 .cmd_rcgr = 0x1f148, 1090 .mnd_width = 16, 1091 .hid_width = 5, 1092 .parent_map = gcc_parent_map_1, 1093 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1094 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 1095 }; 1096 1097 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 1098 .name = "gcc_qupv3_wrap0_s1_clk_src", 1099 .parent_data = gcc_parents_1, 1100 .num_parents = ARRAY_SIZE(gcc_parents_1), 1101 .ops = &clk_rcg2_shared_no_init_park_ops, 1102 }; 1103 1104 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 1105 .cmd_rcgr = 0x1f278, 1106 .mnd_width = 16, 1107 .hid_width = 5, 1108 .parent_map = gcc_parent_map_1, 1109 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1110 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 1111 }; 1112 1113 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 1114 .name = "gcc_qupv3_wrap0_s2_clk_src", 1115 .parent_data = gcc_parents_1, 1116 .num_parents = ARRAY_SIZE(gcc_parents_1), 1117 .ops = &clk_rcg2_shared_no_init_park_ops, 1118 }; 1119 1120 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 1121 .cmd_rcgr = 0x1f3a8, 1122 .mnd_width = 16, 1123 .hid_width = 5, 1124 .parent_map = gcc_parent_map_1, 1125 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1126 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 1127 }; 1128 1129 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 1130 .name = "gcc_qupv3_wrap0_s3_clk_src", 1131 .parent_data = gcc_parents_1, 1132 .num_parents = ARRAY_SIZE(gcc_parents_1), 1133 .ops = &clk_rcg2_shared_no_init_park_ops, 1134 }; 1135 1136 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 1137 .cmd_rcgr = 0x1f4d8, 1138 .mnd_width = 16, 1139 .hid_width = 5, 1140 .parent_map = gcc_parent_map_1, 1141 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1142 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 1143 }; 1144 1145 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 1146 .name = "gcc_qupv3_wrap0_s4_clk_src", 1147 .parent_data = gcc_parents_1, 1148 .num_parents = ARRAY_SIZE(gcc_parents_1), 1149 .ops = &clk_rcg2_shared_no_init_park_ops, 1150 }; 1151 1152 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 1153 .cmd_rcgr = 0x1f608, 1154 .mnd_width = 16, 1155 .hid_width = 5, 1156 .parent_map = gcc_parent_map_1, 1157 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1158 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 1159 }; 1160 1161 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 1162 .name = "gcc_qupv3_wrap0_s5_clk_src", 1163 .parent_data = gcc_parents_1, 1164 .num_parents = ARRAY_SIZE(gcc_parents_1), 1165 .ops = &clk_rcg2_shared_no_init_park_ops, 1166 }; 1167 1168 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 1169 .cmd_rcgr = 0x1f738, 1170 .mnd_width = 16, 1171 .hid_width = 5, 1172 .parent_map = gcc_parent_map_1, 1173 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1174 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 1175 }; 1176 1177 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 1178 F(144000, P_BI_TCXO, 16, 3, 25), 1179 F(400000, P_BI_TCXO, 12, 1, 4), 1180 F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3), 1181 F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2), 1182 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1183 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1184 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 1185 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 1186 { } 1187 }; 1188 1189 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 1190 .cmd_rcgr = 0x38028, 1191 .mnd_width = 8, 1192 .hid_width = 5, 1193 .parent_map = gcc_parent_map_1, 1194 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 1195 .clkr.hw.init = &(struct clk_init_data){ 1196 .name = "gcc_sdcc1_apps_clk_src", 1197 .parent_data = gcc_parents_1, 1198 .num_parents = ARRAY_SIZE(gcc_parents_1), 1199 .ops = &clk_rcg2_floor_ops, 1200 }, 1201 }; 1202 1203 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 1204 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), 1205 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1206 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0), 1207 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1208 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0), 1209 { } 1210 }; 1211 1212 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 1213 .cmd_rcgr = 0x38010, 1214 .mnd_width = 0, 1215 .hid_width = 5, 1216 .parent_map = gcc_parent_map_0, 1217 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 1218 .clkr.hw.init = &(struct clk_init_data){ 1219 .name = "gcc_sdcc1_ice_core_clk_src", 1220 .parent_data = gcc_parents_0, 1221 .num_parents = ARRAY_SIZE(gcc_parents_0), 1222 .ops = &clk_rcg2_shared_ops, 1223 }, 1224 }; 1225 1226 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1227 F(400000, P_BI_TCXO, 12, 1, 4), 1228 F(19200000, P_BI_TCXO, 1, 0, 0), 1229 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), 1230 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), 1231 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), 1232 F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0), 1233 { } 1234 }; 1235 1236 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1237 .cmd_rcgr = 0x1e00c, 1238 .mnd_width = 8, 1239 .hid_width = 5, 1240 .parent_map = gcc_parent_map_12, 1241 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1242 .clkr.hw.init = &(struct clk_init_data){ 1243 .name = "gcc_sdcc2_apps_clk_src", 1244 .parent_data = gcc_parents_12, 1245 .num_parents = ARRAY_SIZE(gcc_parents_12), 1246 .ops = &clk_rcg2_floor_ops, 1247 .flags = CLK_OPS_PARENT_ENABLE, 1248 }, 1249 }; 1250 1251 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1252 F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0), 1253 F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0), 1254 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), 1255 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), 1256 { } 1257 }; 1258 1259 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1260 .cmd_rcgr = 0x1a01c, 1261 .mnd_width = 8, 1262 .hid_width = 5, 1263 .parent_map = gcc_parent_map_0, 1264 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1265 .clkr.hw.init = &(struct clk_init_data){ 1266 .name = "gcc_usb30_prim_master_clk_src", 1267 .parent_data = gcc_parents_0, 1268 .num_parents = ARRAY_SIZE(gcc_parents_0), 1269 .ops = &clk_rcg2_shared_ops, 1270 }, 1271 }; 1272 1273 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1274 .cmd_rcgr = 0x1a060, 1275 .mnd_width = 0, 1276 .hid_width = 5, 1277 .parent_map = gcc_parent_map_13, 1278 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1279 .clkr.hw.init = &(struct clk_init_data){ 1280 .name = "gcc_usb3_prim_phy_aux_clk_src", 1281 .parent_data = gcc_parents_13, 1282 .num_parents = ARRAY_SIZE(gcc_parents_13), 1283 .ops = &clk_rcg2_shared_ops, 1284 }, 1285 }; 1286 1287 static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = { 1288 F(133333333, P_GPLL11_OUT_MAIN, 4.5, 0, 0), 1289 F(240000000, P_GPLL11_OUT_MAIN, 2.5, 0, 0), 1290 F(300000000, P_GPLL11_OUT_MAIN, 2, 0, 0), 1291 F(384000000, P_GPLL11_OUT_MAIN, 2, 0, 0), 1292 { } 1293 }; 1294 1295 static struct clk_rcg2 gcc_video_venus_clk_src = { 1296 .cmd_rcgr = 0x58060, 1297 .mnd_width = 0, 1298 .hid_width = 5, 1299 .parent_map = gcc_parent_map_14, 1300 .freq_tbl = ftbl_gcc_video_venus_clk_src, 1301 .clkr.hw.init = &(struct clk_init_data){ 1302 .name = "gcc_video_venus_clk_src", 1303 .parent_data = gcc_parents_14, 1304 .num_parents = ARRAY_SIZE(gcc_parents_14), 1305 .flags = CLK_SET_RATE_PARENT, 1306 .ops = &clk_rcg2_shared_ops, 1307 }, 1308 }; 1309 1310 static struct clk_branch gcc_ahb2phy_csi_clk = { 1311 .halt_reg = 0x1d004, 1312 .halt_check = BRANCH_HALT_DELAY, 1313 .hwcg_reg = 0x1d004, 1314 .hwcg_bit = 1, 1315 .clkr = { 1316 .enable_reg = 0x1d004, 1317 .enable_mask = BIT(0), 1318 .hw.init = &(struct clk_init_data){ 1319 .name = "gcc_ahb2phy_csi_clk", 1320 .ops = &clk_branch2_ops, 1321 }, 1322 }, 1323 }; 1324 1325 static struct clk_branch gcc_ahb2phy_usb_clk = { 1326 .halt_reg = 0x1d008, 1327 .halt_check = BRANCH_HALT, 1328 .hwcg_reg = 0x1d008, 1329 .hwcg_bit = 1, 1330 .clkr = { 1331 .enable_reg = 0x1d008, 1332 .enable_mask = BIT(0), 1333 .hw.init = &(struct clk_init_data){ 1334 .name = "gcc_ahb2phy_usb_clk", 1335 .ops = &clk_branch2_ops, 1336 }, 1337 }, 1338 }; 1339 1340 static struct clk_branch gcc_bimc_gpu_axi_clk = { 1341 .halt_reg = 0x71154, 1342 .halt_check = BRANCH_HALT_DELAY, 1343 .hwcg_reg = 0x71154, 1344 .hwcg_bit = 1, 1345 .clkr = { 1346 .enable_reg = 0x71154, 1347 .enable_mask = BIT(0), 1348 .hw.init = &(struct clk_init_data){ 1349 .name = "gcc_bimc_gpu_axi_clk", 1350 .ops = &clk_branch2_ops, 1351 }, 1352 }, 1353 }; 1354 1355 static struct clk_branch gcc_boot_rom_ahb_clk = { 1356 .halt_reg = 0x23004, 1357 .halt_check = BRANCH_HALT_VOTED, 1358 .hwcg_reg = 0x23004, 1359 .hwcg_bit = 1, 1360 .clkr = { 1361 .enable_reg = 0x79004, 1362 .enable_mask = BIT(10), 1363 .hw.init = &(struct clk_init_data){ 1364 .name = "gcc_boot_rom_ahb_clk", 1365 .ops = &clk_branch2_ops, 1366 }, 1367 }, 1368 }; 1369 1370 static struct clk_branch gcc_cam_throttle_nrt_clk = { 1371 .halt_reg = 0x17070, 1372 .halt_check = BRANCH_HALT_VOTED, 1373 .hwcg_reg = 0x17070, 1374 .hwcg_bit = 1, 1375 .clkr = { 1376 .enable_reg = 0x79004, 1377 .enable_mask = BIT(27), 1378 .hw.init = &(struct clk_init_data){ 1379 .name = "gcc_cam_throttle_nrt_clk", 1380 .ops = &clk_branch2_ops, 1381 }, 1382 }, 1383 }; 1384 1385 static struct clk_branch gcc_cam_throttle_rt_clk = { 1386 .halt_reg = 0x1706c, 1387 .halt_check = BRANCH_HALT_VOTED, 1388 .hwcg_reg = 0x1706c, 1389 .hwcg_bit = 1, 1390 .clkr = { 1391 .enable_reg = 0x79004, 1392 .enable_mask = BIT(26), 1393 .hw.init = &(struct clk_init_data){ 1394 .name = "gcc_cam_throttle_rt_clk", 1395 .ops = &clk_branch2_ops, 1396 }, 1397 }, 1398 }; 1399 1400 static struct clk_branch gcc_camss_axi_clk = { 1401 .halt_reg = 0x58044, 1402 .halt_check = BRANCH_HALT, 1403 .clkr = { 1404 .enable_reg = 0x58044, 1405 .enable_mask = BIT(0), 1406 .hw.init = &(struct clk_init_data){ 1407 .name = "gcc_camss_axi_clk", 1408 .parent_hws = (const struct clk_hw *[]) 1409 { &gcc_camss_axi_clk_src.clkr.hw }, 1410 .num_parents = 1, 1411 .flags = CLK_SET_RATE_PARENT, 1412 .ops = &clk_branch2_ops, 1413 }, 1414 }, 1415 }; 1416 1417 static struct clk_branch gcc_camss_camnoc_atb_clk = { 1418 .halt_reg = 0x5804c, 1419 .halt_check = BRANCH_HALT_DELAY, 1420 .hwcg_reg = 0x5804c, 1421 .hwcg_bit = 1, 1422 .clkr = { 1423 .enable_reg = 0x5804c, 1424 .enable_mask = BIT(0), 1425 .hw.init = &(struct clk_init_data){ 1426 .name = "gcc_camss_camnoc_atb_clk", 1427 .ops = &clk_branch2_ops, 1428 }, 1429 }, 1430 }; 1431 1432 static struct clk_branch gcc_camss_camnoc_nts_xo_clk = { 1433 .halt_reg = 0x58050, 1434 .halt_check = BRANCH_HALT_DELAY, 1435 .hwcg_reg = 0x58050, 1436 .hwcg_bit = 1, 1437 .clkr = { 1438 .enable_reg = 0x58050, 1439 .enable_mask = BIT(0), 1440 .hw.init = &(struct clk_init_data){ 1441 .name = "gcc_camss_camnoc_nts_xo_clk", 1442 .ops = &clk_branch2_ops, 1443 }, 1444 }, 1445 }; 1446 1447 static struct clk_branch gcc_camss_cci_0_clk = { 1448 .halt_reg = 0x56018, 1449 .halt_check = BRANCH_HALT, 1450 .clkr = { 1451 .enable_reg = 0x56018, 1452 .enable_mask = BIT(0), 1453 .hw.init = &(struct clk_init_data){ 1454 .name = "gcc_camss_cci_0_clk", 1455 .parent_hws = (const struct clk_hw *[]) 1456 { &gcc_camss_cci_clk_src.clkr.hw }, 1457 .num_parents = 1, 1458 .flags = CLK_SET_RATE_PARENT, 1459 .ops = &clk_branch2_ops, 1460 }, 1461 }, 1462 }; 1463 1464 static struct clk_branch gcc_camss_cphy_0_clk = { 1465 .halt_reg = 0x52088, 1466 .halt_check = BRANCH_HALT, 1467 .clkr = { 1468 .enable_reg = 0x52088, 1469 .enable_mask = BIT(0), 1470 .hw.init = &(struct clk_init_data){ 1471 .name = "gcc_camss_cphy_0_clk", 1472 .parent_hws = (const struct clk_hw *[]) 1473 { &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw }, 1474 .num_parents = 1, 1475 .flags = CLK_SET_RATE_PARENT, 1476 .ops = &clk_branch2_ops, 1477 }, 1478 }, 1479 }; 1480 1481 static struct clk_branch gcc_camss_cphy_1_clk = { 1482 .halt_reg = 0x5208c, 1483 .halt_check = BRANCH_HALT, 1484 .clkr = { 1485 .enable_reg = 0x5208c, 1486 .enable_mask = BIT(0), 1487 .hw.init = &(struct clk_init_data){ 1488 .name = "gcc_camss_cphy_1_clk", 1489 .parent_hws = (const struct clk_hw *[]) 1490 { &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw }, 1491 .num_parents = 1, 1492 .flags = CLK_SET_RATE_PARENT, 1493 .ops = &clk_branch2_ops, 1494 }, 1495 }, 1496 }; 1497 1498 static struct clk_branch gcc_camss_csi0phytimer_clk = { 1499 .halt_reg = 0x45018, 1500 .halt_check = BRANCH_HALT, 1501 .clkr = { 1502 .enable_reg = 0x45018, 1503 .enable_mask = BIT(0), 1504 .hw.init = &(struct clk_init_data){ 1505 .name = "gcc_camss_csi0phytimer_clk", 1506 .parent_hws = (const struct clk_hw *[]) 1507 { &gcc_camss_csi0phytimer_clk_src.clkr.hw }, 1508 .num_parents = 1, 1509 .flags = CLK_SET_RATE_PARENT, 1510 .ops = &clk_branch2_ops, 1511 }, 1512 }, 1513 }; 1514 1515 static struct clk_branch gcc_camss_csi1phytimer_clk = { 1516 .halt_reg = 0x45034, 1517 .halt_check = BRANCH_HALT, 1518 .clkr = { 1519 .enable_reg = 0x45034, 1520 .enable_mask = BIT(0), 1521 .hw.init = &(struct clk_init_data){ 1522 .name = "gcc_camss_csi1phytimer_clk", 1523 .parent_hws = (const struct clk_hw *[]) 1524 { &gcc_camss_csi1phytimer_clk_src.clkr.hw }, 1525 .num_parents = 1, 1526 .flags = CLK_SET_RATE_PARENT, 1527 .ops = &clk_branch2_ops, 1528 }, 1529 }, 1530 }; 1531 1532 static struct clk_branch gcc_camss_mclk0_clk = { 1533 .halt_reg = 0x51018, 1534 .halt_check = BRANCH_HALT, 1535 .clkr = { 1536 .enable_reg = 0x51018, 1537 .enable_mask = BIT(0), 1538 .hw.init = &(struct clk_init_data){ 1539 .name = "gcc_camss_mclk0_clk", 1540 .parent_hws = (const struct clk_hw *[]) 1541 { &gcc_camss_mclk0_clk_src.clkr.hw }, 1542 .num_parents = 1, 1543 .flags = CLK_SET_RATE_PARENT, 1544 .ops = &clk_branch2_ops, 1545 }, 1546 }, 1547 }; 1548 1549 static struct clk_branch gcc_camss_mclk1_clk = { 1550 .halt_reg = 0x51034, 1551 .halt_check = BRANCH_HALT, 1552 .clkr = { 1553 .enable_reg = 0x51034, 1554 .enable_mask = BIT(0), 1555 .hw.init = &(struct clk_init_data){ 1556 .name = "gcc_camss_mclk1_clk", 1557 .parent_hws = (const struct clk_hw *[]) 1558 { &gcc_camss_mclk1_clk_src.clkr.hw }, 1559 .num_parents = 1, 1560 .flags = CLK_SET_RATE_PARENT, 1561 .ops = &clk_branch2_ops, 1562 }, 1563 }, 1564 }; 1565 1566 static struct clk_branch gcc_camss_mclk2_clk = { 1567 .halt_reg = 0x51050, 1568 .halt_check = BRANCH_HALT, 1569 .clkr = { 1570 .enable_reg = 0x51050, 1571 .enable_mask = BIT(0), 1572 .hw.init = &(struct clk_init_data){ 1573 .name = "gcc_camss_mclk2_clk", 1574 .parent_hws = (const struct clk_hw *[]) 1575 { &gcc_camss_mclk2_clk_src.clkr.hw }, 1576 .num_parents = 1, 1577 .flags = CLK_SET_RATE_PARENT, 1578 .ops = &clk_branch2_ops, 1579 }, 1580 }, 1581 }; 1582 1583 static struct clk_branch gcc_camss_mclk3_clk = { 1584 .halt_reg = 0x5106c, 1585 .halt_check = BRANCH_HALT, 1586 .clkr = { 1587 .enable_reg = 0x5106c, 1588 .enable_mask = BIT(0), 1589 .hw.init = &(struct clk_init_data){ 1590 .name = "gcc_camss_mclk3_clk", 1591 .parent_hws = (const struct clk_hw *[]) 1592 { &gcc_camss_mclk3_clk_src.clkr.hw }, 1593 .num_parents = 1, 1594 .flags = CLK_SET_RATE_PARENT, 1595 .ops = &clk_branch2_ops, 1596 }, 1597 }, 1598 }; 1599 1600 static struct clk_branch gcc_camss_nrt_axi_clk = { 1601 .halt_reg = 0x58054, 1602 .halt_check = BRANCH_HALT, 1603 .clkr = { 1604 .enable_reg = 0x58054, 1605 .enable_mask = BIT(0), 1606 .hw.init = &(struct clk_init_data){ 1607 .name = "gcc_camss_nrt_axi_clk", 1608 .ops = &clk_branch2_ops, 1609 }, 1610 }, 1611 }; 1612 1613 static struct clk_branch gcc_camss_ope_ahb_clk = { 1614 .halt_reg = 0x5503c, 1615 .halt_check = BRANCH_HALT, 1616 .clkr = { 1617 .enable_reg = 0x5503c, 1618 .enable_mask = BIT(0), 1619 .hw.init = &(struct clk_init_data){ 1620 .name = "gcc_camss_ope_ahb_clk", 1621 .parent_hws = (const struct clk_hw *[]) 1622 { &gcc_camss_ope_ahb_clk_src.clkr.hw }, 1623 .num_parents = 1, 1624 .flags = CLK_SET_RATE_PARENT, 1625 .ops = &clk_branch2_ops, 1626 }, 1627 }, 1628 }; 1629 1630 static struct clk_branch gcc_camss_ope_clk = { 1631 .halt_reg = 0x5501c, 1632 .halt_check = BRANCH_HALT, 1633 .clkr = { 1634 .enable_reg = 0x5501c, 1635 .enable_mask = BIT(0), 1636 .hw.init = &(struct clk_init_data){ 1637 .name = "gcc_camss_ope_clk", 1638 .parent_hws = (const struct clk_hw *[]) 1639 { &gcc_camss_ope_clk_src.clkr.hw }, 1640 .num_parents = 1, 1641 .flags = CLK_SET_RATE_PARENT, 1642 .ops = &clk_branch2_ops, 1643 }, 1644 }, 1645 }; 1646 1647 static struct clk_branch gcc_camss_rt_axi_clk = { 1648 .halt_reg = 0x5805c, 1649 .halt_check = BRANCH_HALT, 1650 .clkr = { 1651 .enable_reg = 0x5805c, 1652 .enable_mask = BIT(0), 1653 .hw.init = &(struct clk_init_data){ 1654 .name = "gcc_camss_rt_axi_clk", 1655 .ops = &clk_branch2_ops, 1656 }, 1657 }, 1658 }; 1659 1660 static struct clk_branch gcc_camss_tfe_0_clk = { 1661 .halt_reg = 0x5201c, 1662 .halt_check = BRANCH_HALT, 1663 .clkr = { 1664 .enable_reg = 0x5201c, 1665 .enable_mask = BIT(0), 1666 .hw.init = &(struct clk_init_data){ 1667 .name = "gcc_camss_tfe_0_clk", 1668 .parent_hws = (const struct clk_hw *[]) 1669 { &gcc_camss_tfe_0_clk_src.clkr.hw }, 1670 .num_parents = 1, 1671 .flags = CLK_SET_RATE_PARENT, 1672 .ops = &clk_branch2_ops, 1673 }, 1674 }, 1675 }; 1676 1677 static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = { 1678 .halt_reg = 0x5207c, 1679 .halt_check = BRANCH_HALT, 1680 .clkr = { 1681 .enable_reg = 0x5207c, 1682 .enable_mask = BIT(0), 1683 .hw.init = &(struct clk_init_data){ 1684 .name = "gcc_camss_tfe_0_cphy_rx_clk", 1685 .parent_hws = (const struct clk_hw *[]) 1686 { &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw }, 1687 .num_parents = 1, 1688 .flags = CLK_SET_RATE_PARENT, 1689 .ops = &clk_branch2_ops, 1690 }, 1691 }, 1692 }; 1693 1694 static struct clk_branch gcc_camss_tfe_0_csid_clk = { 1695 .halt_reg = 0x520ac, 1696 .halt_check = BRANCH_HALT, 1697 .clkr = { 1698 .enable_reg = 0x520ac, 1699 .enable_mask = BIT(0), 1700 .hw.init = &(struct clk_init_data){ 1701 .name = "gcc_camss_tfe_0_csid_clk", 1702 .parent_hws = (const struct clk_hw *[]) 1703 { &gcc_camss_tfe_0_csid_clk_src.clkr.hw }, 1704 .num_parents = 1, 1705 .flags = CLK_SET_RATE_PARENT, 1706 .ops = &clk_branch2_ops, 1707 }, 1708 }, 1709 }; 1710 1711 static struct clk_branch gcc_camss_tfe_1_clk = { 1712 .halt_reg = 0x5203c, 1713 .halt_check = BRANCH_HALT, 1714 .clkr = { 1715 .enable_reg = 0x5203c, 1716 .enable_mask = BIT(0), 1717 .hw.init = &(struct clk_init_data){ 1718 .name = "gcc_camss_tfe_1_clk", 1719 .parent_hws = (const struct clk_hw *[]) 1720 { &gcc_camss_tfe_1_clk_src.clkr.hw }, 1721 .num_parents = 1, 1722 .flags = CLK_SET_RATE_PARENT, 1723 .ops = &clk_branch2_ops, 1724 }, 1725 }, 1726 }; 1727 1728 static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = { 1729 .halt_reg = 0x52080, 1730 .halt_check = BRANCH_HALT, 1731 .clkr = { 1732 .enable_reg = 0x52080, 1733 .enable_mask = BIT(0), 1734 .hw.init = &(struct clk_init_data){ 1735 .name = "gcc_camss_tfe_1_cphy_rx_clk", 1736 .parent_hws = (const struct clk_hw *[]) 1737 { &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw }, 1738 .num_parents = 1, 1739 .flags = CLK_SET_RATE_PARENT, 1740 .ops = &clk_branch2_ops, 1741 }, 1742 }, 1743 }; 1744 1745 static struct clk_branch gcc_camss_tfe_1_csid_clk = { 1746 .halt_reg = 0x520cc, 1747 .halt_check = BRANCH_HALT, 1748 .clkr = { 1749 .enable_reg = 0x520cc, 1750 .enable_mask = BIT(0), 1751 .hw.init = &(struct clk_init_data){ 1752 .name = "gcc_camss_tfe_1_csid_clk", 1753 .parent_hws = (const struct clk_hw *[]) 1754 { &gcc_camss_tfe_1_csid_clk_src.clkr.hw }, 1755 .num_parents = 1, 1756 .flags = CLK_SET_RATE_PARENT, 1757 .ops = &clk_branch2_ops, 1758 }, 1759 }, 1760 }; 1761 1762 static struct clk_branch gcc_camss_top_ahb_clk = { 1763 .halt_reg = 0x58028, 1764 .halt_check = BRANCH_HALT, 1765 .clkr = { 1766 .enable_reg = 0x58028, 1767 .enable_mask = BIT(0), 1768 .hw.init = &(struct clk_init_data){ 1769 .name = "gcc_camss_top_ahb_clk", 1770 .parent_hws = (const struct clk_hw *[]) 1771 { &gcc_camss_top_ahb_clk_src.clkr.hw }, 1772 .num_parents = 1, 1773 .flags = CLK_SET_RATE_PARENT, 1774 .ops = &clk_branch2_ops, 1775 }, 1776 }, 1777 }; 1778 1779 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1780 .halt_reg = 0x1a084, 1781 .halt_check = BRANCH_HALT, 1782 .hwcg_reg = 0x1a084, 1783 .hwcg_bit = 1, 1784 .clkr = { 1785 .enable_reg = 0x1a084, 1786 .enable_mask = BIT(0), 1787 .hw.init = &(struct clk_init_data){ 1788 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1789 .parent_hws = (const struct clk_hw *[]) 1790 { &gcc_usb30_prim_master_clk_src.clkr.hw }, 1791 .num_parents = 1, 1792 .flags = CLK_SET_RATE_PARENT, 1793 .ops = &clk_branch2_ops, 1794 }, 1795 }, 1796 }; 1797 1798 static struct clk_regmap_div gcc_disp_gpll0_clk_src = { 1799 .reg = 0x17058, 1800 .shift = 0, 1801 .width = 2, 1802 .clkr.hw.init = &(struct clk_init_data) { 1803 .name = "gcc_disp_gpll0_clk_src", 1804 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 1805 .num_parents = 1, 1806 .ops = &clk_regmap_div_ops, 1807 }, 1808 }; 1809 1810 static struct clk_branch gcc_disp_gpll0_div_clk_src = { 1811 .halt_check = BRANCH_HALT_DELAY, 1812 .clkr = { 1813 .enable_reg = 0x79004, 1814 .enable_mask = BIT(20), 1815 .hw.init = &(struct clk_init_data){ 1816 .name = "gcc_disp_gpll0_div_clk_src", 1817 .parent_hws = (const struct clk_hw *[]) 1818 { &gcc_disp_gpll0_clk_src.clkr.hw }, 1819 .num_parents = 1, 1820 .flags = CLK_SET_RATE_PARENT, 1821 .ops = &clk_branch2_ops, 1822 }, 1823 }, 1824 }; 1825 1826 static struct clk_branch gcc_disp_hf_axi_clk = { 1827 .halt_reg = 0x17020, 1828 .halt_check = BRANCH_HALT, 1829 .hwcg_reg = 0x17020, 1830 .hwcg_bit = 1, 1831 .clkr = { 1832 .enable_reg = 0x17020, 1833 .enable_mask = BIT(0), 1834 .hw.init = &(struct clk_init_data){ 1835 .name = "gcc_disp_hf_axi_clk", 1836 .ops = &clk_branch2_ops, 1837 }, 1838 }, 1839 }; 1840 1841 static struct clk_branch gcc_disp_throttle_core_clk = { 1842 .halt_reg = 0x17064, 1843 .halt_check = BRANCH_HALT_VOTED, 1844 .hwcg_reg = 0x17064, 1845 .hwcg_bit = 1, 1846 .clkr = { 1847 .enable_reg = 0x7900c, 1848 .enable_mask = BIT(5), 1849 .hw.init = &(struct clk_init_data){ 1850 .name = "gcc_disp_throttle_core_clk", 1851 .ops = &clk_branch2_ops, 1852 }, 1853 }, 1854 }; 1855 1856 static struct clk_branch gcc_gp1_clk = { 1857 .halt_reg = 0x4d000, 1858 .halt_check = BRANCH_HALT, 1859 .clkr = { 1860 .enable_reg = 0x4d000, 1861 .enable_mask = BIT(0), 1862 .hw.init = &(struct clk_init_data){ 1863 .name = "gcc_gp1_clk", 1864 .parent_hws = (const struct clk_hw *[]) 1865 { &gcc_gp1_clk_src.clkr.hw }, 1866 .num_parents = 1, 1867 .flags = CLK_SET_RATE_PARENT, 1868 .ops = &clk_branch2_ops, 1869 }, 1870 }, 1871 }; 1872 1873 static struct clk_branch gcc_gp2_clk = { 1874 .halt_reg = 0x4e000, 1875 .halt_check = BRANCH_HALT, 1876 .clkr = { 1877 .enable_reg = 0x4e000, 1878 .enable_mask = BIT(0), 1879 .hw.init = &(struct clk_init_data){ 1880 .name = "gcc_gp2_clk", 1881 .parent_hws = (const struct clk_hw *[]) 1882 { &gcc_gp2_clk_src.clkr.hw }, 1883 .num_parents = 1, 1884 .flags = CLK_SET_RATE_PARENT, 1885 .ops = &clk_branch2_ops, 1886 }, 1887 }, 1888 }; 1889 1890 static struct clk_branch gcc_gp3_clk = { 1891 .halt_reg = 0x4f000, 1892 .halt_check = BRANCH_HALT, 1893 .clkr = { 1894 .enable_reg = 0x4f000, 1895 .enable_mask = BIT(0), 1896 .hw.init = &(struct clk_init_data){ 1897 .name = "gcc_gp3_clk", 1898 .parent_hws = (const struct clk_hw *[]) 1899 { &gcc_gp3_clk_src.clkr.hw }, 1900 .num_parents = 1, 1901 .flags = CLK_SET_RATE_PARENT, 1902 .ops = &clk_branch2_ops, 1903 }, 1904 }, 1905 }; 1906 1907 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1908 .halt_check = BRANCH_HALT_DELAY, 1909 .clkr = { 1910 .enable_reg = 0x79004, 1911 .enable_mask = BIT(15), 1912 .hw.init = &(struct clk_init_data){ 1913 .name = "gcc_gpu_gpll0_clk_src", 1914 .parent_hws = (const struct clk_hw *[]) 1915 { &gpll0.clkr.hw }, 1916 .num_parents = 1, 1917 .flags = CLK_SET_RATE_PARENT, 1918 .ops = &clk_branch2_ops, 1919 }, 1920 }, 1921 }; 1922 1923 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1924 .halt_check = BRANCH_HALT_DELAY, 1925 .clkr = { 1926 .enable_reg = 0x79004, 1927 .enable_mask = BIT(16), 1928 .hw.init = &(struct clk_init_data){ 1929 .name = "gcc_gpu_gpll0_div_clk_src", 1930 .parent_hws = (const struct clk_hw *[]) 1931 { &gpll0_out_aux2.clkr.hw }, 1932 .num_parents = 1, 1933 .flags = CLK_SET_RATE_PARENT, 1934 .ops = &clk_branch2_ops, 1935 }, 1936 }, 1937 }; 1938 1939 static struct clk_branch gcc_gpu_iref_clk = { 1940 .halt_reg = 0x36100, 1941 .halt_check = BRANCH_HALT_DELAY, 1942 .clkr = { 1943 .enable_reg = 0x36100, 1944 .enable_mask = BIT(0), 1945 .hw.init = &(struct clk_init_data){ 1946 .name = "gcc_gpu_iref_clk", 1947 .ops = &clk_branch2_ops, 1948 }, 1949 }, 1950 }; 1951 1952 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1953 .halt_reg = 0x3600c, 1954 .halt_check = BRANCH_VOTED, 1955 .hwcg_reg = 0x3600c, 1956 .hwcg_bit = 1, 1957 .clkr = { 1958 .enable_reg = 0x3600c, 1959 .enable_mask = BIT(0), 1960 .hw.init = &(struct clk_init_data){ 1961 .name = "gcc_gpu_memnoc_gfx_clk", 1962 .ops = &clk_branch2_ops, 1963 }, 1964 }, 1965 }; 1966 1967 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1968 .halt_reg = 0x36018, 1969 .halt_check = BRANCH_HALT, 1970 .clkr = { 1971 .enable_reg = 0x36018, 1972 .enable_mask = BIT(0), 1973 .hw.init = &(struct clk_init_data){ 1974 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1975 .ops = &clk_branch2_ops, 1976 }, 1977 }, 1978 }; 1979 1980 static struct clk_branch gcc_gpu_throttle_core_clk = { 1981 .halt_reg = 0x36048, 1982 .halt_check = BRANCH_HALT_VOTED, 1983 .hwcg_reg = 0x36048, 1984 .hwcg_bit = 1, 1985 .clkr = { 1986 .enable_reg = 0x79004, 1987 .enable_mask = BIT(31), 1988 .hw.init = &(struct clk_init_data){ 1989 .name = "gcc_gpu_throttle_core_clk", 1990 .flags = CLK_SET_RATE_PARENT, 1991 .ops = &clk_branch2_ops, 1992 }, 1993 }, 1994 }; 1995 1996 static struct clk_branch gcc_pdm2_clk = { 1997 .halt_reg = 0x2000c, 1998 .halt_check = BRANCH_HALT, 1999 .clkr = { 2000 .enable_reg = 0x2000c, 2001 .enable_mask = BIT(0), 2002 .hw.init = &(struct clk_init_data){ 2003 .name = "gcc_pdm2_clk", 2004 .parent_hws = (const struct clk_hw *[]) 2005 { &gcc_pdm2_clk_src.clkr.hw }, 2006 .num_parents = 1, 2007 .flags = CLK_SET_RATE_PARENT, 2008 .ops = &clk_branch2_ops, 2009 }, 2010 }, 2011 }; 2012 2013 static struct clk_branch gcc_pdm_ahb_clk = { 2014 .halt_reg = 0x20004, 2015 .halt_check = BRANCH_HALT, 2016 .hwcg_reg = 0x20004, 2017 .hwcg_bit = 1, 2018 .clkr = { 2019 .enable_reg = 0x20004, 2020 .enable_mask = BIT(0), 2021 .hw.init = &(struct clk_init_data){ 2022 .name = "gcc_pdm_ahb_clk", 2023 .ops = &clk_branch2_ops, 2024 }, 2025 }, 2026 }; 2027 2028 static struct clk_branch gcc_pdm_xo4_clk = { 2029 .halt_reg = 0x20008, 2030 .halt_check = BRANCH_HALT, 2031 .clkr = { 2032 .enable_reg = 0x20008, 2033 .enable_mask = BIT(0), 2034 .hw.init = &(struct clk_init_data){ 2035 .name = "gcc_pdm_xo4_clk", 2036 .ops = &clk_branch2_ops, 2037 }, 2038 }, 2039 }; 2040 2041 static struct clk_branch gcc_pwm0_xo512_clk = { 2042 .halt_reg = 0x2002c, 2043 .halt_check = BRANCH_HALT, 2044 .clkr = { 2045 .enable_reg = 0x2002c, 2046 .enable_mask = BIT(0), 2047 .hw.init = &(struct clk_init_data){ 2048 .name = "gcc_pwm0_xo512_clk", 2049 .ops = &clk_branch2_ops, 2050 }, 2051 }, 2052 }; 2053 2054 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 2055 .halt_reg = 0x17014, 2056 .halt_check = BRANCH_HALT_VOTED, 2057 .hwcg_reg = 0x17014, 2058 .hwcg_bit = 1, 2059 .clkr = { 2060 .enable_reg = 0x7900c, 2061 .enable_mask = BIT(0), 2062 .hw.init = &(struct clk_init_data){ 2063 .name = "gcc_qmip_camera_nrt_ahb_clk", 2064 .ops = &clk_branch2_ops, 2065 }, 2066 }, 2067 }; 2068 2069 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 2070 .halt_reg = 0x17060, 2071 .halt_check = BRANCH_HALT_VOTED, 2072 .hwcg_reg = 0x17060, 2073 .hwcg_bit = 1, 2074 .clkr = { 2075 .enable_reg = 0x7900c, 2076 .enable_mask = BIT(2), 2077 .hw.init = &(struct clk_init_data){ 2078 .name = "gcc_qmip_camera_rt_ahb_clk", 2079 .ops = &clk_branch2_ops, 2080 }, 2081 }, 2082 }; 2083 2084 static struct clk_branch gcc_qmip_disp_ahb_clk = { 2085 .halt_reg = 0x17018, 2086 .halt_check = BRANCH_HALT_VOTED, 2087 .hwcg_reg = 0x17018, 2088 .hwcg_bit = 1, 2089 .clkr = { 2090 .enable_reg = 0x7900c, 2091 .enable_mask = BIT(1), 2092 .hw.init = &(struct clk_init_data){ 2093 .name = "gcc_qmip_disp_ahb_clk", 2094 .ops = &clk_branch2_ops, 2095 }, 2096 }, 2097 }; 2098 2099 static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = { 2100 .halt_reg = 0x36040, 2101 .halt_check = BRANCH_HALT_VOTED, 2102 .hwcg_reg = 0x36040, 2103 .hwcg_bit = 1, 2104 .clkr = { 2105 .enable_reg = 0x7900c, 2106 .enable_mask = BIT(4), 2107 .hw.init = &(struct clk_init_data){ 2108 .name = "gcc_qmip_gpu_cfg_ahb_clk", 2109 .ops = &clk_branch2_ops, 2110 }, 2111 }, 2112 }; 2113 2114 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 2115 .halt_reg = 0x17010, 2116 .halt_check = BRANCH_HALT_VOTED, 2117 .hwcg_reg = 0x17010, 2118 .hwcg_bit = 1, 2119 .clkr = { 2120 .enable_reg = 0x79004, 2121 .enable_mask = BIT(25), 2122 .hw.init = &(struct clk_init_data){ 2123 .name = "gcc_qmip_video_vcodec_ahb_clk", 2124 .ops = &clk_branch2_ops, 2125 }, 2126 }, 2127 }; 2128 2129 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 2130 .halt_reg = 0x1f014, 2131 .halt_check = BRANCH_HALT_VOTED, 2132 .clkr = { 2133 .enable_reg = 0x7900c, 2134 .enable_mask = BIT(9), 2135 .hw.init = &(struct clk_init_data){ 2136 .name = "gcc_qupv3_wrap0_core_2x_clk", 2137 .ops = &clk_branch2_ops, 2138 }, 2139 }, 2140 }; 2141 2142 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 2143 .halt_reg = 0x1f00c, 2144 .halt_check = BRANCH_HALT_VOTED, 2145 .clkr = { 2146 .enable_reg = 0x7900c, 2147 .enable_mask = BIT(8), 2148 .hw.init = &(struct clk_init_data){ 2149 .name = "gcc_qupv3_wrap0_core_clk", 2150 .ops = &clk_branch2_ops, 2151 }, 2152 }, 2153 }; 2154 2155 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2156 .halt_reg = 0x1f144, 2157 .halt_check = BRANCH_HALT_VOTED, 2158 .clkr = { 2159 .enable_reg = 0x7900c, 2160 .enable_mask = BIT(10), 2161 .hw.init = &(struct clk_init_data){ 2162 .name = "gcc_qupv3_wrap0_s0_clk", 2163 .parent_hws = (const struct clk_hw *[]) 2164 { &gcc_qupv3_wrap0_s0_clk_src.clkr.hw }, 2165 .num_parents = 1, 2166 .flags = CLK_SET_RATE_PARENT, 2167 .ops = &clk_branch2_ops, 2168 }, 2169 }, 2170 }; 2171 2172 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2173 .halt_reg = 0x1f274, 2174 .halt_check = BRANCH_HALT_VOTED, 2175 .clkr = { 2176 .enable_reg = 0x7900c, 2177 .enable_mask = BIT(11), 2178 .hw.init = &(struct clk_init_data){ 2179 .name = "gcc_qupv3_wrap0_s1_clk", 2180 .parent_hws = (const struct clk_hw *[]) 2181 { &gcc_qupv3_wrap0_s1_clk_src.clkr.hw }, 2182 .num_parents = 1, 2183 .flags = CLK_SET_RATE_PARENT, 2184 .ops = &clk_branch2_ops, 2185 }, 2186 }, 2187 }; 2188 2189 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2190 .halt_reg = 0x1f3a4, 2191 .halt_check = BRANCH_HALT_VOTED, 2192 .clkr = { 2193 .enable_reg = 0x7900c, 2194 .enable_mask = BIT(12), 2195 .hw.init = &(struct clk_init_data){ 2196 .name = "gcc_qupv3_wrap0_s2_clk", 2197 .parent_hws = (const struct clk_hw *[]) 2198 { &gcc_qupv3_wrap0_s2_clk_src.clkr.hw }, 2199 .num_parents = 1, 2200 .flags = CLK_SET_RATE_PARENT, 2201 .ops = &clk_branch2_ops, 2202 }, 2203 }, 2204 }; 2205 2206 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2207 .halt_reg = 0x1f4d4, 2208 .halt_check = BRANCH_HALT_VOTED, 2209 .clkr = { 2210 .enable_reg = 0x7900c, 2211 .enable_mask = BIT(13), 2212 .hw.init = &(struct clk_init_data){ 2213 .name = "gcc_qupv3_wrap0_s3_clk", 2214 .parent_hws = (const struct clk_hw *[]) 2215 { &gcc_qupv3_wrap0_s3_clk_src.clkr.hw }, 2216 .num_parents = 1, 2217 .flags = CLK_SET_RATE_PARENT, 2218 .ops = &clk_branch2_ops, 2219 }, 2220 }, 2221 }; 2222 2223 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2224 .halt_reg = 0x1f604, 2225 .halt_check = BRANCH_HALT_VOTED, 2226 .clkr = { 2227 .enable_reg = 0x7900c, 2228 .enable_mask = BIT(14), 2229 .hw.init = &(struct clk_init_data){ 2230 .name = "gcc_qupv3_wrap0_s4_clk", 2231 .parent_hws = (const struct clk_hw *[]) 2232 { &gcc_qupv3_wrap0_s4_clk_src.clkr.hw }, 2233 .num_parents = 1, 2234 .flags = CLK_SET_RATE_PARENT, 2235 .ops = &clk_branch2_ops, 2236 }, 2237 }, 2238 }; 2239 2240 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2241 .halt_reg = 0x1f734, 2242 .halt_check = BRANCH_HALT_VOTED, 2243 .clkr = { 2244 .enable_reg = 0x7900c, 2245 .enable_mask = BIT(15), 2246 .hw.init = &(struct clk_init_data){ 2247 .name = "gcc_qupv3_wrap0_s5_clk", 2248 .parent_hws = (const struct clk_hw *[]) 2249 { &gcc_qupv3_wrap0_s5_clk_src.clkr.hw }, 2250 .num_parents = 1, 2251 .flags = CLK_SET_RATE_PARENT, 2252 .ops = &clk_branch2_ops, 2253 }, 2254 }, 2255 }; 2256 2257 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2258 .halt_reg = 0x1f004, 2259 .halt_check = BRANCH_HALT_VOTED, 2260 .hwcg_reg = 0x1f004, 2261 .hwcg_bit = 1, 2262 .clkr = { 2263 .enable_reg = 0x7900c, 2264 .enable_mask = BIT(6), 2265 .hw.init = &(struct clk_init_data){ 2266 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2267 .ops = &clk_branch2_ops, 2268 }, 2269 }, 2270 }; 2271 2272 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2273 .halt_reg = 0x1f008, 2274 .halt_check = BRANCH_HALT_VOTED, 2275 .hwcg_reg = 0x1f008, 2276 .hwcg_bit = 1, 2277 .clkr = { 2278 .enable_reg = 0x7900c, 2279 .enable_mask = BIT(7), 2280 .hw.init = &(struct clk_init_data){ 2281 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2282 .ops = &clk_branch2_ops, 2283 }, 2284 }, 2285 }; 2286 2287 static struct clk_branch gcc_sdcc1_ahb_clk = { 2288 .halt_reg = 0x38008, 2289 .halt_check = BRANCH_HALT, 2290 .clkr = { 2291 .enable_reg = 0x38008, 2292 .enable_mask = BIT(0), 2293 .hw.init = &(struct clk_init_data){ 2294 .name = "gcc_sdcc1_ahb_clk", 2295 .ops = &clk_branch2_ops, 2296 }, 2297 }, 2298 }; 2299 2300 static struct clk_branch gcc_sdcc1_apps_clk = { 2301 .halt_reg = 0x38004, 2302 .halt_check = BRANCH_HALT, 2303 .clkr = { 2304 .enable_reg = 0x38004, 2305 .enable_mask = BIT(0), 2306 .hw.init = &(struct clk_init_data){ 2307 .name = "gcc_sdcc1_apps_clk", 2308 .parent_hws = (const struct clk_hw *[]) 2309 { &gcc_sdcc1_apps_clk_src.clkr.hw }, 2310 .num_parents = 1, 2311 .flags = CLK_SET_RATE_PARENT, 2312 .ops = &clk_branch2_ops, 2313 }, 2314 }, 2315 }; 2316 2317 static struct clk_branch gcc_sdcc1_ice_core_clk = { 2318 .halt_reg = 0x3800c, 2319 .halt_check = BRANCH_HALT, 2320 .hwcg_reg = 0x3800c, 2321 .hwcg_bit = 1, 2322 .clkr = { 2323 .enable_reg = 0x3800c, 2324 .enable_mask = BIT(0), 2325 .hw.init = &(struct clk_init_data){ 2326 .name = "gcc_sdcc1_ice_core_clk", 2327 .parent_hws = (const struct clk_hw *[]) 2328 { &gcc_sdcc1_ice_core_clk_src.clkr.hw }, 2329 .num_parents = 1, 2330 .flags = CLK_SET_RATE_PARENT, 2331 .ops = &clk_branch2_ops, 2332 }, 2333 }, 2334 }; 2335 2336 static struct clk_branch gcc_sdcc2_ahb_clk = { 2337 .halt_reg = 0x1e008, 2338 .halt_check = BRANCH_HALT, 2339 .clkr = { 2340 .enable_reg = 0x1e008, 2341 .enable_mask = BIT(0), 2342 .hw.init = &(struct clk_init_data){ 2343 .name = "gcc_sdcc2_ahb_clk", 2344 .ops = &clk_branch2_ops, 2345 }, 2346 }, 2347 }; 2348 2349 static struct clk_branch gcc_sdcc2_apps_clk = { 2350 .halt_reg = 0x1e004, 2351 .halt_check = BRANCH_HALT, 2352 .clkr = { 2353 .enable_reg = 0x1e004, 2354 .enable_mask = BIT(0), 2355 .hw.init = &(struct clk_init_data){ 2356 .name = "gcc_sdcc2_apps_clk", 2357 .parent_hws = (const struct clk_hw *[]) 2358 { &gcc_sdcc2_apps_clk_src.clkr.hw }, 2359 .num_parents = 1, 2360 .flags = CLK_SET_RATE_PARENT, 2361 .ops = &clk_branch2_ops, 2362 }, 2363 }, 2364 }; 2365 2366 static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { 2367 .halt_reg = 0x1a080, 2368 .halt_check = BRANCH_HALT, 2369 .hwcg_reg = 0x1a080, 2370 .hwcg_bit = 1, 2371 .clkr = { 2372 .enable_reg = 0x1a080, 2373 .enable_mask = BIT(0), 2374 .hw.init = &(struct clk_init_data){ 2375 .name = "gcc_sys_noc_usb3_prim_axi_clk", 2376 .parent_hws = (const struct clk_hw *[]) 2377 { &gcc_usb30_prim_master_clk_src.clkr.hw }, 2378 .num_parents = 1, 2379 .flags = CLK_SET_RATE_PARENT, 2380 .ops = &clk_branch2_ops, 2381 }, 2382 }, 2383 }; 2384 2385 static struct clk_branch gcc_usb30_prim_master_clk = { 2386 .halt_reg = 0x1a010, 2387 .halt_check = BRANCH_HALT, 2388 .clkr = { 2389 .enable_reg = 0x1a010, 2390 .enable_mask = BIT(0), 2391 .hw.init = &(struct clk_init_data){ 2392 .name = "gcc_usb30_prim_master_clk", 2393 .parent_hws = (const struct clk_hw *[]) 2394 { &gcc_usb30_prim_master_clk_src.clkr.hw }, 2395 .num_parents = 1, 2396 .flags = CLK_SET_RATE_PARENT, 2397 .ops = &clk_branch2_ops, 2398 }, 2399 }, 2400 }; 2401 2402 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2403 .halt_reg = 0x1a018, 2404 .halt_check = BRANCH_HALT, 2405 .clkr = { 2406 .enable_reg = 0x1a018, 2407 .enable_mask = BIT(0), 2408 .hw.init = &(struct clk_init_data){ 2409 .name = "gcc_usb30_prim_mock_utmi_clk", 2410 .parent_hws = (const struct clk_hw *[]) 2411 { &gcc_usb30_prim_mock_utmi_postdiv.clkr.hw }, 2412 .num_parents = 1, 2413 .flags = CLK_SET_RATE_PARENT, 2414 .ops = &clk_branch2_ops, 2415 }, 2416 }, 2417 }; 2418 2419 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2420 .halt_reg = 0x1a014, 2421 .halt_check = BRANCH_HALT, 2422 .clkr = { 2423 .enable_reg = 0x1a014, 2424 .enable_mask = BIT(0), 2425 .hw.init = &(struct clk_init_data){ 2426 .name = "gcc_usb30_prim_sleep_clk", 2427 .ops = &clk_branch2_ops, 2428 }, 2429 }, 2430 }; 2431 2432 static struct clk_branch gcc_usb3_prim_clkref_clk = { 2433 .halt_reg = 0x9f000, 2434 .halt_check = BRANCH_HALT, 2435 .clkr = { 2436 .enable_reg = 0x9f000, 2437 .enable_mask = BIT(0), 2438 .hw.init = &(struct clk_init_data){ 2439 .name = "gcc_usb3_prim_clkref_clk", 2440 .ops = &clk_branch2_ops, 2441 }, 2442 }, 2443 }; 2444 2445 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2446 .halt_reg = 0x1a054, 2447 .halt_check = BRANCH_HALT, 2448 .clkr = { 2449 .enable_reg = 0x1a054, 2450 .enable_mask = BIT(0), 2451 .hw.init = &(struct clk_init_data){ 2452 .name = "gcc_usb3_prim_phy_com_aux_clk", 2453 .parent_hws = (const struct clk_hw *[]) 2454 { &gcc_usb3_prim_phy_aux_clk_src.clkr.hw }, 2455 .num_parents = 1, 2456 .flags = CLK_SET_RATE_PARENT, 2457 .ops = &clk_branch2_ops, 2458 }, 2459 }, 2460 }; 2461 2462 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2463 .halt_reg = 0x1a058, 2464 .halt_check = BRANCH_HALT_SKIP, 2465 .hwcg_reg = 0x1a058, 2466 .hwcg_bit = 1, 2467 .clkr = { 2468 .enable_reg = 0x1a058, 2469 .enable_mask = BIT(0), 2470 .hw.init = &(struct clk_init_data){ 2471 .name = "gcc_usb3_prim_phy_pipe_clk", 2472 .ops = &clk_branch2_ops, 2473 }, 2474 }, 2475 }; 2476 2477 static struct clk_branch gcc_vcodec0_axi_clk = { 2478 .halt_reg = 0x6e008, 2479 .halt_check = BRANCH_HALT, 2480 .clkr = { 2481 .enable_reg = 0x6e008, 2482 .enable_mask = BIT(0), 2483 .hw.init = &(struct clk_init_data){ 2484 .name = "gcc_vcodec0_axi_clk", 2485 .ops = &clk_branch2_ops, 2486 }, 2487 }, 2488 }; 2489 2490 static struct clk_branch gcc_venus_ahb_clk = { 2491 .halt_reg = 0x6e010, 2492 .halt_check = BRANCH_HALT, 2493 .clkr = { 2494 .enable_reg = 0x6e010, 2495 .enable_mask = BIT(0), 2496 .hw.init = &(struct clk_init_data){ 2497 .name = "gcc_venus_ahb_clk", 2498 .ops = &clk_branch2_ops, 2499 }, 2500 }, 2501 }; 2502 2503 static struct clk_branch gcc_venus_ctl_axi_clk = { 2504 .halt_reg = 0x6e004, 2505 .halt_check = BRANCH_HALT, 2506 .clkr = { 2507 .enable_reg = 0x6e004, 2508 .enable_mask = BIT(0), 2509 .hw.init = &(struct clk_init_data){ 2510 .name = "gcc_venus_ctl_axi_clk", 2511 .ops = &clk_branch2_ops, 2512 }, 2513 }, 2514 }; 2515 2516 static struct clk_branch gcc_video_ahb_clk = { 2517 .halt_reg = 0x17004, 2518 .halt_check = BRANCH_HALT, 2519 .hwcg_reg = 0x17004, 2520 .hwcg_bit = 1, 2521 .clkr = { 2522 .enable_reg = 0x17004, 2523 .enable_mask = BIT(0), 2524 .hw.init = &(struct clk_init_data){ 2525 .name = "gcc_video_ahb_clk", 2526 .ops = &clk_branch2_ops, 2527 }, 2528 }, 2529 }; 2530 2531 static struct clk_branch gcc_video_axi0_clk = { 2532 .halt_reg = 0x1701c, 2533 .halt_check = BRANCH_HALT, 2534 .hwcg_reg = 0x1701c, 2535 .hwcg_bit = 1, 2536 .clkr = { 2537 .enable_reg = 0x1701c, 2538 .enable_mask = BIT(0), 2539 .hw.init = &(struct clk_init_data){ 2540 .name = "gcc_video_axi0_clk", 2541 .ops = &clk_branch2_ops, 2542 }, 2543 }, 2544 }; 2545 2546 static struct clk_branch gcc_video_throttle_core_clk = { 2547 .halt_reg = 0x17068, 2548 .halt_check = BRANCH_HALT_VOTED, 2549 .hwcg_reg = 0x17068, 2550 .hwcg_bit = 1, 2551 .clkr = { 2552 .enable_reg = 0x79004, 2553 .enable_mask = BIT(28), 2554 .hw.init = &(struct clk_init_data){ 2555 .name = "gcc_video_throttle_core_clk", 2556 .ops = &clk_branch2_ops, 2557 }, 2558 }, 2559 }; 2560 2561 static struct clk_branch gcc_video_vcodec0_sys_clk = { 2562 .halt_reg = 0x580a4, 2563 .halt_check = BRANCH_HALT_DELAY, 2564 .hwcg_reg = 0x580a4, 2565 .hwcg_bit = 1, 2566 .clkr = { 2567 .enable_reg = 0x580a4, 2568 .enable_mask = BIT(0), 2569 .hw.init = &(struct clk_init_data){ 2570 .name = "gcc_video_vcodec0_sys_clk", 2571 .parent_hws = (const struct clk_hw *[]) 2572 { &gcc_video_venus_clk_src.clkr.hw }, 2573 .num_parents = 1, 2574 .flags = CLK_SET_RATE_PARENT, 2575 .ops = &clk_branch2_ops, 2576 }, 2577 }, 2578 }; 2579 2580 static struct clk_branch gcc_video_venus_ctl_clk = { 2581 .halt_reg = 0x5808c, 2582 .halt_check = BRANCH_HALT, 2583 .clkr = { 2584 .enable_reg = 0x5808c, 2585 .enable_mask = BIT(0), 2586 .hw.init = &(struct clk_init_data){ 2587 .name = "gcc_video_venus_ctl_clk", 2588 .parent_hws = (const struct clk_hw *[]) 2589 { &gcc_video_venus_clk_src.clkr.hw }, 2590 .num_parents = 1, 2591 .flags = CLK_SET_RATE_PARENT, 2592 .ops = &clk_branch2_ops, 2593 }, 2594 }, 2595 }; 2596 2597 static struct clk_branch gcc_video_xo_clk = { 2598 .halt_reg = 0x17024, 2599 .halt_check = BRANCH_HALT, 2600 .clkr = { 2601 .enable_reg = 0x17024, 2602 .enable_mask = BIT(0), 2603 .hw.init = &(struct clk_init_data){ 2604 .name = "gcc_video_xo_clk", 2605 .ops = &clk_branch2_ops, 2606 }, 2607 }, 2608 }; 2609 2610 static struct gdsc gcc_camss_top_gdsc = { 2611 .gdscr = 0x58004, 2612 .pd = { 2613 .name = "gcc_camss_top", 2614 }, 2615 .pwrsts = PWRSTS_OFF_ON, 2616 }; 2617 2618 static struct gdsc gcc_usb30_prim_gdsc = { 2619 .gdscr = 0x1a004, 2620 .pd = { 2621 .name = "gcc_usb30_prim", 2622 }, 2623 .pwrsts = PWRSTS_OFF_ON, 2624 }; 2625 2626 static struct gdsc gcc_vcodec0_gdsc = { 2627 .gdscr = 0x58098, 2628 .pd = { 2629 .name = "gcc_vcodec0", 2630 }, 2631 .flags = HW_CTRL_TRIGGER, 2632 .pwrsts = PWRSTS_OFF_ON, 2633 }; 2634 2635 static struct gdsc gcc_venus_gdsc = { 2636 .gdscr = 0x5807c, 2637 .pd = { 2638 .name = "gcc_venus", 2639 }, 2640 .pwrsts = PWRSTS_OFF_ON, 2641 }; 2642 2643 static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = { 2644 .gdscr = 0x7d060, 2645 .pd = { 2646 .name = "hlos1_vote_turing_mmu_tbu1", 2647 }, 2648 .pwrsts = PWRSTS_OFF_ON, 2649 .flags = VOTABLE, 2650 }; 2651 2652 static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = { 2653 .gdscr = 0x7d07c, 2654 .pd = { 2655 .name = "hlos1_vote_turing_mmu_tbu0", 2656 }, 2657 .pwrsts = PWRSTS_OFF_ON, 2658 .flags = VOTABLE, 2659 }; 2660 2661 static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = { 2662 .gdscr = 0x7d074, 2663 .pd = { 2664 .name = "hlos1_vote_mm_snoc_mmu_tbu_rt", 2665 }, 2666 .pwrsts = PWRSTS_OFF_ON, 2667 .flags = VOTABLE, 2668 }; 2669 2670 static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = { 2671 .gdscr = 0x7d078, 2672 .pd = { 2673 .name = "hlos1_vote_mm_snoc_mmu_tbu_nrt", 2674 }, 2675 .pwrsts = PWRSTS_OFF_ON, 2676 .flags = VOTABLE, 2677 }; 2678 2679 static struct clk_regmap *gcc_qcm2290_clocks[] = { 2680 [GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr, 2681 [GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr, 2682 [GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr, 2683 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2684 [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, 2685 [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, 2686 [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, 2687 [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, 2688 [GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr, 2689 [GCC_CAMSS_CAMNOC_NTS_XO_CLK] = &gcc_camss_camnoc_nts_xo_clk.clkr, 2690 [GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr, 2691 [GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr, 2692 [GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr, 2693 [GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr, 2694 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, 2695 [GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr, 2696 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, 2697 [GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr, 2698 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, 2699 [GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr, 2700 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, 2701 [GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr, 2702 [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr, 2703 [GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr, 2704 [GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr, 2705 [GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr, 2706 [GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr, 2707 [GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr, 2708 [GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr, 2709 [GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr, 2710 [GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr, 2711 [GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr, 2712 [GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr, 2713 [GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr, 2714 [GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr, 2715 [GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr, 2716 [GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr, 2717 [GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr, 2718 [GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr, 2719 [GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr, 2720 [GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr, 2721 [GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr, 2722 [GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr, 2723 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, 2724 [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, 2725 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 2726 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, 2727 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, 2728 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 2729 [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, 2730 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2731 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 2732 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2733 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 2734 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2735 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 2736 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 2737 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 2738 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, 2739 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 2740 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 2741 [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr, 2742 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2743 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 2744 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2745 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 2746 [GCC_PWM0_XO512_CLK] = &gcc_pwm0_xo512_clk.clkr, 2747 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 2748 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 2749 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 2750 [GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr, 2751 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 2752 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 2753 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 2754 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 2755 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 2756 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 2757 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 2758 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 2759 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 2760 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 2761 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 2762 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 2763 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 2764 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 2765 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 2766 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 2767 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 2768 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2769 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2770 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 2771 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 2772 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 2773 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2774 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2775 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 2776 [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, 2777 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 2778 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 2779 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 2780 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 2781 &gcc_usb30_prim_mock_utmi_clk_src.clkr, 2782 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV] = 2783 &gcc_usb30_prim_mock_utmi_postdiv.clkr, 2784 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 2785 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 2786 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 2787 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 2788 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 2789 [GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr, 2790 [GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr, 2791 [GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr, 2792 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, 2793 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 2794 [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr, 2795 [GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr, 2796 [GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr, 2797 [GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr, 2798 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 2799 [GPLL0] = &gpll0.clkr, 2800 [GPLL0_OUT_AUX2] = &gpll0_out_aux2.clkr, 2801 [GPLL1] = &gpll1.clkr, 2802 [GPLL10] = &gpll10.clkr, 2803 [GPLL11] = &gpll11.clkr, 2804 [GPLL3] = &gpll3.clkr, 2805 [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr, 2806 [GPLL4] = &gpll4.clkr, 2807 [GPLL5] = &gpll5.clkr, 2808 [GPLL6] = &gpll6.clkr, 2809 [GPLL6_OUT_MAIN] = &gpll6_out_main.clkr, 2810 [GPLL7] = &gpll7.clkr, 2811 [GPLL8] = &gpll8.clkr, 2812 [GPLL8_OUT_MAIN] = &gpll8_out_main.clkr, 2813 [GPLL9] = &gpll9.clkr, 2814 [GPLL9_OUT_MAIN] = &gpll9_out_main.clkr, 2815 }; 2816 2817 static const struct qcom_reset_map gcc_qcm2290_resets[] = { 2818 [GCC_CAMSS_OPE_BCR] = { 0x55000 }, 2819 [GCC_CAMSS_TFE_BCR] = { 0x52000 }, 2820 [GCC_CAMSS_TOP_BCR] = { 0x58000 }, 2821 [GCC_GPU_BCR] = { 0x36000 }, 2822 [GCC_MMSS_BCR] = { 0x17000 }, 2823 [GCC_PDM_BCR] = { 0x20000 }, 2824 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x1f000 }, 2825 [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, 2826 [GCC_SDCC1_BCR] = { 0x38000 }, 2827 [GCC_SDCC2_BCR] = { 0x1e000 }, 2828 [GCC_USB30_PRIM_BCR] = { 0x1a000 }, 2829 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, 2830 [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 }, 2831 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, 2832 [GCC_VCODEC0_BCR] = { 0x58094 }, 2833 [GCC_VENUS_BCR] = { 0x58078 }, 2834 [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 }, 2835 }; 2836 2837 static struct gdsc *gcc_qcm2290_gdscs[] = { 2838 [GCC_CAMSS_TOP_GDSC] = &gcc_camss_top_gdsc, 2839 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, 2840 [GCC_VCODEC0_GDSC] = &gcc_vcodec0_gdsc, 2841 [GCC_VENUS_GDSC] = &gcc_venus_gdsc, 2842 [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc, 2843 [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc, 2844 [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc, 2845 [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc, 2846 }; 2847 2848 static const u32 gcc_qcm2290_critical_cbcrs[] = { 2849 0x17008, /* GCC_CAMERA_AHB_CLK */ 2850 0x17028, /* GCC_CAMERA_XO_CLK */ 2851 0x1700c, /* GCC_DISP_AHB_CLK */ 2852 0x1702c, /* GCC_DISP_XO_CLK */ 2853 0x36004, /* GCC_GPU_CFG_AHB_CLK */ 2854 0x79004, /* GCC_SYS_NOC_CPUSS_AHB_CLK */ 2855 }; 2856 2857 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 2858 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 2859 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 2860 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 2861 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 2862 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 2863 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 2864 }; 2865 2866 static const struct regmap_config gcc_qcm2290_regmap_config = { 2867 .reg_bits = 32, 2868 .reg_stride = 4, 2869 .val_bits = 32, 2870 .max_register = 0xc7000, 2871 .fast_io = true, 2872 }; 2873 2874 static const struct qcom_cc_driver_data gcc_qcm2290_driver_data = { 2875 .clk_cbcrs = gcc_qcm2290_critical_cbcrs, 2876 .num_clk_cbcrs = ARRAY_SIZE(gcc_qcm2290_critical_cbcrs), 2877 }; 2878 2879 static const struct qcom_cc_desc gcc_qcm2290_desc = { 2880 .config = &gcc_qcm2290_regmap_config, 2881 .clks = gcc_qcm2290_clocks, 2882 .num_clks = ARRAY_SIZE(gcc_qcm2290_clocks), 2883 .resets = gcc_qcm2290_resets, 2884 .num_resets = ARRAY_SIZE(gcc_qcm2290_resets), 2885 .gdscs = gcc_qcm2290_gdscs, 2886 .num_gdscs = ARRAY_SIZE(gcc_qcm2290_gdscs), 2887 .driver_data = &gcc_qcm2290_driver_data, 2888 }; 2889 2890 static const struct of_device_id gcc_qcm2290_match_table[] = { 2891 { .compatible = "qcom,gcc-qcm2290" }, 2892 { } 2893 }; 2894 MODULE_DEVICE_TABLE(of, gcc_qcm2290_match_table); 2895 2896 static int gcc_qcm2290_probe(struct platform_device *pdev) 2897 { 2898 struct regmap *regmap; 2899 int ret; 2900 2901 regmap = qcom_cc_map(pdev, &gcc_qcm2290_desc); 2902 if (IS_ERR(regmap)) 2903 return PTR_ERR(regmap); 2904 2905 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 2906 ARRAY_SIZE(gcc_dfs_clocks)); 2907 if (ret) 2908 return ret; 2909 2910 clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config); 2911 clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config); 2912 clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config); 2913 clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config); 2914 2915 return qcom_cc_really_probe(&pdev->dev, &gcc_qcm2290_desc, regmap); 2916 } 2917 2918 static struct platform_driver gcc_qcm2290_driver = { 2919 .probe = gcc_qcm2290_probe, 2920 .driver = { 2921 .name = "gcc-qcm2290", 2922 .of_match_table = gcc_qcm2290_match_table, 2923 }, 2924 }; 2925 2926 static int __init gcc_qcm2290_init(void) 2927 { 2928 return platform_driver_register(&gcc_qcm2290_driver); 2929 } 2930 subsys_initcall(gcc_qcm2290_init); 2931 2932 static void __exit gcc_qcm2290_exit(void) 2933 { 2934 platform_driver_unregister(&gcc_qcm2290_driver); 2935 } 2936 module_exit(gcc_qcm2290_exit); 2937 2938 MODULE_DESCRIPTION("QTI GCC QCM2290 Driver"); 2939 MODULE_LICENSE("GPL v2"); 2940