1 /* 2 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/bitops.h> 16 #include <linux/err.h> 17 #include <linux/platform_device.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/clk-provider.h> 22 #include <linux/regmap.h> 23 #include <linux/reset-controller.h> 24 25 #include <dt-bindings/clock/qcom,gcc-msm8974.h> 26 #include <dt-bindings/reset/qcom,gcc-msm8974.h> 27 28 #include "common.h" 29 #include "clk-regmap.h" 30 #include "clk-pll.h" 31 #include "clk-rcg.h" 32 #include "clk-branch.h" 33 #include "reset.h" 34 #include "gdsc.h" 35 36 enum { 37 P_XO, 38 P_GPLL0, 39 P_GPLL1, 40 P_GPLL4, 41 }; 42 43 static const struct parent_map gcc_xo_gpll0_map[] = { 44 { P_XO, 0 }, 45 { P_GPLL0, 1 } 46 }; 47 48 static const char * const gcc_xo_gpll0[] = { 49 "xo", 50 "gpll0_vote", 51 }; 52 53 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { 54 { P_XO, 0 }, 55 { P_GPLL0, 1 }, 56 { P_GPLL4, 5 } 57 }; 58 59 static const char * const gcc_xo_gpll0_gpll4[] = { 60 "xo", 61 "gpll0_vote", 62 "gpll4_vote", 63 }; 64 65 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } 66 67 static struct clk_pll gpll0 = { 68 .l_reg = 0x0004, 69 .m_reg = 0x0008, 70 .n_reg = 0x000c, 71 .config_reg = 0x0014, 72 .mode_reg = 0x0000, 73 .status_reg = 0x001c, 74 .status_bit = 17, 75 .clkr.hw.init = &(struct clk_init_data){ 76 .name = "gpll0", 77 .parent_names = (const char *[]){ "xo" }, 78 .num_parents = 1, 79 .ops = &clk_pll_ops, 80 }, 81 }; 82 83 static struct clk_regmap gpll0_vote = { 84 .enable_reg = 0x1480, 85 .enable_mask = BIT(0), 86 .hw.init = &(struct clk_init_data){ 87 .name = "gpll0_vote", 88 .parent_names = (const char *[]){ "gpll0" }, 89 .num_parents = 1, 90 .ops = &clk_pll_vote_ops, 91 }, 92 }; 93 94 static struct clk_rcg2 config_noc_clk_src = { 95 .cmd_rcgr = 0x0150, 96 .hid_width = 5, 97 .parent_map = gcc_xo_gpll0_map, 98 .clkr.hw.init = &(struct clk_init_data){ 99 .name = "config_noc_clk_src", 100 .parent_names = gcc_xo_gpll0, 101 .num_parents = 2, 102 .ops = &clk_rcg2_ops, 103 }, 104 }; 105 106 static struct clk_rcg2 periph_noc_clk_src = { 107 .cmd_rcgr = 0x0190, 108 .hid_width = 5, 109 .parent_map = gcc_xo_gpll0_map, 110 .clkr.hw.init = &(struct clk_init_data){ 111 .name = "periph_noc_clk_src", 112 .parent_names = gcc_xo_gpll0, 113 .num_parents = 2, 114 .ops = &clk_rcg2_ops, 115 }, 116 }; 117 118 static struct clk_rcg2 system_noc_clk_src = { 119 .cmd_rcgr = 0x0120, 120 .hid_width = 5, 121 .parent_map = gcc_xo_gpll0_map, 122 .clkr.hw.init = &(struct clk_init_data){ 123 .name = "system_noc_clk_src", 124 .parent_names = gcc_xo_gpll0, 125 .num_parents = 2, 126 .ops = &clk_rcg2_ops, 127 }, 128 }; 129 130 static struct clk_pll gpll1 = { 131 .l_reg = 0x0044, 132 .m_reg = 0x0048, 133 .n_reg = 0x004c, 134 .config_reg = 0x0054, 135 .mode_reg = 0x0040, 136 .status_reg = 0x005c, 137 .status_bit = 17, 138 .clkr.hw.init = &(struct clk_init_data){ 139 .name = "gpll1", 140 .parent_names = (const char *[]){ "xo" }, 141 .num_parents = 1, 142 .ops = &clk_pll_ops, 143 }, 144 }; 145 146 static struct clk_regmap gpll1_vote = { 147 .enable_reg = 0x1480, 148 .enable_mask = BIT(1), 149 .hw.init = &(struct clk_init_data){ 150 .name = "gpll1_vote", 151 .parent_names = (const char *[]){ "gpll1" }, 152 .num_parents = 1, 153 .ops = &clk_pll_vote_ops, 154 }, 155 }; 156 157 static struct clk_pll gpll4 = { 158 .l_reg = 0x1dc4, 159 .m_reg = 0x1dc8, 160 .n_reg = 0x1dcc, 161 .config_reg = 0x1dd4, 162 .mode_reg = 0x1dc0, 163 .status_reg = 0x1ddc, 164 .status_bit = 17, 165 .clkr.hw.init = &(struct clk_init_data){ 166 .name = "gpll4", 167 .parent_names = (const char *[]){ "xo" }, 168 .num_parents = 1, 169 .ops = &clk_pll_ops, 170 }, 171 }; 172 173 static struct clk_regmap gpll4_vote = { 174 .enable_reg = 0x1480, 175 .enable_mask = BIT(4), 176 .hw.init = &(struct clk_init_data){ 177 .name = "gpll4_vote", 178 .parent_names = (const char *[]){ "gpll4" }, 179 .num_parents = 1, 180 .ops = &clk_pll_vote_ops, 181 }, 182 }; 183 184 static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = { 185 F(125000000, P_GPLL0, 1, 5, 24), 186 { } 187 }; 188 189 static struct clk_rcg2 usb30_master_clk_src = { 190 .cmd_rcgr = 0x03d4, 191 .mnd_width = 8, 192 .hid_width = 5, 193 .parent_map = gcc_xo_gpll0_map, 194 .freq_tbl = ftbl_gcc_usb30_master_clk, 195 .clkr.hw.init = &(struct clk_init_data){ 196 .name = "usb30_master_clk_src", 197 .parent_names = gcc_xo_gpll0, 198 .num_parents = 2, 199 .ops = &clk_rcg2_ops, 200 }, 201 }; 202 203 static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = { 204 F(19200000, P_XO, 1, 0, 0), 205 F(37500000, P_GPLL0, 16, 0, 0), 206 F(50000000, P_GPLL0, 12, 0, 0), 207 { } 208 }; 209 210 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 211 .cmd_rcgr = 0x0660, 212 .hid_width = 5, 213 .parent_map = gcc_xo_gpll0_map, 214 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 215 .clkr.hw.init = &(struct clk_init_data){ 216 .name = "blsp1_qup1_i2c_apps_clk_src", 217 .parent_names = gcc_xo_gpll0, 218 .num_parents = 2, 219 .ops = &clk_rcg2_ops, 220 }, 221 }; 222 223 static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = { 224 F(960000, P_XO, 10, 1, 2), 225 F(4800000, P_XO, 4, 0, 0), 226 F(9600000, P_XO, 2, 0, 0), 227 F(15000000, P_GPLL0, 10, 1, 4), 228 F(19200000, P_XO, 1, 0, 0), 229 F(25000000, P_GPLL0, 12, 1, 2), 230 F(50000000, P_GPLL0, 12, 0, 0), 231 { } 232 }; 233 234 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 235 .cmd_rcgr = 0x064c, 236 .mnd_width = 8, 237 .hid_width = 5, 238 .parent_map = gcc_xo_gpll0_map, 239 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 240 .clkr.hw.init = &(struct clk_init_data){ 241 .name = "blsp1_qup1_spi_apps_clk_src", 242 .parent_names = gcc_xo_gpll0, 243 .num_parents = 2, 244 .ops = &clk_rcg2_ops, 245 }, 246 }; 247 248 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 249 .cmd_rcgr = 0x06e0, 250 .hid_width = 5, 251 .parent_map = gcc_xo_gpll0_map, 252 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 253 .clkr.hw.init = &(struct clk_init_data){ 254 .name = "blsp1_qup2_i2c_apps_clk_src", 255 .parent_names = gcc_xo_gpll0, 256 .num_parents = 2, 257 .ops = &clk_rcg2_ops, 258 }, 259 }; 260 261 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 262 .cmd_rcgr = 0x06cc, 263 .mnd_width = 8, 264 .hid_width = 5, 265 .parent_map = gcc_xo_gpll0_map, 266 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 267 .clkr.hw.init = &(struct clk_init_data){ 268 .name = "blsp1_qup2_spi_apps_clk_src", 269 .parent_names = gcc_xo_gpll0, 270 .num_parents = 2, 271 .ops = &clk_rcg2_ops, 272 }, 273 }; 274 275 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 276 .cmd_rcgr = 0x0760, 277 .hid_width = 5, 278 .parent_map = gcc_xo_gpll0_map, 279 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 280 .clkr.hw.init = &(struct clk_init_data){ 281 .name = "blsp1_qup3_i2c_apps_clk_src", 282 .parent_names = gcc_xo_gpll0, 283 .num_parents = 2, 284 .ops = &clk_rcg2_ops, 285 }, 286 }; 287 288 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 289 .cmd_rcgr = 0x074c, 290 .mnd_width = 8, 291 .hid_width = 5, 292 .parent_map = gcc_xo_gpll0_map, 293 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 294 .clkr.hw.init = &(struct clk_init_data){ 295 .name = "blsp1_qup3_spi_apps_clk_src", 296 .parent_names = gcc_xo_gpll0, 297 .num_parents = 2, 298 .ops = &clk_rcg2_ops, 299 }, 300 }; 301 302 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 303 .cmd_rcgr = 0x07e0, 304 .hid_width = 5, 305 .parent_map = gcc_xo_gpll0_map, 306 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 307 .clkr.hw.init = &(struct clk_init_data){ 308 .name = "blsp1_qup4_i2c_apps_clk_src", 309 .parent_names = gcc_xo_gpll0, 310 .num_parents = 2, 311 .ops = &clk_rcg2_ops, 312 }, 313 }; 314 315 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 316 .cmd_rcgr = 0x07cc, 317 .mnd_width = 8, 318 .hid_width = 5, 319 .parent_map = gcc_xo_gpll0_map, 320 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 321 .clkr.hw.init = &(struct clk_init_data){ 322 .name = "blsp1_qup4_spi_apps_clk_src", 323 .parent_names = gcc_xo_gpll0, 324 .num_parents = 2, 325 .ops = &clk_rcg2_ops, 326 }, 327 }; 328 329 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 330 .cmd_rcgr = 0x0860, 331 .hid_width = 5, 332 .parent_map = gcc_xo_gpll0_map, 333 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 334 .clkr.hw.init = &(struct clk_init_data){ 335 .name = "blsp1_qup5_i2c_apps_clk_src", 336 .parent_names = gcc_xo_gpll0, 337 .num_parents = 2, 338 .ops = &clk_rcg2_ops, 339 }, 340 }; 341 342 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 343 .cmd_rcgr = 0x084c, 344 .mnd_width = 8, 345 .hid_width = 5, 346 .parent_map = gcc_xo_gpll0_map, 347 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 348 .clkr.hw.init = &(struct clk_init_data){ 349 .name = "blsp1_qup5_spi_apps_clk_src", 350 .parent_names = gcc_xo_gpll0, 351 .num_parents = 2, 352 .ops = &clk_rcg2_ops, 353 }, 354 }; 355 356 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 357 .cmd_rcgr = 0x08e0, 358 .hid_width = 5, 359 .parent_map = gcc_xo_gpll0_map, 360 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 361 .clkr.hw.init = &(struct clk_init_data){ 362 .name = "blsp1_qup6_i2c_apps_clk_src", 363 .parent_names = gcc_xo_gpll0, 364 .num_parents = 2, 365 .ops = &clk_rcg2_ops, 366 }, 367 }; 368 369 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 370 .cmd_rcgr = 0x08cc, 371 .mnd_width = 8, 372 .hid_width = 5, 373 .parent_map = gcc_xo_gpll0_map, 374 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 375 .clkr.hw.init = &(struct clk_init_data){ 376 .name = "blsp1_qup6_spi_apps_clk_src", 377 .parent_names = gcc_xo_gpll0, 378 .num_parents = 2, 379 .ops = &clk_rcg2_ops, 380 }, 381 }; 382 383 static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = { 384 F(3686400, P_GPLL0, 1, 96, 15625), 385 F(7372800, P_GPLL0, 1, 192, 15625), 386 F(14745600, P_GPLL0, 1, 384, 15625), 387 F(16000000, P_GPLL0, 5, 2, 15), 388 F(19200000, P_XO, 1, 0, 0), 389 F(24000000, P_GPLL0, 5, 1, 5), 390 F(32000000, P_GPLL0, 1, 4, 75), 391 F(40000000, P_GPLL0, 15, 0, 0), 392 F(46400000, P_GPLL0, 1, 29, 375), 393 F(48000000, P_GPLL0, 12.5, 0, 0), 394 F(51200000, P_GPLL0, 1, 32, 375), 395 F(56000000, P_GPLL0, 1, 7, 75), 396 F(58982400, P_GPLL0, 1, 1536, 15625), 397 F(60000000, P_GPLL0, 10, 0, 0), 398 F(63160000, P_GPLL0, 9.5, 0, 0), 399 { } 400 }; 401 402 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 403 .cmd_rcgr = 0x068c, 404 .mnd_width = 16, 405 .hid_width = 5, 406 .parent_map = gcc_xo_gpll0_map, 407 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 408 .clkr.hw.init = &(struct clk_init_data){ 409 .name = "blsp1_uart1_apps_clk_src", 410 .parent_names = gcc_xo_gpll0, 411 .num_parents = 2, 412 .ops = &clk_rcg2_ops, 413 }, 414 }; 415 416 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 417 .cmd_rcgr = 0x070c, 418 .mnd_width = 16, 419 .hid_width = 5, 420 .parent_map = gcc_xo_gpll0_map, 421 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 422 .clkr.hw.init = &(struct clk_init_data){ 423 .name = "blsp1_uart2_apps_clk_src", 424 .parent_names = gcc_xo_gpll0, 425 .num_parents = 2, 426 .ops = &clk_rcg2_ops, 427 }, 428 }; 429 430 static struct clk_rcg2 blsp1_uart3_apps_clk_src = { 431 .cmd_rcgr = 0x078c, 432 .mnd_width = 16, 433 .hid_width = 5, 434 .parent_map = gcc_xo_gpll0_map, 435 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 436 .clkr.hw.init = &(struct clk_init_data){ 437 .name = "blsp1_uart3_apps_clk_src", 438 .parent_names = gcc_xo_gpll0, 439 .num_parents = 2, 440 .ops = &clk_rcg2_ops, 441 }, 442 }; 443 444 static struct clk_rcg2 blsp1_uart4_apps_clk_src = { 445 .cmd_rcgr = 0x080c, 446 .mnd_width = 16, 447 .hid_width = 5, 448 .parent_map = gcc_xo_gpll0_map, 449 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 450 .clkr.hw.init = &(struct clk_init_data){ 451 .name = "blsp1_uart4_apps_clk_src", 452 .parent_names = gcc_xo_gpll0, 453 .num_parents = 2, 454 .ops = &clk_rcg2_ops, 455 }, 456 }; 457 458 static struct clk_rcg2 blsp1_uart5_apps_clk_src = { 459 .cmd_rcgr = 0x088c, 460 .mnd_width = 16, 461 .hid_width = 5, 462 .parent_map = gcc_xo_gpll0_map, 463 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 464 .clkr.hw.init = &(struct clk_init_data){ 465 .name = "blsp1_uart5_apps_clk_src", 466 .parent_names = gcc_xo_gpll0, 467 .num_parents = 2, 468 .ops = &clk_rcg2_ops, 469 }, 470 }; 471 472 static struct clk_rcg2 blsp1_uart6_apps_clk_src = { 473 .cmd_rcgr = 0x090c, 474 .mnd_width = 16, 475 .hid_width = 5, 476 .parent_map = gcc_xo_gpll0_map, 477 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 478 .clkr.hw.init = &(struct clk_init_data){ 479 .name = "blsp1_uart6_apps_clk_src", 480 .parent_names = gcc_xo_gpll0, 481 .num_parents = 2, 482 .ops = &clk_rcg2_ops, 483 }, 484 }; 485 486 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { 487 .cmd_rcgr = 0x09a0, 488 .hid_width = 5, 489 .parent_map = gcc_xo_gpll0_map, 490 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 491 .clkr.hw.init = &(struct clk_init_data){ 492 .name = "blsp2_qup1_i2c_apps_clk_src", 493 .parent_names = gcc_xo_gpll0, 494 .num_parents = 2, 495 .ops = &clk_rcg2_ops, 496 }, 497 }; 498 499 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { 500 .cmd_rcgr = 0x098c, 501 .mnd_width = 8, 502 .hid_width = 5, 503 .parent_map = gcc_xo_gpll0_map, 504 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 505 .clkr.hw.init = &(struct clk_init_data){ 506 .name = "blsp2_qup1_spi_apps_clk_src", 507 .parent_names = gcc_xo_gpll0, 508 .num_parents = 2, 509 .ops = &clk_rcg2_ops, 510 }, 511 }; 512 513 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { 514 .cmd_rcgr = 0x0a20, 515 .hid_width = 5, 516 .parent_map = gcc_xo_gpll0_map, 517 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 518 .clkr.hw.init = &(struct clk_init_data){ 519 .name = "blsp2_qup2_i2c_apps_clk_src", 520 .parent_names = gcc_xo_gpll0, 521 .num_parents = 2, 522 .ops = &clk_rcg2_ops, 523 }, 524 }; 525 526 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { 527 .cmd_rcgr = 0x0a0c, 528 .mnd_width = 8, 529 .hid_width = 5, 530 .parent_map = gcc_xo_gpll0_map, 531 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 532 .clkr.hw.init = &(struct clk_init_data){ 533 .name = "blsp2_qup2_spi_apps_clk_src", 534 .parent_names = gcc_xo_gpll0, 535 .num_parents = 2, 536 .ops = &clk_rcg2_ops, 537 }, 538 }; 539 540 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { 541 .cmd_rcgr = 0x0aa0, 542 .hid_width = 5, 543 .parent_map = gcc_xo_gpll0_map, 544 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 545 .clkr.hw.init = &(struct clk_init_data){ 546 .name = "blsp2_qup3_i2c_apps_clk_src", 547 .parent_names = gcc_xo_gpll0, 548 .num_parents = 2, 549 .ops = &clk_rcg2_ops, 550 }, 551 }; 552 553 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { 554 .cmd_rcgr = 0x0a8c, 555 .mnd_width = 8, 556 .hid_width = 5, 557 .parent_map = gcc_xo_gpll0_map, 558 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 559 .clkr.hw.init = &(struct clk_init_data){ 560 .name = "blsp2_qup3_spi_apps_clk_src", 561 .parent_names = gcc_xo_gpll0, 562 .num_parents = 2, 563 .ops = &clk_rcg2_ops, 564 }, 565 }; 566 567 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { 568 .cmd_rcgr = 0x0b20, 569 .hid_width = 5, 570 .parent_map = gcc_xo_gpll0_map, 571 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 572 .clkr.hw.init = &(struct clk_init_data){ 573 .name = "blsp2_qup4_i2c_apps_clk_src", 574 .parent_names = gcc_xo_gpll0, 575 .num_parents = 2, 576 .ops = &clk_rcg2_ops, 577 }, 578 }; 579 580 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { 581 .cmd_rcgr = 0x0b0c, 582 .mnd_width = 8, 583 .hid_width = 5, 584 .parent_map = gcc_xo_gpll0_map, 585 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 586 .clkr.hw.init = &(struct clk_init_data){ 587 .name = "blsp2_qup4_spi_apps_clk_src", 588 .parent_names = gcc_xo_gpll0, 589 .num_parents = 2, 590 .ops = &clk_rcg2_ops, 591 }, 592 }; 593 594 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { 595 .cmd_rcgr = 0x0ba0, 596 .hid_width = 5, 597 .parent_map = gcc_xo_gpll0_map, 598 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 599 .clkr.hw.init = &(struct clk_init_data){ 600 .name = "blsp2_qup5_i2c_apps_clk_src", 601 .parent_names = gcc_xo_gpll0, 602 .num_parents = 2, 603 .ops = &clk_rcg2_ops, 604 }, 605 }; 606 607 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { 608 .cmd_rcgr = 0x0b8c, 609 .mnd_width = 8, 610 .hid_width = 5, 611 .parent_map = gcc_xo_gpll0_map, 612 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 613 .clkr.hw.init = &(struct clk_init_data){ 614 .name = "blsp2_qup5_spi_apps_clk_src", 615 .parent_names = gcc_xo_gpll0, 616 .num_parents = 2, 617 .ops = &clk_rcg2_ops, 618 }, 619 }; 620 621 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { 622 .cmd_rcgr = 0x0c20, 623 .hid_width = 5, 624 .parent_map = gcc_xo_gpll0_map, 625 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 626 .clkr.hw.init = &(struct clk_init_data){ 627 .name = "blsp2_qup6_i2c_apps_clk_src", 628 .parent_names = gcc_xo_gpll0, 629 .num_parents = 2, 630 .ops = &clk_rcg2_ops, 631 }, 632 }; 633 634 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { 635 .cmd_rcgr = 0x0c0c, 636 .mnd_width = 8, 637 .hid_width = 5, 638 .parent_map = gcc_xo_gpll0_map, 639 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 640 .clkr.hw.init = &(struct clk_init_data){ 641 .name = "blsp2_qup6_spi_apps_clk_src", 642 .parent_names = gcc_xo_gpll0, 643 .num_parents = 2, 644 .ops = &clk_rcg2_ops, 645 }, 646 }; 647 648 static struct clk_rcg2 blsp2_uart1_apps_clk_src = { 649 .cmd_rcgr = 0x09cc, 650 .mnd_width = 16, 651 .hid_width = 5, 652 .parent_map = gcc_xo_gpll0_map, 653 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 654 .clkr.hw.init = &(struct clk_init_data){ 655 .name = "blsp2_uart1_apps_clk_src", 656 .parent_names = gcc_xo_gpll0, 657 .num_parents = 2, 658 .ops = &clk_rcg2_ops, 659 }, 660 }; 661 662 static struct clk_rcg2 blsp2_uart2_apps_clk_src = { 663 .cmd_rcgr = 0x0a4c, 664 .mnd_width = 16, 665 .hid_width = 5, 666 .parent_map = gcc_xo_gpll0_map, 667 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 668 .clkr.hw.init = &(struct clk_init_data){ 669 .name = "blsp2_uart2_apps_clk_src", 670 .parent_names = gcc_xo_gpll0, 671 .num_parents = 2, 672 .ops = &clk_rcg2_ops, 673 }, 674 }; 675 676 static struct clk_rcg2 blsp2_uart3_apps_clk_src = { 677 .cmd_rcgr = 0x0acc, 678 .mnd_width = 16, 679 .hid_width = 5, 680 .parent_map = gcc_xo_gpll0_map, 681 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 682 .clkr.hw.init = &(struct clk_init_data){ 683 .name = "blsp2_uart3_apps_clk_src", 684 .parent_names = gcc_xo_gpll0, 685 .num_parents = 2, 686 .ops = &clk_rcg2_ops, 687 }, 688 }; 689 690 static struct clk_rcg2 blsp2_uart4_apps_clk_src = { 691 .cmd_rcgr = 0x0b4c, 692 .mnd_width = 16, 693 .hid_width = 5, 694 .parent_map = gcc_xo_gpll0_map, 695 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 696 .clkr.hw.init = &(struct clk_init_data){ 697 .name = "blsp2_uart4_apps_clk_src", 698 .parent_names = gcc_xo_gpll0, 699 .num_parents = 2, 700 .ops = &clk_rcg2_ops, 701 }, 702 }; 703 704 static struct clk_rcg2 blsp2_uart5_apps_clk_src = { 705 .cmd_rcgr = 0x0bcc, 706 .mnd_width = 16, 707 .hid_width = 5, 708 .parent_map = gcc_xo_gpll0_map, 709 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 710 .clkr.hw.init = &(struct clk_init_data){ 711 .name = "blsp2_uart5_apps_clk_src", 712 .parent_names = gcc_xo_gpll0, 713 .num_parents = 2, 714 .ops = &clk_rcg2_ops, 715 }, 716 }; 717 718 static struct clk_rcg2 blsp2_uart6_apps_clk_src = { 719 .cmd_rcgr = 0x0c4c, 720 .mnd_width = 16, 721 .hid_width = 5, 722 .parent_map = gcc_xo_gpll0_map, 723 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 724 .clkr.hw.init = &(struct clk_init_data){ 725 .name = "blsp2_uart6_apps_clk_src", 726 .parent_names = gcc_xo_gpll0, 727 .num_parents = 2, 728 .ops = &clk_rcg2_ops, 729 }, 730 }; 731 732 static const struct freq_tbl ftbl_gcc_ce1_clk[] = { 733 F(50000000, P_GPLL0, 12, 0, 0), 734 F(75000000, P_GPLL0, 8, 0, 0), 735 F(100000000, P_GPLL0, 6, 0, 0), 736 F(150000000, P_GPLL0, 4, 0, 0), 737 { } 738 }; 739 740 static struct clk_rcg2 ce1_clk_src = { 741 .cmd_rcgr = 0x1050, 742 .hid_width = 5, 743 .parent_map = gcc_xo_gpll0_map, 744 .freq_tbl = ftbl_gcc_ce1_clk, 745 .clkr.hw.init = &(struct clk_init_data){ 746 .name = "ce1_clk_src", 747 .parent_names = gcc_xo_gpll0, 748 .num_parents = 2, 749 .ops = &clk_rcg2_ops, 750 }, 751 }; 752 753 static const struct freq_tbl ftbl_gcc_ce2_clk[] = { 754 F(50000000, P_GPLL0, 12, 0, 0), 755 F(75000000, P_GPLL0, 8, 0, 0), 756 F(100000000, P_GPLL0, 6, 0, 0), 757 F(150000000, P_GPLL0, 4, 0, 0), 758 { } 759 }; 760 761 static struct clk_rcg2 ce2_clk_src = { 762 .cmd_rcgr = 0x1090, 763 .hid_width = 5, 764 .parent_map = gcc_xo_gpll0_map, 765 .freq_tbl = ftbl_gcc_ce2_clk, 766 .clkr.hw.init = &(struct clk_init_data){ 767 .name = "ce2_clk_src", 768 .parent_names = gcc_xo_gpll0, 769 .num_parents = 2, 770 .ops = &clk_rcg2_ops, 771 }, 772 }; 773 774 static const struct freq_tbl ftbl_gcc_gp_clk[] = { 775 F(4800000, P_XO, 4, 0, 0), 776 F(6000000, P_GPLL0, 10, 1, 10), 777 F(6750000, P_GPLL0, 1, 1, 89), 778 F(8000000, P_GPLL0, 15, 1, 5), 779 F(9600000, P_XO, 2, 0, 0), 780 F(16000000, P_GPLL0, 1, 2, 75), 781 F(19200000, P_XO, 1, 0, 0), 782 F(24000000, P_GPLL0, 5, 1, 5), 783 { } 784 }; 785 786 787 static struct clk_rcg2 gp1_clk_src = { 788 .cmd_rcgr = 0x1904, 789 .mnd_width = 8, 790 .hid_width = 5, 791 .parent_map = gcc_xo_gpll0_map, 792 .freq_tbl = ftbl_gcc_gp_clk, 793 .clkr.hw.init = &(struct clk_init_data){ 794 .name = "gp1_clk_src", 795 .parent_names = gcc_xo_gpll0, 796 .num_parents = 2, 797 .ops = &clk_rcg2_ops, 798 }, 799 }; 800 801 static struct clk_rcg2 gp2_clk_src = { 802 .cmd_rcgr = 0x1944, 803 .mnd_width = 8, 804 .hid_width = 5, 805 .parent_map = gcc_xo_gpll0_map, 806 .freq_tbl = ftbl_gcc_gp_clk, 807 .clkr.hw.init = &(struct clk_init_data){ 808 .name = "gp2_clk_src", 809 .parent_names = gcc_xo_gpll0, 810 .num_parents = 2, 811 .ops = &clk_rcg2_ops, 812 }, 813 }; 814 815 static struct clk_rcg2 gp3_clk_src = { 816 .cmd_rcgr = 0x1984, 817 .mnd_width = 8, 818 .hid_width = 5, 819 .parent_map = gcc_xo_gpll0_map, 820 .freq_tbl = ftbl_gcc_gp_clk, 821 .clkr.hw.init = &(struct clk_init_data){ 822 .name = "gp3_clk_src", 823 .parent_names = gcc_xo_gpll0, 824 .num_parents = 2, 825 .ops = &clk_rcg2_ops, 826 }, 827 }; 828 829 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = { 830 F(60000000, P_GPLL0, 10, 0, 0), 831 { } 832 }; 833 834 static struct clk_rcg2 pdm2_clk_src = { 835 .cmd_rcgr = 0x0cd0, 836 .hid_width = 5, 837 .parent_map = gcc_xo_gpll0_map, 838 .freq_tbl = ftbl_gcc_pdm2_clk, 839 .clkr.hw.init = &(struct clk_init_data){ 840 .name = "pdm2_clk_src", 841 .parent_names = gcc_xo_gpll0, 842 .num_parents = 2, 843 .ops = &clk_rcg2_ops, 844 }, 845 }; 846 847 static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = { 848 F(144000, P_XO, 16, 3, 25), 849 F(400000, P_XO, 12, 1, 4), 850 F(20000000, P_GPLL0, 15, 1, 2), 851 F(25000000, P_GPLL0, 12, 1, 2), 852 F(50000000, P_GPLL0, 12, 0, 0), 853 F(100000000, P_GPLL0, 6, 0, 0), 854 F(200000000, P_GPLL0, 3, 0, 0), 855 { } 856 }; 857 858 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_pro[] = { 859 F(144000, P_XO, 16, 3, 25), 860 F(400000, P_XO, 12, 1, 4), 861 F(20000000, P_GPLL0, 15, 1, 2), 862 F(25000000, P_GPLL0, 12, 1, 2), 863 F(50000000, P_GPLL0, 12, 0, 0), 864 F(100000000, P_GPLL0, 6, 0, 0), 865 F(192000000, P_GPLL4, 4, 0, 0), 866 F(200000000, P_GPLL0, 3, 0, 0), 867 F(384000000, P_GPLL4, 2, 0, 0), 868 { } 869 }; 870 871 static struct clk_init_data sdcc1_apps_clk_src_init = { 872 .name = "sdcc1_apps_clk_src", 873 .parent_names = gcc_xo_gpll0, 874 .num_parents = 2, 875 .ops = &clk_rcg2_ops, 876 }; 877 878 static struct clk_rcg2 sdcc1_apps_clk_src = { 879 .cmd_rcgr = 0x04d0, 880 .mnd_width = 8, 881 .hid_width = 5, 882 .parent_map = gcc_xo_gpll0_map, 883 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, 884 .clkr.hw.init = &sdcc1_apps_clk_src_init, 885 }; 886 887 static struct clk_rcg2 sdcc2_apps_clk_src = { 888 .cmd_rcgr = 0x0510, 889 .mnd_width = 8, 890 .hid_width = 5, 891 .parent_map = gcc_xo_gpll0_map, 892 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, 893 .clkr.hw.init = &(struct clk_init_data){ 894 .name = "sdcc2_apps_clk_src", 895 .parent_names = gcc_xo_gpll0, 896 .num_parents = 2, 897 .ops = &clk_rcg2_ops, 898 }, 899 }; 900 901 static struct clk_rcg2 sdcc3_apps_clk_src = { 902 .cmd_rcgr = 0x0550, 903 .mnd_width = 8, 904 .hid_width = 5, 905 .parent_map = gcc_xo_gpll0_map, 906 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, 907 .clkr.hw.init = &(struct clk_init_data){ 908 .name = "sdcc3_apps_clk_src", 909 .parent_names = gcc_xo_gpll0, 910 .num_parents = 2, 911 .ops = &clk_rcg2_ops, 912 }, 913 }; 914 915 static struct clk_rcg2 sdcc4_apps_clk_src = { 916 .cmd_rcgr = 0x0590, 917 .mnd_width = 8, 918 .hid_width = 5, 919 .parent_map = gcc_xo_gpll0_map, 920 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, 921 .clkr.hw.init = &(struct clk_init_data){ 922 .name = "sdcc4_apps_clk_src", 923 .parent_names = gcc_xo_gpll0, 924 .num_parents = 2, 925 .ops = &clk_rcg2_ops, 926 }, 927 }; 928 929 static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = { 930 F(105000, P_XO, 2, 1, 91), 931 { } 932 }; 933 934 static struct clk_rcg2 tsif_ref_clk_src = { 935 .cmd_rcgr = 0x0d90, 936 .mnd_width = 8, 937 .hid_width = 5, 938 .parent_map = gcc_xo_gpll0_map, 939 .freq_tbl = ftbl_gcc_tsif_ref_clk, 940 .clkr.hw.init = &(struct clk_init_data){ 941 .name = "tsif_ref_clk_src", 942 .parent_names = gcc_xo_gpll0, 943 .num_parents = 2, 944 .ops = &clk_rcg2_ops, 945 }, 946 }; 947 948 static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = { 949 F(60000000, P_GPLL0, 10, 0, 0), 950 { } 951 }; 952 953 static struct clk_rcg2 usb30_mock_utmi_clk_src = { 954 .cmd_rcgr = 0x03e8, 955 .hid_width = 5, 956 .parent_map = gcc_xo_gpll0_map, 957 .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk, 958 .clkr.hw.init = &(struct clk_init_data){ 959 .name = "usb30_mock_utmi_clk_src", 960 .parent_names = gcc_xo_gpll0, 961 .num_parents = 2, 962 .ops = &clk_rcg2_ops, 963 }, 964 }; 965 966 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { 967 F(60000000, P_GPLL0, 10, 0, 0), 968 F(75000000, P_GPLL0, 8, 0, 0), 969 { } 970 }; 971 972 static struct clk_rcg2 usb_hs_system_clk_src = { 973 .cmd_rcgr = 0x0490, 974 .hid_width = 5, 975 .parent_map = gcc_xo_gpll0_map, 976 .freq_tbl = ftbl_gcc_usb_hs_system_clk, 977 .clkr.hw.init = &(struct clk_init_data){ 978 .name = "usb_hs_system_clk_src", 979 .parent_names = gcc_xo_gpll0, 980 .num_parents = 2, 981 .ops = &clk_rcg2_ops, 982 }, 983 }; 984 985 static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = { 986 F(480000000, P_GPLL1, 1, 0, 0), 987 { } 988 }; 989 990 static const struct parent_map usb_hsic_clk_src_map[] = { 991 { P_XO, 0 }, 992 { P_GPLL1, 4 } 993 }; 994 995 static struct clk_rcg2 usb_hsic_clk_src = { 996 .cmd_rcgr = 0x0440, 997 .hid_width = 5, 998 .parent_map = usb_hsic_clk_src_map, 999 .freq_tbl = ftbl_gcc_usb_hsic_clk, 1000 .clkr.hw.init = &(struct clk_init_data){ 1001 .name = "usb_hsic_clk_src", 1002 .parent_names = (const char *[]){ 1003 "xo", 1004 "gpll1_vote", 1005 }, 1006 .num_parents = 2, 1007 .ops = &clk_rcg2_ops, 1008 }, 1009 }; 1010 1011 static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = { 1012 F(9600000, P_XO, 2, 0, 0), 1013 { } 1014 }; 1015 1016 static struct clk_rcg2 usb_hsic_io_cal_clk_src = { 1017 .cmd_rcgr = 0x0458, 1018 .hid_width = 5, 1019 .parent_map = gcc_xo_gpll0_map, 1020 .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk, 1021 .clkr.hw.init = &(struct clk_init_data){ 1022 .name = "usb_hsic_io_cal_clk_src", 1023 .parent_names = gcc_xo_gpll0, 1024 .num_parents = 1, 1025 .ops = &clk_rcg2_ops, 1026 }, 1027 }; 1028 1029 static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = { 1030 F(60000000, P_GPLL0, 10, 0, 0), 1031 F(75000000, P_GPLL0, 8, 0, 0), 1032 { } 1033 }; 1034 1035 static struct clk_rcg2 usb_hsic_system_clk_src = { 1036 .cmd_rcgr = 0x041c, 1037 .hid_width = 5, 1038 .parent_map = gcc_xo_gpll0_map, 1039 .freq_tbl = ftbl_gcc_usb_hsic_system_clk, 1040 .clkr.hw.init = &(struct clk_init_data){ 1041 .name = "usb_hsic_system_clk_src", 1042 .parent_names = gcc_xo_gpll0, 1043 .num_parents = 2, 1044 .ops = &clk_rcg2_ops, 1045 }, 1046 }; 1047 1048 static struct clk_regmap gcc_mmss_gpll0_clk_src = { 1049 .enable_reg = 0x1484, 1050 .enable_mask = BIT(26), 1051 .hw.init = &(struct clk_init_data){ 1052 .name = "mmss_gpll0_vote", 1053 .parent_names = (const char *[]){ 1054 "gpll0_vote", 1055 }, 1056 .num_parents = 1, 1057 .ops = &clk_branch_simple_ops, 1058 }, 1059 }; 1060 1061 static struct clk_branch gcc_bam_dma_ahb_clk = { 1062 .halt_reg = 0x0d44, 1063 .halt_check = BRANCH_HALT_VOTED, 1064 .clkr = { 1065 .enable_reg = 0x1484, 1066 .enable_mask = BIT(12), 1067 .hw.init = &(struct clk_init_data){ 1068 .name = "gcc_bam_dma_ahb_clk", 1069 .parent_names = (const char *[]){ 1070 "periph_noc_clk_src", 1071 }, 1072 .num_parents = 1, 1073 .ops = &clk_branch2_ops, 1074 }, 1075 }, 1076 }; 1077 1078 static struct clk_branch gcc_blsp1_ahb_clk = { 1079 .halt_reg = 0x05c4, 1080 .halt_check = BRANCH_HALT_VOTED, 1081 .clkr = { 1082 .enable_reg = 0x1484, 1083 .enable_mask = BIT(17), 1084 .hw.init = &(struct clk_init_data){ 1085 .name = "gcc_blsp1_ahb_clk", 1086 .parent_names = (const char *[]){ 1087 "periph_noc_clk_src", 1088 }, 1089 .num_parents = 1, 1090 .ops = &clk_branch2_ops, 1091 }, 1092 }, 1093 }; 1094 1095 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1096 .halt_reg = 0x0648, 1097 .clkr = { 1098 .enable_reg = 0x0648, 1099 .enable_mask = BIT(0), 1100 .hw.init = &(struct clk_init_data){ 1101 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1102 .parent_names = (const char *[]){ 1103 "blsp1_qup1_i2c_apps_clk_src", 1104 }, 1105 .num_parents = 1, 1106 .flags = CLK_SET_RATE_PARENT, 1107 .ops = &clk_branch2_ops, 1108 }, 1109 }, 1110 }; 1111 1112 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1113 .halt_reg = 0x0644, 1114 .clkr = { 1115 .enable_reg = 0x0644, 1116 .enable_mask = BIT(0), 1117 .hw.init = &(struct clk_init_data){ 1118 .name = "gcc_blsp1_qup1_spi_apps_clk", 1119 .parent_names = (const char *[]){ 1120 "blsp1_qup1_spi_apps_clk_src", 1121 }, 1122 .num_parents = 1, 1123 .flags = CLK_SET_RATE_PARENT, 1124 .ops = &clk_branch2_ops, 1125 }, 1126 }, 1127 }; 1128 1129 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1130 .halt_reg = 0x06c8, 1131 .clkr = { 1132 .enable_reg = 0x06c8, 1133 .enable_mask = BIT(0), 1134 .hw.init = &(struct clk_init_data){ 1135 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1136 .parent_names = (const char *[]){ 1137 "blsp1_qup2_i2c_apps_clk_src", 1138 }, 1139 .num_parents = 1, 1140 .flags = CLK_SET_RATE_PARENT, 1141 .ops = &clk_branch2_ops, 1142 }, 1143 }, 1144 }; 1145 1146 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1147 .halt_reg = 0x06c4, 1148 .clkr = { 1149 .enable_reg = 0x06c4, 1150 .enable_mask = BIT(0), 1151 .hw.init = &(struct clk_init_data){ 1152 .name = "gcc_blsp1_qup2_spi_apps_clk", 1153 .parent_names = (const char *[]){ 1154 "blsp1_qup2_spi_apps_clk_src", 1155 }, 1156 .num_parents = 1, 1157 .flags = CLK_SET_RATE_PARENT, 1158 .ops = &clk_branch2_ops, 1159 }, 1160 }, 1161 }; 1162 1163 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1164 .halt_reg = 0x0748, 1165 .clkr = { 1166 .enable_reg = 0x0748, 1167 .enable_mask = BIT(0), 1168 .hw.init = &(struct clk_init_data){ 1169 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1170 .parent_names = (const char *[]){ 1171 "blsp1_qup3_i2c_apps_clk_src", 1172 }, 1173 .num_parents = 1, 1174 .flags = CLK_SET_RATE_PARENT, 1175 .ops = &clk_branch2_ops, 1176 }, 1177 }, 1178 }; 1179 1180 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1181 .halt_reg = 0x0744, 1182 .clkr = { 1183 .enable_reg = 0x0744, 1184 .enable_mask = BIT(0), 1185 .hw.init = &(struct clk_init_data){ 1186 .name = "gcc_blsp1_qup3_spi_apps_clk", 1187 .parent_names = (const char *[]){ 1188 "blsp1_qup3_spi_apps_clk_src", 1189 }, 1190 .num_parents = 1, 1191 .flags = CLK_SET_RATE_PARENT, 1192 .ops = &clk_branch2_ops, 1193 }, 1194 }, 1195 }; 1196 1197 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1198 .halt_reg = 0x07c8, 1199 .clkr = { 1200 .enable_reg = 0x07c8, 1201 .enable_mask = BIT(0), 1202 .hw.init = &(struct clk_init_data){ 1203 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1204 .parent_names = (const char *[]){ 1205 "blsp1_qup4_i2c_apps_clk_src", 1206 }, 1207 .num_parents = 1, 1208 .flags = CLK_SET_RATE_PARENT, 1209 .ops = &clk_branch2_ops, 1210 }, 1211 }, 1212 }; 1213 1214 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1215 .halt_reg = 0x07c4, 1216 .clkr = { 1217 .enable_reg = 0x07c4, 1218 .enable_mask = BIT(0), 1219 .hw.init = &(struct clk_init_data){ 1220 .name = "gcc_blsp1_qup4_spi_apps_clk", 1221 .parent_names = (const char *[]){ 1222 "blsp1_qup4_spi_apps_clk_src", 1223 }, 1224 .num_parents = 1, 1225 .flags = CLK_SET_RATE_PARENT, 1226 .ops = &clk_branch2_ops, 1227 }, 1228 }, 1229 }; 1230 1231 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 1232 .halt_reg = 0x0848, 1233 .clkr = { 1234 .enable_reg = 0x0848, 1235 .enable_mask = BIT(0), 1236 .hw.init = &(struct clk_init_data){ 1237 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1238 .parent_names = (const char *[]){ 1239 "blsp1_qup5_i2c_apps_clk_src", 1240 }, 1241 .num_parents = 1, 1242 .flags = CLK_SET_RATE_PARENT, 1243 .ops = &clk_branch2_ops, 1244 }, 1245 }, 1246 }; 1247 1248 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 1249 .halt_reg = 0x0844, 1250 .clkr = { 1251 .enable_reg = 0x0844, 1252 .enable_mask = BIT(0), 1253 .hw.init = &(struct clk_init_data){ 1254 .name = "gcc_blsp1_qup5_spi_apps_clk", 1255 .parent_names = (const char *[]){ 1256 "blsp1_qup5_spi_apps_clk_src", 1257 }, 1258 .num_parents = 1, 1259 .flags = CLK_SET_RATE_PARENT, 1260 .ops = &clk_branch2_ops, 1261 }, 1262 }, 1263 }; 1264 1265 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 1266 .halt_reg = 0x08c8, 1267 .clkr = { 1268 .enable_reg = 0x08c8, 1269 .enable_mask = BIT(0), 1270 .hw.init = &(struct clk_init_data){ 1271 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1272 .parent_names = (const char *[]){ 1273 "blsp1_qup6_i2c_apps_clk_src", 1274 }, 1275 .num_parents = 1, 1276 .flags = CLK_SET_RATE_PARENT, 1277 .ops = &clk_branch2_ops, 1278 }, 1279 }, 1280 }; 1281 1282 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 1283 .halt_reg = 0x08c4, 1284 .clkr = { 1285 .enable_reg = 0x08c4, 1286 .enable_mask = BIT(0), 1287 .hw.init = &(struct clk_init_data){ 1288 .name = "gcc_blsp1_qup6_spi_apps_clk", 1289 .parent_names = (const char *[]){ 1290 "blsp1_qup6_spi_apps_clk_src", 1291 }, 1292 .num_parents = 1, 1293 .flags = CLK_SET_RATE_PARENT, 1294 .ops = &clk_branch2_ops, 1295 }, 1296 }, 1297 }; 1298 1299 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1300 .halt_reg = 0x0684, 1301 .clkr = { 1302 .enable_reg = 0x0684, 1303 .enable_mask = BIT(0), 1304 .hw.init = &(struct clk_init_data){ 1305 .name = "gcc_blsp1_uart1_apps_clk", 1306 .parent_names = (const char *[]){ 1307 "blsp1_uart1_apps_clk_src", 1308 }, 1309 .num_parents = 1, 1310 .flags = CLK_SET_RATE_PARENT, 1311 .ops = &clk_branch2_ops, 1312 }, 1313 }, 1314 }; 1315 1316 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1317 .halt_reg = 0x0704, 1318 .clkr = { 1319 .enable_reg = 0x0704, 1320 .enable_mask = BIT(0), 1321 .hw.init = &(struct clk_init_data){ 1322 .name = "gcc_blsp1_uart2_apps_clk", 1323 .parent_names = (const char *[]){ 1324 "blsp1_uart2_apps_clk_src", 1325 }, 1326 .num_parents = 1, 1327 .flags = CLK_SET_RATE_PARENT, 1328 .ops = &clk_branch2_ops, 1329 }, 1330 }, 1331 }; 1332 1333 static struct clk_branch gcc_blsp1_uart3_apps_clk = { 1334 .halt_reg = 0x0784, 1335 .clkr = { 1336 .enable_reg = 0x0784, 1337 .enable_mask = BIT(0), 1338 .hw.init = &(struct clk_init_data){ 1339 .name = "gcc_blsp1_uart3_apps_clk", 1340 .parent_names = (const char *[]){ 1341 "blsp1_uart3_apps_clk_src", 1342 }, 1343 .num_parents = 1, 1344 .flags = CLK_SET_RATE_PARENT, 1345 .ops = &clk_branch2_ops, 1346 }, 1347 }, 1348 }; 1349 1350 static struct clk_branch gcc_blsp1_uart4_apps_clk = { 1351 .halt_reg = 0x0804, 1352 .clkr = { 1353 .enable_reg = 0x0804, 1354 .enable_mask = BIT(0), 1355 .hw.init = &(struct clk_init_data){ 1356 .name = "gcc_blsp1_uart4_apps_clk", 1357 .parent_names = (const char *[]){ 1358 "blsp1_uart4_apps_clk_src", 1359 }, 1360 .num_parents = 1, 1361 .flags = CLK_SET_RATE_PARENT, 1362 .ops = &clk_branch2_ops, 1363 }, 1364 }, 1365 }; 1366 1367 static struct clk_branch gcc_blsp1_uart5_apps_clk = { 1368 .halt_reg = 0x0884, 1369 .clkr = { 1370 .enable_reg = 0x0884, 1371 .enable_mask = BIT(0), 1372 .hw.init = &(struct clk_init_data){ 1373 .name = "gcc_blsp1_uart5_apps_clk", 1374 .parent_names = (const char *[]){ 1375 "blsp1_uart5_apps_clk_src", 1376 }, 1377 .num_parents = 1, 1378 .flags = CLK_SET_RATE_PARENT, 1379 .ops = &clk_branch2_ops, 1380 }, 1381 }, 1382 }; 1383 1384 static struct clk_branch gcc_blsp1_uart6_apps_clk = { 1385 .halt_reg = 0x0904, 1386 .clkr = { 1387 .enable_reg = 0x0904, 1388 .enable_mask = BIT(0), 1389 .hw.init = &(struct clk_init_data){ 1390 .name = "gcc_blsp1_uart6_apps_clk", 1391 .parent_names = (const char *[]){ 1392 "blsp1_uart6_apps_clk_src", 1393 }, 1394 .num_parents = 1, 1395 .flags = CLK_SET_RATE_PARENT, 1396 .ops = &clk_branch2_ops, 1397 }, 1398 }, 1399 }; 1400 1401 static struct clk_branch gcc_blsp2_ahb_clk = { 1402 .halt_reg = 0x0944, 1403 .halt_check = BRANCH_HALT_VOTED, 1404 .clkr = { 1405 .enable_reg = 0x1484, 1406 .enable_mask = BIT(15), 1407 .hw.init = &(struct clk_init_data){ 1408 .name = "gcc_blsp2_ahb_clk", 1409 .parent_names = (const char *[]){ 1410 "periph_noc_clk_src", 1411 }, 1412 .num_parents = 1, 1413 .ops = &clk_branch2_ops, 1414 }, 1415 }, 1416 }; 1417 1418 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { 1419 .halt_reg = 0x0988, 1420 .clkr = { 1421 .enable_reg = 0x0988, 1422 .enable_mask = BIT(0), 1423 .hw.init = &(struct clk_init_data){ 1424 .name = "gcc_blsp2_qup1_i2c_apps_clk", 1425 .parent_names = (const char *[]){ 1426 "blsp2_qup1_i2c_apps_clk_src", 1427 }, 1428 .num_parents = 1, 1429 .flags = CLK_SET_RATE_PARENT, 1430 .ops = &clk_branch2_ops, 1431 }, 1432 }, 1433 }; 1434 1435 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { 1436 .halt_reg = 0x0984, 1437 .clkr = { 1438 .enable_reg = 0x0984, 1439 .enable_mask = BIT(0), 1440 .hw.init = &(struct clk_init_data){ 1441 .name = "gcc_blsp2_qup1_spi_apps_clk", 1442 .parent_names = (const char *[]){ 1443 "blsp2_qup1_spi_apps_clk_src", 1444 }, 1445 .num_parents = 1, 1446 .flags = CLK_SET_RATE_PARENT, 1447 .ops = &clk_branch2_ops, 1448 }, 1449 }, 1450 }; 1451 1452 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { 1453 .halt_reg = 0x0a08, 1454 .clkr = { 1455 .enable_reg = 0x0a08, 1456 .enable_mask = BIT(0), 1457 .hw.init = &(struct clk_init_data){ 1458 .name = "gcc_blsp2_qup2_i2c_apps_clk", 1459 .parent_names = (const char *[]){ 1460 "blsp2_qup2_i2c_apps_clk_src", 1461 }, 1462 .num_parents = 1, 1463 .flags = CLK_SET_RATE_PARENT, 1464 .ops = &clk_branch2_ops, 1465 }, 1466 }, 1467 }; 1468 1469 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { 1470 .halt_reg = 0x0a04, 1471 .clkr = { 1472 .enable_reg = 0x0a04, 1473 .enable_mask = BIT(0), 1474 .hw.init = &(struct clk_init_data){ 1475 .name = "gcc_blsp2_qup2_spi_apps_clk", 1476 .parent_names = (const char *[]){ 1477 "blsp2_qup2_spi_apps_clk_src", 1478 }, 1479 .num_parents = 1, 1480 .flags = CLK_SET_RATE_PARENT, 1481 .ops = &clk_branch2_ops, 1482 }, 1483 }, 1484 }; 1485 1486 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { 1487 .halt_reg = 0x0a88, 1488 .clkr = { 1489 .enable_reg = 0x0a88, 1490 .enable_mask = BIT(0), 1491 .hw.init = &(struct clk_init_data){ 1492 .name = "gcc_blsp2_qup3_i2c_apps_clk", 1493 .parent_names = (const char *[]){ 1494 "blsp2_qup3_i2c_apps_clk_src", 1495 }, 1496 .num_parents = 1, 1497 .flags = CLK_SET_RATE_PARENT, 1498 .ops = &clk_branch2_ops, 1499 }, 1500 }, 1501 }; 1502 1503 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { 1504 .halt_reg = 0x0a84, 1505 .clkr = { 1506 .enable_reg = 0x0a84, 1507 .enable_mask = BIT(0), 1508 .hw.init = &(struct clk_init_data){ 1509 .name = "gcc_blsp2_qup3_spi_apps_clk", 1510 .parent_names = (const char *[]){ 1511 "blsp2_qup3_spi_apps_clk_src", 1512 }, 1513 .num_parents = 1, 1514 .flags = CLK_SET_RATE_PARENT, 1515 .ops = &clk_branch2_ops, 1516 }, 1517 }, 1518 }; 1519 1520 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { 1521 .halt_reg = 0x0b08, 1522 .clkr = { 1523 .enable_reg = 0x0b08, 1524 .enable_mask = BIT(0), 1525 .hw.init = &(struct clk_init_data){ 1526 .name = "gcc_blsp2_qup4_i2c_apps_clk", 1527 .parent_names = (const char *[]){ 1528 "blsp2_qup4_i2c_apps_clk_src", 1529 }, 1530 .num_parents = 1, 1531 .flags = CLK_SET_RATE_PARENT, 1532 .ops = &clk_branch2_ops, 1533 }, 1534 }, 1535 }; 1536 1537 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { 1538 .halt_reg = 0x0b04, 1539 .clkr = { 1540 .enable_reg = 0x0b04, 1541 .enable_mask = BIT(0), 1542 .hw.init = &(struct clk_init_data){ 1543 .name = "gcc_blsp2_qup4_spi_apps_clk", 1544 .parent_names = (const char *[]){ 1545 "blsp2_qup4_spi_apps_clk_src", 1546 }, 1547 .num_parents = 1, 1548 .flags = CLK_SET_RATE_PARENT, 1549 .ops = &clk_branch2_ops, 1550 }, 1551 }, 1552 }; 1553 1554 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { 1555 .halt_reg = 0x0b88, 1556 .clkr = { 1557 .enable_reg = 0x0b88, 1558 .enable_mask = BIT(0), 1559 .hw.init = &(struct clk_init_data){ 1560 .name = "gcc_blsp2_qup5_i2c_apps_clk", 1561 .parent_names = (const char *[]){ 1562 "blsp2_qup5_i2c_apps_clk_src", 1563 }, 1564 .num_parents = 1, 1565 .flags = CLK_SET_RATE_PARENT, 1566 .ops = &clk_branch2_ops, 1567 }, 1568 }, 1569 }; 1570 1571 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { 1572 .halt_reg = 0x0b84, 1573 .clkr = { 1574 .enable_reg = 0x0b84, 1575 .enable_mask = BIT(0), 1576 .hw.init = &(struct clk_init_data){ 1577 .name = "gcc_blsp2_qup5_spi_apps_clk", 1578 .parent_names = (const char *[]){ 1579 "blsp2_qup5_spi_apps_clk_src", 1580 }, 1581 .num_parents = 1, 1582 .flags = CLK_SET_RATE_PARENT, 1583 .ops = &clk_branch2_ops, 1584 }, 1585 }, 1586 }; 1587 1588 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { 1589 .halt_reg = 0x0c08, 1590 .clkr = { 1591 .enable_reg = 0x0c08, 1592 .enable_mask = BIT(0), 1593 .hw.init = &(struct clk_init_data){ 1594 .name = "gcc_blsp2_qup6_i2c_apps_clk", 1595 .parent_names = (const char *[]){ 1596 "blsp2_qup6_i2c_apps_clk_src", 1597 }, 1598 .num_parents = 1, 1599 .flags = CLK_SET_RATE_PARENT, 1600 .ops = &clk_branch2_ops, 1601 }, 1602 }, 1603 }; 1604 1605 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { 1606 .halt_reg = 0x0c04, 1607 .clkr = { 1608 .enable_reg = 0x0c04, 1609 .enable_mask = BIT(0), 1610 .hw.init = &(struct clk_init_data){ 1611 .name = "gcc_blsp2_qup6_spi_apps_clk", 1612 .parent_names = (const char *[]){ 1613 "blsp2_qup6_spi_apps_clk_src", 1614 }, 1615 .num_parents = 1, 1616 .flags = CLK_SET_RATE_PARENT, 1617 .ops = &clk_branch2_ops, 1618 }, 1619 }, 1620 }; 1621 1622 static struct clk_branch gcc_blsp2_uart1_apps_clk = { 1623 .halt_reg = 0x09c4, 1624 .clkr = { 1625 .enable_reg = 0x09c4, 1626 .enable_mask = BIT(0), 1627 .hw.init = &(struct clk_init_data){ 1628 .name = "gcc_blsp2_uart1_apps_clk", 1629 .parent_names = (const char *[]){ 1630 "blsp2_uart1_apps_clk_src", 1631 }, 1632 .num_parents = 1, 1633 .flags = CLK_SET_RATE_PARENT, 1634 .ops = &clk_branch2_ops, 1635 }, 1636 }, 1637 }; 1638 1639 static struct clk_branch gcc_blsp2_uart2_apps_clk = { 1640 .halt_reg = 0x0a44, 1641 .clkr = { 1642 .enable_reg = 0x0a44, 1643 .enable_mask = BIT(0), 1644 .hw.init = &(struct clk_init_data){ 1645 .name = "gcc_blsp2_uart2_apps_clk", 1646 .parent_names = (const char *[]){ 1647 "blsp2_uart2_apps_clk_src", 1648 }, 1649 .num_parents = 1, 1650 .flags = CLK_SET_RATE_PARENT, 1651 .ops = &clk_branch2_ops, 1652 }, 1653 }, 1654 }; 1655 1656 static struct clk_branch gcc_blsp2_uart3_apps_clk = { 1657 .halt_reg = 0x0ac4, 1658 .clkr = { 1659 .enable_reg = 0x0ac4, 1660 .enable_mask = BIT(0), 1661 .hw.init = &(struct clk_init_data){ 1662 .name = "gcc_blsp2_uart3_apps_clk", 1663 .parent_names = (const char *[]){ 1664 "blsp2_uart3_apps_clk_src", 1665 }, 1666 .num_parents = 1, 1667 .flags = CLK_SET_RATE_PARENT, 1668 .ops = &clk_branch2_ops, 1669 }, 1670 }, 1671 }; 1672 1673 static struct clk_branch gcc_blsp2_uart4_apps_clk = { 1674 .halt_reg = 0x0b44, 1675 .clkr = { 1676 .enable_reg = 0x0b44, 1677 .enable_mask = BIT(0), 1678 .hw.init = &(struct clk_init_data){ 1679 .name = "gcc_blsp2_uart4_apps_clk", 1680 .parent_names = (const char *[]){ 1681 "blsp2_uart4_apps_clk_src", 1682 }, 1683 .num_parents = 1, 1684 .flags = CLK_SET_RATE_PARENT, 1685 .ops = &clk_branch2_ops, 1686 }, 1687 }, 1688 }; 1689 1690 static struct clk_branch gcc_blsp2_uart5_apps_clk = { 1691 .halt_reg = 0x0bc4, 1692 .clkr = { 1693 .enable_reg = 0x0bc4, 1694 .enable_mask = BIT(0), 1695 .hw.init = &(struct clk_init_data){ 1696 .name = "gcc_blsp2_uart5_apps_clk", 1697 .parent_names = (const char *[]){ 1698 "blsp2_uart5_apps_clk_src", 1699 }, 1700 .num_parents = 1, 1701 .flags = CLK_SET_RATE_PARENT, 1702 .ops = &clk_branch2_ops, 1703 }, 1704 }, 1705 }; 1706 1707 static struct clk_branch gcc_blsp2_uart6_apps_clk = { 1708 .halt_reg = 0x0c44, 1709 .clkr = { 1710 .enable_reg = 0x0c44, 1711 .enable_mask = BIT(0), 1712 .hw.init = &(struct clk_init_data){ 1713 .name = "gcc_blsp2_uart6_apps_clk", 1714 .parent_names = (const char *[]){ 1715 "blsp2_uart6_apps_clk_src", 1716 }, 1717 .num_parents = 1, 1718 .flags = CLK_SET_RATE_PARENT, 1719 .ops = &clk_branch2_ops, 1720 }, 1721 }, 1722 }; 1723 1724 static struct clk_branch gcc_boot_rom_ahb_clk = { 1725 .halt_reg = 0x0e04, 1726 .halt_check = BRANCH_HALT_VOTED, 1727 .clkr = { 1728 .enable_reg = 0x1484, 1729 .enable_mask = BIT(10), 1730 .hw.init = &(struct clk_init_data){ 1731 .name = "gcc_boot_rom_ahb_clk", 1732 .parent_names = (const char *[]){ 1733 "config_noc_clk_src", 1734 }, 1735 .num_parents = 1, 1736 .ops = &clk_branch2_ops, 1737 }, 1738 }, 1739 }; 1740 1741 static struct clk_branch gcc_ce1_ahb_clk = { 1742 .halt_reg = 0x104c, 1743 .halt_check = BRANCH_HALT_VOTED, 1744 .clkr = { 1745 .enable_reg = 0x1484, 1746 .enable_mask = BIT(3), 1747 .hw.init = &(struct clk_init_data){ 1748 .name = "gcc_ce1_ahb_clk", 1749 .parent_names = (const char *[]){ 1750 "config_noc_clk_src", 1751 }, 1752 .num_parents = 1, 1753 .ops = &clk_branch2_ops, 1754 }, 1755 }, 1756 }; 1757 1758 static struct clk_branch gcc_ce1_axi_clk = { 1759 .halt_reg = 0x1048, 1760 .halt_check = BRANCH_HALT_VOTED, 1761 .clkr = { 1762 .enable_reg = 0x1484, 1763 .enable_mask = BIT(4), 1764 .hw.init = &(struct clk_init_data){ 1765 .name = "gcc_ce1_axi_clk", 1766 .parent_names = (const char *[]){ 1767 "system_noc_clk_src", 1768 }, 1769 .num_parents = 1, 1770 .ops = &clk_branch2_ops, 1771 }, 1772 }, 1773 }; 1774 1775 static struct clk_branch gcc_ce1_clk = { 1776 .halt_reg = 0x1050, 1777 .halt_check = BRANCH_HALT_VOTED, 1778 .clkr = { 1779 .enable_reg = 0x1484, 1780 .enable_mask = BIT(5), 1781 .hw.init = &(struct clk_init_data){ 1782 .name = "gcc_ce1_clk", 1783 .parent_names = (const char *[]){ 1784 "ce1_clk_src", 1785 }, 1786 .num_parents = 1, 1787 .flags = CLK_SET_RATE_PARENT, 1788 .ops = &clk_branch2_ops, 1789 }, 1790 }, 1791 }; 1792 1793 static struct clk_branch gcc_ce2_ahb_clk = { 1794 .halt_reg = 0x108c, 1795 .halt_check = BRANCH_HALT_VOTED, 1796 .clkr = { 1797 .enable_reg = 0x1484, 1798 .enable_mask = BIT(0), 1799 .hw.init = &(struct clk_init_data){ 1800 .name = "gcc_ce2_ahb_clk", 1801 .parent_names = (const char *[]){ 1802 "config_noc_clk_src", 1803 }, 1804 .num_parents = 1, 1805 .ops = &clk_branch2_ops, 1806 }, 1807 }, 1808 }; 1809 1810 static struct clk_branch gcc_ce2_axi_clk = { 1811 .halt_reg = 0x1088, 1812 .halt_check = BRANCH_HALT_VOTED, 1813 .clkr = { 1814 .enable_reg = 0x1484, 1815 .enable_mask = BIT(1), 1816 .hw.init = &(struct clk_init_data){ 1817 .name = "gcc_ce2_axi_clk", 1818 .parent_names = (const char *[]){ 1819 "system_noc_clk_src", 1820 }, 1821 .num_parents = 1, 1822 .ops = &clk_branch2_ops, 1823 }, 1824 }, 1825 }; 1826 1827 static struct clk_branch gcc_ce2_clk = { 1828 .halt_reg = 0x1090, 1829 .halt_check = BRANCH_HALT_VOTED, 1830 .clkr = { 1831 .enable_reg = 0x1484, 1832 .enable_mask = BIT(2), 1833 .hw.init = &(struct clk_init_data){ 1834 .name = "gcc_ce2_clk", 1835 .parent_names = (const char *[]){ 1836 "ce2_clk_src", 1837 }, 1838 .num_parents = 1, 1839 .flags = CLK_SET_RATE_PARENT, 1840 .ops = &clk_branch2_ops, 1841 }, 1842 }, 1843 }; 1844 1845 static struct clk_branch gcc_gp1_clk = { 1846 .halt_reg = 0x1900, 1847 .clkr = { 1848 .enable_reg = 0x1900, 1849 .enable_mask = BIT(0), 1850 .hw.init = &(struct clk_init_data){ 1851 .name = "gcc_gp1_clk", 1852 .parent_names = (const char *[]){ 1853 "gp1_clk_src", 1854 }, 1855 .num_parents = 1, 1856 .flags = CLK_SET_RATE_PARENT, 1857 .ops = &clk_branch2_ops, 1858 }, 1859 }, 1860 }; 1861 1862 static struct clk_branch gcc_gp2_clk = { 1863 .halt_reg = 0x1940, 1864 .clkr = { 1865 .enable_reg = 0x1940, 1866 .enable_mask = BIT(0), 1867 .hw.init = &(struct clk_init_data){ 1868 .name = "gcc_gp2_clk", 1869 .parent_names = (const char *[]){ 1870 "gp2_clk_src", 1871 }, 1872 .num_parents = 1, 1873 .flags = CLK_SET_RATE_PARENT, 1874 .ops = &clk_branch2_ops, 1875 }, 1876 }, 1877 }; 1878 1879 static struct clk_branch gcc_gp3_clk = { 1880 .halt_reg = 0x1980, 1881 .clkr = { 1882 .enable_reg = 0x1980, 1883 .enable_mask = BIT(0), 1884 .hw.init = &(struct clk_init_data){ 1885 .name = "gcc_gp3_clk", 1886 .parent_names = (const char *[]){ 1887 "gp3_clk_src", 1888 }, 1889 .num_parents = 1, 1890 .flags = CLK_SET_RATE_PARENT, 1891 .ops = &clk_branch2_ops, 1892 }, 1893 }, 1894 }; 1895 1896 static struct clk_branch gcc_lpass_q6_axi_clk = { 1897 .halt_reg = 0x11c0, 1898 .clkr = { 1899 .enable_reg = 0x11c0, 1900 .enable_mask = BIT(0), 1901 .hw.init = &(struct clk_init_data){ 1902 .name = "gcc_lpass_q6_axi_clk", 1903 .parent_names = (const char *[]){ 1904 "system_noc_clk_src", 1905 }, 1906 .num_parents = 1, 1907 .ops = &clk_branch2_ops, 1908 }, 1909 }, 1910 }; 1911 1912 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { 1913 .halt_reg = 0x024c, 1914 .clkr = { 1915 .enable_reg = 0x024c, 1916 .enable_mask = BIT(0), 1917 .hw.init = &(struct clk_init_data){ 1918 .name = "gcc_mmss_noc_cfg_ahb_clk", 1919 .parent_names = (const char *[]){ 1920 "config_noc_clk_src", 1921 }, 1922 .num_parents = 1, 1923 .ops = &clk_branch2_ops, 1924 .flags = CLK_IGNORE_UNUSED, 1925 }, 1926 }, 1927 }; 1928 1929 static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = { 1930 .halt_reg = 0x0248, 1931 .clkr = { 1932 .enable_reg = 0x0248, 1933 .enable_mask = BIT(0), 1934 .hw.init = &(struct clk_init_data){ 1935 .name = "gcc_ocmem_noc_cfg_ahb_clk", 1936 .parent_names = (const char *[]){ 1937 "config_noc_clk_src", 1938 }, 1939 .num_parents = 1, 1940 .ops = &clk_branch2_ops, 1941 }, 1942 }, 1943 }; 1944 1945 static struct clk_branch gcc_mss_cfg_ahb_clk = { 1946 .halt_reg = 0x0280, 1947 .clkr = { 1948 .enable_reg = 0x0280, 1949 .enable_mask = BIT(0), 1950 .hw.init = &(struct clk_init_data){ 1951 .name = "gcc_mss_cfg_ahb_clk", 1952 .parent_names = (const char *[]){ 1953 "config_noc_clk_src", 1954 }, 1955 .num_parents = 1, 1956 .ops = &clk_branch2_ops, 1957 }, 1958 }, 1959 }; 1960 1961 static struct clk_branch gcc_mss_q6_bimc_axi_clk = { 1962 .halt_reg = 0x0284, 1963 .clkr = { 1964 .enable_reg = 0x0284, 1965 .enable_mask = BIT(0), 1966 .hw.init = &(struct clk_init_data){ 1967 .name = "gcc_mss_q6_bimc_axi_clk", 1968 .ops = &clk_branch2_ops, 1969 }, 1970 }, 1971 }; 1972 1973 static struct clk_branch gcc_pdm2_clk = { 1974 .halt_reg = 0x0ccc, 1975 .clkr = { 1976 .enable_reg = 0x0ccc, 1977 .enable_mask = BIT(0), 1978 .hw.init = &(struct clk_init_data){ 1979 .name = "gcc_pdm2_clk", 1980 .parent_names = (const char *[]){ 1981 "pdm2_clk_src", 1982 }, 1983 .num_parents = 1, 1984 .flags = CLK_SET_RATE_PARENT, 1985 .ops = &clk_branch2_ops, 1986 }, 1987 }, 1988 }; 1989 1990 static struct clk_branch gcc_pdm_ahb_clk = { 1991 .halt_reg = 0x0cc4, 1992 .clkr = { 1993 .enable_reg = 0x0cc4, 1994 .enable_mask = BIT(0), 1995 .hw.init = &(struct clk_init_data){ 1996 .name = "gcc_pdm_ahb_clk", 1997 .parent_names = (const char *[]){ 1998 "periph_noc_clk_src", 1999 }, 2000 .num_parents = 1, 2001 .ops = &clk_branch2_ops, 2002 }, 2003 }, 2004 }; 2005 2006 static struct clk_branch gcc_prng_ahb_clk = { 2007 .halt_reg = 0x0d04, 2008 .halt_check = BRANCH_HALT_VOTED, 2009 .clkr = { 2010 .enable_reg = 0x1484, 2011 .enable_mask = BIT(13), 2012 .hw.init = &(struct clk_init_data){ 2013 .name = "gcc_prng_ahb_clk", 2014 .parent_names = (const char *[]){ 2015 "periph_noc_clk_src", 2016 }, 2017 .num_parents = 1, 2018 .ops = &clk_branch2_ops, 2019 }, 2020 }, 2021 }; 2022 2023 static struct clk_branch gcc_sdcc1_ahb_clk = { 2024 .halt_reg = 0x04c8, 2025 .clkr = { 2026 .enable_reg = 0x04c8, 2027 .enable_mask = BIT(0), 2028 .hw.init = &(struct clk_init_data){ 2029 .name = "gcc_sdcc1_ahb_clk", 2030 .parent_names = (const char *[]){ 2031 "periph_noc_clk_src", 2032 }, 2033 .num_parents = 1, 2034 .ops = &clk_branch2_ops, 2035 }, 2036 }, 2037 }; 2038 2039 static struct clk_branch gcc_sdcc1_apps_clk = { 2040 .halt_reg = 0x04c4, 2041 .clkr = { 2042 .enable_reg = 0x04c4, 2043 .enable_mask = BIT(0), 2044 .hw.init = &(struct clk_init_data){ 2045 .name = "gcc_sdcc1_apps_clk", 2046 .parent_names = (const char *[]){ 2047 "sdcc1_apps_clk_src", 2048 }, 2049 .num_parents = 1, 2050 .flags = CLK_SET_RATE_PARENT, 2051 .ops = &clk_branch2_ops, 2052 }, 2053 }, 2054 }; 2055 2056 static struct clk_branch gcc_sdcc1_cdccal_ff_clk = { 2057 .halt_reg = 0x04e8, 2058 .clkr = { 2059 .enable_reg = 0x04e8, 2060 .enable_mask = BIT(0), 2061 .hw.init = &(struct clk_init_data){ 2062 .name = "gcc_sdcc1_cdccal_ff_clk", 2063 .parent_names = (const char *[]){ 2064 "xo" 2065 }, 2066 .num_parents = 1, 2067 .ops = &clk_branch2_ops, 2068 }, 2069 }, 2070 }; 2071 2072 static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = { 2073 .halt_reg = 0x04e4, 2074 .clkr = { 2075 .enable_reg = 0x04e4, 2076 .enable_mask = BIT(0), 2077 .hw.init = &(struct clk_init_data){ 2078 .name = "gcc_sdcc1_cdccal_sleep_clk", 2079 .parent_names = (const char *[]){ 2080 "sleep_clk_src" 2081 }, 2082 .num_parents = 1, 2083 .ops = &clk_branch2_ops, 2084 }, 2085 }, 2086 }; 2087 2088 static struct clk_branch gcc_sdcc2_ahb_clk = { 2089 .halt_reg = 0x0508, 2090 .clkr = { 2091 .enable_reg = 0x0508, 2092 .enable_mask = BIT(0), 2093 .hw.init = &(struct clk_init_data){ 2094 .name = "gcc_sdcc2_ahb_clk", 2095 .parent_names = (const char *[]){ 2096 "periph_noc_clk_src", 2097 }, 2098 .num_parents = 1, 2099 .ops = &clk_branch2_ops, 2100 }, 2101 }, 2102 }; 2103 2104 static struct clk_branch gcc_sdcc2_apps_clk = { 2105 .halt_reg = 0x0504, 2106 .clkr = { 2107 .enable_reg = 0x0504, 2108 .enable_mask = BIT(0), 2109 .hw.init = &(struct clk_init_data){ 2110 .name = "gcc_sdcc2_apps_clk", 2111 .parent_names = (const char *[]){ 2112 "sdcc2_apps_clk_src", 2113 }, 2114 .num_parents = 1, 2115 .flags = CLK_SET_RATE_PARENT, 2116 .ops = &clk_branch2_ops, 2117 }, 2118 }, 2119 }; 2120 2121 static struct clk_branch gcc_sdcc3_ahb_clk = { 2122 .halt_reg = 0x0548, 2123 .clkr = { 2124 .enable_reg = 0x0548, 2125 .enable_mask = BIT(0), 2126 .hw.init = &(struct clk_init_data){ 2127 .name = "gcc_sdcc3_ahb_clk", 2128 .parent_names = (const char *[]){ 2129 "periph_noc_clk_src", 2130 }, 2131 .num_parents = 1, 2132 .ops = &clk_branch2_ops, 2133 }, 2134 }, 2135 }; 2136 2137 static struct clk_branch gcc_sdcc3_apps_clk = { 2138 .halt_reg = 0x0544, 2139 .clkr = { 2140 .enable_reg = 0x0544, 2141 .enable_mask = BIT(0), 2142 .hw.init = &(struct clk_init_data){ 2143 .name = "gcc_sdcc3_apps_clk", 2144 .parent_names = (const char *[]){ 2145 "sdcc3_apps_clk_src", 2146 }, 2147 .num_parents = 1, 2148 .flags = CLK_SET_RATE_PARENT, 2149 .ops = &clk_branch2_ops, 2150 }, 2151 }, 2152 }; 2153 2154 static struct clk_branch gcc_sdcc4_ahb_clk = { 2155 .halt_reg = 0x0588, 2156 .clkr = { 2157 .enable_reg = 0x0588, 2158 .enable_mask = BIT(0), 2159 .hw.init = &(struct clk_init_data){ 2160 .name = "gcc_sdcc4_ahb_clk", 2161 .parent_names = (const char *[]){ 2162 "periph_noc_clk_src", 2163 }, 2164 .num_parents = 1, 2165 .ops = &clk_branch2_ops, 2166 }, 2167 }, 2168 }; 2169 2170 static struct clk_branch gcc_sdcc4_apps_clk = { 2171 .halt_reg = 0x0584, 2172 .clkr = { 2173 .enable_reg = 0x0584, 2174 .enable_mask = BIT(0), 2175 .hw.init = &(struct clk_init_data){ 2176 .name = "gcc_sdcc4_apps_clk", 2177 .parent_names = (const char *[]){ 2178 "sdcc4_apps_clk_src", 2179 }, 2180 .num_parents = 1, 2181 .flags = CLK_SET_RATE_PARENT, 2182 .ops = &clk_branch2_ops, 2183 }, 2184 }, 2185 }; 2186 2187 static struct clk_branch gcc_sys_noc_usb3_axi_clk = { 2188 .halt_reg = 0x0108, 2189 .clkr = { 2190 .enable_reg = 0x0108, 2191 .enable_mask = BIT(0), 2192 .hw.init = &(struct clk_init_data){ 2193 .name = "gcc_sys_noc_usb3_axi_clk", 2194 .parent_names = (const char *[]){ 2195 "usb30_master_clk_src", 2196 }, 2197 .num_parents = 1, 2198 .flags = CLK_SET_RATE_PARENT, 2199 .ops = &clk_branch2_ops, 2200 }, 2201 }, 2202 }; 2203 2204 static struct clk_branch gcc_tsif_ahb_clk = { 2205 .halt_reg = 0x0d84, 2206 .clkr = { 2207 .enable_reg = 0x0d84, 2208 .enable_mask = BIT(0), 2209 .hw.init = &(struct clk_init_data){ 2210 .name = "gcc_tsif_ahb_clk", 2211 .parent_names = (const char *[]){ 2212 "periph_noc_clk_src", 2213 }, 2214 .num_parents = 1, 2215 .ops = &clk_branch2_ops, 2216 }, 2217 }, 2218 }; 2219 2220 static struct clk_branch gcc_tsif_ref_clk = { 2221 .halt_reg = 0x0d88, 2222 .clkr = { 2223 .enable_reg = 0x0d88, 2224 .enable_mask = BIT(0), 2225 .hw.init = &(struct clk_init_data){ 2226 .name = "gcc_tsif_ref_clk", 2227 .parent_names = (const char *[]){ 2228 "tsif_ref_clk_src", 2229 }, 2230 .num_parents = 1, 2231 .flags = CLK_SET_RATE_PARENT, 2232 .ops = &clk_branch2_ops, 2233 }, 2234 }, 2235 }; 2236 2237 static struct clk_branch gcc_usb2a_phy_sleep_clk = { 2238 .halt_reg = 0x04ac, 2239 .clkr = { 2240 .enable_reg = 0x04ac, 2241 .enable_mask = BIT(0), 2242 .hw.init = &(struct clk_init_data){ 2243 .name = "gcc_usb2a_phy_sleep_clk", 2244 .parent_names = (const char *[]){ 2245 "sleep_clk_src", 2246 }, 2247 .num_parents = 1, 2248 .ops = &clk_branch2_ops, 2249 }, 2250 }, 2251 }; 2252 2253 static struct clk_branch gcc_usb2b_phy_sleep_clk = { 2254 .halt_reg = 0x04b4, 2255 .clkr = { 2256 .enable_reg = 0x04b4, 2257 .enable_mask = BIT(0), 2258 .hw.init = &(struct clk_init_data){ 2259 .name = "gcc_usb2b_phy_sleep_clk", 2260 .parent_names = (const char *[]){ 2261 "sleep_clk_src", 2262 }, 2263 .num_parents = 1, 2264 .ops = &clk_branch2_ops, 2265 }, 2266 }, 2267 }; 2268 2269 static struct clk_branch gcc_usb30_master_clk = { 2270 .halt_reg = 0x03c8, 2271 .clkr = { 2272 .enable_reg = 0x03c8, 2273 .enable_mask = BIT(0), 2274 .hw.init = &(struct clk_init_data){ 2275 .name = "gcc_usb30_master_clk", 2276 .parent_names = (const char *[]){ 2277 "usb30_master_clk_src", 2278 }, 2279 .num_parents = 1, 2280 .flags = CLK_SET_RATE_PARENT, 2281 .ops = &clk_branch2_ops, 2282 }, 2283 }, 2284 }; 2285 2286 static struct clk_branch gcc_usb30_mock_utmi_clk = { 2287 .halt_reg = 0x03d0, 2288 .clkr = { 2289 .enable_reg = 0x03d0, 2290 .enable_mask = BIT(0), 2291 .hw.init = &(struct clk_init_data){ 2292 .name = "gcc_usb30_mock_utmi_clk", 2293 .parent_names = (const char *[]){ 2294 "usb30_mock_utmi_clk_src", 2295 }, 2296 .num_parents = 1, 2297 .flags = CLK_SET_RATE_PARENT, 2298 .ops = &clk_branch2_ops, 2299 }, 2300 }, 2301 }; 2302 2303 static struct clk_branch gcc_usb30_sleep_clk = { 2304 .halt_reg = 0x03cc, 2305 .clkr = { 2306 .enable_reg = 0x03cc, 2307 .enable_mask = BIT(0), 2308 .hw.init = &(struct clk_init_data){ 2309 .name = "gcc_usb30_sleep_clk", 2310 .parent_names = (const char *[]){ 2311 "sleep_clk_src", 2312 }, 2313 .num_parents = 1, 2314 .ops = &clk_branch2_ops, 2315 }, 2316 }, 2317 }; 2318 2319 static struct clk_branch gcc_usb_hs_ahb_clk = { 2320 .halt_reg = 0x0488, 2321 .clkr = { 2322 .enable_reg = 0x0488, 2323 .enable_mask = BIT(0), 2324 .hw.init = &(struct clk_init_data){ 2325 .name = "gcc_usb_hs_ahb_clk", 2326 .parent_names = (const char *[]){ 2327 "periph_noc_clk_src", 2328 }, 2329 .num_parents = 1, 2330 .ops = &clk_branch2_ops, 2331 }, 2332 }, 2333 }; 2334 2335 static struct clk_branch gcc_usb_hs_system_clk = { 2336 .halt_reg = 0x0484, 2337 .clkr = { 2338 .enable_reg = 0x0484, 2339 .enable_mask = BIT(0), 2340 .hw.init = &(struct clk_init_data){ 2341 .name = "gcc_usb_hs_system_clk", 2342 .parent_names = (const char *[]){ 2343 "usb_hs_system_clk_src", 2344 }, 2345 .num_parents = 1, 2346 .flags = CLK_SET_RATE_PARENT, 2347 .ops = &clk_branch2_ops, 2348 }, 2349 }, 2350 }; 2351 2352 static struct clk_branch gcc_usb_hsic_ahb_clk = { 2353 .halt_reg = 0x0408, 2354 .clkr = { 2355 .enable_reg = 0x0408, 2356 .enable_mask = BIT(0), 2357 .hw.init = &(struct clk_init_data){ 2358 .name = "gcc_usb_hsic_ahb_clk", 2359 .parent_names = (const char *[]){ 2360 "periph_noc_clk_src", 2361 }, 2362 .num_parents = 1, 2363 .ops = &clk_branch2_ops, 2364 }, 2365 }, 2366 }; 2367 2368 static struct clk_branch gcc_usb_hsic_clk = { 2369 .halt_reg = 0x0410, 2370 .clkr = { 2371 .enable_reg = 0x0410, 2372 .enable_mask = BIT(0), 2373 .hw.init = &(struct clk_init_data){ 2374 .name = "gcc_usb_hsic_clk", 2375 .parent_names = (const char *[]){ 2376 "usb_hsic_clk_src", 2377 }, 2378 .num_parents = 1, 2379 .flags = CLK_SET_RATE_PARENT, 2380 .ops = &clk_branch2_ops, 2381 }, 2382 }, 2383 }; 2384 2385 static struct clk_branch gcc_usb_hsic_io_cal_clk = { 2386 .halt_reg = 0x0414, 2387 .clkr = { 2388 .enable_reg = 0x0414, 2389 .enable_mask = BIT(0), 2390 .hw.init = &(struct clk_init_data){ 2391 .name = "gcc_usb_hsic_io_cal_clk", 2392 .parent_names = (const char *[]){ 2393 "usb_hsic_io_cal_clk_src", 2394 }, 2395 .num_parents = 1, 2396 .flags = CLK_SET_RATE_PARENT, 2397 .ops = &clk_branch2_ops, 2398 }, 2399 }, 2400 }; 2401 2402 static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = { 2403 .halt_reg = 0x0418, 2404 .clkr = { 2405 .enable_reg = 0x0418, 2406 .enable_mask = BIT(0), 2407 .hw.init = &(struct clk_init_data){ 2408 .name = "gcc_usb_hsic_io_cal_sleep_clk", 2409 .parent_names = (const char *[]){ 2410 "sleep_clk_src", 2411 }, 2412 .num_parents = 1, 2413 .ops = &clk_branch2_ops, 2414 }, 2415 }, 2416 }; 2417 2418 static struct clk_branch gcc_usb_hsic_system_clk = { 2419 .halt_reg = 0x040c, 2420 .clkr = { 2421 .enable_reg = 0x040c, 2422 .enable_mask = BIT(0), 2423 .hw.init = &(struct clk_init_data){ 2424 .name = "gcc_usb_hsic_system_clk", 2425 .parent_names = (const char *[]){ 2426 "usb_hsic_system_clk_src", 2427 }, 2428 .num_parents = 1, 2429 .flags = CLK_SET_RATE_PARENT, 2430 .ops = &clk_branch2_ops, 2431 }, 2432 }, 2433 }; 2434 2435 static struct gdsc usb_hs_hsic_gdsc = { 2436 .gdscr = 0x404, 2437 .pd = { 2438 .name = "usb_hs_hsic", 2439 }, 2440 .pwrsts = PWRSTS_OFF_ON, 2441 }; 2442 2443 static struct clk_regmap *gcc_msm8974_clocks[] = { 2444 [GPLL0] = &gpll0.clkr, 2445 [GPLL0_VOTE] = &gpll0_vote, 2446 [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr, 2447 [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr, 2448 [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr, 2449 [GPLL1] = &gpll1.clkr, 2450 [GPLL1_VOTE] = &gpll1_vote, 2451 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, 2452 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 2453 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 2454 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 2455 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 2456 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 2457 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 2458 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 2459 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 2460 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 2461 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 2462 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 2463 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 2464 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 2465 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 2466 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, 2467 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, 2468 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, 2469 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, 2470 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, 2471 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, 2472 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, 2473 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, 2474 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, 2475 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, 2476 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, 2477 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, 2478 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr, 2479 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr, 2480 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr, 2481 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr, 2482 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, 2483 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, 2484 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr, 2485 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr, 2486 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr, 2487 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr, 2488 [CE1_CLK_SRC] = &ce1_clk_src.clkr, 2489 [CE2_CLK_SRC] = &ce2_clk_src.clkr, 2490 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 2491 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 2492 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 2493 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 2494 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 2495 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 2496 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr, 2497 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr, 2498 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr, 2499 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, 2500 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, 2501 [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr, 2502 [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr, 2503 [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr, 2504 [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr, 2505 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 2506 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 2507 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 2508 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 2509 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 2510 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 2511 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 2512 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 2513 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 2514 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 2515 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 2516 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 2517 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 2518 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 2519 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 2520 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 2521 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, 2522 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, 2523 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, 2524 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, 2525 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, 2526 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, 2527 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, 2528 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, 2529 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, 2530 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, 2531 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, 2532 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, 2533 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr, 2534 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr, 2535 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr, 2536 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr, 2537 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, 2538 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, 2539 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr, 2540 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr, 2541 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr, 2542 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr, 2543 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2544 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, 2545 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, 2546 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, 2547 [GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr, 2548 [GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr, 2549 [GCC_CE2_CLK] = &gcc_ce2_clk.clkr, 2550 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2551 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2552 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2553 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, 2554 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr, 2555 [GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr, 2556 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 2557 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, 2558 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2559 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2560 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 2561 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2562 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2563 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2564 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2565 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr, 2566 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr, 2567 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 2568 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 2569 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr, 2570 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 2571 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 2572 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, 2573 [GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr, 2574 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, 2575 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, 2576 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, 2577 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, 2578 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, 2579 [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr, 2580 [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr, 2581 [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr, 2582 [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr, 2583 [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr, 2584 [GCC_MMSS_GPLL0_CLK_SRC] = &gcc_mmss_gpll0_clk_src, 2585 [GPLL4] = NULL, 2586 [GPLL4_VOTE] = NULL, 2587 [GCC_SDCC1_CDCCAL_SLEEP_CLK] = NULL, 2588 [GCC_SDCC1_CDCCAL_FF_CLK] = NULL, 2589 }; 2590 2591 static const struct qcom_reset_map gcc_msm8974_resets[] = { 2592 [GCC_SYSTEM_NOC_BCR] = { 0x0100 }, 2593 [GCC_CONFIG_NOC_BCR] = { 0x0140 }, 2594 [GCC_PERIPH_NOC_BCR] = { 0x0180 }, 2595 [GCC_IMEM_BCR] = { 0x0200 }, 2596 [GCC_MMSS_BCR] = { 0x0240 }, 2597 [GCC_QDSS_BCR] = { 0x0300 }, 2598 [GCC_USB_30_BCR] = { 0x03c0 }, 2599 [GCC_USB3_PHY_BCR] = { 0x03fc }, 2600 [GCC_USB_HS_HSIC_BCR] = { 0x0400 }, 2601 [GCC_USB_HS_BCR] = { 0x0480 }, 2602 [GCC_USB2A_PHY_BCR] = { 0x04a8 }, 2603 [GCC_USB2B_PHY_BCR] = { 0x04b0 }, 2604 [GCC_SDCC1_BCR] = { 0x04c0 }, 2605 [GCC_SDCC2_BCR] = { 0x0500 }, 2606 [GCC_SDCC3_BCR] = { 0x0540 }, 2607 [GCC_SDCC4_BCR] = { 0x0580 }, 2608 [GCC_BLSP1_BCR] = { 0x05c0 }, 2609 [GCC_BLSP1_QUP1_BCR] = { 0x0640 }, 2610 [GCC_BLSP1_UART1_BCR] = { 0x0680 }, 2611 [GCC_BLSP1_QUP2_BCR] = { 0x06c0 }, 2612 [GCC_BLSP1_UART2_BCR] = { 0x0700 }, 2613 [GCC_BLSP1_QUP3_BCR] = { 0x0740 }, 2614 [GCC_BLSP1_UART3_BCR] = { 0x0780 }, 2615 [GCC_BLSP1_QUP4_BCR] = { 0x07c0 }, 2616 [GCC_BLSP1_UART4_BCR] = { 0x0800 }, 2617 [GCC_BLSP1_QUP5_BCR] = { 0x0840 }, 2618 [GCC_BLSP1_UART5_BCR] = { 0x0880 }, 2619 [GCC_BLSP1_QUP6_BCR] = { 0x08c0 }, 2620 [GCC_BLSP1_UART6_BCR] = { 0x0900 }, 2621 [GCC_BLSP2_BCR] = { 0x0940 }, 2622 [GCC_BLSP2_QUP1_BCR] = { 0x0980 }, 2623 [GCC_BLSP2_UART1_BCR] = { 0x09c0 }, 2624 [GCC_BLSP2_QUP2_BCR] = { 0x0a00 }, 2625 [GCC_BLSP2_UART2_BCR] = { 0x0a40 }, 2626 [GCC_BLSP2_QUP3_BCR] = { 0x0a80 }, 2627 [GCC_BLSP2_UART3_BCR] = { 0x0ac0 }, 2628 [GCC_BLSP2_QUP4_BCR] = { 0x0b00 }, 2629 [GCC_BLSP2_UART4_BCR] = { 0x0b40 }, 2630 [GCC_BLSP2_QUP5_BCR] = { 0x0b80 }, 2631 [GCC_BLSP2_UART5_BCR] = { 0x0bc0 }, 2632 [GCC_BLSP2_QUP6_BCR] = { 0x0c00 }, 2633 [GCC_BLSP2_UART6_BCR] = { 0x0c40 }, 2634 [GCC_PDM_BCR] = { 0x0cc0 }, 2635 [GCC_BAM_DMA_BCR] = { 0x0d40 }, 2636 [GCC_TSIF_BCR] = { 0x0d80 }, 2637 [GCC_TCSR_BCR] = { 0x0dc0 }, 2638 [GCC_BOOT_ROM_BCR] = { 0x0e00 }, 2639 [GCC_MSG_RAM_BCR] = { 0x0e40 }, 2640 [GCC_TLMM_BCR] = { 0x0e80 }, 2641 [GCC_MPM_BCR] = { 0x0ec0 }, 2642 [GCC_SEC_CTRL_BCR] = { 0x0f40 }, 2643 [GCC_SPMI_BCR] = { 0x0fc0 }, 2644 [GCC_SPDM_BCR] = { 0x1000 }, 2645 [GCC_CE1_BCR] = { 0x1040 }, 2646 [GCC_CE2_BCR] = { 0x1080 }, 2647 [GCC_BIMC_BCR] = { 0x1100 }, 2648 [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 }, 2649 [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 }, 2650 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 }, 2651 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 }, 2652 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 }, 2653 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 }, 2654 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 }, 2655 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 }, 2656 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 }, 2657 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 }, 2658 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 }, 2659 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 }, 2660 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 }, 2661 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 }, 2662 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 }, 2663 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 }, 2664 [GCC_DEHR_BCR] = { 0x1300 }, 2665 [GCC_RBCPR_BCR] = { 0x1380 }, 2666 [GCC_MSS_RESTART] = { 0x1680 }, 2667 [GCC_LPASS_RESTART] = { 0x16c0 }, 2668 [GCC_WCSS_RESTART] = { 0x1700 }, 2669 [GCC_VENUS_RESTART] = { 0x1740 }, 2670 }; 2671 2672 static struct gdsc *gcc_msm8974_gdscs[] = { 2673 [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc, 2674 }; 2675 2676 static const struct regmap_config gcc_msm8974_regmap_config = { 2677 .reg_bits = 32, 2678 .reg_stride = 4, 2679 .val_bits = 32, 2680 .max_register = 0x1fc0, 2681 .fast_io = true, 2682 }; 2683 2684 static const struct qcom_cc_desc gcc_msm8974_desc = { 2685 .config = &gcc_msm8974_regmap_config, 2686 .clks = gcc_msm8974_clocks, 2687 .num_clks = ARRAY_SIZE(gcc_msm8974_clocks), 2688 .resets = gcc_msm8974_resets, 2689 .num_resets = ARRAY_SIZE(gcc_msm8974_resets), 2690 .gdscs = gcc_msm8974_gdscs, 2691 .num_gdscs = ARRAY_SIZE(gcc_msm8974_gdscs), 2692 }; 2693 2694 static const struct of_device_id gcc_msm8974_match_table[] = { 2695 { .compatible = "qcom,gcc-msm8974" }, 2696 { .compatible = "qcom,gcc-msm8974pro" , .data = (void *)1UL }, 2697 { .compatible = "qcom,gcc-msm8974pro-ac", .data = (void *)1UL }, 2698 { } 2699 }; 2700 MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table); 2701 2702 static void msm8974_pro_clock_override(void) 2703 { 2704 sdcc1_apps_clk_src_init.parent_names = gcc_xo_gpll0_gpll4; 2705 sdcc1_apps_clk_src_init.num_parents = 3; 2706 sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_pro; 2707 sdcc1_apps_clk_src.parent_map = gcc_xo_gpll0_gpll4_map; 2708 2709 gcc_msm8974_clocks[GPLL4] = &gpll4.clkr; 2710 gcc_msm8974_clocks[GPLL4_VOTE] = &gpll4_vote; 2711 gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_SLEEP_CLK] = 2712 &gcc_sdcc1_cdccal_sleep_clk.clkr; 2713 gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_FF_CLK] = 2714 &gcc_sdcc1_cdccal_ff_clk.clkr; 2715 } 2716 2717 static int gcc_msm8974_probe(struct platform_device *pdev) 2718 { 2719 int ret; 2720 struct device *dev = &pdev->dev; 2721 bool pro; 2722 const struct of_device_id *id; 2723 2724 id = of_match_device(gcc_msm8974_match_table, dev); 2725 if (!id) 2726 return -ENODEV; 2727 pro = !!(id->data); 2728 2729 if (pro) 2730 msm8974_pro_clock_override(); 2731 2732 ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000); 2733 if (ret) 2734 return ret; 2735 2736 ret = qcom_cc_register_sleep_clk(dev); 2737 if (ret) 2738 return ret; 2739 2740 return qcom_cc_probe(pdev, &gcc_msm8974_desc); 2741 } 2742 2743 static struct platform_driver gcc_msm8974_driver = { 2744 .probe = gcc_msm8974_probe, 2745 .driver = { 2746 .name = "gcc-msm8974", 2747 .of_match_table = gcc_msm8974_match_table, 2748 }, 2749 }; 2750 2751 static int __init gcc_msm8974_init(void) 2752 { 2753 return platform_driver_register(&gcc_msm8974_driver); 2754 } 2755 core_initcall(gcc_msm8974_init); 2756 2757 static void __exit gcc_msm8974_exit(void) 2758 { 2759 platform_driver_unregister(&gcc_msm8974_driver); 2760 } 2761 module_exit(gcc_msm8974_exit); 2762 2763 MODULE_DESCRIPTION("QCOM GCC MSM8974 Driver"); 2764 MODULE_LICENSE("GPL v2"); 2765 MODULE_ALIAS("platform:gcc-msm8974"); 2766