1 /* 2 * Copyright 2015 Linaro Limited 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/bitops.h> 16 #include <linux/err.h> 17 #include <linux/platform_device.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/clk-provider.h> 22 #include <linux/regmap.h> 23 #include <linux/reset-controller.h> 24 25 #include <dt-bindings/clock/qcom,gcc-msm8916.h> 26 #include <dt-bindings/reset/qcom,gcc-msm8916.h> 27 28 #include "common.h" 29 #include "clk-regmap.h" 30 #include "clk-pll.h" 31 #include "clk-rcg.h" 32 #include "clk-branch.h" 33 #include "reset.h" 34 #include "gdsc.h" 35 36 enum { 37 P_XO, 38 P_GPLL0, 39 P_GPLL0_AUX, 40 P_BIMC, 41 P_GPLL1, 42 P_GPLL1_AUX, 43 P_GPLL2, 44 P_GPLL2_AUX, 45 P_SLEEP_CLK, 46 P_DSI0_PHYPLL_BYTE, 47 P_DSI0_PHYPLL_DSI, 48 P_EXT_PRI_I2S, 49 P_EXT_SEC_I2S, 50 P_EXT_MCLK, 51 }; 52 53 static const struct parent_map gcc_xo_gpll0_map[] = { 54 { P_XO, 0 }, 55 { P_GPLL0, 1 }, 56 }; 57 58 static const char * const gcc_xo_gpll0[] = { 59 "xo", 60 "gpll0_vote", 61 }; 62 63 static const struct parent_map gcc_xo_gpll0_bimc_map[] = { 64 { P_XO, 0 }, 65 { P_GPLL0, 1 }, 66 { P_BIMC, 2 }, 67 }; 68 69 static const char * const gcc_xo_gpll0_bimc[] = { 70 "xo", 71 "gpll0_vote", 72 "bimc_pll_vote", 73 }; 74 75 static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = { 76 { P_XO, 0 }, 77 { P_GPLL0_AUX, 3 }, 78 { P_GPLL1, 1 }, 79 { P_GPLL2_AUX, 2 }, 80 }; 81 82 static const char * const gcc_xo_gpll0a_gpll1_gpll2a[] = { 83 "xo", 84 "gpll0_vote", 85 "gpll1_vote", 86 "gpll2_vote", 87 }; 88 89 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = { 90 { P_XO, 0 }, 91 { P_GPLL0, 1 }, 92 { P_GPLL2, 2 }, 93 }; 94 95 static const char * const gcc_xo_gpll0_gpll2[] = { 96 "xo", 97 "gpll0_vote", 98 "gpll2_vote", 99 }; 100 101 static const struct parent_map gcc_xo_gpll0a_map[] = { 102 { P_XO, 0 }, 103 { P_GPLL0_AUX, 2 }, 104 }; 105 106 static const char * const gcc_xo_gpll0a[] = { 107 "xo", 108 "gpll0_vote", 109 }; 110 111 static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = { 112 { P_XO, 0 }, 113 { P_GPLL0, 1 }, 114 { P_GPLL1_AUX, 2 }, 115 { P_SLEEP_CLK, 6 }, 116 }; 117 118 static const char * const gcc_xo_gpll0_gpll1a_sleep[] = { 119 "xo", 120 "gpll0_vote", 121 "gpll1_vote", 122 "sleep_clk", 123 }; 124 125 static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = { 126 { P_XO, 0 }, 127 { P_GPLL0, 1 }, 128 { P_GPLL1_AUX, 2 }, 129 }; 130 131 static const char * const gcc_xo_gpll0_gpll1a[] = { 132 "xo", 133 "gpll0_vote", 134 "gpll1_vote", 135 }; 136 137 static const struct parent_map gcc_xo_dsibyte_map[] = { 138 { P_XO, 0, }, 139 { P_DSI0_PHYPLL_BYTE, 2 }, 140 }; 141 142 static const char * const gcc_xo_dsibyte[] = { 143 "xo", 144 "dsi0pllbyte", 145 }; 146 147 static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = { 148 { P_XO, 0 }, 149 { P_GPLL0_AUX, 2 }, 150 { P_DSI0_PHYPLL_BYTE, 1 }, 151 }; 152 153 static const char * const gcc_xo_gpll0a_dsibyte[] = { 154 "xo", 155 "gpll0_vote", 156 "dsi0pllbyte", 157 }; 158 159 static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = { 160 { P_XO, 0 }, 161 { P_GPLL0, 1 }, 162 { P_DSI0_PHYPLL_DSI, 2 }, 163 }; 164 165 static const char * const gcc_xo_gpll0_dsiphy[] = { 166 "xo", 167 "gpll0_vote", 168 "dsi0pll", 169 }; 170 171 static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = { 172 { P_XO, 0 }, 173 { P_GPLL0_AUX, 2 }, 174 { P_DSI0_PHYPLL_DSI, 1 }, 175 }; 176 177 static const char * const gcc_xo_gpll0a_dsiphy[] = { 178 "xo", 179 "gpll0_vote", 180 "dsi0pll", 181 }; 182 183 static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = { 184 { P_XO, 0 }, 185 { P_GPLL0_AUX, 1 }, 186 { P_GPLL1, 3 }, 187 { P_GPLL2, 2 }, 188 }; 189 190 static const char * const gcc_xo_gpll0a_gpll1_gpll2[] = { 191 "xo", 192 "gpll0_vote", 193 "gpll1_vote", 194 "gpll2_vote", 195 }; 196 197 static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = { 198 { P_XO, 0 }, 199 { P_GPLL0, 1 }, 200 { P_GPLL1, 2 }, 201 { P_SLEEP_CLK, 6 } 202 }; 203 204 static const char * const gcc_xo_gpll0_gpll1_sleep[] = { 205 "xo", 206 "gpll0_vote", 207 "gpll1_vote", 208 "sleep_clk", 209 }; 210 211 static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = { 212 { P_XO, 0 }, 213 { P_GPLL1, 1 }, 214 { P_EXT_PRI_I2S, 2 }, 215 { P_EXT_MCLK, 3 }, 216 { P_SLEEP_CLK, 6 } 217 }; 218 219 static const char * const gcc_xo_gpll1_epi2s_emclk_sleep[] = { 220 "xo", 221 "gpll1_vote", 222 "ext_pri_i2s", 223 "ext_mclk", 224 "sleep_clk", 225 }; 226 227 static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = { 228 { P_XO, 0 }, 229 { P_GPLL1, 1 }, 230 { P_EXT_SEC_I2S, 2 }, 231 { P_EXT_MCLK, 3 }, 232 { P_SLEEP_CLK, 6 } 233 }; 234 235 static const char * const gcc_xo_gpll1_esi2s_emclk_sleep[] = { 236 "xo", 237 "gpll1_vote", 238 "ext_sec_i2s", 239 "ext_mclk", 240 "sleep_clk", 241 }; 242 243 static const struct parent_map gcc_xo_sleep_map[] = { 244 { P_XO, 0 }, 245 { P_SLEEP_CLK, 6 } 246 }; 247 248 static const char * const gcc_xo_sleep[] = { 249 "xo", 250 "sleep_clk", 251 }; 252 253 static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = { 254 { P_XO, 0 }, 255 { P_GPLL1, 1 }, 256 { P_EXT_MCLK, 2 }, 257 { P_SLEEP_CLK, 6 } 258 }; 259 260 static const char * const gcc_xo_gpll1_emclk_sleep[] = { 261 "xo", 262 "gpll1_vote", 263 "ext_mclk", 264 "sleep_clk", 265 }; 266 267 static struct clk_pll gpll0 = { 268 .l_reg = 0x21004, 269 .m_reg = 0x21008, 270 .n_reg = 0x2100c, 271 .config_reg = 0x21014, 272 .mode_reg = 0x21000, 273 .status_reg = 0x2101c, 274 .status_bit = 17, 275 .clkr.hw.init = &(struct clk_init_data){ 276 .name = "gpll0", 277 .parent_names = (const char *[]){ "xo" }, 278 .num_parents = 1, 279 .ops = &clk_pll_ops, 280 }, 281 }; 282 283 static struct clk_regmap gpll0_vote = { 284 .enable_reg = 0x45000, 285 .enable_mask = BIT(0), 286 .hw.init = &(struct clk_init_data){ 287 .name = "gpll0_vote", 288 .parent_names = (const char *[]){ "gpll0" }, 289 .num_parents = 1, 290 .ops = &clk_pll_vote_ops, 291 }, 292 }; 293 294 static struct clk_pll gpll1 = { 295 .l_reg = 0x20004, 296 .m_reg = 0x20008, 297 .n_reg = 0x2000c, 298 .config_reg = 0x20014, 299 .mode_reg = 0x20000, 300 .status_reg = 0x2001c, 301 .status_bit = 17, 302 .clkr.hw.init = &(struct clk_init_data){ 303 .name = "gpll1", 304 .parent_names = (const char *[]){ "xo" }, 305 .num_parents = 1, 306 .ops = &clk_pll_ops, 307 }, 308 }; 309 310 static struct clk_regmap gpll1_vote = { 311 .enable_reg = 0x45000, 312 .enable_mask = BIT(1), 313 .hw.init = &(struct clk_init_data){ 314 .name = "gpll1_vote", 315 .parent_names = (const char *[]){ "gpll1" }, 316 .num_parents = 1, 317 .ops = &clk_pll_vote_ops, 318 }, 319 }; 320 321 static struct clk_pll gpll2 = { 322 .l_reg = 0x4a004, 323 .m_reg = 0x4a008, 324 .n_reg = 0x4a00c, 325 .config_reg = 0x4a014, 326 .mode_reg = 0x4a000, 327 .status_reg = 0x4a01c, 328 .status_bit = 17, 329 .clkr.hw.init = &(struct clk_init_data){ 330 .name = "gpll2", 331 .parent_names = (const char *[]){ "xo" }, 332 .num_parents = 1, 333 .ops = &clk_pll_ops, 334 }, 335 }; 336 337 static struct clk_regmap gpll2_vote = { 338 .enable_reg = 0x45000, 339 .enable_mask = BIT(2), 340 .hw.init = &(struct clk_init_data){ 341 .name = "gpll2_vote", 342 .parent_names = (const char *[]){ "gpll2" }, 343 .num_parents = 1, 344 .ops = &clk_pll_vote_ops, 345 }, 346 }; 347 348 static struct clk_pll bimc_pll = { 349 .l_reg = 0x23004, 350 .m_reg = 0x23008, 351 .n_reg = 0x2300c, 352 .config_reg = 0x23014, 353 .mode_reg = 0x23000, 354 .status_reg = 0x2301c, 355 .status_bit = 17, 356 .clkr.hw.init = &(struct clk_init_data){ 357 .name = "bimc_pll", 358 .parent_names = (const char *[]){ "xo" }, 359 .num_parents = 1, 360 .ops = &clk_pll_ops, 361 }, 362 }; 363 364 static struct clk_regmap bimc_pll_vote = { 365 .enable_reg = 0x45000, 366 .enable_mask = BIT(3), 367 .hw.init = &(struct clk_init_data){ 368 .name = "bimc_pll_vote", 369 .parent_names = (const char *[]){ "bimc_pll" }, 370 .num_parents = 1, 371 .ops = &clk_pll_vote_ops, 372 }, 373 }; 374 375 static struct clk_rcg2 pcnoc_bfdcd_clk_src = { 376 .cmd_rcgr = 0x27000, 377 .hid_width = 5, 378 .parent_map = gcc_xo_gpll0_bimc_map, 379 .clkr.hw.init = &(struct clk_init_data){ 380 .name = "pcnoc_bfdcd_clk_src", 381 .parent_names = gcc_xo_gpll0_bimc, 382 .num_parents = 3, 383 .ops = &clk_rcg2_ops, 384 }, 385 }; 386 387 static struct clk_rcg2 system_noc_bfdcd_clk_src = { 388 .cmd_rcgr = 0x26004, 389 .hid_width = 5, 390 .parent_map = gcc_xo_gpll0_bimc_map, 391 .clkr.hw.init = &(struct clk_init_data){ 392 .name = "system_noc_bfdcd_clk_src", 393 .parent_names = gcc_xo_gpll0_bimc, 394 .num_parents = 3, 395 .ops = &clk_rcg2_ops, 396 }, 397 }; 398 399 static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = { 400 F(40000000, P_GPLL0, 10, 1, 2), 401 F(80000000, P_GPLL0, 10, 0, 0), 402 { } 403 }; 404 405 static struct clk_rcg2 camss_ahb_clk_src = { 406 .cmd_rcgr = 0x5a000, 407 .mnd_width = 8, 408 .hid_width = 5, 409 .parent_map = gcc_xo_gpll0_map, 410 .freq_tbl = ftbl_gcc_camss_ahb_clk, 411 .clkr.hw.init = &(struct clk_init_data){ 412 .name = "camss_ahb_clk_src", 413 .parent_names = gcc_xo_gpll0, 414 .num_parents = 2, 415 .ops = &clk_rcg2_ops, 416 }, 417 }; 418 419 static const struct freq_tbl ftbl_apss_ahb_clk[] = { 420 F(19200000, P_XO, 1, 0, 0), 421 F(50000000, P_GPLL0, 16, 0, 0), 422 F(100000000, P_GPLL0, 8, 0, 0), 423 F(133330000, P_GPLL0, 6, 0, 0), 424 { } 425 }; 426 427 static struct clk_rcg2 apss_ahb_clk_src = { 428 .cmd_rcgr = 0x46000, 429 .hid_width = 5, 430 .parent_map = gcc_xo_gpll0_map, 431 .freq_tbl = ftbl_apss_ahb_clk, 432 .clkr.hw.init = &(struct clk_init_data){ 433 .name = "apss_ahb_clk_src", 434 .parent_names = gcc_xo_gpll0, 435 .num_parents = 2, 436 .ops = &clk_rcg2_ops, 437 }, 438 }; 439 440 static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = { 441 F(100000000, P_GPLL0, 8, 0, 0), 442 F(200000000, P_GPLL0, 4, 0, 0), 443 { } 444 }; 445 446 static struct clk_rcg2 csi0_clk_src = { 447 .cmd_rcgr = 0x4e020, 448 .hid_width = 5, 449 .parent_map = gcc_xo_gpll0_map, 450 .freq_tbl = ftbl_gcc_camss_csi0_1_clk, 451 .clkr.hw.init = &(struct clk_init_data){ 452 .name = "csi0_clk_src", 453 .parent_names = gcc_xo_gpll0, 454 .num_parents = 2, 455 .ops = &clk_rcg2_ops, 456 }, 457 }; 458 459 static struct clk_rcg2 csi1_clk_src = { 460 .cmd_rcgr = 0x4f020, 461 .hid_width = 5, 462 .parent_map = gcc_xo_gpll0_map, 463 .freq_tbl = ftbl_gcc_camss_csi0_1_clk, 464 .clkr.hw.init = &(struct clk_init_data){ 465 .name = "csi1_clk_src", 466 .parent_names = gcc_xo_gpll0, 467 .num_parents = 2, 468 .ops = &clk_rcg2_ops, 469 }, 470 }; 471 472 static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = { 473 F(19200000, P_XO, 1, 0, 0), 474 F(50000000, P_GPLL0_AUX, 16, 0, 0), 475 F(80000000, P_GPLL0_AUX, 10, 0, 0), 476 F(100000000, P_GPLL0_AUX, 8, 0, 0), 477 F(160000000, P_GPLL0_AUX, 5, 0, 0), 478 F(177780000, P_GPLL0_AUX, 4.5, 0, 0), 479 F(200000000, P_GPLL0_AUX, 4, 0, 0), 480 F(266670000, P_GPLL0_AUX, 3, 0, 0), 481 F(294912000, P_GPLL1, 3, 0, 0), 482 F(310000000, P_GPLL2, 3, 0, 0), 483 F(400000000, P_GPLL0_AUX, 2, 0, 0), 484 { } 485 }; 486 487 static struct clk_rcg2 gfx3d_clk_src = { 488 .cmd_rcgr = 0x59000, 489 .hid_width = 5, 490 .parent_map = gcc_xo_gpll0a_gpll1_gpll2a_map, 491 .freq_tbl = ftbl_gcc_oxili_gfx3d_clk, 492 .clkr.hw.init = &(struct clk_init_data){ 493 .name = "gfx3d_clk_src", 494 .parent_names = gcc_xo_gpll0a_gpll1_gpll2a, 495 .num_parents = 4, 496 .ops = &clk_rcg2_ops, 497 }, 498 }; 499 500 static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = { 501 F(50000000, P_GPLL0, 16, 0, 0), 502 F(80000000, P_GPLL0, 10, 0, 0), 503 F(100000000, P_GPLL0, 8, 0, 0), 504 F(160000000, P_GPLL0, 5, 0, 0), 505 F(177780000, P_GPLL0, 4.5, 0, 0), 506 F(200000000, P_GPLL0, 4, 0, 0), 507 F(266670000, P_GPLL0, 3, 0, 0), 508 F(320000000, P_GPLL0, 2.5, 0, 0), 509 F(400000000, P_GPLL0, 2, 0, 0), 510 F(465000000, P_GPLL2, 2, 0, 0), 511 { } 512 }; 513 514 static struct clk_rcg2 vfe0_clk_src = { 515 .cmd_rcgr = 0x58000, 516 .hid_width = 5, 517 .parent_map = gcc_xo_gpll0_gpll2_map, 518 .freq_tbl = ftbl_gcc_camss_vfe0_clk, 519 .clkr.hw.init = &(struct clk_init_data){ 520 .name = "vfe0_clk_src", 521 .parent_names = gcc_xo_gpll0_gpll2, 522 .num_parents = 3, 523 .ops = &clk_rcg2_ops, 524 }, 525 }; 526 527 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = { 528 F(19200000, P_XO, 1, 0, 0), 529 F(50000000, P_GPLL0, 16, 0, 0), 530 { } 531 }; 532 533 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 534 .cmd_rcgr = 0x0200c, 535 .hid_width = 5, 536 .parent_map = gcc_xo_gpll0_map, 537 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 538 .clkr.hw.init = &(struct clk_init_data){ 539 .name = "blsp1_qup1_i2c_apps_clk_src", 540 .parent_names = gcc_xo_gpll0, 541 .num_parents = 2, 542 .ops = &clk_rcg2_ops, 543 }, 544 }; 545 546 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = { 547 F(100000, P_XO, 16, 2, 24), 548 F(250000, P_XO, 16, 5, 24), 549 F(500000, P_XO, 8, 5, 24), 550 F(960000, P_XO, 10, 1, 2), 551 F(1000000, P_XO, 4, 5, 24), 552 F(4800000, P_XO, 4, 0, 0), 553 F(9600000, P_XO, 2, 0, 0), 554 F(16000000, P_GPLL0, 10, 1, 5), 555 F(19200000, P_XO, 1, 0, 0), 556 F(25000000, P_GPLL0, 16, 1, 2), 557 F(50000000, P_GPLL0, 16, 0, 0), 558 { } 559 }; 560 561 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 562 .cmd_rcgr = 0x02024, 563 .mnd_width = 8, 564 .hid_width = 5, 565 .parent_map = gcc_xo_gpll0_map, 566 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 567 .clkr.hw.init = &(struct clk_init_data){ 568 .name = "blsp1_qup1_spi_apps_clk_src", 569 .parent_names = gcc_xo_gpll0, 570 .num_parents = 2, 571 .ops = &clk_rcg2_ops, 572 }, 573 }; 574 575 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 576 .cmd_rcgr = 0x03000, 577 .hid_width = 5, 578 .parent_map = gcc_xo_gpll0_map, 579 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 580 .clkr.hw.init = &(struct clk_init_data){ 581 .name = "blsp1_qup2_i2c_apps_clk_src", 582 .parent_names = gcc_xo_gpll0, 583 .num_parents = 2, 584 .ops = &clk_rcg2_ops, 585 }, 586 }; 587 588 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 589 .cmd_rcgr = 0x03014, 590 .mnd_width = 8, 591 .hid_width = 5, 592 .parent_map = gcc_xo_gpll0_map, 593 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 594 .clkr.hw.init = &(struct clk_init_data){ 595 .name = "blsp1_qup2_spi_apps_clk_src", 596 .parent_names = gcc_xo_gpll0, 597 .num_parents = 2, 598 .ops = &clk_rcg2_ops, 599 }, 600 }; 601 602 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 603 .cmd_rcgr = 0x04000, 604 .hid_width = 5, 605 .parent_map = gcc_xo_gpll0_map, 606 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 607 .clkr.hw.init = &(struct clk_init_data){ 608 .name = "blsp1_qup3_i2c_apps_clk_src", 609 .parent_names = gcc_xo_gpll0, 610 .num_parents = 2, 611 .ops = &clk_rcg2_ops, 612 }, 613 }; 614 615 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 616 .cmd_rcgr = 0x04024, 617 .mnd_width = 8, 618 .hid_width = 5, 619 .parent_map = gcc_xo_gpll0_map, 620 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 621 .clkr.hw.init = &(struct clk_init_data){ 622 .name = "blsp1_qup3_spi_apps_clk_src", 623 .parent_names = gcc_xo_gpll0, 624 .num_parents = 2, 625 .ops = &clk_rcg2_ops, 626 }, 627 }; 628 629 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 630 .cmd_rcgr = 0x05000, 631 .hid_width = 5, 632 .parent_map = gcc_xo_gpll0_map, 633 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 634 .clkr.hw.init = &(struct clk_init_data){ 635 .name = "blsp1_qup4_i2c_apps_clk_src", 636 .parent_names = gcc_xo_gpll0, 637 .num_parents = 2, 638 .ops = &clk_rcg2_ops, 639 }, 640 }; 641 642 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 643 .cmd_rcgr = 0x05024, 644 .mnd_width = 8, 645 .hid_width = 5, 646 .parent_map = gcc_xo_gpll0_map, 647 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 648 .clkr.hw.init = &(struct clk_init_data){ 649 .name = "blsp1_qup4_spi_apps_clk_src", 650 .parent_names = gcc_xo_gpll0, 651 .num_parents = 2, 652 .ops = &clk_rcg2_ops, 653 }, 654 }; 655 656 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 657 .cmd_rcgr = 0x06000, 658 .hid_width = 5, 659 .parent_map = gcc_xo_gpll0_map, 660 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 661 .clkr.hw.init = &(struct clk_init_data){ 662 .name = "blsp1_qup5_i2c_apps_clk_src", 663 .parent_names = gcc_xo_gpll0, 664 .num_parents = 2, 665 .ops = &clk_rcg2_ops, 666 }, 667 }; 668 669 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 670 .cmd_rcgr = 0x06024, 671 .mnd_width = 8, 672 .hid_width = 5, 673 .parent_map = gcc_xo_gpll0_map, 674 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 675 .clkr.hw.init = &(struct clk_init_data){ 676 .name = "blsp1_qup5_spi_apps_clk_src", 677 .parent_names = gcc_xo_gpll0, 678 .num_parents = 2, 679 .ops = &clk_rcg2_ops, 680 }, 681 }; 682 683 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 684 .cmd_rcgr = 0x07000, 685 .hid_width = 5, 686 .parent_map = gcc_xo_gpll0_map, 687 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 688 .clkr.hw.init = &(struct clk_init_data){ 689 .name = "blsp1_qup6_i2c_apps_clk_src", 690 .parent_names = gcc_xo_gpll0, 691 .num_parents = 2, 692 .ops = &clk_rcg2_ops, 693 }, 694 }; 695 696 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 697 .cmd_rcgr = 0x07024, 698 .mnd_width = 8, 699 .hid_width = 5, 700 .parent_map = gcc_xo_gpll0_map, 701 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 702 .clkr.hw.init = &(struct clk_init_data){ 703 .name = "blsp1_qup6_spi_apps_clk_src", 704 .parent_names = gcc_xo_gpll0, 705 .num_parents = 2, 706 .ops = &clk_rcg2_ops, 707 }, 708 }; 709 710 static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = { 711 F(3686400, P_GPLL0, 1, 72, 15625), 712 F(7372800, P_GPLL0, 1, 144, 15625), 713 F(14745600, P_GPLL0, 1, 288, 15625), 714 F(16000000, P_GPLL0, 10, 1, 5), 715 F(19200000, P_XO, 1, 0, 0), 716 F(24000000, P_GPLL0, 1, 3, 100), 717 F(25000000, P_GPLL0, 16, 1, 2), 718 F(32000000, P_GPLL0, 1, 1, 25), 719 F(40000000, P_GPLL0, 1, 1, 20), 720 F(46400000, P_GPLL0, 1, 29, 500), 721 F(48000000, P_GPLL0, 1, 3, 50), 722 F(51200000, P_GPLL0, 1, 8, 125), 723 F(56000000, P_GPLL0, 1, 7, 100), 724 F(58982400, P_GPLL0, 1, 1152, 15625), 725 F(60000000, P_GPLL0, 1, 3, 40), 726 { } 727 }; 728 729 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 730 .cmd_rcgr = 0x02044, 731 .mnd_width = 16, 732 .hid_width = 5, 733 .parent_map = gcc_xo_gpll0_map, 734 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, 735 .clkr.hw.init = &(struct clk_init_data){ 736 .name = "blsp1_uart1_apps_clk_src", 737 .parent_names = gcc_xo_gpll0, 738 .num_parents = 2, 739 .ops = &clk_rcg2_ops, 740 }, 741 }; 742 743 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 744 .cmd_rcgr = 0x03034, 745 .mnd_width = 16, 746 .hid_width = 5, 747 .parent_map = gcc_xo_gpll0_map, 748 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, 749 .clkr.hw.init = &(struct clk_init_data){ 750 .name = "blsp1_uart2_apps_clk_src", 751 .parent_names = gcc_xo_gpll0, 752 .num_parents = 2, 753 .ops = &clk_rcg2_ops, 754 }, 755 }; 756 757 static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = { 758 F(19200000, P_XO, 1, 0, 0), 759 { } 760 }; 761 762 static struct clk_rcg2 cci_clk_src = { 763 .cmd_rcgr = 0x51000, 764 .mnd_width = 8, 765 .hid_width = 5, 766 .parent_map = gcc_xo_gpll0a_map, 767 .freq_tbl = ftbl_gcc_camss_cci_clk, 768 .clkr.hw.init = &(struct clk_init_data){ 769 .name = "cci_clk_src", 770 .parent_names = gcc_xo_gpll0a, 771 .num_parents = 2, 772 .ops = &clk_rcg2_ops, 773 }, 774 }; 775 776 static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = { 777 F(100000000, P_GPLL0, 8, 0, 0), 778 F(200000000, P_GPLL0, 4, 0, 0), 779 { } 780 }; 781 782 static struct clk_rcg2 camss_gp0_clk_src = { 783 .cmd_rcgr = 0x54000, 784 .mnd_width = 8, 785 .hid_width = 5, 786 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 787 .freq_tbl = ftbl_gcc_camss_gp0_1_clk, 788 .clkr.hw.init = &(struct clk_init_data){ 789 .name = "camss_gp0_clk_src", 790 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 791 .num_parents = 4, 792 .ops = &clk_rcg2_ops, 793 }, 794 }; 795 796 static struct clk_rcg2 camss_gp1_clk_src = { 797 .cmd_rcgr = 0x55000, 798 .mnd_width = 8, 799 .hid_width = 5, 800 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 801 .freq_tbl = ftbl_gcc_camss_gp0_1_clk, 802 .clkr.hw.init = &(struct clk_init_data){ 803 .name = "camss_gp1_clk_src", 804 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 805 .num_parents = 4, 806 .ops = &clk_rcg2_ops, 807 }, 808 }; 809 810 static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = { 811 F(133330000, P_GPLL0, 6, 0, 0), 812 F(266670000, P_GPLL0, 3, 0, 0), 813 F(320000000, P_GPLL0, 2.5, 0, 0), 814 { } 815 }; 816 817 static struct clk_rcg2 jpeg0_clk_src = { 818 .cmd_rcgr = 0x57000, 819 .hid_width = 5, 820 .parent_map = gcc_xo_gpll0_map, 821 .freq_tbl = ftbl_gcc_camss_jpeg0_clk, 822 .clkr.hw.init = &(struct clk_init_data){ 823 .name = "jpeg0_clk_src", 824 .parent_names = gcc_xo_gpll0, 825 .num_parents = 2, 826 .ops = &clk_rcg2_ops, 827 }, 828 }; 829 830 static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = { 831 F(9600000, P_XO, 2, 0, 0), 832 F(23880000, P_GPLL0, 1, 2, 67), 833 F(66670000, P_GPLL0, 12, 0, 0), 834 { } 835 }; 836 837 static struct clk_rcg2 mclk0_clk_src = { 838 .cmd_rcgr = 0x52000, 839 .mnd_width = 8, 840 .hid_width = 5, 841 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 842 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk, 843 .clkr.hw.init = &(struct clk_init_data){ 844 .name = "mclk0_clk_src", 845 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 846 .num_parents = 4, 847 .ops = &clk_rcg2_ops, 848 }, 849 }; 850 851 static struct clk_rcg2 mclk1_clk_src = { 852 .cmd_rcgr = 0x53000, 853 .mnd_width = 8, 854 .hid_width = 5, 855 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 856 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk, 857 .clkr.hw.init = &(struct clk_init_data){ 858 .name = "mclk1_clk_src", 859 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 860 .num_parents = 4, 861 .ops = &clk_rcg2_ops, 862 }, 863 }; 864 865 static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = { 866 F(100000000, P_GPLL0, 8, 0, 0), 867 F(200000000, P_GPLL0, 4, 0, 0), 868 { } 869 }; 870 871 static struct clk_rcg2 csi0phytimer_clk_src = { 872 .cmd_rcgr = 0x4e000, 873 .hid_width = 5, 874 .parent_map = gcc_xo_gpll0_gpll1a_map, 875 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk, 876 .clkr.hw.init = &(struct clk_init_data){ 877 .name = "csi0phytimer_clk_src", 878 .parent_names = gcc_xo_gpll0_gpll1a, 879 .num_parents = 3, 880 .ops = &clk_rcg2_ops, 881 }, 882 }; 883 884 static struct clk_rcg2 csi1phytimer_clk_src = { 885 .cmd_rcgr = 0x4f000, 886 .hid_width = 5, 887 .parent_map = gcc_xo_gpll0_gpll1a_map, 888 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk, 889 .clkr.hw.init = &(struct clk_init_data){ 890 .name = "csi1phytimer_clk_src", 891 .parent_names = gcc_xo_gpll0_gpll1a, 892 .num_parents = 3, 893 .ops = &clk_rcg2_ops, 894 }, 895 }; 896 897 static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = { 898 F(160000000, P_GPLL0, 5, 0, 0), 899 F(320000000, P_GPLL0, 2.5, 0, 0), 900 F(465000000, P_GPLL2, 2, 0, 0), 901 { } 902 }; 903 904 static struct clk_rcg2 cpp_clk_src = { 905 .cmd_rcgr = 0x58018, 906 .hid_width = 5, 907 .parent_map = gcc_xo_gpll0_gpll2_map, 908 .freq_tbl = ftbl_gcc_camss_cpp_clk, 909 .clkr.hw.init = &(struct clk_init_data){ 910 .name = "cpp_clk_src", 911 .parent_names = gcc_xo_gpll0_gpll2, 912 .num_parents = 3, 913 .ops = &clk_rcg2_ops, 914 }, 915 }; 916 917 static const struct freq_tbl ftbl_gcc_crypto_clk[] = { 918 F(50000000, P_GPLL0, 16, 0, 0), 919 F(80000000, P_GPLL0, 10, 0, 0), 920 F(100000000, P_GPLL0, 8, 0, 0), 921 F(160000000, P_GPLL0, 5, 0, 0), 922 { } 923 }; 924 925 static struct clk_rcg2 crypto_clk_src = { 926 .cmd_rcgr = 0x16004, 927 .hid_width = 5, 928 .parent_map = gcc_xo_gpll0_map, 929 .freq_tbl = ftbl_gcc_crypto_clk, 930 .clkr.hw.init = &(struct clk_init_data){ 931 .name = "crypto_clk_src", 932 .parent_names = gcc_xo_gpll0, 933 .num_parents = 2, 934 .ops = &clk_rcg2_ops, 935 }, 936 }; 937 938 static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = { 939 F(19200000, P_XO, 1, 0, 0), 940 { } 941 }; 942 943 static struct clk_rcg2 gp1_clk_src = { 944 .cmd_rcgr = 0x08004, 945 .mnd_width = 8, 946 .hid_width = 5, 947 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 948 .freq_tbl = ftbl_gcc_gp1_3_clk, 949 .clkr.hw.init = &(struct clk_init_data){ 950 .name = "gp1_clk_src", 951 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 952 .num_parents = 3, 953 .ops = &clk_rcg2_ops, 954 }, 955 }; 956 957 static struct clk_rcg2 gp2_clk_src = { 958 .cmd_rcgr = 0x09004, 959 .mnd_width = 8, 960 .hid_width = 5, 961 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 962 .freq_tbl = ftbl_gcc_gp1_3_clk, 963 .clkr.hw.init = &(struct clk_init_data){ 964 .name = "gp2_clk_src", 965 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 966 .num_parents = 3, 967 .ops = &clk_rcg2_ops, 968 }, 969 }; 970 971 static struct clk_rcg2 gp3_clk_src = { 972 .cmd_rcgr = 0x0a004, 973 .mnd_width = 8, 974 .hid_width = 5, 975 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 976 .freq_tbl = ftbl_gcc_gp1_3_clk, 977 .clkr.hw.init = &(struct clk_init_data){ 978 .name = "gp3_clk_src", 979 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 980 .num_parents = 3, 981 .ops = &clk_rcg2_ops, 982 }, 983 }; 984 985 static struct clk_rcg2 byte0_clk_src = { 986 .cmd_rcgr = 0x4d044, 987 .hid_width = 5, 988 .parent_map = gcc_xo_gpll0a_dsibyte_map, 989 .clkr.hw.init = &(struct clk_init_data){ 990 .name = "byte0_clk_src", 991 .parent_names = gcc_xo_gpll0a_dsibyte, 992 .num_parents = 3, 993 .ops = &clk_byte2_ops, 994 .flags = CLK_SET_RATE_PARENT, 995 }, 996 }; 997 998 static const struct freq_tbl ftbl_gcc_mdss_esc0_clk[] = { 999 F(19200000, P_XO, 1, 0, 0), 1000 { } 1001 }; 1002 1003 static struct clk_rcg2 esc0_clk_src = { 1004 .cmd_rcgr = 0x4d05c, 1005 .hid_width = 5, 1006 .parent_map = gcc_xo_dsibyte_map, 1007 .freq_tbl = ftbl_gcc_mdss_esc0_clk, 1008 .clkr.hw.init = &(struct clk_init_data){ 1009 .name = "esc0_clk_src", 1010 .parent_names = gcc_xo_dsibyte, 1011 .num_parents = 2, 1012 .ops = &clk_rcg2_ops, 1013 }, 1014 }; 1015 1016 static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = { 1017 F(50000000, P_GPLL0, 16, 0, 0), 1018 F(80000000, P_GPLL0, 10, 0, 0), 1019 F(100000000, P_GPLL0, 8, 0, 0), 1020 F(160000000, P_GPLL0, 5, 0, 0), 1021 F(177780000, P_GPLL0, 4.5, 0, 0), 1022 F(200000000, P_GPLL0, 4, 0, 0), 1023 F(266670000, P_GPLL0, 3, 0, 0), 1024 F(320000000, P_GPLL0, 2.5, 0, 0), 1025 { } 1026 }; 1027 1028 static struct clk_rcg2 mdp_clk_src = { 1029 .cmd_rcgr = 0x4d014, 1030 .hid_width = 5, 1031 .parent_map = gcc_xo_gpll0_dsiphy_map, 1032 .freq_tbl = ftbl_gcc_mdss_mdp_clk, 1033 .clkr.hw.init = &(struct clk_init_data){ 1034 .name = "mdp_clk_src", 1035 .parent_names = gcc_xo_gpll0_dsiphy, 1036 .num_parents = 3, 1037 .ops = &clk_rcg2_ops, 1038 }, 1039 }; 1040 1041 static struct clk_rcg2 pclk0_clk_src = { 1042 .cmd_rcgr = 0x4d000, 1043 .mnd_width = 8, 1044 .hid_width = 5, 1045 .parent_map = gcc_xo_gpll0a_dsiphy_map, 1046 .clkr.hw.init = &(struct clk_init_data){ 1047 .name = "pclk0_clk_src", 1048 .parent_names = gcc_xo_gpll0a_dsiphy, 1049 .num_parents = 3, 1050 .ops = &clk_pixel_ops, 1051 .flags = CLK_SET_RATE_PARENT, 1052 }, 1053 }; 1054 1055 static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = { 1056 F(19200000, P_XO, 1, 0, 0), 1057 { } 1058 }; 1059 1060 static struct clk_rcg2 vsync_clk_src = { 1061 .cmd_rcgr = 0x4d02c, 1062 .hid_width = 5, 1063 .parent_map = gcc_xo_gpll0a_map, 1064 .freq_tbl = ftbl_gcc_mdss_vsync_clk, 1065 .clkr.hw.init = &(struct clk_init_data){ 1066 .name = "vsync_clk_src", 1067 .parent_names = gcc_xo_gpll0a, 1068 .num_parents = 2, 1069 .ops = &clk_rcg2_ops, 1070 }, 1071 }; 1072 1073 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = { 1074 F(64000000, P_GPLL0, 12.5, 0, 0), 1075 { } 1076 }; 1077 1078 static struct clk_rcg2 pdm2_clk_src = { 1079 .cmd_rcgr = 0x44010, 1080 .hid_width = 5, 1081 .parent_map = gcc_xo_gpll0_map, 1082 .freq_tbl = ftbl_gcc_pdm2_clk, 1083 .clkr.hw.init = &(struct clk_init_data){ 1084 .name = "pdm2_clk_src", 1085 .parent_names = gcc_xo_gpll0, 1086 .num_parents = 2, 1087 .ops = &clk_rcg2_ops, 1088 }, 1089 }; 1090 1091 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = { 1092 F(144000, P_XO, 16, 3, 25), 1093 F(400000, P_XO, 12, 1, 4), 1094 F(20000000, P_GPLL0, 10, 1, 4), 1095 F(25000000, P_GPLL0, 16, 1, 2), 1096 F(50000000, P_GPLL0, 16, 0, 0), 1097 F(100000000, P_GPLL0, 8, 0, 0), 1098 F(177770000, P_GPLL0, 4.5, 0, 0), 1099 { } 1100 }; 1101 1102 static struct clk_rcg2 sdcc1_apps_clk_src = { 1103 .cmd_rcgr = 0x42004, 1104 .mnd_width = 8, 1105 .hid_width = 5, 1106 .parent_map = gcc_xo_gpll0_map, 1107 .freq_tbl = ftbl_gcc_sdcc1_apps_clk, 1108 .clkr.hw.init = &(struct clk_init_data){ 1109 .name = "sdcc1_apps_clk_src", 1110 .parent_names = gcc_xo_gpll0, 1111 .num_parents = 2, 1112 .ops = &clk_rcg2_floor_ops, 1113 }, 1114 }; 1115 1116 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk[] = { 1117 F(144000, P_XO, 16, 3, 25), 1118 F(400000, P_XO, 12, 1, 4), 1119 F(20000000, P_GPLL0, 10, 1, 4), 1120 F(25000000, P_GPLL0, 16, 1, 2), 1121 F(50000000, P_GPLL0, 16, 0, 0), 1122 F(100000000, P_GPLL0, 8, 0, 0), 1123 F(200000000, P_GPLL0, 4, 0, 0), 1124 { } 1125 }; 1126 1127 static struct clk_rcg2 sdcc2_apps_clk_src = { 1128 .cmd_rcgr = 0x43004, 1129 .mnd_width = 8, 1130 .hid_width = 5, 1131 .parent_map = gcc_xo_gpll0_map, 1132 .freq_tbl = ftbl_gcc_sdcc2_apps_clk, 1133 .clkr.hw.init = &(struct clk_init_data){ 1134 .name = "sdcc2_apps_clk_src", 1135 .parent_names = gcc_xo_gpll0, 1136 .num_parents = 2, 1137 .ops = &clk_rcg2_floor_ops, 1138 }, 1139 }; 1140 1141 static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = { 1142 F(155000000, P_GPLL2, 6, 0, 0), 1143 F(310000000, P_GPLL2, 3, 0, 0), 1144 F(400000000, P_GPLL0, 2, 0, 0), 1145 { } 1146 }; 1147 1148 static struct clk_rcg2 apss_tcu_clk_src = { 1149 .cmd_rcgr = 0x1207c, 1150 .hid_width = 5, 1151 .parent_map = gcc_xo_gpll0a_gpll1_gpll2_map, 1152 .freq_tbl = ftbl_gcc_apss_tcu_clk, 1153 .clkr.hw.init = &(struct clk_init_data){ 1154 .name = "apss_tcu_clk_src", 1155 .parent_names = gcc_xo_gpll0a_gpll1_gpll2, 1156 .num_parents = 4, 1157 .ops = &clk_rcg2_ops, 1158 }, 1159 }; 1160 1161 static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = { 1162 F(19200000, P_XO, 1, 0, 0), 1163 F(100000000, P_GPLL0, 8, 0, 0), 1164 F(200000000, P_GPLL0, 4, 0, 0), 1165 F(266500000, P_BIMC, 4, 0, 0), 1166 F(400000000, P_GPLL0, 2, 0, 0), 1167 F(533000000, P_BIMC, 2, 0, 0), 1168 { } 1169 }; 1170 1171 static struct clk_rcg2 bimc_gpu_clk_src = { 1172 .cmd_rcgr = 0x31028, 1173 .hid_width = 5, 1174 .parent_map = gcc_xo_gpll0_bimc_map, 1175 .freq_tbl = ftbl_gcc_bimc_gpu_clk, 1176 .clkr.hw.init = &(struct clk_init_data){ 1177 .name = "bimc_gpu_clk_src", 1178 .parent_names = gcc_xo_gpll0_bimc, 1179 .num_parents = 3, 1180 .flags = CLK_GET_RATE_NOCACHE, 1181 .ops = &clk_rcg2_ops, 1182 }, 1183 }; 1184 1185 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { 1186 F(80000000, P_GPLL0, 10, 0, 0), 1187 { } 1188 }; 1189 1190 static struct clk_rcg2 usb_hs_system_clk_src = { 1191 .cmd_rcgr = 0x41010, 1192 .hid_width = 5, 1193 .parent_map = gcc_xo_gpll0_map, 1194 .freq_tbl = ftbl_gcc_usb_hs_system_clk, 1195 .clkr.hw.init = &(struct clk_init_data){ 1196 .name = "usb_hs_system_clk_src", 1197 .parent_names = gcc_xo_gpll0, 1198 .num_parents = 2, 1199 .ops = &clk_rcg2_ops, 1200 }, 1201 }; 1202 1203 static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = { 1204 F(3200000, P_XO, 6, 0, 0), 1205 F(6400000, P_XO, 3, 0, 0), 1206 F(9600000, P_XO, 2, 0, 0), 1207 F(19200000, P_XO, 1, 0, 0), 1208 F(40000000, P_GPLL0, 10, 1, 2), 1209 F(66670000, P_GPLL0, 12, 0, 0), 1210 F(80000000, P_GPLL0, 10, 0, 0), 1211 F(100000000, P_GPLL0, 8, 0, 0), 1212 { } 1213 }; 1214 1215 static struct clk_rcg2 ultaudio_ahbfabric_clk_src = { 1216 .cmd_rcgr = 0x1c010, 1217 .hid_width = 5, 1218 .mnd_width = 8, 1219 .parent_map = gcc_xo_gpll0_gpll1_sleep_map, 1220 .freq_tbl = ftbl_gcc_ultaudio_ahb_clk, 1221 .clkr.hw.init = &(struct clk_init_data){ 1222 .name = "ultaudio_ahbfabric_clk_src", 1223 .parent_names = gcc_xo_gpll0_gpll1_sleep, 1224 .num_parents = 4, 1225 .ops = &clk_rcg2_ops, 1226 }, 1227 }; 1228 1229 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = { 1230 .halt_reg = 0x1c028, 1231 .clkr = { 1232 .enable_reg = 0x1c028, 1233 .enable_mask = BIT(0), 1234 .hw.init = &(struct clk_init_data){ 1235 .name = "gcc_ultaudio_ahbfabric_ixfabric_clk", 1236 .parent_names = (const char *[]){ 1237 "ultaudio_ahbfabric_clk_src", 1238 }, 1239 .num_parents = 1, 1240 .flags = CLK_SET_RATE_PARENT, 1241 .ops = &clk_branch2_ops, 1242 }, 1243 }, 1244 }; 1245 1246 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = { 1247 .halt_reg = 0x1c024, 1248 .clkr = { 1249 .enable_reg = 0x1c024, 1250 .enable_mask = BIT(0), 1251 .hw.init = &(struct clk_init_data){ 1252 .name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk", 1253 .parent_names = (const char *[]){ 1254 "ultaudio_ahbfabric_clk_src", 1255 }, 1256 .num_parents = 1, 1257 .flags = CLK_SET_RATE_PARENT, 1258 .ops = &clk_branch2_ops, 1259 }, 1260 }, 1261 }; 1262 1263 static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = { 1264 F(128000, P_XO, 10, 1, 15), 1265 F(256000, P_XO, 5, 1, 15), 1266 F(384000, P_XO, 5, 1, 10), 1267 F(512000, P_XO, 5, 2, 15), 1268 F(576000, P_XO, 5, 3, 20), 1269 F(705600, P_GPLL1, 16, 1, 80), 1270 F(768000, P_XO, 5, 1, 5), 1271 F(800000, P_XO, 5, 5, 24), 1272 F(1024000, P_XO, 5, 4, 15), 1273 F(1152000, P_XO, 1, 3, 50), 1274 F(1411200, P_GPLL1, 16, 1, 40), 1275 F(1536000, P_XO, 1, 2, 25), 1276 F(1600000, P_XO, 12, 0, 0), 1277 F(1728000, P_XO, 5, 9, 20), 1278 F(2048000, P_XO, 5, 8, 15), 1279 F(2304000, P_XO, 5, 3, 5), 1280 F(2400000, P_XO, 8, 0, 0), 1281 F(2822400, P_GPLL1, 16, 1, 20), 1282 F(3072000, P_XO, 5, 4, 5), 1283 F(4096000, P_GPLL1, 9, 2, 49), 1284 F(4800000, P_XO, 4, 0, 0), 1285 F(5644800, P_GPLL1, 16, 1, 10), 1286 F(6144000, P_GPLL1, 7, 1, 21), 1287 F(8192000, P_GPLL1, 9, 4, 49), 1288 F(9600000, P_XO, 2, 0, 0), 1289 F(11289600, P_GPLL1, 16, 1, 5), 1290 F(12288000, P_GPLL1, 7, 2, 21), 1291 { } 1292 }; 1293 1294 static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = { 1295 .cmd_rcgr = 0x1c054, 1296 .hid_width = 5, 1297 .mnd_width = 8, 1298 .parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map, 1299 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, 1300 .clkr.hw.init = &(struct clk_init_data){ 1301 .name = "ultaudio_lpaif_pri_i2s_clk_src", 1302 .parent_names = gcc_xo_gpll1_epi2s_emclk_sleep, 1303 .num_parents = 5, 1304 .ops = &clk_rcg2_ops, 1305 }, 1306 }; 1307 1308 static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = { 1309 .halt_reg = 0x1c068, 1310 .clkr = { 1311 .enable_reg = 0x1c068, 1312 .enable_mask = BIT(0), 1313 .hw.init = &(struct clk_init_data){ 1314 .name = "gcc_ultaudio_lpaif_pri_i2s_clk", 1315 .parent_names = (const char *[]){ 1316 "ultaudio_lpaif_pri_i2s_clk_src", 1317 }, 1318 .num_parents = 1, 1319 .flags = CLK_SET_RATE_PARENT, 1320 .ops = &clk_branch2_ops, 1321 }, 1322 }, 1323 }; 1324 1325 static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = { 1326 .cmd_rcgr = 0x1c06c, 1327 .hid_width = 5, 1328 .mnd_width = 8, 1329 .parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map, 1330 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, 1331 .clkr.hw.init = &(struct clk_init_data){ 1332 .name = "ultaudio_lpaif_sec_i2s_clk_src", 1333 .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep, 1334 .num_parents = 5, 1335 .ops = &clk_rcg2_ops, 1336 }, 1337 }; 1338 1339 static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = { 1340 .halt_reg = 0x1c080, 1341 .clkr = { 1342 .enable_reg = 0x1c080, 1343 .enable_mask = BIT(0), 1344 .hw.init = &(struct clk_init_data){ 1345 .name = "gcc_ultaudio_lpaif_sec_i2s_clk", 1346 .parent_names = (const char *[]){ 1347 "ultaudio_lpaif_sec_i2s_clk_src", 1348 }, 1349 .num_parents = 1, 1350 .flags = CLK_SET_RATE_PARENT, 1351 .ops = &clk_branch2_ops, 1352 }, 1353 }, 1354 }; 1355 1356 static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = { 1357 .cmd_rcgr = 0x1c084, 1358 .hid_width = 5, 1359 .mnd_width = 8, 1360 .parent_map = gcc_xo_gpll1_emclk_sleep_map, 1361 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, 1362 .clkr.hw.init = &(struct clk_init_data){ 1363 .name = "ultaudio_lpaif_aux_i2s_clk_src", 1364 .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep, 1365 .num_parents = 5, 1366 .ops = &clk_rcg2_ops, 1367 }, 1368 }; 1369 1370 static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = { 1371 .halt_reg = 0x1c098, 1372 .clkr = { 1373 .enable_reg = 0x1c098, 1374 .enable_mask = BIT(0), 1375 .hw.init = &(struct clk_init_data){ 1376 .name = "gcc_ultaudio_lpaif_aux_i2s_clk", 1377 .parent_names = (const char *[]){ 1378 "ultaudio_lpaif_aux_i2s_clk_src", 1379 }, 1380 .num_parents = 1, 1381 .flags = CLK_SET_RATE_PARENT, 1382 .ops = &clk_branch2_ops, 1383 }, 1384 }, 1385 }; 1386 1387 static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = { 1388 F(19200000, P_XO, 1, 0, 0), 1389 { } 1390 }; 1391 1392 static struct clk_rcg2 ultaudio_xo_clk_src = { 1393 .cmd_rcgr = 0x1c034, 1394 .hid_width = 5, 1395 .parent_map = gcc_xo_sleep_map, 1396 .freq_tbl = ftbl_gcc_ultaudio_xo_clk, 1397 .clkr.hw.init = &(struct clk_init_data){ 1398 .name = "ultaudio_xo_clk_src", 1399 .parent_names = gcc_xo_sleep, 1400 .num_parents = 2, 1401 .ops = &clk_rcg2_ops, 1402 }, 1403 }; 1404 1405 static struct clk_branch gcc_ultaudio_avsync_xo_clk = { 1406 .halt_reg = 0x1c04c, 1407 .clkr = { 1408 .enable_reg = 0x1c04c, 1409 .enable_mask = BIT(0), 1410 .hw.init = &(struct clk_init_data){ 1411 .name = "gcc_ultaudio_avsync_xo_clk", 1412 .parent_names = (const char *[]){ 1413 "ultaudio_xo_clk_src", 1414 }, 1415 .num_parents = 1, 1416 .flags = CLK_SET_RATE_PARENT, 1417 .ops = &clk_branch2_ops, 1418 }, 1419 }, 1420 }; 1421 1422 static struct clk_branch gcc_ultaudio_stc_xo_clk = { 1423 .halt_reg = 0x1c050, 1424 .clkr = { 1425 .enable_reg = 0x1c050, 1426 .enable_mask = BIT(0), 1427 .hw.init = &(struct clk_init_data){ 1428 .name = "gcc_ultaudio_stc_xo_clk", 1429 .parent_names = (const char *[]){ 1430 "ultaudio_xo_clk_src", 1431 }, 1432 .num_parents = 1, 1433 .flags = CLK_SET_RATE_PARENT, 1434 .ops = &clk_branch2_ops, 1435 }, 1436 }, 1437 }; 1438 1439 static const struct freq_tbl ftbl_codec_clk[] = { 1440 F(9600000, P_XO, 2, 0, 0), 1441 F(12288000, P_XO, 1, 16, 25), 1442 F(19200000, P_XO, 1, 0, 0), 1443 F(11289600, P_EXT_MCLK, 1, 0, 0), 1444 { } 1445 }; 1446 1447 static struct clk_rcg2 codec_digcodec_clk_src = { 1448 .cmd_rcgr = 0x1c09c, 1449 .mnd_width = 8, 1450 .hid_width = 5, 1451 .parent_map = gcc_xo_gpll1_emclk_sleep_map, 1452 .freq_tbl = ftbl_codec_clk, 1453 .clkr.hw.init = &(struct clk_init_data){ 1454 .name = "codec_digcodec_clk_src", 1455 .parent_names = gcc_xo_gpll1_emclk_sleep, 1456 .num_parents = 4, 1457 .ops = &clk_rcg2_ops, 1458 }, 1459 }; 1460 1461 static struct clk_branch gcc_codec_digcodec_clk = { 1462 .halt_reg = 0x1c0b0, 1463 .clkr = { 1464 .enable_reg = 0x1c0b0, 1465 .enable_mask = BIT(0), 1466 .hw.init = &(struct clk_init_data){ 1467 .name = "gcc_ultaudio_codec_digcodec_clk", 1468 .parent_names = (const char *[]){ 1469 "codec_digcodec_clk_src", 1470 }, 1471 .num_parents = 1, 1472 .flags = CLK_SET_RATE_PARENT, 1473 .ops = &clk_branch2_ops, 1474 }, 1475 }, 1476 }; 1477 1478 static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = { 1479 .halt_reg = 0x1c000, 1480 .clkr = { 1481 .enable_reg = 0x1c000, 1482 .enable_mask = BIT(0), 1483 .hw.init = &(struct clk_init_data){ 1484 .name = "gcc_ultaudio_pcnoc_mport_clk", 1485 .parent_names = (const char *[]){ 1486 "pcnoc_bfdcd_clk_src", 1487 }, 1488 .num_parents = 1, 1489 .ops = &clk_branch2_ops, 1490 }, 1491 }, 1492 }; 1493 1494 static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = { 1495 .halt_reg = 0x1c004, 1496 .clkr = { 1497 .enable_reg = 0x1c004, 1498 .enable_mask = BIT(0), 1499 .hw.init = &(struct clk_init_data){ 1500 .name = "gcc_ultaudio_pcnoc_sway_clk", 1501 .parent_names = (const char *[]){ 1502 "pcnoc_bfdcd_clk_src", 1503 }, 1504 .num_parents = 1, 1505 .ops = &clk_branch2_ops, 1506 }, 1507 }, 1508 }; 1509 1510 static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = { 1511 F(100000000, P_GPLL0, 8, 0, 0), 1512 F(160000000, P_GPLL0, 5, 0, 0), 1513 F(228570000, P_GPLL0, 3.5, 0, 0), 1514 { } 1515 }; 1516 1517 static struct clk_rcg2 vcodec0_clk_src = { 1518 .cmd_rcgr = 0x4C000, 1519 .mnd_width = 8, 1520 .hid_width = 5, 1521 .parent_map = gcc_xo_gpll0_map, 1522 .freq_tbl = ftbl_gcc_venus0_vcodec0_clk, 1523 .clkr.hw.init = &(struct clk_init_data){ 1524 .name = "vcodec0_clk_src", 1525 .parent_names = gcc_xo_gpll0, 1526 .num_parents = 2, 1527 .ops = &clk_rcg2_ops, 1528 }, 1529 }; 1530 1531 static struct clk_branch gcc_blsp1_ahb_clk = { 1532 .halt_reg = 0x01008, 1533 .halt_check = BRANCH_HALT_VOTED, 1534 .clkr = { 1535 .enable_reg = 0x45004, 1536 .enable_mask = BIT(10), 1537 .hw.init = &(struct clk_init_data){ 1538 .name = "gcc_blsp1_ahb_clk", 1539 .parent_names = (const char *[]){ 1540 "pcnoc_bfdcd_clk_src", 1541 }, 1542 .num_parents = 1, 1543 .ops = &clk_branch2_ops, 1544 }, 1545 }, 1546 }; 1547 1548 static struct clk_branch gcc_blsp1_sleep_clk = { 1549 .halt_reg = 0x01004, 1550 .clkr = { 1551 .enable_reg = 0x01004, 1552 .enable_mask = BIT(0), 1553 .hw.init = &(struct clk_init_data){ 1554 .name = "gcc_blsp1_sleep_clk", 1555 .parent_names = (const char *[]){ 1556 "sleep_clk_src", 1557 }, 1558 .num_parents = 1, 1559 .flags = CLK_SET_RATE_PARENT, 1560 .ops = &clk_branch2_ops, 1561 }, 1562 }, 1563 }; 1564 1565 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1566 .halt_reg = 0x02008, 1567 .clkr = { 1568 .enable_reg = 0x02008, 1569 .enable_mask = BIT(0), 1570 .hw.init = &(struct clk_init_data){ 1571 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1572 .parent_names = (const char *[]){ 1573 "blsp1_qup1_i2c_apps_clk_src", 1574 }, 1575 .num_parents = 1, 1576 .flags = CLK_SET_RATE_PARENT, 1577 .ops = &clk_branch2_ops, 1578 }, 1579 }, 1580 }; 1581 1582 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1583 .halt_reg = 0x02004, 1584 .clkr = { 1585 .enable_reg = 0x02004, 1586 .enable_mask = BIT(0), 1587 .hw.init = &(struct clk_init_data){ 1588 .name = "gcc_blsp1_qup1_spi_apps_clk", 1589 .parent_names = (const char *[]){ 1590 "blsp1_qup1_spi_apps_clk_src", 1591 }, 1592 .num_parents = 1, 1593 .flags = CLK_SET_RATE_PARENT, 1594 .ops = &clk_branch2_ops, 1595 }, 1596 }, 1597 }; 1598 1599 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1600 .halt_reg = 0x03010, 1601 .clkr = { 1602 .enable_reg = 0x03010, 1603 .enable_mask = BIT(0), 1604 .hw.init = &(struct clk_init_data){ 1605 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1606 .parent_names = (const char *[]){ 1607 "blsp1_qup2_i2c_apps_clk_src", 1608 }, 1609 .num_parents = 1, 1610 .flags = CLK_SET_RATE_PARENT, 1611 .ops = &clk_branch2_ops, 1612 }, 1613 }, 1614 }; 1615 1616 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1617 .halt_reg = 0x0300c, 1618 .clkr = { 1619 .enable_reg = 0x0300c, 1620 .enable_mask = BIT(0), 1621 .hw.init = &(struct clk_init_data){ 1622 .name = "gcc_blsp1_qup2_spi_apps_clk", 1623 .parent_names = (const char *[]){ 1624 "blsp1_qup2_spi_apps_clk_src", 1625 }, 1626 .num_parents = 1, 1627 .flags = CLK_SET_RATE_PARENT, 1628 .ops = &clk_branch2_ops, 1629 }, 1630 }, 1631 }; 1632 1633 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1634 .halt_reg = 0x04020, 1635 .clkr = { 1636 .enable_reg = 0x04020, 1637 .enable_mask = BIT(0), 1638 .hw.init = &(struct clk_init_data){ 1639 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1640 .parent_names = (const char *[]){ 1641 "blsp1_qup3_i2c_apps_clk_src", 1642 }, 1643 .num_parents = 1, 1644 .flags = CLK_SET_RATE_PARENT, 1645 .ops = &clk_branch2_ops, 1646 }, 1647 }, 1648 }; 1649 1650 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1651 .halt_reg = 0x0401c, 1652 .clkr = { 1653 .enable_reg = 0x0401c, 1654 .enable_mask = BIT(0), 1655 .hw.init = &(struct clk_init_data){ 1656 .name = "gcc_blsp1_qup3_spi_apps_clk", 1657 .parent_names = (const char *[]){ 1658 "blsp1_qup3_spi_apps_clk_src", 1659 }, 1660 .num_parents = 1, 1661 .flags = CLK_SET_RATE_PARENT, 1662 .ops = &clk_branch2_ops, 1663 }, 1664 }, 1665 }; 1666 1667 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1668 .halt_reg = 0x05020, 1669 .clkr = { 1670 .enable_reg = 0x05020, 1671 .enable_mask = BIT(0), 1672 .hw.init = &(struct clk_init_data){ 1673 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1674 .parent_names = (const char *[]){ 1675 "blsp1_qup4_i2c_apps_clk_src", 1676 }, 1677 .num_parents = 1, 1678 .flags = CLK_SET_RATE_PARENT, 1679 .ops = &clk_branch2_ops, 1680 }, 1681 }, 1682 }; 1683 1684 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1685 .halt_reg = 0x0501c, 1686 .clkr = { 1687 .enable_reg = 0x0501c, 1688 .enable_mask = BIT(0), 1689 .hw.init = &(struct clk_init_data){ 1690 .name = "gcc_blsp1_qup4_spi_apps_clk", 1691 .parent_names = (const char *[]){ 1692 "blsp1_qup4_spi_apps_clk_src", 1693 }, 1694 .num_parents = 1, 1695 .flags = CLK_SET_RATE_PARENT, 1696 .ops = &clk_branch2_ops, 1697 }, 1698 }, 1699 }; 1700 1701 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 1702 .halt_reg = 0x06020, 1703 .clkr = { 1704 .enable_reg = 0x06020, 1705 .enable_mask = BIT(0), 1706 .hw.init = &(struct clk_init_data){ 1707 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1708 .parent_names = (const char *[]){ 1709 "blsp1_qup5_i2c_apps_clk_src", 1710 }, 1711 .num_parents = 1, 1712 .flags = CLK_SET_RATE_PARENT, 1713 .ops = &clk_branch2_ops, 1714 }, 1715 }, 1716 }; 1717 1718 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 1719 .halt_reg = 0x0601c, 1720 .clkr = { 1721 .enable_reg = 0x0601c, 1722 .enable_mask = BIT(0), 1723 .hw.init = &(struct clk_init_data){ 1724 .name = "gcc_blsp1_qup5_spi_apps_clk", 1725 .parent_names = (const char *[]){ 1726 "blsp1_qup5_spi_apps_clk_src", 1727 }, 1728 .num_parents = 1, 1729 .flags = CLK_SET_RATE_PARENT, 1730 .ops = &clk_branch2_ops, 1731 }, 1732 }, 1733 }; 1734 1735 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 1736 .halt_reg = 0x07020, 1737 .clkr = { 1738 .enable_reg = 0x07020, 1739 .enable_mask = BIT(0), 1740 .hw.init = &(struct clk_init_data){ 1741 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1742 .parent_names = (const char *[]){ 1743 "blsp1_qup6_i2c_apps_clk_src", 1744 }, 1745 .num_parents = 1, 1746 .flags = CLK_SET_RATE_PARENT, 1747 .ops = &clk_branch2_ops, 1748 }, 1749 }, 1750 }; 1751 1752 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 1753 .halt_reg = 0x0701c, 1754 .clkr = { 1755 .enable_reg = 0x0701c, 1756 .enable_mask = BIT(0), 1757 .hw.init = &(struct clk_init_data){ 1758 .name = "gcc_blsp1_qup6_spi_apps_clk", 1759 .parent_names = (const char *[]){ 1760 "blsp1_qup6_spi_apps_clk_src", 1761 }, 1762 .num_parents = 1, 1763 .flags = CLK_SET_RATE_PARENT, 1764 .ops = &clk_branch2_ops, 1765 }, 1766 }, 1767 }; 1768 1769 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1770 .halt_reg = 0x0203c, 1771 .clkr = { 1772 .enable_reg = 0x0203c, 1773 .enable_mask = BIT(0), 1774 .hw.init = &(struct clk_init_data){ 1775 .name = "gcc_blsp1_uart1_apps_clk", 1776 .parent_names = (const char *[]){ 1777 "blsp1_uart1_apps_clk_src", 1778 }, 1779 .num_parents = 1, 1780 .flags = CLK_SET_RATE_PARENT, 1781 .ops = &clk_branch2_ops, 1782 }, 1783 }, 1784 }; 1785 1786 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1787 .halt_reg = 0x0302c, 1788 .clkr = { 1789 .enable_reg = 0x0302c, 1790 .enable_mask = BIT(0), 1791 .hw.init = &(struct clk_init_data){ 1792 .name = "gcc_blsp1_uart2_apps_clk", 1793 .parent_names = (const char *[]){ 1794 "blsp1_uart2_apps_clk_src", 1795 }, 1796 .num_parents = 1, 1797 .flags = CLK_SET_RATE_PARENT, 1798 .ops = &clk_branch2_ops, 1799 }, 1800 }, 1801 }; 1802 1803 static struct clk_branch gcc_boot_rom_ahb_clk = { 1804 .halt_reg = 0x1300c, 1805 .halt_check = BRANCH_HALT_VOTED, 1806 .clkr = { 1807 .enable_reg = 0x45004, 1808 .enable_mask = BIT(7), 1809 .hw.init = &(struct clk_init_data){ 1810 .name = "gcc_boot_rom_ahb_clk", 1811 .parent_names = (const char *[]){ 1812 "pcnoc_bfdcd_clk_src", 1813 }, 1814 .num_parents = 1, 1815 .ops = &clk_branch2_ops, 1816 }, 1817 }, 1818 }; 1819 1820 static struct clk_branch gcc_camss_cci_ahb_clk = { 1821 .halt_reg = 0x5101c, 1822 .clkr = { 1823 .enable_reg = 0x5101c, 1824 .enable_mask = BIT(0), 1825 .hw.init = &(struct clk_init_data){ 1826 .name = "gcc_camss_cci_ahb_clk", 1827 .parent_names = (const char *[]){ 1828 "camss_ahb_clk_src", 1829 }, 1830 .num_parents = 1, 1831 .flags = CLK_SET_RATE_PARENT, 1832 .ops = &clk_branch2_ops, 1833 }, 1834 }, 1835 }; 1836 1837 static struct clk_branch gcc_camss_cci_clk = { 1838 .halt_reg = 0x51018, 1839 .clkr = { 1840 .enable_reg = 0x51018, 1841 .enable_mask = BIT(0), 1842 .hw.init = &(struct clk_init_data){ 1843 .name = "gcc_camss_cci_clk", 1844 .parent_names = (const char *[]){ 1845 "cci_clk_src", 1846 }, 1847 .num_parents = 1, 1848 .flags = CLK_SET_RATE_PARENT, 1849 .ops = &clk_branch2_ops, 1850 }, 1851 }, 1852 }; 1853 1854 static struct clk_branch gcc_camss_csi0_ahb_clk = { 1855 .halt_reg = 0x4e040, 1856 .clkr = { 1857 .enable_reg = 0x4e040, 1858 .enable_mask = BIT(0), 1859 .hw.init = &(struct clk_init_data){ 1860 .name = "gcc_camss_csi0_ahb_clk", 1861 .parent_names = (const char *[]){ 1862 "camss_ahb_clk_src", 1863 }, 1864 .num_parents = 1, 1865 .flags = CLK_SET_RATE_PARENT, 1866 .ops = &clk_branch2_ops, 1867 }, 1868 }, 1869 }; 1870 1871 static struct clk_branch gcc_camss_csi0_clk = { 1872 .halt_reg = 0x4e03c, 1873 .clkr = { 1874 .enable_reg = 0x4e03c, 1875 .enable_mask = BIT(0), 1876 .hw.init = &(struct clk_init_data){ 1877 .name = "gcc_camss_csi0_clk", 1878 .parent_names = (const char *[]){ 1879 "csi0_clk_src", 1880 }, 1881 .num_parents = 1, 1882 .flags = CLK_SET_RATE_PARENT, 1883 .ops = &clk_branch2_ops, 1884 }, 1885 }, 1886 }; 1887 1888 static struct clk_branch gcc_camss_csi0phy_clk = { 1889 .halt_reg = 0x4e048, 1890 .clkr = { 1891 .enable_reg = 0x4e048, 1892 .enable_mask = BIT(0), 1893 .hw.init = &(struct clk_init_data){ 1894 .name = "gcc_camss_csi0phy_clk", 1895 .parent_names = (const char *[]){ 1896 "csi0_clk_src", 1897 }, 1898 .num_parents = 1, 1899 .flags = CLK_SET_RATE_PARENT, 1900 .ops = &clk_branch2_ops, 1901 }, 1902 }, 1903 }; 1904 1905 static struct clk_branch gcc_camss_csi0pix_clk = { 1906 .halt_reg = 0x4e058, 1907 .clkr = { 1908 .enable_reg = 0x4e058, 1909 .enable_mask = BIT(0), 1910 .hw.init = &(struct clk_init_data){ 1911 .name = "gcc_camss_csi0pix_clk", 1912 .parent_names = (const char *[]){ 1913 "csi0_clk_src", 1914 }, 1915 .num_parents = 1, 1916 .flags = CLK_SET_RATE_PARENT, 1917 .ops = &clk_branch2_ops, 1918 }, 1919 }, 1920 }; 1921 1922 static struct clk_branch gcc_camss_csi0rdi_clk = { 1923 .halt_reg = 0x4e050, 1924 .clkr = { 1925 .enable_reg = 0x4e050, 1926 .enable_mask = BIT(0), 1927 .hw.init = &(struct clk_init_data){ 1928 .name = "gcc_camss_csi0rdi_clk", 1929 .parent_names = (const char *[]){ 1930 "csi0_clk_src", 1931 }, 1932 .num_parents = 1, 1933 .flags = CLK_SET_RATE_PARENT, 1934 .ops = &clk_branch2_ops, 1935 }, 1936 }, 1937 }; 1938 1939 static struct clk_branch gcc_camss_csi1_ahb_clk = { 1940 .halt_reg = 0x4f040, 1941 .clkr = { 1942 .enable_reg = 0x4f040, 1943 .enable_mask = BIT(0), 1944 .hw.init = &(struct clk_init_data){ 1945 .name = "gcc_camss_csi1_ahb_clk", 1946 .parent_names = (const char *[]){ 1947 "camss_ahb_clk_src", 1948 }, 1949 .num_parents = 1, 1950 .flags = CLK_SET_RATE_PARENT, 1951 .ops = &clk_branch2_ops, 1952 }, 1953 }, 1954 }; 1955 1956 static struct clk_branch gcc_camss_csi1_clk = { 1957 .halt_reg = 0x4f03c, 1958 .clkr = { 1959 .enable_reg = 0x4f03c, 1960 .enable_mask = BIT(0), 1961 .hw.init = &(struct clk_init_data){ 1962 .name = "gcc_camss_csi1_clk", 1963 .parent_names = (const char *[]){ 1964 "csi1_clk_src", 1965 }, 1966 .num_parents = 1, 1967 .flags = CLK_SET_RATE_PARENT, 1968 .ops = &clk_branch2_ops, 1969 }, 1970 }, 1971 }; 1972 1973 static struct clk_branch gcc_camss_csi1phy_clk = { 1974 .halt_reg = 0x4f048, 1975 .clkr = { 1976 .enable_reg = 0x4f048, 1977 .enable_mask = BIT(0), 1978 .hw.init = &(struct clk_init_data){ 1979 .name = "gcc_camss_csi1phy_clk", 1980 .parent_names = (const char *[]){ 1981 "csi1_clk_src", 1982 }, 1983 .num_parents = 1, 1984 .flags = CLK_SET_RATE_PARENT, 1985 .ops = &clk_branch2_ops, 1986 }, 1987 }, 1988 }; 1989 1990 static struct clk_branch gcc_camss_csi1pix_clk = { 1991 .halt_reg = 0x4f058, 1992 .clkr = { 1993 .enable_reg = 0x4f058, 1994 .enable_mask = BIT(0), 1995 .hw.init = &(struct clk_init_data){ 1996 .name = "gcc_camss_csi1pix_clk", 1997 .parent_names = (const char *[]){ 1998 "csi1_clk_src", 1999 }, 2000 .num_parents = 1, 2001 .flags = CLK_SET_RATE_PARENT, 2002 .ops = &clk_branch2_ops, 2003 }, 2004 }, 2005 }; 2006 2007 static struct clk_branch gcc_camss_csi1rdi_clk = { 2008 .halt_reg = 0x4f050, 2009 .clkr = { 2010 .enable_reg = 0x4f050, 2011 .enable_mask = BIT(0), 2012 .hw.init = &(struct clk_init_data){ 2013 .name = "gcc_camss_csi1rdi_clk", 2014 .parent_names = (const char *[]){ 2015 "csi1_clk_src", 2016 }, 2017 .num_parents = 1, 2018 .flags = CLK_SET_RATE_PARENT, 2019 .ops = &clk_branch2_ops, 2020 }, 2021 }, 2022 }; 2023 2024 static struct clk_branch gcc_camss_csi_vfe0_clk = { 2025 .halt_reg = 0x58050, 2026 .clkr = { 2027 .enable_reg = 0x58050, 2028 .enable_mask = BIT(0), 2029 .hw.init = &(struct clk_init_data){ 2030 .name = "gcc_camss_csi_vfe0_clk", 2031 .parent_names = (const char *[]){ 2032 "vfe0_clk_src", 2033 }, 2034 .num_parents = 1, 2035 .flags = CLK_SET_RATE_PARENT, 2036 .ops = &clk_branch2_ops, 2037 }, 2038 }, 2039 }; 2040 2041 static struct clk_branch gcc_camss_gp0_clk = { 2042 .halt_reg = 0x54018, 2043 .clkr = { 2044 .enable_reg = 0x54018, 2045 .enable_mask = BIT(0), 2046 .hw.init = &(struct clk_init_data){ 2047 .name = "gcc_camss_gp0_clk", 2048 .parent_names = (const char *[]){ 2049 "camss_gp0_clk_src", 2050 }, 2051 .num_parents = 1, 2052 .flags = CLK_SET_RATE_PARENT, 2053 .ops = &clk_branch2_ops, 2054 }, 2055 }, 2056 }; 2057 2058 static struct clk_branch gcc_camss_gp1_clk = { 2059 .halt_reg = 0x55018, 2060 .clkr = { 2061 .enable_reg = 0x55018, 2062 .enable_mask = BIT(0), 2063 .hw.init = &(struct clk_init_data){ 2064 .name = "gcc_camss_gp1_clk", 2065 .parent_names = (const char *[]){ 2066 "camss_gp1_clk_src", 2067 }, 2068 .num_parents = 1, 2069 .flags = CLK_SET_RATE_PARENT, 2070 .ops = &clk_branch2_ops, 2071 }, 2072 }, 2073 }; 2074 2075 static struct clk_branch gcc_camss_ispif_ahb_clk = { 2076 .halt_reg = 0x50004, 2077 .clkr = { 2078 .enable_reg = 0x50004, 2079 .enable_mask = BIT(0), 2080 .hw.init = &(struct clk_init_data){ 2081 .name = "gcc_camss_ispif_ahb_clk", 2082 .parent_names = (const char *[]){ 2083 "camss_ahb_clk_src", 2084 }, 2085 .num_parents = 1, 2086 .flags = CLK_SET_RATE_PARENT, 2087 .ops = &clk_branch2_ops, 2088 }, 2089 }, 2090 }; 2091 2092 static struct clk_branch gcc_camss_jpeg0_clk = { 2093 .halt_reg = 0x57020, 2094 .clkr = { 2095 .enable_reg = 0x57020, 2096 .enable_mask = BIT(0), 2097 .hw.init = &(struct clk_init_data){ 2098 .name = "gcc_camss_jpeg0_clk", 2099 .parent_names = (const char *[]){ 2100 "jpeg0_clk_src", 2101 }, 2102 .num_parents = 1, 2103 .flags = CLK_SET_RATE_PARENT, 2104 .ops = &clk_branch2_ops, 2105 }, 2106 }, 2107 }; 2108 2109 static struct clk_branch gcc_camss_jpeg_ahb_clk = { 2110 .halt_reg = 0x57024, 2111 .clkr = { 2112 .enable_reg = 0x57024, 2113 .enable_mask = BIT(0), 2114 .hw.init = &(struct clk_init_data){ 2115 .name = "gcc_camss_jpeg_ahb_clk", 2116 .parent_names = (const char *[]){ 2117 "camss_ahb_clk_src", 2118 }, 2119 .num_parents = 1, 2120 .flags = CLK_SET_RATE_PARENT, 2121 .ops = &clk_branch2_ops, 2122 }, 2123 }, 2124 }; 2125 2126 static struct clk_branch gcc_camss_jpeg_axi_clk = { 2127 .halt_reg = 0x57028, 2128 .clkr = { 2129 .enable_reg = 0x57028, 2130 .enable_mask = BIT(0), 2131 .hw.init = &(struct clk_init_data){ 2132 .name = "gcc_camss_jpeg_axi_clk", 2133 .parent_names = (const char *[]){ 2134 "system_noc_bfdcd_clk_src", 2135 }, 2136 .num_parents = 1, 2137 .flags = CLK_SET_RATE_PARENT, 2138 .ops = &clk_branch2_ops, 2139 }, 2140 }, 2141 }; 2142 2143 static struct clk_branch gcc_camss_mclk0_clk = { 2144 .halt_reg = 0x52018, 2145 .clkr = { 2146 .enable_reg = 0x52018, 2147 .enable_mask = BIT(0), 2148 .hw.init = &(struct clk_init_data){ 2149 .name = "gcc_camss_mclk0_clk", 2150 .parent_names = (const char *[]){ 2151 "mclk0_clk_src", 2152 }, 2153 .num_parents = 1, 2154 .flags = CLK_SET_RATE_PARENT, 2155 .ops = &clk_branch2_ops, 2156 }, 2157 }, 2158 }; 2159 2160 static struct clk_branch gcc_camss_mclk1_clk = { 2161 .halt_reg = 0x53018, 2162 .clkr = { 2163 .enable_reg = 0x53018, 2164 .enable_mask = BIT(0), 2165 .hw.init = &(struct clk_init_data){ 2166 .name = "gcc_camss_mclk1_clk", 2167 .parent_names = (const char *[]){ 2168 "mclk1_clk_src", 2169 }, 2170 .num_parents = 1, 2171 .flags = CLK_SET_RATE_PARENT, 2172 .ops = &clk_branch2_ops, 2173 }, 2174 }, 2175 }; 2176 2177 static struct clk_branch gcc_camss_micro_ahb_clk = { 2178 .halt_reg = 0x5600c, 2179 .clkr = { 2180 .enable_reg = 0x5600c, 2181 .enable_mask = BIT(0), 2182 .hw.init = &(struct clk_init_data){ 2183 .name = "gcc_camss_micro_ahb_clk", 2184 .parent_names = (const char *[]){ 2185 "camss_ahb_clk_src", 2186 }, 2187 .num_parents = 1, 2188 .flags = CLK_SET_RATE_PARENT, 2189 .ops = &clk_branch2_ops, 2190 }, 2191 }, 2192 }; 2193 2194 static struct clk_branch gcc_camss_csi0phytimer_clk = { 2195 .halt_reg = 0x4e01c, 2196 .clkr = { 2197 .enable_reg = 0x4e01c, 2198 .enable_mask = BIT(0), 2199 .hw.init = &(struct clk_init_data){ 2200 .name = "gcc_camss_csi0phytimer_clk", 2201 .parent_names = (const char *[]){ 2202 "csi0phytimer_clk_src", 2203 }, 2204 .num_parents = 1, 2205 .flags = CLK_SET_RATE_PARENT, 2206 .ops = &clk_branch2_ops, 2207 }, 2208 }, 2209 }; 2210 2211 static struct clk_branch gcc_camss_csi1phytimer_clk = { 2212 .halt_reg = 0x4f01c, 2213 .clkr = { 2214 .enable_reg = 0x4f01c, 2215 .enable_mask = BIT(0), 2216 .hw.init = &(struct clk_init_data){ 2217 .name = "gcc_camss_csi1phytimer_clk", 2218 .parent_names = (const char *[]){ 2219 "csi1phytimer_clk_src", 2220 }, 2221 .num_parents = 1, 2222 .flags = CLK_SET_RATE_PARENT, 2223 .ops = &clk_branch2_ops, 2224 }, 2225 }, 2226 }; 2227 2228 static struct clk_branch gcc_camss_ahb_clk = { 2229 .halt_reg = 0x5a014, 2230 .clkr = { 2231 .enable_reg = 0x5a014, 2232 .enable_mask = BIT(0), 2233 .hw.init = &(struct clk_init_data){ 2234 .name = "gcc_camss_ahb_clk", 2235 .parent_names = (const char *[]){ 2236 "camss_ahb_clk_src", 2237 }, 2238 .num_parents = 1, 2239 .flags = CLK_SET_RATE_PARENT, 2240 .ops = &clk_branch2_ops, 2241 }, 2242 }, 2243 }; 2244 2245 static struct clk_branch gcc_camss_top_ahb_clk = { 2246 .halt_reg = 0x56004, 2247 .clkr = { 2248 .enable_reg = 0x56004, 2249 .enable_mask = BIT(0), 2250 .hw.init = &(struct clk_init_data){ 2251 .name = "gcc_camss_top_ahb_clk", 2252 .parent_names = (const char *[]){ 2253 "pcnoc_bfdcd_clk_src", 2254 }, 2255 .num_parents = 1, 2256 .flags = CLK_SET_RATE_PARENT, 2257 .ops = &clk_branch2_ops, 2258 }, 2259 }, 2260 }; 2261 2262 static struct clk_branch gcc_camss_cpp_ahb_clk = { 2263 .halt_reg = 0x58040, 2264 .clkr = { 2265 .enable_reg = 0x58040, 2266 .enable_mask = BIT(0), 2267 .hw.init = &(struct clk_init_data){ 2268 .name = "gcc_camss_cpp_ahb_clk", 2269 .parent_names = (const char *[]){ 2270 "camss_ahb_clk_src", 2271 }, 2272 .num_parents = 1, 2273 .flags = CLK_SET_RATE_PARENT, 2274 .ops = &clk_branch2_ops, 2275 }, 2276 }, 2277 }; 2278 2279 static struct clk_branch gcc_camss_cpp_clk = { 2280 .halt_reg = 0x5803c, 2281 .clkr = { 2282 .enable_reg = 0x5803c, 2283 .enable_mask = BIT(0), 2284 .hw.init = &(struct clk_init_data){ 2285 .name = "gcc_camss_cpp_clk", 2286 .parent_names = (const char *[]){ 2287 "cpp_clk_src", 2288 }, 2289 .num_parents = 1, 2290 .flags = CLK_SET_RATE_PARENT, 2291 .ops = &clk_branch2_ops, 2292 }, 2293 }, 2294 }; 2295 2296 static struct clk_branch gcc_camss_vfe0_clk = { 2297 .halt_reg = 0x58038, 2298 .clkr = { 2299 .enable_reg = 0x58038, 2300 .enable_mask = BIT(0), 2301 .hw.init = &(struct clk_init_data){ 2302 .name = "gcc_camss_vfe0_clk", 2303 .parent_names = (const char *[]){ 2304 "vfe0_clk_src", 2305 }, 2306 .num_parents = 1, 2307 .flags = CLK_SET_RATE_PARENT, 2308 .ops = &clk_branch2_ops, 2309 }, 2310 }, 2311 }; 2312 2313 static struct clk_branch gcc_camss_vfe_ahb_clk = { 2314 .halt_reg = 0x58044, 2315 .clkr = { 2316 .enable_reg = 0x58044, 2317 .enable_mask = BIT(0), 2318 .hw.init = &(struct clk_init_data){ 2319 .name = "gcc_camss_vfe_ahb_clk", 2320 .parent_names = (const char *[]){ 2321 "camss_ahb_clk_src", 2322 }, 2323 .num_parents = 1, 2324 .flags = CLK_SET_RATE_PARENT, 2325 .ops = &clk_branch2_ops, 2326 }, 2327 }, 2328 }; 2329 2330 static struct clk_branch gcc_camss_vfe_axi_clk = { 2331 .halt_reg = 0x58048, 2332 .clkr = { 2333 .enable_reg = 0x58048, 2334 .enable_mask = BIT(0), 2335 .hw.init = &(struct clk_init_data){ 2336 .name = "gcc_camss_vfe_axi_clk", 2337 .parent_names = (const char *[]){ 2338 "system_noc_bfdcd_clk_src", 2339 }, 2340 .num_parents = 1, 2341 .flags = CLK_SET_RATE_PARENT, 2342 .ops = &clk_branch2_ops, 2343 }, 2344 }, 2345 }; 2346 2347 static struct clk_branch gcc_crypto_ahb_clk = { 2348 .halt_reg = 0x16024, 2349 .halt_check = BRANCH_HALT_VOTED, 2350 .clkr = { 2351 .enable_reg = 0x45004, 2352 .enable_mask = BIT(0), 2353 .hw.init = &(struct clk_init_data){ 2354 .name = "gcc_crypto_ahb_clk", 2355 .parent_names = (const char *[]){ 2356 "pcnoc_bfdcd_clk_src", 2357 }, 2358 .num_parents = 1, 2359 .flags = CLK_SET_RATE_PARENT, 2360 .ops = &clk_branch2_ops, 2361 }, 2362 }, 2363 }; 2364 2365 static struct clk_branch gcc_crypto_axi_clk = { 2366 .halt_reg = 0x16020, 2367 .halt_check = BRANCH_HALT_VOTED, 2368 .clkr = { 2369 .enable_reg = 0x45004, 2370 .enable_mask = BIT(1), 2371 .hw.init = &(struct clk_init_data){ 2372 .name = "gcc_crypto_axi_clk", 2373 .parent_names = (const char *[]){ 2374 "pcnoc_bfdcd_clk_src", 2375 }, 2376 .num_parents = 1, 2377 .flags = CLK_SET_RATE_PARENT, 2378 .ops = &clk_branch2_ops, 2379 }, 2380 }, 2381 }; 2382 2383 static struct clk_branch gcc_crypto_clk = { 2384 .halt_reg = 0x1601c, 2385 .halt_check = BRANCH_HALT_VOTED, 2386 .clkr = { 2387 .enable_reg = 0x45004, 2388 .enable_mask = BIT(2), 2389 .hw.init = &(struct clk_init_data){ 2390 .name = "gcc_crypto_clk", 2391 .parent_names = (const char *[]){ 2392 "crypto_clk_src", 2393 }, 2394 .num_parents = 1, 2395 .flags = CLK_SET_RATE_PARENT, 2396 .ops = &clk_branch2_ops, 2397 }, 2398 }, 2399 }; 2400 2401 static struct clk_branch gcc_oxili_gmem_clk = { 2402 .halt_reg = 0x59024, 2403 .clkr = { 2404 .enable_reg = 0x59024, 2405 .enable_mask = BIT(0), 2406 .hw.init = &(struct clk_init_data){ 2407 .name = "gcc_oxili_gmem_clk", 2408 .parent_names = (const char *[]){ 2409 "gfx3d_clk_src", 2410 }, 2411 .num_parents = 1, 2412 .flags = CLK_SET_RATE_PARENT, 2413 .ops = &clk_branch2_ops, 2414 }, 2415 }, 2416 }; 2417 2418 static struct clk_branch gcc_gp1_clk = { 2419 .halt_reg = 0x08000, 2420 .clkr = { 2421 .enable_reg = 0x08000, 2422 .enable_mask = BIT(0), 2423 .hw.init = &(struct clk_init_data){ 2424 .name = "gcc_gp1_clk", 2425 .parent_names = (const char *[]){ 2426 "gp1_clk_src", 2427 }, 2428 .num_parents = 1, 2429 .flags = CLK_SET_RATE_PARENT, 2430 .ops = &clk_branch2_ops, 2431 }, 2432 }, 2433 }; 2434 2435 static struct clk_branch gcc_gp2_clk = { 2436 .halt_reg = 0x09000, 2437 .clkr = { 2438 .enable_reg = 0x09000, 2439 .enable_mask = BIT(0), 2440 .hw.init = &(struct clk_init_data){ 2441 .name = "gcc_gp2_clk", 2442 .parent_names = (const char *[]){ 2443 "gp2_clk_src", 2444 }, 2445 .num_parents = 1, 2446 .flags = CLK_SET_RATE_PARENT, 2447 .ops = &clk_branch2_ops, 2448 }, 2449 }, 2450 }; 2451 2452 static struct clk_branch gcc_gp3_clk = { 2453 .halt_reg = 0x0a000, 2454 .clkr = { 2455 .enable_reg = 0x0a000, 2456 .enable_mask = BIT(0), 2457 .hw.init = &(struct clk_init_data){ 2458 .name = "gcc_gp3_clk", 2459 .parent_names = (const char *[]){ 2460 "gp3_clk_src", 2461 }, 2462 .num_parents = 1, 2463 .flags = CLK_SET_RATE_PARENT, 2464 .ops = &clk_branch2_ops, 2465 }, 2466 }, 2467 }; 2468 2469 static struct clk_branch gcc_mdss_ahb_clk = { 2470 .halt_reg = 0x4d07c, 2471 .clkr = { 2472 .enable_reg = 0x4d07c, 2473 .enable_mask = BIT(0), 2474 .hw.init = &(struct clk_init_data){ 2475 .name = "gcc_mdss_ahb_clk", 2476 .parent_names = (const char *[]){ 2477 "pcnoc_bfdcd_clk_src", 2478 }, 2479 .num_parents = 1, 2480 .flags = CLK_SET_RATE_PARENT, 2481 .ops = &clk_branch2_ops, 2482 }, 2483 }, 2484 }; 2485 2486 static struct clk_branch gcc_mdss_axi_clk = { 2487 .halt_reg = 0x4d080, 2488 .clkr = { 2489 .enable_reg = 0x4d080, 2490 .enable_mask = BIT(0), 2491 .hw.init = &(struct clk_init_data){ 2492 .name = "gcc_mdss_axi_clk", 2493 .parent_names = (const char *[]){ 2494 "system_noc_bfdcd_clk_src", 2495 }, 2496 .num_parents = 1, 2497 .flags = CLK_SET_RATE_PARENT, 2498 .ops = &clk_branch2_ops, 2499 }, 2500 }, 2501 }; 2502 2503 static struct clk_branch gcc_mdss_byte0_clk = { 2504 .halt_reg = 0x4d094, 2505 .clkr = { 2506 .enable_reg = 0x4d094, 2507 .enable_mask = BIT(0), 2508 .hw.init = &(struct clk_init_data){ 2509 .name = "gcc_mdss_byte0_clk", 2510 .parent_names = (const char *[]){ 2511 "byte0_clk_src", 2512 }, 2513 .num_parents = 1, 2514 .flags = CLK_SET_RATE_PARENT, 2515 .ops = &clk_branch2_ops, 2516 }, 2517 }, 2518 }; 2519 2520 static struct clk_branch gcc_mdss_esc0_clk = { 2521 .halt_reg = 0x4d098, 2522 .clkr = { 2523 .enable_reg = 0x4d098, 2524 .enable_mask = BIT(0), 2525 .hw.init = &(struct clk_init_data){ 2526 .name = "gcc_mdss_esc0_clk", 2527 .parent_names = (const char *[]){ 2528 "esc0_clk_src", 2529 }, 2530 .num_parents = 1, 2531 .flags = CLK_SET_RATE_PARENT, 2532 .ops = &clk_branch2_ops, 2533 }, 2534 }, 2535 }; 2536 2537 static struct clk_branch gcc_mdss_mdp_clk = { 2538 .halt_reg = 0x4D088, 2539 .clkr = { 2540 .enable_reg = 0x4D088, 2541 .enable_mask = BIT(0), 2542 .hw.init = &(struct clk_init_data){ 2543 .name = "gcc_mdss_mdp_clk", 2544 .parent_names = (const char *[]){ 2545 "mdp_clk_src", 2546 }, 2547 .num_parents = 1, 2548 .flags = CLK_SET_RATE_PARENT, 2549 .ops = &clk_branch2_ops, 2550 }, 2551 }, 2552 }; 2553 2554 static struct clk_branch gcc_mdss_pclk0_clk = { 2555 .halt_reg = 0x4d084, 2556 .clkr = { 2557 .enable_reg = 0x4d084, 2558 .enable_mask = BIT(0), 2559 .hw.init = &(struct clk_init_data){ 2560 .name = "gcc_mdss_pclk0_clk", 2561 .parent_names = (const char *[]){ 2562 "pclk0_clk_src", 2563 }, 2564 .num_parents = 1, 2565 .flags = CLK_SET_RATE_PARENT, 2566 .ops = &clk_branch2_ops, 2567 }, 2568 }, 2569 }; 2570 2571 static struct clk_branch gcc_mdss_vsync_clk = { 2572 .halt_reg = 0x4d090, 2573 .clkr = { 2574 .enable_reg = 0x4d090, 2575 .enable_mask = BIT(0), 2576 .hw.init = &(struct clk_init_data){ 2577 .name = "gcc_mdss_vsync_clk", 2578 .parent_names = (const char *[]){ 2579 "vsync_clk_src", 2580 }, 2581 .num_parents = 1, 2582 .flags = CLK_SET_RATE_PARENT, 2583 .ops = &clk_branch2_ops, 2584 }, 2585 }, 2586 }; 2587 2588 static struct clk_branch gcc_mss_cfg_ahb_clk = { 2589 .halt_reg = 0x49000, 2590 .clkr = { 2591 .enable_reg = 0x49000, 2592 .enable_mask = BIT(0), 2593 .hw.init = &(struct clk_init_data){ 2594 .name = "gcc_mss_cfg_ahb_clk", 2595 .parent_names = (const char *[]){ 2596 "pcnoc_bfdcd_clk_src", 2597 }, 2598 .num_parents = 1, 2599 .flags = CLK_SET_RATE_PARENT, 2600 .ops = &clk_branch2_ops, 2601 }, 2602 }, 2603 }; 2604 2605 static struct clk_branch gcc_mss_q6_bimc_axi_clk = { 2606 .halt_reg = 0x49004, 2607 .clkr = { 2608 .enable_reg = 0x49004, 2609 .enable_mask = BIT(0), 2610 .hw.init = &(struct clk_init_data){ 2611 .name = "gcc_mss_q6_bimc_axi_clk", 2612 .parent_names = (const char *[]){ 2613 "bimc_ddr_clk_src", 2614 }, 2615 .num_parents = 1, 2616 .flags = CLK_SET_RATE_PARENT, 2617 .ops = &clk_branch2_ops, 2618 }, 2619 }, 2620 }; 2621 2622 static struct clk_branch gcc_oxili_ahb_clk = { 2623 .halt_reg = 0x59028, 2624 .clkr = { 2625 .enable_reg = 0x59028, 2626 .enable_mask = BIT(0), 2627 .hw.init = &(struct clk_init_data){ 2628 .name = "gcc_oxili_ahb_clk", 2629 .parent_names = (const char *[]){ 2630 "pcnoc_bfdcd_clk_src", 2631 }, 2632 .num_parents = 1, 2633 .flags = CLK_SET_RATE_PARENT, 2634 .ops = &clk_branch2_ops, 2635 }, 2636 }, 2637 }; 2638 2639 static struct clk_branch gcc_oxili_gfx3d_clk = { 2640 .halt_reg = 0x59020, 2641 .clkr = { 2642 .enable_reg = 0x59020, 2643 .enable_mask = BIT(0), 2644 .hw.init = &(struct clk_init_data){ 2645 .name = "gcc_oxili_gfx3d_clk", 2646 .parent_names = (const char *[]){ 2647 "gfx3d_clk_src", 2648 }, 2649 .num_parents = 1, 2650 .flags = CLK_SET_RATE_PARENT, 2651 .ops = &clk_branch2_ops, 2652 }, 2653 }, 2654 }; 2655 2656 static struct clk_branch gcc_pdm2_clk = { 2657 .halt_reg = 0x4400c, 2658 .clkr = { 2659 .enable_reg = 0x4400c, 2660 .enable_mask = BIT(0), 2661 .hw.init = &(struct clk_init_data){ 2662 .name = "gcc_pdm2_clk", 2663 .parent_names = (const char *[]){ 2664 "pdm2_clk_src", 2665 }, 2666 .num_parents = 1, 2667 .flags = CLK_SET_RATE_PARENT, 2668 .ops = &clk_branch2_ops, 2669 }, 2670 }, 2671 }; 2672 2673 static struct clk_branch gcc_pdm_ahb_clk = { 2674 .halt_reg = 0x44004, 2675 .clkr = { 2676 .enable_reg = 0x44004, 2677 .enable_mask = BIT(0), 2678 .hw.init = &(struct clk_init_data){ 2679 .name = "gcc_pdm_ahb_clk", 2680 .parent_names = (const char *[]){ 2681 "pcnoc_bfdcd_clk_src", 2682 }, 2683 .num_parents = 1, 2684 .flags = CLK_SET_RATE_PARENT, 2685 .ops = &clk_branch2_ops, 2686 }, 2687 }, 2688 }; 2689 2690 static struct clk_branch gcc_prng_ahb_clk = { 2691 .halt_reg = 0x13004, 2692 .halt_check = BRANCH_HALT_VOTED, 2693 .clkr = { 2694 .enable_reg = 0x45004, 2695 .enable_mask = BIT(8), 2696 .hw.init = &(struct clk_init_data){ 2697 .name = "gcc_prng_ahb_clk", 2698 .parent_names = (const char *[]){ 2699 "pcnoc_bfdcd_clk_src", 2700 }, 2701 .num_parents = 1, 2702 .ops = &clk_branch2_ops, 2703 }, 2704 }, 2705 }; 2706 2707 static struct clk_branch gcc_sdcc1_ahb_clk = { 2708 .halt_reg = 0x4201c, 2709 .clkr = { 2710 .enable_reg = 0x4201c, 2711 .enable_mask = BIT(0), 2712 .hw.init = &(struct clk_init_data){ 2713 .name = "gcc_sdcc1_ahb_clk", 2714 .parent_names = (const char *[]){ 2715 "pcnoc_bfdcd_clk_src", 2716 }, 2717 .num_parents = 1, 2718 .flags = CLK_SET_RATE_PARENT, 2719 .ops = &clk_branch2_ops, 2720 }, 2721 }, 2722 }; 2723 2724 static struct clk_branch gcc_sdcc1_apps_clk = { 2725 .halt_reg = 0x42018, 2726 .clkr = { 2727 .enable_reg = 0x42018, 2728 .enable_mask = BIT(0), 2729 .hw.init = &(struct clk_init_data){ 2730 .name = "gcc_sdcc1_apps_clk", 2731 .parent_names = (const char *[]){ 2732 "sdcc1_apps_clk_src", 2733 }, 2734 .num_parents = 1, 2735 .flags = CLK_SET_RATE_PARENT, 2736 .ops = &clk_branch2_ops, 2737 }, 2738 }, 2739 }; 2740 2741 static struct clk_branch gcc_sdcc2_ahb_clk = { 2742 .halt_reg = 0x4301c, 2743 .clkr = { 2744 .enable_reg = 0x4301c, 2745 .enable_mask = BIT(0), 2746 .hw.init = &(struct clk_init_data){ 2747 .name = "gcc_sdcc2_ahb_clk", 2748 .parent_names = (const char *[]){ 2749 "pcnoc_bfdcd_clk_src", 2750 }, 2751 .num_parents = 1, 2752 .flags = CLK_SET_RATE_PARENT, 2753 .ops = &clk_branch2_ops, 2754 }, 2755 }, 2756 }; 2757 2758 static struct clk_branch gcc_sdcc2_apps_clk = { 2759 .halt_reg = 0x43018, 2760 .clkr = { 2761 .enable_reg = 0x43018, 2762 .enable_mask = BIT(0), 2763 .hw.init = &(struct clk_init_data){ 2764 .name = "gcc_sdcc2_apps_clk", 2765 .parent_names = (const char *[]){ 2766 "sdcc2_apps_clk_src", 2767 }, 2768 .num_parents = 1, 2769 .flags = CLK_SET_RATE_PARENT, 2770 .ops = &clk_branch2_ops, 2771 }, 2772 }, 2773 }; 2774 2775 static struct clk_rcg2 bimc_ddr_clk_src = { 2776 .cmd_rcgr = 0x32004, 2777 .hid_width = 5, 2778 .parent_map = gcc_xo_gpll0_bimc_map, 2779 .clkr.hw.init = &(struct clk_init_data){ 2780 .name = "bimc_ddr_clk_src", 2781 .parent_names = gcc_xo_gpll0_bimc, 2782 .num_parents = 3, 2783 .ops = &clk_rcg2_ops, 2784 .flags = CLK_GET_RATE_NOCACHE, 2785 }, 2786 }; 2787 2788 static struct clk_branch gcc_apss_tcu_clk = { 2789 .halt_reg = 0x12018, 2790 .clkr = { 2791 .enable_reg = 0x4500c, 2792 .enable_mask = BIT(1), 2793 .hw.init = &(struct clk_init_data){ 2794 .name = "gcc_apss_tcu_clk", 2795 .parent_names = (const char *[]){ 2796 "bimc_ddr_clk_src", 2797 }, 2798 .num_parents = 1, 2799 .ops = &clk_branch2_ops, 2800 }, 2801 }, 2802 }; 2803 2804 static struct clk_branch gcc_gfx_tcu_clk = { 2805 .halt_reg = 0x12020, 2806 .clkr = { 2807 .enable_reg = 0x4500c, 2808 .enable_mask = BIT(2), 2809 .hw.init = &(struct clk_init_data){ 2810 .name = "gcc_gfx_tcu_clk", 2811 .parent_names = (const char *[]){ 2812 "bimc_ddr_clk_src", 2813 }, 2814 .num_parents = 1, 2815 .ops = &clk_branch2_ops, 2816 }, 2817 }, 2818 }; 2819 2820 static struct clk_branch gcc_gtcu_ahb_clk = { 2821 .halt_reg = 0x12044, 2822 .clkr = { 2823 .enable_reg = 0x4500c, 2824 .enable_mask = BIT(13), 2825 .hw.init = &(struct clk_init_data){ 2826 .name = "gcc_gtcu_ahb_clk", 2827 .parent_names = (const char *[]){ 2828 "pcnoc_bfdcd_clk_src", 2829 }, 2830 .num_parents = 1, 2831 .flags = CLK_SET_RATE_PARENT, 2832 .ops = &clk_branch2_ops, 2833 }, 2834 }, 2835 }; 2836 2837 static struct clk_branch gcc_bimc_gfx_clk = { 2838 .halt_reg = 0x31024, 2839 .clkr = { 2840 .enable_reg = 0x31024, 2841 .enable_mask = BIT(0), 2842 .hw.init = &(struct clk_init_data){ 2843 .name = "gcc_bimc_gfx_clk", 2844 .parent_names = (const char *[]){ 2845 "bimc_gpu_clk_src", 2846 }, 2847 .num_parents = 1, 2848 .flags = CLK_SET_RATE_PARENT, 2849 .ops = &clk_branch2_ops, 2850 }, 2851 }, 2852 }; 2853 2854 static struct clk_branch gcc_bimc_gpu_clk = { 2855 .halt_reg = 0x31040, 2856 .clkr = { 2857 .enable_reg = 0x31040, 2858 .enable_mask = BIT(0), 2859 .hw.init = &(struct clk_init_data){ 2860 .name = "gcc_bimc_gpu_clk", 2861 .parent_names = (const char *[]){ 2862 "bimc_gpu_clk_src", 2863 }, 2864 .num_parents = 1, 2865 .flags = CLK_SET_RATE_PARENT, 2866 .ops = &clk_branch2_ops, 2867 }, 2868 }, 2869 }; 2870 2871 static struct clk_branch gcc_jpeg_tbu_clk = { 2872 .halt_reg = 0x12034, 2873 .clkr = { 2874 .enable_reg = 0x4500c, 2875 .enable_mask = BIT(10), 2876 .hw.init = &(struct clk_init_data){ 2877 .name = "gcc_jpeg_tbu_clk", 2878 .parent_names = (const char *[]){ 2879 "system_noc_bfdcd_clk_src", 2880 }, 2881 .num_parents = 1, 2882 .flags = CLK_SET_RATE_PARENT, 2883 .ops = &clk_branch2_ops, 2884 }, 2885 }, 2886 }; 2887 2888 static struct clk_branch gcc_mdp_tbu_clk = { 2889 .halt_reg = 0x1201c, 2890 .clkr = { 2891 .enable_reg = 0x4500c, 2892 .enable_mask = BIT(4), 2893 .hw.init = &(struct clk_init_data){ 2894 .name = "gcc_mdp_tbu_clk", 2895 .parent_names = (const char *[]){ 2896 "system_noc_bfdcd_clk_src", 2897 }, 2898 .num_parents = 1, 2899 .flags = CLK_SET_RATE_PARENT, 2900 .ops = &clk_branch2_ops, 2901 }, 2902 }, 2903 }; 2904 2905 static struct clk_branch gcc_smmu_cfg_clk = { 2906 .halt_reg = 0x12038, 2907 .clkr = { 2908 .enable_reg = 0x4500c, 2909 .enable_mask = BIT(12), 2910 .hw.init = &(struct clk_init_data){ 2911 .name = "gcc_smmu_cfg_clk", 2912 .parent_names = (const char *[]){ 2913 "pcnoc_bfdcd_clk_src", 2914 }, 2915 .num_parents = 1, 2916 .flags = CLK_SET_RATE_PARENT, 2917 .ops = &clk_branch2_ops, 2918 }, 2919 }, 2920 }; 2921 2922 static struct clk_branch gcc_venus_tbu_clk = { 2923 .halt_reg = 0x12014, 2924 .clkr = { 2925 .enable_reg = 0x4500c, 2926 .enable_mask = BIT(5), 2927 .hw.init = &(struct clk_init_data){ 2928 .name = "gcc_venus_tbu_clk", 2929 .parent_names = (const char *[]){ 2930 "system_noc_bfdcd_clk_src", 2931 }, 2932 .num_parents = 1, 2933 .flags = CLK_SET_RATE_PARENT, 2934 .ops = &clk_branch2_ops, 2935 }, 2936 }, 2937 }; 2938 2939 static struct clk_branch gcc_vfe_tbu_clk = { 2940 .halt_reg = 0x1203c, 2941 .clkr = { 2942 .enable_reg = 0x4500c, 2943 .enable_mask = BIT(9), 2944 .hw.init = &(struct clk_init_data){ 2945 .name = "gcc_vfe_tbu_clk", 2946 .parent_names = (const char *[]){ 2947 "system_noc_bfdcd_clk_src", 2948 }, 2949 .num_parents = 1, 2950 .flags = CLK_SET_RATE_PARENT, 2951 .ops = &clk_branch2_ops, 2952 }, 2953 }, 2954 }; 2955 2956 static struct clk_branch gcc_usb2a_phy_sleep_clk = { 2957 .halt_reg = 0x4102c, 2958 .clkr = { 2959 .enable_reg = 0x4102c, 2960 .enable_mask = BIT(0), 2961 .hw.init = &(struct clk_init_data){ 2962 .name = "gcc_usb2a_phy_sleep_clk", 2963 .parent_names = (const char *[]){ 2964 "sleep_clk_src", 2965 }, 2966 .num_parents = 1, 2967 .flags = CLK_SET_RATE_PARENT, 2968 .ops = &clk_branch2_ops, 2969 }, 2970 }, 2971 }; 2972 2973 static struct clk_branch gcc_usb_hs_ahb_clk = { 2974 .halt_reg = 0x41008, 2975 .clkr = { 2976 .enable_reg = 0x41008, 2977 .enable_mask = BIT(0), 2978 .hw.init = &(struct clk_init_data){ 2979 .name = "gcc_usb_hs_ahb_clk", 2980 .parent_names = (const char *[]){ 2981 "pcnoc_bfdcd_clk_src", 2982 }, 2983 .num_parents = 1, 2984 .flags = CLK_SET_RATE_PARENT, 2985 .ops = &clk_branch2_ops, 2986 }, 2987 }, 2988 }; 2989 2990 static struct clk_branch gcc_usb_hs_system_clk = { 2991 .halt_reg = 0x41004, 2992 .clkr = { 2993 .enable_reg = 0x41004, 2994 .enable_mask = BIT(0), 2995 .hw.init = &(struct clk_init_data){ 2996 .name = "gcc_usb_hs_system_clk", 2997 .parent_names = (const char *[]){ 2998 "usb_hs_system_clk_src", 2999 }, 3000 .num_parents = 1, 3001 .flags = CLK_SET_RATE_PARENT, 3002 .ops = &clk_branch2_ops, 3003 }, 3004 }, 3005 }; 3006 3007 static struct clk_branch gcc_venus0_ahb_clk = { 3008 .halt_reg = 0x4c020, 3009 .clkr = { 3010 .enable_reg = 0x4c020, 3011 .enable_mask = BIT(0), 3012 .hw.init = &(struct clk_init_data){ 3013 .name = "gcc_venus0_ahb_clk", 3014 .parent_names = (const char *[]){ 3015 "pcnoc_bfdcd_clk_src", 3016 }, 3017 .num_parents = 1, 3018 .flags = CLK_SET_RATE_PARENT, 3019 .ops = &clk_branch2_ops, 3020 }, 3021 }, 3022 }; 3023 3024 static struct clk_branch gcc_venus0_axi_clk = { 3025 .halt_reg = 0x4c024, 3026 .clkr = { 3027 .enable_reg = 0x4c024, 3028 .enable_mask = BIT(0), 3029 .hw.init = &(struct clk_init_data){ 3030 .name = "gcc_venus0_axi_clk", 3031 .parent_names = (const char *[]){ 3032 "system_noc_bfdcd_clk_src", 3033 }, 3034 .num_parents = 1, 3035 .flags = CLK_SET_RATE_PARENT, 3036 .ops = &clk_branch2_ops, 3037 }, 3038 }, 3039 }; 3040 3041 static struct clk_branch gcc_venus0_vcodec0_clk = { 3042 .halt_reg = 0x4c01c, 3043 .clkr = { 3044 .enable_reg = 0x4c01c, 3045 .enable_mask = BIT(0), 3046 .hw.init = &(struct clk_init_data){ 3047 .name = "gcc_venus0_vcodec0_clk", 3048 .parent_names = (const char *[]){ 3049 "vcodec0_clk_src", 3050 }, 3051 .num_parents = 1, 3052 .flags = CLK_SET_RATE_PARENT, 3053 .ops = &clk_branch2_ops, 3054 }, 3055 }, 3056 }; 3057 3058 static struct gdsc venus_gdsc = { 3059 .gdscr = 0x4c018, 3060 .pd = { 3061 .name = "venus", 3062 }, 3063 .pwrsts = PWRSTS_OFF_ON, 3064 }; 3065 3066 static struct gdsc mdss_gdsc = { 3067 .gdscr = 0x4d078, 3068 .pd = { 3069 .name = "mdss", 3070 }, 3071 .pwrsts = PWRSTS_OFF_ON, 3072 }; 3073 3074 static struct gdsc jpeg_gdsc = { 3075 .gdscr = 0x5701c, 3076 .pd = { 3077 .name = "jpeg", 3078 }, 3079 .pwrsts = PWRSTS_OFF_ON, 3080 }; 3081 3082 static struct gdsc vfe_gdsc = { 3083 .gdscr = 0x58034, 3084 .pd = { 3085 .name = "vfe", 3086 }, 3087 .pwrsts = PWRSTS_OFF_ON, 3088 }; 3089 3090 static struct gdsc oxili_gdsc = { 3091 .gdscr = 0x5901c, 3092 .pd = { 3093 .name = "oxili", 3094 }, 3095 .pwrsts = PWRSTS_OFF_ON, 3096 }; 3097 3098 static struct clk_regmap *gcc_msm8916_clocks[] = { 3099 [GPLL0] = &gpll0.clkr, 3100 [GPLL0_VOTE] = &gpll0_vote, 3101 [BIMC_PLL] = &bimc_pll.clkr, 3102 [BIMC_PLL_VOTE] = &bimc_pll_vote, 3103 [GPLL1] = &gpll1.clkr, 3104 [GPLL1_VOTE] = &gpll1_vote, 3105 [GPLL2] = &gpll2.clkr, 3106 [GPLL2_VOTE] = &gpll2_vote, 3107 [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr, 3108 [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr, 3109 [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr, 3110 [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr, 3111 [CSI0_CLK_SRC] = &csi0_clk_src.clkr, 3112 [CSI1_CLK_SRC] = &csi1_clk_src.clkr, 3113 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, 3114 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, 3115 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 3116 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 3117 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 3118 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 3119 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 3120 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 3121 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 3122 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 3123 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 3124 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 3125 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 3126 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 3127 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 3128 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 3129 [CCI_CLK_SRC] = &cci_clk_src.clkr, 3130 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, 3131 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, 3132 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, 3133 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, 3134 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, 3135 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, 3136 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, 3137 [CPP_CLK_SRC] = &cpp_clk_src.clkr, 3138 [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr, 3139 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 3140 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 3141 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 3142 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, 3143 [ESC0_CLK_SRC] = &esc0_clk_src.clkr, 3144 [MDP_CLK_SRC] = &mdp_clk_src.clkr, 3145 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, 3146 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, 3147 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 3148 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 3149 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 3150 [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr, 3151 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, 3152 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr, 3153 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 3154 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr, 3155 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 3156 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 3157 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 3158 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 3159 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 3160 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 3161 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 3162 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 3163 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 3164 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 3165 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 3166 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 3167 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 3168 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 3169 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3170 [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr, 3171 [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr, 3172 [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr, 3173 [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr, 3174 [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr, 3175 [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr, 3176 [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr, 3177 [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr, 3178 [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr, 3179 [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr, 3180 [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr, 3181 [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr, 3182 [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr, 3183 [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr, 3184 [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr, 3185 [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr, 3186 [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr, 3187 [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr, 3188 [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr, 3189 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, 3190 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, 3191 [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr, 3192 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, 3193 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, 3194 [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr, 3195 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, 3196 [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr, 3197 [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr, 3198 [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr, 3199 [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr, 3200 [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr, 3201 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, 3202 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, 3203 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, 3204 [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr, 3205 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3206 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3207 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3208 [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr, 3209 [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr, 3210 [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr, 3211 [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr, 3212 [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr, 3213 [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr, 3214 [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr, 3215 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 3216 [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr, 3217 [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr, 3218 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3219 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3220 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3221 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 3222 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 3223 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3224 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3225 [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr, 3226 [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr, 3227 [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr, 3228 [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr, 3229 [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr, 3230 [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr, 3231 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, 3232 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, 3233 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, 3234 [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr, 3235 [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr, 3236 [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr, 3237 [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr, 3238 [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr, 3239 [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr, 3240 [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr, 3241 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, 3242 [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr, 3243 [ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr, 3244 [ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr, 3245 [ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr, 3246 [ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr, 3247 [ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr, 3248 [CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr, 3249 [GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr, 3250 [GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr, 3251 [GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr, 3252 [GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr, 3253 [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_clk.clkr, 3254 [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr, 3255 [GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr, 3256 [GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr, 3257 [GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr, 3258 [GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr, 3259 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, 3260 }; 3261 3262 static struct gdsc *gcc_msm8916_gdscs[] = { 3263 [VENUS_GDSC] = &venus_gdsc, 3264 [MDSS_GDSC] = &mdss_gdsc, 3265 [JPEG_GDSC] = &jpeg_gdsc, 3266 [VFE_GDSC] = &vfe_gdsc, 3267 [OXILI_GDSC] = &oxili_gdsc, 3268 }; 3269 3270 static const struct qcom_reset_map gcc_msm8916_resets[] = { 3271 [GCC_BLSP1_BCR] = { 0x01000 }, 3272 [GCC_BLSP1_QUP1_BCR] = { 0x02000 }, 3273 [GCC_BLSP1_UART1_BCR] = { 0x02038 }, 3274 [GCC_BLSP1_QUP2_BCR] = { 0x03008 }, 3275 [GCC_BLSP1_UART2_BCR] = { 0x03028 }, 3276 [GCC_BLSP1_QUP3_BCR] = { 0x04018 }, 3277 [GCC_BLSP1_QUP4_BCR] = { 0x05018 }, 3278 [GCC_BLSP1_QUP5_BCR] = { 0x06018 }, 3279 [GCC_BLSP1_QUP6_BCR] = { 0x07018 }, 3280 [GCC_IMEM_BCR] = { 0x0e000 }, 3281 [GCC_SMMU_BCR] = { 0x12000 }, 3282 [GCC_APSS_TCU_BCR] = { 0x12050 }, 3283 [GCC_SMMU_XPU_BCR] = { 0x12054 }, 3284 [GCC_PCNOC_TBU_BCR] = { 0x12058 }, 3285 [GCC_PRNG_BCR] = { 0x13000 }, 3286 [GCC_BOOT_ROM_BCR] = { 0x13008 }, 3287 [GCC_CRYPTO_BCR] = { 0x16000 }, 3288 [GCC_SEC_CTRL_BCR] = { 0x1a000 }, 3289 [GCC_AUDIO_CORE_BCR] = { 0x1c008 }, 3290 [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 }, 3291 [GCC_DEHR_BCR] = { 0x1f000 }, 3292 [GCC_SYSTEM_NOC_BCR] = { 0x26000 }, 3293 [GCC_PCNOC_BCR] = { 0x27018 }, 3294 [GCC_TCSR_BCR] = { 0x28000 }, 3295 [GCC_QDSS_BCR] = { 0x29000 }, 3296 [GCC_DCD_BCR] = { 0x2a000 }, 3297 [GCC_MSG_RAM_BCR] = { 0x2b000 }, 3298 [GCC_MPM_BCR] = { 0x2c000 }, 3299 [GCC_SPMI_BCR] = { 0x2e000 }, 3300 [GCC_SPDM_BCR] = { 0x2f000 }, 3301 [GCC_MM_SPDM_BCR] = { 0x2f024 }, 3302 [GCC_BIMC_BCR] = { 0x31000 }, 3303 [GCC_RBCPR_BCR] = { 0x33000 }, 3304 [GCC_TLMM_BCR] = { 0x34000 }, 3305 [GCC_USB_HS_BCR] = { 0x41000 }, 3306 [GCC_USB2A_PHY_BCR] = { 0x41028 }, 3307 [GCC_SDCC1_BCR] = { 0x42000 }, 3308 [GCC_SDCC2_BCR] = { 0x43000 }, 3309 [GCC_PDM_BCR] = { 0x44000 }, 3310 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 }, 3311 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 }, 3312 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 }, 3313 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 }, 3314 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 }, 3315 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 }, 3316 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 }, 3317 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 }, 3318 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 }, 3319 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 }, 3320 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 }, 3321 [GCC_MMSS_BCR] = { 0x4b000 }, 3322 [GCC_VENUS0_BCR] = { 0x4c014 }, 3323 [GCC_MDSS_BCR] = { 0x4d074 }, 3324 [GCC_CAMSS_PHY0_BCR] = { 0x4e018 }, 3325 [GCC_CAMSS_CSI0_BCR] = { 0x4e038 }, 3326 [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 }, 3327 [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c }, 3328 [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 }, 3329 [GCC_CAMSS_PHY1_BCR] = { 0x4f018 }, 3330 [GCC_CAMSS_CSI1_BCR] = { 0x4f038 }, 3331 [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 }, 3332 [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c }, 3333 [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 }, 3334 [GCC_CAMSS_ISPIF_BCR] = { 0x50000 }, 3335 [GCC_CAMSS_CCI_BCR] = { 0x51014 }, 3336 [GCC_CAMSS_MCLK0_BCR] = { 0x52014 }, 3337 [GCC_CAMSS_MCLK1_BCR] = { 0x53014 }, 3338 [GCC_CAMSS_GP0_BCR] = { 0x54014 }, 3339 [GCC_CAMSS_GP1_BCR] = { 0x55014 }, 3340 [GCC_CAMSS_TOP_BCR] = { 0x56000 }, 3341 [GCC_CAMSS_MICRO_BCR] = { 0x56008 }, 3342 [GCC_CAMSS_JPEG_BCR] = { 0x57018 }, 3343 [GCC_CAMSS_VFE_BCR] = { 0x58030 }, 3344 [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c }, 3345 [GCC_OXILI_BCR] = { 0x59018 }, 3346 [GCC_GMEM_BCR] = { 0x5902c }, 3347 [GCC_CAMSS_AHB_BCR] = { 0x5a018 }, 3348 [GCC_MDP_TBU_BCR] = { 0x62000 }, 3349 [GCC_GFX_TBU_BCR] = { 0x63000 }, 3350 [GCC_GFX_TCU_BCR] = { 0x64000 }, 3351 [GCC_MSS_TBU_AXI_BCR] = { 0x65000 }, 3352 [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 }, 3353 [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 }, 3354 [GCC_GTCU_AHB_BCR] = { 0x68000 }, 3355 [GCC_SMMU_CFG_BCR] = { 0x69000 }, 3356 [GCC_VFE_TBU_BCR] = { 0x6a000 }, 3357 [GCC_VENUS_TBU_BCR] = { 0x6b000 }, 3358 [GCC_JPEG_TBU_BCR] = { 0x6c000 }, 3359 [GCC_PRONTO_TBU_BCR] = { 0x6d000 }, 3360 [GCC_SMMU_CATS_BCR] = { 0x7c000 }, 3361 }; 3362 3363 static const struct regmap_config gcc_msm8916_regmap_config = { 3364 .reg_bits = 32, 3365 .reg_stride = 4, 3366 .val_bits = 32, 3367 .max_register = 0x80000, 3368 .fast_io = true, 3369 }; 3370 3371 static const struct qcom_cc_desc gcc_msm8916_desc = { 3372 .config = &gcc_msm8916_regmap_config, 3373 .clks = gcc_msm8916_clocks, 3374 .num_clks = ARRAY_SIZE(gcc_msm8916_clocks), 3375 .resets = gcc_msm8916_resets, 3376 .num_resets = ARRAY_SIZE(gcc_msm8916_resets), 3377 .gdscs = gcc_msm8916_gdscs, 3378 .num_gdscs = ARRAY_SIZE(gcc_msm8916_gdscs), 3379 }; 3380 3381 static const struct of_device_id gcc_msm8916_match_table[] = { 3382 { .compatible = "qcom,gcc-msm8916" }, 3383 { } 3384 }; 3385 MODULE_DEVICE_TABLE(of, gcc_msm8916_match_table); 3386 3387 static int gcc_msm8916_probe(struct platform_device *pdev) 3388 { 3389 int ret; 3390 struct device *dev = &pdev->dev; 3391 3392 ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000); 3393 if (ret) 3394 return ret; 3395 3396 ret = qcom_cc_register_sleep_clk(dev); 3397 if (ret) 3398 return ret; 3399 3400 return qcom_cc_probe(pdev, &gcc_msm8916_desc); 3401 } 3402 3403 static struct platform_driver gcc_msm8916_driver = { 3404 .probe = gcc_msm8916_probe, 3405 .driver = { 3406 .name = "gcc-msm8916", 3407 .of_match_table = gcc_msm8916_match_table, 3408 }, 3409 }; 3410 3411 static int __init gcc_msm8916_init(void) 3412 { 3413 return platform_driver_register(&gcc_msm8916_driver); 3414 } 3415 core_initcall(gcc_msm8916_init); 3416 3417 static void __exit gcc_msm8916_exit(void) 3418 { 3419 platform_driver_unregister(&gcc_msm8916_driver); 3420 } 3421 module_exit(gcc_msm8916_exit); 3422 3423 MODULE_DESCRIPTION("Qualcomm GCC MSM8916 Driver"); 3424 MODULE_LICENSE("GPL v2"); 3425 MODULE_ALIAS("platform:gcc-msm8916"); 3426