1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright 2015 Linaro Limited 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/bitops.h> 8 #include <linux/err.h> 9 #include <linux/platform_device.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/clk-provider.h> 14 #include <linux/regmap.h> 15 #include <linux/reset-controller.h> 16 17 #include <dt-bindings/clock/qcom,gcc-msm8916.h> 18 #include <dt-bindings/reset/qcom,gcc-msm8916.h> 19 20 #include "common.h" 21 #include "clk-regmap.h" 22 #include "clk-pll.h" 23 #include "clk-rcg.h" 24 #include "clk-branch.h" 25 #include "reset.h" 26 #include "gdsc.h" 27 28 enum { 29 P_XO, 30 P_GPLL0, 31 P_GPLL0_AUX, 32 P_BIMC, 33 P_GPLL1, 34 P_GPLL1_AUX, 35 P_GPLL2, 36 P_GPLL2_AUX, 37 P_SLEEP_CLK, 38 P_DSI0_PHYPLL_BYTE, 39 P_DSI0_PHYPLL_DSI, 40 P_EXT_PRI_I2S, 41 P_EXT_SEC_I2S, 42 P_EXT_MCLK, 43 }; 44 45 static const struct parent_map gcc_xo_gpll0_map[] = { 46 { P_XO, 0 }, 47 { P_GPLL0, 1 }, 48 }; 49 50 static const char * const gcc_xo_gpll0[] = { 51 "xo", 52 "gpll0_vote", 53 }; 54 55 static const struct parent_map gcc_xo_gpll0_bimc_map[] = { 56 { P_XO, 0 }, 57 { P_GPLL0, 1 }, 58 { P_BIMC, 2 }, 59 }; 60 61 static const char * const gcc_xo_gpll0_bimc[] = { 62 "xo", 63 "gpll0_vote", 64 "bimc_pll_vote", 65 }; 66 67 static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = { 68 { P_XO, 0 }, 69 { P_GPLL0_AUX, 3 }, 70 { P_GPLL1, 1 }, 71 { P_GPLL2_AUX, 2 }, 72 }; 73 74 static const char * const gcc_xo_gpll0a_gpll1_gpll2a[] = { 75 "xo", 76 "gpll0_vote", 77 "gpll1_vote", 78 "gpll2_vote", 79 }; 80 81 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = { 82 { P_XO, 0 }, 83 { P_GPLL0, 1 }, 84 { P_GPLL2, 2 }, 85 }; 86 87 static const char * const gcc_xo_gpll0_gpll2[] = { 88 "xo", 89 "gpll0_vote", 90 "gpll2_vote", 91 }; 92 93 static const struct parent_map gcc_xo_gpll0a_map[] = { 94 { P_XO, 0 }, 95 { P_GPLL0_AUX, 2 }, 96 }; 97 98 static const char * const gcc_xo_gpll0a[] = { 99 "xo", 100 "gpll0_vote", 101 }; 102 103 static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = { 104 { P_XO, 0 }, 105 { P_GPLL0, 1 }, 106 { P_GPLL1_AUX, 2 }, 107 { P_SLEEP_CLK, 6 }, 108 }; 109 110 static const char * const gcc_xo_gpll0_gpll1a_sleep[] = { 111 "xo", 112 "gpll0_vote", 113 "gpll1_vote", 114 "sleep_clk", 115 }; 116 117 static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = { 118 { P_XO, 0 }, 119 { P_GPLL0, 1 }, 120 { P_GPLL1_AUX, 2 }, 121 }; 122 123 static const char * const gcc_xo_gpll0_gpll1a[] = { 124 "xo", 125 "gpll0_vote", 126 "gpll1_vote", 127 }; 128 129 static const struct parent_map gcc_xo_dsibyte_map[] = { 130 { P_XO, 0, }, 131 { P_DSI0_PHYPLL_BYTE, 2 }, 132 }; 133 134 static const char * const gcc_xo_dsibyte[] = { 135 "xo", 136 "dsi0pllbyte", 137 }; 138 139 static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = { 140 { P_XO, 0 }, 141 { P_GPLL0_AUX, 2 }, 142 { P_DSI0_PHYPLL_BYTE, 1 }, 143 }; 144 145 static const char * const gcc_xo_gpll0a_dsibyte[] = { 146 "xo", 147 "gpll0_vote", 148 "dsi0pllbyte", 149 }; 150 151 static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = { 152 { P_XO, 0 }, 153 { P_GPLL0, 1 }, 154 { P_DSI0_PHYPLL_DSI, 2 }, 155 }; 156 157 static const char * const gcc_xo_gpll0_dsiphy[] = { 158 "xo", 159 "gpll0_vote", 160 "dsi0pll", 161 }; 162 163 static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = { 164 { P_XO, 0 }, 165 { P_GPLL0_AUX, 2 }, 166 { P_DSI0_PHYPLL_DSI, 1 }, 167 }; 168 169 static const char * const gcc_xo_gpll0a_dsiphy[] = { 170 "xo", 171 "gpll0_vote", 172 "dsi0pll", 173 }; 174 175 static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = { 176 { P_XO, 0 }, 177 { P_GPLL0_AUX, 1 }, 178 { P_GPLL1, 3 }, 179 { P_GPLL2, 2 }, 180 }; 181 182 static const char * const gcc_xo_gpll0a_gpll1_gpll2[] = { 183 "xo", 184 "gpll0_vote", 185 "gpll1_vote", 186 "gpll2_vote", 187 }; 188 189 static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = { 190 { P_XO, 0 }, 191 { P_GPLL0, 1 }, 192 { P_GPLL1, 2 }, 193 { P_SLEEP_CLK, 6 } 194 }; 195 196 static const char * const gcc_xo_gpll0_gpll1_sleep[] = { 197 "xo", 198 "gpll0_vote", 199 "gpll1_vote", 200 "sleep_clk", 201 }; 202 203 static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = { 204 { P_XO, 0 }, 205 { P_GPLL1, 1 }, 206 { P_EXT_PRI_I2S, 2 }, 207 { P_EXT_MCLK, 3 }, 208 { P_SLEEP_CLK, 6 } 209 }; 210 211 static const char * const gcc_xo_gpll1_epi2s_emclk_sleep[] = { 212 "xo", 213 "gpll1_vote", 214 "ext_pri_i2s", 215 "ext_mclk", 216 "sleep_clk", 217 }; 218 219 static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = { 220 { P_XO, 0 }, 221 { P_GPLL1, 1 }, 222 { P_EXT_SEC_I2S, 2 }, 223 { P_EXT_MCLK, 3 }, 224 { P_SLEEP_CLK, 6 } 225 }; 226 227 static const char * const gcc_xo_gpll1_esi2s_emclk_sleep[] = { 228 "xo", 229 "gpll1_vote", 230 "ext_sec_i2s", 231 "ext_mclk", 232 "sleep_clk", 233 }; 234 235 static const struct parent_map gcc_xo_sleep_map[] = { 236 { P_XO, 0 }, 237 { P_SLEEP_CLK, 6 } 238 }; 239 240 static const char * const gcc_xo_sleep[] = { 241 "xo", 242 "sleep_clk", 243 }; 244 245 static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = { 246 { P_XO, 0 }, 247 { P_GPLL1, 1 }, 248 { P_EXT_MCLK, 2 }, 249 { P_SLEEP_CLK, 6 } 250 }; 251 252 static const char * const gcc_xo_gpll1_emclk_sleep[] = { 253 "xo", 254 "gpll1_vote", 255 "ext_mclk", 256 "sleep_clk", 257 }; 258 259 static struct clk_pll gpll0 = { 260 .l_reg = 0x21004, 261 .m_reg = 0x21008, 262 .n_reg = 0x2100c, 263 .config_reg = 0x21010, 264 .mode_reg = 0x21000, 265 .status_reg = 0x2101c, 266 .status_bit = 17, 267 .clkr.hw.init = &(struct clk_init_data){ 268 .name = "gpll0", 269 .parent_names = (const char *[]){ "xo" }, 270 .num_parents = 1, 271 .ops = &clk_pll_ops, 272 }, 273 }; 274 275 static struct clk_regmap gpll0_vote = { 276 .enable_reg = 0x45000, 277 .enable_mask = BIT(0), 278 .hw.init = &(struct clk_init_data){ 279 .name = "gpll0_vote", 280 .parent_names = (const char *[]){ "gpll0" }, 281 .num_parents = 1, 282 .ops = &clk_pll_vote_ops, 283 }, 284 }; 285 286 static struct clk_pll gpll1 = { 287 .l_reg = 0x20004, 288 .m_reg = 0x20008, 289 .n_reg = 0x2000c, 290 .config_reg = 0x20010, 291 .mode_reg = 0x20000, 292 .status_reg = 0x2001c, 293 .status_bit = 17, 294 .clkr.hw.init = &(struct clk_init_data){ 295 .name = "gpll1", 296 .parent_names = (const char *[]){ "xo" }, 297 .num_parents = 1, 298 .ops = &clk_pll_ops, 299 }, 300 }; 301 302 static struct clk_regmap gpll1_vote = { 303 .enable_reg = 0x45000, 304 .enable_mask = BIT(1), 305 .hw.init = &(struct clk_init_data){ 306 .name = "gpll1_vote", 307 .parent_names = (const char *[]){ "gpll1" }, 308 .num_parents = 1, 309 .ops = &clk_pll_vote_ops, 310 }, 311 }; 312 313 static struct clk_pll gpll2 = { 314 .l_reg = 0x4a004, 315 .m_reg = 0x4a008, 316 .n_reg = 0x4a00c, 317 .config_reg = 0x4a010, 318 .mode_reg = 0x4a000, 319 .status_reg = 0x4a01c, 320 .status_bit = 17, 321 .clkr.hw.init = &(struct clk_init_data){ 322 .name = "gpll2", 323 .parent_names = (const char *[]){ "xo" }, 324 .num_parents = 1, 325 .ops = &clk_pll_ops, 326 }, 327 }; 328 329 static struct clk_regmap gpll2_vote = { 330 .enable_reg = 0x45000, 331 .enable_mask = BIT(2), 332 .hw.init = &(struct clk_init_data){ 333 .name = "gpll2_vote", 334 .parent_names = (const char *[]){ "gpll2" }, 335 .num_parents = 1, 336 .ops = &clk_pll_vote_ops, 337 }, 338 }; 339 340 static struct clk_pll bimc_pll = { 341 .l_reg = 0x23004, 342 .m_reg = 0x23008, 343 .n_reg = 0x2300c, 344 .config_reg = 0x23010, 345 .mode_reg = 0x23000, 346 .status_reg = 0x2301c, 347 .status_bit = 17, 348 .clkr.hw.init = &(struct clk_init_data){ 349 .name = "bimc_pll", 350 .parent_names = (const char *[]){ "xo" }, 351 .num_parents = 1, 352 .ops = &clk_pll_ops, 353 }, 354 }; 355 356 static struct clk_regmap bimc_pll_vote = { 357 .enable_reg = 0x45000, 358 .enable_mask = BIT(3), 359 .hw.init = &(struct clk_init_data){ 360 .name = "bimc_pll_vote", 361 .parent_names = (const char *[]){ "bimc_pll" }, 362 .num_parents = 1, 363 .ops = &clk_pll_vote_ops, 364 }, 365 }; 366 367 static struct clk_rcg2 pcnoc_bfdcd_clk_src = { 368 .cmd_rcgr = 0x27000, 369 .hid_width = 5, 370 .parent_map = gcc_xo_gpll0_bimc_map, 371 .clkr.hw.init = &(struct clk_init_data){ 372 .name = "pcnoc_bfdcd_clk_src", 373 .parent_names = gcc_xo_gpll0_bimc, 374 .num_parents = 3, 375 .ops = &clk_rcg2_ops, 376 }, 377 }; 378 379 static struct clk_rcg2 system_noc_bfdcd_clk_src = { 380 .cmd_rcgr = 0x26004, 381 .hid_width = 5, 382 .parent_map = gcc_xo_gpll0_bimc_map, 383 .clkr.hw.init = &(struct clk_init_data){ 384 .name = "system_noc_bfdcd_clk_src", 385 .parent_names = gcc_xo_gpll0_bimc, 386 .num_parents = 3, 387 .ops = &clk_rcg2_ops, 388 }, 389 }; 390 391 static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = { 392 F(40000000, P_GPLL0, 10, 1, 2), 393 F(80000000, P_GPLL0, 10, 0, 0), 394 { } 395 }; 396 397 static struct clk_rcg2 camss_ahb_clk_src = { 398 .cmd_rcgr = 0x5a000, 399 .mnd_width = 8, 400 .hid_width = 5, 401 .parent_map = gcc_xo_gpll0_map, 402 .freq_tbl = ftbl_gcc_camss_ahb_clk, 403 .clkr.hw.init = &(struct clk_init_data){ 404 .name = "camss_ahb_clk_src", 405 .parent_names = gcc_xo_gpll0, 406 .num_parents = 2, 407 .ops = &clk_rcg2_ops, 408 }, 409 }; 410 411 static const struct freq_tbl ftbl_apss_ahb_clk[] = { 412 F(19200000, P_XO, 1, 0, 0), 413 F(50000000, P_GPLL0, 16, 0, 0), 414 F(100000000, P_GPLL0, 8, 0, 0), 415 F(133330000, P_GPLL0, 6, 0, 0), 416 { } 417 }; 418 419 static struct clk_rcg2 apss_ahb_clk_src = { 420 .cmd_rcgr = 0x46000, 421 .hid_width = 5, 422 .parent_map = gcc_xo_gpll0_map, 423 .freq_tbl = ftbl_apss_ahb_clk, 424 .clkr.hw.init = &(struct clk_init_data){ 425 .name = "apss_ahb_clk_src", 426 .parent_names = gcc_xo_gpll0, 427 .num_parents = 2, 428 .ops = &clk_rcg2_ops, 429 }, 430 }; 431 432 static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = { 433 F(100000000, P_GPLL0, 8, 0, 0), 434 F(200000000, P_GPLL0, 4, 0, 0), 435 { } 436 }; 437 438 static struct clk_rcg2 csi0_clk_src = { 439 .cmd_rcgr = 0x4e020, 440 .hid_width = 5, 441 .parent_map = gcc_xo_gpll0_map, 442 .freq_tbl = ftbl_gcc_camss_csi0_1_clk, 443 .clkr.hw.init = &(struct clk_init_data){ 444 .name = "csi0_clk_src", 445 .parent_names = gcc_xo_gpll0, 446 .num_parents = 2, 447 .ops = &clk_rcg2_ops, 448 }, 449 }; 450 451 static struct clk_rcg2 csi1_clk_src = { 452 .cmd_rcgr = 0x4f020, 453 .hid_width = 5, 454 .parent_map = gcc_xo_gpll0_map, 455 .freq_tbl = ftbl_gcc_camss_csi0_1_clk, 456 .clkr.hw.init = &(struct clk_init_data){ 457 .name = "csi1_clk_src", 458 .parent_names = gcc_xo_gpll0, 459 .num_parents = 2, 460 .ops = &clk_rcg2_ops, 461 }, 462 }; 463 464 static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = { 465 F(19200000, P_XO, 1, 0, 0), 466 F(50000000, P_GPLL0_AUX, 16, 0, 0), 467 F(80000000, P_GPLL0_AUX, 10, 0, 0), 468 F(100000000, P_GPLL0_AUX, 8, 0, 0), 469 F(160000000, P_GPLL0_AUX, 5, 0, 0), 470 F(177780000, P_GPLL0_AUX, 4.5, 0, 0), 471 F(200000000, P_GPLL0_AUX, 4, 0, 0), 472 F(266670000, P_GPLL0_AUX, 3, 0, 0), 473 F(294912000, P_GPLL1, 3, 0, 0), 474 F(310000000, P_GPLL2, 3, 0, 0), 475 F(400000000, P_GPLL0_AUX, 2, 0, 0), 476 { } 477 }; 478 479 static struct clk_rcg2 gfx3d_clk_src = { 480 .cmd_rcgr = 0x59000, 481 .hid_width = 5, 482 .parent_map = gcc_xo_gpll0a_gpll1_gpll2a_map, 483 .freq_tbl = ftbl_gcc_oxili_gfx3d_clk, 484 .clkr.hw.init = &(struct clk_init_data){ 485 .name = "gfx3d_clk_src", 486 .parent_names = gcc_xo_gpll0a_gpll1_gpll2a, 487 .num_parents = 4, 488 .ops = &clk_rcg2_ops, 489 }, 490 }; 491 492 static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = { 493 F(50000000, P_GPLL0, 16, 0, 0), 494 F(80000000, P_GPLL0, 10, 0, 0), 495 F(100000000, P_GPLL0, 8, 0, 0), 496 F(160000000, P_GPLL0, 5, 0, 0), 497 F(177780000, P_GPLL0, 4.5, 0, 0), 498 F(200000000, P_GPLL0, 4, 0, 0), 499 F(266670000, P_GPLL0, 3, 0, 0), 500 F(320000000, P_GPLL0, 2.5, 0, 0), 501 F(400000000, P_GPLL0, 2, 0, 0), 502 F(465000000, P_GPLL2, 2, 0, 0), 503 { } 504 }; 505 506 static struct clk_rcg2 vfe0_clk_src = { 507 .cmd_rcgr = 0x58000, 508 .hid_width = 5, 509 .parent_map = gcc_xo_gpll0_gpll2_map, 510 .freq_tbl = ftbl_gcc_camss_vfe0_clk, 511 .clkr.hw.init = &(struct clk_init_data){ 512 .name = "vfe0_clk_src", 513 .parent_names = gcc_xo_gpll0_gpll2, 514 .num_parents = 3, 515 .ops = &clk_rcg2_ops, 516 }, 517 }; 518 519 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = { 520 F(19200000, P_XO, 1, 0, 0), 521 F(50000000, P_GPLL0, 16, 0, 0), 522 { } 523 }; 524 525 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 526 .cmd_rcgr = 0x0200c, 527 .hid_width = 5, 528 .parent_map = gcc_xo_gpll0_map, 529 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 530 .clkr.hw.init = &(struct clk_init_data){ 531 .name = "blsp1_qup1_i2c_apps_clk_src", 532 .parent_names = gcc_xo_gpll0, 533 .num_parents = 2, 534 .ops = &clk_rcg2_ops, 535 }, 536 }; 537 538 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = { 539 F(100000, P_XO, 16, 2, 24), 540 F(250000, P_XO, 16, 5, 24), 541 F(500000, P_XO, 8, 5, 24), 542 F(960000, P_XO, 10, 1, 2), 543 F(1000000, P_XO, 4, 5, 24), 544 F(4800000, P_XO, 4, 0, 0), 545 F(9600000, P_XO, 2, 0, 0), 546 F(16000000, P_GPLL0, 10, 1, 5), 547 F(19200000, P_XO, 1, 0, 0), 548 F(25000000, P_GPLL0, 16, 1, 2), 549 F(50000000, P_GPLL0, 16, 0, 0), 550 { } 551 }; 552 553 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 554 .cmd_rcgr = 0x02024, 555 .mnd_width = 8, 556 .hid_width = 5, 557 .parent_map = gcc_xo_gpll0_map, 558 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 559 .clkr.hw.init = &(struct clk_init_data){ 560 .name = "blsp1_qup1_spi_apps_clk_src", 561 .parent_names = gcc_xo_gpll0, 562 .num_parents = 2, 563 .ops = &clk_rcg2_ops, 564 }, 565 }; 566 567 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 568 .cmd_rcgr = 0x03000, 569 .hid_width = 5, 570 .parent_map = gcc_xo_gpll0_map, 571 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 572 .clkr.hw.init = &(struct clk_init_data){ 573 .name = "blsp1_qup2_i2c_apps_clk_src", 574 .parent_names = gcc_xo_gpll0, 575 .num_parents = 2, 576 .ops = &clk_rcg2_ops, 577 }, 578 }; 579 580 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 581 .cmd_rcgr = 0x03014, 582 .mnd_width = 8, 583 .hid_width = 5, 584 .parent_map = gcc_xo_gpll0_map, 585 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 586 .clkr.hw.init = &(struct clk_init_data){ 587 .name = "blsp1_qup2_spi_apps_clk_src", 588 .parent_names = gcc_xo_gpll0, 589 .num_parents = 2, 590 .ops = &clk_rcg2_ops, 591 }, 592 }; 593 594 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 595 .cmd_rcgr = 0x04000, 596 .hid_width = 5, 597 .parent_map = gcc_xo_gpll0_map, 598 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 599 .clkr.hw.init = &(struct clk_init_data){ 600 .name = "blsp1_qup3_i2c_apps_clk_src", 601 .parent_names = gcc_xo_gpll0, 602 .num_parents = 2, 603 .ops = &clk_rcg2_ops, 604 }, 605 }; 606 607 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 608 .cmd_rcgr = 0x04024, 609 .mnd_width = 8, 610 .hid_width = 5, 611 .parent_map = gcc_xo_gpll0_map, 612 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 613 .clkr.hw.init = &(struct clk_init_data){ 614 .name = "blsp1_qup3_spi_apps_clk_src", 615 .parent_names = gcc_xo_gpll0, 616 .num_parents = 2, 617 .ops = &clk_rcg2_ops, 618 }, 619 }; 620 621 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 622 .cmd_rcgr = 0x05000, 623 .hid_width = 5, 624 .parent_map = gcc_xo_gpll0_map, 625 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 626 .clkr.hw.init = &(struct clk_init_data){ 627 .name = "blsp1_qup4_i2c_apps_clk_src", 628 .parent_names = gcc_xo_gpll0, 629 .num_parents = 2, 630 .ops = &clk_rcg2_ops, 631 }, 632 }; 633 634 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 635 .cmd_rcgr = 0x05024, 636 .mnd_width = 8, 637 .hid_width = 5, 638 .parent_map = gcc_xo_gpll0_map, 639 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 640 .clkr.hw.init = &(struct clk_init_data){ 641 .name = "blsp1_qup4_spi_apps_clk_src", 642 .parent_names = gcc_xo_gpll0, 643 .num_parents = 2, 644 .ops = &clk_rcg2_ops, 645 }, 646 }; 647 648 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 649 .cmd_rcgr = 0x06000, 650 .hid_width = 5, 651 .parent_map = gcc_xo_gpll0_map, 652 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 653 .clkr.hw.init = &(struct clk_init_data){ 654 .name = "blsp1_qup5_i2c_apps_clk_src", 655 .parent_names = gcc_xo_gpll0, 656 .num_parents = 2, 657 .ops = &clk_rcg2_ops, 658 }, 659 }; 660 661 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 662 .cmd_rcgr = 0x06024, 663 .mnd_width = 8, 664 .hid_width = 5, 665 .parent_map = gcc_xo_gpll0_map, 666 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 667 .clkr.hw.init = &(struct clk_init_data){ 668 .name = "blsp1_qup5_spi_apps_clk_src", 669 .parent_names = gcc_xo_gpll0, 670 .num_parents = 2, 671 .ops = &clk_rcg2_ops, 672 }, 673 }; 674 675 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 676 .cmd_rcgr = 0x07000, 677 .hid_width = 5, 678 .parent_map = gcc_xo_gpll0_map, 679 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 680 .clkr.hw.init = &(struct clk_init_data){ 681 .name = "blsp1_qup6_i2c_apps_clk_src", 682 .parent_names = gcc_xo_gpll0, 683 .num_parents = 2, 684 .ops = &clk_rcg2_ops, 685 }, 686 }; 687 688 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 689 .cmd_rcgr = 0x07024, 690 .mnd_width = 8, 691 .hid_width = 5, 692 .parent_map = gcc_xo_gpll0_map, 693 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 694 .clkr.hw.init = &(struct clk_init_data){ 695 .name = "blsp1_qup6_spi_apps_clk_src", 696 .parent_names = gcc_xo_gpll0, 697 .num_parents = 2, 698 .ops = &clk_rcg2_ops, 699 }, 700 }; 701 702 static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = { 703 F(3686400, P_GPLL0, 1, 72, 15625), 704 F(7372800, P_GPLL0, 1, 144, 15625), 705 F(14745600, P_GPLL0, 1, 288, 15625), 706 F(16000000, P_GPLL0, 10, 1, 5), 707 F(19200000, P_XO, 1, 0, 0), 708 F(24000000, P_GPLL0, 1, 3, 100), 709 F(25000000, P_GPLL0, 16, 1, 2), 710 F(32000000, P_GPLL0, 1, 1, 25), 711 F(40000000, P_GPLL0, 1, 1, 20), 712 F(46400000, P_GPLL0, 1, 29, 500), 713 F(48000000, P_GPLL0, 1, 3, 50), 714 F(51200000, P_GPLL0, 1, 8, 125), 715 F(56000000, P_GPLL0, 1, 7, 100), 716 F(58982400, P_GPLL0, 1, 1152, 15625), 717 F(60000000, P_GPLL0, 1, 3, 40), 718 { } 719 }; 720 721 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 722 .cmd_rcgr = 0x02044, 723 .mnd_width = 16, 724 .hid_width = 5, 725 .parent_map = gcc_xo_gpll0_map, 726 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, 727 .clkr.hw.init = &(struct clk_init_data){ 728 .name = "blsp1_uart1_apps_clk_src", 729 .parent_names = gcc_xo_gpll0, 730 .num_parents = 2, 731 .ops = &clk_rcg2_ops, 732 }, 733 }; 734 735 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 736 .cmd_rcgr = 0x03034, 737 .mnd_width = 16, 738 .hid_width = 5, 739 .parent_map = gcc_xo_gpll0_map, 740 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, 741 .clkr.hw.init = &(struct clk_init_data){ 742 .name = "blsp1_uart2_apps_clk_src", 743 .parent_names = gcc_xo_gpll0, 744 .num_parents = 2, 745 .ops = &clk_rcg2_ops, 746 }, 747 }; 748 749 static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = { 750 F(19200000, P_XO, 1, 0, 0), 751 { } 752 }; 753 754 static struct clk_rcg2 cci_clk_src = { 755 .cmd_rcgr = 0x51000, 756 .mnd_width = 8, 757 .hid_width = 5, 758 .parent_map = gcc_xo_gpll0a_map, 759 .freq_tbl = ftbl_gcc_camss_cci_clk, 760 .clkr.hw.init = &(struct clk_init_data){ 761 .name = "cci_clk_src", 762 .parent_names = gcc_xo_gpll0a, 763 .num_parents = 2, 764 .ops = &clk_rcg2_ops, 765 }, 766 }; 767 768 /* 769 * This is a frequency table for "General Purpose" clocks. 770 * These clocks can be muxed to the SoC pins and may be used by 771 * external devices. They're often used as PWM source. 772 * 773 * See comment at ftbl_gcc_gp1_3_clk. 774 */ 775 static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = { 776 F(10000, P_XO, 16, 1, 120), 777 F(100000, P_XO, 16, 1, 12), 778 F(500000, P_GPLL0, 16, 1, 100), 779 F(1000000, P_GPLL0, 16, 1, 50), 780 F(2500000, P_GPLL0, 16, 1, 20), 781 F(5000000, P_GPLL0, 16, 1, 10), 782 F(100000000, P_GPLL0, 8, 0, 0), 783 F(200000000, P_GPLL0, 4, 0, 0), 784 { } 785 }; 786 787 static struct clk_rcg2 camss_gp0_clk_src = { 788 .cmd_rcgr = 0x54000, 789 .mnd_width = 8, 790 .hid_width = 5, 791 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 792 .freq_tbl = ftbl_gcc_camss_gp0_1_clk, 793 .clkr.hw.init = &(struct clk_init_data){ 794 .name = "camss_gp0_clk_src", 795 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 796 .num_parents = 4, 797 .ops = &clk_rcg2_ops, 798 }, 799 }; 800 801 static struct clk_rcg2 camss_gp1_clk_src = { 802 .cmd_rcgr = 0x55000, 803 .mnd_width = 8, 804 .hid_width = 5, 805 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 806 .freq_tbl = ftbl_gcc_camss_gp0_1_clk, 807 .clkr.hw.init = &(struct clk_init_data){ 808 .name = "camss_gp1_clk_src", 809 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 810 .num_parents = 4, 811 .ops = &clk_rcg2_ops, 812 }, 813 }; 814 815 static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = { 816 F(133330000, P_GPLL0, 6, 0, 0), 817 F(266670000, P_GPLL0, 3, 0, 0), 818 F(320000000, P_GPLL0, 2.5, 0, 0), 819 { } 820 }; 821 822 static struct clk_rcg2 jpeg0_clk_src = { 823 .cmd_rcgr = 0x57000, 824 .hid_width = 5, 825 .parent_map = gcc_xo_gpll0_map, 826 .freq_tbl = ftbl_gcc_camss_jpeg0_clk, 827 .clkr.hw.init = &(struct clk_init_data){ 828 .name = "jpeg0_clk_src", 829 .parent_names = gcc_xo_gpll0, 830 .num_parents = 2, 831 .ops = &clk_rcg2_ops, 832 }, 833 }; 834 835 static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = { 836 F(9600000, P_XO, 2, 0, 0), 837 F(23880000, P_GPLL0, 1, 2, 67), 838 F(66670000, P_GPLL0, 12, 0, 0), 839 { } 840 }; 841 842 static struct clk_rcg2 mclk0_clk_src = { 843 .cmd_rcgr = 0x52000, 844 .mnd_width = 8, 845 .hid_width = 5, 846 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 847 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk, 848 .clkr.hw.init = &(struct clk_init_data){ 849 .name = "mclk0_clk_src", 850 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 851 .num_parents = 4, 852 .ops = &clk_rcg2_ops, 853 }, 854 }; 855 856 static struct clk_rcg2 mclk1_clk_src = { 857 .cmd_rcgr = 0x53000, 858 .mnd_width = 8, 859 .hid_width = 5, 860 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 861 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk, 862 .clkr.hw.init = &(struct clk_init_data){ 863 .name = "mclk1_clk_src", 864 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 865 .num_parents = 4, 866 .ops = &clk_rcg2_ops, 867 }, 868 }; 869 870 static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = { 871 F(100000000, P_GPLL0, 8, 0, 0), 872 F(200000000, P_GPLL0, 4, 0, 0), 873 { } 874 }; 875 876 static struct clk_rcg2 csi0phytimer_clk_src = { 877 .cmd_rcgr = 0x4e000, 878 .hid_width = 5, 879 .parent_map = gcc_xo_gpll0_gpll1a_map, 880 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk, 881 .clkr.hw.init = &(struct clk_init_data){ 882 .name = "csi0phytimer_clk_src", 883 .parent_names = gcc_xo_gpll0_gpll1a, 884 .num_parents = 3, 885 .ops = &clk_rcg2_ops, 886 }, 887 }; 888 889 static struct clk_rcg2 csi1phytimer_clk_src = { 890 .cmd_rcgr = 0x4f000, 891 .hid_width = 5, 892 .parent_map = gcc_xo_gpll0_gpll1a_map, 893 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk, 894 .clkr.hw.init = &(struct clk_init_data){ 895 .name = "csi1phytimer_clk_src", 896 .parent_names = gcc_xo_gpll0_gpll1a, 897 .num_parents = 3, 898 .ops = &clk_rcg2_ops, 899 }, 900 }; 901 902 static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = { 903 F(160000000, P_GPLL0, 5, 0, 0), 904 F(320000000, P_GPLL0, 2.5, 0, 0), 905 F(465000000, P_GPLL2, 2, 0, 0), 906 { } 907 }; 908 909 static struct clk_rcg2 cpp_clk_src = { 910 .cmd_rcgr = 0x58018, 911 .hid_width = 5, 912 .parent_map = gcc_xo_gpll0_gpll2_map, 913 .freq_tbl = ftbl_gcc_camss_cpp_clk, 914 .clkr.hw.init = &(struct clk_init_data){ 915 .name = "cpp_clk_src", 916 .parent_names = gcc_xo_gpll0_gpll2, 917 .num_parents = 3, 918 .ops = &clk_rcg2_ops, 919 }, 920 }; 921 922 static const struct freq_tbl ftbl_gcc_crypto_clk[] = { 923 F(50000000, P_GPLL0, 16, 0, 0), 924 F(80000000, P_GPLL0, 10, 0, 0), 925 F(100000000, P_GPLL0, 8, 0, 0), 926 F(160000000, P_GPLL0, 5, 0, 0), 927 { } 928 }; 929 930 static struct clk_rcg2 crypto_clk_src = { 931 .cmd_rcgr = 0x16004, 932 .hid_width = 5, 933 .parent_map = gcc_xo_gpll0_map, 934 .freq_tbl = ftbl_gcc_crypto_clk, 935 .clkr.hw.init = &(struct clk_init_data){ 936 .name = "crypto_clk_src", 937 .parent_names = gcc_xo_gpll0, 938 .num_parents = 2, 939 .ops = &clk_rcg2_ops, 940 }, 941 }; 942 943 /* 944 * This is a frequency table for "General Purpose" clocks. 945 * These clocks can be muxed to the SoC pins and may be used by 946 * external devices. They're often used as PWM source. 947 * 948 * Please note that MND divider must be enabled for duty-cycle 949 * control to be possible. (M != N) Also since D register is configured 950 * with a value multiplied by 2, and duty cycle is calculated as 951 * (2 * D) % 2^W 952 * DutyCycle = ---------------- 953 * 2 * (N % 2^W) 954 * (where W = .mnd_width) 955 * N must be half or less than maximum value for the register. 956 * Otherwise duty-cycle control would be limited. 957 * (e.g. for 8-bit NMD N should be less than 128) 958 */ 959 static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = { 960 F(10000, P_XO, 16, 1, 120), 961 F(100000, P_XO, 16, 1, 12), 962 F(500000, P_GPLL0, 16, 1, 100), 963 F(1000000, P_GPLL0, 16, 1, 50), 964 F(2500000, P_GPLL0, 16, 1, 20), 965 F(5000000, P_GPLL0, 16, 1, 10), 966 F(19200000, P_XO, 1, 0, 0), 967 { } 968 }; 969 970 static struct clk_rcg2 gp1_clk_src = { 971 .cmd_rcgr = 0x08004, 972 .mnd_width = 8, 973 .hid_width = 5, 974 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 975 .freq_tbl = ftbl_gcc_gp1_3_clk, 976 .clkr.hw.init = &(struct clk_init_data){ 977 .name = "gp1_clk_src", 978 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 979 .num_parents = 3, 980 .ops = &clk_rcg2_ops, 981 }, 982 }; 983 984 static struct clk_rcg2 gp2_clk_src = { 985 .cmd_rcgr = 0x09004, 986 .mnd_width = 8, 987 .hid_width = 5, 988 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 989 .freq_tbl = ftbl_gcc_gp1_3_clk, 990 .clkr.hw.init = &(struct clk_init_data){ 991 .name = "gp2_clk_src", 992 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 993 .num_parents = 3, 994 .ops = &clk_rcg2_ops, 995 }, 996 }; 997 998 static struct clk_rcg2 gp3_clk_src = { 999 .cmd_rcgr = 0x0a004, 1000 .mnd_width = 8, 1001 .hid_width = 5, 1002 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 1003 .freq_tbl = ftbl_gcc_gp1_3_clk, 1004 .clkr.hw.init = &(struct clk_init_data){ 1005 .name = "gp3_clk_src", 1006 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 1007 .num_parents = 3, 1008 .ops = &clk_rcg2_ops, 1009 }, 1010 }; 1011 1012 static struct clk_rcg2 byte0_clk_src = { 1013 .cmd_rcgr = 0x4d044, 1014 .hid_width = 5, 1015 .parent_map = gcc_xo_gpll0a_dsibyte_map, 1016 .clkr.hw.init = &(struct clk_init_data){ 1017 .name = "byte0_clk_src", 1018 .parent_names = gcc_xo_gpll0a_dsibyte, 1019 .num_parents = 3, 1020 .ops = &clk_byte2_ops, 1021 .flags = CLK_SET_RATE_PARENT, 1022 }, 1023 }; 1024 1025 static const struct freq_tbl ftbl_gcc_mdss_esc0_clk[] = { 1026 F(19200000, P_XO, 1, 0, 0), 1027 { } 1028 }; 1029 1030 static struct clk_rcg2 esc0_clk_src = { 1031 .cmd_rcgr = 0x4d05c, 1032 .hid_width = 5, 1033 .parent_map = gcc_xo_dsibyte_map, 1034 .freq_tbl = ftbl_gcc_mdss_esc0_clk, 1035 .clkr.hw.init = &(struct clk_init_data){ 1036 .name = "esc0_clk_src", 1037 .parent_names = gcc_xo_dsibyte, 1038 .num_parents = 2, 1039 .ops = &clk_rcg2_ops, 1040 }, 1041 }; 1042 1043 static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = { 1044 F(50000000, P_GPLL0, 16, 0, 0), 1045 F(80000000, P_GPLL0, 10, 0, 0), 1046 F(100000000, P_GPLL0, 8, 0, 0), 1047 F(160000000, P_GPLL0, 5, 0, 0), 1048 F(177780000, P_GPLL0, 4.5, 0, 0), 1049 F(200000000, P_GPLL0, 4, 0, 0), 1050 F(266670000, P_GPLL0, 3, 0, 0), 1051 F(320000000, P_GPLL0, 2.5, 0, 0), 1052 { } 1053 }; 1054 1055 static struct clk_rcg2 mdp_clk_src = { 1056 .cmd_rcgr = 0x4d014, 1057 .hid_width = 5, 1058 .parent_map = gcc_xo_gpll0_dsiphy_map, 1059 .freq_tbl = ftbl_gcc_mdss_mdp_clk, 1060 .clkr.hw.init = &(struct clk_init_data){ 1061 .name = "mdp_clk_src", 1062 .parent_names = gcc_xo_gpll0_dsiphy, 1063 .num_parents = 3, 1064 .ops = &clk_rcg2_ops, 1065 }, 1066 }; 1067 1068 static struct clk_rcg2 pclk0_clk_src = { 1069 .cmd_rcgr = 0x4d000, 1070 .mnd_width = 8, 1071 .hid_width = 5, 1072 .parent_map = gcc_xo_gpll0a_dsiphy_map, 1073 .clkr.hw.init = &(struct clk_init_data){ 1074 .name = "pclk0_clk_src", 1075 .parent_names = gcc_xo_gpll0a_dsiphy, 1076 .num_parents = 3, 1077 .ops = &clk_pixel_ops, 1078 .flags = CLK_SET_RATE_PARENT, 1079 }, 1080 }; 1081 1082 static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = { 1083 F(19200000, P_XO, 1, 0, 0), 1084 { } 1085 }; 1086 1087 static struct clk_rcg2 vsync_clk_src = { 1088 .cmd_rcgr = 0x4d02c, 1089 .hid_width = 5, 1090 .parent_map = gcc_xo_gpll0a_map, 1091 .freq_tbl = ftbl_gcc_mdss_vsync_clk, 1092 .clkr.hw.init = &(struct clk_init_data){ 1093 .name = "vsync_clk_src", 1094 .parent_names = gcc_xo_gpll0a, 1095 .num_parents = 2, 1096 .ops = &clk_rcg2_ops, 1097 }, 1098 }; 1099 1100 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = { 1101 F(64000000, P_GPLL0, 12.5, 0, 0), 1102 { } 1103 }; 1104 1105 static struct clk_rcg2 pdm2_clk_src = { 1106 .cmd_rcgr = 0x44010, 1107 .hid_width = 5, 1108 .parent_map = gcc_xo_gpll0_map, 1109 .freq_tbl = ftbl_gcc_pdm2_clk, 1110 .clkr.hw.init = &(struct clk_init_data){ 1111 .name = "pdm2_clk_src", 1112 .parent_names = gcc_xo_gpll0, 1113 .num_parents = 2, 1114 .ops = &clk_rcg2_ops, 1115 }, 1116 }; 1117 1118 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = { 1119 F(144000, P_XO, 16, 3, 25), 1120 F(400000, P_XO, 12, 1, 4), 1121 F(20000000, P_GPLL0, 10, 1, 4), 1122 F(25000000, P_GPLL0, 16, 1, 2), 1123 F(50000000, P_GPLL0, 16, 0, 0), 1124 F(100000000, P_GPLL0, 8, 0, 0), 1125 F(177770000, P_GPLL0, 4.5, 0, 0), 1126 { } 1127 }; 1128 1129 static struct clk_rcg2 sdcc1_apps_clk_src = { 1130 .cmd_rcgr = 0x42004, 1131 .mnd_width = 8, 1132 .hid_width = 5, 1133 .parent_map = gcc_xo_gpll0_map, 1134 .freq_tbl = ftbl_gcc_sdcc1_apps_clk, 1135 .clkr.hw.init = &(struct clk_init_data){ 1136 .name = "sdcc1_apps_clk_src", 1137 .parent_names = gcc_xo_gpll0, 1138 .num_parents = 2, 1139 .ops = &clk_rcg2_floor_ops, 1140 }, 1141 }; 1142 1143 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk[] = { 1144 F(144000, P_XO, 16, 3, 25), 1145 F(400000, P_XO, 12, 1, 4), 1146 F(20000000, P_GPLL0, 10, 1, 4), 1147 F(25000000, P_GPLL0, 16, 1, 2), 1148 F(50000000, P_GPLL0, 16, 0, 0), 1149 F(100000000, P_GPLL0, 8, 0, 0), 1150 F(200000000, P_GPLL0, 4, 0, 0), 1151 { } 1152 }; 1153 1154 static struct clk_rcg2 sdcc2_apps_clk_src = { 1155 .cmd_rcgr = 0x43004, 1156 .mnd_width = 8, 1157 .hid_width = 5, 1158 .parent_map = gcc_xo_gpll0_map, 1159 .freq_tbl = ftbl_gcc_sdcc2_apps_clk, 1160 .clkr.hw.init = &(struct clk_init_data){ 1161 .name = "sdcc2_apps_clk_src", 1162 .parent_names = gcc_xo_gpll0, 1163 .num_parents = 2, 1164 .ops = &clk_rcg2_floor_ops, 1165 }, 1166 }; 1167 1168 static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = { 1169 F(155000000, P_GPLL2, 6, 0, 0), 1170 F(310000000, P_GPLL2, 3, 0, 0), 1171 F(400000000, P_GPLL0, 2, 0, 0), 1172 { } 1173 }; 1174 1175 static struct clk_rcg2 apss_tcu_clk_src = { 1176 .cmd_rcgr = 0x1207c, 1177 .hid_width = 5, 1178 .parent_map = gcc_xo_gpll0a_gpll1_gpll2_map, 1179 .freq_tbl = ftbl_gcc_apss_tcu_clk, 1180 .clkr.hw.init = &(struct clk_init_data){ 1181 .name = "apss_tcu_clk_src", 1182 .parent_names = gcc_xo_gpll0a_gpll1_gpll2, 1183 .num_parents = 4, 1184 .ops = &clk_rcg2_ops, 1185 }, 1186 }; 1187 1188 static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = { 1189 F(19200000, P_XO, 1, 0, 0), 1190 F(100000000, P_GPLL0, 8, 0, 0), 1191 F(200000000, P_GPLL0, 4, 0, 0), 1192 F(266500000, P_BIMC, 4, 0, 0), 1193 F(400000000, P_GPLL0, 2, 0, 0), 1194 F(533000000, P_BIMC, 2, 0, 0), 1195 { } 1196 }; 1197 1198 static struct clk_rcg2 bimc_gpu_clk_src = { 1199 .cmd_rcgr = 0x31028, 1200 .hid_width = 5, 1201 .parent_map = gcc_xo_gpll0_bimc_map, 1202 .freq_tbl = ftbl_gcc_bimc_gpu_clk, 1203 .clkr.hw.init = &(struct clk_init_data){ 1204 .name = "bimc_gpu_clk_src", 1205 .parent_names = gcc_xo_gpll0_bimc, 1206 .num_parents = 3, 1207 .flags = CLK_GET_RATE_NOCACHE, 1208 .ops = &clk_rcg2_ops, 1209 }, 1210 }; 1211 1212 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { 1213 F(80000000, P_GPLL0, 10, 0, 0), 1214 { } 1215 }; 1216 1217 static struct clk_rcg2 usb_hs_system_clk_src = { 1218 .cmd_rcgr = 0x41010, 1219 .hid_width = 5, 1220 .parent_map = gcc_xo_gpll0_map, 1221 .freq_tbl = ftbl_gcc_usb_hs_system_clk, 1222 .clkr.hw.init = &(struct clk_init_data){ 1223 .name = "usb_hs_system_clk_src", 1224 .parent_names = gcc_xo_gpll0, 1225 .num_parents = 2, 1226 .ops = &clk_rcg2_ops, 1227 }, 1228 }; 1229 1230 static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = { 1231 F(3200000, P_XO, 6, 0, 0), 1232 F(6400000, P_XO, 3, 0, 0), 1233 F(9600000, P_XO, 2, 0, 0), 1234 F(19200000, P_XO, 1, 0, 0), 1235 F(40000000, P_GPLL0, 10, 1, 2), 1236 F(66670000, P_GPLL0, 12, 0, 0), 1237 F(80000000, P_GPLL0, 10, 0, 0), 1238 F(100000000, P_GPLL0, 8, 0, 0), 1239 { } 1240 }; 1241 1242 static struct clk_rcg2 ultaudio_ahbfabric_clk_src = { 1243 .cmd_rcgr = 0x1c010, 1244 .hid_width = 5, 1245 .mnd_width = 8, 1246 .parent_map = gcc_xo_gpll0_gpll1_sleep_map, 1247 .freq_tbl = ftbl_gcc_ultaudio_ahb_clk, 1248 .clkr.hw.init = &(struct clk_init_data){ 1249 .name = "ultaudio_ahbfabric_clk_src", 1250 .parent_names = gcc_xo_gpll0_gpll1_sleep, 1251 .num_parents = 4, 1252 .ops = &clk_rcg2_ops, 1253 }, 1254 }; 1255 1256 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = { 1257 .halt_reg = 0x1c028, 1258 .clkr = { 1259 .enable_reg = 0x1c028, 1260 .enable_mask = BIT(0), 1261 .hw.init = &(struct clk_init_data){ 1262 .name = "gcc_ultaudio_ahbfabric_ixfabric_clk", 1263 .parent_names = (const char *[]){ 1264 "ultaudio_ahbfabric_clk_src", 1265 }, 1266 .num_parents = 1, 1267 .flags = CLK_SET_RATE_PARENT, 1268 .ops = &clk_branch2_ops, 1269 }, 1270 }, 1271 }; 1272 1273 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = { 1274 .halt_reg = 0x1c024, 1275 .clkr = { 1276 .enable_reg = 0x1c024, 1277 .enable_mask = BIT(0), 1278 .hw.init = &(struct clk_init_data){ 1279 .name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk", 1280 .parent_names = (const char *[]){ 1281 "ultaudio_ahbfabric_clk_src", 1282 }, 1283 .num_parents = 1, 1284 .flags = CLK_SET_RATE_PARENT, 1285 .ops = &clk_branch2_ops, 1286 }, 1287 }, 1288 }; 1289 1290 static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = { 1291 F(128000, P_XO, 10, 1, 15), 1292 F(256000, P_XO, 5, 1, 15), 1293 F(384000, P_XO, 5, 1, 10), 1294 F(512000, P_XO, 5, 2, 15), 1295 F(576000, P_XO, 5, 3, 20), 1296 F(705600, P_GPLL1, 16, 1, 80), 1297 F(768000, P_XO, 5, 1, 5), 1298 F(800000, P_XO, 5, 5, 24), 1299 F(1024000, P_XO, 5, 4, 15), 1300 F(1152000, P_XO, 1, 3, 50), 1301 F(1411200, P_GPLL1, 16, 1, 40), 1302 F(1536000, P_XO, 1, 2, 25), 1303 F(1600000, P_XO, 12, 0, 0), 1304 F(1728000, P_XO, 5, 9, 20), 1305 F(2048000, P_XO, 5, 8, 15), 1306 F(2304000, P_XO, 5, 3, 5), 1307 F(2400000, P_XO, 8, 0, 0), 1308 F(2822400, P_GPLL1, 16, 1, 20), 1309 F(3072000, P_XO, 5, 4, 5), 1310 F(4096000, P_GPLL1, 9, 2, 49), 1311 F(4800000, P_XO, 4, 0, 0), 1312 F(5644800, P_GPLL1, 16, 1, 10), 1313 F(6144000, P_GPLL1, 7, 1, 21), 1314 F(8192000, P_GPLL1, 9, 4, 49), 1315 F(9600000, P_XO, 2, 0, 0), 1316 F(11289600, P_GPLL1, 16, 1, 5), 1317 F(12288000, P_GPLL1, 7, 2, 21), 1318 { } 1319 }; 1320 1321 static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = { 1322 .cmd_rcgr = 0x1c054, 1323 .hid_width = 5, 1324 .mnd_width = 8, 1325 .parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map, 1326 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, 1327 .clkr.hw.init = &(struct clk_init_data){ 1328 .name = "ultaudio_lpaif_pri_i2s_clk_src", 1329 .parent_names = gcc_xo_gpll1_epi2s_emclk_sleep, 1330 .num_parents = 5, 1331 .ops = &clk_rcg2_ops, 1332 }, 1333 }; 1334 1335 static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = { 1336 .halt_reg = 0x1c068, 1337 .clkr = { 1338 .enable_reg = 0x1c068, 1339 .enable_mask = BIT(0), 1340 .hw.init = &(struct clk_init_data){ 1341 .name = "gcc_ultaudio_lpaif_pri_i2s_clk", 1342 .parent_names = (const char *[]){ 1343 "ultaudio_lpaif_pri_i2s_clk_src", 1344 }, 1345 .num_parents = 1, 1346 .flags = CLK_SET_RATE_PARENT, 1347 .ops = &clk_branch2_ops, 1348 }, 1349 }, 1350 }; 1351 1352 static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = { 1353 .cmd_rcgr = 0x1c06c, 1354 .hid_width = 5, 1355 .mnd_width = 8, 1356 .parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map, 1357 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, 1358 .clkr.hw.init = &(struct clk_init_data){ 1359 .name = "ultaudio_lpaif_sec_i2s_clk_src", 1360 .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep, 1361 .num_parents = 5, 1362 .ops = &clk_rcg2_ops, 1363 }, 1364 }; 1365 1366 static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = { 1367 .halt_reg = 0x1c080, 1368 .clkr = { 1369 .enable_reg = 0x1c080, 1370 .enable_mask = BIT(0), 1371 .hw.init = &(struct clk_init_data){ 1372 .name = "gcc_ultaudio_lpaif_sec_i2s_clk", 1373 .parent_names = (const char *[]){ 1374 "ultaudio_lpaif_sec_i2s_clk_src", 1375 }, 1376 .num_parents = 1, 1377 .flags = CLK_SET_RATE_PARENT, 1378 .ops = &clk_branch2_ops, 1379 }, 1380 }, 1381 }; 1382 1383 static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = { 1384 .cmd_rcgr = 0x1c084, 1385 .hid_width = 5, 1386 .mnd_width = 8, 1387 .parent_map = gcc_xo_gpll1_emclk_sleep_map, 1388 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, 1389 .clkr.hw.init = &(struct clk_init_data){ 1390 .name = "ultaudio_lpaif_aux_i2s_clk_src", 1391 .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep, 1392 .num_parents = 5, 1393 .ops = &clk_rcg2_ops, 1394 }, 1395 }; 1396 1397 static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = { 1398 .halt_reg = 0x1c098, 1399 .clkr = { 1400 .enable_reg = 0x1c098, 1401 .enable_mask = BIT(0), 1402 .hw.init = &(struct clk_init_data){ 1403 .name = "gcc_ultaudio_lpaif_aux_i2s_clk", 1404 .parent_names = (const char *[]){ 1405 "ultaudio_lpaif_aux_i2s_clk_src", 1406 }, 1407 .num_parents = 1, 1408 .flags = CLK_SET_RATE_PARENT, 1409 .ops = &clk_branch2_ops, 1410 }, 1411 }, 1412 }; 1413 1414 static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = { 1415 F(19200000, P_XO, 1, 0, 0), 1416 { } 1417 }; 1418 1419 static struct clk_rcg2 ultaudio_xo_clk_src = { 1420 .cmd_rcgr = 0x1c034, 1421 .hid_width = 5, 1422 .parent_map = gcc_xo_sleep_map, 1423 .freq_tbl = ftbl_gcc_ultaudio_xo_clk, 1424 .clkr.hw.init = &(struct clk_init_data){ 1425 .name = "ultaudio_xo_clk_src", 1426 .parent_names = gcc_xo_sleep, 1427 .num_parents = 2, 1428 .ops = &clk_rcg2_ops, 1429 }, 1430 }; 1431 1432 static struct clk_branch gcc_ultaudio_avsync_xo_clk = { 1433 .halt_reg = 0x1c04c, 1434 .clkr = { 1435 .enable_reg = 0x1c04c, 1436 .enable_mask = BIT(0), 1437 .hw.init = &(struct clk_init_data){ 1438 .name = "gcc_ultaudio_avsync_xo_clk", 1439 .parent_names = (const char *[]){ 1440 "ultaudio_xo_clk_src", 1441 }, 1442 .num_parents = 1, 1443 .flags = CLK_SET_RATE_PARENT, 1444 .ops = &clk_branch2_ops, 1445 }, 1446 }, 1447 }; 1448 1449 static struct clk_branch gcc_ultaudio_stc_xo_clk = { 1450 .halt_reg = 0x1c050, 1451 .clkr = { 1452 .enable_reg = 0x1c050, 1453 .enable_mask = BIT(0), 1454 .hw.init = &(struct clk_init_data){ 1455 .name = "gcc_ultaudio_stc_xo_clk", 1456 .parent_names = (const char *[]){ 1457 "ultaudio_xo_clk_src", 1458 }, 1459 .num_parents = 1, 1460 .flags = CLK_SET_RATE_PARENT, 1461 .ops = &clk_branch2_ops, 1462 }, 1463 }, 1464 }; 1465 1466 static const struct freq_tbl ftbl_codec_clk[] = { 1467 F(9600000, P_XO, 2, 0, 0), 1468 F(12288000, P_XO, 1, 16, 25), 1469 F(19200000, P_XO, 1, 0, 0), 1470 F(11289600, P_EXT_MCLK, 1, 0, 0), 1471 { } 1472 }; 1473 1474 static struct clk_rcg2 codec_digcodec_clk_src = { 1475 .cmd_rcgr = 0x1c09c, 1476 .mnd_width = 8, 1477 .hid_width = 5, 1478 .parent_map = gcc_xo_gpll1_emclk_sleep_map, 1479 .freq_tbl = ftbl_codec_clk, 1480 .clkr.hw.init = &(struct clk_init_data){ 1481 .name = "codec_digcodec_clk_src", 1482 .parent_names = gcc_xo_gpll1_emclk_sleep, 1483 .num_parents = 4, 1484 .ops = &clk_rcg2_ops, 1485 }, 1486 }; 1487 1488 static struct clk_branch gcc_codec_digcodec_clk = { 1489 .halt_reg = 0x1c0b0, 1490 .clkr = { 1491 .enable_reg = 0x1c0b0, 1492 .enable_mask = BIT(0), 1493 .hw.init = &(struct clk_init_data){ 1494 .name = "gcc_ultaudio_codec_digcodec_clk", 1495 .parent_names = (const char *[]){ 1496 "codec_digcodec_clk_src", 1497 }, 1498 .num_parents = 1, 1499 .flags = CLK_SET_RATE_PARENT, 1500 .ops = &clk_branch2_ops, 1501 }, 1502 }, 1503 }; 1504 1505 static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = { 1506 .halt_reg = 0x1c000, 1507 .clkr = { 1508 .enable_reg = 0x1c000, 1509 .enable_mask = BIT(0), 1510 .hw.init = &(struct clk_init_data){ 1511 .name = "gcc_ultaudio_pcnoc_mport_clk", 1512 .parent_names = (const char *[]){ 1513 "pcnoc_bfdcd_clk_src", 1514 }, 1515 .num_parents = 1, 1516 .ops = &clk_branch2_ops, 1517 }, 1518 }, 1519 }; 1520 1521 static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = { 1522 .halt_reg = 0x1c004, 1523 .clkr = { 1524 .enable_reg = 0x1c004, 1525 .enable_mask = BIT(0), 1526 .hw.init = &(struct clk_init_data){ 1527 .name = "gcc_ultaudio_pcnoc_sway_clk", 1528 .parent_names = (const char *[]){ 1529 "pcnoc_bfdcd_clk_src", 1530 }, 1531 .num_parents = 1, 1532 .ops = &clk_branch2_ops, 1533 }, 1534 }, 1535 }; 1536 1537 static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = { 1538 F(100000000, P_GPLL0, 8, 0, 0), 1539 F(160000000, P_GPLL0, 5, 0, 0), 1540 F(228570000, P_GPLL0, 3.5, 0, 0), 1541 { } 1542 }; 1543 1544 static struct clk_rcg2 vcodec0_clk_src = { 1545 .cmd_rcgr = 0x4C000, 1546 .mnd_width = 8, 1547 .hid_width = 5, 1548 .parent_map = gcc_xo_gpll0_map, 1549 .freq_tbl = ftbl_gcc_venus0_vcodec0_clk, 1550 .clkr.hw.init = &(struct clk_init_data){ 1551 .name = "vcodec0_clk_src", 1552 .parent_names = gcc_xo_gpll0, 1553 .num_parents = 2, 1554 .ops = &clk_rcg2_ops, 1555 }, 1556 }; 1557 1558 static struct clk_branch gcc_blsp1_ahb_clk = { 1559 .halt_reg = 0x01008, 1560 .halt_check = BRANCH_HALT_VOTED, 1561 .clkr = { 1562 .enable_reg = 0x45004, 1563 .enable_mask = BIT(10), 1564 .hw.init = &(struct clk_init_data){ 1565 .name = "gcc_blsp1_ahb_clk", 1566 .parent_names = (const char *[]){ 1567 "pcnoc_bfdcd_clk_src", 1568 }, 1569 .num_parents = 1, 1570 .ops = &clk_branch2_ops, 1571 }, 1572 }, 1573 }; 1574 1575 static struct clk_branch gcc_blsp1_sleep_clk = { 1576 .halt_reg = 0x01004, 1577 .clkr = { 1578 .enable_reg = 0x01004, 1579 .enable_mask = BIT(0), 1580 .hw.init = &(struct clk_init_data){ 1581 .name = "gcc_blsp1_sleep_clk", 1582 .parent_names = (const char *[]){ 1583 "sleep_clk_src", 1584 }, 1585 .num_parents = 1, 1586 .flags = CLK_SET_RATE_PARENT, 1587 .ops = &clk_branch2_ops, 1588 }, 1589 }, 1590 }; 1591 1592 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1593 .halt_reg = 0x02008, 1594 .clkr = { 1595 .enable_reg = 0x02008, 1596 .enable_mask = BIT(0), 1597 .hw.init = &(struct clk_init_data){ 1598 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1599 .parent_names = (const char *[]){ 1600 "blsp1_qup1_i2c_apps_clk_src", 1601 }, 1602 .num_parents = 1, 1603 .flags = CLK_SET_RATE_PARENT, 1604 .ops = &clk_branch2_ops, 1605 }, 1606 }, 1607 }; 1608 1609 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1610 .halt_reg = 0x02004, 1611 .clkr = { 1612 .enable_reg = 0x02004, 1613 .enable_mask = BIT(0), 1614 .hw.init = &(struct clk_init_data){ 1615 .name = "gcc_blsp1_qup1_spi_apps_clk", 1616 .parent_names = (const char *[]){ 1617 "blsp1_qup1_spi_apps_clk_src", 1618 }, 1619 .num_parents = 1, 1620 .flags = CLK_SET_RATE_PARENT, 1621 .ops = &clk_branch2_ops, 1622 }, 1623 }, 1624 }; 1625 1626 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1627 .halt_reg = 0x03010, 1628 .clkr = { 1629 .enable_reg = 0x03010, 1630 .enable_mask = BIT(0), 1631 .hw.init = &(struct clk_init_data){ 1632 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1633 .parent_names = (const char *[]){ 1634 "blsp1_qup2_i2c_apps_clk_src", 1635 }, 1636 .num_parents = 1, 1637 .flags = CLK_SET_RATE_PARENT, 1638 .ops = &clk_branch2_ops, 1639 }, 1640 }, 1641 }; 1642 1643 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1644 .halt_reg = 0x0300c, 1645 .clkr = { 1646 .enable_reg = 0x0300c, 1647 .enable_mask = BIT(0), 1648 .hw.init = &(struct clk_init_data){ 1649 .name = "gcc_blsp1_qup2_spi_apps_clk", 1650 .parent_names = (const char *[]){ 1651 "blsp1_qup2_spi_apps_clk_src", 1652 }, 1653 .num_parents = 1, 1654 .flags = CLK_SET_RATE_PARENT, 1655 .ops = &clk_branch2_ops, 1656 }, 1657 }, 1658 }; 1659 1660 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1661 .halt_reg = 0x04020, 1662 .clkr = { 1663 .enable_reg = 0x04020, 1664 .enable_mask = BIT(0), 1665 .hw.init = &(struct clk_init_data){ 1666 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1667 .parent_names = (const char *[]){ 1668 "blsp1_qup3_i2c_apps_clk_src", 1669 }, 1670 .num_parents = 1, 1671 .flags = CLK_SET_RATE_PARENT, 1672 .ops = &clk_branch2_ops, 1673 }, 1674 }, 1675 }; 1676 1677 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1678 .halt_reg = 0x0401c, 1679 .clkr = { 1680 .enable_reg = 0x0401c, 1681 .enable_mask = BIT(0), 1682 .hw.init = &(struct clk_init_data){ 1683 .name = "gcc_blsp1_qup3_spi_apps_clk", 1684 .parent_names = (const char *[]){ 1685 "blsp1_qup3_spi_apps_clk_src", 1686 }, 1687 .num_parents = 1, 1688 .flags = CLK_SET_RATE_PARENT, 1689 .ops = &clk_branch2_ops, 1690 }, 1691 }, 1692 }; 1693 1694 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1695 .halt_reg = 0x05020, 1696 .clkr = { 1697 .enable_reg = 0x05020, 1698 .enable_mask = BIT(0), 1699 .hw.init = &(struct clk_init_data){ 1700 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1701 .parent_names = (const char *[]){ 1702 "blsp1_qup4_i2c_apps_clk_src", 1703 }, 1704 .num_parents = 1, 1705 .flags = CLK_SET_RATE_PARENT, 1706 .ops = &clk_branch2_ops, 1707 }, 1708 }, 1709 }; 1710 1711 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1712 .halt_reg = 0x0501c, 1713 .clkr = { 1714 .enable_reg = 0x0501c, 1715 .enable_mask = BIT(0), 1716 .hw.init = &(struct clk_init_data){ 1717 .name = "gcc_blsp1_qup4_spi_apps_clk", 1718 .parent_names = (const char *[]){ 1719 "blsp1_qup4_spi_apps_clk_src", 1720 }, 1721 .num_parents = 1, 1722 .flags = CLK_SET_RATE_PARENT, 1723 .ops = &clk_branch2_ops, 1724 }, 1725 }, 1726 }; 1727 1728 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 1729 .halt_reg = 0x06020, 1730 .clkr = { 1731 .enable_reg = 0x06020, 1732 .enable_mask = BIT(0), 1733 .hw.init = &(struct clk_init_data){ 1734 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1735 .parent_names = (const char *[]){ 1736 "blsp1_qup5_i2c_apps_clk_src", 1737 }, 1738 .num_parents = 1, 1739 .flags = CLK_SET_RATE_PARENT, 1740 .ops = &clk_branch2_ops, 1741 }, 1742 }, 1743 }; 1744 1745 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 1746 .halt_reg = 0x0601c, 1747 .clkr = { 1748 .enable_reg = 0x0601c, 1749 .enable_mask = BIT(0), 1750 .hw.init = &(struct clk_init_data){ 1751 .name = "gcc_blsp1_qup5_spi_apps_clk", 1752 .parent_names = (const char *[]){ 1753 "blsp1_qup5_spi_apps_clk_src", 1754 }, 1755 .num_parents = 1, 1756 .flags = CLK_SET_RATE_PARENT, 1757 .ops = &clk_branch2_ops, 1758 }, 1759 }, 1760 }; 1761 1762 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 1763 .halt_reg = 0x07020, 1764 .clkr = { 1765 .enable_reg = 0x07020, 1766 .enable_mask = BIT(0), 1767 .hw.init = &(struct clk_init_data){ 1768 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1769 .parent_names = (const char *[]){ 1770 "blsp1_qup6_i2c_apps_clk_src", 1771 }, 1772 .num_parents = 1, 1773 .flags = CLK_SET_RATE_PARENT, 1774 .ops = &clk_branch2_ops, 1775 }, 1776 }, 1777 }; 1778 1779 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 1780 .halt_reg = 0x0701c, 1781 .clkr = { 1782 .enable_reg = 0x0701c, 1783 .enable_mask = BIT(0), 1784 .hw.init = &(struct clk_init_data){ 1785 .name = "gcc_blsp1_qup6_spi_apps_clk", 1786 .parent_names = (const char *[]){ 1787 "blsp1_qup6_spi_apps_clk_src", 1788 }, 1789 .num_parents = 1, 1790 .flags = CLK_SET_RATE_PARENT, 1791 .ops = &clk_branch2_ops, 1792 }, 1793 }, 1794 }; 1795 1796 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1797 .halt_reg = 0x0203c, 1798 .clkr = { 1799 .enable_reg = 0x0203c, 1800 .enable_mask = BIT(0), 1801 .hw.init = &(struct clk_init_data){ 1802 .name = "gcc_blsp1_uart1_apps_clk", 1803 .parent_names = (const char *[]){ 1804 "blsp1_uart1_apps_clk_src", 1805 }, 1806 .num_parents = 1, 1807 .flags = CLK_SET_RATE_PARENT, 1808 .ops = &clk_branch2_ops, 1809 }, 1810 }, 1811 }; 1812 1813 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1814 .halt_reg = 0x0302c, 1815 .clkr = { 1816 .enable_reg = 0x0302c, 1817 .enable_mask = BIT(0), 1818 .hw.init = &(struct clk_init_data){ 1819 .name = "gcc_blsp1_uart2_apps_clk", 1820 .parent_names = (const char *[]){ 1821 "blsp1_uart2_apps_clk_src", 1822 }, 1823 .num_parents = 1, 1824 .flags = CLK_SET_RATE_PARENT, 1825 .ops = &clk_branch2_ops, 1826 }, 1827 }, 1828 }; 1829 1830 static struct clk_branch gcc_boot_rom_ahb_clk = { 1831 .halt_reg = 0x1300c, 1832 .halt_check = BRANCH_HALT_VOTED, 1833 .clkr = { 1834 .enable_reg = 0x45004, 1835 .enable_mask = BIT(7), 1836 .hw.init = &(struct clk_init_data){ 1837 .name = "gcc_boot_rom_ahb_clk", 1838 .parent_names = (const char *[]){ 1839 "pcnoc_bfdcd_clk_src", 1840 }, 1841 .num_parents = 1, 1842 .ops = &clk_branch2_ops, 1843 }, 1844 }, 1845 }; 1846 1847 static struct clk_branch gcc_camss_cci_ahb_clk = { 1848 .halt_reg = 0x5101c, 1849 .clkr = { 1850 .enable_reg = 0x5101c, 1851 .enable_mask = BIT(0), 1852 .hw.init = &(struct clk_init_data){ 1853 .name = "gcc_camss_cci_ahb_clk", 1854 .parent_names = (const char *[]){ 1855 "camss_ahb_clk_src", 1856 }, 1857 .num_parents = 1, 1858 .flags = CLK_SET_RATE_PARENT, 1859 .ops = &clk_branch2_ops, 1860 }, 1861 }, 1862 }; 1863 1864 static struct clk_branch gcc_camss_cci_clk = { 1865 .halt_reg = 0x51018, 1866 .clkr = { 1867 .enable_reg = 0x51018, 1868 .enable_mask = BIT(0), 1869 .hw.init = &(struct clk_init_data){ 1870 .name = "gcc_camss_cci_clk", 1871 .parent_names = (const char *[]){ 1872 "cci_clk_src", 1873 }, 1874 .num_parents = 1, 1875 .flags = CLK_SET_RATE_PARENT, 1876 .ops = &clk_branch2_ops, 1877 }, 1878 }, 1879 }; 1880 1881 static struct clk_branch gcc_camss_csi0_ahb_clk = { 1882 .halt_reg = 0x4e040, 1883 .clkr = { 1884 .enable_reg = 0x4e040, 1885 .enable_mask = BIT(0), 1886 .hw.init = &(struct clk_init_data){ 1887 .name = "gcc_camss_csi0_ahb_clk", 1888 .parent_names = (const char *[]){ 1889 "camss_ahb_clk_src", 1890 }, 1891 .num_parents = 1, 1892 .flags = CLK_SET_RATE_PARENT, 1893 .ops = &clk_branch2_ops, 1894 }, 1895 }, 1896 }; 1897 1898 static struct clk_branch gcc_camss_csi0_clk = { 1899 .halt_reg = 0x4e03c, 1900 .clkr = { 1901 .enable_reg = 0x4e03c, 1902 .enable_mask = BIT(0), 1903 .hw.init = &(struct clk_init_data){ 1904 .name = "gcc_camss_csi0_clk", 1905 .parent_names = (const char *[]){ 1906 "csi0_clk_src", 1907 }, 1908 .num_parents = 1, 1909 .flags = CLK_SET_RATE_PARENT, 1910 .ops = &clk_branch2_ops, 1911 }, 1912 }, 1913 }; 1914 1915 static struct clk_branch gcc_camss_csi0phy_clk = { 1916 .halt_reg = 0x4e048, 1917 .clkr = { 1918 .enable_reg = 0x4e048, 1919 .enable_mask = BIT(0), 1920 .hw.init = &(struct clk_init_data){ 1921 .name = "gcc_camss_csi0phy_clk", 1922 .parent_names = (const char *[]){ 1923 "csi0_clk_src", 1924 }, 1925 .num_parents = 1, 1926 .flags = CLK_SET_RATE_PARENT, 1927 .ops = &clk_branch2_ops, 1928 }, 1929 }, 1930 }; 1931 1932 static struct clk_branch gcc_camss_csi0pix_clk = { 1933 .halt_reg = 0x4e058, 1934 .clkr = { 1935 .enable_reg = 0x4e058, 1936 .enable_mask = BIT(0), 1937 .hw.init = &(struct clk_init_data){ 1938 .name = "gcc_camss_csi0pix_clk", 1939 .parent_names = (const char *[]){ 1940 "csi0_clk_src", 1941 }, 1942 .num_parents = 1, 1943 .flags = CLK_SET_RATE_PARENT, 1944 .ops = &clk_branch2_ops, 1945 }, 1946 }, 1947 }; 1948 1949 static struct clk_branch gcc_camss_csi0rdi_clk = { 1950 .halt_reg = 0x4e050, 1951 .clkr = { 1952 .enable_reg = 0x4e050, 1953 .enable_mask = BIT(0), 1954 .hw.init = &(struct clk_init_data){ 1955 .name = "gcc_camss_csi0rdi_clk", 1956 .parent_names = (const char *[]){ 1957 "csi0_clk_src", 1958 }, 1959 .num_parents = 1, 1960 .flags = CLK_SET_RATE_PARENT, 1961 .ops = &clk_branch2_ops, 1962 }, 1963 }, 1964 }; 1965 1966 static struct clk_branch gcc_camss_csi1_ahb_clk = { 1967 .halt_reg = 0x4f040, 1968 .clkr = { 1969 .enable_reg = 0x4f040, 1970 .enable_mask = BIT(0), 1971 .hw.init = &(struct clk_init_data){ 1972 .name = "gcc_camss_csi1_ahb_clk", 1973 .parent_names = (const char *[]){ 1974 "camss_ahb_clk_src", 1975 }, 1976 .num_parents = 1, 1977 .flags = CLK_SET_RATE_PARENT, 1978 .ops = &clk_branch2_ops, 1979 }, 1980 }, 1981 }; 1982 1983 static struct clk_branch gcc_camss_csi1_clk = { 1984 .halt_reg = 0x4f03c, 1985 .clkr = { 1986 .enable_reg = 0x4f03c, 1987 .enable_mask = BIT(0), 1988 .hw.init = &(struct clk_init_data){ 1989 .name = "gcc_camss_csi1_clk", 1990 .parent_names = (const char *[]){ 1991 "csi1_clk_src", 1992 }, 1993 .num_parents = 1, 1994 .flags = CLK_SET_RATE_PARENT, 1995 .ops = &clk_branch2_ops, 1996 }, 1997 }, 1998 }; 1999 2000 static struct clk_branch gcc_camss_csi1phy_clk = { 2001 .halt_reg = 0x4f048, 2002 .clkr = { 2003 .enable_reg = 0x4f048, 2004 .enable_mask = BIT(0), 2005 .hw.init = &(struct clk_init_data){ 2006 .name = "gcc_camss_csi1phy_clk", 2007 .parent_names = (const char *[]){ 2008 "csi1_clk_src", 2009 }, 2010 .num_parents = 1, 2011 .flags = CLK_SET_RATE_PARENT, 2012 .ops = &clk_branch2_ops, 2013 }, 2014 }, 2015 }; 2016 2017 static struct clk_branch gcc_camss_csi1pix_clk = { 2018 .halt_reg = 0x4f058, 2019 .clkr = { 2020 .enable_reg = 0x4f058, 2021 .enable_mask = BIT(0), 2022 .hw.init = &(struct clk_init_data){ 2023 .name = "gcc_camss_csi1pix_clk", 2024 .parent_names = (const char *[]){ 2025 "csi1_clk_src", 2026 }, 2027 .num_parents = 1, 2028 .flags = CLK_SET_RATE_PARENT, 2029 .ops = &clk_branch2_ops, 2030 }, 2031 }, 2032 }; 2033 2034 static struct clk_branch gcc_camss_csi1rdi_clk = { 2035 .halt_reg = 0x4f050, 2036 .clkr = { 2037 .enable_reg = 0x4f050, 2038 .enable_mask = BIT(0), 2039 .hw.init = &(struct clk_init_data){ 2040 .name = "gcc_camss_csi1rdi_clk", 2041 .parent_names = (const char *[]){ 2042 "csi1_clk_src", 2043 }, 2044 .num_parents = 1, 2045 .flags = CLK_SET_RATE_PARENT, 2046 .ops = &clk_branch2_ops, 2047 }, 2048 }, 2049 }; 2050 2051 static struct clk_branch gcc_camss_csi_vfe0_clk = { 2052 .halt_reg = 0x58050, 2053 .clkr = { 2054 .enable_reg = 0x58050, 2055 .enable_mask = BIT(0), 2056 .hw.init = &(struct clk_init_data){ 2057 .name = "gcc_camss_csi_vfe0_clk", 2058 .parent_names = (const char *[]){ 2059 "vfe0_clk_src", 2060 }, 2061 .num_parents = 1, 2062 .flags = CLK_SET_RATE_PARENT, 2063 .ops = &clk_branch2_ops, 2064 }, 2065 }, 2066 }; 2067 2068 static struct clk_branch gcc_camss_gp0_clk = { 2069 .halt_reg = 0x54018, 2070 .clkr = { 2071 .enable_reg = 0x54018, 2072 .enable_mask = BIT(0), 2073 .hw.init = &(struct clk_init_data){ 2074 .name = "gcc_camss_gp0_clk", 2075 .parent_names = (const char *[]){ 2076 "camss_gp0_clk_src", 2077 }, 2078 .num_parents = 1, 2079 .flags = CLK_SET_RATE_PARENT, 2080 .ops = &clk_branch2_ops, 2081 }, 2082 }, 2083 }; 2084 2085 static struct clk_branch gcc_camss_gp1_clk = { 2086 .halt_reg = 0x55018, 2087 .clkr = { 2088 .enable_reg = 0x55018, 2089 .enable_mask = BIT(0), 2090 .hw.init = &(struct clk_init_data){ 2091 .name = "gcc_camss_gp1_clk", 2092 .parent_names = (const char *[]){ 2093 "camss_gp1_clk_src", 2094 }, 2095 .num_parents = 1, 2096 .flags = CLK_SET_RATE_PARENT, 2097 .ops = &clk_branch2_ops, 2098 }, 2099 }, 2100 }; 2101 2102 static struct clk_branch gcc_camss_ispif_ahb_clk = { 2103 .halt_reg = 0x50004, 2104 .clkr = { 2105 .enable_reg = 0x50004, 2106 .enable_mask = BIT(0), 2107 .hw.init = &(struct clk_init_data){ 2108 .name = "gcc_camss_ispif_ahb_clk", 2109 .parent_names = (const char *[]){ 2110 "camss_ahb_clk_src", 2111 }, 2112 .num_parents = 1, 2113 .flags = CLK_SET_RATE_PARENT, 2114 .ops = &clk_branch2_ops, 2115 }, 2116 }, 2117 }; 2118 2119 static struct clk_branch gcc_camss_jpeg0_clk = { 2120 .halt_reg = 0x57020, 2121 .clkr = { 2122 .enable_reg = 0x57020, 2123 .enable_mask = BIT(0), 2124 .hw.init = &(struct clk_init_data){ 2125 .name = "gcc_camss_jpeg0_clk", 2126 .parent_names = (const char *[]){ 2127 "jpeg0_clk_src", 2128 }, 2129 .num_parents = 1, 2130 .flags = CLK_SET_RATE_PARENT, 2131 .ops = &clk_branch2_ops, 2132 }, 2133 }, 2134 }; 2135 2136 static struct clk_branch gcc_camss_jpeg_ahb_clk = { 2137 .halt_reg = 0x57024, 2138 .clkr = { 2139 .enable_reg = 0x57024, 2140 .enable_mask = BIT(0), 2141 .hw.init = &(struct clk_init_data){ 2142 .name = "gcc_camss_jpeg_ahb_clk", 2143 .parent_names = (const char *[]){ 2144 "camss_ahb_clk_src", 2145 }, 2146 .num_parents = 1, 2147 .flags = CLK_SET_RATE_PARENT, 2148 .ops = &clk_branch2_ops, 2149 }, 2150 }, 2151 }; 2152 2153 static struct clk_branch gcc_camss_jpeg_axi_clk = { 2154 .halt_reg = 0x57028, 2155 .clkr = { 2156 .enable_reg = 0x57028, 2157 .enable_mask = BIT(0), 2158 .hw.init = &(struct clk_init_data){ 2159 .name = "gcc_camss_jpeg_axi_clk", 2160 .parent_names = (const char *[]){ 2161 "system_noc_bfdcd_clk_src", 2162 }, 2163 .num_parents = 1, 2164 .flags = CLK_SET_RATE_PARENT, 2165 .ops = &clk_branch2_ops, 2166 }, 2167 }, 2168 }; 2169 2170 static struct clk_branch gcc_camss_mclk0_clk = { 2171 .halt_reg = 0x52018, 2172 .clkr = { 2173 .enable_reg = 0x52018, 2174 .enable_mask = BIT(0), 2175 .hw.init = &(struct clk_init_data){ 2176 .name = "gcc_camss_mclk0_clk", 2177 .parent_names = (const char *[]){ 2178 "mclk0_clk_src", 2179 }, 2180 .num_parents = 1, 2181 .flags = CLK_SET_RATE_PARENT, 2182 .ops = &clk_branch2_ops, 2183 }, 2184 }, 2185 }; 2186 2187 static struct clk_branch gcc_camss_mclk1_clk = { 2188 .halt_reg = 0x53018, 2189 .clkr = { 2190 .enable_reg = 0x53018, 2191 .enable_mask = BIT(0), 2192 .hw.init = &(struct clk_init_data){ 2193 .name = "gcc_camss_mclk1_clk", 2194 .parent_names = (const char *[]){ 2195 "mclk1_clk_src", 2196 }, 2197 .num_parents = 1, 2198 .flags = CLK_SET_RATE_PARENT, 2199 .ops = &clk_branch2_ops, 2200 }, 2201 }, 2202 }; 2203 2204 static struct clk_branch gcc_camss_micro_ahb_clk = { 2205 .halt_reg = 0x5600c, 2206 .clkr = { 2207 .enable_reg = 0x5600c, 2208 .enable_mask = BIT(0), 2209 .hw.init = &(struct clk_init_data){ 2210 .name = "gcc_camss_micro_ahb_clk", 2211 .parent_names = (const char *[]){ 2212 "camss_ahb_clk_src", 2213 }, 2214 .num_parents = 1, 2215 .flags = CLK_SET_RATE_PARENT, 2216 .ops = &clk_branch2_ops, 2217 }, 2218 }, 2219 }; 2220 2221 static struct clk_branch gcc_camss_csi0phytimer_clk = { 2222 .halt_reg = 0x4e01c, 2223 .clkr = { 2224 .enable_reg = 0x4e01c, 2225 .enable_mask = BIT(0), 2226 .hw.init = &(struct clk_init_data){ 2227 .name = "gcc_camss_csi0phytimer_clk", 2228 .parent_names = (const char *[]){ 2229 "csi0phytimer_clk_src", 2230 }, 2231 .num_parents = 1, 2232 .flags = CLK_SET_RATE_PARENT, 2233 .ops = &clk_branch2_ops, 2234 }, 2235 }, 2236 }; 2237 2238 static struct clk_branch gcc_camss_csi1phytimer_clk = { 2239 .halt_reg = 0x4f01c, 2240 .clkr = { 2241 .enable_reg = 0x4f01c, 2242 .enable_mask = BIT(0), 2243 .hw.init = &(struct clk_init_data){ 2244 .name = "gcc_camss_csi1phytimer_clk", 2245 .parent_names = (const char *[]){ 2246 "csi1phytimer_clk_src", 2247 }, 2248 .num_parents = 1, 2249 .flags = CLK_SET_RATE_PARENT, 2250 .ops = &clk_branch2_ops, 2251 }, 2252 }, 2253 }; 2254 2255 static struct clk_branch gcc_camss_ahb_clk = { 2256 .halt_reg = 0x5a014, 2257 .clkr = { 2258 .enable_reg = 0x5a014, 2259 .enable_mask = BIT(0), 2260 .hw.init = &(struct clk_init_data){ 2261 .name = "gcc_camss_ahb_clk", 2262 .parent_names = (const char *[]){ 2263 "camss_ahb_clk_src", 2264 }, 2265 .num_parents = 1, 2266 .flags = CLK_SET_RATE_PARENT, 2267 .ops = &clk_branch2_ops, 2268 }, 2269 }, 2270 }; 2271 2272 static struct clk_branch gcc_camss_top_ahb_clk = { 2273 .halt_reg = 0x56004, 2274 .clkr = { 2275 .enable_reg = 0x56004, 2276 .enable_mask = BIT(0), 2277 .hw.init = &(struct clk_init_data){ 2278 .name = "gcc_camss_top_ahb_clk", 2279 .parent_names = (const char *[]){ 2280 "pcnoc_bfdcd_clk_src", 2281 }, 2282 .num_parents = 1, 2283 .flags = CLK_SET_RATE_PARENT, 2284 .ops = &clk_branch2_ops, 2285 }, 2286 }, 2287 }; 2288 2289 static struct clk_branch gcc_camss_cpp_ahb_clk = { 2290 .halt_reg = 0x58040, 2291 .clkr = { 2292 .enable_reg = 0x58040, 2293 .enable_mask = BIT(0), 2294 .hw.init = &(struct clk_init_data){ 2295 .name = "gcc_camss_cpp_ahb_clk", 2296 .parent_names = (const char *[]){ 2297 "camss_ahb_clk_src", 2298 }, 2299 .num_parents = 1, 2300 .flags = CLK_SET_RATE_PARENT, 2301 .ops = &clk_branch2_ops, 2302 }, 2303 }, 2304 }; 2305 2306 static struct clk_branch gcc_camss_cpp_clk = { 2307 .halt_reg = 0x5803c, 2308 .clkr = { 2309 .enable_reg = 0x5803c, 2310 .enable_mask = BIT(0), 2311 .hw.init = &(struct clk_init_data){ 2312 .name = "gcc_camss_cpp_clk", 2313 .parent_names = (const char *[]){ 2314 "cpp_clk_src", 2315 }, 2316 .num_parents = 1, 2317 .flags = CLK_SET_RATE_PARENT, 2318 .ops = &clk_branch2_ops, 2319 }, 2320 }, 2321 }; 2322 2323 static struct clk_branch gcc_camss_vfe0_clk = { 2324 .halt_reg = 0x58038, 2325 .clkr = { 2326 .enable_reg = 0x58038, 2327 .enable_mask = BIT(0), 2328 .hw.init = &(struct clk_init_data){ 2329 .name = "gcc_camss_vfe0_clk", 2330 .parent_names = (const char *[]){ 2331 "vfe0_clk_src", 2332 }, 2333 .num_parents = 1, 2334 .flags = CLK_SET_RATE_PARENT, 2335 .ops = &clk_branch2_ops, 2336 }, 2337 }, 2338 }; 2339 2340 static struct clk_branch gcc_camss_vfe_ahb_clk = { 2341 .halt_reg = 0x58044, 2342 .clkr = { 2343 .enable_reg = 0x58044, 2344 .enable_mask = BIT(0), 2345 .hw.init = &(struct clk_init_data){ 2346 .name = "gcc_camss_vfe_ahb_clk", 2347 .parent_names = (const char *[]){ 2348 "camss_ahb_clk_src", 2349 }, 2350 .num_parents = 1, 2351 .flags = CLK_SET_RATE_PARENT, 2352 .ops = &clk_branch2_ops, 2353 }, 2354 }, 2355 }; 2356 2357 static struct clk_branch gcc_camss_vfe_axi_clk = { 2358 .halt_reg = 0x58048, 2359 .clkr = { 2360 .enable_reg = 0x58048, 2361 .enable_mask = BIT(0), 2362 .hw.init = &(struct clk_init_data){ 2363 .name = "gcc_camss_vfe_axi_clk", 2364 .parent_names = (const char *[]){ 2365 "system_noc_bfdcd_clk_src", 2366 }, 2367 .num_parents = 1, 2368 .flags = CLK_SET_RATE_PARENT, 2369 .ops = &clk_branch2_ops, 2370 }, 2371 }, 2372 }; 2373 2374 static struct clk_branch gcc_crypto_ahb_clk = { 2375 .halt_reg = 0x16024, 2376 .halt_check = BRANCH_HALT_VOTED, 2377 .clkr = { 2378 .enable_reg = 0x45004, 2379 .enable_mask = BIT(0), 2380 .hw.init = &(struct clk_init_data){ 2381 .name = "gcc_crypto_ahb_clk", 2382 .parent_names = (const char *[]){ 2383 "pcnoc_bfdcd_clk_src", 2384 }, 2385 .num_parents = 1, 2386 .flags = CLK_SET_RATE_PARENT, 2387 .ops = &clk_branch2_ops, 2388 }, 2389 }, 2390 }; 2391 2392 static struct clk_branch gcc_crypto_axi_clk = { 2393 .halt_reg = 0x16020, 2394 .halt_check = BRANCH_HALT_VOTED, 2395 .clkr = { 2396 .enable_reg = 0x45004, 2397 .enable_mask = BIT(1), 2398 .hw.init = &(struct clk_init_data){ 2399 .name = "gcc_crypto_axi_clk", 2400 .parent_names = (const char *[]){ 2401 "pcnoc_bfdcd_clk_src", 2402 }, 2403 .num_parents = 1, 2404 .flags = CLK_SET_RATE_PARENT, 2405 .ops = &clk_branch2_ops, 2406 }, 2407 }, 2408 }; 2409 2410 static struct clk_branch gcc_crypto_clk = { 2411 .halt_reg = 0x1601c, 2412 .halt_check = BRANCH_HALT_VOTED, 2413 .clkr = { 2414 .enable_reg = 0x45004, 2415 .enable_mask = BIT(2), 2416 .hw.init = &(struct clk_init_data){ 2417 .name = "gcc_crypto_clk", 2418 .parent_names = (const char *[]){ 2419 "crypto_clk_src", 2420 }, 2421 .num_parents = 1, 2422 .flags = CLK_SET_RATE_PARENT, 2423 .ops = &clk_branch2_ops, 2424 }, 2425 }, 2426 }; 2427 2428 static struct clk_branch gcc_oxili_gmem_clk = { 2429 .halt_reg = 0x59024, 2430 .clkr = { 2431 .enable_reg = 0x59024, 2432 .enable_mask = BIT(0), 2433 .hw.init = &(struct clk_init_data){ 2434 .name = "gcc_oxili_gmem_clk", 2435 .parent_names = (const char *[]){ 2436 "gfx3d_clk_src", 2437 }, 2438 .num_parents = 1, 2439 .flags = CLK_SET_RATE_PARENT, 2440 .ops = &clk_branch2_ops, 2441 }, 2442 }, 2443 }; 2444 2445 static struct clk_branch gcc_gp1_clk = { 2446 .halt_reg = 0x08000, 2447 .clkr = { 2448 .enable_reg = 0x08000, 2449 .enable_mask = BIT(0), 2450 .hw.init = &(struct clk_init_data){ 2451 .name = "gcc_gp1_clk", 2452 .parent_names = (const char *[]){ 2453 "gp1_clk_src", 2454 }, 2455 .num_parents = 1, 2456 .flags = CLK_SET_RATE_PARENT, 2457 .ops = &clk_branch2_ops, 2458 }, 2459 }, 2460 }; 2461 2462 static struct clk_branch gcc_gp2_clk = { 2463 .halt_reg = 0x09000, 2464 .clkr = { 2465 .enable_reg = 0x09000, 2466 .enable_mask = BIT(0), 2467 .hw.init = &(struct clk_init_data){ 2468 .name = "gcc_gp2_clk", 2469 .parent_names = (const char *[]){ 2470 "gp2_clk_src", 2471 }, 2472 .num_parents = 1, 2473 .flags = CLK_SET_RATE_PARENT, 2474 .ops = &clk_branch2_ops, 2475 }, 2476 }, 2477 }; 2478 2479 static struct clk_branch gcc_gp3_clk = { 2480 .halt_reg = 0x0a000, 2481 .clkr = { 2482 .enable_reg = 0x0a000, 2483 .enable_mask = BIT(0), 2484 .hw.init = &(struct clk_init_data){ 2485 .name = "gcc_gp3_clk", 2486 .parent_names = (const char *[]){ 2487 "gp3_clk_src", 2488 }, 2489 .num_parents = 1, 2490 .flags = CLK_SET_RATE_PARENT, 2491 .ops = &clk_branch2_ops, 2492 }, 2493 }, 2494 }; 2495 2496 static struct clk_branch gcc_mdss_ahb_clk = { 2497 .halt_reg = 0x4d07c, 2498 .clkr = { 2499 .enable_reg = 0x4d07c, 2500 .enable_mask = BIT(0), 2501 .hw.init = &(struct clk_init_data){ 2502 .name = "gcc_mdss_ahb_clk", 2503 .parent_names = (const char *[]){ 2504 "pcnoc_bfdcd_clk_src", 2505 }, 2506 .num_parents = 1, 2507 .flags = CLK_SET_RATE_PARENT, 2508 .ops = &clk_branch2_ops, 2509 }, 2510 }, 2511 }; 2512 2513 static struct clk_branch gcc_mdss_axi_clk = { 2514 .halt_reg = 0x4d080, 2515 .clkr = { 2516 .enable_reg = 0x4d080, 2517 .enable_mask = BIT(0), 2518 .hw.init = &(struct clk_init_data){ 2519 .name = "gcc_mdss_axi_clk", 2520 .parent_names = (const char *[]){ 2521 "system_noc_bfdcd_clk_src", 2522 }, 2523 .num_parents = 1, 2524 .flags = CLK_SET_RATE_PARENT, 2525 .ops = &clk_branch2_ops, 2526 }, 2527 }, 2528 }; 2529 2530 static struct clk_branch gcc_mdss_byte0_clk = { 2531 .halt_reg = 0x4d094, 2532 .clkr = { 2533 .enable_reg = 0x4d094, 2534 .enable_mask = BIT(0), 2535 .hw.init = &(struct clk_init_data){ 2536 .name = "gcc_mdss_byte0_clk", 2537 .parent_names = (const char *[]){ 2538 "byte0_clk_src", 2539 }, 2540 .num_parents = 1, 2541 .flags = CLK_SET_RATE_PARENT, 2542 .ops = &clk_branch2_ops, 2543 }, 2544 }, 2545 }; 2546 2547 static struct clk_branch gcc_mdss_esc0_clk = { 2548 .halt_reg = 0x4d098, 2549 .clkr = { 2550 .enable_reg = 0x4d098, 2551 .enable_mask = BIT(0), 2552 .hw.init = &(struct clk_init_data){ 2553 .name = "gcc_mdss_esc0_clk", 2554 .parent_names = (const char *[]){ 2555 "esc0_clk_src", 2556 }, 2557 .num_parents = 1, 2558 .flags = CLK_SET_RATE_PARENT, 2559 .ops = &clk_branch2_ops, 2560 }, 2561 }, 2562 }; 2563 2564 static struct clk_branch gcc_mdss_mdp_clk = { 2565 .halt_reg = 0x4D088, 2566 .clkr = { 2567 .enable_reg = 0x4D088, 2568 .enable_mask = BIT(0), 2569 .hw.init = &(struct clk_init_data){ 2570 .name = "gcc_mdss_mdp_clk", 2571 .parent_names = (const char *[]){ 2572 "mdp_clk_src", 2573 }, 2574 .num_parents = 1, 2575 .flags = CLK_SET_RATE_PARENT, 2576 .ops = &clk_branch2_ops, 2577 }, 2578 }, 2579 }; 2580 2581 static struct clk_branch gcc_mdss_pclk0_clk = { 2582 .halt_reg = 0x4d084, 2583 .clkr = { 2584 .enable_reg = 0x4d084, 2585 .enable_mask = BIT(0), 2586 .hw.init = &(struct clk_init_data){ 2587 .name = "gcc_mdss_pclk0_clk", 2588 .parent_names = (const char *[]){ 2589 "pclk0_clk_src", 2590 }, 2591 .num_parents = 1, 2592 .flags = CLK_SET_RATE_PARENT, 2593 .ops = &clk_branch2_ops, 2594 }, 2595 }, 2596 }; 2597 2598 static struct clk_branch gcc_mdss_vsync_clk = { 2599 .halt_reg = 0x4d090, 2600 .clkr = { 2601 .enable_reg = 0x4d090, 2602 .enable_mask = BIT(0), 2603 .hw.init = &(struct clk_init_data){ 2604 .name = "gcc_mdss_vsync_clk", 2605 .parent_names = (const char *[]){ 2606 "vsync_clk_src", 2607 }, 2608 .num_parents = 1, 2609 .flags = CLK_SET_RATE_PARENT, 2610 .ops = &clk_branch2_ops, 2611 }, 2612 }, 2613 }; 2614 2615 static struct clk_branch gcc_mss_cfg_ahb_clk = { 2616 .halt_reg = 0x49000, 2617 .clkr = { 2618 .enable_reg = 0x49000, 2619 .enable_mask = BIT(0), 2620 .hw.init = &(struct clk_init_data){ 2621 .name = "gcc_mss_cfg_ahb_clk", 2622 .parent_names = (const char *[]){ 2623 "pcnoc_bfdcd_clk_src", 2624 }, 2625 .num_parents = 1, 2626 .flags = CLK_SET_RATE_PARENT, 2627 .ops = &clk_branch2_ops, 2628 }, 2629 }, 2630 }; 2631 2632 static struct clk_branch gcc_mss_q6_bimc_axi_clk = { 2633 .halt_reg = 0x49004, 2634 .clkr = { 2635 .enable_reg = 0x49004, 2636 .enable_mask = BIT(0), 2637 .hw.init = &(struct clk_init_data){ 2638 .name = "gcc_mss_q6_bimc_axi_clk", 2639 .parent_names = (const char *[]){ 2640 "bimc_ddr_clk_src", 2641 }, 2642 .num_parents = 1, 2643 .flags = CLK_SET_RATE_PARENT, 2644 .ops = &clk_branch2_ops, 2645 }, 2646 }, 2647 }; 2648 2649 static struct clk_branch gcc_oxili_ahb_clk = { 2650 .halt_reg = 0x59028, 2651 .clkr = { 2652 .enable_reg = 0x59028, 2653 .enable_mask = BIT(0), 2654 .hw.init = &(struct clk_init_data){ 2655 .name = "gcc_oxili_ahb_clk", 2656 .parent_names = (const char *[]){ 2657 "pcnoc_bfdcd_clk_src", 2658 }, 2659 .num_parents = 1, 2660 .flags = CLK_SET_RATE_PARENT, 2661 .ops = &clk_branch2_ops, 2662 }, 2663 }, 2664 }; 2665 2666 static struct clk_branch gcc_oxili_gfx3d_clk = { 2667 .halt_reg = 0x59020, 2668 .clkr = { 2669 .enable_reg = 0x59020, 2670 .enable_mask = BIT(0), 2671 .hw.init = &(struct clk_init_data){ 2672 .name = "gcc_oxili_gfx3d_clk", 2673 .parent_names = (const char *[]){ 2674 "gfx3d_clk_src", 2675 }, 2676 .num_parents = 1, 2677 .flags = CLK_SET_RATE_PARENT, 2678 .ops = &clk_branch2_ops, 2679 }, 2680 }, 2681 }; 2682 2683 static struct clk_branch gcc_pdm2_clk = { 2684 .halt_reg = 0x4400c, 2685 .clkr = { 2686 .enable_reg = 0x4400c, 2687 .enable_mask = BIT(0), 2688 .hw.init = &(struct clk_init_data){ 2689 .name = "gcc_pdm2_clk", 2690 .parent_names = (const char *[]){ 2691 "pdm2_clk_src", 2692 }, 2693 .num_parents = 1, 2694 .flags = CLK_SET_RATE_PARENT, 2695 .ops = &clk_branch2_ops, 2696 }, 2697 }, 2698 }; 2699 2700 static struct clk_branch gcc_pdm_ahb_clk = { 2701 .halt_reg = 0x44004, 2702 .clkr = { 2703 .enable_reg = 0x44004, 2704 .enable_mask = BIT(0), 2705 .hw.init = &(struct clk_init_data){ 2706 .name = "gcc_pdm_ahb_clk", 2707 .parent_names = (const char *[]){ 2708 "pcnoc_bfdcd_clk_src", 2709 }, 2710 .num_parents = 1, 2711 .flags = CLK_SET_RATE_PARENT, 2712 .ops = &clk_branch2_ops, 2713 }, 2714 }, 2715 }; 2716 2717 static struct clk_branch gcc_prng_ahb_clk = { 2718 .halt_reg = 0x13004, 2719 .halt_check = BRANCH_HALT_VOTED, 2720 .clkr = { 2721 .enable_reg = 0x45004, 2722 .enable_mask = BIT(8), 2723 .hw.init = &(struct clk_init_data){ 2724 .name = "gcc_prng_ahb_clk", 2725 .parent_names = (const char *[]){ 2726 "pcnoc_bfdcd_clk_src", 2727 }, 2728 .num_parents = 1, 2729 .ops = &clk_branch2_ops, 2730 }, 2731 }, 2732 }; 2733 2734 static struct clk_branch gcc_sdcc1_ahb_clk = { 2735 .halt_reg = 0x4201c, 2736 .clkr = { 2737 .enable_reg = 0x4201c, 2738 .enable_mask = BIT(0), 2739 .hw.init = &(struct clk_init_data){ 2740 .name = "gcc_sdcc1_ahb_clk", 2741 .parent_names = (const char *[]){ 2742 "pcnoc_bfdcd_clk_src", 2743 }, 2744 .num_parents = 1, 2745 .flags = CLK_SET_RATE_PARENT, 2746 .ops = &clk_branch2_ops, 2747 }, 2748 }, 2749 }; 2750 2751 static struct clk_branch gcc_sdcc1_apps_clk = { 2752 .halt_reg = 0x42018, 2753 .clkr = { 2754 .enable_reg = 0x42018, 2755 .enable_mask = BIT(0), 2756 .hw.init = &(struct clk_init_data){ 2757 .name = "gcc_sdcc1_apps_clk", 2758 .parent_names = (const char *[]){ 2759 "sdcc1_apps_clk_src", 2760 }, 2761 .num_parents = 1, 2762 .flags = CLK_SET_RATE_PARENT, 2763 .ops = &clk_branch2_ops, 2764 }, 2765 }, 2766 }; 2767 2768 static struct clk_branch gcc_sdcc2_ahb_clk = { 2769 .halt_reg = 0x4301c, 2770 .clkr = { 2771 .enable_reg = 0x4301c, 2772 .enable_mask = BIT(0), 2773 .hw.init = &(struct clk_init_data){ 2774 .name = "gcc_sdcc2_ahb_clk", 2775 .parent_names = (const char *[]){ 2776 "pcnoc_bfdcd_clk_src", 2777 }, 2778 .num_parents = 1, 2779 .flags = CLK_SET_RATE_PARENT, 2780 .ops = &clk_branch2_ops, 2781 }, 2782 }, 2783 }; 2784 2785 static struct clk_branch gcc_sdcc2_apps_clk = { 2786 .halt_reg = 0x43018, 2787 .clkr = { 2788 .enable_reg = 0x43018, 2789 .enable_mask = BIT(0), 2790 .hw.init = &(struct clk_init_data){ 2791 .name = "gcc_sdcc2_apps_clk", 2792 .parent_names = (const char *[]){ 2793 "sdcc2_apps_clk_src", 2794 }, 2795 .num_parents = 1, 2796 .flags = CLK_SET_RATE_PARENT, 2797 .ops = &clk_branch2_ops, 2798 }, 2799 }, 2800 }; 2801 2802 static struct clk_rcg2 bimc_ddr_clk_src = { 2803 .cmd_rcgr = 0x32004, 2804 .hid_width = 5, 2805 .parent_map = gcc_xo_gpll0_bimc_map, 2806 .clkr.hw.init = &(struct clk_init_data){ 2807 .name = "bimc_ddr_clk_src", 2808 .parent_names = gcc_xo_gpll0_bimc, 2809 .num_parents = 3, 2810 .ops = &clk_rcg2_ops, 2811 .flags = CLK_GET_RATE_NOCACHE, 2812 }, 2813 }; 2814 2815 static struct clk_branch gcc_apss_tcu_clk = { 2816 .halt_reg = 0x12018, 2817 .clkr = { 2818 .enable_reg = 0x4500c, 2819 .enable_mask = BIT(1), 2820 .hw.init = &(struct clk_init_data){ 2821 .name = "gcc_apss_tcu_clk", 2822 .parent_names = (const char *[]){ 2823 "bimc_ddr_clk_src", 2824 }, 2825 .num_parents = 1, 2826 .ops = &clk_branch2_ops, 2827 }, 2828 }, 2829 }; 2830 2831 static struct clk_branch gcc_gfx_tcu_clk = { 2832 .halt_reg = 0x12020, 2833 .clkr = { 2834 .enable_reg = 0x4500c, 2835 .enable_mask = BIT(2), 2836 .hw.init = &(struct clk_init_data){ 2837 .name = "gcc_gfx_tcu_clk", 2838 .parent_names = (const char *[]){ 2839 "bimc_ddr_clk_src", 2840 }, 2841 .num_parents = 1, 2842 .ops = &clk_branch2_ops, 2843 }, 2844 }, 2845 }; 2846 2847 static struct clk_branch gcc_gtcu_ahb_clk = { 2848 .halt_reg = 0x12044, 2849 .clkr = { 2850 .enable_reg = 0x4500c, 2851 .enable_mask = BIT(13), 2852 .hw.init = &(struct clk_init_data){ 2853 .name = "gcc_gtcu_ahb_clk", 2854 .parent_names = (const char *[]){ 2855 "pcnoc_bfdcd_clk_src", 2856 }, 2857 .num_parents = 1, 2858 .flags = CLK_SET_RATE_PARENT, 2859 .ops = &clk_branch2_ops, 2860 }, 2861 }, 2862 }; 2863 2864 static struct clk_branch gcc_bimc_gfx_clk = { 2865 .halt_reg = 0x31024, 2866 .clkr = { 2867 .enable_reg = 0x31024, 2868 .enable_mask = BIT(0), 2869 .hw.init = &(struct clk_init_data){ 2870 .name = "gcc_bimc_gfx_clk", 2871 .parent_names = (const char *[]){ 2872 "bimc_gpu_clk_src", 2873 }, 2874 .num_parents = 1, 2875 .flags = CLK_SET_RATE_PARENT, 2876 .ops = &clk_branch2_ops, 2877 }, 2878 }, 2879 }; 2880 2881 static struct clk_branch gcc_bimc_gpu_clk = { 2882 .halt_reg = 0x31040, 2883 .clkr = { 2884 .enable_reg = 0x31040, 2885 .enable_mask = BIT(0), 2886 .hw.init = &(struct clk_init_data){ 2887 .name = "gcc_bimc_gpu_clk", 2888 .parent_names = (const char *[]){ 2889 "bimc_gpu_clk_src", 2890 }, 2891 .num_parents = 1, 2892 .flags = CLK_SET_RATE_PARENT, 2893 .ops = &clk_branch2_ops, 2894 }, 2895 }, 2896 }; 2897 2898 static struct clk_branch gcc_jpeg_tbu_clk = { 2899 .halt_reg = 0x12034, 2900 .clkr = { 2901 .enable_reg = 0x4500c, 2902 .enable_mask = BIT(10), 2903 .hw.init = &(struct clk_init_data){ 2904 .name = "gcc_jpeg_tbu_clk", 2905 .parent_names = (const char *[]){ 2906 "system_noc_bfdcd_clk_src", 2907 }, 2908 .num_parents = 1, 2909 .flags = CLK_SET_RATE_PARENT, 2910 .ops = &clk_branch2_ops, 2911 }, 2912 }, 2913 }; 2914 2915 static struct clk_branch gcc_mdp_tbu_clk = { 2916 .halt_reg = 0x1201c, 2917 .clkr = { 2918 .enable_reg = 0x4500c, 2919 .enable_mask = BIT(4), 2920 .hw.init = &(struct clk_init_data){ 2921 .name = "gcc_mdp_tbu_clk", 2922 .parent_names = (const char *[]){ 2923 "system_noc_bfdcd_clk_src", 2924 }, 2925 .num_parents = 1, 2926 .flags = CLK_SET_RATE_PARENT, 2927 .ops = &clk_branch2_ops, 2928 }, 2929 }, 2930 }; 2931 2932 static struct clk_branch gcc_smmu_cfg_clk = { 2933 .halt_reg = 0x12038, 2934 .clkr = { 2935 .enable_reg = 0x4500c, 2936 .enable_mask = BIT(12), 2937 .hw.init = &(struct clk_init_data){ 2938 .name = "gcc_smmu_cfg_clk", 2939 .parent_names = (const char *[]){ 2940 "pcnoc_bfdcd_clk_src", 2941 }, 2942 .num_parents = 1, 2943 .flags = CLK_SET_RATE_PARENT, 2944 .ops = &clk_branch2_ops, 2945 }, 2946 }, 2947 }; 2948 2949 static struct clk_branch gcc_venus_tbu_clk = { 2950 .halt_reg = 0x12014, 2951 .clkr = { 2952 .enable_reg = 0x4500c, 2953 .enable_mask = BIT(5), 2954 .hw.init = &(struct clk_init_data){ 2955 .name = "gcc_venus_tbu_clk", 2956 .parent_names = (const char *[]){ 2957 "system_noc_bfdcd_clk_src", 2958 }, 2959 .num_parents = 1, 2960 .flags = CLK_SET_RATE_PARENT, 2961 .ops = &clk_branch2_ops, 2962 }, 2963 }, 2964 }; 2965 2966 static struct clk_branch gcc_vfe_tbu_clk = { 2967 .halt_reg = 0x1203c, 2968 .clkr = { 2969 .enable_reg = 0x4500c, 2970 .enable_mask = BIT(9), 2971 .hw.init = &(struct clk_init_data){ 2972 .name = "gcc_vfe_tbu_clk", 2973 .parent_names = (const char *[]){ 2974 "system_noc_bfdcd_clk_src", 2975 }, 2976 .num_parents = 1, 2977 .flags = CLK_SET_RATE_PARENT, 2978 .ops = &clk_branch2_ops, 2979 }, 2980 }, 2981 }; 2982 2983 static struct clk_branch gcc_usb2a_phy_sleep_clk = { 2984 .halt_reg = 0x4102c, 2985 .clkr = { 2986 .enable_reg = 0x4102c, 2987 .enable_mask = BIT(0), 2988 .hw.init = &(struct clk_init_data){ 2989 .name = "gcc_usb2a_phy_sleep_clk", 2990 .parent_names = (const char *[]){ 2991 "sleep_clk_src", 2992 }, 2993 .num_parents = 1, 2994 .flags = CLK_SET_RATE_PARENT, 2995 .ops = &clk_branch2_ops, 2996 }, 2997 }, 2998 }; 2999 3000 static struct clk_branch gcc_usb_hs_ahb_clk = { 3001 .halt_reg = 0x41008, 3002 .clkr = { 3003 .enable_reg = 0x41008, 3004 .enable_mask = BIT(0), 3005 .hw.init = &(struct clk_init_data){ 3006 .name = "gcc_usb_hs_ahb_clk", 3007 .parent_names = (const char *[]){ 3008 "pcnoc_bfdcd_clk_src", 3009 }, 3010 .num_parents = 1, 3011 .flags = CLK_SET_RATE_PARENT, 3012 .ops = &clk_branch2_ops, 3013 }, 3014 }, 3015 }; 3016 3017 static struct clk_branch gcc_usb_hs_system_clk = { 3018 .halt_reg = 0x41004, 3019 .clkr = { 3020 .enable_reg = 0x41004, 3021 .enable_mask = BIT(0), 3022 .hw.init = &(struct clk_init_data){ 3023 .name = "gcc_usb_hs_system_clk", 3024 .parent_names = (const char *[]){ 3025 "usb_hs_system_clk_src", 3026 }, 3027 .num_parents = 1, 3028 .flags = CLK_SET_RATE_PARENT, 3029 .ops = &clk_branch2_ops, 3030 }, 3031 }, 3032 }; 3033 3034 static struct clk_branch gcc_venus0_ahb_clk = { 3035 .halt_reg = 0x4c020, 3036 .clkr = { 3037 .enable_reg = 0x4c020, 3038 .enable_mask = BIT(0), 3039 .hw.init = &(struct clk_init_data){ 3040 .name = "gcc_venus0_ahb_clk", 3041 .parent_names = (const char *[]){ 3042 "pcnoc_bfdcd_clk_src", 3043 }, 3044 .num_parents = 1, 3045 .flags = CLK_SET_RATE_PARENT, 3046 .ops = &clk_branch2_ops, 3047 }, 3048 }, 3049 }; 3050 3051 static struct clk_branch gcc_venus0_axi_clk = { 3052 .halt_reg = 0x4c024, 3053 .clkr = { 3054 .enable_reg = 0x4c024, 3055 .enable_mask = BIT(0), 3056 .hw.init = &(struct clk_init_data){ 3057 .name = "gcc_venus0_axi_clk", 3058 .parent_names = (const char *[]){ 3059 "system_noc_bfdcd_clk_src", 3060 }, 3061 .num_parents = 1, 3062 .flags = CLK_SET_RATE_PARENT, 3063 .ops = &clk_branch2_ops, 3064 }, 3065 }, 3066 }; 3067 3068 static struct clk_branch gcc_venus0_vcodec0_clk = { 3069 .halt_reg = 0x4c01c, 3070 .clkr = { 3071 .enable_reg = 0x4c01c, 3072 .enable_mask = BIT(0), 3073 .hw.init = &(struct clk_init_data){ 3074 .name = "gcc_venus0_vcodec0_clk", 3075 .parent_names = (const char *[]){ 3076 "vcodec0_clk_src", 3077 }, 3078 .num_parents = 1, 3079 .flags = CLK_SET_RATE_PARENT, 3080 .ops = &clk_branch2_ops, 3081 }, 3082 }, 3083 }; 3084 3085 static struct gdsc venus_gdsc = { 3086 .gdscr = 0x4c018, 3087 .pd = { 3088 .name = "venus", 3089 }, 3090 .pwrsts = PWRSTS_OFF_ON, 3091 }; 3092 3093 static struct gdsc mdss_gdsc = { 3094 .gdscr = 0x4d078, 3095 .pd = { 3096 .name = "mdss", 3097 }, 3098 .pwrsts = PWRSTS_OFF_ON, 3099 }; 3100 3101 static struct gdsc jpeg_gdsc = { 3102 .gdscr = 0x5701c, 3103 .pd = { 3104 .name = "jpeg", 3105 }, 3106 .pwrsts = PWRSTS_OFF_ON, 3107 }; 3108 3109 static struct gdsc vfe_gdsc = { 3110 .gdscr = 0x58034, 3111 .pd = { 3112 .name = "vfe", 3113 }, 3114 .pwrsts = PWRSTS_OFF_ON, 3115 }; 3116 3117 static struct gdsc oxili_gdsc = { 3118 .gdscr = 0x5901c, 3119 .pd = { 3120 .name = "oxili", 3121 }, 3122 .pwrsts = PWRSTS_OFF_ON, 3123 }; 3124 3125 static struct clk_regmap *gcc_msm8916_clocks[] = { 3126 [GPLL0] = &gpll0.clkr, 3127 [GPLL0_VOTE] = &gpll0_vote, 3128 [BIMC_PLL] = &bimc_pll.clkr, 3129 [BIMC_PLL_VOTE] = &bimc_pll_vote, 3130 [GPLL1] = &gpll1.clkr, 3131 [GPLL1_VOTE] = &gpll1_vote, 3132 [GPLL2] = &gpll2.clkr, 3133 [GPLL2_VOTE] = &gpll2_vote, 3134 [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr, 3135 [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr, 3136 [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr, 3137 [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr, 3138 [CSI0_CLK_SRC] = &csi0_clk_src.clkr, 3139 [CSI1_CLK_SRC] = &csi1_clk_src.clkr, 3140 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, 3141 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, 3142 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 3143 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 3144 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 3145 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 3146 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 3147 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 3148 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 3149 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 3150 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 3151 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 3152 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 3153 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 3154 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 3155 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 3156 [CCI_CLK_SRC] = &cci_clk_src.clkr, 3157 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, 3158 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, 3159 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, 3160 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, 3161 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, 3162 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, 3163 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, 3164 [CPP_CLK_SRC] = &cpp_clk_src.clkr, 3165 [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr, 3166 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 3167 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 3168 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 3169 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, 3170 [ESC0_CLK_SRC] = &esc0_clk_src.clkr, 3171 [MDP_CLK_SRC] = &mdp_clk_src.clkr, 3172 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, 3173 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, 3174 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 3175 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 3176 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 3177 [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr, 3178 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, 3179 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr, 3180 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 3181 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr, 3182 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 3183 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 3184 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 3185 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 3186 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 3187 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 3188 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 3189 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 3190 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 3191 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 3192 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 3193 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 3194 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 3195 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 3196 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3197 [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr, 3198 [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr, 3199 [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr, 3200 [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr, 3201 [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr, 3202 [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr, 3203 [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr, 3204 [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr, 3205 [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr, 3206 [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr, 3207 [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr, 3208 [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr, 3209 [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr, 3210 [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr, 3211 [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr, 3212 [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr, 3213 [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr, 3214 [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr, 3215 [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr, 3216 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, 3217 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, 3218 [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr, 3219 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, 3220 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, 3221 [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr, 3222 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, 3223 [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr, 3224 [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr, 3225 [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr, 3226 [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr, 3227 [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr, 3228 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, 3229 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, 3230 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, 3231 [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr, 3232 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3233 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3234 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3235 [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr, 3236 [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr, 3237 [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr, 3238 [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr, 3239 [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr, 3240 [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr, 3241 [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr, 3242 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 3243 [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr, 3244 [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr, 3245 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3246 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3247 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3248 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 3249 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 3250 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3251 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3252 [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr, 3253 [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr, 3254 [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr, 3255 [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr, 3256 [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr, 3257 [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr, 3258 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, 3259 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, 3260 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, 3261 [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr, 3262 [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr, 3263 [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr, 3264 [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr, 3265 [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr, 3266 [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr, 3267 [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr, 3268 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, 3269 [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr, 3270 [ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr, 3271 [ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr, 3272 [ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr, 3273 [ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr, 3274 [ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr, 3275 [CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr, 3276 [GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr, 3277 [GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr, 3278 [GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr, 3279 [GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr, 3280 [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_clk.clkr, 3281 [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr, 3282 [GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr, 3283 [GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr, 3284 [GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr, 3285 [GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr, 3286 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, 3287 }; 3288 3289 static struct gdsc *gcc_msm8916_gdscs[] = { 3290 [VENUS_GDSC] = &venus_gdsc, 3291 [MDSS_GDSC] = &mdss_gdsc, 3292 [JPEG_GDSC] = &jpeg_gdsc, 3293 [VFE_GDSC] = &vfe_gdsc, 3294 [OXILI_GDSC] = &oxili_gdsc, 3295 }; 3296 3297 static const struct qcom_reset_map gcc_msm8916_resets[] = { 3298 [GCC_BLSP1_BCR] = { 0x01000 }, 3299 [GCC_BLSP1_QUP1_BCR] = { 0x02000 }, 3300 [GCC_BLSP1_UART1_BCR] = { 0x02038 }, 3301 [GCC_BLSP1_QUP2_BCR] = { 0x03008 }, 3302 [GCC_BLSP1_UART2_BCR] = { 0x03028 }, 3303 [GCC_BLSP1_QUP3_BCR] = { 0x04018 }, 3304 [GCC_BLSP1_QUP4_BCR] = { 0x05018 }, 3305 [GCC_BLSP1_QUP5_BCR] = { 0x06018 }, 3306 [GCC_BLSP1_QUP6_BCR] = { 0x07018 }, 3307 [GCC_IMEM_BCR] = { 0x0e000 }, 3308 [GCC_SMMU_BCR] = { 0x12000 }, 3309 [GCC_APSS_TCU_BCR] = { 0x12050 }, 3310 [GCC_SMMU_XPU_BCR] = { 0x12054 }, 3311 [GCC_PCNOC_TBU_BCR] = { 0x12058 }, 3312 [GCC_PRNG_BCR] = { 0x13000 }, 3313 [GCC_BOOT_ROM_BCR] = { 0x13008 }, 3314 [GCC_CRYPTO_BCR] = { 0x16000 }, 3315 [GCC_SEC_CTRL_BCR] = { 0x1a000 }, 3316 [GCC_AUDIO_CORE_BCR] = { 0x1c008 }, 3317 [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 }, 3318 [GCC_DEHR_BCR] = { 0x1f000 }, 3319 [GCC_SYSTEM_NOC_BCR] = { 0x26000 }, 3320 [GCC_PCNOC_BCR] = { 0x27018 }, 3321 [GCC_TCSR_BCR] = { 0x28000 }, 3322 [GCC_QDSS_BCR] = { 0x29000 }, 3323 [GCC_DCD_BCR] = { 0x2a000 }, 3324 [GCC_MSG_RAM_BCR] = { 0x2b000 }, 3325 [GCC_MPM_BCR] = { 0x2c000 }, 3326 [GCC_SPMI_BCR] = { 0x2e000 }, 3327 [GCC_SPDM_BCR] = { 0x2f000 }, 3328 [GCC_MM_SPDM_BCR] = { 0x2f024 }, 3329 [GCC_BIMC_BCR] = { 0x31000 }, 3330 [GCC_RBCPR_BCR] = { 0x33000 }, 3331 [GCC_TLMM_BCR] = { 0x34000 }, 3332 [GCC_USB_HS_BCR] = { 0x41000 }, 3333 [GCC_USB2A_PHY_BCR] = { 0x41028 }, 3334 [GCC_SDCC1_BCR] = { 0x42000 }, 3335 [GCC_SDCC2_BCR] = { 0x43000 }, 3336 [GCC_PDM_BCR] = { 0x44000 }, 3337 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 }, 3338 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 }, 3339 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 }, 3340 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 }, 3341 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 }, 3342 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 }, 3343 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 }, 3344 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 }, 3345 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 }, 3346 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 }, 3347 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 }, 3348 [GCC_MMSS_BCR] = { 0x4b000 }, 3349 [GCC_VENUS0_BCR] = { 0x4c014 }, 3350 [GCC_MDSS_BCR] = { 0x4d074 }, 3351 [GCC_CAMSS_PHY0_BCR] = { 0x4e018 }, 3352 [GCC_CAMSS_CSI0_BCR] = { 0x4e038 }, 3353 [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 }, 3354 [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c }, 3355 [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 }, 3356 [GCC_CAMSS_PHY1_BCR] = { 0x4f018 }, 3357 [GCC_CAMSS_CSI1_BCR] = { 0x4f038 }, 3358 [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 }, 3359 [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c }, 3360 [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 }, 3361 [GCC_CAMSS_ISPIF_BCR] = { 0x50000 }, 3362 [GCC_CAMSS_CCI_BCR] = { 0x51014 }, 3363 [GCC_CAMSS_MCLK0_BCR] = { 0x52014 }, 3364 [GCC_CAMSS_MCLK1_BCR] = { 0x53014 }, 3365 [GCC_CAMSS_GP0_BCR] = { 0x54014 }, 3366 [GCC_CAMSS_GP1_BCR] = { 0x55014 }, 3367 [GCC_CAMSS_TOP_BCR] = { 0x56000 }, 3368 [GCC_CAMSS_MICRO_BCR] = { 0x56008 }, 3369 [GCC_CAMSS_JPEG_BCR] = { 0x57018 }, 3370 [GCC_CAMSS_VFE_BCR] = { 0x58030 }, 3371 [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c }, 3372 [GCC_OXILI_BCR] = { 0x59018 }, 3373 [GCC_GMEM_BCR] = { 0x5902c }, 3374 [GCC_CAMSS_AHB_BCR] = { 0x5a018 }, 3375 [GCC_MDP_TBU_BCR] = { 0x62000 }, 3376 [GCC_GFX_TBU_BCR] = { 0x63000 }, 3377 [GCC_GFX_TCU_BCR] = { 0x64000 }, 3378 [GCC_MSS_TBU_AXI_BCR] = { 0x65000 }, 3379 [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 }, 3380 [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 }, 3381 [GCC_GTCU_AHB_BCR] = { 0x68000 }, 3382 [GCC_SMMU_CFG_BCR] = { 0x69000 }, 3383 [GCC_VFE_TBU_BCR] = { 0x6a000 }, 3384 [GCC_VENUS_TBU_BCR] = { 0x6b000 }, 3385 [GCC_JPEG_TBU_BCR] = { 0x6c000 }, 3386 [GCC_PRONTO_TBU_BCR] = { 0x6d000 }, 3387 [GCC_SMMU_CATS_BCR] = { 0x7c000 }, 3388 }; 3389 3390 static const struct regmap_config gcc_msm8916_regmap_config = { 3391 .reg_bits = 32, 3392 .reg_stride = 4, 3393 .val_bits = 32, 3394 .max_register = 0x80000, 3395 .fast_io = true, 3396 }; 3397 3398 static const struct qcom_cc_desc gcc_msm8916_desc = { 3399 .config = &gcc_msm8916_regmap_config, 3400 .clks = gcc_msm8916_clocks, 3401 .num_clks = ARRAY_SIZE(gcc_msm8916_clocks), 3402 .resets = gcc_msm8916_resets, 3403 .num_resets = ARRAY_SIZE(gcc_msm8916_resets), 3404 .gdscs = gcc_msm8916_gdscs, 3405 .num_gdscs = ARRAY_SIZE(gcc_msm8916_gdscs), 3406 }; 3407 3408 static const struct of_device_id gcc_msm8916_match_table[] = { 3409 { .compatible = "qcom,gcc-msm8916" }, 3410 { } 3411 }; 3412 MODULE_DEVICE_TABLE(of, gcc_msm8916_match_table); 3413 3414 static int gcc_msm8916_probe(struct platform_device *pdev) 3415 { 3416 int ret; 3417 struct device *dev = &pdev->dev; 3418 3419 ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000); 3420 if (ret) 3421 return ret; 3422 3423 ret = qcom_cc_register_sleep_clk(dev); 3424 if (ret) 3425 return ret; 3426 3427 return qcom_cc_probe(pdev, &gcc_msm8916_desc); 3428 } 3429 3430 static struct platform_driver gcc_msm8916_driver = { 3431 .probe = gcc_msm8916_probe, 3432 .driver = { 3433 .name = "gcc-msm8916", 3434 .of_match_table = gcc_msm8916_match_table, 3435 }, 3436 }; 3437 3438 static int __init gcc_msm8916_init(void) 3439 { 3440 return platform_driver_register(&gcc_msm8916_driver); 3441 } 3442 core_initcall(gcc_msm8916_init); 3443 3444 static void __exit gcc_msm8916_exit(void) 3445 { 3446 platform_driver_unregister(&gcc_msm8916_driver); 3447 } 3448 module_exit(gcc_msm8916_exit); 3449 3450 MODULE_DESCRIPTION("Qualcomm GCC MSM8916 Driver"); 3451 MODULE_LICENSE("GPL v2"); 3452 MODULE_ALIAS("platform:gcc-msm8916"); 3453