1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,milos-gcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap-divider.h" 18 #include "clk-regmap-mux.h" 19 #include "gdsc.h" 20 #include "reset.h" 21 22 /* Need to match the order of clocks in DT binding */ 23 enum { 24 DT_BI_TCXO, 25 DT_SLEEP_CLK, 26 DT_PCIE_0_PIPE, 27 DT_PCIE_1_PIPE, 28 DT_UFS_PHY_RX_SYMBOL_0, 29 DT_UFS_PHY_RX_SYMBOL_1, 30 DT_UFS_PHY_TX_SYMBOL_0, 31 DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE, 32 }; 33 34 enum { 35 P_BI_TCXO, 36 P_GCC_GPLL0_OUT_EVEN, 37 P_GCC_GPLL0_OUT_MAIN, 38 P_GCC_GPLL0_OUT_ODD, 39 P_GCC_GPLL2_OUT_MAIN, 40 P_GCC_GPLL4_OUT_MAIN, 41 P_GCC_GPLL6_OUT_MAIN, 42 P_GCC_GPLL7_OUT_MAIN, 43 P_GCC_GPLL9_OUT_MAIN, 44 P_PCIE_0_PIPE_CLK, 45 P_PCIE_1_PIPE_CLK, 46 P_SLEEP_CLK, 47 P_UFS_PHY_RX_SYMBOL_0_CLK, 48 P_UFS_PHY_RX_SYMBOL_1_CLK, 49 P_UFS_PHY_TX_SYMBOL_0_CLK, 50 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 51 }; 52 53 static struct clk_alpha_pll gcc_gpll0 = { 54 .offset = 0x0, 55 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 56 .clkr = { 57 .enable_reg = 0x52020, 58 .enable_mask = BIT(0), 59 .hw.init = &(const struct clk_init_data) { 60 .name = "gcc_gpll0", 61 .parent_data = &(const struct clk_parent_data) { 62 .index = DT_BI_TCXO, 63 }, 64 .num_parents = 1, 65 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 66 }, 67 }, 68 }; 69 70 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 71 { 0x1, 2 }, 72 { } 73 }; 74 75 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 76 .offset = 0x0, 77 .post_div_shift = 10, 78 .post_div_table = post_div_table_gcc_gpll0_out_even, 79 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 80 .width = 4, 81 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 82 .clkr.hw.init = &(const struct clk_init_data) { 83 .name = "gcc_gpll0_out_even", 84 .parent_hws = (const struct clk_hw*[]) { 85 &gcc_gpll0.clkr.hw, 86 }, 87 .num_parents = 1, 88 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 89 }, 90 }; 91 92 static struct clk_alpha_pll gcc_gpll2 = { 93 .offset = 0x2000, 94 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 95 .clkr = { 96 .enable_reg = 0x52020, 97 .enable_mask = BIT(2), 98 .hw.init = &(const struct clk_init_data) { 99 .name = "gcc_gpll2", 100 .parent_data = &(const struct clk_parent_data) { 101 .index = DT_BI_TCXO, 102 }, 103 .num_parents = 1, 104 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 105 }, 106 }, 107 }; 108 109 static struct clk_alpha_pll gcc_gpll4 = { 110 .offset = 0x4000, 111 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 112 .clkr = { 113 .enable_reg = 0x52020, 114 .enable_mask = BIT(4), 115 .hw.init = &(const struct clk_init_data) { 116 .name = "gcc_gpll4", 117 .parent_data = &(const struct clk_parent_data) { 118 .index = DT_BI_TCXO, 119 }, 120 .num_parents = 1, 121 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 122 }, 123 }, 124 }; 125 126 static struct clk_alpha_pll gcc_gpll6 = { 127 .offset = 0x6000, 128 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 129 .clkr = { 130 .enable_reg = 0x52020, 131 .enable_mask = BIT(6), 132 .hw.init = &(const struct clk_init_data) { 133 .name = "gcc_gpll6", 134 .parent_data = &(const struct clk_parent_data) { 135 .index = DT_BI_TCXO, 136 }, 137 .num_parents = 1, 138 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 139 }, 140 }, 141 }; 142 143 static struct clk_alpha_pll gcc_gpll7 = { 144 .offset = 0x7000, 145 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 146 .clkr = { 147 .enable_reg = 0x52020, 148 .enable_mask = BIT(7), 149 .hw.init = &(const struct clk_init_data) { 150 .name = "gcc_gpll7", 151 .parent_data = &(const struct clk_parent_data) { 152 .index = DT_BI_TCXO, 153 }, 154 .num_parents = 1, 155 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 156 }, 157 }, 158 }; 159 160 static struct clk_alpha_pll gcc_gpll9 = { 161 .offset = 0x9000, 162 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 163 .clkr = { 164 .enable_reg = 0x52020, 165 .enable_mask = BIT(9), 166 .hw.init = &(const struct clk_init_data) { 167 .name = "gcc_gpll9", 168 .parent_data = &(const struct clk_parent_data) { 169 .index = DT_BI_TCXO, 170 }, 171 .num_parents = 1, 172 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 173 }, 174 }, 175 }; 176 177 static const struct parent_map gcc_parent_map_0[] = { 178 { P_BI_TCXO, 0 }, 179 { P_GCC_GPLL0_OUT_MAIN, 1 }, 180 { P_GCC_GPLL0_OUT_EVEN, 6 }, 181 }; 182 183 static const struct clk_parent_data gcc_parent_data_0[] = { 184 { .index = DT_BI_TCXO }, 185 { .hw = &gcc_gpll0.clkr.hw }, 186 { .hw = &gcc_gpll0_out_even.clkr.hw }, 187 }; 188 189 static const struct parent_map gcc_parent_map_1[] = { 190 { P_BI_TCXO, 0 }, 191 { P_GCC_GPLL0_OUT_MAIN, 1 }, 192 { P_SLEEP_CLK, 5 }, 193 { P_GCC_GPLL0_OUT_EVEN, 6 }, 194 }; 195 196 static const struct clk_parent_data gcc_parent_data_1[] = { 197 { .index = DT_BI_TCXO }, 198 { .hw = &gcc_gpll0.clkr.hw }, 199 { .index = DT_SLEEP_CLK }, 200 { .hw = &gcc_gpll0_out_even.clkr.hw }, 201 }; 202 203 static const struct parent_map gcc_parent_map_2[] = { 204 { P_BI_TCXO, 0 }, 205 { P_GCC_GPLL0_OUT_MAIN, 1 }, 206 { P_GCC_GPLL4_OUT_MAIN, 5 }, 207 { P_GCC_GPLL0_OUT_EVEN, 6 }, 208 }; 209 210 static const struct clk_parent_data gcc_parent_data_2[] = { 211 { .index = DT_BI_TCXO }, 212 { .hw = &gcc_gpll0.clkr.hw }, 213 { .hw = &gcc_gpll4.clkr.hw }, 214 { .hw = &gcc_gpll0_out_even.clkr.hw }, 215 }; 216 217 static const struct parent_map gcc_parent_map_3[] = { 218 { P_BI_TCXO, 0 }, 219 { P_SLEEP_CLK, 5 }, 220 }; 221 222 static const struct clk_parent_data gcc_parent_data_3[] = { 223 { .index = DT_BI_TCXO }, 224 { .index = DT_SLEEP_CLK }, 225 }; 226 227 static const struct parent_map gcc_parent_map_4[] = { 228 { P_BI_TCXO, 0 }, 229 { P_GCC_GPLL0_OUT_MAIN, 1 }, 230 { P_GCC_GPLL6_OUT_MAIN, 2 }, 231 { P_GCC_GPLL7_OUT_MAIN, 3 }, 232 { P_GCC_GPLL0_OUT_EVEN, 6 }, 233 }; 234 235 static const struct clk_parent_data gcc_parent_data_4[] = { 236 { .index = DT_BI_TCXO }, 237 { .hw = &gcc_gpll0.clkr.hw }, 238 { .hw = &gcc_gpll6.clkr.hw }, 239 { .hw = &gcc_gpll7.clkr.hw }, 240 { .hw = &gcc_gpll0_out_even.clkr.hw }, 241 }; 242 243 static const struct parent_map gcc_parent_map_5[] = { 244 { P_BI_TCXO, 0 }, 245 }; 246 247 static const struct clk_parent_data gcc_parent_data_5[] = { 248 { .index = DT_BI_TCXO }, 249 }; 250 251 static const struct parent_map gcc_parent_map_6[] = { 252 { P_PCIE_0_PIPE_CLK, 0 }, 253 { P_BI_TCXO, 2 }, 254 }; 255 256 static const struct clk_parent_data gcc_parent_data_6[] = { 257 { .index = DT_PCIE_0_PIPE }, 258 { .index = DT_BI_TCXO }, 259 }; 260 261 static const struct parent_map gcc_parent_map_7[] = { 262 { P_PCIE_1_PIPE_CLK, 0 }, 263 { P_BI_TCXO, 2 }, 264 }; 265 266 static const struct clk_parent_data gcc_parent_data_7[] = { 267 { .index = DT_PCIE_1_PIPE }, 268 { .index = DT_BI_TCXO }, 269 }; 270 271 static const struct parent_map gcc_parent_map_8[] = { 272 { P_BI_TCXO, 0 }, 273 { P_GCC_GPLL0_OUT_MAIN, 1 }, 274 { P_GCC_GPLL7_OUT_MAIN, 2 }, 275 { P_GCC_GPLL0_OUT_EVEN, 6 }, 276 }; 277 278 static const struct clk_parent_data gcc_parent_data_8[] = { 279 { .index = DT_BI_TCXO }, 280 { .hw = &gcc_gpll0.clkr.hw }, 281 { .hw = &gcc_gpll7.clkr.hw }, 282 { .hw = &gcc_gpll0_out_even.clkr.hw }, 283 }; 284 285 static const struct parent_map gcc_parent_map_9[] = { 286 { P_BI_TCXO, 0 }, 287 { P_GCC_GPLL0_OUT_MAIN, 1 }, 288 { P_GCC_GPLL6_OUT_MAIN, 2 }, 289 { P_GCC_GPLL0_OUT_ODD, 3 }, 290 { P_GCC_GPLL2_OUT_MAIN, 4 }, 291 { P_GCC_GPLL0_OUT_EVEN, 6 }, 292 }; 293 294 static const struct clk_parent_data gcc_parent_data_9[] = { 295 { .index = DT_BI_TCXO }, 296 { .hw = &gcc_gpll0.clkr.hw }, 297 { .hw = &gcc_gpll6.clkr.hw }, 298 { .hw = &gcc_gpll0.clkr.hw }, 299 { .hw = &gcc_gpll2.clkr.hw }, 300 { .hw = &gcc_gpll0_out_even.clkr.hw }, 301 }; 302 303 static const struct parent_map gcc_parent_map_10[] = { 304 { P_BI_TCXO, 0 }, 305 { P_GCC_GPLL0_OUT_MAIN, 1 }, 306 { P_GCC_GPLL6_OUT_MAIN, 2 }, 307 { P_GCC_GPLL0_OUT_ODD, 3 }, 308 { P_GCC_GPLL0_OUT_EVEN, 6 }, 309 }; 310 311 static const struct clk_parent_data gcc_parent_data_10[] = { 312 { .index = DT_BI_TCXO }, 313 { .hw = &gcc_gpll0.clkr.hw }, 314 { .hw = &gcc_gpll6.clkr.hw }, 315 { .hw = &gcc_gpll0.clkr.hw }, 316 { .hw = &gcc_gpll0_out_even.clkr.hw }, 317 }; 318 319 static const struct parent_map gcc_parent_map_11[] = { 320 { P_BI_TCXO, 0 }, 321 { P_GCC_GPLL0_OUT_MAIN, 1 }, 322 { P_GCC_GPLL9_OUT_MAIN, 2 }, 323 { P_GCC_GPLL4_OUT_MAIN, 5 }, 324 { P_GCC_GPLL0_OUT_EVEN, 6 }, 325 }; 326 327 static const struct clk_parent_data gcc_parent_data_11[] = { 328 { .index = DT_BI_TCXO }, 329 { .hw = &gcc_gpll0.clkr.hw }, 330 { .hw = &gcc_gpll9.clkr.hw }, 331 { .hw = &gcc_gpll4.clkr.hw }, 332 { .hw = &gcc_gpll0_out_even.clkr.hw }, 333 }; 334 335 static const struct parent_map gcc_parent_map_12[] = { 336 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 }, 337 { P_BI_TCXO, 2 }, 338 }; 339 340 static const struct clk_parent_data gcc_parent_data_12[] = { 341 { .index = DT_UFS_PHY_RX_SYMBOL_0 }, 342 { .index = DT_BI_TCXO }, 343 }; 344 345 static const struct parent_map gcc_parent_map_13[] = { 346 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 }, 347 { P_BI_TCXO, 2 }, 348 }; 349 350 static const struct clk_parent_data gcc_parent_data_13[] = { 351 { .index = DT_UFS_PHY_RX_SYMBOL_1 }, 352 { .index = DT_BI_TCXO }, 353 }; 354 355 static const struct parent_map gcc_parent_map_14[] = { 356 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 }, 357 { P_BI_TCXO, 2 }, 358 }; 359 360 static const struct clk_parent_data gcc_parent_data_14[] = { 361 { .index = DT_UFS_PHY_TX_SYMBOL_0 }, 362 { .index = DT_BI_TCXO }, 363 }; 364 365 static const struct parent_map gcc_parent_map_15[] = { 366 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 367 { P_BI_TCXO, 2 }, 368 }; 369 370 static const struct clk_parent_data gcc_parent_data_15[] = { 371 { .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE }, 372 { .index = DT_BI_TCXO }, 373 }; 374 375 static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { 376 .reg = 0x6b070, 377 .shift = 0, 378 .width = 2, 379 .parent_map = gcc_parent_map_6, 380 .clkr = { 381 .hw.init = &(const struct clk_init_data) { 382 .name = "gcc_pcie_0_pipe_clk_src", 383 .parent_data = gcc_parent_data_6, 384 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 385 .ops = &clk_regmap_mux_closest_ops, 386 }, 387 }, 388 }; 389 390 static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { 391 .reg = 0x9006c, 392 .shift = 0, 393 .width = 2, 394 .parent_map = gcc_parent_map_7, 395 .clkr = { 396 .hw.init = &(const struct clk_init_data) { 397 .name = "gcc_pcie_1_pipe_clk_src", 398 .parent_data = gcc_parent_data_7, 399 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 400 .ops = &clk_regmap_mux_closest_ops, 401 }, 402 }, 403 }; 404 405 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = { 406 .reg = 0x77064, 407 .shift = 0, 408 .width = 2, 409 .parent_map = gcc_parent_map_12, 410 .clkr = { 411 .hw.init = &(const struct clk_init_data) { 412 .name = "gcc_ufs_phy_rx_symbol_0_clk_src", 413 .parent_data = gcc_parent_data_12, 414 .num_parents = ARRAY_SIZE(gcc_parent_data_12), 415 .ops = &clk_regmap_mux_closest_ops, 416 }, 417 }, 418 }; 419 420 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = { 421 .reg = 0x770e0, 422 .shift = 0, 423 .width = 2, 424 .parent_map = gcc_parent_map_13, 425 .clkr = { 426 .hw.init = &(const struct clk_init_data) { 427 .name = "gcc_ufs_phy_rx_symbol_1_clk_src", 428 .parent_data = gcc_parent_data_13, 429 .num_parents = ARRAY_SIZE(gcc_parent_data_13), 430 .ops = &clk_regmap_mux_closest_ops, 431 }, 432 }, 433 }; 434 435 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = { 436 .reg = 0x77054, 437 .shift = 0, 438 .width = 2, 439 .parent_map = gcc_parent_map_14, 440 .clkr = { 441 .hw.init = &(const struct clk_init_data) { 442 .name = "gcc_ufs_phy_tx_symbol_0_clk_src", 443 .parent_data = gcc_parent_data_14, 444 .num_parents = ARRAY_SIZE(gcc_parent_data_14), 445 .ops = &clk_regmap_mux_closest_ops, 446 }, 447 }, 448 }; 449 450 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 451 .reg = 0x3906c, 452 .shift = 0, 453 .width = 2, 454 .parent_map = gcc_parent_map_15, 455 .clkr = { 456 .hw.init = &(const struct clk_init_data) { 457 .name = "gcc_usb3_prim_phy_pipe_clk_src", 458 .parent_data = gcc_parent_data_15, 459 .num_parents = ARRAY_SIZE(gcc_parent_data_15), 460 .ops = &clk_regmap_mux_closest_ops, 461 }, 462 }, 463 }; 464 465 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 466 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 467 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 468 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 469 { } 470 }; 471 472 static struct clk_rcg2 gcc_gp1_clk_src = { 473 .cmd_rcgr = 0x64004, 474 .mnd_width = 16, 475 .hid_width = 5, 476 .parent_map = gcc_parent_map_1, 477 .freq_tbl = ftbl_gcc_gp1_clk_src, 478 .clkr.hw.init = &(const struct clk_init_data) { 479 .name = "gcc_gp1_clk_src", 480 .parent_data = gcc_parent_data_1, 481 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 482 .ops = &clk_rcg2_shared_ops, 483 }, 484 }; 485 486 static struct clk_rcg2 gcc_gp2_clk_src = { 487 .cmd_rcgr = 0x65004, 488 .mnd_width = 16, 489 .hid_width = 5, 490 .parent_map = gcc_parent_map_1, 491 .freq_tbl = ftbl_gcc_gp1_clk_src, 492 .clkr.hw.init = &(const struct clk_init_data) { 493 .name = "gcc_gp2_clk_src", 494 .parent_data = gcc_parent_data_1, 495 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 496 .ops = &clk_rcg2_shared_ops, 497 }, 498 }; 499 500 static struct clk_rcg2 gcc_gp3_clk_src = { 501 .cmd_rcgr = 0x66004, 502 .mnd_width = 16, 503 .hid_width = 5, 504 .parent_map = gcc_parent_map_1, 505 .freq_tbl = ftbl_gcc_gp1_clk_src, 506 .clkr.hw.init = &(const struct clk_init_data) { 507 .name = "gcc_gp3_clk_src", 508 .parent_data = gcc_parent_data_1, 509 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 510 .ops = &clk_rcg2_shared_ops, 511 }, 512 }; 513 514 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 515 F(19200000, P_BI_TCXO, 1, 0, 0), 516 { } 517 }; 518 519 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 520 .cmd_rcgr = 0x6b074, 521 .mnd_width = 16, 522 .hid_width = 5, 523 .parent_map = gcc_parent_map_3, 524 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 525 .clkr.hw.init = &(const struct clk_init_data) { 526 .name = "gcc_pcie_0_aux_clk_src", 527 .parent_data = gcc_parent_data_3, 528 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 529 .ops = &clk_rcg2_shared_ops, 530 }, 531 }; 532 533 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 534 F(19200000, P_BI_TCXO, 1, 0, 0), 535 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 536 { } 537 }; 538 539 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 540 .cmd_rcgr = 0x6b058, 541 .mnd_width = 0, 542 .hid_width = 5, 543 .parent_map = gcc_parent_map_0, 544 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 545 .clkr.hw.init = &(const struct clk_init_data) { 546 .name = "gcc_pcie_0_phy_rchng_clk_src", 547 .parent_data = gcc_parent_data_0, 548 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 549 .ops = &clk_rcg2_shared_ops, 550 }, 551 }; 552 553 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 554 .cmd_rcgr = 0x90070, 555 .mnd_width = 16, 556 .hid_width = 5, 557 .parent_map = gcc_parent_map_3, 558 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 559 .clkr.hw.init = &(const struct clk_init_data) { 560 .name = "gcc_pcie_1_aux_clk_src", 561 .parent_data = gcc_parent_data_3, 562 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 563 .ops = &clk_rcg2_shared_ops, 564 }, 565 }; 566 567 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { 568 .cmd_rcgr = 0x90054, 569 .mnd_width = 0, 570 .hid_width = 5, 571 .parent_map = gcc_parent_map_0, 572 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 573 .clkr.hw.init = &(const struct clk_init_data) { 574 .name = "gcc_pcie_1_phy_rchng_clk_src", 575 .parent_data = gcc_parent_data_0, 576 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 577 .ops = &clk_rcg2_shared_ops, 578 }, 579 }; 580 581 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 582 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 583 { } 584 }; 585 586 static struct clk_rcg2 gcc_pdm2_clk_src = { 587 .cmd_rcgr = 0x33010, 588 .mnd_width = 0, 589 .hid_width = 5, 590 .parent_map = gcc_parent_map_0, 591 .freq_tbl = ftbl_gcc_pdm2_clk_src, 592 .clkr.hw.init = &(const struct clk_init_data) { 593 .name = "gcc_pdm2_clk_src", 594 .parent_data = gcc_parent_data_0, 595 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 596 .ops = &clk_rcg2_shared_ops, 597 }, 598 }; 599 600 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_qspi_ref_clk_src[] = { 601 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 602 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 603 F(19200000, P_BI_TCXO, 1, 0, 0), 604 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 605 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 606 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 607 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 608 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 609 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 610 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 611 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 612 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 613 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 614 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 615 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 616 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 617 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 618 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 619 { } 620 }; 621 622 static struct clk_init_data gcc_qupv3_wrap0_qspi_ref_clk_src_init = { 623 .name = "gcc_qupv3_wrap0_qspi_ref_clk_src", 624 .parent_data = gcc_parent_data_0, 625 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 626 .ops = &clk_rcg2_ops, 627 }; 628 629 static struct clk_rcg2 gcc_qupv3_wrap0_qspi_ref_clk_src = { 630 .cmd_rcgr = 0x18768, 631 .mnd_width = 16, 632 .hid_width = 5, 633 .parent_map = gcc_parent_map_0, 634 .freq_tbl = ftbl_gcc_qupv3_wrap0_qspi_ref_clk_src, 635 .clkr.hw.init = &gcc_qupv3_wrap0_qspi_ref_clk_src_init, 636 }; 637 638 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 639 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 640 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 641 F(19200000, P_BI_TCXO, 1, 0, 0), 642 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 643 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 644 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 645 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 646 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 647 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 648 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 649 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 650 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 651 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 652 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 653 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 654 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 655 { } 656 }; 657 658 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 659 .name = "gcc_qupv3_wrap0_s0_clk_src", 660 .parent_data = gcc_parent_data_0, 661 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 662 .ops = &clk_rcg2_ops, 663 }; 664 665 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 666 .cmd_rcgr = 0x18010, 667 .mnd_width = 16, 668 .hid_width = 5, 669 .parent_map = gcc_parent_map_0, 670 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 671 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 672 }; 673 674 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 675 .name = "gcc_qupv3_wrap0_s1_clk_src", 676 .parent_data = gcc_parent_data_0, 677 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 678 .ops = &clk_rcg2_ops, 679 }; 680 681 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 682 .cmd_rcgr = 0x18148, 683 .mnd_width = 16, 684 .hid_width = 5, 685 .parent_map = gcc_parent_map_0, 686 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 687 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 688 }; 689 690 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s3_clk_src[] = { 691 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 692 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 693 F(19200000, P_BI_TCXO, 1, 0, 0), 694 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 695 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 696 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 697 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 698 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 699 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 700 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 701 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 702 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 703 { } 704 }; 705 706 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 707 .name = "gcc_qupv3_wrap0_s3_clk_src", 708 .parent_data = gcc_parent_data_0, 709 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 710 .ops = &clk_rcg2_ops, 711 }; 712 713 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 714 .cmd_rcgr = 0x18290, 715 .mnd_width = 16, 716 .hid_width = 5, 717 .parent_map = gcc_parent_map_0, 718 .freq_tbl = ftbl_gcc_qupv3_wrap0_s3_clk_src, 719 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 720 }; 721 722 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s4_clk_src[] = { 723 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 724 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 725 F(19200000, P_BI_TCXO, 1, 0, 0), 726 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 727 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 728 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 729 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 730 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 731 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 732 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 733 F(128000000, P_GCC_GPLL6_OUT_MAIN, 3, 0, 0), 734 { } 735 }; 736 737 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 738 .name = "gcc_qupv3_wrap0_s4_clk_src", 739 .parent_data = gcc_parent_data_4, 740 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 741 .ops = &clk_rcg2_ops, 742 }; 743 744 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 745 .cmd_rcgr = 0x183c8, 746 .mnd_width = 16, 747 .hid_width = 5, 748 .parent_map = gcc_parent_map_4, 749 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 750 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 751 }; 752 753 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 754 .name = "gcc_qupv3_wrap0_s5_clk_src", 755 .parent_data = gcc_parent_data_0, 756 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 757 .ops = &clk_rcg2_ops, 758 }; 759 760 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 761 .cmd_rcgr = 0x18500, 762 .mnd_width = 16, 763 .hid_width = 5, 764 .parent_map = gcc_parent_map_0, 765 .freq_tbl = ftbl_gcc_qupv3_wrap0_s3_clk_src, 766 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 767 }; 768 769 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 770 .name = "gcc_qupv3_wrap0_s6_clk_src", 771 .parent_data = gcc_parent_data_0, 772 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 773 .ops = &clk_rcg2_ops, 774 }; 775 776 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 777 .cmd_rcgr = 0x18638, 778 .mnd_width = 16, 779 .hid_width = 5, 780 .parent_map = gcc_parent_map_0, 781 .freq_tbl = ftbl_gcc_qupv3_wrap0_s3_clk_src, 782 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 783 }; 784 785 static struct clk_init_data gcc_qupv3_wrap1_qspi_ref_clk_src_init = { 786 .name = "gcc_qupv3_wrap1_qspi_ref_clk_src", 787 .parent_data = gcc_parent_data_0, 788 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 789 .ops = &clk_rcg2_ops, 790 }; 791 792 static struct clk_rcg2 gcc_qupv3_wrap1_qspi_ref_clk_src = { 793 .cmd_rcgr = 0x1e768, 794 .mnd_width = 16, 795 .hid_width = 5, 796 .parent_map = gcc_parent_map_0, 797 .freq_tbl = ftbl_gcc_qupv3_wrap0_qspi_ref_clk_src, 798 .clkr.hw.init = &gcc_qupv3_wrap1_qspi_ref_clk_src_init, 799 }; 800 801 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 802 .name = "gcc_qupv3_wrap1_s0_clk_src", 803 .parent_data = gcc_parent_data_0, 804 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 805 .ops = &clk_rcg2_ops, 806 }; 807 808 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 809 .cmd_rcgr = 0x1e010, 810 .mnd_width = 16, 811 .hid_width = 5, 812 .parent_map = gcc_parent_map_0, 813 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 814 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 815 }; 816 817 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 818 .name = "gcc_qupv3_wrap1_s1_clk_src", 819 .parent_data = gcc_parent_data_0, 820 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 821 .ops = &clk_rcg2_ops, 822 }; 823 824 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 825 .cmd_rcgr = 0x1e148, 826 .mnd_width = 16, 827 .hid_width = 5, 828 .parent_map = gcc_parent_map_0, 829 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 830 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 831 }; 832 833 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 834 .name = "gcc_qupv3_wrap1_s3_clk_src", 835 .parent_data = gcc_parent_data_0, 836 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 837 .ops = &clk_rcg2_ops, 838 }; 839 840 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 841 .cmd_rcgr = 0x1e290, 842 .mnd_width = 16, 843 .hid_width = 5, 844 .parent_map = gcc_parent_map_0, 845 .freq_tbl = ftbl_gcc_qupv3_wrap0_s3_clk_src, 846 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 847 }; 848 849 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 850 .name = "gcc_qupv3_wrap1_s4_clk_src", 851 .parent_data = gcc_parent_data_4, 852 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 853 .ops = &clk_rcg2_ops, 854 }; 855 856 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 857 .cmd_rcgr = 0x1e3c8, 858 .mnd_width = 16, 859 .hid_width = 5, 860 .parent_map = gcc_parent_map_4, 861 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 862 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 863 }; 864 865 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 866 .name = "gcc_qupv3_wrap1_s5_clk_src", 867 .parent_data = gcc_parent_data_0, 868 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 869 .ops = &clk_rcg2_ops, 870 }; 871 872 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 873 .cmd_rcgr = 0x1e500, 874 .mnd_width = 16, 875 .hid_width = 5, 876 .parent_map = gcc_parent_map_0, 877 .freq_tbl = ftbl_gcc_qupv3_wrap0_s3_clk_src, 878 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 879 }; 880 881 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 882 .name = "gcc_qupv3_wrap1_s6_clk_src", 883 .parent_data = gcc_parent_data_8, 884 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 885 .ops = &clk_rcg2_ops, 886 }; 887 888 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 889 .cmd_rcgr = 0x1e638, 890 .mnd_width = 16, 891 .hid_width = 5, 892 .parent_map = gcc_parent_map_8, 893 .freq_tbl = ftbl_gcc_qupv3_wrap0_s3_clk_src, 894 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 895 }; 896 897 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 898 F(144000, P_BI_TCXO, 16, 3, 25), 899 F(400000, P_BI_TCXO, 12, 1, 4), 900 F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3), 901 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 902 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 903 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 904 F(192000000, P_GCC_GPLL6_OUT_MAIN, 2, 0, 0), 905 F(384000000, P_GCC_GPLL6_OUT_MAIN, 1, 0, 0), 906 { } 907 }; 908 909 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 910 .cmd_rcgr = 0xa3014, 911 .mnd_width = 8, 912 .hid_width = 5, 913 .parent_map = gcc_parent_map_9, 914 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 915 .clkr.hw.init = &(const struct clk_init_data) { 916 .name = "gcc_sdcc1_apps_clk_src", 917 .parent_data = gcc_parent_data_9, 918 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 919 .ops = &clk_rcg2_shared_floor_ops, 920 }, 921 }; 922 923 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 924 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 925 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 926 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0), 927 { } 928 }; 929 930 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 931 .cmd_rcgr = 0xa3038, 932 .mnd_width = 0, 933 .hid_width = 5, 934 .parent_map = gcc_parent_map_10, 935 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 936 .clkr.hw.init = &(const struct clk_init_data) { 937 .name = "gcc_sdcc1_ice_core_clk_src", 938 .parent_data = gcc_parent_data_10, 939 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 940 .ops = &clk_rcg2_shared_floor_ops, 941 }, 942 }; 943 944 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 945 F(400000, P_BI_TCXO, 12, 1, 4), 946 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 947 F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0), 948 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 949 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 950 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), 951 { } 952 }; 953 954 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 955 .cmd_rcgr = 0x14018, 956 .mnd_width = 8, 957 .hid_width = 5, 958 .parent_map = gcc_parent_map_11, 959 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 960 .clkr.hw.init = &(const struct clk_init_data) { 961 .name = "gcc_sdcc2_apps_clk_src", 962 .parent_data = gcc_parent_data_11, 963 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 964 .ops = &clk_rcg2_shared_floor_ops, 965 }, 966 }; 967 968 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 969 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 970 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 971 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 972 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 973 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 974 { } 975 }; 976 977 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 978 .cmd_rcgr = 0x77030, 979 .mnd_width = 8, 980 .hid_width = 5, 981 .parent_map = gcc_parent_map_2, 982 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 983 .clkr.hw.init = &(const struct clk_init_data) { 984 .name = "gcc_ufs_phy_axi_clk_src", 985 .parent_data = gcc_parent_data_2, 986 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 987 .ops = &clk_rcg2_shared_ops, 988 }, 989 }; 990 991 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 992 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 993 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), 994 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 995 { } 996 }; 997 998 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 999 .cmd_rcgr = 0x77080, 1000 .mnd_width = 0, 1001 .hid_width = 5, 1002 .parent_map = gcc_parent_map_2, 1003 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1004 .clkr.hw.init = &(const struct clk_init_data) { 1005 .name = "gcc_ufs_phy_ice_core_clk_src", 1006 .parent_data = gcc_parent_data_2, 1007 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1008 .ops = &clk_rcg2_shared_ops, 1009 }, 1010 }; 1011 1012 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 1013 F(9600000, P_BI_TCXO, 2, 0, 0), 1014 F(19200000, P_BI_TCXO, 1, 0, 0), 1015 { } 1016 }; 1017 1018 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1019 .cmd_rcgr = 0x770b4, 1020 .mnd_width = 0, 1021 .hid_width = 5, 1022 .parent_map = gcc_parent_map_5, 1023 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 1024 .clkr.hw.init = &(const struct clk_init_data) { 1025 .name = "gcc_ufs_phy_phy_aux_clk_src", 1026 .parent_data = gcc_parent_data_5, 1027 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1028 .ops = &clk_rcg2_shared_ops, 1029 }, 1030 }; 1031 1032 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { 1033 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1034 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), 1035 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), 1036 { } 1037 }; 1038 1039 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1040 .cmd_rcgr = 0x77098, 1041 .mnd_width = 0, 1042 .hid_width = 5, 1043 .parent_map = gcc_parent_map_2, 1044 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, 1045 .clkr.hw.init = &(const struct clk_init_data) { 1046 .name = "gcc_ufs_phy_unipro_core_clk_src", 1047 .parent_data = gcc_parent_data_2, 1048 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1049 .ops = &clk_rcg2_shared_ops, 1050 }, 1051 }; 1052 1053 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1054 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), 1055 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 1056 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1057 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 1058 { } 1059 }; 1060 1061 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1062 .cmd_rcgr = 0x3902c, 1063 .mnd_width = 8, 1064 .hid_width = 5, 1065 .parent_map = gcc_parent_map_0, 1066 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1067 .clkr.hw.init = &(const struct clk_init_data) { 1068 .name = "gcc_usb30_prim_master_clk_src", 1069 .parent_data = gcc_parent_data_0, 1070 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1071 .ops = &clk_rcg2_shared_ops, 1072 }, 1073 }; 1074 1075 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1076 .cmd_rcgr = 0x39044, 1077 .mnd_width = 0, 1078 .hid_width = 5, 1079 .parent_map = gcc_parent_map_0, 1080 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1081 .clkr.hw.init = &(const struct clk_init_data) { 1082 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1083 .parent_data = gcc_parent_data_0, 1084 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1085 .ops = &clk_rcg2_shared_ops, 1086 }, 1087 }; 1088 1089 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1090 .cmd_rcgr = 0x39070, 1091 .mnd_width = 0, 1092 .hid_width = 5, 1093 .parent_map = gcc_parent_map_3, 1094 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1095 .clkr.hw.init = &(const struct clk_init_data) { 1096 .name = "gcc_usb3_prim_phy_aux_clk_src", 1097 .parent_data = gcc_parent_data_3, 1098 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1099 .ops = &clk_rcg2_shared_ops, 1100 }, 1101 }; 1102 1103 static struct clk_regmap_div gcc_pcie_0_pipe_div2_clk_src = { 1104 .reg = 0x6b094, 1105 .shift = 0, 1106 .width = 4, 1107 .clkr.hw.init = &(const struct clk_init_data) { 1108 .name = "gcc_pcie_0_pipe_div2_clk_src", 1109 .parent_hws = (const struct clk_hw*[]) { 1110 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1111 }, 1112 .num_parents = 1, 1113 .flags = CLK_SET_RATE_PARENT, 1114 .ops = &clk_regmap_div_ro_ops, 1115 }, 1116 }; 1117 1118 static struct clk_regmap_div gcc_pcie_1_pipe_div2_clk_src = { 1119 .reg = 0x90090, 1120 .shift = 0, 1121 .width = 4, 1122 .clkr.hw.init = &(const struct clk_init_data) { 1123 .name = "gcc_pcie_1_pipe_div2_clk_src", 1124 .parent_hws = (const struct clk_hw*[]) { 1125 &gcc_pcie_1_pipe_clk_src.clkr.hw, 1126 }, 1127 .num_parents = 1, 1128 .flags = CLK_SET_RATE_PARENT, 1129 .ops = &clk_regmap_div_ro_ops, 1130 }, 1131 }; 1132 1133 static struct clk_regmap_div gcc_qupv3_wrap0_s2_clk_src = { 1134 .reg = 0x18280, 1135 .shift = 0, 1136 .width = 4, 1137 .clkr.hw.init = &(const struct clk_init_data) { 1138 .name = "gcc_qupv3_wrap0_s2_clk_src", 1139 .parent_hws = (const struct clk_hw*[]) { 1140 &gcc_qupv3_wrap0_qspi_ref_clk_src.clkr.hw, 1141 }, 1142 .num_parents = 1, 1143 .flags = CLK_SET_RATE_PARENT, 1144 .ops = &clk_regmap_div_ro_ops, 1145 }, 1146 }; 1147 1148 static struct clk_regmap_div gcc_qupv3_wrap1_s2_clk_src = { 1149 .reg = 0x1e280, 1150 .shift = 0, 1151 .width = 4, 1152 .clkr.hw.init = &(const struct clk_init_data) { 1153 .name = "gcc_qupv3_wrap1_s2_clk_src", 1154 .parent_hws = (const struct clk_hw*[]) { 1155 &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw, 1156 }, 1157 .num_parents = 1, 1158 .flags = CLK_SET_RATE_PARENT, 1159 .ops = &clk_regmap_div_ro_ops, 1160 }, 1161 }; 1162 1163 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1164 .reg = 0x3905c, 1165 .shift = 0, 1166 .width = 4, 1167 .clkr.hw.init = &(const struct clk_init_data) { 1168 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1169 .parent_hws = (const struct clk_hw*[]) { 1170 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1171 }, 1172 .num_parents = 1, 1173 .flags = CLK_SET_RATE_PARENT, 1174 .ops = &clk_regmap_div_ro_ops, 1175 }, 1176 }; 1177 1178 static struct clk_branch gcc_aggre_noc_pcie_axi_clk = { 1179 .halt_reg = 0x1005c, 1180 .halt_check = BRANCH_HALT_SKIP, 1181 .hwcg_reg = 0x1005c, 1182 .hwcg_bit = 1, 1183 .clkr = { 1184 .enable_reg = 0x52000, 1185 .enable_mask = BIT(12), 1186 .hw.init = &(const struct clk_init_data) { 1187 .name = "gcc_aggre_noc_pcie_axi_clk", 1188 .ops = &clk_branch2_ops, 1189 }, 1190 }, 1191 }; 1192 1193 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1194 .halt_reg = 0x770e4, 1195 .halt_check = BRANCH_HALT_VOTED, 1196 .hwcg_reg = 0x770e4, 1197 .hwcg_bit = 1, 1198 .clkr = { 1199 .enable_reg = 0x770e4, 1200 .enable_mask = BIT(0), 1201 .hw.init = &(const struct clk_init_data) { 1202 .name = "gcc_aggre_ufs_phy_axi_clk", 1203 .parent_hws = (const struct clk_hw*[]) { 1204 &gcc_ufs_phy_axi_clk_src.clkr.hw, 1205 }, 1206 .num_parents = 1, 1207 .flags = CLK_SET_RATE_PARENT, 1208 .ops = &clk_branch2_ops, 1209 }, 1210 }, 1211 }; 1212 1213 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { 1214 .halt_reg = 0x770e4, 1215 .halt_check = BRANCH_HALT_VOTED, 1216 .hwcg_reg = 0x770e4, 1217 .hwcg_bit = 1, 1218 .clkr = { 1219 .enable_reg = 0x770e4, 1220 .enable_mask = BIT(1), 1221 .hw.init = &(const struct clk_init_data) { 1222 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", 1223 .parent_hws = (const struct clk_hw*[]) { 1224 &gcc_ufs_phy_axi_clk_src.clkr.hw, 1225 }, 1226 .num_parents = 1, 1227 .flags = CLK_SET_RATE_PARENT, 1228 .ops = &clk_branch2_ops, 1229 }, 1230 }, 1231 }; 1232 1233 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1234 .halt_reg = 0x39090, 1235 .halt_check = BRANCH_HALT_VOTED, 1236 .hwcg_reg = 0x39090, 1237 .hwcg_bit = 1, 1238 .clkr = { 1239 .enable_reg = 0x39090, 1240 .enable_mask = BIT(0), 1241 .hw.init = &(const struct clk_init_data) { 1242 .name = "gcc_aggre_usb3_prim_axi_clk", 1243 .parent_hws = (const struct clk_hw*[]) { 1244 &gcc_usb30_prim_master_clk_src.clkr.hw, 1245 }, 1246 .num_parents = 1, 1247 .flags = CLK_SET_RATE_PARENT, 1248 .ops = &clk_branch2_ops, 1249 }, 1250 }, 1251 }; 1252 1253 static struct clk_branch gcc_boot_rom_ahb_clk = { 1254 .halt_reg = 0x38004, 1255 .halt_check = BRANCH_HALT_VOTED, 1256 .hwcg_reg = 0x38004, 1257 .hwcg_bit = 1, 1258 .clkr = { 1259 .enable_reg = 0x52000, 1260 .enable_mask = BIT(10), 1261 .hw.init = &(const struct clk_init_data) { 1262 .name = "gcc_boot_rom_ahb_clk", 1263 .ops = &clk_branch2_ops, 1264 }, 1265 }, 1266 }; 1267 1268 static struct clk_branch gcc_camera_hf_axi_clk = { 1269 .halt_reg = 0x26010, 1270 .halt_check = BRANCH_HALT_SKIP, 1271 .hwcg_reg = 0x26010, 1272 .hwcg_bit = 1, 1273 .clkr = { 1274 .enable_reg = 0x26010, 1275 .enable_mask = BIT(0), 1276 .hw.init = &(const struct clk_init_data) { 1277 .name = "gcc_camera_hf_axi_clk", 1278 .ops = &clk_branch2_ops, 1279 }, 1280 }, 1281 }; 1282 1283 static struct clk_branch gcc_camera_sf_axi_clk = { 1284 .halt_reg = 0x26014, 1285 .halt_check = BRANCH_HALT_SKIP, 1286 .hwcg_reg = 0x26014, 1287 .hwcg_bit = 1, 1288 .clkr = { 1289 .enable_reg = 0x26014, 1290 .enable_mask = BIT(0), 1291 .hw.init = &(const struct clk_init_data) { 1292 .name = "gcc_camera_sf_axi_clk", 1293 .ops = &clk_branch2_ops, 1294 }, 1295 }, 1296 }; 1297 1298 static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = { 1299 .halt_reg = 0x10050, 1300 .halt_check = BRANCH_HALT_SKIP, 1301 .hwcg_reg = 0x10050, 1302 .hwcg_bit = 1, 1303 .clkr = { 1304 .enable_reg = 0x52000, 1305 .enable_mask = BIT(20), 1306 .hw.init = &(const struct clk_init_data) { 1307 .name = "gcc_cfg_noc_pcie_anoc_ahb_clk", 1308 .ops = &clk_branch2_ops, 1309 }, 1310 }, 1311 }; 1312 1313 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1314 .halt_reg = 0x3908c, 1315 .halt_check = BRANCH_HALT_VOTED, 1316 .clkr = { 1317 .enable_reg = 0x3908c, 1318 .enable_mask = BIT(0), 1319 .hw.init = &(const struct clk_init_data) { 1320 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1321 .parent_hws = (const struct clk_hw*[]) { 1322 &gcc_usb30_prim_master_clk_src.clkr.hw, 1323 }, 1324 .num_parents = 1, 1325 .flags = CLK_SET_RATE_PARENT, 1326 .ops = &clk_branch2_ops, 1327 }, 1328 }, 1329 }; 1330 1331 static struct clk_branch gcc_cnoc_pcie_sf_axi_clk = { 1332 .halt_reg = 0x10058, 1333 .halt_check = BRANCH_HALT_VOTED, 1334 .hwcg_reg = 0x10058, 1335 .hwcg_bit = 1, 1336 .clkr = { 1337 .enable_reg = 0x52008, 1338 .enable_mask = BIT(6), 1339 .hw.init = &(const struct clk_init_data) { 1340 .name = "gcc_cnoc_pcie_sf_axi_clk", 1341 .ops = &clk_branch2_ops, 1342 }, 1343 }, 1344 }; 1345 1346 static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1347 .halt_reg = 0x7115c, 1348 .halt_check = BRANCH_HALT_SKIP, 1349 .hwcg_reg = 0x7115c, 1350 .hwcg_bit = 1, 1351 .clkr = { 1352 .enable_reg = 0x7115c, 1353 .enable_mask = BIT(0), 1354 .hw.init = &(const struct clk_init_data) { 1355 .name = "gcc_ddrss_gpu_axi_clk", 1356 .ops = &clk_branch2_aon_ops, 1357 }, 1358 }, 1359 }; 1360 1361 static struct clk_branch gcc_ddrss_pcie_sf_qtb_clk = { 1362 .halt_reg = 0x1006c, 1363 .halt_check = BRANCH_HALT_SKIP, 1364 .hwcg_reg = 0x1006c, 1365 .hwcg_bit = 1, 1366 .clkr = { 1367 .enable_reg = 0x52000, 1368 .enable_mask = BIT(19), 1369 .hw.init = &(const struct clk_init_data) { 1370 .name = "gcc_ddrss_pcie_sf_qtb_clk", 1371 .ops = &clk_branch2_ops, 1372 }, 1373 }, 1374 }; 1375 1376 static struct clk_branch gcc_disp_gpll0_div_clk_src = { 1377 .halt_check = BRANCH_HALT_DELAY, 1378 .clkr = { 1379 .enable_reg = 0x52000, 1380 .enable_mask = BIT(23), 1381 .hw.init = &(const struct clk_init_data) { 1382 .name = "gcc_disp_gpll0_div_clk_src", 1383 .parent_hws = (const struct clk_hw*[]) { 1384 &gcc_gpll0_out_even.clkr.hw, 1385 }, 1386 .num_parents = 1, 1387 .flags = CLK_SET_RATE_PARENT, 1388 .ops = &clk_branch2_ops, 1389 }, 1390 }, 1391 }; 1392 1393 static struct clk_branch gcc_disp_hf_axi_clk = { 1394 .halt_reg = 0x2700c, 1395 .halt_check = BRANCH_HALT_SKIP, 1396 .hwcg_reg = 0x2700c, 1397 .hwcg_bit = 1, 1398 .clkr = { 1399 .enable_reg = 0x2700c, 1400 .enable_mask = BIT(0), 1401 .hw.init = &(const struct clk_init_data) { 1402 .name = "gcc_disp_hf_axi_clk", 1403 .ops = &clk_branch2_ops, 1404 }, 1405 }, 1406 }; 1407 1408 static struct clk_branch gcc_gp1_clk = { 1409 .halt_reg = 0x64000, 1410 .halt_check = BRANCH_HALT, 1411 .clkr = { 1412 .enable_reg = 0x64000, 1413 .enable_mask = BIT(0), 1414 .hw.init = &(const struct clk_init_data) { 1415 .name = "gcc_gp1_clk", 1416 .parent_hws = (const struct clk_hw*[]) { 1417 &gcc_gp1_clk_src.clkr.hw, 1418 }, 1419 .num_parents = 1, 1420 .flags = CLK_SET_RATE_PARENT, 1421 .ops = &clk_branch2_ops, 1422 }, 1423 }, 1424 }; 1425 1426 static struct clk_branch gcc_gp2_clk = { 1427 .halt_reg = 0x65000, 1428 .halt_check = BRANCH_HALT, 1429 .clkr = { 1430 .enable_reg = 0x65000, 1431 .enable_mask = BIT(0), 1432 .hw.init = &(const struct clk_init_data) { 1433 .name = "gcc_gp2_clk", 1434 .parent_hws = (const struct clk_hw*[]) { 1435 &gcc_gp2_clk_src.clkr.hw, 1436 }, 1437 .num_parents = 1, 1438 .flags = CLK_SET_RATE_PARENT, 1439 .ops = &clk_branch2_ops, 1440 }, 1441 }, 1442 }; 1443 1444 static struct clk_branch gcc_gp3_clk = { 1445 .halt_reg = 0x66000, 1446 .halt_check = BRANCH_HALT, 1447 .clkr = { 1448 .enable_reg = 0x66000, 1449 .enable_mask = BIT(0), 1450 .hw.init = &(const struct clk_init_data) { 1451 .name = "gcc_gp3_clk", 1452 .parent_hws = (const struct clk_hw*[]) { 1453 &gcc_gp3_clk_src.clkr.hw, 1454 }, 1455 .num_parents = 1, 1456 .flags = CLK_SET_RATE_PARENT, 1457 .ops = &clk_branch2_ops, 1458 }, 1459 }, 1460 }; 1461 1462 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1463 .halt_check = BRANCH_HALT_DELAY, 1464 .clkr = { 1465 .enable_reg = 0x52000, 1466 .enable_mask = BIT(15), 1467 .hw.init = &(const struct clk_init_data) { 1468 .name = "gcc_gpu_gpll0_clk_src", 1469 .parent_hws = (const struct clk_hw*[]) { 1470 &gcc_gpll0.clkr.hw, 1471 }, 1472 .num_parents = 1, 1473 .flags = CLK_SET_RATE_PARENT, 1474 .ops = &clk_branch2_ops, 1475 }, 1476 }, 1477 }; 1478 1479 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1480 .halt_check = BRANCH_HALT_DELAY, 1481 .clkr = { 1482 .enable_reg = 0x52000, 1483 .enable_mask = BIT(16), 1484 .hw.init = &(const struct clk_init_data) { 1485 .name = "gcc_gpu_gpll0_div_clk_src", 1486 .parent_hws = (const struct clk_hw*[]) { 1487 &gcc_gpll0_out_even.clkr.hw, 1488 }, 1489 .num_parents = 1, 1490 .flags = CLK_SET_RATE_PARENT, 1491 .ops = &clk_branch2_ops, 1492 }, 1493 }, 1494 }; 1495 1496 static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1497 .halt_reg = 0x71010, 1498 .halt_check = BRANCH_HALT_VOTED, 1499 .hwcg_reg = 0x71010, 1500 .hwcg_bit = 1, 1501 .clkr = { 1502 .enable_reg = 0x71010, 1503 .enable_mask = BIT(0), 1504 .hw.init = &(const struct clk_init_data) { 1505 .name = "gcc_gpu_memnoc_gfx_clk", 1506 .ops = &clk_branch2_ops, 1507 }, 1508 }, 1509 }; 1510 1511 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1512 .halt_reg = 0x71018, 1513 .halt_check = BRANCH_HALT_DELAY, 1514 .clkr = { 1515 .enable_reg = 0x71018, 1516 .enable_mask = BIT(0), 1517 .hw.init = &(const struct clk_init_data) { 1518 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1519 .ops = &clk_branch2_ops, 1520 }, 1521 }, 1522 }; 1523 1524 static struct clk_branch gcc_pcie_0_aux_clk = { 1525 .halt_reg = 0x6b03c, 1526 .halt_check = BRANCH_HALT_VOTED, 1527 .clkr = { 1528 .enable_reg = 0x52008, 1529 .enable_mask = BIT(3), 1530 .hw.init = &(const struct clk_init_data) { 1531 .name = "gcc_pcie_0_aux_clk", 1532 .parent_hws = (const struct clk_hw*[]) { 1533 &gcc_pcie_0_aux_clk_src.clkr.hw, 1534 }, 1535 .num_parents = 1, 1536 .flags = CLK_SET_RATE_PARENT, 1537 .ops = &clk_branch2_ops, 1538 }, 1539 }, 1540 }; 1541 1542 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1543 .halt_reg = 0x6b038, 1544 .halt_check = BRANCH_HALT_VOTED, 1545 .hwcg_reg = 0x6b038, 1546 .hwcg_bit = 1, 1547 .clkr = { 1548 .enable_reg = 0x52008, 1549 .enable_mask = BIT(2), 1550 .hw.init = &(const struct clk_init_data) { 1551 .name = "gcc_pcie_0_cfg_ahb_clk", 1552 .ops = &clk_branch2_ops, 1553 }, 1554 }, 1555 }; 1556 1557 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1558 .halt_reg = 0x6b02c, 1559 .halt_check = BRANCH_HALT_SKIP, 1560 .hwcg_reg = 0x6b02c, 1561 .hwcg_bit = 1, 1562 .clkr = { 1563 .enable_reg = 0x52008, 1564 .enable_mask = BIT(1), 1565 .hw.init = &(const struct clk_init_data) { 1566 .name = "gcc_pcie_0_mstr_axi_clk", 1567 .ops = &clk_branch2_ops, 1568 }, 1569 }, 1570 }; 1571 1572 static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 1573 .halt_reg = 0x6b054, 1574 .halt_check = BRANCH_HALT_VOTED, 1575 .clkr = { 1576 .enable_reg = 0x52000, 1577 .enable_mask = BIT(22), 1578 .hw.init = &(const struct clk_init_data) { 1579 .name = "gcc_pcie_0_phy_rchng_clk", 1580 .parent_hws = (const struct clk_hw*[]) { 1581 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 1582 }, 1583 .num_parents = 1, 1584 .flags = CLK_SET_RATE_PARENT, 1585 .ops = &clk_branch2_ops, 1586 }, 1587 }, 1588 }; 1589 1590 static struct clk_branch gcc_pcie_0_pipe_clk = { 1591 .halt_reg = 0x6b048, 1592 .halt_check = BRANCH_HALT_SKIP, 1593 .clkr = { 1594 .enable_reg = 0x52008, 1595 .enable_mask = BIT(4), 1596 .hw.init = &(const struct clk_init_data) { 1597 .name = "gcc_pcie_0_pipe_clk", 1598 .parent_hws = (const struct clk_hw*[]) { 1599 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1600 }, 1601 .num_parents = 1, 1602 .flags = CLK_SET_RATE_PARENT, 1603 .ops = &clk_branch2_ops, 1604 }, 1605 }, 1606 }; 1607 1608 static struct clk_branch gcc_pcie_0_pipe_div2_clk = { 1609 .halt_reg = 0x6b098, 1610 .halt_check = BRANCH_HALT_SKIP, 1611 .clkr = { 1612 .enable_reg = 0x52018, 1613 .enable_mask = BIT(13), 1614 .hw.init = &(const struct clk_init_data) { 1615 .name = "gcc_pcie_0_pipe_div2_clk", 1616 .parent_hws = (const struct clk_hw*[]) { 1617 &gcc_pcie_0_pipe_div2_clk_src.clkr.hw, 1618 }, 1619 .num_parents = 1, 1620 .flags = CLK_SET_RATE_PARENT, 1621 .ops = &clk_branch2_ops, 1622 }, 1623 }, 1624 }; 1625 1626 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1627 .halt_reg = 0x6b020, 1628 .halt_check = BRANCH_HALT_VOTED, 1629 .hwcg_reg = 0x6b020, 1630 .hwcg_bit = 1, 1631 .clkr = { 1632 .enable_reg = 0x52008, 1633 .enable_mask = BIT(0), 1634 .hw.init = &(const struct clk_init_data) { 1635 .name = "gcc_pcie_0_slv_axi_clk", 1636 .ops = &clk_branch2_ops, 1637 }, 1638 }, 1639 }; 1640 1641 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1642 .halt_reg = 0x6b01c, 1643 .halt_check = BRANCH_HALT_VOTED, 1644 .clkr = { 1645 .enable_reg = 0x52008, 1646 .enable_mask = BIT(5), 1647 .hw.init = &(const struct clk_init_data) { 1648 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1649 .ops = &clk_branch2_ops, 1650 }, 1651 }, 1652 }; 1653 1654 static struct clk_branch gcc_pcie_1_aux_clk = { 1655 .halt_reg = 0x90038, 1656 .halt_check = BRANCH_HALT_VOTED, 1657 .clkr = { 1658 .enable_reg = 0x52000, 1659 .enable_mask = BIT(29), 1660 .hw.init = &(const struct clk_init_data) { 1661 .name = "gcc_pcie_1_aux_clk", 1662 .parent_hws = (const struct clk_hw*[]) { 1663 &gcc_pcie_1_aux_clk_src.clkr.hw, 1664 }, 1665 .num_parents = 1, 1666 .flags = CLK_SET_RATE_PARENT, 1667 .ops = &clk_branch2_ops, 1668 }, 1669 }, 1670 }; 1671 1672 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1673 .halt_reg = 0x90034, 1674 .halt_check = BRANCH_HALT_VOTED, 1675 .hwcg_reg = 0x90034, 1676 .hwcg_bit = 1, 1677 .clkr = { 1678 .enable_reg = 0x52000, 1679 .enable_mask = BIT(28), 1680 .hw.init = &(const struct clk_init_data) { 1681 .name = "gcc_pcie_1_cfg_ahb_clk", 1682 .ops = &clk_branch2_ops, 1683 }, 1684 }, 1685 }; 1686 1687 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1688 .halt_reg = 0x90028, 1689 .halt_check = BRANCH_HALT_SKIP, 1690 .hwcg_reg = 0x90028, 1691 .hwcg_bit = 1, 1692 .clkr = { 1693 .enable_reg = 0x52000, 1694 .enable_mask = BIT(27), 1695 .hw.init = &(const struct clk_init_data) { 1696 .name = "gcc_pcie_1_mstr_axi_clk", 1697 .ops = &clk_branch2_ops, 1698 }, 1699 }, 1700 }; 1701 1702 static struct clk_branch gcc_pcie_1_phy_rchng_clk = { 1703 .halt_reg = 0x90050, 1704 .halt_check = BRANCH_HALT_VOTED, 1705 .clkr = { 1706 .enable_reg = 0x52008, 1707 .enable_mask = BIT(8), 1708 .hw.init = &(const struct clk_init_data) { 1709 .name = "gcc_pcie_1_phy_rchng_clk", 1710 .parent_hws = (const struct clk_hw*[]) { 1711 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, 1712 }, 1713 .num_parents = 1, 1714 .flags = CLK_SET_RATE_PARENT, 1715 .ops = &clk_branch2_ops, 1716 }, 1717 }, 1718 }; 1719 1720 static struct clk_branch gcc_pcie_1_pipe_clk = { 1721 .halt_reg = 0x90044, 1722 .halt_check = BRANCH_HALT_SKIP, 1723 .clkr = { 1724 .enable_reg = 0x52008, 1725 .enable_mask = BIT(7), 1726 .hw.init = &(const struct clk_init_data) { 1727 .name = "gcc_pcie_1_pipe_clk", 1728 .parent_hws = (const struct clk_hw*[]) { 1729 &gcc_pcie_1_pipe_clk_src.clkr.hw, 1730 }, 1731 .num_parents = 1, 1732 .flags = CLK_SET_RATE_PARENT, 1733 .ops = &clk_branch2_ops, 1734 }, 1735 }, 1736 }; 1737 1738 static struct clk_branch gcc_pcie_1_pipe_div2_clk = { 1739 .halt_reg = 0x90094, 1740 .halt_check = BRANCH_HALT_SKIP, 1741 .clkr = { 1742 .enable_reg = 0x52018, 1743 .enable_mask = BIT(15), 1744 .hw.init = &(const struct clk_init_data) { 1745 .name = "gcc_pcie_1_pipe_div2_clk", 1746 .parent_hws = (const struct clk_hw*[]) { 1747 &gcc_pcie_1_pipe_div2_clk_src.clkr.hw, 1748 }, 1749 .num_parents = 1, 1750 .flags = CLK_SET_RATE_PARENT, 1751 .ops = &clk_branch2_ops, 1752 }, 1753 }, 1754 }; 1755 1756 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1757 .halt_reg = 0x9001c, 1758 .halt_check = BRANCH_HALT_VOTED, 1759 .hwcg_reg = 0x9001c, 1760 .hwcg_bit = 1, 1761 .clkr = { 1762 .enable_reg = 0x52000, 1763 .enable_mask = BIT(26), 1764 .hw.init = &(const struct clk_init_data) { 1765 .name = "gcc_pcie_1_slv_axi_clk", 1766 .ops = &clk_branch2_ops, 1767 }, 1768 }, 1769 }; 1770 1771 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 1772 .halt_reg = 0x90018, 1773 .halt_check = BRANCH_HALT_VOTED, 1774 .clkr = { 1775 .enable_reg = 0x52000, 1776 .enable_mask = BIT(25), 1777 .hw.init = &(const struct clk_init_data) { 1778 .name = "gcc_pcie_1_slv_q2a_axi_clk", 1779 .ops = &clk_branch2_ops, 1780 }, 1781 }, 1782 }; 1783 1784 static struct clk_branch gcc_pcie_rscc_cfg_ahb_clk = { 1785 .halt_reg = 0x11004, 1786 .halt_check = BRANCH_HALT_VOTED, 1787 .hwcg_reg = 0x11004, 1788 .hwcg_bit = 1, 1789 .clkr = { 1790 .enable_reg = 0x52010, 1791 .enable_mask = BIT(20), 1792 .hw.init = &(const struct clk_init_data) { 1793 .name = "gcc_pcie_rscc_cfg_ahb_clk", 1794 .ops = &clk_branch2_ops, 1795 }, 1796 }, 1797 }; 1798 1799 static struct clk_branch gcc_pcie_rscc_xo_clk = { 1800 .halt_reg = 0x11008, 1801 .halt_check = BRANCH_HALT_VOTED, 1802 .clkr = { 1803 .enable_reg = 0x52010, 1804 .enable_mask = BIT(21), 1805 .hw.init = &(const struct clk_init_data) { 1806 .name = "gcc_pcie_rscc_xo_clk", 1807 .ops = &clk_branch2_ops, 1808 }, 1809 }, 1810 }; 1811 1812 static struct clk_branch gcc_pdm2_clk = { 1813 .halt_reg = 0x3300c, 1814 .halt_check = BRANCH_HALT, 1815 .clkr = { 1816 .enable_reg = 0x3300c, 1817 .enable_mask = BIT(0), 1818 .hw.init = &(const struct clk_init_data) { 1819 .name = "gcc_pdm2_clk", 1820 .parent_hws = (const struct clk_hw*[]) { 1821 &gcc_pdm2_clk_src.clkr.hw, 1822 }, 1823 .num_parents = 1, 1824 .flags = CLK_SET_RATE_PARENT, 1825 .ops = &clk_branch2_ops, 1826 }, 1827 }, 1828 }; 1829 1830 static struct clk_branch gcc_pdm_ahb_clk = { 1831 .halt_reg = 0x33004, 1832 .halt_check = BRANCH_HALT_VOTED, 1833 .hwcg_reg = 0x33004, 1834 .hwcg_bit = 1, 1835 .clkr = { 1836 .enable_reg = 0x33004, 1837 .enable_mask = BIT(0), 1838 .hw.init = &(const struct clk_init_data) { 1839 .name = "gcc_pdm_ahb_clk", 1840 .ops = &clk_branch2_ops, 1841 }, 1842 }, 1843 }; 1844 1845 static struct clk_branch gcc_pdm_xo4_clk = { 1846 .halt_reg = 0x33008, 1847 .halt_check = BRANCH_HALT, 1848 .clkr = { 1849 .enable_reg = 0x33008, 1850 .enable_mask = BIT(0), 1851 .hw.init = &(const struct clk_init_data) { 1852 .name = "gcc_pdm_xo4_clk", 1853 .ops = &clk_branch2_ops, 1854 }, 1855 }, 1856 }; 1857 1858 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 1859 .halt_reg = 0x26008, 1860 .halt_check = BRANCH_HALT_VOTED, 1861 .hwcg_reg = 0x26008, 1862 .hwcg_bit = 1, 1863 .clkr = { 1864 .enable_reg = 0x26008, 1865 .enable_mask = BIT(0), 1866 .hw.init = &(const struct clk_init_data) { 1867 .name = "gcc_qmip_camera_nrt_ahb_clk", 1868 .ops = &clk_branch2_ops, 1869 }, 1870 }, 1871 }; 1872 1873 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 1874 .halt_reg = 0x2600c, 1875 .halt_check = BRANCH_HALT_VOTED, 1876 .hwcg_reg = 0x2600c, 1877 .hwcg_bit = 1, 1878 .clkr = { 1879 .enable_reg = 0x2600c, 1880 .enable_mask = BIT(0), 1881 .hw.init = &(const struct clk_init_data) { 1882 .name = "gcc_qmip_camera_rt_ahb_clk", 1883 .ops = &clk_branch2_ops, 1884 }, 1885 }, 1886 }; 1887 1888 static struct clk_branch gcc_qmip_disp_ahb_clk = { 1889 .halt_reg = 0x27008, 1890 .halt_check = BRANCH_HALT_VOTED, 1891 .hwcg_reg = 0x27008, 1892 .hwcg_bit = 1, 1893 .clkr = { 1894 .enable_reg = 0x27008, 1895 .enable_mask = BIT(0), 1896 .hw.init = &(const struct clk_init_data) { 1897 .name = "gcc_qmip_disp_ahb_clk", 1898 .ops = &clk_branch2_ops, 1899 }, 1900 }, 1901 }; 1902 1903 static struct clk_branch gcc_qmip_gpu_ahb_clk = { 1904 .halt_reg = 0x71008, 1905 .halt_check = BRANCH_HALT_VOTED, 1906 .hwcg_reg = 0x71008, 1907 .hwcg_bit = 1, 1908 .clkr = { 1909 .enable_reg = 0x71008, 1910 .enable_mask = BIT(0), 1911 .hw.init = &(const struct clk_init_data) { 1912 .name = "gcc_qmip_gpu_ahb_clk", 1913 .ops = &clk_branch2_ops, 1914 }, 1915 }, 1916 }; 1917 1918 static struct clk_branch gcc_qmip_pcie_ahb_clk = { 1919 .halt_reg = 0x6b018, 1920 .halt_check = BRANCH_HALT_VOTED, 1921 .hwcg_reg = 0x6b018, 1922 .hwcg_bit = 1, 1923 .clkr = { 1924 .enable_reg = 0x52000, 1925 .enable_mask = BIT(11), 1926 .hw.init = &(const struct clk_init_data) { 1927 .name = "gcc_qmip_pcie_ahb_clk", 1928 .ops = &clk_branch2_ops, 1929 }, 1930 }, 1931 }; 1932 1933 static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = { 1934 .halt_reg = 0x32014, 1935 .halt_check = BRANCH_HALT_VOTED, 1936 .hwcg_reg = 0x32014, 1937 .hwcg_bit = 1, 1938 .clkr = { 1939 .enable_reg = 0x32014, 1940 .enable_mask = BIT(0), 1941 .hw.init = &(const struct clk_init_data) { 1942 .name = "gcc_qmip_video_cv_cpu_ahb_clk", 1943 .ops = &clk_branch2_ops, 1944 }, 1945 }, 1946 }; 1947 1948 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 1949 .halt_reg = 0x32008, 1950 .halt_check = BRANCH_HALT_VOTED, 1951 .hwcg_reg = 0x32008, 1952 .hwcg_bit = 1, 1953 .clkr = { 1954 .enable_reg = 0x32008, 1955 .enable_mask = BIT(0), 1956 .hw.init = &(const struct clk_init_data) { 1957 .name = "gcc_qmip_video_cvp_ahb_clk", 1958 .ops = &clk_branch2_ops, 1959 }, 1960 }, 1961 }; 1962 1963 static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = { 1964 .halt_reg = 0x32010, 1965 .halt_check = BRANCH_HALT_VOTED, 1966 .hwcg_reg = 0x32010, 1967 .hwcg_bit = 1, 1968 .clkr = { 1969 .enable_reg = 0x32010, 1970 .enable_mask = BIT(0), 1971 .hw.init = &(const struct clk_init_data) { 1972 .name = "gcc_qmip_video_v_cpu_ahb_clk", 1973 .ops = &clk_branch2_ops, 1974 }, 1975 }, 1976 }; 1977 1978 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 1979 .halt_reg = 0x3200c, 1980 .halt_check = BRANCH_HALT_VOTED, 1981 .hwcg_reg = 0x3200c, 1982 .hwcg_bit = 1, 1983 .clkr = { 1984 .enable_reg = 0x3200c, 1985 .enable_mask = BIT(0), 1986 .hw.init = &(const struct clk_init_data) { 1987 .name = "gcc_qmip_video_vcodec_ahb_clk", 1988 .ops = &clk_branch2_ops, 1989 }, 1990 }, 1991 }; 1992 1993 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 1994 .halt_reg = 0x23018, 1995 .halt_check = BRANCH_HALT_VOTED, 1996 .clkr = { 1997 .enable_reg = 0x52008, 1998 .enable_mask = BIT(18), 1999 .hw.init = &(const struct clk_init_data) { 2000 .name = "gcc_qupv3_wrap0_core_2x_clk", 2001 .ops = &clk_branch2_ops, 2002 }, 2003 }, 2004 }; 2005 2006 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 2007 .halt_reg = 0x23008, 2008 .halt_check = BRANCH_HALT_VOTED, 2009 .clkr = { 2010 .enable_reg = 0x52008, 2011 .enable_mask = BIT(19), 2012 .hw.init = &(const struct clk_init_data) { 2013 .name = "gcc_qupv3_wrap0_core_clk", 2014 .ops = &clk_branch2_ops, 2015 }, 2016 }, 2017 }; 2018 2019 static struct clk_branch gcc_qupv3_wrap0_qspi_ref_clk = { 2020 .halt_reg = 0x18764, 2021 .halt_check = BRANCH_HALT_VOTED, 2022 .clkr = { 2023 .enable_reg = 0x52010, 2024 .enable_mask = BIT(29), 2025 .hw.init = &(const struct clk_init_data) { 2026 .name = "gcc_qupv3_wrap0_qspi_ref_clk", 2027 .parent_hws = (const struct clk_hw*[]) { 2028 &gcc_qupv3_wrap0_qspi_ref_clk_src.clkr.hw, 2029 }, 2030 .num_parents = 1, 2031 .flags = CLK_SET_RATE_PARENT, 2032 .ops = &clk_branch2_ops, 2033 }, 2034 }, 2035 }; 2036 2037 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2038 .halt_reg = 0x18004, 2039 .halt_check = BRANCH_HALT_VOTED, 2040 .clkr = { 2041 .enable_reg = 0x52008, 2042 .enable_mask = BIT(22), 2043 .hw.init = &(const struct clk_init_data) { 2044 .name = "gcc_qupv3_wrap0_s0_clk", 2045 .parent_hws = (const struct clk_hw*[]) { 2046 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 2047 }, 2048 .num_parents = 1, 2049 .flags = CLK_SET_RATE_PARENT, 2050 .ops = &clk_branch2_ops, 2051 }, 2052 }, 2053 }; 2054 2055 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2056 .halt_reg = 0x1813c, 2057 .halt_check = BRANCH_HALT_VOTED, 2058 .clkr = { 2059 .enable_reg = 0x52008, 2060 .enable_mask = BIT(23), 2061 .hw.init = &(const struct clk_init_data) { 2062 .name = "gcc_qupv3_wrap0_s1_clk", 2063 .parent_hws = (const struct clk_hw*[]) { 2064 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 2065 }, 2066 .num_parents = 1, 2067 .flags = CLK_SET_RATE_PARENT, 2068 .ops = &clk_branch2_ops, 2069 }, 2070 }, 2071 }; 2072 2073 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2074 .halt_reg = 0x18274, 2075 .halt_check = BRANCH_HALT_VOTED, 2076 .clkr = { 2077 .enable_reg = 0x52008, 2078 .enable_mask = BIT(24), 2079 .hw.init = &(const struct clk_init_data) { 2080 .name = "gcc_qupv3_wrap0_s2_clk", 2081 .parent_hws = (const struct clk_hw*[]) { 2082 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 2083 }, 2084 .num_parents = 1, 2085 .flags = CLK_SET_RATE_PARENT, 2086 .ops = &clk_branch2_ops, 2087 }, 2088 }, 2089 }; 2090 2091 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2092 .halt_reg = 0x18284, 2093 .halt_check = BRANCH_HALT_VOTED, 2094 .clkr = { 2095 .enable_reg = 0x52008, 2096 .enable_mask = BIT(25), 2097 .hw.init = &(const struct clk_init_data) { 2098 .name = "gcc_qupv3_wrap0_s3_clk", 2099 .parent_hws = (const struct clk_hw*[]) { 2100 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 2101 }, 2102 .num_parents = 1, 2103 .flags = CLK_SET_RATE_PARENT, 2104 .ops = &clk_branch2_ops, 2105 }, 2106 }, 2107 }; 2108 2109 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2110 .halt_reg = 0x183bc, 2111 .halt_check = BRANCH_HALT_VOTED, 2112 .clkr = { 2113 .enable_reg = 0x52008, 2114 .enable_mask = BIT(26), 2115 .hw.init = &(const struct clk_init_data) { 2116 .name = "gcc_qupv3_wrap0_s4_clk", 2117 .parent_hws = (const struct clk_hw*[]) { 2118 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 2119 }, 2120 .num_parents = 1, 2121 .flags = CLK_SET_RATE_PARENT, 2122 .ops = &clk_branch2_ops, 2123 }, 2124 }, 2125 }; 2126 2127 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2128 .halt_reg = 0x184f4, 2129 .halt_check = BRANCH_HALT_VOTED, 2130 .clkr = { 2131 .enable_reg = 0x52008, 2132 .enable_mask = BIT(27), 2133 .hw.init = &(const struct clk_init_data) { 2134 .name = "gcc_qupv3_wrap0_s5_clk", 2135 .parent_hws = (const struct clk_hw*[]) { 2136 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 2137 }, 2138 .num_parents = 1, 2139 .flags = CLK_SET_RATE_PARENT, 2140 .ops = &clk_branch2_ops, 2141 }, 2142 }, 2143 }; 2144 2145 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 2146 .halt_reg = 0x1862c, 2147 .halt_check = BRANCH_HALT_VOTED, 2148 .clkr = { 2149 .enable_reg = 0x52008, 2150 .enable_mask = BIT(28), 2151 .hw.init = &(const struct clk_init_data) { 2152 .name = "gcc_qupv3_wrap0_s6_clk", 2153 .parent_hws = (const struct clk_hw*[]) { 2154 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 2155 }, 2156 .num_parents = 1, 2157 .flags = CLK_SET_RATE_PARENT, 2158 .ops = &clk_branch2_ops, 2159 }, 2160 }, 2161 }; 2162 2163 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 2164 .halt_reg = 0x23168, 2165 .halt_check = BRANCH_HALT_VOTED, 2166 .clkr = { 2167 .enable_reg = 0x52010, 2168 .enable_mask = BIT(3), 2169 .hw.init = &(const struct clk_init_data) { 2170 .name = "gcc_qupv3_wrap1_core_2x_clk", 2171 .ops = &clk_branch2_ops, 2172 }, 2173 }, 2174 }; 2175 2176 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 2177 .halt_reg = 0x23158, 2178 .halt_check = BRANCH_HALT_VOTED, 2179 .clkr = { 2180 .enable_reg = 0x52010, 2181 .enable_mask = BIT(0), 2182 .hw.init = &(const struct clk_init_data) { 2183 .name = "gcc_qupv3_wrap1_core_clk", 2184 .ops = &clk_branch2_ops, 2185 }, 2186 }, 2187 }; 2188 2189 static struct clk_branch gcc_qupv3_wrap1_qspi_ref_clk = { 2190 .halt_reg = 0x1e764, 2191 .halt_check = BRANCH_HALT_VOTED, 2192 .clkr = { 2193 .enable_reg = 0x52010, 2194 .enable_mask = BIT(30), 2195 .hw.init = &(const struct clk_init_data) { 2196 .name = "gcc_qupv3_wrap1_qspi_ref_clk", 2197 .parent_hws = (const struct clk_hw*[]) { 2198 &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw, 2199 }, 2200 .num_parents = 1, 2201 .flags = CLK_SET_RATE_PARENT, 2202 .ops = &clk_branch2_ops, 2203 }, 2204 }, 2205 }; 2206 2207 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2208 .halt_reg = 0x1e004, 2209 .halt_check = BRANCH_HALT_VOTED, 2210 .clkr = { 2211 .enable_reg = 0x52010, 2212 .enable_mask = BIT(4), 2213 .hw.init = &(const struct clk_init_data) { 2214 .name = "gcc_qupv3_wrap1_s0_clk", 2215 .parent_hws = (const struct clk_hw*[]) { 2216 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 2217 }, 2218 .num_parents = 1, 2219 .flags = CLK_SET_RATE_PARENT, 2220 .ops = &clk_branch2_ops, 2221 }, 2222 }, 2223 }; 2224 2225 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2226 .halt_reg = 0x1e13c, 2227 .halt_check = BRANCH_HALT_VOTED, 2228 .clkr = { 2229 .enable_reg = 0x52010, 2230 .enable_mask = BIT(5), 2231 .hw.init = &(const struct clk_init_data) { 2232 .name = "gcc_qupv3_wrap1_s1_clk", 2233 .parent_hws = (const struct clk_hw*[]) { 2234 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 2235 }, 2236 .num_parents = 1, 2237 .flags = CLK_SET_RATE_PARENT, 2238 .ops = &clk_branch2_ops, 2239 }, 2240 }, 2241 }; 2242 2243 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2244 .halt_reg = 0x1e274, 2245 .halt_check = BRANCH_HALT_VOTED, 2246 .clkr = { 2247 .enable_reg = 0x52010, 2248 .enable_mask = BIT(6), 2249 .hw.init = &(const struct clk_init_data) { 2250 .name = "gcc_qupv3_wrap1_s2_clk", 2251 .parent_hws = (const struct clk_hw*[]) { 2252 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 2253 }, 2254 .num_parents = 1, 2255 .flags = CLK_SET_RATE_PARENT, 2256 .ops = &clk_branch2_ops, 2257 }, 2258 }, 2259 }; 2260 2261 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2262 .halt_reg = 0x1e284, 2263 .halt_check = BRANCH_HALT_VOTED, 2264 .clkr = { 2265 .enable_reg = 0x52010, 2266 .enable_mask = BIT(7), 2267 .hw.init = &(const struct clk_init_data) { 2268 .name = "gcc_qupv3_wrap1_s3_clk", 2269 .parent_hws = (const struct clk_hw*[]) { 2270 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2271 }, 2272 .num_parents = 1, 2273 .flags = CLK_SET_RATE_PARENT, 2274 .ops = &clk_branch2_ops, 2275 }, 2276 }, 2277 }; 2278 2279 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2280 .halt_reg = 0x1e3bc, 2281 .halt_check = BRANCH_HALT_VOTED, 2282 .clkr = { 2283 .enable_reg = 0x52010, 2284 .enable_mask = BIT(8), 2285 .hw.init = &(const struct clk_init_data) { 2286 .name = "gcc_qupv3_wrap1_s4_clk", 2287 .parent_hws = (const struct clk_hw*[]) { 2288 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2289 }, 2290 .num_parents = 1, 2291 .flags = CLK_SET_RATE_PARENT, 2292 .ops = &clk_branch2_ops, 2293 }, 2294 }, 2295 }; 2296 2297 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2298 .halt_reg = 0x1e4f4, 2299 .halt_check = BRANCH_HALT_VOTED, 2300 .clkr = { 2301 .enable_reg = 0x52010, 2302 .enable_mask = BIT(9), 2303 .hw.init = &(const struct clk_init_data) { 2304 .name = "gcc_qupv3_wrap1_s5_clk", 2305 .parent_hws = (const struct clk_hw*[]) { 2306 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 2307 }, 2308 .num_parents = 1, 2309 .flags = CLK_SET_RATE_PARENT, 2310 .ops = &clk_branch2_ops, 2311 }, 2312 }, 2313 }; 2314 2315 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 2316 .halt_reg = 0x1e62c, 2317 .halt_check = BRANCH_HALT_VOTED, 2318 .clkr = { 2319 .enable_reg = 0x52010, 2320 .enable_mask = BIT(10), 2321 .hw.init = &(const struct clk_init_data) { 2322 .name = "gcc_qupv3_wrap1_s6_clk", 2323 .parent_hws = (const struct clk_hw*[]) { 2324 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 2325 }, 2326 .num_parents = 1, 2327 .flags = CLK_SET_RATE_PARENT, 2328 .ops = &clk_branch2_ops, 2329 }, 2330 }, 2331 }; 2332 2333 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2334 .halt_reg = 0x23000, 2335 .halt_check = BRANCH_HALT_VOTED, 2336 .clkr = { 2337 .enable_reg = 0x52008, 2338 .enable_mask = BIT(20), 2339 .hw.init = &(const struct clk_init_data) { 2340 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2341 .ops = &clk_branch2_ops, 2342 }, 2343 }, 2344 }; 2345 2346 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2347 .halt_reg = 0x23004, 2348 .halt_check = BRANCH_HALT_VOTED, 2349 .hwcg_reg = 0x23004, 2350 .hwcg_bit = 1, 2351 .clkr = { 2352 .enable_reg = 0x52008, 2353 .enable_mask = BIT(21), 2354 .hw.init = &(const struct clk_init_data) { 2355 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2356 .ops = &clk_branch2_ops, 2357 }, 2358 }, 2359 }; 2360 2361 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2362 .halt_reg = 0x23150, 2363 .halt_check = BRANCH_HALT_VOTED, 2364 .clkr = { 2365 .enable_reg = 0x52010, 2366 .enable_mask = BIT(2), 2367 .hw.init = &(const struct clk_init_data) { 2368 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2369 .ops = &clk_branch2_ops, 2370 }, 2371 }, 2372 }; 2373 2374 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2375 .halt_reg = 0x23154, 2376 .halt_check = BRANCH_HALT_VOTED, 2377 .hwcg_reg = 0x23154, 2378 .hwcg_bit = 1, 2379 .clkr = { 2380 .enable_reg = 0x52010, 2381 .enable_mask = BIT(1), 2382 .hw.init = &(const struct clk_init_data) { 2383 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2384 .ops = &clk_branch2_ops, 2385 }, 2386 }, 2387 }; 2388 2389 static struct clk_branch gcc_sdcc1_ahb_clk = { 2390 .halt_reg = 0xa3004, 2391 .halt_check = BRANCH_HALT, 2392 .clkr = { 2393 .enable_reg = 0xa3004, 2394 .enable_mask = BIT(0), 2395 .hw.init = &(const struct clk_init_data) { 2396 .name = "gcc_sdcc1_ahb_clk", 2397 .ops = &clk_branch2_ops, 2398 }, 2399 }, 2400 }; 2401 2402 static struct clk_branch gcc_sdcc1_apps_clk = { 2403 .halt_reg = 0xa3008, 2404 .halt_check = BRANCH_HALT, 2405 .clkr = { 2406 .enable_reg = 0xa3008, 2407 .enable_mask = BIT(0), 2408 .hw.init = &(const struct clk_init_data) { 2409 .name = "gcc_sdcc1_apps_clk", 2410 .parent_hws = (const struct clk_hw*[]) { 2411 &gcc_sdcc1_apps_clk_src.clkr.hw, 2412 }, 2413 .num_parents = 1, 2414 .flags = CLK_SET_RATE_PARENT, 2415 .ops = &clk_branch2_ops, 2416 }, 2417 }, 2418 }; 2419 2420 static struct clk_branch gcc_sdcc1_ice_core_clk = { 2421 .halt_reg = 0xa302c, 2422 .halt_check = BRANCH_HALT_VOTED, 2423 .hwcg_reg = 0xa302c, 2424 .hwcg_bit = 1, 2425 .clkr = { 2426 .enable_reg = 0xa302c, 2427 .enable_mask = BIT(0), 2428 .hw.init = &(const struct clk_init_data) { 2429 .name = "gcc_sdcc1_ice_core_clk", 2430 .parent_hws = (const struct clk_hw*[]) { 2431 &gcc_sdcc1_ice_core_clk_src.clkr.hw, 2432 }, 2433 .num_parents = 1, 2434 .flags = CLK_SET_RATE_PARENT, 2435 .ops = &clk_branch2_ops, 2436 }, 2437 }, 2438 }; 2439 2440 static struct clk_branch gcc_sdcc2_ahb_clk = { 2441 .halt_reg = 0x14010, 2442 .halt_check = BRANCH_HALT, 2443 .clkr = { 2444 .enable_reg = 0x14010, 2445 .enable_mask = BIT(0), 2446 .hw.init = &(const struct clk_init_data) { 2447 .name = "gcc_sdcc2_ahb_clk", 2448 .ops = &clk_branch2_ops, 2449 }, 2450 }, 2451 }; 2452 2453 static struct clk_branch gcc_sdcc2_apps_clk = { 2454 .halt_reg = 0x14004, 2455 .halt_check = BRANCH_HALT, 2456 .clkr = { 2457 .enable_reg = 0x14004, 2458 .enable_mask = BIT(0), 2459 .hw.init = &(const struct clk_init_data) { 2460 .name = "gcc_sdcc2_apps_clk", 2461 .parent_hws = (const struct clk_hw*[]) { 2462 &gcc_sdcc2_apps_clk_src.clkr.hw, 2463 }, 2464 .num_parents = 1, 2465 .flags = CLK_SET_RATE_PARENT, 2466 .ops = &clk_branch2_ops, 2467 }, 2468 }, 2469 }; 2470 2471 static struct clk_branch gcc_ufs_phy_ahb_clk = { 2472 .halt_reg = 0x77024, 2473 .halt_check = BRANCH_HALT_VOTED, 2474 .hwcg_reg = 0x77024, 2475 .hwcg_bit = 1, 2476 .clkr = { 2477 .enable_reg = 0x77024, 2478 .enable_mask = BIT(0), 2479 .hw.init = &(const struct clk_init_data) { 2480 .name = "gcc_ufs_phy_ahb_clk", 2481 .ops = &clk_branch2_ops, 2482 }, 2483 }, 2484 }; 2485 2486 static struct clk_branch gcc_ufs_phy_axi_clk = { 2487 .halt_reg = 0x77018, 2488 .halt_check = BRANCH_HALT_VOTED, 2489 .hwcg_reg = 0x77018, 2490 .hwcg_bit = 1, 2491 .clkr = { 2492 .enable_reg = 0x77018, 2493 .enable_mask = BIT(0), 2494 .hw.init = &(const struct clk_init_data) { 2495 .name = "gcc_ufs_phy_axi_clk", 2496 .parent_hws = (const struct clk_hw*[]) { 2497 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2498 }, 2499 .num_parents = 1, 2500 .flags = CLK_SET_RATE_PARENT, 2501 .ops = &clk_branch2_ops, 2502 }, 2503 }, 2504 }; 2505 2506 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { 2507 .halt_reg = 0x77018, 2508 .halt_check = BRANCH_HALT_VOTED, 2509 .hwcg_reg = 0x77018, 2510 .hwcg_bit = 1, 2511 .clkr = { 2512 .enable_reg = 0x77018, 2513 .enable_mask = BIT(1), 2514 .hw.init = &(const struct clk_init_data) { 2515 .name = "gcc_ufs_phy_axi_hw_ctl_clk", 2516 .parent_hws = (const struct clk_hw*[]) { 2517 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2518 }, 2519 .num_parents = 1, 2520 .flags = CLK_SET_RATE_PARENT, 2521 .ops = &clk_branch2_ops, 2522 }, 2523 }, 2524 }; 2525 2526 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2527 .halt_reg = 0x77074, 2528 .halt_check = BRANCH_HALT_VOTED, 2529 .hwcg_reg = 0x77074, 2530 .hwcg_bit = 1, 2531 .clkr = { 2532 .enable_reg = 0x77074, 2533 .enable_mask = BIT(0), 2534 .hw.init = &(const struct clk_init_data) { 2535 .name = "gcc_ufs_phy_ice_core_clk", 2536 .parent_hws = (const struct clk_hw*[]) { 2537 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2538 }, 2539 .num_parents = 1, 2540 .flags = CLK_SET_RATE_PARENT, 2541 .ops = &clk_branch2_ops, 2542 }, 2543 }, 2544 }; 2545 2546 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { 2547 .halt_reg = 0x77074, 2548 .halt_check = BRANCH_HALT_VOTED, 2549 .hwcg_reg = 0x77074, 2550 .hwcg_bit = 1, 2551 .clkr = { 2552 .enable_reg = 0x77074, 2553 .enable_mask = BIT(1), 2554 .hw.init = &(const struct clk_init_data) { 2555 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", 2556 .parent_hws = (const struct clk_hw*[]) { 2557 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2558 }, 2559 .num_parents = 1, 2560 .flags = CLK_SET_RATE_PARENT, 2561 .ops = &clk_branch2_ops, 2562 }, 2563 }, 2564 }; 2565 2566 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2567 .halt_reg = 0x770b0, 2568 .halt_check = BRANCH_HALT_VOTED, 2569 .hwcg_reg = 0x770b0, 2570 .hwcg_bit = 1, 2571 .clkr = { 2572 .enable_reg = 0x770b0, 2573 .enable_mask = BIT(0), 2574 .hw.init = &(const struct clk_init_data) { 2575 .name = "gcc_ufs_phy_phy_aux_clk", 2576 .parent_hws = (const struct clk_hw*[]) { 2577 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2578 }, 2579 .num_parents = 1, 2580 .flags = CLK_SET_RATE_PARENT, 2581 .ops = &clk_branch2_ops, 2582 }, 2583 }, 2584 }; 2585 2586 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { 2587 .halt_reg = 0x770b0, 2588 .halt_check = BRANCH_HALT_VOTED, 2589 .hwcg_reg = 0x770b0, 2590 .hwcg_bit = 1, 2591 .clkr = { 2592 .enable_reg = 0x770b0, 2593 .enable_mask = BIT(1), 2594 .hw.init = &(const struct clk_init_data) { 2595 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", 2596 .parent_hws = (const struct clk_hw*[]) { 2597 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2598 }, 2599 .num_parents = 1, 2600 .flags = CLK_SET_RATE_PARENT, 2601 .ops = &clk_branch2_ops, 2602 }, 2603 }, 2604 }; 2605 2606 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2607 .halt_reg = 0x7702c, 2608 .halt_check = BRANCH_HALT_DELAY, 2609 .clkr = { 2610 .enable_reg = 0x7702c, 2611 .enable_mask = BIT(0), 2612 .hw.init = &(const struct clk_init_data) { 2613 .name = "gcc_ufs_phy_rx_symbol_0_clk", 2614 .parent_hws = (const struct clk_hw*[]) { 2615 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, 2616 }, 2617 .num_parents = 1, 2618 .flags = CLK_SET_RATE_PARENT, 2619 .ops = &clk_branch2_ops, 2620 }, 2621 }, 2622 }; 2623 2624 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 2625 .halt_reg = 0x770cc, 2626 .halt_check = BRANCH_HALT_DELAY, 2627 .clkr = { 2628 .enable_reg = 0x770cc, 2629 .enable_mask = BIT(0), 2630 .hw.init = &(const struct clk_init_data) { 2631 .name = "gcc_ufs_phy_rx_symbol_1_clk", 2632 .parent_hws = (const struct clk_hw*[]) { 2633 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, 2634 }, 2635 .num_parents = 1, 2636 .flags = CLK_SET_RATE_PARENT, 2637 .ops = &clk_branch2_ops, 2638 }, 2639 }, 2640 }; 2641 2642 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2643 .halt_reg = 0x77028, 2644 .halt_check = BRANCH_HALT_DELAY, 2645 .clkr = { 2646 .enable_reg = 0x77028, 2647 .enable_mask = BIT(0), 2648 .hw.init = &(const struct clk_init_data) { 2649 .name = "gcc_ufs_phy_tx_symbol_0_clk", 2650 .parent_hws = (const struct clk_hw*[]) { 2651 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, 2652 }, 2653 .num_parents = 1, 2654 .flags = CLK_SET_RATE_PARENT, 2655 .ops = &clk_branch2_ops, 2656 }, 2657 }, 2658 }; 2659 2660 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2661 .halt_reg = 0x77068, 2662 .halt_check = BRANCH_HALT_VOTED, 2663 .hwcg_reg = 0x77068, 2664 .hwcg_bit = 1, 2665 .clkr = { 2666 .enable_reg = 0x77068, 2667 .enable_mask = BIT(0), 2668 .hw.init = &(const struct clk_init_data) { 2669 .name = "gcc_ufs_phy_unipro_core_clk", 2670 .parent_hws = (const struct clk_hw*[]) { 2671 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2672 }, 2673 .num_parents = 1, 2674 .flags = CLK_SET_RATE_PARENT, 2675 .ops = &clk_branch2_ops, 2676 }, 2677 }, 2678 }; 2679 2680 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { 2681 .halt_reg = 0x77068, 2682 .halt_check = BRANCH_HALT_VOTED, 2683 .hwcg_reg = 0x77068, 2684 .hwcg_bit = 1, 2685 .clkr = { 2686 .enable_reg = 0x77068, 2687 .enable_mask = BIT(1), 2688 .hw.init = &(const struct clk_init_data) { 2689 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", 2690 .parent_hws = (const struct clk_hw*[]) { 2691 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2692 }, 2693 .num_parents = 1, 2694 .flags = CLK_SET_RATE_PARENT, 2695 .ops = &clk_branch2_ops, 2696 }, 2697 }, 2698 }; 2699 2700 static struct clk_branch gcc_usb30_prim_atb_clk = { 2701 .halt_reg = 0x39088, 2702 .halt_check = BRANCH_HALT_VOTED, 2703 .clkr = { 2704 .enable_reg = 0x39088, 2705 .enable_mask = BIT(0), 2706 .hw.init = &(const struct clk_init_data) { 2707 .name = "gcc_usb30_prim_atb_clk", 2708 .parent_hws = (const struct clk_hw*[]) { 2709 &gcc_usb30_prim_master_clk_src.clkr.hw, 2710 }, 2711 .num_parents = 1, 2712 .flags = CLK_SET_RATE_PARENT, 2713 .ops = &clk_branch2_ops, 2714 }, 2715 }, 2716 }; 2717 2718 static struct clk_branch gcc_usb30_prim_master_clk = { 2719 .halt_reg = 0x39018, 2720 .halt_check = BRANCH_HALT, 2721 .clkr = { 2722 .enable_reg = 0x39018, 2723 .enable_mask = BIT(0), 2724 .hw.init = &(const struct clk_init_data) { 2725 .name = "gcc_usb30_prim_master_clk", 2726 .parent_hws = (const struct clk_hw*[]) { 2727 &gcc_usb30_prim_master_clk_src.clkr.hw, 2728 }, 2729 .num_parents = 1, 2730 .flags = CLK_SET_RATE_PARENT, 2731 .ops = &clk_branch2_ops, 2732 }, 2733 }, 2734 }; 2735 2736 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 2737 .halt_reg = 0x39028, 2738 .halt_check = BRANCH_HALT, 2739 .clkr = { 2740 .enable_reg = 0x39028, 2741 .enable_mask = BIT(0), 2742 .hw.init = &(const struct clk_init_data) { 2743 .name = "gcc_usb30_prim_mock_utmi_clk", 2744 .parent_hws = (const struct clk_hw*[]) { 2745 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 2746 }, 2747 .num_parents = 1, 2748 .flags = CLK_SET_RATE_PARENT, 2749 .ops = &clk_branch2_ops, 2750 }, 2751 }, 2752 }; 2753 2754 static struct clk_branch gcc_usb30_prim_sleep_clk = { 2755 .halt_reg = 0x39024, 2756 .halt_check = BRANCH_HALT, 2757 .clkr = { 2758 .enable_reg = 0x39024, 2759 .enable_mask = BIT(0), 2760 .hw.init = &(const struct clk_init_data) { 2761 .name = "gcc_usb30_prim_sleep_clk", 2762 .ops = &clk_branch2_ops, 2763 }, 2764 }, 2765 }; 2766 2767 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 2768 .halt_reg = 0x39060, 2769 .halt_check = BRANCH_HALT, 2770 .clkr = { 2771 .enable_reg = 0x39060, 2772 .enable_mask = BIT(0), 2773 .hw.init = &(const struct clk_init_data) { 2774 .name = "gcc_usb3_prim_phy_aux_clk", 2775 .parent_hws = (const struct clk_hw*[]) { 2776 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2777 }, 2778 .num_parents = 1, 2779 .flags = CLK_SET_RATE_PARENT, 2780 .ops = &clk_branch2_ops, 2781 }, 2782 }, 2783 }; 2784 2785 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 2786 .halt_reg = 0x39064, 2787 .halt_check = BRANCH_HALT, 2788 .clkr = { 2789 .enable_reg = 0x39064, 2790 .enable_mask = BIT(0), 2791 .hw.init = &(const struct clk_init_data) { 2792 .name = "gcc_usb3_prim_phy_com_aux_clk", 2793 .parent_hws = (const struct clk_hw*[]) { 2794 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 2795 }, 2796 .num_parents = 1, 2797 .flags = CLK_SET_RATE_PARENT, 2798 .ops = &clk_branch2_ops, 2799 }, 2800 }, 2801 }; 2802 2803 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 2804 .halt_reg = 0x39068, 2805 .halt_check = BRANCH_HALT_DELAY, 2806 .hwcg_reg = 0x39068, 2807 .hwcg_bit = 1, 2808 .clkr = { 2809 .enable_reg = 0x39068, 2810 .enable_mask = BIT(0), 2811 .hw.init = &(const struct clk_init_data) { 2812 .name = "gcc_usb3_prim_phy_pipe_clk", 2813 .parent_hws = (const struct clk_hw*[]) { 2814 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 2815 }, 2816 .num_parents = 1, 2817 .flags = CLK_SET_RATE_PARENT, 2818 .ops = &clk_branch2_ops, 2819 }, 2820 }, 2821 }; 2822 2823 static struct clk_branch gcc_video_axi0_clk = { 2824 .halt_reg = 0x32018, 2825 .halt_check = BRANCH_HALT_SKIP, 2826 .hwcg_reg = 0x32018, 2827 .hwcg_bit = 1, 2828 .clkr = { 2829 .enable_reg = 0x32018, 2830 .enable_mask = BIT(0), 2831 .hw.init = &(const struct clk_init_data) { 2832 .name = "gcc_video_axi0_clk", 2833 .ops = &clk_branch2_ops, 2834 }, 2835 }, 2836 }; 2837 2838 static struct gdsc pcie_0_gdsc = { 2839 .gdscr = 0x6b004, 2840 .collapse_ctrl = 0x5214c, 2841 .collapse_mask = BIT(0), 2842 .en_rest_wait_val = 0x2, 2843 .en_few_wait_val = 0x2, 2844 .clk_dis_wait_val = 0xf, 2845 .pd = { 2846 .name = "pcie_0_gdsc", 2847 }, 2848 .pwrsts = PWRSTS_OFF_ON, 2849 .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2850 }; 2851 2852 static struct gdsc pcie_0_phy_gdsc = { 2853 .gdscr = 0x6c000, 2854 .collapse_ctrl = 0x5214c, 2855 .collapse_mask = BIT(1), 2856 .en_rest_wait_val = 0x2, 2857 .en_few_wait_val = 0x2, 2858 .clk_dis_wait_val = 0x2, 2859 .pd = { 2860 .name = "pcie_0_phy_gdsc", 2861 }, 2862 .pwrsts = PWRSTS_OFF_ON, 2863 .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2864 }; 2865 2866 static struct gdsc pcie_1_gdsc = { 2867 .gdscr = 0x90004, 2868 .collapse_ctrl = 0x5214c, 2869 .collapse_mask = BIT(3), 2870 .en_rest_wait_val = 0x2, 2871 .en_few_wait_val = 0x2, 2872 .clk_dis_wait_val = 0xf, 2873 .pd = { 2874 .name = "pcie_1_gdsc", 2875 }, 2876 .pwrsts = PWRSTS_OFF_ON, 2877 .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2878 }; 2879 2880 static struct gdsc pcie_1_phy_gdsc = { 2881 .gdscr = 0xa2000, 2882 .collapse_ctrl = 0x5214c, 2883 .collapse_mask = BIT(4), 2884 .en_rest_wait_val = 0x2, 2885 .en_few_wait_val = 0x2, 2886 .clk_dis_wait_val = 0x2, 2887 .pd = { 2888 .name = "pcie_1_phy_gdsc", 2889 }, 2890 .pwrsts = PWRSTS_OFF_ON, 2891 .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2892 }; 2893 2894 static struct gdsc ufs_phy_gdsc = { 2895 .gdscr = 0x77004, 2896 .en_rest_wait_val = 0x2, 2897 .en_few_wait_val = 0x2, 2898 .clk_dis_wait_val = 0xf, 2899 .pd = { 2900 .name = "ufs_phy_gdsc", 2901 }, 2902 .pwrsts = PWRSTS_OFF_ON, 2903 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2904 }; 2905 2906 static struct gdsc ufs_mem_phy_gdsc = { 2907 .gdscr = 0x9e000, 2908 .en_rest_wait_val = 0x2, 2909 .en_few_wait_val = 0x2, 2910 .clk_dis_wait_val = 0x2, 2911 .pd = { 2912 .name = "ufs_mem_phy_gdsc", 2913 }, 2914 .pwrsts = PWRSTS_OFF_ON, 2915 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2916 }; 2917 2918 static struct gdsc usb30_prim_gdsc = { 2919 .gdscr = 0x39004, 2920 .en_rest_wait_val = 0x2, 2921 .en_few_wait_val = 0x2, 2922 .clk_dis_wait_val = 0xf, 2923 .pd = { 2924 .name = "usb30_prim_gdsc", 2925 }, 2926 .pwrsts = PWRSTS_RET_ON, 2927 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2928 }; 2929 2930 static struct gdsc usb3_phy_gdsc = { 2931 .gdscr = 0x5000c, 2932 .en_rest_wait_val = 0x2, 2933 .en_few_wait_val = 0x2, 2934 .clk_dis_wait_val = 0x2, 2935 .pd = { 2936 .name = "usb3_phy_gdsc", 2937 }, 2938 .pwrsts = PWRSTS_RET_ON, 2939 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 2940 }; 2941 2942 static struct clk_regmap *gcc_milos_clocks[] = { 2943 [GCC_AGGRE_NOC_PCIE_AXI_CLK] = &gcc_aggre_noc_pcie_axi_clk.clkr, 2944 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 2945 [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr, 2946 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 2947 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2948 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 2949 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 2950 [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr, 2951 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 2952 [GCC_CNOC_PCIE_SF_AXI_CLK] = &gcc_cnoc_pcie_sf_axi_clk.clkr, 2953 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 2954 [GCC_DDRSS_PCIE_SF_QTB_CLK] = &gcc_ddrss_pcie_sf_qtb_clk.clkr, 2955 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, 2956 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 2957 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2958 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 2959 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2960 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 2961 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2962 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 2963 [GCC_GPLL0] = &gcc_gpll0.clkr, 2964 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 2965 [GCC_GPLL2] = &gcc_gpll2.clkr, 2966 [GCC_GPLL4] = &gcc_gpll4.clkr, 2967 [GCC_GPLL6] = &gcc_gpll6.clkr, 2968 [GCC_GPLL7] = &gcc_gpll7.clkr, 2969 [GCC_GPLL9] = &gcc_gpll9.clkr, 2970 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 2971 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 2972 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 2973 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 2974 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 2975 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 2976 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 2977 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 2978 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 2979 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 2980 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 2981 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 2982 [GCC_PCIE_0_PIPE_DIV2_CLK] = &gcc_pcie_0_pipe_div2_clk.clkr, 2983 [GCC_PCIE_0_PIPE_DIV2_CLK_SRC] = &gcc_pcie_0_pipe_div2_clk_src.clkr, 2984 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 2985 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 2986 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 2987 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 2988 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 2989 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 2990 [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr, 2991 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, 2992 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 2993 [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr, 2994 [GCC_PCIE_1_PIPE_DIV2_CLK] = &gcc_pcie_1_pipe_div2_clk.clkr, 2995 [GCC_PCIE_1_PIPE_DIV2_CLK_SRC] = &gcc_pcie_1_pipe_div2_clk_src.clkr, 2996 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 2997 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 2998 [GCC_PCIE_RSCC_CFG_AHB_CLK] = &gcc_pcie_rscc_cfg_ahb_clk.clkr, 2999 [GCC_PCIE_RSCC_XO_CLK] = &gcc_pcie_rscc_xo_clk.clkr, 3000 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3001 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3002 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3003 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3004 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3005 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3006 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3007 [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr, 3008 [GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr, 3009 [GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr, 3010 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 3011 [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr, 3012 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3013 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 3014 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 3015 [GCC_QUPV3_WRAP0_QSPI_REF_CLK] = &gcc_qupv3_wrap0_qspi_ref_clk.clkr, 3016 [GCC_QUPV3_WRAP0_QSPI_REF_CLK_SRC] = &gcc_qupv3_wrap0_qspi_ref_clk_src.clkr, 3017 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3018 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3019 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3020 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3021 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3022 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3023 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3024 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3025 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3026 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3027 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3028 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3029 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 3030 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 3031 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 3032 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 3033 [GCC_QUPV3_WRAP1_QSPI_REF_CLK] = &gcc_qupv3_wrap1_qspi_ref_clk.clkr, 3034 [GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC] = &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr, 3035 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3036 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3037 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3038 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3039 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3040 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3041 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3042 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3043 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3044 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3045 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3046 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3047 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 3048 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 3049 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3050 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3051 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 3052 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3053 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 3054 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 3055 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 3056 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 3057 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 3058 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3059 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3060 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3061 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3062 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3063 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3064 [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr, 3065 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3066 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3067 [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr, 3068 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3069 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3070 [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, 3071 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3072 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr, 3073 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 3074 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr, 3075 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3076 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr, 3077 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3078 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 3079 [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr, 3080 [GCC_USB30_PRIM_ATB_CLK] = &gcc_usb30_prim_atb_clk.clkr, 3081 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3082 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3083 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3084 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3085 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3086 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3087 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 3088 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3089 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3090 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3091 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 3092 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3093 }; 3094 3095 static const struct qcom_reset_map gcc_milos_resets[] = { 3096 [GCC_CAMERA_BCR] = { 0x26000 }, 3097 [GCC_DISPLAY_BCR] = { 0x27000 }, 3098 [GCC_GPU_BCR] = { 0x71000 }, 3099 [GCC_PCIE_0_BCR] = { 0x6b000 }, 3100 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, 3101 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, 3102 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 3103 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 }, 3104 [GCC_PCIE_1_BCR] = { 0x90000 }, 3105 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 }, 3106 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 }, 3107 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, 3108 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 }, 3109 [GCC_PCIE_RSCC_BCR] = { 0x11000 }, 3110 [GCC_PDM_BCR] = { 0x33000 }, 3111 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x18000 }, 3112 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x1e000 }, 3113 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 3114 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 3115 [GCC_SDCC1_BCR] = { 0xa3000 }, 3116 [GCC_SDCC2_BCR] = { 0x14000 }, 3117 [GCC_UFS_PHY_BCR] = { 0x77000 }, 3118 [GCC_USB30_PRIM_BCR] = { 0x39000 }, 3119 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 3120 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 3121 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 3122 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 }, 3123 [GCC_VIDEO_BCR] = { 0x32000 }, 3124 }; 3125 3126 static const struct clk_rcg_dfs_data gcc_milos_dfs_clocks[] = { 3127 DEFINE_RCG_DFS(gcc_qupv3_wrap0_qspi_ref_clk_src), 3128 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 3129 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 3130 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 3131 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 3132 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 3133 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 3134 DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_ref_clk_src), 3135 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3136 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3137 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3138 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3139 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3140 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 3141 }; 3142 3143 static struct gdsc *gcc_milos_gdscs[] = { 3144 [PCIE_0_GDSC] = &pcie_0_gdsc, 3145 [PCIE_0_PHY_GDSC] = &pcie_0_phy_gdsc, 3146 [PCIE_1_GDSC] = &pcie_1_gdsc, 3147 [PCIE_1_PHY_GDSC] = &pcie_1_phy_gdsc, 3148 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 3149 [UFS_MEM_PHY_GDSC] = &ufs_mem_phy_gdsc, 3150 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 3151 [USB3_PHY_GDSC] = &usb3_phy_gdsc, 3152 }; 3153 3154 static const u32 gcc_milos_critical_cbcrs[] = { 3155 0x26004, /* GCC_CAMERA_AHB_CLK */ 3156 0x26018, /* GCC_CAMERA_HF_XO_CLK */ 3157 0x2601c, /* GCC_CAMERA_SF_XO_CLK */ 3158 0x27004, /* GCC_DISP_AHB_CLK */ 3159 0x27018, /* GCC_DISP_XO_CLK */ 3160 0x71004, /* GCC_GPU_CFG_AHB_CLK */ 3161 0x32004, /* GCC_VIDEO_AHB_CLK */ 3162 0x32024, /* GCC_VIDEO_XO_CLK */ 3163 }; 3164 3165 static const struct regmap_config gcc_milos_regmap_config = { 3166 .reg_bits = 32, 3167 .reg_stride = 4, 3168 .val_bits = 32, 3169 .max_register = 0x1f41f0, 3170 .fast_io = true, 3171 }; 3172 3173 static const struct qcom_cc_driver_data gcc_milos_driver_data = { 3174 .clk_cbcrs = gcc_milos_critical_cbcrs, 3175 .num_clk_cbcrs = ARRAY_SIZE(gcc_milos_critical_cbcrs), 3176 .dfs_rcgs = gcc_milos_dfs_clocks, 3177 .num_dfs_rcgs = ARRAY_SIZE(gcc_milos_dfs_clocks), 3178 }; 3179 3180 static const struct qcom_cc_desc gcc_milos_desc = { 3181 .config = &gcc_milos_regmap_config, 3182 .clks = gcc_milos_clocks, 3183 .num_clks = ARRAY_SIZE(gcc_milos_clocks), 3184 .resets = gcc_milos_resets, 3185 .num_resets = ARRAY_SIZE(gcc_milos_resets), 3186 .gdscs = gcc_milos_gdscs, 3187 .num_gdscs = ARRAY_SIZE(gcc_milos_gdscs), 3188 .use_rpm = true, 3189 .driver_data = &gcc_milos_driver_data, 3190 }; 3191 3192 static const struct of_device_id gcc_milos_match_table[] = { 3193 { .compatible = "qcom,milos-gcc" }, 3194 { } 3195 }; 3196 MODULE_DEVICE_TABLE(of, gcc_milos_match_table); 3197 3198 static int gcc_milos_probe(struct platform_device *pdev) 3199 { 3200 return qcom_cc_probe(pdev, &gcc_milos_desc); 3201 } 3202 3203 static struct platform_driver gcc_milos_driver = { 3204 .probe = gcc_milos_probe, 3205 .driver = { 3206 .name = "gcc-milos", 3207 .of_match_table = gcc_milos_match_table, 3208 }, 3209 }; 3210 3211 static int __init gcc_milos_init(void) 3212 { 3213 return platform_driver_register(&gcc_milos_driver); 3214 } 3215 subsys_initcall(gcc_milos_init); 3216 3217 static void __exit gcc_milos_exit(void) 3218 { 3219 platform_driver_unregister(&gcc_milos_driver); 3220 } 3221 module_exit(gcc_milos_exit); 3222 3223 MODULE_DESCRIPTION("QTI GCC Milos Driver"); 3224 MODULE_LICENSE("GPL"); 3225