1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/bitops.h> 8 #include <linux/err.h> 9 #include <linux/platform_device.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/clk-provider.h> 13 #include <linux/regmap.h> 14 #include <linux/reset-controller.h> 15 16 #include <dt-bindings/clock/qcom,gcc-mdm9607.h> 17 18 #include "common.h" 19 #include "clk-regmap.h" 20 #include "clk-alpha-pll.h" 21 #include "clk-pll.h" 22 #include "clk-rcg.h" 23 #include "clk-branch.h" 24 #include "reset.h" 25 #include "gdsc.h" 26 27 enum { 28 P_XO, 29 P_GPLL0, 30 P_GPLL1, 31 P_GPLL2, 32 P_SLEEP_CLK, 33 }; 34 35 static struct clk_alpha_pll gpll0_early = { 36 .offset = 0x21000, 37 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 38 .clkr = { 39 .enable_reg = 0x45000, 40 .enable_mask = BIT(0), 41 .hw.init = &(struct clk_init_data) 42 { 43 .name = "gpll0_early", 44 .parent_data = &(const struct clk_parent_data){ 45 .fw_name = "xo", 46 }, 47 .num_parents = 1, 48 .ops = &clk_alpha_pll_ops, 49 }, 50 }, 51 }; 52 53 static struct clk_alpha_pll_postdiv gpll0 = { 54 .offset = 0x21000, 55 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 56 .clkr.hw.init = &(struct clk_init_data) 57 { 58 .name = "gpll0", 59 .parent_hws = (const struct clk_hw *[]){ &gpll0_early.clkr.hw }, 60 .num_parents = 1, 61 .ops = &clk_alpha_pll_postdiv_ops, 62 }, 63 }; 64 65 static const struct parent_map gcc_xo_gpll0_map[] = { 66 { P_XO, 0 }, 67 { P_GPLL0, 1 }, 68 }; 69 70 static const struct clk_parent_data gcc_xo_gpll0[] = { 71 { .fw_name = "xo" }, 72 { .hw = &gpll0.clkr.hw }, 73 }; 74 75 static struct clk_pll gpll1 = { 76 .l_reg = 0x20004, 77 .m_reg = 0x20008, 78 .n_reg = 0x2000c, 79 .config_reg = 0x20010, 80 .mode_reg = 0x20000, 81 .status_reg = 0x2001c, 82 .status_bit = 17, 83 .clkr.hw.init = &(struct clk_init_data){ 84 .name = "gpll1", 85 .parent_data = &(const struct clk_parent_data){ 86 .fw_name = "xo", 87 }, 88 .num_parents = 1, 89 .ops = &clk_pll_ops, 90 }, 91 }; 92 93 static struct clk_regmap gpll1_vote = { 94 .enable_reg = 0x45000, 95 .enable_mask = BIT(1), 96 .hw.init = &(struct clk_init_data){ 97 .name = "gpll1_vote", 98 .parent_hws = (const struct clk_hw *[]){ &gpll1.clkr.hw }, 99 .num_parents = 1, 100 .ops = &clk_pll_vote_ops, 101 }, 102 }; 103 104 static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = { 105 { P_XO, 0 }, 106 { P_GPLL0, 1 }, 107 { P_GPLL1, 2 }, 108 { P_SLEEP_CLK, 6 }, 109 }; 110 111 static const struct clk_parent_data gcc_xo_gpll0_gpll1_sleep[] = { 112 { .fw_name = "xo" }, 113 { .hw = &gpll0.clkr.hw }, 114 { .hw = &gpll1_vote.hw }, 115 { .fw_name = "sleep_clk" }, 116 }; 117 118 static struct clk_alpha_pll gpll2_early = { 119 .offset = 0x25000, 120 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 121 .clkr = { 122 .enable_reg = 0x45000, 123 .enable_mask = BIT(3), /* BIT(2) is used for BIMC PLL */ 124 .hw.init = &(struct clk_init_data) 125 { 126 .name = "gpll2_early", 127 .parent_data = &(const struct clk_parent_data){ 128 .fw_name = "xo", 129 }, 130 .num_parents = 1, 131 .ops = &clk_alpha_pll_ops, 132 }, 133 }, 134 }; 135 136 static struct clk_alpha_pll_postdiv gpll2 = { 137 .offset = 0x25000, 138 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 139 .clkr.hw.init = &(struct clk_init_data) 140 { 141 .name = "gpll2", 142 .parent_hws = (const struct clk_hw *[]){ &gpll2_early.clkr.hw }, 143 .num_parents = 1, 144 .ops = &clk_alpha_pll_postdiv_ops, 145 }, 146 }; 147 148 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = { 149 { P_XO, 0 }, 150 { P_GPLL0, 1 }, 151 { P_GPLL2, 2 }, 152 }; 153 154 static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = { 155 { .fw_name = "xo" }, 156 { .hw = &gpll0.clkr.hw }, 157 { .hw = &gpll2.clkr.hw }, 158 }; 159 160 static const struct freq_tbl ftbl_apss_ahb_clk[] = { 161 F(19200000, P_XO, 1, 0, 0), 162 F(50000000, P_GPLL0, 16, 0, 0), 163 F(100000000, P_GPLL0, 8, 0, 0), 164 { } 165 }; 166 167 static struct clk_rcg2 apss_ahb_clk_src = { 168 .cmd_rcgr = 0x46000, 169 .hid_width = 5, 170 .parent_map = gcc_xo_gpll0_map, 171 .freq_tbl = ftbl_apss_ahb_clk, 172 .clkr.hw.init = &(struct clk_init_data){ 173 .name = "apss_ahb_clk_src", 174 .parent_data = gcc_xo_gpll0, 175 .num_parents = 2, 176 .ops = &clk_rcg2_ops, 177 }, 178 }; 179 180 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = { 181 F(19200000, P_XO, 1, 0, 0), 182 F(50000000, P_GPLL0, 16, 0, 0), 183 { } 184 }; 185 186 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 187 .cmd_rcgr = 0x200c, 188 .hid_width = 5, 189 .parent_map = gcc_xo_gpll0_map, 190 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 191 .clkr.hw.init = &(struct clk_init_data){ 192 .name = "blsp1_qup1_i2c_apps_clk_src", 193 .parent_data = gcc_xo_gpll0, 194 .num_parents = 2, 195 .ops = &clk_rcg2_ops, 196 }, 197 }; 198 199 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = { 200 F(960000, P_XO, 10, 1, 2), 201 F(4800000, P_XO, 4, 0, 0), 202 F(9600000, P_XO, 2, 0, 0), 203 F(16000000, P_GPLL0, 10, 1, 5), 204 F(19200000, P_XO, 1, 0, 0), 205 F(25000000, P_GPLL0, 16, 1, 2), 206 F(50000000, P_GPLL0, 16, 0, 0), 207 { } 208 }; 209 210 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 211 .cmd_rcgr = 0x2024, 212 .mnd_width = 8, 213 .hid_width = 5, 214 .parent_map = gcc_xo_gpll0_map, 215 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 216 .clkr.hw.init = &(struct clk_init_data){ 217 .name = "blsp1_qup1_spi_apps_clk_src", 218 .parent_data = gcc_xo_gpll0, 219 .num_parents = 2, 220 .ops = &clk_rcg2_ops, 221 }, 222 }; 223 224 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 225 .cmd_rcgr = 0x3000, 226 .hid_width = 5, 227 .parent_map = gcc_xo_gpll0_map, 228 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 229 .clkr.hw.init = &(struct clk_init_data){ 230 .name = "blsp1_qup2_i2c_apps_clk_src", 231 .parent_data = gcc_xo_gpll0, 232 .num_parents = 2, 233 .ops = &clk_rcg2_ops, 234 }, 235 }; 236 237 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 238 .cmd_rcgr = 0x3014, 239 .mnd_width = 8, 240 .hid_width = 5, 241 .parent_map = gcc_xo_gpll0_map, 242 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 243 .clkr.hw.init = &(struct clk_init_data){ 244 .name = "blsp1_qup2_spi_apps_clk_src", 245 .parent_data = gcc_xo_gpll0, 246 .num_parents = 2, 247 .ops = &clk_rcg2_ops, 248 }, 249 }; 250 251 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 252 .cmd_rcgr = 0x4000, 253 .hid_width = 5, 254 .parent_map = gcc_xo_gpll0_map, 255 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 256 .clkr.hw.init = &(struct clk_init_data){ 257 .name = "blsp1_qup3_i2c_apps_clk_src", 258 .parent_data = gcc_xo_gpll0, 259 .num_parents = 2, 260 .ops = &clk_rcg2_ops, 261 }, 262 }; 263 264 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 265 .cmd_rcgr = 0x4024, 266 .mnd_width = 8, 267 .hid_width = 5, 268 .parent_map = gcc_xo_gpll0_map, 269 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 270 .clkr.hw.init = &(struct clk_init_data){ 271 .name = "blsp1_qup3_spi_apps_clk_src", 272 .parent_data = gcc_xo_gpll0, 273 .num_parents = 2, 274 .ops = &clk_rcg2_ops, 275 }, 276 }; 277 278 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 279 .cmd_rcgr = 0x5000, 280 .hid_width = 5, 281 .parent_map = gcc_xo_gpll0_map, 282 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 283 .clkr.hw.init = &(struct clk_init_data){ 284 .name = "blsp1_qup4_i2c_apps_clk_src", 285 .parent_data = gcc_xo_gpll0, 286 .num_parents = 2, 287 .ops = &clk_rcg2_ops, 288 }, 289 }; 290 291 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 292 .cmd_rcgr = 0x5024, 293 .mnd_width = 8, 294 .hid_width = 5, 295 .parent_map = gcc_xo_gpll0_map, 296 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 297 .clkr.hw.init = &(struct clk_init_data){ 298 .name = "blsp1_qup4_spi_apps_clk_src", 299 .parent_data = gcc_xo_gpll0, 300 .num_parents = 2, 301 .ops = &clk_rcg2_ops, 302 }, 303 }; 304 305 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 306 .cmd_rcgr = 0x6000, 307 .hid_width = 5, 308 .parent_map = gcc_xo_gpll0_map, 309 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 310 .clkr.hw.init = &(struct clk_init_data){ 311 .name = "blsp1_qup5_i2c_apps_clk_src", 312 .parent_data = gcc_xo_gpll0, 313 .num_parents = 2, 314 .ops = &clk_rcg2_ops, 315 }, 316 }; 317 318 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 319 .cmd_rcgr = 0x6024, 320 .mnd_width = 8, 321 .hid_width = 5, 322 .parent_map = gcc_xo_gpll0_map, 323 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 324 .clkr.hw.init = &(struct clk_init_data){ 325 .name = "blsp1_qup5_spi_apps_clk_src", 326 .parent_data = gcc_xo_gpll0, 327 .num_parents = 2, 328 .ops = &clk_rcg2_ops, 329 }, 330 }; 331 332 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 333 .cmd_rcgr = 0x7000, 334 .hid_width = 5, 335 .parent_map = gcc_xo_gpll0_map, 336 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 337 .clkr.hw.init = &(struct clk_init_data){ 338 .name = "blsp1_qup6_i2c_apps_clk_src", 339 .parent_data = gcc_xo_gpll0, 340 .num_parents = 2, 341 .ops = &clk_rcg2_ops, 342 }, 343 }; 344 345 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 346 .cmd_rcgr = 0x7024, 347 .mnd_width = 8, 348 .hid_width = 5, 349 .parent_map = gcc_xo_gpll0_map, 350 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 351 .clkr.hw.init = &(struct clk_init_data){ 352 .name = "blsp1_qup6_spi_apps_clk_src", 353 .parent_data = gcc_xo_gpll0, 354 .num_parents = 2, 355 .ops = &clk_rcg2_ops, 356 }, 357 }; 358 359 static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = { 360 F(3686400, P_GPLL0, 1, 72, 15625), 361 F(7372800, P_GPLL0, 1, 144, 15625), 362 F(14745600, P_GPLL0, 1, 288, 15625), 363 F(16000000, P_GPLL0, 10, 1, 5), 364 F(19200000, P_XO, 1, 0, 0), 365 F(24000000, P_GPLL0, 1, 3, 100), 366 F(25000000, P_GPLL0, 16, 1, 2), 367 F(32000000, P_GPLL0, 1, 1, 25), 368 F(40000000, P_GPLL0, 1, 1, 20), 369 F(46400000, P_GPLL0, 1, 29, 500), 370 F(48000000, P_GPLL0, 1, 3, 50), 371 F(51200000, P_GPLL0, 1, 8, 125), 372 F(56000000, P_GPLL0, 1, 7, 100), 373 F(58982400, P_GPLL0, 1, 1152, 15625), 374 F(60000000, P_GPLL0, 1, 3, 40), 375 { } 376 }; 377 378 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 379 .cmd_rcgr = 0x2044, 380 .mnd_width = 16, 381 .hid_width = 5, 382 .parent_map = gcc_xo_gpll0_map, 383 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, 384 .clkr.hw.init = &(struct clk_init_data){ 385 .name = "blsp1_uart1_apps_clk_src", 386 .parent_data = gcc_xo_gpll0, 387 .num_parents = 2, 388 .ops = &clk_rcg2_ops, 389 }, 390 }; 391 392 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 393 .cmd_rcgr = 0x3034, 394 .mnd_width = 16, 395 .hid_width = 5, 396 .parent_map = gcc_xo_gpll0_map, 397 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, 398 .clkr.hw.init = &(struct clk_init_data){ 399 .name = "blsp1_uart2_apps_clk_src", 400 .parent_data = gcc_xo_gpll0, 401 .num_parents = 2, 402 .ops = &clk_rcg2_ops, 403 }, 404 }; 405 406 static struct clk_rcg2 blsp1_uart3_apps_clk_src = { 407 .cmd_rcgr = 0x4044, 408 .mnd_width = 16, 409 .hid_width = 5, 410 .parent_map = gcc_xo_gpll0_map, 411 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, 412 .clkr.hw.init = &(struct clk_init_data){ 413 .name = "blsp1_uart3_apps_clk_src", 414 .parent_data = gcc_xo_gpll0, 415 .num_parents = 2, 416 .ops = &clk_rcg2_ops, 417 }, 418 }; 419 420 static struct clk_rcg2 blsp1_uart4_apps_clk_src = { 421 .cmd_rcgr = 0x5044, 422 .mnd_width = 16, 423 .hid_width = 5, 424 .parent_map = gcc_xo_gpll0_map, 425 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, 426 .clkr.hw.init = &(struct clk_init_data){ 427 .name = "blsp1_uart4_apps_clk_src", 428 .parent_data = gcc_xo_gpll0, 429 .num_parents = 2, 430 .ops = &clk_rcg2_ops, 431 }, 432 }; 433 434 static struct clk_rcg2 blsp1_uart5_apps_clk_src = { 435 .cmd_rcgr = 0x6044, 436 .mnd_width = 16, 437 .hid_width = 5, 438 .parent_map = gcc_xo_gpll0_map, 439 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, 440 .clkr.hw.init = &(struct clk_init_data){ 441 .name = "blsp1_uart5_apps_clk_src", 442 .parent_data = gcc_xo_gpll0, 443 .num_parents = 2, 444 .ops = &clk_rcg2_ops, 445 }, 446 }; 447 448 static struct clk_rcg2 blsp1_uart6_apps_clk_src = { 449 .cmd_rcgr = 0x7044, 450 .mnd_width = 16, 451 .hid_width = 5, 452 .parent_map = gcc_xo_gpll0_map, 453 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, 454 .clkr.hw.init = &(struct clk_init_data){ 455 .name = "blsp1_uart6_apps_clk_src", 456 .parent_data = gcc_xo_gpll0, 457 .num_parents = 2, 458 .ops = &clk_rcg2_ops, 459 }, 460 }; 461 462 static const struct freq_tbl ftbl_gcc_crypto_clk[] = { 463 F(50000000, P_GPLL0, 16, 0, 0), 464 F(80000000, P_GPLL0, 10, 0, 0), 465 F(100000000, P_GPLL0, 8, 0, 0), 466 F(160000000, P_GPLL0, 5, 0, 0), 467 { } 468 }; 469 470 static struct clk_rcg2 crypto_clk_src = { 471 .cmd_rcgr = 0x16004, 472 .hid_width = 5, 473 .parent_map = gcc_xo_gpll0_map, 474 .freq_tbl = ftbl_gcc_crypto_clk, 475 .clkr.hw.init = &(struct clk_init_data){ 476 .name = "crypto_clk_src", 477 .parent_data = gcc_xo_gpll0, 478 .num_parents = 2, 479 .ops = &clk_rcg2_ops, 480 }, 481 }; 482 483 static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = { 484 F(19200000, P_XO, 1, 0, 0), 485 { } 486 }; 487 488 static struct clk_rcg2 gp1_clk_src = { 489 .cmd_rcgr = 0x8004, 490 .mnd_width = 8, 491 .hid_width = 5, 492 .parent_map = gcc_xo_gpll0_gpll1_sleep_map, 493 .freq_tbl = ftbl_gcc_gp1_3_clk, 494 .clkr.hw.init = &(struct clk_init_data){ 495 .name = "gp1_clk_src", 496 .parent_data = gcc_xo_gpll0_gpll1_sleep, 497 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep), 498 .ops = &clk_rcg2_ops, 499 }, 500 }; 501 502 static struct clk_rcg2 gp2_clk_src = { 503 .cmd_rcgr = 0x09004, 504 .mnd_width = 8, 505 .hid_width = 5, 506 .parent_map = gcc_xo_gpll0_gpll1_sleep_map, 507 .freq_tbl = ftbl_gcc_gp1_3_clk, 508 .clkr.hw.init = &(struct clk_init_data){ 509 .name = "gp2_clk_src", 510 .parent_data = gcc_xo_gpll0_gpll1_sleep, 511 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep), 512 .ops = &clk_rcg2_ops, 513 }, 514 }; 515 516 static struct clk_rcg2 gp3_clk_src = { 517 .cmd_rcgr = 0x0a004, 518 .mnd_width = 8, 519 .hid_width = 5, 520 .parent_map = gcc_xo_gpll0_gpll1_sleep_map, 521 .freq_tbl = ftbl_gcc_gp1_3_clk, 522 .clkr.hw.init = &(struct clk_init_data){ 523 .name = "gp3_clk_src", 524 .parent_data = gcc_xo_gpll0_gpll1_sleep, 525 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep), 526 .ops = &clk_rcg2_ops, 527 }, 528 }; 529 530 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = { 531 F(64000000, P_GPLL0, 12.5, 0, 0), 532 { } 533 }; 534 535 static struct clk_rcg2 pdm2_clk_src = { 536 .cmd_rcgr = 0x44010, 537 .hid_width = 5, 538 .parent_map = gcc_xo_gpll0_map, 539 .freq_tbl = ftbl_gcc_pdm2_clk, 540 .clkr.hw.init = &(struct clk_init_data){ 541 .name = "pdm2_clk_src", 542 .parent_data = gcc_xo_gpll0, 543 .num_parents = 2, 544 .ops = &clk_rcg2_ops, 545 }, 546 }; 547 548 static const struct freq_tbl ftbl_gcc_sdcc_apps_clk[] = { 549 F(144000, P_XO, 16, 3, 25), 550 F(400000, P_XO, 12, 1, 4), 551 F(20000000, P_GPLL0, 10, 1, 4), 552 F(25000000, P_GPLL0, 16, 1, 2), 553 F(50000000, P_GPLL0, 16, 0, 0), 554 F(100000000, P_GPLL0, 8, 0, 0), 555 F(177770000, P_GPLL0, 4.5, 0, 0), 556 F(200000000, P_GPLL0, 4, 0, 0), 557 { } 558 }; 559 560 static struct clk_rcg2 sdcc1_apps_clk_src = { 561 .cmd_rcgr = 0x42004, 562 .mnd_width = 8, 563 .hid_width = 5, 564 .parent_map = gcc_xo_gpll0_map, 565 .freq_tbl = ftbl_gcc_sdcc_apps_clk, 566 .clkr.hw.init = &(struct clk_init_data){ 567 .name = "sdcc1_apps_clk_src", 568 .parent_data = gcc_xo_gpll0, 569 .num_parents = 2, 570 .ops = &clk_rcg2_floor_ops, 571 }, 572 }; 573 574 static struct clk_rcg2 sdcc2_apps_clk_src = { 575 .cmd_rcgr = 0x43004, 576 .mnd_width = 8, 577 .hid_width = 5, 578 .parent_map = gcc_xo_gpll0_map, 579 .freq_tbl = ftbl_gcc_sdcc_apps_clk, 580 .clkr.hw.init = &(struct clk_init_data){ 581 .name = "sdcc2_apps_clk_src", 582 .parent_data = gcc_xo_gpll0, 583 .num_parents = 2, 584 .ops = &clk_rcg2_floor_ops, 585 }, 586 }; 587 588 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { 589 F(19200000, P_XO, 1, 0, 0), 590 F(57140000, P_GPLL0, 14, 0, 0), 591 F(69565000, P_GPLL0, 11.5, 0, 0), 592 F(133330000, P_GPLL0, 6, 0, 0), 593 F(177778000, P_GPLL0, 4.5, 0, 0), 594 { } 595 }; 596 597 static struct clk_rcg2 usb_hs_system_clk_src = { 598 .cmd_rcgr = 0x41010, 599 .hid_width = 5, 600 .parent_map = gcc_xo_gpll0_map, 601 .freq_tbl = ftbl_gcc_usb_hs_system_clk, 602 .clkr.hw.init = &(struct clk_init_data){ 603 .name = "usb_hs_system_clk_src", 604 .parent_data = gcc_xo_gpll0, 605 .num_parents = 2, 606 .ops = &clk_rcg2_ops, 607 }, 608 }; 609 610 static const struct freq_tbl ftbl_usb_hsic_clk_src[] = { 611 F(480000000, P_GPLL2, 1, 0, 0), 612 { } 613 }; 614 615 static struct clk_rcg2 usb_hsic_clk_src = { 616 .cmd_rcgr = 0x3d018, 617 .hid_width = 5, 618 .parent_map = gcc_xo_gpll0_gpll2_map, 619 .freq_tbl = ftbl_usb_hsic_clk_src, 620 .clkr.hw.init = &(struct clk_init_data){ 621 .name = "usb_hsic_clk_src", 622 .parent_data = gcc_xo_gpll0_gpll2, 623 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2), 624 .ops = &clk_rcg2_ops, 625 }, 626 }; 627 628 static const struct freq_tbl ftbl_usb_hsic_io_cal_clk_src[] = { 629 F(9600000, P_XO, 2, 0, 0), 630 { } 631 }; 632 633 static struct clk_rcg2 usb_hsic_io_cal_clk_src = { 634 .cmd_rcgr = 0x3d030, 635 .hid_width = 5, 636 .parent_map = gcc_xo_gpll0_map, 637 .freq_tbl = ftbl_usb_hsic_io_cal_clk_src, 638 .clkr.hw.init = &(struct clk_init_data){ 639 .name = "usb_hsic_io_cal_clk_src", 640 .parent_data = gcc_xo_gpll0, 641 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 642 .ops = &clk_rcg2_ops, 643 }, 644 }; 645 646 static const struct freq_tbl ftbl_usb_hsic_system_clk_src[] = { 647 F(19200000, P_XO, 1, 0, 0), 648 F(57140000, P_GPLL0, 14, 0, 0), 649 F(133330000, P_GPLL0, 6, 0, 0), 650 F(177778000, P_GPLL0, 4.5, 0, 0), 651 { } 652 }; 653 654 static struct clk_rcg2 usb_hsic_system_clk_src = { 655 .cmd_rcgr = 0x3d000, 656 .hid_width = 5, 657 .parent_map = gcc_xo_gpll0_map, 658 .freq_tbl = ftbl_usb_hsic_system_clk_src, 659 .clkr.hw.init = &(struct clk_init_data){ 660 .name = "usb_hsic_system_clk_src", 661 .parent_data = gcc_xo_gpll0, 662 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 663 .ops = &clk_rcg2_ops, 664 }, 665 }; 666 667 static struct clk_branch gcc_blsp1_ahb_clk = { 668 .halt_reg = 0x1008, 669 .halt_check = BRANCH_HALT_VOTED, 670 .clkr = { 671 .enable_reg = 0x45004, 672 .enable_mask = BIT(10), 673 .hw.init = &(struct clk_init_data){ 674 .name = "gcc_blsp1_ahb_clk", 675 .ops = &clk_branch2_ops, 676 }, 677 }, 678 }; 679 680 static struct clk_branch gcc_blsp1_sleep_clk = { 681 .halt_reg = 0x1004, 682 .halt_check = BRANCH_HALT_VOTED, 683 .clkr = { 684 .enable_reg = 0x45004, 685 .enable_mask = BIT(9), 686 .hw.init = &(struct clk_init_data){ 687 .name = "gcc_blsp1_sleep_clk", 688 .parent_data = &(const struct clk_parent_data){ 689 .fw_name = "sleep_clk", 690 }, 691 .num_parents = 1, 692 .flags = CLK_SET_RATE_PARENT, 693 .ops = &clk_branch2_ops, 694 }, 695 }, 696 }; 697 698 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 699 .halt_reg = 0x2008, 700 .clkr = { 701 .enable_reg = 0x2008, 702 .enable_mask = BIT(0), 703 .hw.init = &(struct clk_init_data){ 704 .name = "gcc_blsp1_qup1_i2c_apps_clk", 705 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_i2c_apps_clk_src.clkr.hw }, 706 .num_parents = 1, 707 .flags = CLK_SET_RATE_PARENT, 708 .ops = &clk_branch2_ops, 709 }, 710 }, 711 }; 712 713 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 714 .halt_reg = 0x2004, 715 .clkr = { 716 .enable_reg = 0x2004, 717 .enable_mask = BIT(0), 718 .hw.init = &(struct clk_init_data){ 719 .name = "gcc_blsp1_qup1_spi_apps_clk", 720 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_spi_apps_clk_src.clkr.hw }, 721 .num_parents = 1, 722 .flags = CLK_SET_RATE_PARENT, 723 .ops = &clk_branch2_ops, 724 }, 725 }, 726 }; 727 728 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 729 .halt_reg = 0x3010, 730 .clkr = { 731 .enable_reg = 0x3010, 732 .enable_mask = BIT(0), 733 .hw.init = &(struct clk_init_data){ 734 .name = "gcc_blsp1_qup2_i2c_apps_clk", 735 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_i2c_apps_clk_src.clkr.hw }, 736 .num_parents = 1, 737 .flags = CLK_SET_RATE_PARENT, 738 .ops = &clk_branch2_ops, 739 }, 740 }, 741 }; 742 743 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 744 .halt_reg = 0x300c, 745 .clkr = { 746 .enable_reg = 0x300c, 747 .enable_mask = BIT(0), 748 .hw.init = &(struct clk_init_data){ 749 .name = "gcc_blsp1_qup2_spi_apps_clk", 750 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_spi_apps_clk_src.clkr.hw }, 751 .num_parents = 1, 752 .flags = CLK_SET_RATE_PARENT, 753 .ops = &clk_branch2_ops, 754 }, 755 }, 756 }; 757 758 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 759 .halt_reg = 0x4020, 760 .clkr = { 761 .enable_reg = 0x4020, 762 .enable_mask = BIT(0), 763 .hw.init = &(struct clk_init_data){ 764 .name = "gcc_blsp1_qup3_i2c_apps_clk", 765 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_i2c_apps_clk_src.clkr.hw }, 766 .num_parents = 1, 767 .flags = CLK_SET_RATE_PARENT, 768 .ops = &clk_branch2_ops, 769 }, 770 }, 771 }; 772 773 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 774 .halt_reg = 0x401c, 775 .clkr = { 776 .enable_reg = 0x401c, 777 .enable_mask = BIT(0), 778 .hw.init = &(struct clk_init_data){ 779 .name = "gcc_blsp1_qup3_spi_apps_clk", 780 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_spi_apps_clk_src.clkr.hw }, 781 .num_parents = 1, 782 .flags = CLK_SET_RATE_PARENT, 783 .ops = &clk_branch2_ops, 784 }, 785 }, 786 }; 787 788 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 789 .halt_reg = 0x5020, 790 .clkr = { 791 .enable_reg = 0x5020, 792 .enable_mask = BIT(0), 793 .hw.init = &(struct clk_init_data){ 794 .name = "gcc_blsp1_qup4_i2c_apps_clk", 795 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_i2c_apps_clk_src.clkr.hw }, 796 .num_parents = 1, 797 .flags = CLK_SET_RATE_PARENT, 798 .ops = &clk_branch2_ops, 799 }, 800 }, 801 }; 802 803 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 804 .halt_reg = 0x501c, 805 .clkr = { 806 .enable_reg = 0x501c, 807 .enable_mask = BIT(0), 808 .hw.init = &(struct clk_init_data){ 809 .name = "gcc_blsp1_qup4_spi_apps_clk", 810 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_spi_apps_clk_src.clkr.hw }, 811 .num_parents = 1, 812 .flags = CLK_SET_RATE_PARENT, 813 .ops = &clk_branch2_ops, 814 }, 815 }, 816 }; 817 818 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 819 .halt_reg = 0x6020, 820 .clkr = { 821 .enable_reg = 0x6020, 822 .enable_mask = BIT(0), 823 .hw.init = &(struct clk_init_data){ 824 .name = "gcc_blsp1_qup5_i2c_apps_clk", 825 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_i2c_apps_clk_src.clkr.hw }, 826 .num_parents = 1, 827 .flags = CLK_SET_RATE_PARENT, 828 .ops = &clk_branch2_ops, 829 }, 830 }, 831 }; 832 833 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 834 .halt_reg = 0x601c, 835 .clkr = { 836 .enable_reg = 0x601c, 837 .enable_mask = BIT(0), 838 .hw.init = &(struct clk_init_data){ 839 .name = "gcc_blsp1_qup5_spi_apps_clk", 840 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_spi_apps_clk_src.clkr.hw }, 841 .num_parents = 1, 842 .flags = CLK_SET_RATE_PARENT, 843 .ops = &clk_branch2_ops, 844 }, 845 }, 846 }; 847 848 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 849 .halt_reg = 0x7020, 850 .clkr = { 851 .enable_reg = 0x7020, 852 .enable_mask = BIT(0), 853 .hw.init = &(struct clk_init_data){ 854 .name = "gcc_blsp1_qup6_i2c_apps_clk", 855 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_i2c_apps_clk_src.clkr.hw }, 856 .num_parents = 1, 857 .flags = CLK_SET_RATE_PARENT, 858 .ops = &clk_branch2_ops, 859 }, 860 }, 861 }; 862 863 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 864 .halt_reg = 0x701c, 865 .clkr = { 866 .enable_reg = 0x701c, 867 .enable_mask = BIT(0), 868 .hw.init = &(struct clk_init_data){ 869 .name = "gcc_blsp1_qup6_spi_apps_clk", 870 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_spi_apps_clk_src.clkr.hw }, 871 .num_parents = 1, 872 .flags = CLK_SET_RATE_PARENT, 873 .ops = &clk_branch2_ops, 874 }, 875 }, 876 }; 877 878 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 879 .halt_reg = 0x203c, 880 .clkr = { 881 .enable_reg = 0x203c, 882 .enable_mask = BIT(0), 883 .hw.init = &(struct clk_init_data){ 884 .name = "gcc_blsp1_uart1_apps_clk", 885 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart1_apps_clk_src.clkr.hw }, 886 .num_parents = 1, 887 .flags = CLK_SET_RATE_PARENT, 888 .ops = &clk_branch2_ops, 889 }, 890 }, 891 }; 892 893 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 894 .halt_reg = 0x302c, 895 .clkr = { 896 .enable_reg = 0x302c, 897 .enable_mask = BIT(0), 898 .hw.init = &(struct clk_init_data){ 899 .name = "gcc_blsp1_uart2_apps_clk", 900 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart2_apps_clk_src.clkr.hw }, 901 .num_parents = 1, 902 .flags = CLK_SET_RATE_PARENT, 903 .ops = &clk_branch2_ops, 904 }, 905 }, 906 }; 907 908 static struct clk_branch gcc_blsp1_uart3_apps_clk = { 909 .halt_reg = 0x403c, 910 .clkr = { 911 .enable_reg = 0x403c, 912 .enable_mask = BIT(0), 913 .hw.init = &(struct clk_init_data){ 914 .name = "gcc_blsp1_uart3_apps_clk", 915 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart3_apps_clk_src.clkr.hw }, 916 .num_parents = 1, 917 .flags = CLK_SET_RATE_PARENT, 918 .ops = &clk_branch2_ops, 919 }, 920 }, 921 }; 922 923 static struct clk_branch gcc_blsp1_uart4_apps_clk = { 924 .halt_reg = 0x503c, 925 .clkr = { 926 .enable_reg = 0x503c, 927 .enable_mask = BIT(0), 928 .hw.init = &(struct clk_init_data){ 929 .name = "gcc_blsp1_uart4_apps_clk", 930 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart4_apps_clk_src.clkr.hw }, 931 .num_parents = 1, 932 .flags = CLK_SET_RATE_PARENT, 933 .ops = &clk_branch2_ops, 934 }, 935 }, 936 }; 937 938 static struct clk_branch gcc_blsp1_uart5_apps_clk = { 939 .halt_reg = 0x603c, 940 .clkr = { 941 .enable_reg = 0x603c, 942 .enable_mask = BIT(0), 943 .hw.init = &(struct clk_init_data){ 944 .name = "gcc_blsp1_uart5_apps_clk", 945 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart5_apps_clk_src.clkr.hw }, 946 .num_parents = 1, 947 .flags = CLK_SET_RATE_PARENT, 948 .ops = &clk_branch2_ops, 949 }, 950 }, 951 }; 952 953 static struct clk_branch gcc_blsp1_uart6_apps_clk = { 954 .halt_reg = 0x703c, 955 .clkr = { 956 .enable_reg = 0x703c, 957 .enable_mask = BIT(0), 958 .hw.init = &(struct clk_init_data){ 959 .name = "gcc_blsp1_uart6_apps_clk", 960 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart6_apps_clk_src.clkr.hw }, 961 .num_parents = 1, 962 .flags = CLK_SET_RATE_PARENT, 963 .ops = &clk_branch2_ops, 964 }, 965 }, 966 }; 967 968 static struct clk_branch gcc_boot_rom_ahb_clk = { 969 .halt_reg = 0x1300c, 970 .halt_check = BRANCH_HALT_VOTED, 971 .clkr = { 972 .enable_reg = 0x45004, 973 .enable_mask = BIT(7), 974 .hw.init = &(struct clk_init_data){ 975 .name = "gcc_boot_rom_ahb_clk", 976 .ops = &clk_branch2_ops, 977 }, 978 }, 979 }; 980 981 static struct clk_branch gcc_crypto_ahb_clk = { 982 .halt_reg = 0x16024, 983 .halt_check = BRANCH_HALT_VOTED, 984 .clkr = { 985 .enable_reg = 0x45004, 986 .enable_mask = BIT(0), 987 .hw.init = &(struct clk_init_data){ 988 .name = "gcc_crypto_ahb_clk", 989 .ops = &clk_branch2_ops, 990 }, 991 }, 992 }; 993 994 static struct clk_branch gcc_crypto_axi_clk = { 995 .halt_reg = 0x16020, 996 .halt_check = BRANCH_HALT_VOTED, 997 .clkr = { 998 .enable_reg = 0x45004, 999 .enable_mask = BIT(1), 1000 .hw.init = &(struct clk_init_data){ 1001 .name = "gcc_crypto_axi_clk", 1002 .ops = &clk_branch2_ops, 1003 }, 1004 }, 1005 }; 1006 1007 static struct clk_branch gcc_crypto_clk = { 1008 .halt_reg = 0x1601c, 1009 .halt_check = BRANCH_HALT_VOTED, 1010 .clkr = { 1011 .enable_reg = 0x45004, 1012 .enable_mask = BIT(2), 1013 .hw.init = &(struct clk_init_data){ 1014 .name = "gcc_crypto_clk", 1015 .parent_hws = (const struct clk_hw *[]){ &crypto_clk_src.clkr.hw }, 1016 .num_parents = 1, 1017 .flags = CLK_SET_RATE_PARENT, 1018 .ops = &clk_branch2_ops, 1019 }, 1020 }, 1021 }; 1022 1023 static struct clk_branch gcc_gp1_clk = { 1024 .halt_reg = 0x08000, 1025 .clkr = { 1026 .enable_reg = 0x08000, 1027 .enable_mask = BIT(0), 1028 .hw.init = &(struct clk_init_data){ 1029 .name = "gcc_gp1_clk", 1030 .parent_hws = (const struct clk_hw *[]){ &gp1_clk_src.clkr.hw }, 1031 .num_parents = 1, 1032 .flags = CLK_SET_RATE_PARENT, 1033 .ops = &clk_branch2_ops, 1034 }, 1035 }, 1036 }; 1037 1038 static struct clk_branch gcc_gp2_clk = { 1039 .halt_reg = 0x09000, 1040 .clkr = { 1041 .enable_reg = 0x09000, 1042 .enable_mask = BIT(0), 1043 .hw.init = &(struct clk_init_data){ 1044 .name = "gcc_gp2_clk", 1045 .parent_hws = (const struct clk_hw *[]){ &gp2_clk_src.clkr.hw }, 1046 .num_parents = 1, 1047 .flags = CLK_SET_RATE_PARENT, 1048 .ops = &clk_branch2_ops, 1049 }, 1050 }, 1051 }; 1052 1053 static struct clk_branch gcc_gp3_clk = { 1054 .halt_reg = 0x0a000, 1055 .clkr = { 1056 .enable_reg = 0x0a000, 1057 .enable_mask = BIT(0), 1058 .hw.init = &(struct clk_init_data){ 1059 .name = "gcc_gp3_clk", 1060 .parent_hws = (const struct clk_hw *[]){ &gp3_clk_src.clkr.hw }, 1061 .num_parents = 1, 1062 .flags = CLK_SET_RATE_PARENT, 1063 .ops = &clk_branch2_ops, 1064 }, 1065 }, 1066 }; 1067 1068 static struct clk_branch gcc_mss_cfg_ahb_clk = { 1069 .halt_reg = 0x49000, 1070 .clkr = { 1071 .enable_reg = 0x49000, 1072 .enable_mask = BIT(0), 1073 .hw.init = &(struct clk_init_data){ 1074 .name = "gcc_mss_cfg_ahb_clk", 1075 .ops = &clk_branch2_ops, 1076 }, 1077 }, 1078 }; 1079 1080 static struct clk_branch gcc_pdm2_clk = { 1081 .halt_reg = 0x4400c, 1082 .clkr = { 1083 .enable_reg = 0x4400c, 1084 .enable_mask = BIT(0), 1085 .hw.init = &(struct clk_init_data){ 1086 .name = "gcc_pdm2_clk", 1087 .parent_hws = (const struct clk_hw *[]){ &pdm2_clk_src.clkr.hw }, 1088 .num_parents = 1, 1089 .flags = CLK_SET_RATE_PARENT, 1090 .ops = &clk_branch2_ops, 1091 }, 1092 }, 1093 }; 1094 1095 static struct clk_branch gcc_pdm_ahb_clk = { 1096 .halt_reg = 0x44004, 1097 .clkr = { 1098 .enable_reg = 0x44004, 1099 .enable_mask = BIT(0), 1100 .hw.init = &(struct clk_init_data){ 1101 .name = "gcc_pdm_ahb_clk", 1102 .ops = &clk_branch2_ops, 1103 }, 1104 }, 1105 }; 1106 1107 static struct clk_branch gcc_prng_ahb_clk = { 1108 .halt_reg = 0x13004, 1109 .halt_check = BRANCH_HALT_VOTED, 1110 .clkr = { 1111 .enable_reg = 0x45004, 1112 .enable_mask = BIT(8), 1113 .hw.init = &(struct clk_init_data){ 1114 .name = "gcc_prng_ahb_clk", 1115 .ops = &clk_branch2_ops, 1116 }, 1117 }, 1118 }; 1119 1120 static struct clk_branch gcc_sdcc1_ahb_clk = { 1121 .halt_reg = 0x4201c, 1122 .clkr = { 1123 .enable_reg = 0x4201c, 1124 .enable_mask = BIT(0), 1125 .hw.init = &(struct clk_init_data){ 1126 .name = "gcc_sdcc1_ahb_clk", 1127 .ops = &clk_branch2_ops, 1128 }, 1129 }, 1130 }; 1131 1132 static struct clk_branch gcc_sdcc1_apps_clk = { 1133 .halt_reg = 0x42018, 1134 .clkr = { 1135 .enable_reg = 0x42018, 1136 .enable_mask = BIT(0), 1137 .hw.init = &(struct clk_init_data){ 1138 .name = "gcc_sdcc1_apps_clk", 1139 .parent_hws = (const struct clk_hw *[]){ &sdcc1_apps_clk_src.clkr.hw }, 1140 .num_parents = 1, 1141 .flags = CLK_SET_RATE_PARENT, 1142 .ops = &clk_branch2_ops, 1143 }, 1144 }, 1145 }; 1146 1147 static struct clk_branch gcc_sdcc2_ahb_clk = { 1148 .halt_reg = 0x4301c, 1149 .clkr = { 1150 .enable_reg = 0x4301c, 1151 .enable_mask = BIT(0), 1152 .hw.init = &(struct clk_init_data){ 1153 .name = "gcc_sdcc2_ahb_clk", 1154 .ops = &clk_branch2_ops, 1155 }, 1156 }, 1157 }; 1158 1159 static struct clk_branch gcc_sdcc2_apps_clk = { 1160 .halt_reg = 0x43018, 1161 .clkr = { 1162 .enable_reg = 0x43018, 1163 .enable_mask = BIT(0), 1164 .hw.init = &(struct clk_init_data){ 1165 .name = "gcc_sdcc2_apps_clk", 1166 .parent_hws = (const struct clk_hw *[]){ &sdcc2_apps_clk_src.clkr.hw }, 1167 .num_parents = 1, 1168 .flags = CLK_SET_RATE_PARENT, 1169 .ops = &clk_branch2_ops, 1170 }, 1171 }, 1172 }; 1173 1174 static struct clk_branch gcc_mss_q6_bimc_axi_clk = { 1175 .halt_reg = 0x49004, 1176 .clkr = { 1177 .enable_reg = 0x49004, 1178 .enable_mask = BIT(0), 1179 .hw.init = &(struct clk_init_data){ 1180 .name = "gcc_mss_q6_bimc_axi_clk", 1181 .ops = &clk_branch2_ops, 1182 }, 1183 }, 1184 }; 1185 1186 static struct clk_branch gcc_apss_tcu_clk = { 1187 .halt_reg = 0x12018, 1188 .halt_check = BRANCH_HALT_VOTED, 1189 .clkr = { 1190 .enable_reg = 0x4500c, 1191 .enable_mask = BIT(1), 1192 .hw.init = &(struct clk_init_data){ 1193 .name = "gcc_apss_tcu_clk", 1194 .ops = &clk_branch2_ops, 1195 }, 1196 }, 1197 }; 1198 1199 static struct clk_branch gcc_smmu_cfg_clk = { 1200 .halt_reg = 0x12038, 1201 .halt_check = BRANCH_HALT_VOTED, 1202 .clkr = { 1203 .enable_reg = 0x4500c, 1204 .enable_mask = BIT(12), 1205 .hw.init = &(struct clk_init_data){ 1206 .name = "gcc_smmu_cfg_clk", 1207 .ops = &clk_branch2_ops, 1208 }, 1209 }, 1210 }; 1211 1212 static struct clk_branch gcc_qdss_dap_clk = { 1213 .halt_reg = 0x29084, 1214 .halt_check = BRANCH_HALT_VOTED, 1215 .clkr = { 1216 .enable_reg = 0x45004, 1217 .enable_mask = BIT(19), 1218 .hw.init = &(struct clk_init_data){ 1219 .name = "gcc_qdss_dap_clk", 1220 .parent_data = &(const struct clk_parent_data){ 1221 .fw_name = "xo", 1222 }, 1223 .num_parents = 1, 1224 .ops = &clk_branch2_ops, 1225 }, 1226 }, 1227 }; 1228 1229 static struct clk_branch gcc_usb2a_phy_sleep_clk = { 1230 .halt_reg = 0x4102c, 1231 .clkr = { 1232 .enable_reg = 0x4102c, 1233 .enable_mask = BIT(0), 1234 .hw.init = &(struct clk_init_data){ 1235 .name = "gcc_usb2a_phy_sleep_clk", 1236 .parent_data = &(const struct clk_parent_data){ 1237 .fw_name = "sleep_clk", 1238 }, 1239 .num_parents = 1, 1240 .flags = CLK_SET_RATE_PARENT, 1241 .ops = &clk_branch2_ops, 1242 }, 1243 }, 1244 }; 1245 1246 static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = { 1247 .halt_reg = 0x41030, 1248 .halt_check = BRANCH_HALT, 1249 .clkr = { 1250 .enable_reg = 0x41030, 1251 .enable_mask = BIT(0), 1252 .hw.init = &(struct clk_init_data){ 1253 .name = "gcc_usb_hs_phy_cfg_ahb_clk", 1254 .ops = &clk_branch2_ops, 1255 }, 1256 }, 1257 }; 1258 1259 static struct clk_branch gcc_usb_hs_ahb_clk = { 1260 .halt_reg = 0x41008, 1261 .clkr = { 1262 .enable_reg = 0x41008, 1263 .enable_mask = BIT(0), 1264 .hw.init = &(struct clk_init_data){ 1265 .name = "gcc_usb_hs_ahb_clk", 1266 .ops = &clk_branch2_ops, 1267 }, 1268 }, 1269 }; 1270 1271 static struct clk_branch gcc_usb_hs_system_clk = { 1272 .halt_reg = 0x41004, 1273 .clkr = { 1274 .enable_reg = 0x41004, 1275 .enable_mask = BIT(0), 1276 .hw.init = &(struct clk_init_data){ 1277 .name = "gcc_usb_hs_system_clk", 1278 .parent_hws = (const struct clk_hw *[]){ &usb_hs_system_clk_src.clkr.hw }, 1279 .num_parents = 1, 1280 .flags = CLK_SET_RATE_PARENT, 1281 .ops = &clk_branch2_ops, 1282 }, 1283 }, 1284 }; 1285 1286 static struct clk_branch gcc_apss_ahb_clk = { 1287 .halt_reg = 0x4601c, 1288 .halt_check = BRANCH_HALT_VOTED, 1289 .clkr = { 1290 .enable_reg = 0x45004, 1291 .enable_mask = BIT(14), 1292 .hw.init = &(struct clk_init_data){ 1293 .name = "gcc_apss_ahb_clk", 1294 .ops = &clk_branch2_ops, 1295 }, 1296 }, 1297 }; 1298 1299 static struct clk_branch gcc_apss_axi_clk = { 1300 .halt_reg = 0x46020, 1301 .halt_check = BRANCH_HALT_VOTED, 1302 .clkr = { 1303 .enable_reg = 0x45004, 1304 .enable_mask = BIT(13), 1305 .hw.init = &(struct clk_init_data){ 1306 .name = "gcc_apss_axi_clk", 1307 .ops = &clk_branch2_ops, 1308 }, 1309 }, 1310 }; 1311 1312 static struct clk_regmap *gcc_mdm9607_clocks[] = { 1313 [GPLL0] = &gpll0.clkr, 1314 [GPLL0_EARLY] = &gpll0_early.clkr, 1315 [GPLL1] = &gpll1.clkr, 1316 [GPLL1_VOTE] = &gpll1_vote, 1317 [GPLL2] = &gpll2.clkr, 1318 [GPLL2_EARLY] = &gpll2_early.clkr, 1319 [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr, 1320 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 1321 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 1322 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 1323 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 1324 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 1325 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 1326 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 1327 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 1328 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 1329 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 1330 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 1331 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 1332 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 1333 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 1334 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, 1335 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, 1336 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, 1337 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, 1338 [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr, 1339 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 1340 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 1341 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 1342 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 1343 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 1344 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 1345 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, 1346 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 1347 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr, 1348 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 1349 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 1350 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 1351 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 1352 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 1353 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 1354 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 1355 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 1356 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 1357 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 1358 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 1359 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 1360 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 1361 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 1362 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 1363 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, 1364 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, 1365 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, 1366 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 1367 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, 1368 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, 1369 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, 1370 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 1371 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 1372 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 1373 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 1374 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 1375 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 1376 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 1377 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 1378 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 1379 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 1380 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 1381 [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr, 1382 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, 1383 [GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr, 1384 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, 1385 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, 1386 [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr, 1387 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, 1388 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, 1389 [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr, 1390 [GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr, 1391 [GCC_USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr, 1392 [GCC_USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr, 1393 [GCC_USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr, 1394 }; 1395 1396 static const struct qcom_reset_map gcc_mdm9607_resets[] = { 1397 [USB_HS_HSIC_BCR] = { 0x3d05c }, 1398 [GCC_MSS_RESTART] = { 0x3e000 }, 1399 [USB_HS_BCR] = { 0x41000 }, 1400 [USB2_HS_PHY_ONLY_BCR] = { .reg = 0x41034, .udelay = 15 }, 1401 [QUSB2_PHY_BCR] = { 0x4103c }, 1402 }; 1403 1404 static const struct regmap_config gcc_mdm9607_regmap_config = { 1405 .reg_bits = 32, 1406 .reg_stride = 4, 1407 .val_bits = 32, 1408 .max_register = 0x80000, 1409 .fast_io = true, 1410 }; 1411 1412 static const struct qcom_cc_desc gcc_mdm9607_desc = { 1413 .config = &gcc_mdm9607_regmap_config, 1414 .clks = gcc_mdm9607_clocks, 1415 .num_clks = ARRAY_SIZE(gcc_mdm9607_clocks), 1416 .resets = gcc_mdm9607_resets, 1417 .num_resets = ARRAY_SIZE(gcc_mdm9607_resets), 1418 }; 1419 1420 static const struct of_device_id gcc_mdm9607_match_table[] = { 1421 { .compatible = "qcom,gcc-mdm9607" }, 1422 { } 1423 }; 1424 MODULE_DEVICE_TABLE(of, gcc_mdm9607_match_table); 1425 1426 static int gcc_mdm9607_probe(struct platform_device *pdev) 1427 { 1428 return qcom_cc_probe(pdev, &gcc_mdm9607_desc); 1429 } 1430 1431 static struct platform_driver gcc_mdm9607_driver = { 1432 .probe = gcc_mdm9607_probe, 1433 .driver = { 1434 .name = "gcc-mdm9607", 1435 .of_match_table = gcc_mdm9607_match_table, 1436 }, 1437 }; 1438 1439 static int __init gcc_mdm9607_init(void) 1440 { 1441 return platform_driver_register(&gcc_mdm9607_driver); 1442 } 1443 core_initcall(gcc_mdm9607_init); 1444 1445 static void __exit gcc_mdm9607_exit(void) 1446 { 1447 platform_driver_unregister(&gcc_mdm9607_driver); 1448 } 1449 module_exit(gcc_mdm9607_exit); 1450 1451 MODULE_DESCRIPTION("Qualcomm GCC mdm9607 Driver"); 1452 MODULE_LICENSE("GPL v2"); 1453