xref: /linux/drivers/clk/qcom/gcc-ipq9574.c (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0)
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /*
3  * Copyright (c) 2023 The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/clk-provider.h>
7 #include <linux/interconnect-clk.h>
8 #include <linux/interconnect-provider.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 
15 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
16 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
17 #include <dt-bindings/interconnect/qcom,ipq9574.h>
18 
19 #include "clk-alpha-pll.h"
20 #include "clk-branch.h"
21 #include "clk-rcg.h"
22 #include "clk-regmap.h"
23 #include "clk-regmap-divider.h"
24 #include "clk-regmap-mux.h"
25 #include "clk-regmap-phy-mux.h"
26 #include "common.h"
27 #include "reset.h"
28 
29 /* Need to match the order of clocks in DT binding */
30 enum {
31 	DT_XO,
32 	DT_SLEEP_CLK,
33 	DT_BIAS_PLL_UBI_NC_CLK,
34 	DT_PCIE30_PHY0_PIPE_CLK,
35 	DT_PCIE30_PHY1_PIPE_CLK,
36 	DT_PCIE30_PHY2_PIPE_CLK,
37 	DT_PCIE30_PHY3_PIPE_CLK,
38 	DT_USB3PHY_0_CC_PIPE_CLK,
39 };
40 
41 enum {
42 	P_XO,
43 	P_PCIE30_PHY0_PIPE,
44 	P_PCIE30_PHY1_PIPE,
45 	P_PCIE30_PHY2_PIPE,
46 	P_PCIE30_PHY3_PIPE,
47 	P_USB3PHY_0_PIPE,
48 	P_GPLL0,
49 	P_GPLL0_DIV2,
50 	P_GPLL0_OUT_AUX,
51 	P_GPLL2,
52 	P_GPLL4,
53 	P_PI_SLEEP,
54 	P_BIAS_PLL_UBI_NC_CLK,
55 };
56 
57 static const struct parent_map gcc_xo_map[] = {
58 	{ P_XO, 0 },
59 };
60 
61 static const struct clk_parent_data gcc_xo_data[] = {
62 	{ .index = DT_XO },
63 };
64 
65 static const struct clk_parent_data gcc_sleep_clk_data[] = {
66 	{ .index = DT_SLEEP_CLK },
67 };
68 
69 static struct clk_alpha_pll gpll0_main = {
70 	.offset = 0x20000,
71 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
72 	.clkr = {
73 		.enable_reg = 0x0b000,
74 		.enable_mask = BIT(0),
75 		.hw.init = &(const struct clk_init_data) {
76 			.name = "gpll0_main",
77 			.parent_data = gcc_xo_data,
78 			.num_parents = ARRAY_SIZE(gcc_xo_data),
79 			.ops = &clk_alpha_pll_ops,
80 		},
81 	},
82 };
83 
84 static struct clk_fixed_factor gpll0_out_main_div2 = {
85 	.mult = 1,
86 	.div = 2,
87 	.hw.init = &(const struct clk_init_data) {
88 		.name = "gpll0_out_main_div2",
89 		.parent_hws = (const struct clk_hw *[]) {
90 			&gpll0_main.clkr.hw
91 		},
92 		.num_parents = 1,
93 		.ops = &clk_fixed_factor_ops,
94 	},
95 };
96 
97 static struct clk_alpha_pll_postdiv gpll0 = {
98 	.offset = 0x20000,
99 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
100 	.width = 4,
101 	.clkr.hw.init = &(const struct clk_init_data) {
102 		.name = "gpll0",
103 		.parent_hws = (const struct clk_hw *[]) {
104 			&gpll0_main.clkr.hw
105 		},
106 		.num_parents = 1,
107 		.ops = &clk_alpha_pll_postdiv_ro_ops,
108 	},
109 };
110 
111 static struct clk_alpha_pll gpll4_main = {
112 	.offset = 0x22000,
113 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
114 	.clkr = {
115 		.enable_reg = 0x0b000,
116 		.enable_mask = BIT(2),
117 		.hw.init = &(const struct clk_init_data) {
118 			.name = "gpll4_main",
119 			.parent_data = gcc_xo_data,
120 			.num_parents = ARRAY_SIZE(gcc_xo_data),
121 			.ops = &clk_alpha_pll_ops,
122 		},
123 	},
124 };
125 
126 static struct clk_alpha_pll_postdiv gpll4 = {
127 	.offset = 0x22000,
128 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
129 	.width = 4,
130 	.clkr.hw.init = &(const struct clk_init_data) {
131 		.name = "gpll4",
132 		.parent_hws = (const struct clk_hw *[]) {
133 			&gpll4_main.clkr.hw
134 		},
135 		.num_parents = 1,
136 		.ops = &clk_alpha_pll_postdiv_ro_ops,
137 	},
138 };
139 
140 static struct clk_alpha_pll gpll2_main = {
141 	.offset = 0x21000,
142 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
143 	.clkr = {
144 		.enable_reg = 0x0b000,
145 		.enable_mask = BIT(1),
146 		.hw.init = &(const struct clk_init_data) {
147 			.name = "gpll2_main",
148 			.parent_data = gcc_xo_data,
149 			.num_parents = ARRAY_SIZE(gcc_xo_data),
150 			.ops = &clk_alpha_pll_ops,
151 		},
152 	},
153 };
154 
155 static struct clk_alpha_pll_postdiv gpll2 = {
156 	.offset = 0x21000,
157 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
158 	.width = 4,
159 	.clkr.hw.init = &(const struct clk_init_data) {
160 		.name = "gpll2",
161 		.parent_hws = (const struct clk_hw *[]) {
162 			&gpll2_main.clkr.hw
163 		},
164 		.num_parents = 1,
165 		.ops = &clk_alpha_pll_postdiv_ro_ops,
166 	},
167 };
168 
169 static struct clk_branch gcc_sleep_clk_src = {
170 	.halt_reg = 0x3400c,
171 	.clkr = {
172 		.enable_reg = 0x3400c,
173 		.enable_mask = BIT(1),
174 		.hw.init = &(const struct clk_init_data) {
175 			.name = "gcc_sleep_clk_src",
176 			.parent_data = gcc_sleep_clk_data,
177 			.num_parents = ARRAY_SIZE(gcc_sleep_clk_data),
178 			.flags = CLK_IS_CRITICAL,
179 			.ops = &clk_branch2_ops,
180 		},
181 	},
182 };
183 
184 static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
185 	{ .index = DT_XO },
186 	{ .hw = &gpll0.clkr.hw },
187 	{ .hw = &gpll0_out_main_div2.hw },
188 };
189 
190 static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
191 	{ P_XO, 0 },
192 	{ P_GPLL0, 1 },
193 	{ P_GPLL0_DIV2, 4 },
194 };
195 
196 static const struct clk_parent_data gcc_xo_gpll0[] = {
197 	{ .index = DT_XO },
198 	{ .hw = &gpll0.clkr.hw },
199 };
200 
201 static const struct parent_map gcc_xo_gpll0_map[] = {
202 	{ P_XO, 0 },
203 	{ P_GPLL0, 1 },
204 };
205 
206 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
207 	{ .index = DT_XO },
208 	{ .hw = &gpll0.clkr.hw },
209 	{ .hw = &gpll4.clkr.hw },
210 };
211 
212 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
213 	{ P_XO, 0 },
214 	{ P_GPLL0, 1 },
215 	{ P_GPLL4, 2 },
216 };
217 
218 static const struct clk_parent_data gcc_xo_gpll0_gpll0_div2_gpll0[] = {
219 	{ .index = DT_XO },
220 	{ .hw = &gpll0.clkr.hw },
221 	{ .hw = &gpll0_out_main_div2.hw },
222 	{ .hw = &gpll0.clkr.hw },
223 };
224 
225 static const struct parent_map gcc_xo_gpll0_gpll0_div2_gpll0_map[] = {
226 	{ P_XO, 0 },
227 	{ P_GPLL0, 1 },
228 	{ P_GPLL0_DIV2, 4 },
229 	{ P_GPLL0, 5 },
230 };
231 
232 static const struct clk_parent_data gcc_xo_gpll0_gpll0_sleep_clk[] = {
233 	{ .index = DT_XO },
234 	{ .hw = &gpll0.clkr.hw },
235 	{ .hw = &gpll0_out_main_div2.hw },
236 	{ .index = DT_SLEEP_CLK },
237 };
238 
239 static const struct parent_map gcc_xo_gpll0_gpll0_sleep_clk_map[] = {
240 	{ P_XO, 0 },
241 	{ P_GPLL0, 1 },
242 	{ P_GPLL0_DIV2, 4 },
243 	{ P_PI_SLEEP, 6 },
244 };
245 
246 static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {
247 	{ .index = DT_XO },
248 	{ .hw = &gpll0.clkr.hw },
249 	{ .index = DT_SLEEP_CLK },
250 };
251 
252 static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {
253 	{ P_XO, 0 },
254 	{ P_GPLL0, 2 },
255 	{ P_PI_SLEEP, 6 },
256 };
257 
258 static const struct clk_parent_data gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk[] = {
259 	{ .index = DT_XO },
260 	{ .hw = &gpll0.clkr.hw },
261 	{ .hw = &gpll4.clkr.hw },
262 	{ .index = DT_BIAS_PLL_UBI_NC_CLK },
263 };
264 
265 static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map[] = {
266 	{ P_XO, 0 },
267 	{ P_GPLL0, 1 },
268 	{ P_GPLL4, 2 },
269 	{ P_BIAS_PLL_UBI_NC_CLK, 3 },
270 };
271 
272 static const struct clk_parent_data
273 			gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk[] = {
274 	{ .index = DT_XO },
275 	{ .hw = &gpll0.clkr.hw },
276 	{ .hw = &gpll0.clkr.hw },
277 	{ .index = DT_SLEEP_CLK },
278 };
279 
280 static const struct parent_map
281 			gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk_map[] = {
282 	{ P_XO, 0 },
283 	{ P_GPLL0, 1 },
284 	{ P_GPLL0_OUT_AUX, 2 },
285 	{ P_PI_SLEEP, 6 },
286 };
287 
288 static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
289 	{ .index = DT_XO },
290 	{ .hw = &gpll0.clkr.hw },
291 	{ .hw = &gpll0_out_main_div2.hw },
292 };
293 
294 static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
295 	{ P_XO, 0 },
296 	{ P_GPLL0, 1 },
297 	{ P_GPLL0_DIV2, 4 },
298 };
299 
300 static const struct clk_parent_data
301 			gcc_xo_gpll4_gpll0_gpll0_out_main_div2[] = {
302 	{ .index = DT_XO },
303 	{ .hw = &gpll4.clkr.hw },
304 	{ .hw = &gpll0.clkr.hw },
305 	{ .hw = &gpll0_out_main_div2.hw },
306 };
307 
308 static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map[] = {
309 	{ P_XO, 0 },
310 	{ P_GPLL4, 1 },
311 	{ P_GPLL0, 3 },
312 	{ P_GPLL0_DIV2, 4 },
313 };
314 
315 static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
316 	{ .index = DT_USB3PHY_0_CC_PIPE_CLK },
317 	{ .index = DT_XO },
318 };
319 
320 static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
321 	{ P_USB3PHY_0_PIPE, 0 },
322 	{ P_XO, 2 },
323 };
324 
325 static const struct clk_parent_data
326 			gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
327 	{ .index = DT_XO },
328 	{ .hw = &gpll0.clkr.hw },
329 	{ .hw = &gpll2.clkr.hw },
330 	{ .hw = &gpll0_out_main_div2.hw },
331 };
332 
333 static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
334 	{ P_XO, 0 },
335 	{ P_GPLL0, 1 },
336 	{ P_GPLL2, 2 },
337 	{ P_GPLL0_DIV2, 4 },
338 };
339 
340 static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_div2[] = {
341 	{ .index = DT_XO},
342 	{ .hw = &gpll0.clkr.hw },
343 	{ .hw = &gpll4.clkr.hw },
344 	{ .hw = &gpll0_out_main_div2.hw },
345 };
346 
347 static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_div2_map[] = {
348 	{ P_XO, 0 },
349 	{ P_GPLL0, 1 },
350 	{ P_GPLL4, 2 },
351 	{ P_GPLL0_DIV2, 4 },
352 };
353 
354 static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_div2[] = {
355 	{ .index = DT_XO },
356 	{ .hw = &gpll4.clkr.hw },
357 	{ .hw = &gpll0.clkr.hw },
358 	{ .hw = &gpll0_out_main_div2.hw },
359 };
360 
361 static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_div2_map[] = {
362 	{ P_XO, 0 },
363 	{ P_GPLL4, 1 },
364 	{ P_GPLL0, 2 },
365 	{ P_GPLL0_DIV2, 4 },
366 };
367 
368 static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {
369 	{ .index = DT_XO },
370 	{ .hw = &gpll0.clkr.hw },
371 	{ .hw = &gpll2.clkr.hw },
372 };
373 
374 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
375 	{ P_XO, 0 },
376 	{ P_GPLL0, 1 },
377 	{ P_GPLL2, 2 },
378 };
379 
380 static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_pi_sleep[] = {
381 	{ .index = DT_XO },
382 	{ .hw = &gpll0.clkr.hw },
383 	{ .hw = &gpll2.clkr.hw },
384 	{ .hw = &gpll4.clkr.hw },
385 	{ .index = DT_SLEEP_CLK },
386 };
387 
388 static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map[] = {
389 	{ P_XO, 0 },
390 	{ P_GPLL0, 1 },
391 	{ P_GPLL2, 2 },
392 	{ P_GPLL4, 3 },
393 	{ P_PI_SLEEP, 6 },
394 };
395 
396 static const struct clk_parent_data gcc_xo_gpll0_gpll0_aux_gpll2[] = {
397 	{ .index = DT_XO },
398 	{ .hw = &gpll0.clkr.hw },
399 	{ .hw = &gpll0.clkr.hw },
400 	{ .hw = &gpll2.clkr.hw },
401 };
402 
403 static const struct parent_map gcc_xo_gpll0_gpll0_aux_gpll2_map[] = {
404 	{ P_XO, 0 },
405 	{ P_GPLL0, 1 },
406 	{ P_GPLL0_OUT_AUX, 2 },
407 	{ P_GPLL2, 3 },
408 };
409 
410 static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
411 	F(24000000, P_XO, 1, 0, 0),
412 	F(50000000, P_GPLL0, 16, 0, 0),
413 	F(100000000, P_GPLL0, 8, 0, 0),
414 	{ }
415 };
416 
417 static struct clk_rcg2 apss_ahb_clk_src = {
418 	.cmd_rcgr = 0x2400c,
419 	.freq_tbl = ftbl_apss_ahb_clk_src,
420 	.hid_width = 5,
421 	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
422 	.clkr.hw.init = &(const struct clk_init_data) {
423 		.name = "apss_ahb_clk_src",
424 		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
425 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
426 		.ops = &clk_rcg2_ops,
427 	},
428 };
429 
430 static const struct freq_tbl ftbl_apss_axi_clk_src[] = {
431 	F(533000000, P_GPLL0, 1.5, 0, 0),
432 	{ }
433 };
434 
435 static struct clk_rcg2 apss_axi_clk_src = {
436 	.cmd_rcgr = 0x24004,
437 	.freq_tbl = ftbl_apss_axi_clk_src,
438 	.hid_width = 5,
439 	.parent_map = gcc_xo_gpll0_gpll0_div2_gpll0_map,
440 	.clkr.hw.init = &(const struct clk_init_data) {
441 		.name = "apss_axi_clk_src",
442 		.parent_data = gcc_xo_gpll0_gpll0_div2_gpll0,
443 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_div2_gpll0),
444 		.ops = &clk_rcg2_ops,
445 	},
446 };
447 
448 static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
449 	F(9600000, P_XO, 2.5, 0, 0),
450 	F(24000000, P_XO, 1, 0, 0),
451 	F(50000000, P_GPLL0, 16, 0, 0),
452 	{ }
453 };
454 
455 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
456 	.cmd_rcgr = 0x02018,
457 	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
458 	.hid_width = 5,
459 	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
460 	.clkr.hw.init = &(const struct clk_init_data) {
461 		.name = "blsp1_qup1_i2c_apps_clk_src",
462 		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
463 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
464 		.ops = &clk_rcg2_ops,
465 	},
466 };
467 
468 static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
469 	F(960000, P_XO, 10, 2, 5),
470 	F(4800000, P_XO, 5, 0, 0),
471 	F(9600000, P_XO, 2, 4, 5),
472 	F(16000000, P_GPLL0, 10, 1, 5),
473 	F(24000000, P_XO, 1, 0, 0),
474 	F(25000000, P_GPLL0, 16, 1, 2),
475 	F(50000000, P_GPLL0, 16, 0, 0),
476 	{ }
477 };
478 
479 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
480 	.cmd_rcgr = 0x02004,
481 	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
482 	.mnd_width = 8,
483 	.hid_width = 5,
484 	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
485 	.clkr.hw.init = &(const struct clk_init_data) {
486 		.name = "blsp1_qup1_spi_apps_clk_src",
487 		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
488 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
489 		.ops = &clk_rcg2_ops,
490 	},
491 };
492 
493 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
494 	.cmd_rcgr = 0x03018,
495 	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
496 	.hid_width = 5,
497 	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
498 	.clkr.hw.init = &(const struct clk_init_data) {
499 		.name = "blsp1_qup2_i2c_apps_clk_src",
500 		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
501 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
502 		.ops = &clk_rcg2_ops,
503 	},
504 };
505 
506 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
507 	.cmd_rcgr = 0x03004,
508 	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
509 	.mnd_width = 8,
510 	.hid_width = 5,
511 	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
512 	.clkr.hw.init = &(const struct clk_init_data) {
513 		.name = "blsp1_qup2_spi_apps_clk_src",
514 		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
515 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
516 		.ops = &clk_rcg2_ops,
517 	},
518 };
519 
520 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
521 	.cmd_rcgr = 0x04018,
522 	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
523 	.hid_width = 5,
524 	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
525 	.clkr.hw.init = &(const struct clk_init_data) {
526 		.name = "blsp1_qup3_i2c_apps_clk_src",
527 		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
528 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
529 		.ops = &clk_rcg2_ops,
530 	},
531 };
532 
533 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
534 	.cmd_rcgr = 0x04004,
535 	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
536 	.mnd_width = 8,
537 	.hid_width = 5,
538 	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
539 	.clkr.hw.init = &(const struct clk_init_data) {
540 		.name = "blsp1_qup3_spi_apps_clk_src",
541 		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
542 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
543 		.ops = &clk_rcg2_ops,
544 	},
545 };
546 
547 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
548 	.cmd_rcgr = 0x05018,
549 	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
550 	.hid_width = 5,
551 	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
552 	.clkr.hw.init = &(const struct clk_init_data) {
553 		.name = "blsp1_qup4_i2c_apps_clk_src",
554 		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
555 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
556 		.ops = &clk_rcg2_ops,
557 	},
558 };
559 
560 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
561 	.cmd_rcgr = 0x05004,
562 	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
563 	.mnd_width = 8,
564 	.hid_width = 5,
565 	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
566 	.clkr.hw.init = &(const struct clk_init_data) {
567 		.name = "blsp1_qup4_spi_apps_clk_src",
568 		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
569 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
570 		.ops = &clk_rcg2_ops,
571 	},
572 };
573 
574 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
575 	.cmd_rcgr = 0x06018,
576 	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
577 	.hid_width = 5,
578 	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
579 	.clkr.hw.init = &(const struct clk_init_data) {
580 		.name = "blsp1_qup5_i2c_apps_clk_src",
581 		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
582 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
583 		.ops = &clk_rcg2_ops,
584 	},
585 };
586 
587 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
588 	.cmd_rcgr = 0x06004,
589 	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
590 	.mnd_width = 8,
591 	.hid_width = 5,
592 	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
593 	.clkr.hw.init = &(const struct clk_init_data) {
594 		.name = "blsp1_qup5_spi_apps_clk_src",
595 		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
596 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
597 		.ops = &clk_rcg2_ops,
598 	},
599 };
600 
601 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
602 	.cmd_rcgr = 0x07018,
603 	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
604 	.hid_width = 5,
605 	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
606 	.clkr.hw.init = &(const struct clk_init_data) {
607 		.name = "blsp1_qup6_i2c_apps_clk_src",
608 		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
609 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
610 		.ops = &clk_rcg2_ops,
611 	},
612 };
613 
614 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
615 	.cmd_rcgr = 0x07004,
616 	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
617 	.mnd_width = 8,
618 	.hid_width = 5,
619 	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
620 	.clkr.hw.init = &(const struct clk_init_data) {
621 		.name = "blsp1_qup6_spi_apps_clk_src",
622 		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
623 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
624 		.ops = &clk_rcg2_ops,
625 	},
626 };
627 
628 static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
629 	F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
630 	F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
631 	F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
632 	F(24000000, P_XO, 1, 0, 0),
633 	F(25000000, P_GPLL0, 16, 1, 2),
634 	F(32000000, P_GPLL0, 1, 1, 25),
635 	F(40000000, P_GPLL0, 1, 1, 20),
636 	F(46400000, P_GPLL0, 1, 29, 500),
637 	F(48000000, P_GPLL0, 1, 3, 50),
638 	F(51200000, P_GPLL0, 1, 8, 125),
639 	F(56000000, P_GPLL0, 1, 7, 100),
640 	F(58982400, P_GPLL0, 1, 1152, 15625),
641 	F(60000000, P_GPLL0, 1, 3, 40),
642 	F(64000000, P_GPLL0, 12.5, 0, 0),
643 	{ }
644 };
645 
646 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
647 	.cmd_rcgr = 0x0202c,
648 	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
649 	.mnd_width = 16,
650 	.hid_width = 5,
651 	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
652 	.clkr.hw.init = &(const struct clk_init_data) {
653 		.name = "blsp1_uart1_apps_clk_src",
654 		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
655 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
656 		.ops = &clk_rcg2_ops,
657 	},
658 };
659 
660 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
661 	.cmd_rcgr = 0x0302c,
662 	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
663 	.mnd_width = 16,
664 	.hid_width = 5,
665 	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
666 	.clkr.hw.init = &(const struct clk_init_data) {
667 		.name = "blsp1_uart2_apps_clk_src",
668 		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
669 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
670 		.ops = &clk_rcg2_ops,
671 	},
672 };
673 
674 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
675 	.cmd_rcgr = 0x0402c,
676 	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
677 	.mnd_width = 16,
678 	.hid_width = 5,
679 	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
680 	.clkr.hw.init = &(const struct clk_init_data) {
681 		.name = "blsp1_uart3_apps_clk_src",
682 		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
683 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
684 		.ops = &clk_rcg2_ops,
685 	},
686 };
687 
688 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
689 	.cmd_rcgr = 0x0502c,
690 	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
691 	.mnd_width = 16,
692 	.hid_width = 5,
693 	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
694 	.clkr.hw.init = &(const struct clk_init_data) {
695 		.name = "blsp1_uart4_apps_clk_src",
696 		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
697 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
698 		.ops = &clk_rcg2_ops,
699 	},
700 };
701 
702 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
703 	.cmd_rcgr = 0x0602c,
704 	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
705 	.mnd_width = 16,
706 	.hid_width = 5,
707 	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
708 	.clkr.hw.init = &(const struct clk_init_data) {
709 		.name = "blsp1_uart5_apps_clk_src",
710 		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
711 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
712 		.ops = &clk_rcg2_ops,
713 	},
714 };
715 
716 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
717 	.cmd_rcgr = 0x0702c,
718 	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
719 	.mnd_width = 16,
720 	.hid_width = 5,
721 	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
722 	.clkr.hw.init = &(const struct clk_init_data) {
723 		.name = "blsp1_uart6_apps_clk_src",
724 		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
725 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
726 		.ops = &clk_rcg2_ops,
727 	},
728 };
729 
730 static const struct freq_tbl ftbl_gcc_crypto_clk_src[] = {
731 	F(160000000, P_GPLL0, 5, 0, 0),
732 	{ }
733 };
734 
735 static struct clk_rcg2 gcc_crypto_clk_src = {
736 	.cmd_rcgr = 0x16004,
737 	.freq_tbl = ftbl_gcc_crypto_clk_src,
738 	.hid_width = 5,
739 	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
740 	.clkr.hw.init = &(const struct clk_init_data) {
741 		.name = "gcc_crypto_clk_src",
742 		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
743 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
744 		.ops = &clk_rcg2_ops,
745 	},
746 };
747 
748 static struct clk_branch gcc_crypto_clk = {
749 	.halt_reg = 0x1600c,
750 	.halt_check = BRANCH_HALT_VOTED,
751 	.clkr = {
752 		.enable_reg = 0x0b004,
753 		.enable_mask = BIT(14),
754 		.hw.init = &(const struct clk_init_data) {
755 			.name = "gcc_crypto_clk",
756 			.parent_hws = (const struct clk_hw *[]) {
757 				&gcc_crypto_clk_src.clkr.hw },
758 			.num_parents = 1,
759 			.flags = CLK_SET_RATE_PARENT,
760 			.ops = &clk_branch2_ops,
761 		},
762 	},
763 };
764 
765 static struct clk_branch gcc_apss_ahb_clk = {
766 	.halt_reg = 0x24018,
767 	.halt_check = BRANCH_HALT_VOTED,
768 	.clkr = {
769 		.enable_reg = 0x0b004,
770 		.enable_mask = BIT(0),
771 		.hw.init = &(const struct clk_init_data) {
772 			.name = "gcc_apss_ahb_clk",
773 			.parent_hws = (const struct clk_hw *[]) {
774 				&apss_ahb_clk_src.clkr.hw
775 			},
776 			.num_parents = 1,
777 			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
778 			.ops = &clk_branch2_ops,
779 		},
780 	},
781 };
782 
783 static struct clk_branch gcc_apss_axi_clk = {
784 	.halt_reg = 0x2401c,
785 	.halt_check = BRANCH_HALT_VOTED,
786 	.clkr = {
787 		.enable_reg = 0x0b004,
788 		.enable_mask = BIT(1),
789 		.hw.init = &(const struct clk_init_data) {
790 			.name = "gcc_apss_axi_clk",
791 			.parent_hws = (const struct clk_hw *[]) {
792 				&apss_axi_clk_src.clkr.hw
793 			},
794 			.num_parents = 1,
795 			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
796 			.ops = &clk_branch2_ops,
797 		},
798 	},
799 };
800 
801 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
802 	.halt_reg = 0x2024,
803 	.clkr = {
804 		.enable_reg = 0x2024,
805 		.enable_mask = BIT(0),
806 		.hw.init = &(const struct clk_init_data) {
807 			.name = "gcc_blsp1_qup1_i2c_apps_clk",
808 			.parent_hws = (const struct clk_hw *[]) {
809 				&blsp1_qup1_i2c_apps_clk_src.clkr.hw
810 			},
811 			.num_parents = 1,
812 			.flags = CLK_SET_RATE_PARENT,
813 			.ops = &clk_branch2_ops,
814 		},
815 	},
816 };
817 
818 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
819 	.halt_reg = 0x02020,
820 	.clkr = {
821 		.enable_reg = 0x02020,
822 		.enable_mask = BIT(0),
823 		.hw.init = &(const struct clk_init_data) {
824 			.name = "gcc_blsp1_qup1_spi_apps_clk",
825 			.parent_hws = (const struct clk_hw *[]) {
826 				&blsp1_qup1_spi_apps_clk_src.clkr.hw
827 			},
828 			.num_parents = 1,
829 			.flags = CLK_SET_RATE_PARENT,
830 			.ops = &clk_branch2_ops,
831 		},
832 	},
833 };
834 
835 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
836 	.halt_reg = 0x03024,
837 	.clkr = {
838 		.enable_reg = 0x03024,
839 		.enable_mask = BIT(0),
840 		.hw.init = &(const struct clk_init_data) {
841 			.name = "gcc_blsp1_qup2_i2c_apps_clk",
842 			.parent_hws = (const struct clk_hw *[]) {
843 				&blsp1_qup2_i2c_apps_clk_src.clkr.hw
844 			},
845 			.num_parents = 1,
846 			.flags = CLK_SET_RATE_PARENT,
847 			.ops = &clk_branch2_ops,
848 		},
849 	},
850 };
851 
852 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
853 	.halt_reg = 0x03020,
854 	.clkr = {
855 		.enable_reg = 0x03020,
856 		.enable_mask = BIT(0),
857 		.hw.init = &(const struct clk_init_data) {
858 			.name = "gcc_blsp1_qup2_spi_apps_clk",
859 			.parent_hws = (const struct clk_hw *[]) {
860 				&blsp1_qup2_spi_apps_clk_src.clkr.hw
861 			},
862 			.num_parents = 1,
863 			.flags = CLK_SET_RATE_PARENT,
864 			.ops = &clk_branch2_ops,
865 		},
866 	},
867 };
868 
869 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
870 	.halt_reg = 0x04024,
871 	.clkr = {
872 		.enable_reg = 0x04024,
873 		.enable_mask = BIT(0),
874 		.hw.init = &(const struct clk_init_data) {
875 			.name = "gcc_blsp1_qup3_i2c_apps_clk",
876 			.parent_hws = (const struct clk_hw *[]) {
877 				&blsp1_qup3_i2c_apps_clk_src.clkr.hw
878 			},
879 			.num_parents = 1,
880 			.flags = CLK_SET_RATE_PARENT,
881 			.ops = &clk_branch2_ops,
882 		},
883 	},
884 };
885 
886 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
887 	.halt_reg = 0x04020,
888 	.clkr = {
889 		.enable_reg = 0x04020,
890 		.enable_mask = BIT(0),
891 		.hw.init = &(const struct clk_init_data) {
892 			.name = "gcc_blsp1_qup3_spi_apps_clk",
893 			.parent_hws = (const struct clk_hw *[]) {
894 				&blsp1_qup3_spi_apps_clk_src.clkr.hw
895 			},
896 			.num_parents = 1,
897 			.flags = CLK_SET_RATE_PARENT,
898 			.ops = &clk_branch2_ops,
899 		},
900 	},
901 };
902 
903 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
904 	.halt_reg = 0x05024,
905 	.clkr = {
906 		.enable_reg = 0x05024,
907 		.enable_mask = BIT(0),
908 		.hw.init = &(const struct clk_init_data) {
909 			.name = "gcc_blsp1_qup4_i2c_apps_clk",
910 			.parent_hws = (const struct clk_hw *[]) {
911 				&blsp1_qup4_i2c_apps_clk_src.clkr.hw
912 			},
913 			.num_parents = 1,
914 			.flags = CLK_SET_RATE_PARENT,
915 			.ops = &clk_branch2_ops,
916 		},
917 	},
918 };
919 
920 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
921 	.halt_reg = 0x05020,
922 	.clkr = {
923 		.enable_reg = 0x05020,
924 		.enable_mask = BIT(0),
925 		.hw.init = &(const struct clk_init_data) {
926 			.name = "gcc_blsp1_qup4_spi_apps_clk",
927 			.parent_hws = (const struct clk_hw *[]) {
928 				&blsp1_qup4_spi_apps_clk_src.clkr.hw
929 			},
930 			.num_parents = 1,
931 			.flags = CLK_SET_RATE_PARENT,
932 			.ops = &clk_branch2_ops,
933 		},
934 	},
935 };
936 
937 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
938 	.halt_reg = 0x06024,
939 	.clkr = {
940 		.enable_reg = 0x06024,
941 		.enable_mask = BIT(0),
942 		.hw.init = &(const struct clk_init_data) {
943 			.name = "gcc_blsp1_qup5_i2c_apps_clk",
944 			.parent_hws = (const struct clk_hw *[]) {
945 				&blsp1_qup5_i2c_apps_clk_src.clkr.hw
946 			},
947 			.num_parents = 1,
948 			.flags = CLK_SET_RATE_PARENT,
949 			.ops = &clk_branch2_ops,
950 		},
951 	},
952 };
953 
954 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
955 	.halt_reg = 0x06020,
956 	.clkr = {
957 		.enable_reg = 0x06020,
958 		.enable_mask = BIT(0),
959 		.hw.init = &(const struct clk_init_data) {
960 			.name = "gcc_blsp1_qup5_spi_apps_clk",
961 			.parent_hws = (const struct clk_hw *[]) {
962 				&blsp1_qup5_spi_apps_clk_src.clkr.hw
963 			},
964 			.num_parents = 1,
965 			.flags = CLK_SET_RATE_PARENT,
966 			.ops = &clk_branch2_ops,
967 		},
968 	},
969 };
970 
971 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
972 	.halt_reg = 0x07024,
973 	.clkr = {
974 		.enable_reg = 0x07024,
975 		.enable_mask = BIT(0),
976 		.hw.init = &(const struct clk_init_data) {
977 			.name = "gcc_blsp1_qup6_i2c_apps_clk",
978 			.parent_hws = (const struct clk_hw *[]) {
979 				&blsp1_qup6_i2c_apps_clk_src.clkr.hw
980 			},
981 			.num_parents = 1,
982 			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
983 			.ops = &clk_branch2_ops,
984 		},
985 	},
986 };
987 
988 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
989 	.halt_reg = 0x07020,
990 	.clkr = {
991 		.enable_reg = 0x07020,
992 		.enable_mask = BIT(0),
993 		.hw.init = &(const struct clk_init_data) {
994 			.name = "gcc_blsp1_qup6_spi_apps_clk",
995 			.parent_hws = (const struct clk_hw *[]) {
996 				&blsp1_qup6_spi_apps_clk_src.clkr.hw
997 			},
998 			.num_parents = 1,
999 			.flags = CLK_SET_RATE_PARENT,
1000 			.ops = &clk_branch2_ops,
1001 		},
1002 	},
1003 };
1004 
1005 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1006 	.halt_reg = 0x02040,
1007 	.clkr = {
1008 		.enable_reg = 0x02040,
1009 		.enable_mask = BIT(0),
1010 		.hw.init = &(const struct clk_init_data) {
1011 			.name = "gcc_blsp1_uart1_apps_clk",
1012 			.parent_hws = (const struct clk_hw *[]) {
1013 				&blsp1_uart1_apps_clk_src.clkr.hw
1014 			},
1015 			.num_parents = 1,
1016 			.flags = CLK_SET_RATE_PARENT,
1017 			.ops = &clk_branch2_ops,
1018 		},
1019 	},
1020 };
1021 
1022 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1023 	.halt_reg = 0x03040,
1024 	.clkr = {
1025 		.enable_reg = 0x03040,
1026 		.enable_mask = BIT(0),
1027 		.hw.init = &(const struct clk_init_data) {
1028 			.name = "gcc_blsp1_uart2_apps_clk",
1029 			.parent_hws = (const struct clk_hw *[]) {
1030 				&blsp1_uart2_apps_clk_src.clkr.hw
1031 			},
1032 			.num_parents = 1,
1033 			.flags = CLK_SET_RATE_PARENT,
1034 			.ops = &clk_branch2_ops,
1035 		},
1036 	},
1037 };
1038 
1039 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1040 	.halt_reg = 0x04054,
1041 	.clkr = {
1042 		.enable_reg = 0x04054,
1043 		.enable_mask = BIT(0),
1044 		.hw.init = &(const struct clk_init_data) {
1045 			.name = "gcc_blsp1_uart3_apps_clk",
1046 			.parent_hws = (const struct clk_hw *[]) {
1047 				&blsp1_uart3_apps_clk_src.clkr.hw
1048 			},
1049 			.num_parents = 1,
1050 			.flags = CLK_SET_RATE_PARENT,
1051 			.ops = &clk_branch2_ops,
1052 		},
1053 	},
1054 };
1055 
1056 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1057 	.halt_reg = 0x05040,
1058 	.clkr = {
1059 		.enable_reg = 0x05040,
1060 		.enable_mask = BIT(0),
1061 		.hw.init = &(const struct clk_init_data) {
1062 			.name = "gcc_blsp1_uart4_apps_clk",
1063 			.parent_hws = (const struct clk_hw *[]) {
1064 				&blsp1_uart4_apps_clk_src.clkr.hw
1065 			},
1066 			.num_parents = 1,
1067 			.flags = CLK_SET_RATE_PARENT,
1068 			.ops = &clk_branch2_ops,
1069 		},
1070 	},
1071 };
1072 
1073 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1074 	.halt_reg = 0x06040,
1075 	.clkr = {
1076 		.enable_reg = 0x06040,
1077 		.enable_mask = BIT(0),
1078 		.hw.init = &(const struct clk_init_data) {
1079 			.name = "gcc_blsp1_uart5_apps_clk",
1080 			.parent_hws = (const struct clk_hw *[]) {
1081 				&blsp1_uart5_apps_clk_src.clkr.hw
1082 			},
1083 			.num_parents = 1,
1084 			.flags = CLK_SET_RATE_PARENT,
1085 			.ops = &clk_branch2_ops,
1086 		},
1087 	},
1088 };
1089 
1090 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1091 	.halt_reg = 0x07040,
1092 	.clkr = {
1093 		.enable_reg = 0x07040,
1094 		.enable_mask = BIT(0),
1095 		.hw.init = &(const struct clk_init_data) {
1096 			.name = "gcc_blsp1_uart6_apps_clk",
1097 			.parent_hws = (const struct clk_hw *[]) {
1098 				&blsp1_uart6_apps_clk_src.clkr.hw
1099 			},
1100 			.num_parents = 1,
1101 			.flags = CLK_SET_RATE_PARENT,
1102 			.ops = &clk_branch2_ops,
1103 		},
1104 	},
1105 };
1106 
1107 static const struct freq_tbl ftbl_pcie0_axi_m_clk_src[] = {
1108 	F(240000000, P_GPLL4, 5, 0, 0),
1109 	{ }
1110 };
1111 
1112 static struct clk_rcg2 pcie0_axi_m_clk_src = {
1113 	.cmd_rcgr = 0x28018,
1114 	.freq_tbl = ftbl_pcie0_axi_m_clk_src,
1115 	.hid_width = 5,
1116 	.parent_map = gcc_xo_gpll0_gpll4_map,
1117 	.clkr.hw.init = &(const struct clk_init_data) {
1118 		.name = "pcie0_axi_m_clk_src",
1119 		.parent_data = gcc_xo_gpll0_gpll4,
1120 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1121 		.ops = &clk_rcg2_ops,
1122 	},
1123 };
1124 
1125 static struct clk_branch gcc_pcie0_axi_m_clk = {
1126 	.halt_reg = 0x28038,
1127 	.clkr = {
1128 		.enable_reg = 0x28038,
1129 		.enable_mask = BIT(0),
1130 		.hw.init = &(const struct clk_init_data) {
1131 			.name = "gcc_pcie0_axi_m_clk",
1132 			.parent_hws = (const struct clk_hw *[]) {
1133 				&pcie0_axi_m_clk_src.clkr.hw
1134 			},
1135 			.num_parents = 1,
1136 			.flags = CLK_SET_RATE_PARENT,
1137 			.ops = &clk_branch2_ops,
1138 		},
1139 	},
1140 };
1141 
1142 static struct clk_branch gcc_anoc_pcie0_1lane_m_clk = {
1143 	.halt_reg = 0x2e07c,
1144 	.clkr = {
1145 		.enable_reg = 0x2e07c,
1146 		.enable_mask = BIT(0),
1147 		.hw.init = &(const struct clk_init_data) {
1148 			.name = "gcc_anoc_pcie0_1lane_m_clk",
1149 			.parent_hws = (const struct clk_hw *[]) {
1150 				&pcie0_axi_m_clk_src.clkr.hw
1151 			},
1152 			.num_parents = 1,
1153 			.flags = CLK_SET_RATE_PARENT,
1154 			.ops = &clk_branch2_ops,
1155 		},
1156 	},
1157 };
1158 
1159 static struct clk_rcg2 pcie1_axi_m_clk_src = {
1160 	.cmd_rcgr = 0x29018,
1161 	.freq_tbl = ftbl_pcie0_axi_m_clk_src,
1162 	.hid_width = 5,
1163 	.parent_map = gcc_xo_gpll0_gpll4_map,
1164 	.clkr.hw.init = &(const struct clk_init_data) {
1165 		.name = "pcie1_axi_m_clk_src",
1166 		.parent_data = gcc_xo_gpll0_gpll4,
1167 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1168 		.ops = &clk_rcg2_ops,
1169 	},
1170 };
1171 
1172 static struct clk_branch gcc_pcie1_axi_m_clk = {
1173 	.halt_reg = 0x29038,
1174 	.clkr = {
1175 		.enable_reg = 0x29038,
1176 		.enable_mask = BIT(0),
1177 		.hw.init = &(const struct clk_init_data) {
1178 			.name = "gcc_pcie1_axi_m_clk",
1179 			.parent_hws = (const struct clk_hw *[]) {
1180 				&pcie1_axi_m_clk_src.clkr.hw
1181 			},
1182 			.num_parents = 1,
1183 			.flags = CLK_SET_RATE_PARENT,
1184 			.ops = &clk_branch2_ops,
1185 		},
1186 	},
1187 };
1188 
1189 static struct clk_branch gcc_anoc_pcie1_1lane_m_clk = {
1190 	.halt_reg = 0x2e08c,
1191 	.clkr = {
1192 		.enable_reg = 0x2e08c,
1193 		.enable_mask = BIT(0),
1194 		.hw.init = &(const struct clk_init_data) {
1195 			.name = "gcc_anoc_pcie1_1lane_m_clk",
1196 			.parent_hws = (const struct clk_hw *[]) {
1197 				&pcie1_axi_m_clk_src.clkr.hw
1198 			},
1199 			.num_parents = 1,
1200 			.flags = CLK_SET_RATE_PARENT,
1201 			.ops = &clk_branch2_ops,
1202 		},
1203 	},
1204 };
1205 
1206 static const struct freq_tbl ftbl_pcie2_axi_m_clk_src[] = {
1207 	F(342857143, P_GPLL4, 3.5, 0, 0),
1208 	{ }
1209 };
1210 
1211 static struct clk_rcg2 pcie2_axi_m_clk_src = {
1212 	.cmd_rcgr = 0x2a018,
1213 	.freq_tbl = ftbl_pcie2_axi_m_clk_src,
1214 	.hid_width = 5,
1215 	.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map,
1216 	.clkr.hw.init = &(const struct clk_init_data) {
1217 		.name = "pcie2_axi_m_clk_src",
1218 		.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
1219 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
1220 		.ops = &clk_rcg2_ops,
1221 	},
1222 };
1223 
1224 static struct clk_branch gcc_pcie2_axi_m_clk = {
1225 	.halt_reg = 0x2a038,
1226 	.clkr = {
1227 		.enable_reg = 0x2a038,
1228 		.enable_mask = BIT(0),
1229 		.hw.init = &(const struct clk_init_data) {
1230 			.name = "gcc_pcie2_axi_m_clk",
1231 			.parent_hws = (const struct clk_hw *[]) {
1232 				&pcie2_axi_m_clk_src.clkr.hw
1233 			},
1234 			.num_parents = 1,
1235 			.flags = CLK_SET_RATE_PARENT,
1236 			.ops = &clk_branch2_ops,
1237 		},
1238 	},
1239 };
1240 
1241 static struct clk_branch gcc_anoc_pcie2_2lane_m_clk = {
1242 	.halt_reg = 0x2e080,
1243 	.clkr = {
1244 		.enable_reg = 0x2e080,
1245 		.enable_mask = BIT(0),
1246 		.hw.init = &(const struct clk_init_data) {
1247 			.name = "gcc_anoc_pcie2_2lane_m_clk",
1248 			.parent_hws = (const struct clk_hw *[]) {
1249 				&pcie2_axi_m_clk_src.clkr.hw
1250 			},
1251 			.num_parents = 1,
1252 			.flags = CLK_SET_RATE_PARENT,
1253 			.ops = &clk_branch2_ops,
1254 		},
1255 	},
1256 };
1257 
1258 static struct clk_rcg2 pcie3_axi_m_clk_src = {
1259 	.cmd_rcgr = 0x2b018,
1260 	.freq_tbl = ftbl_pcie2_axi_m_clk_src,
1261 	.hid_width = 5,
1262 	.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map,
1263 	.clkr.hw.init = &(const struct clk_init_data) {
1264 		.name = "pcie3_axi_m_clk_src",
1265 		.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
1266 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
1267 		.ops = &clk_rcg2_ops,
1268 	},
1269 };
1270 
1271 static struct clk_branch gcc_pcie3_axi_m_clk = {
1272 	.halt_reg = 0x2b038,
1273 	.clkr = {
1274 		.enable_reg = 0x2b038,
1275 		.enable_mask = BIT(0),
1276 		.hw.init = &(const struct clk_init_data) {
1277 			.name = "gcc_pcie3_axi_m_clk",
1278 			.parent_hws = (const struct clk_hw *[]) {
1279 				&pcie3_axi_m_clk_src.clkr.hw
1280 			},
1281 			.num_parents = 1,
1282 			.flags = CLK_SET_RATE_PARENT,
1283 			.ops = &clk_branch2_ops,
1284 		},
1285 	},
1286 };
1287 
1288 static struct clk_branch gcc_anoc_pcie3_2lane_m_clk = {
1289 	.halt_reg = 0x2e090,
1290 	.clkr = {
1291 		.enable_reg = 0x2e090,
1292 		.enable_mask = BIT(0),
1293 		.hw.init = &(const struct clk_init_data) {
1294 			.name = "gcc_anoc_pcie3_2lane_m_clk",
1295 			.parent_hws = (const struct clk_hw *[]) {
1296 				&pcie3_axi_m_clk_src.clkr.hw
1297 			},
1298 			.num_parents = 1,
1299 			.flags = CLK_SET_RATE_PARENT,
1300 			.ops = &clk_branch2_ops,
1301 		},
1302 	},
1303 };
1304 
1305 static struct clk_rcg2 pcie0_axi_s_clk_src = {
1306 	.cmd_rcgr = 0x28020,
1307 	.freq_tbl = ftbl_pcie0_axi_m_clk_src,
1308 	.hid_width = 5,
1309 	.parent_map = gcc_xo_gpll0_gpll4_map,
1310 	.clkr.hw.init = &(const struct clk_init_data) {
1311 		.name = "pcie0_axi_s_clk_src",
1312 		.parent_data = gcc_xo_gpll0_gpll4,
1313 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1314 		.ops = &clk_rcg2_ops,
1315 	},
1316 };
1317 
1318 static struct clk_branch gcc_pcie0_axi_s_clk = {
1319 	.halt_reg = 0x2803c,
1320 	.clkr = {
1321 		.enable_reg = 0x2803c,
1322 		.enable_mask = BIT(0),
1323 		.hw.init = &(const struct clk_init_data) {
1324 			.name = "gcc_pcie0_axi_s_clk",
1325 			.parent_hws = (const struct clk_hw *[]) {
1326 				&pcie0_axi_s_clk_src.clkr.hw
1327 			},
1328 			.num_parents = 1,
1329 			.flags = CLK_SET_RATE_PARENT,
1330 			.ops = &clk_branch2_ops,
1331 		},
1332 	},
1333 };
1334 
1335 static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
1336 	.halt_reg = 0x28040,
1337 	.clkr = {
1338 		.enable_reg = 0x28040,
1339 		.enable_mask = BIT(0),
1340 		.hw.init = &(const struct clk_init_data) {
1341 			.name = "gcc_pcie0_axi_s_bridge_clk",
1342 			.parent_hws = (const struct clk_hw *[]) {
1343 				&pcie0_axi_s_clk_src.clkr.hw
1344 			},
1345 			.num_parents = 1,
1346 			.flags = CLK_SET_RATE_PARENT,
1347 			.ops = &clk_branch2_ops,
1348 		},
1349 	},
1350 };
1351 
1352 static struct clk_branch gcc_snoc_pcie0_1lane_s_clk = {
1353 	.halt_reg = 0x2e048,
1354 	.clkr = {
1355 		.enable_reg = 0x2e048,
1356 		.enable_mask = BIT(0),
1357 		.hw.init = &(const struct clk_init_data) {
1358 			.name = "gcc_snoc_pcie0_1lane_s_clk",
1359 			.parent_hws = (const struct clk_hw *[]) {
1360 				&pcie0_axi_s_clk_src.clkr.hw
1361 			},
1362 			.num_parents = 1,
1363 			.flags = CLK_SET_RATE_PARENT,
1364 			.ops = &clk_branch2_ops,
1365 		},
1366 	},
1367 };
1368 
1369 static struct clk_rcg2 pcie1_axi_s_clk_src = {
1370 	.cmd_rcgr = 0x29020,
1371 	.freq_tbl = ftbl_pcie0_axi_m_clk_src,
1372 	.hid_width = 5,
1373 	.parent_map = gcc_xo_gpll0_gpll4_map,
1374 	.clkr.hw.init = &(const struct clk_init_data) {
1375 		.name = "pcie1_axi_s_clk_src",
1376 		.parent_data = gcc_xo_gpll0_gpll4,
1377 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1378 		.ops = &clk_rcg2_ops,
1379 	},
1380 };
1381 
1382 static struct clk_branch gcc_pcie1_axi_s_clk = {
1383 	.halt_reg = 0x2903c,
1384 	.clkr = {
1385 		.enable_reg = 0x2903c,
1386 		.enable_mask = BIT(0),
1387 		.hw.init = &(const struct clk_init_data) {
1388 			.name = "gcc_pcie1_axi_s_clk",
1389 			.parent_hws = (const struct clk_hw *[]) {
1390 				&pcie1_axi_s_clk_src.clkr.hw
1391 			},
1392 			.num_parents = 1,
1393 			.flags = CLK_SET_RATE_PARENT,
1394 			.ops = &clk_branch2_ops,
1395 		},
1396 	},
1397 };
1398 
1399 static struct clk_branch gcc_pcie1_axi_s_bridge_clk = {
1400 	.halt_reg = 0x29040,
1401 	.clkr = {
1402 		.enable_reg = 0x29040,
1403 		.enable_mask = BIT(0),
1404 		.hw.init = &(const struct clk_init_data) {
1405 			.name = "gcc_pcie1_axi_s_bridge_clk",
1406 			.parent_hws = (const struct clk_hw *[]) {
1407 				&pcie1_axi_s_clk_src.clkr.hw
1408 			},
1409 			.num_parents = 1,
1410 			.flags = CLK_SET_RATE_PARENT,
1411 			.ops = &clk_branch2_ops,
1412 		},
1413 	},
1414 };
1415 
1416 static struct clk_branch gcc_snoc_pcie1_1lane_s_clk = {
1417 	.halt_reg = 0x2e04c,
1418 	.clkr = {
1419 		.enable_reg = 0x2e04c,
1420 		.enable_mask = BIT(0),
1421 		.hw.init = &(const struct clk_init_data) {
1422 			.name = "gcc_snoc_pcie1_1lane_s_clk",
1423 			.parent_hws = (const struct clk_hw *[]) {
1424 				&pcie1_axi_s_clk_src.clkr.hw
1425 			},
1426 			.num_parents = 1,
1427 			.flags = CLK_SET_RATE_PARENT,
1428 			.ops = &clk_branch2_ops,
1429 		},
1430 	},
1431 };
1432 
1433 static struct clk_rcg2 pcie2_axi_s_clk_src = {
1434 	.cmd_rcgr = 0x2a020,
1435 	.freq_tbl = ftbl_pcie0_axi_m_clk_src,
1436 	.hid_width = 5,
1437 	.parent_map = gcc_xo_gpll0_gpll4_map,
1438 	.clkr.hw.init = &(const struct clk_init_data) {
1439 		.name = "pcie2_axi_s_clk_src",
1440 		.parent_data = gcc_xo_gpll0_gpll4,
1441 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1442 		.ops = &clk_rcg2_ops,
1443 	},
1444 };
1445 
1446 static struct clk_branch gcc_pcie2_axi_s_clk = {
1447 	.halt_reg = 0x2a03c,
1448 	.clkr = {
1449 		.enable_reg = 0x2a03c,
1450 		.enable_mask = BIT(0),
1451 		.hw.init = &(const struct clk_init_data) {
1452 			.name = "gcc_pcie2_axi_s_clk",
1453 			.parent_hws = (const struct clk_hw *[]) {
1454 				&pcie2_axi_s_clk_src.clkr.hw
1455 			},
1456 			.num_parents = 1,
1457 			.flags = CLK_SET_RATE_PARENT,
1458 			.ops = &clk_branch2_ops,
1459 		},
1460 	},
1461 };
1462 
1463 static struct clk_branch gcc_pcie2_axi_s_bridge_clk = {
1464 	.halt_reg = 0x2a040,
1465 	.clkr = {
1466 		.enable_reg = 0x2a040,
1467 		.enable_mask = BIT(0),
1468 		.hw.init = &(const struct clk_init_data) {
1469 			.name = "gcc_pcie2_axi_s_bridge_clk",
1470 			.parent_hws = (const struct clk_hw *[]) {
1471 				&pcie2_axi_s_clk_src.clkr.hw
1472 			},
1473 			.num_parents = 1,
1474 			.flags = CLK_SET_RATE_PARENT,
1475 			.ops = &clk_branch2_ops,
1476 		},
1477 	},
1478 };
1479 
1480 static struct clk_branch gcc_snoc_pcie2_2lane_s_clk = {
1481 	.halt_reg = 0x2e050,
1482 	.clkr = {
1483 		.enable_reg = 0x2e050,
1484 		.enable_mask = BIT(0),
1485 		.hw.init = &(const struct clk_init_data) {
1486 			.name = "gcc_snoc_pcie2_2lane_s_clk",
1487 			.parent_hws = (const struct clk_hw *[]) {
1488 				&pcie2_axi_s_clk_src.clkr.hw
1489 			},
1490 			.num_parents = 1,
1491 			.flags = CLK_SET_RATE_PARENT,
1492 			.ops = &clk_branch2_ops,
1493 		},
1494 	},
1495 };
1496 
1497 static struct clk_rcg2 pcie3_axi_s_clk_src = {
1498 	.cmd_rcgr = 0x2b020,
1499 	.freq_tbl = ftbl_pcie0_axi_m_clk_src,
1500 	.hid_width = 5,
1501 	.parent_map = gcc_xo_gpll0_gpll4_map,
1502 	.clkr.hw.init = &(const struct clk_init_data) {
1503 		.name = "pcie3_axi_s_clk_src",
1504 		.parent_data = gcc_xo_gpll0_gpll4,
1505 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1506 		.ops = &clk_rcg2_ops,
1507 	},
1508 };
1509 
1510 static struct clk_branch gcc_pcie3_axi_s_clk = {
1511 	.halt_reg = 0x2b03c,
1512 	.clkr = {
1513 		.enable_reg = 0x2b03c,
1514 		.enable_mask = BIT(0),
1515 		.hw.init = &(const struct clk_init_data) {
1516 			.name = "gcc_pcie3_axi_s_clk",
1517 			.parent_hws = (const struct clk_hw *[]) {
1518 				&pcie3_axi_s_clk_src.clkr.hw
1519 			},
1520 			.num_parents = 1,
1521 			.flags = CLK_SET_RATE_PARENT,
1522 			.ops = &clk_branch2_ops,
1523 		},
1524 	},
1525 };
1526 
1527 static struct clk_branch gcc_pcie3_axi_s_bridge_clk = {
1528 	.halt_reg = 0x2b040,
1529 	.clkr = {
1530 		.enable_reg = 0x2b040,
1531 		.enable_mask = BIT(0),
1532 		.hw.init = &(const struct clk_init_data) {
1533 			.name = "gcc_pcie3_axi_s_bridge_clk",
1534 			.parent_hws = (const struct clk_hw *[]) {
1535 				&pcie3_axi_s_clk_src.clkr.hw
1536 			},
1537 			.num_parents = 1,
1538 			.flags = CLK_SET_RATE_PARENT,
1539 			.ops = &clk_branch2_ops,
1540 		},
1541 	},
1542 };
1543 
1544 static struct clk_branch gcc_snoc_pcie3_2lane_s_clk = {
1545 	.halt_reg = 0x2e054,
1546 	.clkr = {
1547 		.enable_reg = 0x2e054,
1548 		.enable_mask = BIT(0),
1549 		.hw.init = &(const struct clk_init_data) {
1550 			.name = "gcc_snoc_pcie3_2lane_s_clk",
1551 			.parent_hws = (const struct clk_hw *[]) {
1552 				&pcie3_axi_s_clk_src.clkr.hw
1553 			},
1554 			.num_parents = 1,
1555 			.flags = CLK_SET_RATE_PARENT,
1556 			.ops = &clk_branch2_ops,
1557 		},
1558 	},
1559 };
1560 
1561 static struct clk_regmap_phy_mux pcie0_pipe_clk_src = {
1562 	.reg = 0x28064,
1563 	.clkr = {
1564 		.hw.init = &(const struct clk_init_data) {
1565 			.name = "pcie0_pipe_clk_src",
1566 			.parent_data = &(const struct clk_parent_data) {
1567 				.index = DT_PCIE30_PHY0_PIPE_CLK,
1568 			},
1569 			.num_parents = 1,
1570 			.ops = &clk_regmap_phy_mux_ops,
1571 		},
1572 	},
1573 };
1574 
1575 static struct clk_branch gcc_pcie0_pipe_clk = {
1576 	.halt_reg = 0x28044,
1577 	.halt_check = BRANCH_HALT_DELAY,
1578 	.clkr = {
1579 		.enable_reg = 0x28044,
1580 		.enable_mask = BIT(0),
1581 		.hw.init = &(const struct clk_init_data) {
1582 			.name = "gcc_pcie0_pipe_clk",
1583 			.parent_hws = (const struct clk_hw *[]) {
1584 				&pcie0_pipe_clk_src.clkr.hw
1585 			},
1586 			.num_parents = 1,
1587 			.flags = CLK_SET_RATE_PARENT,
1588 			.ops = &clk_branch2_ops,
1589 		},
1590 	},
1591 };
1592 
1593 static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
1594 	.reg = 0x29064,
1595 	.clkr = {
1596 		.hw.init = &(const struct clk_init_data) {
1597 			.name = "pcie1_pipe_clk_src",
1598 			.parent_data = &(const struct clk_parent_data) {
1599 				.index = DT_PCIE30_PHY1_PIPE_CLK,
1600 			},
1601 			.num_parents = 1,
1602 			.ops = &clk_regmap_phy_mux_ops,
1603 		},
1604 	},
1605 };
1606 
1607 static struct clk_branch gcc_pcie1_pipe_clk = {
1608 	.halt_reg = 0x29044,
1609 	.halt_check = BRANCH_HALT_DELAY,
1610 	.clkr = {
1611 		.enable_reg = 0x29044,
1612 		.enable_mask = BIT(0),
1613 		.hw.init = &(const struct clk_init_data) {
1614 			.name = "gcc_pcie1_pipe_clk",
1615 			.parent_hws = (const struct clk_hw *[]) {
1616 				&pcie1_pipe_clk_src.clkr.hw
1617 			},
1618 			.num_parents = 1,
1619 			.flags = CLK_SET_RATE_PARENT,
1620 			.ops = &clk_branch2_ops,
1621 		},
1622 	},
1623 };
1624 
1625 static struct clk_regmap_phy_mux pcie2_pipe_clk_src = {
1626 	.reg = 0x2a064,
1627 	.clkr = {
1628 		.hw.init = &(const struct clk_init_data) {
1629 			.name = "pcie2_pipe_clk_src",
1630 			.parent_data = &(const struct clk_parent_data) {
1631 				.index = DT_PCIE30_PHY2_PIPE_CLK,
1632 			},
1633 			.num_parents = 1,
1634 			.ops = &clk_regmap_phy_mux_ops,
1635 		},
1636 	},
1637 };
1638 
1639 static struct clk_branch gcc_pcie2_pipe_clk = {
1640 	.halt_reg = 0x2a044,
1641 	.halt_check = BRANCH_HALT_DELAY,
1642 	.clkr = {
1643 		.enable_reg = 0x2a044,
1644 		.enable_mask = BIT(0),
1645 		.hw.init = &(const struct clk_init_data) {
1646 			.name = "gcc_pcie2_pipe_clk",
1647 			.parent_hws = (const struct clk_hw *[]) {
1648 				&pcie2_pipe_clk_src.clkr.hw
1649 			},
1650 			.num_parents = 1,
1651 			.flags = CLK_SET_RATE_PARENT,
1652 			.ops = &clk_branch2_ops,
1653 		},
1654 	},
1655 };
1656 
1657 static struct clk_regmap_phy_mux pcie3_pipe_clk_src = {
1658 	.reg = 0x2b064,
1659 	.clkr = {
1660 		.hw.init = &(const struct clk_init_data) {
1661 			.name = "pcie3_pipe_clk_src",
1662 			.parent_data = &(const struct clk_parent_data) {
1663 				.index = DT_PCIE30_PHY3_PIPE_CLK,
1664 			},
1665 			.num_parents = 1,
1666 			.ops = &clk_regmap_phy_mux_ops,
1667 		},
1668 	},
1669 };
1670 
1671 static struct clk_branch gcc_pcie3_pipe_clk = {
1672 	.halt_reg = 0x2b044,
1673 	.halt_check = BRANCH_HALT_DELAY,
1674 	.clkr = {
1675 		.enable_reg = 0x2b044,
1676 		.enable_mask = BIT(0),
1677 		.hw.init = &(const struct clk_init_data) {
1678 			.name = "gcc_pcie3_pipe_clk",
1679 			.parent_hws = (const struct clk_hw *[]) {
1680 				&pcie3_pipe_clk_src.clkr.hw
1681 			},
1682 			.num_parents = 1,
1683 			.flags = CLK_SET_RATE_PARENT,
1684 			.ops = &clk_branch2_ops,
1685 		},
1686 	},
1687 };
1688 
1689 static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
1690 	F(24000000, P_XO, 1, 0, 0),
1691 	F(100000000, P_GPLL0, 8, 0, 0),
1692 	{ }
1693 };
1694 
1695 static struct clk_rcg2 pcie0_rchng_clk_src = {
1696 	.cmd_rcgr = 0x28028,
1697 	.freq_tbl = ftbl_pcie_rchng_clk_src,
1698 	.hid_width = 5,
1699 	.parent_map = gcc_xo_gpll0_map,
1700 	.clkr.hw.init = &(const struct clk_init_data) {
1701 		.name = "pcie0_rchng_clk_src",
1702 		.parent_data = gcc_xo_gpll0,
1703 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1704 		.ops = &clk_rcg2_ops,
1705 	},
1706 };
1707 
1708 static struct clk_branch gcc_pcie0_rchng_clk = {
1709 	.halt_reg = 0x28028,
1710 	.clkr = {
1711 		.enable_reg = 0x28028,
1712 		.enable_mask = BIT(1),
1713 		.hw.init = &(const struct clk_init_data) {
1714 			.name = "gcc_pcie0_rchng_clk",
1715 			.parent_hws = (const struct clk_hw *[]) {
1716 				&pcie0_rchng_clk_src.clkr.hw
1717 
1718 			},
1719 			.num_parents = 1,
1720 			.flags = CLK_SET_RATE_PARENT,
1721 			.ops = &clk_branch2_ops,
1722 		},
1723 	},
1724 };
1725 
1726 static struct clk_rcg2 pcie1_rchng_clk_src = {
1727 	.cmd_rcgr = 0x29028,
1728 	.freq_tbl = ftbl_pcie_rchng_clk_src,
1729 	.hid_width = 5,
1730 	.parent_map = gcc_xo_gpll0_map,
1731 	.clkr.hw.init = &(const struct clk_init_data) {
1732 		.name = "pcie1_rchng_clk_src",
1733 		.parent_data = gcc_xo_gpll0,
1734 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1735 		.ops = &clk_rcg2_ops,
1736 	},
1737 };
1738 
1739 static struct clk_branch gcc_pcie1_rchng_clk = {
1740 	.halt_reg = 0x29028,
1741 	.clkr = {
1742 		.enable_reg = 0x29028,
1743 		.enable_mask = BIT(1),
1744 		.hw.init = &(const struct clk_init_data) {
1745 			.name = "gcc_pcie1_rchng_clk",
1746 			.parent_hws = (const struct clk_hw *[]) {
1747 				&pcie1_rchng_clk_src.clkr.hw
1748 			},
1749 			.num_parents = 1,
1750 			.flags = CLK_SET_RATE_PARENT,
1751 			.ops = &clk_branch2_ops,
1752 		},
1753 	},
1754 };
1755 
1756 static struct clk_rcg2 pcie2_rchng_clk_src = {
1757 	.cmd_rcgr = 0x2a028,
1758 	.freq_tbl = ftbl_pcie_rchng_clk_src,
1759 	.hid_width = 5,
1760 	.parent_map = gcc_xo_gpll0_map,
1761 	.clkr.hw.init = &(const struct clk_init_data) {
1762 		.name = "pcie2_rchng_clk_src",
1763 		.parent_data = gcc_xo_gpll0,
1764 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1765 		.ops = &clk_rcg2_ops,
1766 	},
1767 };
1768 
1769 static struct clk_branch gcc_pcie2_rchng_clk = {
1770 	.halt_reg = 0x2a028,
1771 	.clkr = {
1772 		.enable_reg = 0x2a028,
1773 		.enable_mask = BIT(1),
1774 		.hw.init = &(const struct clk_init_data) {
1775 			.name = "gcc_pcie2_rchng_clk",
1776 			.parent_hws = (const struct clk_hw *[]) {
1777 				&pcie2_rchng_clk_src.clkr.hw
1778 			},
1779 			.num_parents = 1,
1780 			.flags = CLK_SET_RATE_PARENT,
1781 			.ops = &clk_branch2_ops,
1782 		},
1783 	},
1784 };
1785 
1786 static struct clk_rcg2 pcie3_rchng_clk_src = {
1787 	.cmd_rcgr = 0x2b028,
1788 	.freq_tbl = ftbl_pcie_rchng_clk_src,
1789 	.hid_width = 5,
1790 	.parent_map = gcc_xo_gpll0_map,
1791 	.clkr.hw.init = &(const struct clk_init_data) {
1792 		.name = "pcie3_rchng_clk_src",
1793 		.parent_data = gcc_xo_gpll0,
1794 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1795 		.ops = &clk_rcg2_ops,
1796 	},
1797 };
1798 
1799 static struct clk_branch gcc_pcie3_rchng_clk = {
1800 	.halt_reg = 0x2b028,
1801 	.clkr = {
1802 		.enable_reg = 0x2b028,
1803 		.enable_mask = BIT(1),
1804 		.hw.init = &(const struct clk_init_data) {
1805 			.name = "gcc_pcie3_rchng_clk",
1806 			.parent_hws = (const struct clk_hw *[]) {
1807 				&pcie3_rchng_clk_src.clkr.hw
1808 			},
1809 			.num_parents = 1,
1810 			.flags = CLK_SET_RATE_PARENT,
1811 			.ops = &clk_branch2_ops,
1812 		},
1813 	},
1814 };
1815 
1816 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
1817 	F(20000000, P_GPLL0, 10, 1, 4),
1818 	{ }
1819 };
1820 
1821 static struct clk_rcg2 pcie_aux_clk_src = {
1822 	.cmd_rcgr = 0x28004,
1823 	.freq_tbl = ftbl_pcie_aux_clk_src,
1824 	.mnd_width = 16,
1825 	.hid_width = 5,
1826 	.parent_map = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk_map,
1827 	.clkr.hw.init = &(const struct clk_init_data) {
1828 		.name = "pcie_aux_clk_src",
1829 		.parent_data = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk,
1830 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk),
1831 		.ops = &clk_rcg2_ops,
1832 	},
1833 };
1834 
1835 static struct clk_branch gcc_pcie0_aux_clk = {
1836 	.halt_reg = 0x28034,
1837 	.clkr = {
1838 		.enable_reg = 0x28034,
1839 		.enable_mask = BIT(0),
1840 		.hw.init = &(const struct clk_init_data) {
1841 			.name = "gcc_pcie0_aux_clk",
1842 			.parent_hws = (const struct clk_hw *[]) {
1843 				&pcie_aux_clk_src.clkr.hw
1844 			},
1845 			.num_parents = 1,
1846 			.flags = CLK_SET_RATE_PARENT,
1847 			.ops = &clk_branch2_ops,
1848 		},
1849 	},
1850 };
1851 
1852 static struct clk_branch gcc_pcie1_aux_clk = {
1853 	.halt_reg = 0x29034,
1854 	.clkr = {
1855 		.enable_reg = 0x29034,
1856 		.enable_mask = BIT(0),
1857 		.hw.init = &(const struct clk_init_data) {
1858 			.name = "gcc_pcie1_aux_clk",
1859 			.parent_hws = (const struct clk_hw *[]) {
1860 				&pcie_aux_clk_src.clkr.hw
1861 			},
1862 			.num_parents = 1,
1863 			.flags = CLK_SET_RATE_PARENT,
1864 			.ops = &clk_branch2_ops,
1865 		},
1866 	},
1867 };
1868 
1869 static struct clk_branch gcc_pcie2_aux_clk = {
1870 	.halt_reg = 0x2a034,
1871 	.clkr = {
1872 		.enable_reg = 0x2a034,
1873 		.enable_mask = BIT(0),
1874 		.hw.init = &(const struct clk_init_data) {
1875 			.name = "gcc_pcie2_aux_clk",
1876 			.parent_hws = (const struct clk_hw *[]) {
1877 				&pcie_aux_clk_src.clkr.hw
1878 			},
1879 			.num_parents = 1,
1880 			.flags = CLK_SET_RATE_PARENT,
1881 			.ops = &clk_branch2_ops,
1882 		},
1883 	},
1884 };
1885 
1886 static struct clk_branch gcc_pcie3_aux_clk = {
1887 	.halt_reg = 0x2b034,
1888 	.clkr = {
1889 		.enable_reg = 0x2b034,
1890 		.enable_mask = BIT(0),
1891 		.hw.init = &(const struct clk_init_data) {
1892 			.name = "gcc_pcie3_aux_clk",
1893 			.parent_hws = (const struct clk_hw *[]) {
1894 				&pcie_aux_clk_src.clkr.hw
1895 			},
1896 			.num_parents = 1,
1897 			.flags = CLK_SET_RATE_PARENT,
1898 			.ops = &clk_branch2_ops,
1899 		},
1900 	},
1901 };
1902 
1903 static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
1904 	F(24000000, P_XO, 1, 0, 0),
1905 	{ }
1906 };
1907 
1908 static struct clk_rcg2 usb0_aux_clk_src = {
1909 	.cmd_rcgr = 0x2c018,
1910 	.freq_tbl = ftbl_usb_aux_clk_src,
1911 	.mnd_width = 16,
1912 	.hid_width = 5,
1913 	.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
1914 	.clkr.hw.init = &(const struct clk_init_data) {
1915 		.name = "usb0_aux_clk_src",
1916 		.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
1917 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
1918 		.ops = &clk_rcg2_ops,
1919 	},
1920 };
1921 
1922 static struct clk_branch gcc_usb0_aux_clk = {
1923 	.halt_reg = 0x2c048,
1924 	.clkr = {
1925 		.enable_reg = 0x2c048,
1926 		.enable_mask = BIT(0),
1927 		.hw.init = &(const struct clk_init_data) {
1928 			.name = "gcc_usb0_aux_clk",
1929 			.parent_hws = (const struct clk_hw *[]) {
1930 				&usb0_aux_clk_src.clkr.hw
1931 			},
1932 			.num_parents = 1,
1933 			.flags = CLK_SET_RATE_PARENT,
1934 			.ops = &clk_branch2_ops,
1935 		},
1936 	},
1937 };
1938 
1939 static const struct freq_tbl ftbl_usb0_master_clk_src[] = {
1940 	F(100000000, P_GPLL0, 8, 0, 0),
1941 	F(200000000, P_GPLL0, 4, 0, 0),
1942 	{ }
1943 };
1944 
1945 static struct clk_rcg2 usb0_master_clk_src = {
1946 	.cmd_rcgr = 0x2c004,
1947 	.freq_tbl = ftbl_usb0_master_clk_src,
1948 	.mnd_width = 8,
1949 	.hid_width = 5,
1950 	.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1951 	.clkr.hw.init = &(const struct clk_init_data) {
1952 		.name = "usb0_master_clk_src",
1953 		.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
1954 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
1955 		.ops = &clk_rcg2_ops,
1956 	},
1957 };
1958 
1959 static struct clk_branch gcc_usb0_master_clk = {
1960 	.halt_reg = 0x2c044,
1961 	.clkr = {
1962 		.enable_reg = 0x2c044,
1963 		.enable_mask = BIT(0),
1964 		.hw.init = &(const struct clk_init_data) {
1965 			.name = "gcc_usb0_master_clk",
1966 			.parent_hws = (const struct clk_hw *[]) {
1967 				&usb0_master_clk_src.clkr.hw
1968 			},
1969 			.num_parents = 1,
1970 			.flags = CLK_SET_RATE_PARENT,
1971 			.ops = &clk_branch2_ops,
1972 		},
1973 	},
1974 };
1975 
1976 static struct clk_branch gcc_snoc_usb_clk = {
1977 	.halt_reg = 0x2e058,
1978 	.clkr = {
1979 		.enable_reg = 0x2e058,
1980 		.enable_mask = BIT(0),
1981 		.hw.init = &(const struct clk_init_data) {
1982 			.name = "gcc_snoc_usb_clk",
1983 			.parent_hws = (const struct clk_hw *[]) {
1984 				&usb0_master_clk_src.clkr.hw
1985 			},
1986 			.num_parents = 1,
1987 			.flags = CLK_SET_RATE_PARENT,
1988 			.ops = &clk_branch2_ops,
1989 		},
1990 	},
1991 };
1992 
1993 static struct clk_branch gcc_anoc_usb_axi_clk = {
1994 	.halt_reg = 0x2e084,
1995 	.clkr = {
1996 		.enable_reg = 0x2e084,
1997 		.enable_mask = BIT(0),
1998 		.hw.init = &(const struct clk_init_data) {
1999 			.name = "gcc_anoc_usb_axi_clk",
2000 			.parent_hws = (const struct clk_hw *[]) {
2001 				&usb0_master_clk_src.clkr.hw
2002 			},
2003 			.num_parents = 1,
2004 			.flags = CLK_SET_RATE_PARENT,
2005 			.ops = &clk_branch2_ops,
2006 		},
2007 	},
2008 };
2009 
2010 static const struct freq_tbl ftbl_usb0_mock_utmi_clk_src[] = {
2011 	F(24000000, P_XO, 1, 0, 0),
2012 	F(60000000, P_GPLL4, 10, 1, 2),
2013 	{ }
2014 };
2015 
2016 static struct clk_rcg2 usb0_mock_utmi_clk_src = {
2017 	.cmd_rcgr = 0x2c02c,
2018 	.freq_tbl = ftbl_usb0_mock_utmi_clk_src,
2019 	.mnd_width = 8,
2020 	.hid_width = 5,
2021 	.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map,
2022 	.clkr.hw.init = &(const struct clk_init_data) {
2023 		.name = "usb0_mock_utmi_clk_src",
2024 		.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
2025 		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
2026 		.ops = &clk_rcg2_ops,
2027 	},
2028 };
2029 
2030 static struct clk_regmap_div usb0_mock_utmi_div_clk_src = {
2031 	.reg = 0x2c040,
2032 	.shift = 0,
2033 	.width = 2,
2034 	.clkr.hw.init = &(const struct clk_init_data) {
2035 		.name = "usb0_mock_utmi_div_clk_src",
2036 		.parent_data = &(const struct clk_parent_data) {
2037 			.hw = &usb0_mock_utmi_clk_src.clkr.hw,
2038 		},
2039 		.num_parents = 1,
2040 		.flags = CLK_SET_RATE_PARENT,
2041 		.ops = &clk_regmap_div_ro_ops,
2042 	},
2043 };
2044 
2045 static struct clk_branch gcc_usb0_mock_utmi_clk = {
2046 	.halt_reg = 0x2c04c,
2047 	.clkr = {
2048 		.enable_reg = 0x2c04c,
2049 		.enable_mask = BIT(0),
2050 		.hw.init = &(const struct clk_init_data) {
2051 			.name = "gcc_usb0_mock_utmi_clk",
2052 			.parent_hws = (const struct clk_hw *[]) {
2053 				&usb0_mock_utmi_div_clk_src.clkr.hw
2054 			},
2055 			.num_parents = 1,
2056 			.flags = CLK_SET_RATE_PARENT,
2057 			.ops = &clk_branch2_ops,
2058 		},
2059 	},
2060 };
2061 
2062 static struct clk_regmap_mux usb0_pipe_clk_src = {
2063 	.reg = 0x2C074,
2064 	.shift = 8,
2065 	.width = 2,
2066 	.parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
2067 	.clkr = {
2068 		.hw.init = &(const struct clk_init_data) {
2069 			.name = "usb0_pipe_clk_src",
2070 			.parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
2071 			.num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
2072 			.flags = CLK_SET_RATE_PARENT,
2073 			.ops = &clk_regmap_mux_closest_ops,
2074 		},
2075 	},
2076 };
2077 
2078 static struct clk_branch gcc_usb0_pipe_clk = {
2079 	.halt_reg = 0x2c054,
2080 	.halt_check = BRANCH_HALT_DELAY,
2081 	.clkr = {
2082 		.enable_reg = 0x2c054,
2083 		.enable_mask = BIT(0),
2084 		.hw.init = &(const struct clk_init_data){
2085 			.name = "gcc_usb0_pipe_clk",
2086 			.parent_hws = (const struct clk_hw *[]) {
2087 				&usb0_pipe_clk_src.clkr.hw
2088 			},
2089 			.num_parents = 1,
2090 			.flags = CLK_SET_RATE_PARENT,
2091 			.ops = &clk_branch2_ops,
2092 		},
2093 	},
2094 };
2095 
2096 static struct clk_branch gcc_usb0_sleep_clk = {
2097 	.halt_reg = 0x2c058,
2098 	.clkr = {
2099 		.enable_reg = 0x2c058,
2100 		.enable_mask = BIT(0),
2101 		.hw.init = &(const struct clk_init_data){
2102 			.name = "gcc_usb0_sleep_clk",
2103 			.parent_hws = (const struct clk_hw *[]) {
2104 				&gcc_sleep_clk_src.clkr.hw
2105 			},
2106 			.num_parents = 1,
2107 			.flags = CLK_SET_RATE_PARENT,
2108 			.ops = &clk_branch2_ops,
2109 		},
2110 	},
2111 };
2112 
2113 static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
2114 	F(144000, P_XO, 16, 12, 125),
2115 	F(400000, P_XO, 12, 1, 5),
2116 	F(24000000, P_GPLL2, 12, 1, 4),
2117 	F(48000000, P_GPLL2, 12, 1, 2),
2118 	F(96000000, P_GPLL2, 12, 0, 0),
2119 	F(177777778, P_GPLL0, 4.5, 0, 0),
2120 	F(192000000, P_GPLL2, 6, 0, 0),
2121 	F(384000000, P_GPLL2, 3, 0, 0),
2122 	F(400000000, P_GPLL0, 2, 0, 0),
2123 	{ }
2124 };
2125 
2126 static struct clk_rcg2 sdcc1_apps_clk_src = {
2127 	.cmd_rcgr = 0x33004,
2128 	.freq_tbl = ftbl_sdcc_apps_clk_src,
2129 	.mnd_width = 8,
2130 	.hid_width = 5,
2131 	.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
2132 	.clkr.hw.init = &(const struct clk_init_data) {
2133 		.name = "sdcc1_apps_clk_src",
2134 		.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
2135 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
2136 		.ops = &clk_rcg2_floor_ops,
2137 	},
2138 };
2139 
2140 static struct clk_branch gcc_sdcc1_apps_clk = {
2141 	.halt_reg = 0x3302c,
2142 	.clkr = {
2143 		.enable_reg = 0x3302c,
2144 		.enable_mask = BIT(0),
2145 		.hw.init = &(const struct clk_init_data) {
2146 			.name = "gcc_sdcc1_apps_clk",
2147 			.parent_hws = (const struct clk_hw *[]) {
2148 				&sdcc1_apps_clk_src.clkr.hw
2149 			},
2150 			.num_parents = 1,
2151 			.flags = CLK_SET_RATE_PARENT,
2152 			.ops = &clk_branch2_ops,
2153 		},
2154 	},
2155 };
2156 
2157 static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
2158 	F(150000000, P_GPLL4, 8, 0, 0),
2159 	F(300000000, P_GPLL4, 4, 0, 0),
2160 	{ }
2161 };
2162 
2163 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
2164 	.cmd_rcgr = 0x33018,
2165 	.freq_tbl = ftbl_sdcc_ice_core_clk_src,
2166 	.mnd_width = 8,
2167 	.hid_width = 5,
2168 	.parent_map = gcc_xo_gpll0_gpll4_gpll0_div2_map,
2169 	.clkr.hw.init = &(const struct clk_init_data) {
2170 		.name = "sdcc1_ice_core_clk_src",
2171 		.parent_data = gcc_xo_gpll0_gpll4_gpll0_div2,
2172 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_div2),
2173 		.ops = &clk_rcg2_ops,
2174 	},
2175 };
2176 
2177 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2178 	.halt_reg = 0x33030,
2179 	.clkr = {
2180 		.enable_reg = 0x33030,
2181 		.enable_mask = BIT(0),
2182 		.hw.init = &(const struct clk_init_data) {
2183 			.name = "gcc_sdcc1_ice_core_clk",
2184 			.parent_hws = (const struct clk_hw *[]) {
2185 				&sdcc1_ice_core_clk_src.clkr.hw
2186 			},
2187 			.num_parents = 1,
2188 			.flags = CLK_SET_RATE_PARENT,
2189 			.ops = &clk_branch2_ops,
2190 		},
2191 	},
2192 };
2193 
2194 static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
2195 	F(24000000, P_XO, 1, 0, 0),
2196 	F(50000000, P_GPLL0, 16, 0, 0),
2197 	F(80000000, P_GPLL0, 10, 0, 0),
2198 	F(100000000, P_GPLL0, 8, 0, 0),
2199 	{ }
2200 };
2201 
2202 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
2203 	.cmd_rcgr = 0x31004,
2204 	.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
2205 	.hid_width = 5,
2206 	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
2207 	.clkr.hw.init = &(const struct clk_init_data) {
2208 		.name = "pcnoc_bfdcd_clk_src",
2209 		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
2210 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
2211 		.flags = CLK_IS_CRITICAL,
2212 		.ops = &clk_rcg2_ops,
2213 	},
2214 };
2215 
2216 static struct clk_branch gcc_crypto_axi_clk = {
2217 	.halt_reg = 0x16010,
2218 	.halt_check = BRANCH_HALT_VOTED,
2219 	.clkr = {
2220 		.enable_reg = 0xb004,
2221 		.enable_mask = BIT(15),
2222 		.hw.init = &(const struct clk_init_data) {
2223 			.name = "gcc_crypto_axi_clk",
2224 			.parent_hws = (const struct clk_hw *[]) {
2225 				&pcnoc_bfdcd_clk_src.clkr.hw },
2226 			.num_parents = 1,
2227 			.flags = CLK_SET_RATE_PARENT,
2228 			.ops = &clk_branch2_ops,
2229 		},
2230 	},
2231 };
2232 
2233 static struct clk_branch gcc_crypto_ahb_clk = {
2234 	.halt_reg = 0x16014,
2235 	.halt_check = BRANCH_HALT_VOTED,
2236 	.clkr = {
2237 		.enable_reg = 0xb004,
2238 		.enable_mask = BIT(16),
2239 		.hw.init = &(const struct clk_init_data) {
2240 			.name = "gcc_crypto_ahb_clk",
2241 			.parent_hws = (const struct clk_hw *[]) {
2242 				&pcnoc_bfdcd_clk_src.clkr.hw },
2243 			.num_parents = 1,
2244 			.flags = CLK_SET_RATE_PARENT,
2245 			.ops = &clk_branch2_ops,
2246 		},
2247 	},
2248 };
2249 
2250 static struct clk_branch gcc_nsscfg_clk = {
2251 	.halt_reg = 0x1702c,
2252 	.clkr = {
2253 		.enable_reg = 0x1702c,
2254 		.enable_mask = BIT(0),
2255 		.hw.init = &(const struct clk_init_data) {
2256 			.name = "gcc_nsscfg_clk",
2257 			.parent_hws = (const struct clk_hw *[]) {
2258 				&pcnoc_bfdcd_clk_src.clkr.hw
2259 			},
2260 			.num_parents = 1,
2261 			.flags = CLK_SET_RATE_PARENT,
2262 			.ops = &clk_branch2_ops,
2263 		},
2264 	},
2265 };
2266 
2267 static struct clk_branch gcc_nssnoc_nsscc_clk = {
2268 	.halt_reg = 0x17030,
2269 	.clkr = {
2270 		.enable_reg = 0x17030,
2271 		.enable_mask = BIT(0),
2272 		.hw.init = &(const struct clk_init_data) {
2273 			.name = "gcc_nssnoc_nsscc_clk",
2274 			.parent_hws = (const struct clk_hw *[]) {
2275 				&pcnoc_bfdcd_clk_src.clkr.hw
2276 			},
2277 			.num_parents = 1,
2278 			.flags = CLK_SET_RATE_PARENT,
2279 			.ops = &clk_branch2_ops,
2280 		},
2281 	},
2282 };
2283 
2284 static struct clk_branch gcc_nsscc_clk = {
2285 	.halt_reg = 0x17034,
2286 	.clkr = {
2287 		.enable_reg = 0x17034,
2288 		.enable_mask = BIT(0),
2289 		.hw.init = &(const struct clk_init_data) {
2290 			.name = "gcc_nsscc_clk",
2291 			.parent_hws = (const struct clk_hw *[]) {
2292 				&pcnoc_bfdcd_clk_src.clkr.hw
2293 			},
2294 			.num_parents = 1,
2295 			.flags = CLK_SET_RATE_PARENT,
2296 			.ops = &clk_branch2_ops,
2297 		},
2298 	},
2299 };
2300 
2301 static struct clk_branch gcc_nssnoc_pcnoc_1_clk = {
2302 	.halt_reg = 0x17080,
2303 	.clkr = {
2304 		.enable_reg = 0x17080,
2305 		.enable_mask = BIT(0),
2306 		.hw.init = &(const struct clk_init_data) {
2307 			.name = "gcc_nssnoc_pcnoc_1_clk",
2308 			.parent_hws = (const struct clk_hw *[]) {
2309 				&pcnoc_bfdcd_clk_src.clkr.hw
2310 			},
2311 			.num_parents = 1,
2312 			.flags = CLK_SET_RATE_PARENT,
2313 			.ops = &clk_branch2_ops,
2314 		},
2315 	},
2316 };
2317 
2318 static struct clk_branch gcc_qdss_dap_ahb_clk = {
2319 	.halt_reg = 0x2d064,
2320 	.clkr = {
2321 		.enable_reg = 0x2d064,
2322 		.enable_mask = BIT(0),
2323 		.hw.init = &(const struct clk_init_data) {
2324 			.name = "gcc_qdss_dap_ahb_clk",
2325 			.parent_hws = (const struct clk_hw *[]) {
2326 				&pcnoc_bfdcd_clk_src.clkr.hw
2327 			},
2328 			.num_parents = 1,
2329 			.flags = CLK_SET_RATE_PARENT,
2330 			.ops = &clk_branch2_ops,
2331 		},
2332 	},
2333 };
2334 
2335 static struct clk_branch gcc_qdss_cfg_ahb_clk = {
2336 	.halt_reg = 0x2d068,
2337 	.clkr = {
2338 		.enable_reg = 0x2d068,
2339 		.enable_mask = BIT(0),
2340 		.hw.init = &(const struct clk_init_data) {
2341 			.name = "gcc_qdss_cfg_ahb_clk",
2342 			.parent_hws = (const struct clk_hw *[]) {
2343 				&pcnoc_bfdcd_clk_src.clkr.hw
2344 			},
2345 			.num_parents = 1,
2346 			.flags = CLK_SET_RATE_PARENT,
2347 			.ops = &clk_branch2_ops,
2348 		},
2349 	},
2350 };
2351 
2352 static struct clk_branch gcc_qpic_ahb_clk = {
2353 	.halt_reg = 0x32010,
2354 	.clkr = {
2355 		.enable_reg = 0x32010,
2356 		.enable_mask = BIT(0),
2357 		.hw.init = &(const struct clk_init_data) {
2358 			.name = "gcc_qpic_ahb_clk",
2359 			.parent_hws = (const struct clk_hw *[]) {
2360 				&pcnoc_bfdcd_clk_src.clkr.hw
2361 			},
2362 			.num_parents = 1,
2363 			.flags = CLK_SET_RATE_PARENT,
2364 			.ops = &clk_branch2_ops,
2365 		},
2366 	},
2367 };
2368 
2369 static struct clk_branch gcc_qpic_clk = {
2370 	.halt_reg = 0x32014,
2371 	.clkr = {
2372 		.enable_reg = 0x32014,
2373 		.enable_mask = BIT(0),
2374 		.hw.init = &(const struct clk_init_data) {
2375 			.name = "gcc_qpic_clk",
2376 			.parent_hws = (const struct clk_hw *[]) {
2377 				&pcnoc_bfdcd_clk_src.clkr.hw
2378 			},
2379 			.num_parents = 1,
2380 			.flags = CLK_SET_RATE_PARENT,
2381 			.ops = &clk_branch2_ops,
2382 		},
2383 	},
2384 };
2385 
2386 static struct clk_branch gcc_blsp1_ahb_clk = {
2387 	.halt_reg = 0x01004,
2388 	.halt_check = BRANCH_HALT_VOTED,
2389 	.clkr = {
2390 		.enable_reg = 0x0b004,
2391 		.enable_mask = BIT(4),
2392 		.hw.init = &(const struct clk_init_data) {
2393 			.name = "gcc_blsp1_ahb_clk",
2394 			.parent_hws = (const struct clk_hw *[]) {
2395 				&pcnoc_bfdcd_clk_src.clkr.hw
2396 			},
2397 			.num_parents = 1,
2398 			.flags = CLK_SET_RATE_PARENT,
2399 			.ops = &clk_branch2_ops,
2400 		},
2401 	},
2402 };
2403 
2404 static struct clk_branch gcc_mdio_ahb_clk = {
2405 	.halt_reg = 0x17040,
2406 	.clkr = {
2407 		.enable_reg = 0x17040,
2408 		.enable_mask = BIT(0),
2409 		.hw.init = &(const struct clk_init_data) {
2410 			.name = "gcc_mdio_ahb_clk",
2411 			.parent_hws = (const struct clk_hw *[]) {
2412 				&pcnoc_bfdcd_clk_src.clkr.hw
2413 			},
2414 			.num_parents = 1,
2415 			.flags = CLK_SET_RATE_PARENT,
2416 			.ops = &clk_branch2_ops,
2417 		},
2418 	},
2419 };
2420 
2421 static struct clk_branch gcc_prng_ahb_clk = {
2422 	.halt_reg = 0x13024,
2423 	.halt_check = BRANCH_HALT_VOTED,
2424 	.clkr = {
2425 		.enable_reg = 0x0b004,
2426 		.enable_mask = BIT(10),
2427 		.hw.init = &(const struct clk_init_data) {
2428 			.name = "gcc_prng_ahb_clk",
2429 			.parent_hws = (const struct clk_hw *[]) {
2430 				&pcnoc_bfdcd_clk_src.clkr.hw
2431 			},
2432 			.num_parents = 1,
2433 			.flags = CLK_SET_RATE_PARENT,
2434 			.ops = &clk_branch2_ops,
2435 		},
2436 	},
2437 };
2438 
2439 static struct clk_branch gcc_uniphy0_ahb_clk = {
2440 	.halt_reg = 0x1704c,
2441 	.clkr = {
2442 		.enable_reg = 0x1704c,
2443 		.enable_mask = BIT(0),
2444 		.hw.init = &(const struct clk_init_data) {
2445 			.name = "gcc_uniphy0_ahb_clk",
2446 			.parent_hws = (const struct clk_hw *[]) {
2447 				&pcnoc_bfdcd_clk_src.clkr.hw
2448 			},
2449 			.num_parents = 1,
2450 			.flags = CLK_SET_RATE_PARENT,
2451 			.ops = &clk_branch2_ops,
2452 		},
2453 	},
2454 };
2455 
2456 static struct clk_branch gcc_uniphy1_ahb_clk = {
2457 	.halt_reg = 0x1705c,
2458 	.clkr = {
2459 		.enable_reg = 0x1705c,
2460 		.enable_mask = BIT(0),
2461 		.hw.init = &(const struct clk_init_data) {
2462 			.name = "gcc_uniphy1_ahb_clk",
2463 			.parent_hws = (const struct clk_hw *[]) {
2464 				&pcnoc_bfdcd_clk_src.clkr.hw
2465 			},
2466 			.num_parents = 1,
2467 			.flags = CLK_SET_RATE_PARENT,
2468 			.ops = &clk_branch2_ops,
2469 		},
2470 	},
2471 };
2472 
2473 static struct clk_branch gcc_uniphy2_ahb_clk = {
2474 	.halt_reg = 0x1706c,
2475 	.clkr = {
2476 		.enable_reg = 0x1706c,
2477 		.enable_mask = BIT(0),
2478 		.hw.init = &(const struct clk_init_data) {
2479 			.name = "gcc_uniphy2_ahb_clk",
2480 			.parent_hws = (const struct clk_hw *[]) {
2481 				&pcnoc_bfdcd_clk_src.clkr.hw
2482 			},
2483 			.num_parents = 1,
2484 			.flags = CLK_SET_RATE_PARENT,
2485 			.ops = &clk_branch2_ops,
2486 		},
2487 	},
2488 };
2489 
2490 static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
2491 	.halt_reg = 0x3a004,
2492 	.clkr = {
2493 		.enable_reg = 0x3a004,
2494 		.enable_mask = BIT(0),
2495 		.hw.init = &(const struct clk_init_data) {
2496 			.name = "gcc_cmn_12gpll_ahb_clk",
2497 			.parent_hws = (const struct clk_hw *[]) {
2498 				&pcnoc_bfdcd_clk_src.clkr.hw
2499 			},
2500 			.num_parents = 1,
2501 			.flags = CLK_SET_RATE_PARENT,
2502 			.ops = &clk_branch2_ops,
2503 		},
2504 	},
2505 };
2506 
2507 static struct clk_branch gcc_cmn_12gpll_apu_clk = {
2508 	.halt_reg = 0x3a00c,
2509 	.clkr = {
2510 		.enable_reg = 0x3a00c,
2511 		.enable_mask = BIT(0),
2512 		.hw.init = &(const struct clk_init_data) {
2513 			.name = "gcc_cmn_12gpll_apu_clk",
2514 			.parent_hws = (const struct clk_hw *[]) {
2515 				&pcnoc_bfdcd_clk_src.clkr.hw
2516 			},
2517 			.num_parents = 1,
2518 			.flags = CLK_SET_RATE_PARENT,
2519 			.ops = &clk_branch2_ops,
2520 		},
2521 	},
2522 };
2523 
2524 static struct clk_branch gcc_pcie0_ahb_clk = {
2525 	.halt_reg = 0x28030,
2526 	.clkr = {
2527 		.enable_reg = 0x28030,
2528 		.enable_mask = BIT(0),
2529 		.hw.init = &(const struct clk_init_data) {
2530 			.name = "gcc_pcie0_ahb_clk",
2531 			.parent_hws = (const struct clk_hw *[]) {
2532 				&pcnoc_bfdcd_clk_src.clkr.hw
2533 			},
2534 			.num_parents = 1,
2535 			.flags = CLK_SET_RATE_PARENT,
2536 			.ops = &clk_branch2_ops,
2537 		},
2538 	},
2539 };
2540 
2541 static struct clk_branch gcc_pcie1_ahb_clk = {
2542 	.halt_reg = 0x29030,
2543 	.clkr = {
2544 		.enable_reg = 0x29030,
2545 		.enable_mask = BIT(0),
2546 		.hw.init = &(const struct clk_init_data) {
2547 			.name = "gcc_pcie1_ahb_clk",
2548 			.parent_hws = (const struct clk_hw *[]) {
2549 				&pcnoc_bfdcd_clk_src.clkr.hw
2550 			},
2551 			.num_parents = 1,
2552 			.flags = CLK_SET_RATE_PARENT,
2553 			.ops = &clk_branch2_ops,
2554 		},
2555 	},
2556 };
2557 
2558 static struct clk_branch gcc_pcie2_ahb_clk = {
2559 	.halt_reg = 0x2a030,
2560 	.clkr = {
2561 		.enable_reg = 0x2a030,
2562 		.enable_mask = BIT(0),
2563 		.hw.init = &(const struct clk_init_data) {
2564 			.name = "gcc_pcie2_ahb_clk",
2565 			.parent_hws = (const struct clk_hw *[]) {
2566 				&pcnoc_bfdcd_clk_src.clkr.hw
2567 			},
2568 			.num_parents = 1,
2569 			.flags = CLK_SET_RATE_PARENT,
2570 			.ops = &clk_branch2_ops,
2571 		},
2572 	},
2573 };
2574 
2575 static struct clk_branch gcc_pcie3_ahb_clk = {
2576 	.halt_reg = 0x2b030,
2577 	.clkr = {
2578 		.enable_reg = 0x2b030,
2579 		.enable_mask = BIT(0),
2580 		.hw.init = &(const struct clk_init_data) {
2581 			.name = "gcc_pcie3_ahb_clk",
2582 			.parent_hws = (const struct clk_hw *[]) {
2583 				&pcnoc_bfdcd_clk_src.clkr.hw
2584 			},
2585 			.num_parents = 1,
2586 			.flags = CLK_SET_RATE_PARENT,
2587 			.ops = &clk_branch2_ops,
2588 		},
2589 	},
2590 };
2591 
2592 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
2593 	.halt_reg = 0x2c05c,
2594 	.clkr = {
2595 		.enable_reg = 0x2c05c,
2596 		.enable_mask = BIT(0),
2597 		.hw.init = &(const struct clk_init_data) {
2598 			.name = "gcc_usb0_phy_cfg_ahb_clk",
2599 			.parent_hws = (const struct clk_hw *[]) {
2600 				&pcnoc_bfdcd_clk_src.clkr.hw
2601 			},
2602 			.num_parents = 1,
2603 			.flags = CLK_SET_RATE_PARENT,
2604 			.ops = &clk_branch2_ops,
2605 		},
2606 	},
2607 };
2608 
2609 static struct clk_branch gcc_sdcc1_ahb_clk = {
2610 	.halt_reg = 0x33034,
2611 	.clkr = {
2612 		.enable_reg = 0x33034,
2613 		.enable_mask = BIT(0),
2614 		.hw.init = &(const struct clk_init_data) {
2615 			.name = "gcc_sdcc1_ahb_clk",
2616 			.parent_hws = (const struct clk_hw *[]) {
2617 				&pcnoc_bfdcd_clk_src.clkr.hw
2618 			},
2619 			.num_parents = 1,
2620 			.flags = CLK_SET_RATE_PARENT,
2621 			.ops = &clk_branch2_ops,
2622 		},
2623 	},
2624 };
2625 
2626 static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
2627 	F(24000000, P_XO, 1, 0, 0),
2628 	F(133333333, P_GPLL0, 6, 0, 0),
2629 	F(200000000, P_GPLL0, 4, 0, 0),
2630 	F(342850000, P_GPLL4, 3.5, 0, 0),
2631 	{ }
2632 };
2633 
2634 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
2635 	.cmd_rcgr = 0x2e004,
2636 	.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
2637 	.hid_width = 5,
2638 	.parent_map = gcc_xo_gpll0_gpll4_map,
2639 	.clkr.hw.init = &(const struct clk_init_data) {
2640 		.name = "system_noc_bfdcd_clk_src",
2641 		.parent_data = gcc_xo_gpll0_gpll4,
2642 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
2643 		.flags = CLK_IS_CRITICAL,
2644 		.ops = &clk_rcg2_ops,
2645 	},
2646 };
2647 
2648 static struct clk_branch gcc_q6ss_boot_clk = {
2649 	.halt_reg = 0x25080,
2650 	.halt_check = BRANCH_HALT_SKIP,
2651 	.clkr = {
2652 		.enable_reg = 0x25080,
2653 		.enable_mask = BIT(0),
2654 		.hw.init = &(const struct clk_init_data) {
2655 			.name = "gcc_q6ss_boot_clk",
2656 			.parent_hws = (const struct clk_hw *[]) {
2657 				&system_noc_bfdcd_clk_src.clkr.hw
2658 			},
2659 			.num_parents = 1,
2660 			.flags = CLK_SET_RATE_PARENT,
2661 			.ops = &clk_branch2_ops,
2662 		},
2663 	},
2664 };
2665 
2666 static struct clk_branch gcc_nssnoc_snoc_clk = {
2667 	.halt_reg = 0x17028,
2668 	.clkr = {
2669 		.enable_reg = 0x17028,
2670 		.enable_mask = BIT(0),
2671 		.hw.init = &(const struct clk_init_data) {
2672 			.name = "gcc_nssnoc_snoc_clk",
2673 			.parent_hws = (const struct clk_hw *[]) {
2674 				&system_noc_bfdcd_clk_src.clkr.hw
2675 			},
2676 			.num_parents = 1,
2677 			.flags = CLK_SET_RATE_PARENT,
2678 			.ops = &clk_branch2_ops,
2679 		},
2680 	},
2681 };
2682 
2683 static struct clk_branch gcc_nssnoc_snoc_1_clk = {
2684 	.halt_reg = 0x1707c,
2685 	.clkr = {
2686 		.enable_reg = 0x1707c,
2687 		.enable_mask = BIT(0),
2688 		.hw.init = &(const struct clk_init_data) {
2689 			.name = "gcc_nssnoc_snoc_1_clk",
2690 			.parent_hws = (const struct clk_hw *[]) {
2691 				&system_noc_bfdcd_clk_src.clkr.hw
2692 			},
2693 			.num_parents = 1,
2694 			.flags = CLK_SET_RATE_PARENT,
2695 			.ops = &clk_branch2_ops,
2696 		},
2697 	},
2698 };
2699 
2700 static struct clk_branch gcc_qdss_etr_usb_clk = {
2701 	.halt_reg = 0x2d060,
2702 	.clkr = {
2703 		.enable_reg = 0x2d060,
2704 		.enable_mask = BIT(0),
2705 		.hw.init = &(const struct clk_init_data) {
2706 			.name = "gcc_qdss_etr_usb_clk",
2707 			.parent_hws = (const struct clk_hw *[]) {
2708 				&system_noc_bfdcd_clk_src.clkr.hw
2709 			},
2710 			.num_parents = 1,
2711 			.flags = CLK_SET_RATE_PARENT,
2712 			.ops = &clk_branch2_ops,
2713 		},
2714 	},
2715 };
2716 
2717 static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
2718 	F(24000000, P_XO, 1, 0, 0),
2719 	F(133333333, P_GPLL0, 6, 0, 0),
2720 	{ }
2721 };
2722 
2723 static struct clk_rcg2 wcss_ahb_clk_src = {
2724 	.cmd_rcgr = 0x25030,
2725 	.freq_tbl = ftbl_wcss_ahb_clk_src,
2726 	.hid_width = 5,
2727 	.parent_map = gcc_xo_gpll0_map,
2728 	.clkr.hw.init = &(const struct clk_init_data) {
2729 		.name = "wcss_ahb_clk_src",
2730 		.parent_data = gcc_xo_gpll0,
2731 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
2732 		.ops = &clk_rcg2_ops,
2733 	},
2734 };
2735 
2736 static struct clk_branch gcc_q6_ahb_clk = {
2737 	.halt_reg = 0x25014,
2738 	.clkr = {
2739 		.enable_reg = 0x25014,
2740 		.enable_mask = BIT(0),
2741 		.hw.init = &(const struct clk_init_data) {
2742 			.name = "gcc_q6_ahb_clk",
2743 			.parent_hws = (const struct clk_hw *[]) {
2744 				&wcss_ahb_clk_src.clkr.hw
2745 			},
2746 			.num_parents = 1,
2747 			.flags = CLK_SET_RATE_PARENT,
2748 			.ops = &clk_branch2_ops,
2749 		},
2750 	},
2751 };
2752 
2753 static struct clk_branch gcc_q6_ahb_s_clk = {
2754 	.halt_reg = 0x25018,
2755 	.clkr = {
2756 		.enable_reg = 0x25018,
2757 		.enable_mask = BIT(0),
2758 		.hw.init = &(const struct clk_init_data) {
2759 			.name = "gcc_q6_ahb_s_clk",
2760 			.parent_hws = (const struct clk_hw *[]) {
2761 				&wcss_ahb_clk_src.clkr.hw
2762 			},
2763 			.num_parents = 1,
2764 			.flags = CLK_SET_RATE_PARENT,
2765 			.ops = &clk_branch2_ops,
2766 		},
2767 	},
2768 };
2769 
2770 static struct clk_branch gcc_wcss_ecahb_clk = {
2771 	.halt_reg = 0x25058,
2772 	.clkr = {
2773 		.enable_reg = 0x25058,
2774 		.enable_mask = BIT(0),
2775 		.hw.init = &(const struct clk_init_data) {
2776 			.name = "gcc_wcss_ecahb_clk",
2777 			.parent_hws = (const struct clk_hw *[]) {
2778 				&wcss_ahb_clk_src.clkr.hw
2779 			},
2780 			.num_parents = 1,
2781 			.flags = CLK_SET_RATE_PARENT,
2782 			.ops = &clk_branch2_ops,
2783 		},
2784 	},
2785 };
2786 
2787 static struct clk_branch gcc_wcss_acmt_clk = {
2788 	.halt_reg = 0x2505c,
2789 	.clkr = {
2790 		.enable_reg = 0x2505c,
2791 		.enable_mask = BIT(0),
2792 		.hw.init = &(const struct clk_init_data) {
2793 			.name = "gcc_wcss_acmt_clk",
2794 			.parent_hws = (const struct clk_hw *[]) {
2795 				&wcss_ahb_clk_src.clkr.hw
2796 			},
2797 			.num_parents = 1,
2798 			.flags = CLK_SET_RATE_PARENT,
2799 			.ops = &clk_branch2_ops,
2800 		},
2801 	},
2802 };
2803 
2804 static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
2805 	.halt_reg = 0x2e030,
2806 	.clkr = {
2807 		.enable_reg = 0x2e030,
2808 		.enable_mask = BIT(0),
2809 		.hw.init = &(const struct clk_init_data) {
2810 			.name = "gcc_sys_noc_wcss_ahb_clk",
2811 			.parent_hws = (const struct clk_hw *[]) {
2812 				&wcss_ahb_clk_src.clkr.hw
2813 			},
2814 			.num_parents = 1,
2815 			.flags = CLK_SET_RATE_PARENT,
2816 			.ops = &clk_branch2_ops,
2817 		},
2818 	},
2819 };
2820 
2821 static const struct freq_tbl ftbl_wcss_axi_m_clk_src[] = {
2822 	F(24000000, P_XO, 1, 0, 0),
2823 	F(133333333, P_GPLL0, 6, 0, 0),
2824 	F(266666667, P_GPLL0, 3, 0, 0),
2825 	{ }
2826 };
2827 
2828 static struct clk_rcg2 wcss_axi_m_clk_src = {
2829 	.cmd_rcgr = 0x25078,
2830 	.freq_tbl = ftbl_wcss_axi_m_clk_src,
2831 	.hid_width = 5,
2832 	.parent_map = gcc_xo_gpll0_map,
2833 	.clkr.hw.init = &(const struct clk_init_data) {
2834 		.name = "wcss_axi_m_clk_src",
2835 		.parent_data = gcc_xo_gpll0,
2836 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
2837 		.ops = &clk_rcg2_ops,
2838 	},
2839 };
2840 
2841 static struct clk_branch gcc_anoc_wcss_axi_m_clk = {
2842 	.halt_reg = 0x2e0a8,
2843 	.clkr = {
2844 		.enable_reg = 0x2e0a8,
2845 		.enable_mask = BIT(0),
2846 		.hw.init = &(const struct clk_init_data) {
2847 			.name = "gcc_anoc_wcss_axi_m_clk",
2848 			.parent_hws = (const struct clk_hw *[]) {
2849 				&wcss_axi_m_clk_src.clkr.hw
2850 			},
2851 			.num_parents = 1,
2852 			.flags = CLK_SET_RATE_PARENT,
2853 			.ops = &clk_branch2_ops,
2854 		},
2855 	},
2856 };
2857 
2858 static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
2859 	F(240000000, P_GPLL4, 5, 0, 0),
2860 	{ }
2861 };
2862 
2863 static struct clk_rcg2 qdss_at_clk_src = {
2864 	.cmd_rcgr = 0x2d004,
2865 	.freq_tbl = ftbl_qdss_at_clk_src,
2866 	.hid_width = 5,
2867 	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
2868 	.clkr.hw.init = &(const struct clk_init_data) {
2869 		.name = "qdss_at_clk_src",
2870 		.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
2871 		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
2872 		.ops = &clk_rcg2_ops,
2873 	},
2874 };
2875 
2876 static struct clk_branch gcc_q6ss_atbm_clk = {
2877 	.halt_reg = 0x2501c,
2878 	.clkr = {
2879 		.enable_reg = 0x2501c,
2880 		.enable_mask = BIT(0),
2881 		.hw.init = &(const struct clk_init_data) {
2882 			.name = "gcc_q6ss_atbm_clk",
2883 			.parent_hws = (const struct clk_hw *[]) {
2884 				&qdss_at_clk_src.clkr.hw
2885 			},
2886 			.num_parents = 1,
2887 			.flags = CLK_SET_RATE_PARENT,
2888 			.ops = &clk_branch2_ops,
2889 		},
2890 	},
2891 };
2892 
2893 static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {
2894 	.halt_reg = 0x2503c,
2895 	.clkr = {
2896 		.enable_reg = 0x2503c,
2897 		.enable_mask = BIT(0),
2898 		.hw.init = &(const struct clk_init_data) {
2899 			.name = "gcc_wcss_dbg_ifc_atb_clk",
2900 			.parent_hws = (const struct clk_hw *[]) {
2901 				&qdss_at_clk_src.clkr.hw
2902 			},
2903 			.num_parents = 1,
2904 			.flags = CLK_SET_RATE_PARENT,
2905 			.ops = &clk_branch2_ops,
2906 		},
2907 	},
2908 };
2909 
2910 static struct clk_branch gcc_nssnoc_atb_clk = {
2911 	.halt_reg = 0x17014,
2912 	.clkr = {
2913 		.enable_reg = 0x17014,
2914 		.enable_mask = BIT(0),
2915 		.hw.init = &(const struct clk_init_data) {
2916 			.name = "gcc_nssnoc_atb_clk",
2917 			.parent_hws = (const struct clk_hw *[]) {
2918 				&qdss_at_clk_src.clkr.hw
2919 			},
2920 			.num_parents = 1,
2921 			.flags = CLK_SET_RATE_PARENT,
2922 			.ops = &clk_branch2_ops,
2923 		},
2924 	},
2925 };
2926 
2927 static struct clk_branch gcc_qdss_at_clk = {
2928 	.halt_reg = 0x2d038,
2929 	.clkr = {
2930 		.enable_reg = 0x2d038,
2931 		.enable_mask = BIT(0),
2932 		.hw.init = &(const struct clk_init_data) {
2933 			.name = "gcc_qdss_at_clk",
2934 			.parent_hws = (const struct clk_hw *[]) {
2935 				&qdss_at_clk_src.clkr.hw
2936 			},
2937 			.num_parents = 1,
2938 			.flags = CLK_SET_RATE_PARENT,
2939 			.ops = &clk_branch2_ops,
2940 		},
2941 	},
2942 };
2943 
2944 static struct clk_branch gcc_sys_noc_at_clk = {
2945 	.halt_reg = 0x2e038,
2946 	.clkr = {
2947 		.enable_reg = 0x2e038,
2948 		.enable_mask = BIT(0),
2949 		.hw.init = &(const struct clk_init_data) {
2950 			.name = "gcc_sys_noc_at_clk",
2951 			.parent_hws = (const struct clk_hw *[]) {
2952 				&qdss_at_clk_src.clkr.hw
2953 			},
2954 			.num_parents = 1,
2955 			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2956 			.ops = &clk_branch2_ops,
2957 		},
2958 	},
2959 };
2960 
2961 static struct clk_branch gcc_pcnoc_at_clk = {
2962 	.halt_reg = 0x31024,
2963 	.clkr = {
2964 		.enable_reg = 0x31024,
2965 		.enable_mask = BIT(0),
2966 		.hw.init = &(const struct clk_init_data) {
2967 			.name = "gcc_pcnoc_at_clk",
2968 			.parent_hws = (const struct clk_hw *[]) {
2969 				&qdss_at_clk_src.clkr.hw
2970 			},
2971 			.num_parents = 1,
2972 			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2973 			.ops = &clk_branch2_ops,
2974 		},
2975 	},
2976 };
2977 
2978 static struct clk_fixed_factor gcc_eud_at_div_clk_src = {
2979 	.mult = 1,
2980 	.div = 6,
2981 	.hw.init = &(const struct clk_init_data) {
2982 		.name = "gcc_eud_at_div_clk_src",
2983 		.parent_hws = (const struct clk_hw *[]) {
2984 			&qdss_at_clk_src.clkr.hw
2985 		},
2986 		.num_parents = 1,
2987 		.flags = CLK_SET_RATE_PARENT,
2988 		.ops = &clk_fixed_factor_ops,
2989 	},
2990 };
2991 
2992 static struct clk_branch gcc_usb0_eud_at_clk = {
2993 	.halt_reg = 0x30004,
2994 	.clkr = {
2995 		.enable_reg = 0x30004,
2996 		.enable_mask = BIT(0),
2997 		.hw.init = &(const struct clk_init_data) {
2998 			.name = "gcc_usb0_eud_at_clk",
2999 			.parent_hws = (const struct clk_hw *[]) {
3000 				&gcc_eud_at_div_clk_src.hw
3001 			},
3002 			.num_parents = 1,
3003 			.flags = CLK_SET_RATE_PARENT,
3004 			.ops = &clk_branch2_ops,
3005 		},
3006 	},
3007 };
3008 
3009 static struct clk_branch gcc_qdss_eud_at_clk = {
3010 	.halt_reg = 0x2d06c,
3011 	.clkr = {
3012 		.enable_reg = 0x2d06c,
3013 		.enable_mask = BIT(0),
3014 		.hw.init = &(const struct clk_init_data) {
3015 			.name = "gcc_qdss_eud_at_clk",
3016 			.parent_hws = (const struct clk_hw *[]) {
3017 				&gcc_eud_at_div_clk_src.hw
3018 			},
3019 			.num_parents = 1,
3020 			.flags = CLK_SET_RATE_PARENT,
3021 			.ops = &clk_branch2_ops,
3022 		},
3023 	},
3024 };
3025 
3026 static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
3027 	F(24000000, P_XO, 1, 0, 0),
3028 	F(200000000, P_GPLL0, 4, 0, 0),
3029 	{ }
3030 };
3031 
3032 static struct clk_rcg2 qdss_stm_clk_src = {
3033 	.cmd_rcgr = 0x2d00c,
3034 	.freq_tbl = ftbl_qdss_stm_clk_src,
3035 	.hid_width = 5,
3036 	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
3037 	.clkr.hw.init = &(const struct clk_init_data) {
3038 		.name = "qdss_stm_clk_src",
3039 		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
3040 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
3041 		.ops = &clk_rcg2_ops,
3042 	},
3043 };
3044 
3045 static struct clk_branch gcc_qdss_stm_clk = {
3046 	.halt_reg = 0x2d03c,
3047 	.clkr = {
3048 		.enable_reg = 0x2d03c,
3049 		.enable_mask = BIT(0),
3050 		.hw.init = &(const struct clk_init_data) {
3051 			.name = "gcc_qdss_stm_clk",
3052 			.parent_hws = (const struct clk_hw *[]) {
3053 				&qdss_stm_clk_src.clkr.hw
3054 			},
3055 			.num_parents = 1,
3056 			.flags = CLK_SET_RATE_PARENT,
3057 			.ops = &clk_branch2_ops,
3058 		},
3059 	},
3060 };
3061 
3062 static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = {
3063 	.halt_reg = 0x2e034,
3064 	.clkr = {
3065 		.enable_reg = 0x2e034,
3066 		.enable_mask = BIT(0),
3067 		.hw.init = &(const struct clk_init_data) {
3068 			.name = "gcc_sys_noc_qdss_stm_axi_clk",
3069 			.parent_hws = (const struct clk_hw *[]) {
3070 				&qdss_stm_clk_src.clkr.hw
3071 			},
3072 			.num_parents = 1,
3073 			.flags = CLK_SET_RATE_PARENT,
3074 			.ops = &clk_branch2_ops,
3075 		},
3076 	},
3077 };
3078 
3079 static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
3080 	F(300000000, P_GPLL4, 4, 0, 0),
3081 	{ }
3082 };
3083 
3084 static struct clk_rcg2 qdss_traceclkin_clk_src = {
3085 	.cmd_rcgr = 0x2d014,
3086 	.freq_tbl = ftbl_qdss_traceclkin_clk_src,
3087 	.hid_width = 5,
3088 	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
3089 	.clkr.hw.init = &(const struct clk_init_data) {
3090 		.name = "qdss_traceclkin_clk_src",
3091 		.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
3092 		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
3093 		.ops = &clk_rcg2_ops,
3094 	},
3095 };
3096 
3097 static struct clk_branch gcc_qdss_traceclkin_clk = {
3098 	.halt_reg = 0x2d040,
3099 	.clkr = {
3100 		.enable_reg = 0x2d040,
3101 		.enable_mask = BIT(0),
3102 		.hw.init = &(const struct clk_init_data) {
3103 			.name = "gcc_qdss_traceclkin_clk",
3104 			.parent_hws = (const struct clk_hw *[]) {
3105 				&qdss_traceclkin_clk_src.clkr.hw
3106 			},
3107 			.num_parents = 1,
3108 			.flags = CLK_SET_RATE_PARENT,
3109 			.ops = &clk_branch2_ops,
3110 		},
3111 	},
3112 };
3113 
3114 static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
3115 	F(600000000, P_GPLL4, 2, 0, 0),
3116 	{ }
3117 };
3118 
3119 static struct clk_rcg2 qdss_tsctr_clk_src = {
3120 	.cmd_rcgr = 0x2d01c,
3121 	.freq_tbl = ftbl_qdss_tsctr_clk_src,
3122 	.hid_width = 5,
3123 	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
3124 	.clkr.hw.init = &(const struct clk_init_data) {
3125 		.name = "qdss_tsctr_clk_src",
3126 		.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
3127 		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
3128 		.ops = &clk_rcg2_ops,
3129 	},
3130 };
3131 
3132 static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
3133 	.mult = 1,
3134 	.div = 2,
3135 	.hw.init = &(const struct clk_init_data) {
3136 		.name = "qdss_tsctr_div2_clk_src",
3137 		.parent_hws = (const struct clk_hw *[]) {
3138 			&qdss_tsctr_clk_src.clkr.hw
3139 		},
3140 		.num_parents = 1,
3141 		.flags = CLK_SET_RATE_PARENT,
3142 		.ops = &clk_fixed_factor_ops,
3143 	},
3144 };
3145 
3146 static struct clk_branch gcc_q6_tsctr_1to2_clk = {
3147 	.halt_reg = 0x25020,
3148 	.clkr = {
3149 		.enable_reg = 0x25020,
3150 		.enable_mask = BIT(0),
3151 		.hw.init = &(const struct clk_init_data) {
3152 			.name = "gcc_q6_tsctr_1to2_clk",
3153 			.parent_hws = (const struct clk_hw *[]) {
3154 				&qdss_tsctr_div2_clk_src.hw
3155 			},
3156 			.num_parents = 1,
3157 			.flags = CLK_SET_RATE_PARENT,
3158 			.ops = &clk_branch2_ops,
3159 		},
3160 	},
3161 };
3162 
3163 static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {
3164 	.halt_reg = 0x25040,
3165 	.clkr = {
3166 		.enable_reg = 0x25040,
3167 		.enable_mask = BIT(0),
3168 		.hw.init = &(const struct clk_init_data) {
3169 			.name = "gcc_wcss_dbg_ifc_nts_clk",
3170 			.parent_hws = (const struct clk_hw *[]) {
3171 				&qdss_tsctr_div2_clk_src.hw
3172 			},
3173 			.num_parents = 1,
3174 			.flags = CLK_SET_RATE_PARENT,
3175 			.ops = &clk_branch2_ops,
3176 		},
3177 	},
3178 };
3179 
3180 static struct clk_branch gcc_qdss_tsctr_div2_clk = {
3181 	.halt_reg = 0x2d044,
3182 	.clkr = {
3183 		.enable_reg = 0x2d044,
3184 		.enable_mask = BIT(0),
3185 		.hw.init = &(const struct clk_init_data) {
3186 			.name = "gcc_qdss_tsctr_div2_clk",
3187 			.parent_hws = (const struct clk_hw *[]) {
3188 				&qdss_tsctr_div2_clk_src.hw
3189 			},
3190 			.num_parents = 1,
3191 			.flags = CLK_SET_RATE_PARENT,
3192 			.ops = &clk_branch2_ops,
3193 		},
3194 	},
3195 };
3196 
3197 static const struct freq_tbl ftbl_uniphy_sys_clk_src[] = {
3198 	F(24000000, P_XO, 1, 0, 0),
3199 	{ }
3200 };
3201 
3202 static struct clk_rcg2 uniphy_sys_clk_src = {
3203 	.cmd_rcgr = 0x17090,
3204 	.freq_tbl = ftbl_uniphy_sys_clk_src,
3205 	.mnd_width = 8,
3206 	.hid_width = 5,
3207 	.parent_map = gcc_xo_map,
3208 	.clkr.hw.init = &(const struct clk_init_data) {
3209 		.name = "uniphy_sys_clk_src",
3210 		.parent_data = gcc_xo_data,
3211 		.num_parents = ARRAY_SIZE(gcc_xo_data),
3212 		.ops = &clk_rcg2_ops,
3213 	},
3214 };
3215 
3216 static struct clk_rcg2 nss_ts_clk_src = {
3217 	.cmd_rcgr = 0x17088,
3218 	.freq_tbl = ftbl_uniphy_sys_clk_src,
3219 	.mnd_width = 8,
3220 	.hid_width = 5,
3221 	.parent_map = gcc_xo_map,
3222 	.clkr.hw.init = &(const struct clk_init_data) {
3223 		.name = "nss_ts_clk_src",
3224 		.parent_data = gcc_xo_data,
3225 		.num_parents = ARRAY_SIZE(gcc_xo_data),
3226 		.ops = &clk_rcg2_ops,
3227 	},
3228 };
3229 
3230 static struct clk_branch gcc_qdss_ts_clk = {
3231 	.halt_reg = 0x2d078,
3232 	.clkr = {
3233 		.enable_reg = 0x2d078,
3234 		.enable_mask = BIT(0),
3235 		.hw.init = &(const struct clk_init_data) {
3236 			.name = "gcc_qdss_ts_clk",
3237 			.parent_hws = (const struct clk_hw *[]) {
3238 				&nss_ts_clk_src.clkr.hw
3239 			},
3240 			.num_parents = 1,
3241 			.flags = CLK_SET_RATE_PARENT,
3242 			.ops = &clk_branch2_ops,
3243 		},
3244 	},
3245 };
3246 
3247 static struct clk_fixed_factor qdss_dap_sync_clk_src = {
3248 	.mult = 1,
3249 	.div = 4,
3250 	.hw.init = &(const struct clk_init_data) {
3251 		.name = "qdss_dap_sync_clk_src",
3252 		.parent_hws = (const struct clk_hw *[]) {
3253 			&qdss_tsctr_clk_src.clkr.hw
3254 		},
3255 		.num_parents = 1,
3256 		.ops = &clk_fixed_factor_ops,
3257 	},
3258 };
3259 
3260 static struct clk_branch gcc_qdss_tsctr_div4_clk = {
3261 	.halt_reg = 0x2d04c,
3262 	.clkr = {
3263 		.enable_reg = 0x2d04c,
3264 		.enable_mask = BIT(0),
3265 		.hw.init = &(const struct clk_init_data) {
3266 			.name = "gcc_qdss_tsctr_div4_clk",
3267 			.parent_hws = (const struct clk_hw *[]) {
3268 				&qdss_dap_sync_clk_src.hw
3269 			},
3270 			.num_parents = 1,
3271 			.flags = CLK_SET_RATE_PARENT,
3272 			.ops = &clk_branch2_ops,
3273 		},
3274 	},
3275 };
3276 
3277 static struct clk_fixed_factor qdss_tsctr_div8_clk_src = {
3278 	.mult = 1,
3279 	.div = 8,
3280 	.hw.init = &(const struct clk_init_data) {
3281 		.name = "qdss_tsctr_div8_clk_src",
3282 		.parent_hws = (const struct clk_hw *[]) {
3283 			&qdss_tsctr_clk_src.clkr.hw
3284 		},
3285 		.num_parents = 1,
3286 		.ops = &clk_fixed_factor_ops,
3287 	},
3288 };
3289 
3290 static struct clk_branch gcc_nss_ts_clk = {
3291 	.halt_reg = 0x17018,
3292 	.clkr = {
3293 		.enable_reg = 0x17018,
3294 		.enable_mask = BIT(0),
3295 		.hw.init = &(const struct clk_init_data) {
3296 			.name = "gcc_nss_ts_clk",
3297 			.parent_hws = (const struct clk_hw *[]) {
3298 				&nss_ts_clk_src.clkr.hw
3299 			},
3300 			.num_parents = 1,
3301 			.flags = CLK_SET_RATE_PARENT,
3302 			.ops = &clk_branch2_ops,
3303 		},
3304 	},
3305 };
3306 
3307 static struct clk_branch gcc_qdss_tsctr_div8_clk = {
3308 	.halt_reg = 0x2d050,
3309 	.clkr = {
3310 		.enable_reg = 0x2d050,
3311 		.enable_mask = BIT(0),
3312 		.hw.init = &(const struct clk_init_data) {
3313 			.name = "gcc_qdss_tsctr_div8_clk",
3314 			.parent_hws = (const struct clk_hw *[]) {
3315 				&qdss_tsctr_div8_clk_src.hw
3316 			},
3317 			.num_parents = 1,
3318 			.flags = CLK_SET_RATE_PARENT,
3319 			.ops = &clk_branch2_ops,
3320 		},
3321 	},
3322 };
3323 
3324 static struct clk_fixed_factor qdss_tsctr_div16_clk_src = {
3325 	.mult = 1,
3326 	.div = 16,
3327 	.hw.init = &(const struct clk_init_data) {
3328 		.name = "qdss_tsctr_div16_clk_src",
3329 		.parent_hws = (const struct clk_hw *[]) {
3330 			&qdss_tsctr_clk_src.clkr.hw
3331 		},
3332 		.num_parents = 1,
3333 		.ops = &clk_fixed_factor_ops,
3334 	},
3335 };
3336 
3337 static struct clk_branch gcc_qdss_tsctr_div16_clk = {
3338 	.halt_reg = 0x2d054,
3339 	.clkr = {
3340 		.enable_reg = 0x2d054,
3341 		.enable_mask = BIT(0),
3342 		.hw.init = &(const struct clk_init_data) {
3343 			.name = "gcc_qdss_tsctr_div16_clk",
3344 			.parent_hws = (const struct clk_hw *[]) {
3345 				&qdss_tsctr_div16_clk_src.hw
3346 			},
3347 			.num_parents = 1,
3348 			.flags = CLK_SET_RATE_PARENT,
3349 			.ops = &clk_branch2_ops,
3350 		},
3351 	},
3352 };
3353 
3354 static struct clk_branch gcc_q6ss_pclkdbg_clk = {
3355 	.halt_reg = 0x25024,
3356 	.clkr = {
3357 		.enable_reg = 0x25024,
3358 		.enable_mask = BIT(0),
3359 		.hw.init = &(const struct clk_init_data) {
3360 			.name = "gcc_q6ss_pclkdbg_clk",
3361 			.parent_hws = (const struct clk_hw *[]) {
3362 				&qdss_dap_sync_clk_src.hw
3363 			},
3364 			.num_parents = 1,
3365 			.flags = CLK_SET_RATE_PARENT,
3366 			.ops = &clk_branch2_ops,
3367 		},
3368 	},
3369 };
3370 
3371 static struct clk_branch gcc_q6ss_trig_clk = {
3372 	.halt_reg = 0x25068,
3373 	.clkr = {
3374 		.enable_reg = 0x25068,
3375 		.enable_mask = BIT(0),
3376 		.hw.init = &(const struct clk_init_data) {
3377 			.name = "gcc_q6ss_trig_clk",
3378 			.parent_hws = (const struct clk_hw *[]) {
3379 				&qdss_dap_sync_clk_src.hw
3380 			},
3381 			.num_parents = 1,
3382 			.flags = CLK_SET_RATE_PARENT,
3383 			.ops = &clk_branch2_ops,
3384 		},
3385 	},
3386 };
3387 
3388 static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {
3389 	.halt_reg = 0x25038,
3390 	.clkr = {
3391 		.enable_reg = 0x25038,
3392 		.enable_mask = BIT(0),
3393 		.hw.init = &(const struct clk_init_data) {
3394 			.name = "gcc_wcss_dbg_ifc_apb_clk",
3395 			.parent_hws = (const struct clk_hw *[]) {
3396 				&qdss_dap_sync_clk_src.hw
3397 			},
3398 			.num_parents = 1,
3399 			.flags = CLK_SET_RATE_PARENT,
3400 			.ops = &clk_branch2_ops,
3401 		},
3402 	},
3403 };
3404 
3405 static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = {
3406 	.halt_reg = 0x25044,
3407 	.clkr = {
3408 		.enable_reg = 0x25044,
3409 		.enable_mask = BIT(0),
3410 		.hw.init = &(const struct clk_init_data) {
3411 			.name = "gcc_wcss_dbg_ifc_dapbus_clk",
3412 			.parent_hws = (const struct clk_hw *[]) {
3413 				&qdss_dap_sync_clk_src.hw
3414 			},
3415 			.num_parents = 1,
3416 			.flags = CLK_SET_RATE_PARENT,
3417 			.ops = &clk_branch2_ops,
3418 		},
3419 	},
3420 };
3421 
3422 static struct clk_branch gcc_qdss_dap_clk = {
3423 	.halt_reg = 0x2d058,
3424 	.clkr = {
3425 		.enable_reg = 0x2d058,
3426 		.enable_mask = BIT(0),
3427 		.hw.init = &(const struct clk_init_data) {
3428 			.name = "gcc_qdss_dap_clk",
3429 			.parent_hws = (const struct clk_hw *[]) {
3430 				&qdss_dap_sync_clk_src.hw
3431 			},
3432 			.num_parents = 1,
3433 			.flags = CLK_SET_RATE_PARENT,
3434 			.ops = &clk_branch2_ops,
3435 		},
3436 	},
3437 };
3438 
3439 static struct clk_branch gcc_qdss_apb2jtag_clk = {
3440 	.halt_reg = 0x2d05c,
3441 	.clkr = {
3442 		.enable_reg = 0x2d05c,
3443 		.enable_mask = BIT(0),
3444 		.hw.init = &(const struct clk_init_data) {
3445 			.name = "gcc_qdss_apb2jtag_clk",
3446 			.parent_hws = (const struct clk_hw *[]) {
3447 				&qdss_dap_sync_clk_src.hw
3448 			},
3449 			.num_parents = 1,
3450 			.flags = CLK_SET_RATE_PARENT,
3451 			.ops = &clk_branch2_ops,
3452 		},
3453 	},
3454 };
3455 
3456 static struct clk_fixed_factor qdss_tsctr_div3_clk_src = {
3457 	.mult = 1,
3458 	.div = 3,
3459 	.hw.init = &(const struct clk_init_data) {
3460 		.name = "qdss_tsctr_div3_clk_src",
3461 		.parent_hws = (const struct clk_hw *[]) {
3462 			&qdss_tsctr_clk_src.clkr.hw
3463 		},
3464 		.num_parents = 1,
3465 		.ops = &clk_fixed_factor_ops,
3466 	},
3467 };
3468 
3469 static struct clk_branch gcc_qdss_tsctr_div3_clk = {
3470 	.halt_reg = 0x2d048,
3471 	.clkr = {
3472 		.enable_reg = 0x2d048,
3473 		.enable_mask = BIT(0),
3474 		.hw.init = &(const struct clk_init_data) {
3475 			.name = "gcc_qdss_tsctr_div3_clk",
3476 			.parent_hws = (const struct clk_hw *[]) {
3477 				&qdss_tsctr_div3_clk_src.hw
3478 			},
3479 			.num_parents = 1,
3480 			.flags = CLK_SET_RATE_PARENT,
3481 			.ops = &clk_branch2_ops,
3482 		},
3483 	},
3484 };
3485 
3486 static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = {
3487 	F(24000000, P_XO, 1, 0, 0),
3488 	F(100000000, P_GPLL0, 8, 0, 0),
3489 	F(200000000, P_GPLL0, 4, 0, 0),
3490 	F(320000000, P_GPLL0, 2.5, 0, 0),
3491 	F(400000000, P_GPLL0, 2, 0, 0),
3492 	{ }
3493 };
3494 
3495 static struct clk_rcg2 qpic_io_macro_clk_src = {
3496 	.cmd_rcgr = 0x32004,
3497 	.freq_tbl = ftbl_qpic_io_macro_clk_src,
3498 	.hid_width = 5,
3499 	.parent_map = gcc_xo_gpll0_gpll2_map,
3500 	.clkr.hw.init = &(const struct clk_init_data) {
3501 		.name = "qpic_io_macro_clk_src",
3502 		.parent_data = gcc_xo_gpll0_gpll2,
3503 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
3504 		.ops = &clk_rcg2_ops,
3505 	},
3506 };
3507 
3508 static struct clk_branch gcc_qpic_io_macro_clk = {
3509 	.halt_reg = 0x3200c,
3510 	.clkr = {
3511 		.enable_reg = 0x3200c,
3512 		.enable_mask = BIT(0),
3513 		.hw.init = &(const struct clk_init_data){
3514 			.name = "gcc_qpic_io_macro_clk",
3515 			.parent_hws = (const struct clk_hw *[]){
3516 				&qpic_io_macro_clk_src.clkr.hw
3517 			},
3518 			.num_parents = 1,
3519 			.flags = CLK_SET_RATE_PARENT,
3520 			.ops = &clk_branch2_ops,
3521 		},
3522 	},
3523 };
3524 
3525 static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
3526 	F(533333333, P_GPLL0, 1.5, 0, 0),
3527 	{ }
3528 };
3529 
3530 static struct clk_rcg2 q6_axi_clk_src = {
3531 	.cmd_rcgr = 0x25004,
3532 	.freq_tbl = ftbl_q6_axi_clk_src,
3533 	.hid_width = 5,
3534 	.parent_map = gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map,
3535 	.clkr.hw.init = &(const struct clk_init_data) {
3536 		.name = "q6_axi_clk_src",
3537 		.parent_data = gcc_xo_gpll0_gpll2_gpll4_pi_sleep,
3538 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_pi_sleep),
3539 		.ops = &clk_rcg2_ops,
3540 	},
3541 };
3542 
3543 static struct clk_branch gcc_q6_axim_clk = {
3544 	.halt_reg = 0x2500c,
3545 	.clkr = {
3546 		.enable_reg = 0x2500c,
3547 		.enable_mask = BIT(0),
3548 		.hw.init = &(const struct clk_init_data) {
3549 			.name = "gcc_q6_axim_clk",
3550 			.parent_hws = (const struct clk_hw *[]) {
3551 				&q6_axi_clk_src.clkr.hw
3552 			},
3553 			.num_parents = 1,
3554 			.flags = CLK_SET_RATE_PARENT,
3555 			.ops = &clk_branch2_ops,
3556 		},
3557 	},
3558 };
3559 
3560 static struct clk_branch gcc_wcss_q6_tbu_clk = {
3561 	.halt_reg = 0x12050,
3562 	.halt_check = BRANCH_HALT_DELAY,
3563 	.clkr = {
3564 		.enable_reg = 0xb00c,
3565 		.enable_mask = BIT(6),
3566 		.hw.init = &(const struct clk_init_data) {
3567 			.name = "gcc_wcss_q6_tbu_clk",
3568 			.parent_hws = (const struct clk_hw *[]) {
3569 				&q6_axi_clk_src.clkr.hw
3570 			},
3571 			.num_parents = 1,
3572 			.flags = CLK_SET_RATE_PARENT,
3573 			.ops = &clk_branch2_ops,
3574 		},
3575 	},
3576 };
3577 
3578 static struct clk_branch gcc_mem_noc_q6_axi_clk = {
3579 	.halt_reg = 0x19010,
3580 	.clkr = {
3581 		.enable_reg = 0x19010,
3582 		.enable_mask = BIT(0),
3583 		.hw.init = &(const struct clk_init_data) {
3584 			.name = "gcc_mem_noc_q6_axi_clk",
3585 			.parent_hws = (const struct clk_hw *[]) {
3586 				&q6_axi_clk_src.clkr.hw
3587 			},
3588 			.num_parents = 1,
3589 			.flags = CLK_SET_RATE_PARENT,
3590 			.ops = &clk_branch2_ops,
3591 		},
3592 	},
3593 };
3594 
3595 static const struct freq_tbl ftbl_q6_axim2_clk_src[] = {
3596 	F(342857143, P_GPLL4, 3.5, 0, 0),
3597 	{ }
3598 };
3599 
3600 static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map[] = {
3601 	{ P_XO, 0 },
3602 	{ P_GPLL0, 1 },
3603 	{ P_GPLL4, 2 },
3604 	{ P_BIAS_PLL_UBI_NC_CLK, 4 },
3605 };
3606 
3607 static struct clk_rcg2 q6_axim2_clk_src = {
3608 	.cmd_rcgr = 0x25028,
3609 	.freq_tbl = ftbl_q6_axim2_clk_src,
3610 	.hid_width = 5,
3611 	.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map,
3612 	.clkr.hw.init = &(const struct clk_init_data) {
3613 		.name = "q6_axim2_clk_src",
3614 		.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
3615 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
3616 		.ops = &clk_rcg2_ops,
3617 	},
3618 };
3619 
3620 static const struct freq_tbl ftbl_nssnoc_memnoc_bfdcd_clk_src[] = {
3621 	F(533333333, P_GPLL0, 1.5, 0, 0),
3622 	{ }
3623 };
3624 
3625 static struct clk_rcg2 nssnoc_memnoc_bfdcd_clk_src = {
3626 	.cmd_rcgr = 0x17004,
3627 	.freq_tbl = ftbl_nssnoc_memnoc_bfdcd_clk_src,
3628 	.hid_width = 5,
3629 	.parent_map = gcc_xo_gpll0_gpll0_aux_gpll2_map,
3630 	.clkr.hw.init = &(const struct clk_init_data) {
3631 		.name = "nssnoc_memnoc_bfdcd_clk_src",
3632 		.parent_data = gcc_xo_gpll0_gpll0_aux_gpll2,
3633 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_gpll2),
3634 		.ops = &clk_rcg2_ops,
3635 	},
3636 };
3637 
3638 static struct clk_branch gcc_nssnoc_memnoc_clk = {
3639 	.halt_reg = 0x17024,
3640 	.clkr = {
3641 		.enable_reg = 0x17024,
3642 		.enable_mask = BIT(0),
3643 		.hw.init = &(const struct clk_init_data) {
3644 			.name = "gcc_nssnoc_memnoc_clk",
3645 			.parent_hws = (const struct clk_hw *[]) {
3646 				&nssnoc_memnoc_bfdcd_clk_src.clkr.hw
3647 			},
3648 			.num_parents = 1,
3649 			.flags = CLK_SET_RATE_PARENT,
3650 			.ops = &clk_branch2_ops,
3651 		},
3652 	},
3653 };
3654 
3655 static struct clk_branch gcc_nssnoc_mem_noc_1_clk = {
3656 	.halt_reg = 0x17084,
3657 	.clkr = {
3658 		.enable_reg = 0x17084,
3659 		.enable_mask = BIT(0),
3660 		.hw.init = &(const struct clk_init_data) {
3661 			.name = "gcc_nssnoc_mem_noc_1_clk",
3662 			.parent_hws = (const struct clk_hw *[]) {
3663 				&nssnoc_memnoc_bfdcd_clk_src.clkr.hw
3664 			},
3665 			.num_parents = 1,
3666 			.flags = CLK_SET_RATE_PARENT,
3667 			.ops = &clk_branch2_ops,
3668 		},
3669 	},
3670 };
3671 
3672 static struct clk_branch gcc_nss_tbu_clk = {
3673 	.halt_reg = 0x12040,
3674 	.clkr = {
3675 		.enable_reg = 0xb00c,
3676 		.enable_mask = BIT(4),
3677 		.hw.init = &(const struct clk_init_data) {
3678 			.name = "gcc_nss_tbu_clk",
3679 			.parent_hws = (const struct clk_hw *[]) {
3680 				&nssnoc_memnoc_bfdcd_clk_src.clkr.hw
3681 			},
3682 			.num_parents = 1,
3683 			.flags = CLK_SET_RATE_PARENT,
3684 			.ops = &clk_branch2_ops,
3685 		},
3686 	},
3687 };
3688 
3689 static struct clk_branch gcc_mem_noc_nssnoc_clk = {
3690 	.halt_reg = 0x19014,
3691 	.clkr = {
3692 		.enable_reg = 0x19014,
3693 		.enable_mask = BIT(0),
3694 		.hw.init = &(const struct clk_init_data) {
3695 			.name = "gcc_mem_noc_nssnoc_clk",
3696 			.parent_hws = (const struct clk_hw *[]) {
3697 				&nssnoc_memnoc_bfdcd_clk_src.clkr.hw
3698 			},
3699 			.num_parents = 1,
3700 			.flags = CLK_SET_RATE_PARENT,
3701 			.ops = &clk_branch2_ops,
3702 		},
3703 	},
3704 };
3705 
3706 static const struct freq_tbl ftbl_lpass_axim_clk_src[] = {
3707 	F(133333333, P_GPLL0, 6, 0, 0),
3708 	{ }
3709 };
3710 
3711 static struct clk_rcg2 lpass_axim_clk_src = {
3712 	.cmd_rcgr = 0x2700c,
3713 	.freq_tbl = ftbl_lpass_axim_clk_src,
3714 	.hid_width = 5,
3715 	.parent_map = gcc_xo_gpll0_map,
3716 	.clkr.hw.init = &(const struct clk_init_data) {
3717 		.name = "lpass_axim_clk_src",
3718 		.parent_data = gcc_xo_gpll0,
3719 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
3720 		.ops = &clk_rcg2_ops,
3721 	},
3722 };
3723 
3724 static struct clk_rcg2 lpass_sway_clk_src = {
3725 	.cmd_rcgr = 0x27004,
3726 	.freq_tbl = ftbl_lpass_axim_clk_src,
3727 	.hid_width = 5,
3728 	.parent_map = gcc_xo_gpll0_map,
3729 	.clkr.hw.init = &(const struct clk_init_data) {
3730 		.name = "lpass_sway_clk_src",
3731 		.parent_data = gcc_xo_gpll0,
3732 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
3733 		.ops = &clk_rcg2_ops,
3734 	},
3735 };
3736 
3737 static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
3738 	F(24000000, P_XO, 1, 0, 0),
3739 	F(100000000, P_GPLL0, 8, 0, 0),
3740 	{ }
3741 };
3742 
3743 static struct clk_rcg2 adss_pwm_clk_src = {
3744 	.cmd_rcgr = 0x1c004,
3745 	.freq_tbl = ftbl_adss_pwm_clk_src,
3746 	.hid_width = 5,
3747 	.parent_map = gcc_xo_gpll0_map,
3748 	.clkr.hw.init = &(const struct clk_init_data) {
3749 		.name = "adss_pwm_clk_src",
3750 		.parent_data = gcc_xo_gpll0,
3751 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
3752 		.ops = &clk_rcg2_ops,
3753 	},
3754 };
3755 
3756 static struct clk_branch gcc_adss_pwm_clk = {
3757 	.halt_reg = 0x1c00c,
3758 	.clkr = {
3759 		.enable_reg = 0x1c00c,
3760 		.enable_mask = BIT(0),
3761 		.hw.init = &(const struct clk_init_data) {
3762 			.name = "gcc_adss_pwm_clk",
3763 			.parent_hws = (const struct clk_hw *[]) {
3764 				&adss_pwm_clk_src.clkr.hw
3765 			},
3766 			.num_parents = 1,
3767 			.flags = CLK_SET_RATE_PARENT,
3768 			.ops = &clk_branch2_ops,
3769 		},
3770 	},
3771 };
3772 
3773 static const struct freq_tbl ftbl_gp1_clk_src[] = {
3774 	F(24000000, P_XO, 1, 0, 0),
3775 	F(200000000, P_GPLL0, 4, 0, 0),
3776 	{ }
3777 };
3778 
3779 static struct clk_rcg2 gp1_clk_src = {
3780 	.cmd_rcgr = 0x8004,
3781 	.freq_tbl = ftbl_gp1_clk_src,
3782 	.hid_width = 5,
3783 	.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
3784 	.clkr.hw.init = &(const struct clk_init_data) {
3785 		.name = "gp1_clk_src",
3786 		.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
3787 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
3788 		.ops = &clk_rcg2_ops,
3789 	},
3790 };
3791 
3792 static struct clk_rcg2 gp2_clk_src = {
3793 	.cmd_rcgr = 0x9004,
3794 	.freq_tbl = ftbl_gp1_clk_src,
3795 	.hid_width = 5,
3796 	.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
3797 	.clkr.hw.init = &(const struct clk_init_data) {
3798 		.name = "gp2_clk_src",
3799 		.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
3800 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
3801 		.ops = &clk_rcg2_ops,
3802 	},
3803 };
3804 
3805 static struct clk_rcg2 gp3_clk_src = {
3806 	.cmd_rcgr = 0xa004,
3807 	.freq_tbl = ftbl_gp1_clk_src,
3808 	.hid_width = 5,
3809 	.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
3810 	.clkr.hw.init = &(const struct clk_init_data) {
3811 		.name = "gp3_clk_src",
3812 		.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
3813 		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
3814 		.ops = &clk_rcg2_ops,
3815 	},
3816 };
3817 
3818 static struct clk_branch gcc_xo_clk_src = {
3819 	.halt_reg = 0x34004,
3820 	.clkr = {
3821 		.enable_reg = 0x34004,
3822 		.enable_mask = BIT(1),
3823 		.hw.init = &(const struct clk_init_data) {
3824 			.name = "gcc_xo_clk_src",
3825 			.parent_data = gcc_xo_data,
3826 			.num_parents = ARRAY_SIZE(gcc_xo_data),
3827 			.flags = CLK_SET_RATE_PARENT,
3828 			.ops = &clk_branch2_ops,
3829 		},
3830 	},
3831 };
3832 
3833 static struct clk_branch gcc_nssnoc_xo_dcd_clk = {
3834 	.halt_reg = 0x17074,
3835 	.clkr = {
3836 		.enable_reg = 0x17074,
3837 		.enable_mask = BIT(0),
3838 		.hw.init = &(const struct clk_init_data) {
3839 			.name = "gcc_nssnoc_xo_dcd_clk",
3840 			.parent_hws = (const struct clk_hw *[]) {
3841 				&gcc_xo_clk_src.clkr.hw
3842 			},
3843 			.num_parents = 1,
3844 			.flags = CLK_SET_RATE_PARENT,
3845 			.ops = &clk_branch2_ops,
3846 		},
3847 	},
3848 };
3849 
3850 static struct clk_branch gcc_xo_clk = {
3851 	.halt_reg = 0x34018,
3852 	.clkr = {
3853 		.enable_reg = 0x34018,
3854 		.enable_mask = BIT(0),
3855 		.hw.init = &(const struct clk_init_data) {
3856 			.name = "gcc_xo_clk",
3857 			.parent_hws = (const struct clk_hw *[]) {
3858 				&gcc_xo_clk_src.clkr.hw
3859 			},
3860 			.num_parents = 1,
3861 			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
3862 			.ops = &clk_branch2_ops,
3863 		},
3864 	},
3865 };
3866 
3867 static struct clk_branch gcc_uniphy0_sys_clk = {
3868 	.halt_reg = 0x17048,
3869 	.clkr = {
3870 		.enable_reg = 0x17048,
3871 		.enable_mask = BIT(0),
3872 		.hw.init = &(const struct clk_init_data) {
3873 			.name = "gcc_uniphy0_sys_clk",
3874 			.parent_hws = (const struct clk_hw *[]) {
3875 				&uniphy_sys_clk_src.clkr.hw
3876 			},
3877 			.num_parents = 1,
3878 			.flags = CLK_SET_RATE_PARENT,
3879 			.ops = &clk_branch2_ops,
3880 		},
3881 	},
3882 };
3883 
3884 static struct clk_branch gcc_uniphy1_sys_clk = {
3885 	.halt_reg = 0x17058,
3886 	.clkr = {
3887 		.enable_reg = 0x17058,
3888 		.enable_mask = BIT(0),
3889 		.hw.init = &(const struct clk_init_data) {
3890 			.name = "gcc_uniphy1_sys_clk",
3891 			.parent_hws = (const struct clk_hw *[]) {
3892 				&uniphy_sys_clk_src.clkr.hw
3893 			},
3894 			.num_parents = 1,
3895 			.flags = CLK_SET_RATE_PARENT,
3896 			.ops = &clk_branch2_ops,
3897 		},
3898 	},
3899 };
3900 
3901 static struct clk_branch gcc_uniphy2_sys_clk = {
3902 	.halt_reg = 0x17068,
3903 	.clkr = {
3904 		.enable_reg = 0x17068,
3905 		.enable_mask = BIT(0),
3906 		.hw.init = &(const struct clk_init_data) {
3907 			.name = "gcc_uniphy2_sys_clk",
3908 			.parent_hws = (const struct clk_hw *[]) {
3909 				&uniphy_sys_clk_src.clkr.hw
3910 			},
3911 			.num_parents = 1,
3912 			.flags = CLK_SET_RATE_PARENT,
3913 			.ops = &clk_branch2_ops,
3914 		},
3915 	},
3916 };
3917 
3918 static struct clk_branch gcc_cmn_12gpll_sys_clk = {
3919 	.halt_reg = 0x3a008,
3920 	.clkr = {
3921 		.enable_reg = 0x3a008,
3922 		.enable_mask = BIT(0),
3923 		.hw.init = &(const struct clk_init_data) {
3924 			.name = "gcc_cmn_12gpll_sys_clk",
3925 			.parent_hws = (const struct clk_hw *[]) {
3926 				&uniphy_sys_clk_src.clkr.hw
3927 			},
3928 			.num_parents = 1,
3929 			.flags = CLK_SET_RATE_PARENT,
3930 			.ops = &clk_branch2_ops,
3931 		},
3932 	},
3933 };
3934 
3935 static struct clk_fixed_factor gcc_xo_div4_clk_src = {
3936 	.mult = 1,
3937 	.div = 4,
3938 	.hw.init = &(const struct clk_init_data) {
3939 		.name = "gcc_xo_div4_clk_src",
3940 		.parent_hws = (const struct clk_hw *[]) {
3941 			&gcc_xo_clk_src.clkr.hw
3942 		},
3943 		.num_parents = 1,
3944 		.flags = CLK_SET_RATE_PARENT,
3945 		.ops = &clk_fixed_factor_ops,
3946 	},
3947 };
3948 
3949 static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
3950 	.halt_reg = 0x1701c,
3951 	.clkr = {
3952 		.enable_reg = 0x1701c,
3953 		.enable_mask = BIT(0),
3954 		.hw.init = &(const struct clk_init_data) {
3955 			.name = "gcc_nssnoc_qosgen_ref_clk",
3956 			.parent_hws = (const struct clk_hw *[]) {
3957 				&gcc_xo_div4_clk_src.hw
3958 			},
3959 			.num_parents = 1,
3960 			.flags = CLK_SET_RATE_PARENT,
3961 			.ops = &clk_branch2_ops,
3962 		},
3963 	},
3964 };
3965 
3966 static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
3967 	.halt_reg = 0x17020,
3968 	.clkr = {
3969 		.enable_reg = 0x17020,
3970 		.enable_mask = BIT(0),
3971 		.hw.init = &(const struct clk_init_data) {
3972 			.name = "gcc_nssnoc_timeout_ref_clk",
3973 			.parent_hws = (const struct clk_hw *[]) {
3974 				&gcc_xo_div4_clk_src.hw
3975 			},
3976 			.num_parents = 1,
3977 			.flags = CLK_SET_RATE_PARENT,
3978 			.ops = &clk_branch2_ops,
3979 		},
3980 	},
3981 };
3982 
3983 static struct clk_branch gcc_xo_div4_clk = {
3984 	.halt_reg = 0x3401c,
3985 	.clkr = {
3986 		.enable_reg = 0x3401c,
3987 		.enable_mask = BIT(0),
3988 		.hw.init = &(const struct clk_init_data) {
3989 			.name = "gcc_xo_div4_clk",
3990 			.parent_hws = (const struct clk_hw *[]) {
3991 				&gcc_xo_div4_clk_src.hw
3992 			},
3993 			.num_parents = 1,
3994 			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
3995 			.ops = &clk_branch2_ops,
3996 		},
3997 	},
3998 };
3999 
4000 static struct clk_hw *gcc_ipq9574_hws[] = {
4001 	&gpll0_out_main_div2.hw,
4002 	&gcc_xo_div4_clk_src.hw,
4003 	&qdss_dap_sync_clk_src.hw,
4004 	&qdss_tsctr_div2_clk_src.hw,
4005 	&qdss_tsctr_div8_clk_src.hw,
4006 	&qdss_tsctr_div16_clk_src.hw,
4007 	&qdss_tsctr_div3_clk_src.hw,
4008 	&gcc_eud_at_div_clk_src.hw,
4009 };
4010 
4011 static struct clk_regmap *gcc_ipq9574_clks[] = {
4012 	[GPLL0_MAIN] = &gpll0_main.clkr,
4013 	[GPLL0] = &gpll0.clkr,
4014 	[GPLL4_MAIN] = &gpll4_main.clkr,
4015 	[GPLL4] = &gpll4.clkr,
4016 	[GPLL2_MAIN] = &gpll2_main.clkr,
4017 	[GPLL2] = &gpll2.clkr,
4018 	[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
4019 	[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
4020 	[APSS_AXI_CLK_SRC] = &apss_axi_clk_src.clkr,
4021 	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
4022 	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
4023 	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
4024 	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
4025 	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
4026 	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
4027 	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
4028 	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
4029 	[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
4030 	[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
4031 	[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
4032 	[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
4033 	[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
4034 	[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
4035 	[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
4036 	[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
4037 	[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
4038 	[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
4039 	[GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
4040 	[GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
4041 	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
4042 	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
4043 	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
4044 	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
4045 	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
4046 	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
4047 	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
4048 	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
4049 	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
4050 	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
4051 	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
4052 	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
4053 	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
4054 	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
4055 	[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
4056 	[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
4057 	[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
4058 	[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
4059 	[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
4060 	[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
4061 	[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
4062 	[GCC_CRYPTO_CLK_SRC] = &gcc_crypto_clk_src.clkr,
4063 	[PCIE0_AXI_M_CLK_SRC] = &pcie0_axi_m_clk_src.clkr,
4064 	[GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
4065 	[PCIE1_AXI_M_CLK_SRC] = &pcie1_axi_m_clk_src.clkr,
4066 	[GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
4067 	[PCIE2_AXI_M_CLK_SRC] = &pcie2_axi_m_clk_src.clkr,
4068 	[GCC_PCIE2_AXI_M_CLK] = &gcc_pcie2_axi_m_clk.clkr,
4069 	[PCIE3_AXI_M_CLK_SRC] = &pcie3_axi_m_clk_src.clkr,
4070 	[GCC_PCIE3_AXI_M_CLK] = &gcc_pcie3_axi_m_clk.clkr,
4071 	[PCIE0_AXI_S_CLK_SRC] = &pcie0_axi_s_clk_src.clkr,
4072 	[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
4073 	[GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
4074 	[PCIE1_AXI_S_CLK_SRC] = &pcie1_axi_s_clk_src.clkr,
4075 	[GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,
4076 	[GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
4077 	[PCIE2_AXI_S_CLK_SRC] = &pcie2_axi_s_clk_src.clkr,
4078 	[GCC_PCIE2_AXI_S_BRIDGE_CLK] = &gcc_pcie2_axi_s_bridge_clk.clkr,
4079 	[GCC_PCIE2_AXI_S_CLK] = &gcc_pcie2_axi_s_clk.clkr,
4080 	[PCIE3_AXI_S_CLK_SRC] = &pcie3_axi_s_clk_src.clkr,
4081 	[GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr,
4082 	[GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr,
4083 	[PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
4084 	[PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
4085 	[PCIE2_PIPE_CLK_SRC] = &pcie2_pipe_clk_src.clkr,
4086 	[PCIE3_PIPE_CLK_SRC] = &pcie3_pipe_clk_src.clkr,
4087 	[PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
4088 	[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
4089 	[GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
4090 	[GCC_PCIE2_AUX_CLK] = &gcc_pcie2_aux_clk.clkr,
4091 	[GCC_PCIE3_AUX_CLK] = &gcc_pcie3_aux_clk.clkr,
4092 	[PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
4093 	[GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
4094 	[PCIE1_RCHNG_CLK_SRC] = &pcie1_rchng_clk_src.clkr,
4095 	[GCC_PCIE1_RCHNG_CLK] = &gcc_pcie1_rchng_clk.clkr,
4096 	[PCIE2_RCHNG_CLK_SRC] = &pcie2_rchng_clk_src.clkr,
4097 	[GCC_PCIE2_RCHNG_CLK] = &gcc_pcie2_rchng_clk.clkr,
4098 	[PCIE3_RCHNG_CLK_SRC] = &pcie3_rchng_clk_src.clkr,
4099 	[GCC_PCIE3_RCHNG_CLK] = &gcc_pcie3_rchng_clk.clkr,
4100 	[GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
4101 	[GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
4102 	[GCC_PCIE2_AHB_CLK] = &gcc_pcie2_ahb_clk.clkr,
4103 	[GCC_PCIE3_AHB_CLK] = &gcc_pcie3_ahb_clk.clkr,
4104 	[USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
4105 	[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
4106 	[USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
4107 	[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
4108 	[GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr,
4109 	[GCC_ANOC_USB_AXI_CLK] = &gcc_anoc_usb_axi_clk.clkr,
4110 	[USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
4111 	[USB0_MOCK_UTMI_DIV_CLK_SRC] = &usb0_mock_utmi_div_clk_src.clkr,
4112 	[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
4113 	[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
4114 	[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
4115 	[GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
4116 	[GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
4117 	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
4118 	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
4119 	[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
4120 	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
4121 	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
4122 	[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
4123 	[GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,
4124 	[GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,
4125 	[GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
4126 	[GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
4127 	[GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
4128 	[GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
4129 	[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
4130 	[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
4131 	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
4132 	[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
4133 	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
4134 	[GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
4135 	[GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
4136 	[GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
4137 	[GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
4138 	[GCC_CMN_12GPLL_APU_CLK] = &gcc_cmn_12gpll_apu_clk.clkr,
4139 	[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
4140 	[GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
4141 	[GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,
4142 	[GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
4143 	[WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
4144 	[GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,
4145 	[GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,
4146 	[GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,
4147 	[GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr,
4148 	[GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,
4149 	[WCSS_AXI_M_CLK_SRC] = &wcss_axi_m_clk_src.clkr,
4150 	[GCC_ANOC_WCSS_AXI_M_CLK] = &gcc_anoc_wcss_axi_m_clk.clkr,
4151 	[QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
4152 	[GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,
4153 	[GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,
4154 	[GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,
4155 	[GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
4156 	[GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr,
4157 	[GCC_PCNOC_AT_CLK] = &gcc_pcnoc_at_clk.clkr,
4158 	[GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
4159 	[GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
4160 	[QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
4161 	[GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr,
4162 	[GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr,
4163 	[QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
4164 	[GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr,
4165 	[QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
4166 	[GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,
4167 	[GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,
4168 	[GCC_QDSS_TSCTR_DIV2_CLK] = &gcc_qdss_tsctr_div2_clk.clkr,
4169 	[GCC_QDSS_TS_CLK] = &gcc_qdss_ts_clk.clkr,
4170 	[GCC_QDSS_TSCTR_DIV4_CLK] = &gcc_qdss_tsctr_div4_clk.clkr,
4171 	[GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
4172 	[GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr,
4173 	[GCC_QDSS_TSCTR_DIV16_CLK] = &gcc_qdss_tsctr_div16_clk.clkr,
4174 	[GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,
4175 	[GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,
4176 	[GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,
4177 	[GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr,
4178 	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
4179 	[GCC_QDSS_APB2JTAG_CLK] = &gcc_qdss_apb2jtag_clk.clkr,
4180 	[GCC_QDSS_TSCTR_DIV3_CLK] = &gcc_qdss_tsctr_div3_clk.clkr,
4181 	[QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr,
4182 	[GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
4183 	[Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
4184 	[GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,
4185 	[GCC_WCSS_Q6_TBU_CLK] = &gcc_wcss_q6_tbu_clk.clkr,
4186 	[GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr,
4187 	[Q6_AXIM2_CLK_SRC] = &q6_axim2_clk_src.clkr,
4188 	[NSSNOC_MEMNOC_BFDCD_CLK_SRC] = &nssnoc_memnoc_bfdcd_clk_src.clkr,
4189 	[GCC_NSSNOC_MEMNOC_CLK] = &gcc_nssnoc_memnoc_clk.clkr,
4190 	[GCC_NSSNOC_MEM_NOC_1_CLK] = &gcc_nssnoc_mem_noc_1_clk.clkr,
4191 	[GCC_NSS_TBU_CLK] = &gcc_nss_tbu_clk.clkr,
4192 	[GCC_MEM_NOC_NSSNOC_CLK] = &gcc_mem_noc_nssnoc_clk.clkr,
4193 	[LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr,
4194 	[LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr,
4195 	[ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
4196 	[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
4197 	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
4198 	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
4199 	[GP3_CLK_SRC] = &gp3_clk_src.clkr,
4200 	[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
4201 	[GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr,
4202 	[GCC_XO_CLK] = &gcc_xo_clk.clkr,
4203 	[GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
4204 	[GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
4205 	[GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
4206 	[GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
4207 	[GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
4208 	[GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
4209 	[GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
4210 	[GCC_Q6SS_BOOT_CLK] = &gcc_q6ss_boot_clk.clkr,
4211 	[UNIPHY_SYS_CLK_SRC] = &uniphy_sys_clk_src.clkr,
4212 	[NSS_TS_CLK_SRC] = &nss_ts_clk_src.clkr,
4213 	[GCC_ANOC_PCIE0_1LANE_M_CLK] = &gcc_anoc_pcie0_1lane_m_clk.clkr,
4214 	[GCC_ANOC_PCIE1_1LANE_M_CLK] = &gcc_anoc_pcie1_1lane_m_clk.clkr,
4215 	[GCC_ANOC_PCIE2_2LANE_M_CLK] = &gcc_anoc_pcie2_2lane_m_clk.clkr,
4216 	[GCC_ANOC_PCIE3_2LANE_M_CLK] = &gcc_anoc_pcie3_2lane_m_clk.clkr,
4217 	[GCC_SNOC_PCIE0_1LANE_S_CLK] = &gcc_snoc_pcie0_1lane_s_clk.clkr,
4218 	[GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,
4219 	[GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,
4220 	[GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
4221 	[GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
4222 	[GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
4223 	[GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr,
4224 	[GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr,
4225 };
4226 
4227 static const struct qcom_reset_map gcc_ipq9574_resets[] = {
4228 	[GCC_ADSS_BCR] = { 0x1c000, 0 },
4229 	[GCC_ANOC0_TBU_BCR] = { 0x1203c, 0 },
4230 	[GCC_ANOC1_TBU_BCR] = { 0x1204c, 0 },
4231 	[GCC_ANOC_BCR] = { 0x2e074, 0 },
4232 	[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000, 0 },
4233 	[GCC_APSS_TCU_BCR] = { 0x12014, 0 },
4234 	[GCC_BLSP1_BCR] = { 0x01000, 0 },
4235 	[GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4236 	[GCC_BLSP1_QUP2_BCR] = { 0x03000, 0 },
4237 	[GCC_BLSP1_QUP3_BCR] = { 0x04000, 0 },
4238 	[GCC_BLSP1_QUP4_BCR] = { 0x05000, 0 },
4239 	[GCC_BLSP1_QUP5_BCR] = { 0x06000, 0 },
4240 	[GCC_BLSP1_QUP6_BCR] = { 0x07000, 0 },
4241 	[GCC_BLSP1_UART1_BCR] = { 0x02028, 0 },
4242 	[GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4243 	[GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4244 	[GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4245 	[GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4246 	[GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4247 	[GCC_BOOT_ROM_BCR] = { 0x13028, 0 },
4248 	[GCC_CMN_BLK_BCR] = { 0x3a000, 0 },
4249 	[GCC_CMN_BLK_AHB_ARES] = { 0x3a010, 0 },
4250 	[GCC_CMN_BLK_SYS_ARES] = { 0x3a010, 1 },
4251 	[GCC_CMN_BLK_APU_ARES] = { 0x3a010, 2 },
4252 	[GCC_CRYPTO_BCR] = { 0x16000, 0 },
4253 	[GCC_DCC_BCR] = { 0x35000, 0 },
4254 	[GCC_DDRSS_BCR] = { 0x11000, 0 },
4255 	[GCC_IMEM_BCR] = { 0x0e000, 0 },
4256 	[GCC_LPASS_BCR] = { 0x27000, 0 },
4257 	[GCC_MDIO_BCR] = { 0x1703c, 0 },
4258 	[GCC_MPM_BCR] = { 0x37000, 0 },
4259 	[GCC_MSG_RAM_BCR] = { 0x26000, 0 },
4260 	[GCC_NSS_BCR] = { 0x17000, 0 },
4261 	[GCC_NSS_TBU_BCR] = { 0x12044, 0 },
4262 	[GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17038, 13 },
4263 	[GCC_NSSNOC_PCNOC_1_ARES] = { 0x17038, 12 },
4264 	[GCC_NSSNOC_SNOC_1_ARES] = { 0x17038,  11 },
4265 	[GCC_NSSNOC_XO_DCD_ARES] = { 0x17038,  10 },
4266 	[GCC_NSSNOC_TS_ARES] = { 0x17038, 9 },
4267 	[GCC_NSSCC_ARES] = { 0x17038, 8 },
4268 	[GCC_NSSNOC_NSSCC_ARES] = { 0x17038, 7 },
4269 	[GCC_NSSNOC_ATB_ARES] = { 0x17038, 6 },
4270 	[GCC_NSSNOC_MEMNOC_ARES] = { 0x17038, 5 },
4271 	[GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x17038, 4 },
4272 	[GCC_NSSNOC_SNOC_ARES] = { 0x17038, 3 },
4273 	[GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17038, 2 },
4274 	[GCC_NSS_CFG_ARES] = { 0x17038, 1 },
4275 	[GCC_UBI0_DBG_ARES] = { 0x17038, 0 },
4276 	[GCC_PCIE0PHY_PHY_BCR] = { 0x2805c, 0 },
4277 	[GCC_PCIE0_AHB_ARES] = { 0x28058, 7 },
4278 	[GCC_PCIE0_AUX_ARES] = { 0x28058, 6 },
4279 	[GCC_PCIE0_AXI_M_ARES] = { 0x28058, 5 },
4280 	[GCC_PCIE0_AXI_M_STICKY_ARES] = { 0x28058, 4 },
4281 	[GCC_PCIE0_AXI_S_ARES] = { 0x28058, 3 },
4282 	[GCC_PCIE0_AXI_S_STICKY_ARES] = { 0x28058, 2 },
4283 	[GCC_PCIE0_CORE_STICKY_ARES] = { 0x28058, 1 },
4284 	[GCC_PCIE0_PIPE_ARES] = { 0x28058, 0 },
4285 	[GCC_PCIE1_AHB_ARES] = { 0x29058, 7 },
4286 	[GCC_PCIE1_AUX_ARES] = { 0x29058, 6 },
4287 	[GCC_PCIE1_AXI_M_ARES] = { 0x29058, 5 },
4288 	[GCC_PCIE1_AXI_M_STICKY_ARES] = { 0x29058, 4 },
4289 	[GCC_PCIE1_AXI_S_ARES] = { 0x29058, 3 },
4290 	[GCC_PCIE1_AXI_S_STICKY_ARES] = { 0x29058, 2 },
4291 	[GCC_PCIE1_CORE_STICKY_ARES] = { 0x29058, 1 },
4292 	[GCC_PCIE1_PIPE_ARES] = { 0x29058, 0 },
4293 	[GCC_PCIE2_AHB_ARES] = { 0x2a058, 7 },
4294 	[GCC_PCIE2_AUX_ARES] = { 0x2a058, 6 },
4295 	[GCC_PCIE2_AXI_M_ARES] = { 0x2a058, 5 },
4296 	[GCC_PCIE2_AXI_M_STICKY_ARES] = { 0x2a058, 4 },
4297 	[GCC_PCIE2_AXI_S_ARES] = { 0x2a058, 3 },
4298 	[GCC_PCIE2_AXI_S_STICKY_ARES] = { 0x2a058, 2 },
4299 	[GCC_PCIE2_CORE_STICKY_ARES] = { 0x2a058, 1 },
4300 	[GCC_PCIE2_PIPE_ARES] = { 0x2a058, 0 },
4301 	[GCC_PCIE3_AHB_ARES] = { 0x2b058, 7 },
4302 	[GCC_PCIE3_AUX_ARES] = { 0x2b058, 6 },
4303 	[GCC_PCIE3_AXI_M_ARES] = { 0x2b058, 5 },
4304 	[GCC_PCIE3_AXI_M_STICKY_ARES] = { 0x2b058, 4 },
4305 	[GCC_PCIE3_AXI_S_ARES] = { 0x2b058, 3 },
4306 	[GCC_PCIE3_AXI_S_STICKY_ARES] = { 0x2b058, 2 },
4307 	[GCC_PCIE3_CORE_STICKY_ARES] = { 0x2b058, 1 },
4308 	[GCC_PCIE3_PIPE_ARES] = { 0x2b058, 0 },
4309 	[GCC_PCIE0_BCR] = { 0x28000, 0 },
4310 	[GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054, 0 },
4311 	[GCC_PCIE0_PHY_BCR] = { 0x28060, 0 },
4312 	[GCC_PCIE1_BCR] = { 0x29000, 0 },
4313 	[GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054, 0 },
4314 	[GCC_PCIE1_PHY_BCR] = { 0x29060, 0 },
4315 	[GCC_PCIE1PHY_PHY_BCR] = { 0x2905c, 0 },
4316 	[GCC_PCIE2_BCR] = { 0x2a000, 0 },
4317 	[GCC_PCIE2_LINK_DOWN_BCR] = { 0x2a054, 0 },
4318 	[GCC_PCIE2_PHY_BCR] = { 0x2a060, 0 },
4319 	[GCC_PCIE2PHY_PHY_BCR] = { 0x2a05c, 0 },
4320 	[GCC_PCIE3_BCR] = { 0x2b000, 0 },
4321 	[GCC_PCIE3_LINK_DOWN_BCR] = { 0x2b054, 0 },
4322 	[GCC_PCIE3PHY_PHY_BCR] = { 0x2b05c, 0 },
4323 	[GCC_PCIE3_PHY_BCR] = { 0x2b060, 0 },
4324 	[GCC_PCNOC_BCR] = { 0x31000, 0 },
4325 	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x31030, 0 },
4326 	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x31038, 0 },
4327 	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x31040, 0 },
4328 	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x31048, 0 },
4329 	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x31050, 0 },
4330 	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x31058, 0 },
4331 	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x31060, 0 },
4332 	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x31068, 0 },
4333 	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x31070, 0 },
4334 	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x31078, 0 },
4335 	[GCC_PCNOC_TBU_BCR] = { 0x12034, 0 },
4336 	[GCC_PRNG_BCR] = { 0x13020, 0 },
4337 	[GCC_Q6SS_DBG_ARES] = { 0x2506c, 4 },
4338 	[GCC_Q6_AHB_ARES] = { 0x2506c, 3 },
4339 	[GCC_Q6_AHB_S_ARES] = { 0x2506c, 2 },
4340 	[GCC_Q6_AXIM2_ARES] = { 0x2506c, 1 },
4341 	[GCC_Q6_AXIM_ARES] = { 0x2506c, 0 },
4342 	[GCC_QDSS_BCR] = { 0x2d000, 0 },
4343 	[GCC_QPIC_BCR] = { 0x32000, 0 },
4344 	[GCC_QPIC_AHB_ARES] = { 0x3201c, 1 },
4345 	[GCC_QPIC_ARES] = { 0x3201c, 0 },
4346 	[GCC_QUSB2_0_PHY_BCR] = { 0x2c068, 0 },
4347 	[GCC_RBCPR_BCR] = { 0x39000, 0 },
4348 	[GCC_RBCPR_MX_BCR] = { 0x39014, 0 },
4349 	[GCC_SDCC_BCR] = { 0x33000, 0 },
4350 	[GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4351 	[GCC_SMMU_CFG_BCR] = { 0x1202c, 0 },
4352 	[GCC_SNOC_BCR] = { 0x2e000, 0 },
4353 	[GCC_SPDM_BCR] = { 0x36000, 0 },
4354 	[GCC_TCSR_BCR] = { 0x3d000, 0 },
4355 	[GCC_TLMM_BCR] = { 0x3e000, 0 },
4356 	[GCC_TME_BCR] = { 0x10000, 0 },
4357 	[GCC_UNIPHY0_BCR] = { 0x17044, 0 },
4358 	[GCC_UNIPHY0_SYS_RESET] = { 0x17050, 0 },
4359 	[GCC_UNIPHY0_AHB_RESET] = { 0x17050, 1 },
4360 	[GCC_UNIPHY0_XPCS_RESET] = { 0x17050, 2 },
4361 	[GCC_UNIPHY1_SYS_RESET] = { 0x17060, 0 },
4362 	[GCC_UNIPHY1_AHB_RESET] = { 0x17060, 1 },
4363 	[GCC_UNIPHY1_XPCS_RESET] = { 0x17060, 2 },
4364 	[GCC_UNIPHY2_SYS_RESET] = { 0x17070, 0 },
4365 	[GCC_UNIPHY2_AHB_RESET] = { 0x17070, 1 },
4366 	[GCC_UNIPHY2_XPCS_RESET] = { 0x17070, 2 },
4367 	[GCC_UNIPHY1_BCR] = { 0x17054, 0 },
4368 	[GCC_UNIPHY2_BCR] = { 0x17064, 0 },
4369 	[GCC_USB0_PHY_BCR] = { 0x2c06c, 0 },
4370 	[GCC_USB3PHY_0_PHY_BCR] = { 0x2c070, 0 },
4371 	[GCC_USB_BCR] = { 0x2c000, 0 },
4372 	[GCC_USB_MISC_RESET] = { 0x2c064, 0 },
4373 	[GCC_WCSSAON_RESET] = { 0x25074, 0 },
4374 	[GCC_WCSS_ACMT_ARES] = { 0x25070, 5 },
4375 	[GCC_WCSS_AHB_S_ARES] = { 0x25070, 4 },
4376 	[GCC_WCSS_AXI_M_ARES] = { 0x25070, 3 },
4377 	[GCC_WCSS_BCR] = { 0x18004, 0 },
4378 	[GCC_WCSS_DBG_ARES] = { 0x25070, 2 },
4379 	[GCC_WCSS_DBG_BDG_ARES] = { 0x25070, 1 },
4380 	[GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 },
4381 	[GCC_WCSS_Q6_BCR] = { 0x18000, 0 },
4382 	[GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
4383 };
4384 
4385 #define IPQ_APPS_ID			9574	/* some unique value */
4386 
4387 static struct qcom_icc_hws_data icc_ipq9574_hws[] = {
4388 	{ MASTER_ANOC_PCIE0, SLAVE_ANOC_PCIE0, GCC_ANOC_PCIE0_1LANE_M_CLK },
4389 	{ MASTER_SNOC_PCIE0, SLAVE_SNOC_PCIE0, GCC_SNOC_PCIE0_1LANE_S_CLK },
4390 	{ MASTER_ANOC_PCIE1, SLAVE_ANOC_PCIE1, GCC_ANOC_PCIE1_1LANE_M_CLK },
4391 	{ MASTER_SNOC_PCIE1, SLAVE_SNOC_PCIE1, GCC_SNOC_PCIE1_1LANE_S_CLK },
4392 	{ MASTER_ANOC_PCIE2, SLAVE_ANOC_PCIE2, GCC_ANOC_PCIE2_2LANE_M_CLK },
4393 	{ MASTER_SNOC_PCIE2, SLAVE_SNOC_PCIE2, GCC_SNOC_PCIE2_2LANE_S_CLK },
4394 	{ MASTER_ANOC_PCIE3, SLAVE_ANOC_PCIE3, GCC_ANOC_PCIE3_2LANE_M_CLK },
4395 	{ MASTER_SNOC_PCIE3, SLAVE_SNOC_PCIE3, GCC_SNOC_PCIE3_2LANE_S_CLK },
4396 	{ MASTER_USB, SLAVE_USB, GCC_SNOC_USB_CLK },
4397 	{ MASTER_USB_AXI, SLAVE_USB_AXI, GCC_ANOC_USB_AXI_CLK },
4398 	{ MASTER_NSSNOC_NSSCC, SLAVE_NSSNOC_NSSCC, GCC_NSSNOC_NSSCC_CLK },
4399 	{ MASTER_NSSNOC_SNOC_0, SLAVE_NSSNOC_SNOC_0, GCC_NSSNOC_SNOC_CLK },
4400 	{ MASTER_NSSNOC_SNOC_1, SLAVE_NSSNOC_SNOC_1, GCC_NSSNOC_SNOC_1_CLK },
4401 	{ MASTER_NSSNOC_PCNOC_1, SLAVE_NSSNOC_PCNOC_1, GCC_NSSNOC_PCNOC_1_CLK },
4402 	{ MASTER_NSSNOC_QOSGEN_REF, SLAVE_NSSNOC_QOSGEN_REF, GCC_NSSNOC_QOSGEN_REF_CLK },
4403 	{ MASTER_NSSNOC_TIMEOUT_REF, SLAVE_NSSNOC_TIMEOUT_REF, GCC_NSSNOC_TIMEOUT_REF_CLK },
4404 	{ MASTER_NSSNOC_XO_DCD, SLAVE_NSSNOC_XO_DCD, GCC_NSSNOC_XO_DCD_CLK },
4405 	{ MASTER_NSSNOC_ATB, SLAVE_NSSNOC_ATB, GCC_NSSNOC_ATB_CLK },
4406 	{ MASTER_MEM_NOC_NSSNOC, SLAVE_MEM_NOC_NSSNOC, GCC_MEM_NOC_NSSNOC_CLK },
4407 	{ MASTER_NSSNOC_MEMNOC, SLAVE_NSSNOC_MEMNOC, GCC_NSSNOC_MEMNOC_CLK },
4408 	{ MASTER_NSSNOC_MEM_NOC_1, SLAVE_NSSNOC_MEM_NOC_1, GCC_NSSNOC_MEM_NOC_1_CLK },
4409 };
4410 
4411 static const struct of_device_id gcc_ipq9574_match_table[] = {
4412 	{ .compatible = "qcom,ipq9574-gcc" },
4413 	{ }
4414 };
4415 MODULE_DEVICE_TABLE(of, gcc_ipq9574_match_table);
4416 
4417 static const struct regmap_config gcc_ipq9574_regmap_config = {
4418 	.reg_bits       = 32,
4419 	.reg_stride     = 4,
4420 	.val_bits       = 32,
4421 	.max_register   = 0x7fffc,
4422 	.fast_io	= true,
4423 };
4424 
4425 static const struct qcom_cc_desc gcc_ipq9574_desc = {
4426 	.config = &gcc_ipq9574_regmap_config,
4427 	.clks = gcc_ipq9574_clks,
4428 	.num_clks = ARRAY_SIZE(gcc_ipq9574_clks),
4429 	.resets = gcc_ipq9574_resets,
4430 	.num_resets = ARRAY_SIZE(gcc_ipq9574_resets),
4431 	.clk_hws = gcc_ipq9574_hws,
4432 	.num_clk_hws = ARRAY_SIZE(gcc_ipq9574_hws),
4433 	.icc_hws = icc_ipq9574_hws,
4434 	.num_icc_hws = ARRAY_SIZE(icc_ipq9574_hws),
4435 	.icc_first_node_id = IPQ_APPS_ID,
4436 };
4437 
4438 static int gcc_ipq9574_probe(struct platform_device *pdev)
4439 {
4440 	return qcom_cc_probe(pdev, &gcc_ipq9574_desc);
4441 }
4442 
4443 static struct platform_driver gcc_ipq9574_driver = {
4444 	.probe = gcc_ipq9574_probe,
4445 	.driver = {
4446 		.name   = "qcom,gcc-ipq9574",
4447 		.of_match_table = gcc_ipq9574_match_table,
4448 		.sync_state = icc_sync_state,
4449 	},
4450 };
4451 
4452 static int __init gcc_ipq9574_init(void)
4453 {
4454 	return platform_driver_register(&gcc_ipq9574_driver);
4455 }
4456 core_initcall(gcc_ipq9574_init);
4457 
4458 static void __exit gcc_ipq9574_exit(void)
4459 {
4460 	platform_driver_unregister(&gcc_ipq9574_driver);
4461 }
4462 module_exit(gcc_ipq9574_exit);
4463 
4464 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ9574 Driver");
4465 MODULE_LICENSE("GPL");
4466