1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018,2020 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/interconnect-provider.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 15 #include <dt-bindings/clock/qcom,ipq5424-gcc.h> 16 #include <dt-bindings/interconnect/qcom,ipq5424.h> 17 #include <dt-bindings/reset/qcom,ipq5424-gcc.h> 18 19 #include "clk-alpha-pll.h" 20 #include "clk-branch.h" 21 #include "clk-rcg.h" 22 #include "clk-regmap.h" 23 #include "clk-regmap-divider.h" 24 #include "clk-regmap-mux.h" 25 #include "clk-regmap-phy-mux.h" 26 #include "common.h" 27 #include "reset.h" 28 29 enum { 30 DT_XO, 31 DT_SLEEP_CLK, 32 DT_PCIE30_PHY0_PIPE_CLK, 33 DT_PCIE30_PHY1_PIPE_CLK, 34 DT_PCIE30_PHY2_PIPE_CLK, 35 DT_PCIE30_PHY3_PIPE_CLK, 36 DT_USB_PCIE_WRAPPER_PIPE_CLK, 37 }; 38 39 enum { 40 P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 41 P_GPLL0_OUT_AUX, 42 P_GPLL0_OUT_MAIN, 43 P_GPLL2_OUT_AUX, 44 P_GPLL2_OUT_MAIN, 45 P_GPLL4_OUT_AUX, 46 P_GPLL4_OUT_MAIN, 47 P_SLEEP_CLK, 48 P_XO, 49 P_USB3PHY_0_PIPE, 50 }; 51 52 static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO }; 53 54 static struct clk_alpha_pll gpll0 = { 55 .offset = 0x20000, 56 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 57 .clkr = { 58 .enable_reg = 0xb000, 59 .enable_mask = BIT(0), 60 .hw.init = &(const struct clk_init_data) { 61 .name = "gpll0", 62 .parent_data = &gcc_parent_data_xo, 63 .num_parents = 1, 64 .ops = &clk_alpha_pll_ops, 65 }, 66 }, 67 }; 68 69 static struct clk_fixed_factor gpll0_div2 = { 70 .mult = 1, 71 .div = 2, 72 .hw.init = &(const struct clk_init_data) { 73 .name = "gpll0_div2", 74 .parent_hws = (const struct clk_hw *[]) { 75 &gpll0.clkr.hw 76 }, 77 .num_parents = 1, 78 .ops = &clk_fixed_factor_ops, 79 }, 80 }; 81 82 static struct clk_alpha_pll gpll2 = { 83 .offset = 0x21000, 84 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA], 85 .clkr = { 86 .enable_reg = 0xb000, 87 .enable_mask = BIT(1), 88 .hw.init = &(const struct clk_init_data) { 89 .name = "gpll2", 90 .parent_data = &gcc_parent_data_xo, 91 .num_parents = 1, 92 .ops = &clk_alpha_pll_ops, 93 }, 94 }, 95 }; 96 97 static const struct clk_div_table post_div_table_gpll2_out_main[] = { 98 { 0x1, 2 }, 99 { } 100 }; 101 102 static struct clk_alpha_pll_postdiv gpll2_out_main = { 103 .offset = 0x21000, 104 .post_div_table = post_div_table_gpll2_out_main, 105 .num_post_div = ARRAY_SIZE(post_div_table_gpll2_out_main), 106 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA], 107 .clkr.hw.init = &(const struct clk_init_data) { 108 .name = "gpll2_out_main", 109 .parent_hws = (const struct clk_hw*[]) { 110 &gpll2.clkr.hw, 111 }, 112 .num_parents = 1, 113 .ops = &clk_alpha_pll_postdiv_ro_ops, 114 }, 115 }; 116 117 static struct clk_alpha_pll gpll4 = { 118 .offset = 0x22000, 119 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 120 .clkr = { 121 .enable_reg = 0xb000, 122 .enable_mask = BIT(2), 123 .hw.init = &(const struct clk_init_data) { 124 .name = "gpll4", 125 .parent_data = &gcc_parent_data_xo, 126 .num_parents = 1, 127 .ops = &clk_alpha_pll_ops, 128 /* 129 * There are no consumers for this GPLL in kernel yet, 130 * (will be added soon), so the clock framework 131 * disables this source. But some of the clocks 132 * initialized by boot loaders uses this source. So we 133 * need to keep this clock ON. Add the 134 * CLK_IGNORE_UNUSED flag so the clock will not be 135 * disabled. Once the consumer in kernel is added, we 136 * can get rid of this flag. 137 */ 138 .flags = CLK_IGNORE_UNUSED, 139 }, 140 }, 141 }; 142 143 static const struct parent_map gcc_parent_map_xo[] = { 144 { P_XO, 0 }, 145 }; 146 147 static const struct parent_map gcc_parent_map_0[] = { 148 { P_XO, 0 }, 149 { P_GPLL0_OUT_MAIN, 1 }, 150 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 151 }; 152 153 static const struct clk_parent_data gcc_parent_data_0[] = { 154 { .index = DT_XO }, 155 { .hw = &gpll0.clkr.hw }, 156 { .hw = &gpll0_div2.hw }, 157 }; 158 159 static const struct parent_map gcc_parent_map_1[] = { 160 { P_XO, 0 }, 161 { P_GPLL0_OUT_MAIN, 1 }, 162 }; 163 164 static const struct clk_parent_data gcc_parent_data_1[] = { 165 { .index = DT_XO }, 166 { .hw = &gpll0.clkr.hw }, 167 }; 168 169 static const struct parent_map gcc_parent_map_2[] = { 170 { P_XO, 0 }, 171 { P_GPLL0_OUT_MAIN, 1 }, 172 { P_GPLL4_OUT_MAIN, 2 }, 173 }; 174 175 static const struct clk_parent_data gcc_parent_data_2[] = { 176 { .index = DT_XO }, 177 { .hw = &gpll0.clkr.hw }, 178 { .hw = &gpll4.clkr.hw }, 179 }; 180 181 static const struct parent_map gcc_parent_map_3[] = { 182 { P_XO, 0 }, 183 { P_GPLL4_OUT_MAIN, 1 }, 184 { P_GPLL0_OUT_AUX, 2 }, 185 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 186 }; 187 188 static const struct clk_parent_data gcc_parent_data_3[] = { 189 { .index = DT_XO }, 190 { .hw = &gpll4.clkr.hw }, 191 { .hw = &gpll0.clkr.hw }, 192 { .hw = &gpll0_div2.hw }, 193 }; 194 195 static const struct parent_map gcc_parent_map_4[] = { 196 { P_XO, 0 }, 197 }; 198 199 static const struct clk_parent_data gcc_parent_data_4[] = { 200 { .index = DT_XO }, 201 }; 202 203 static const struct parent_map gcc_parent_map_5[] = { 204 { P_XO, 0 }, 205 { P_GPLL4_OUT_AUX, 1 }, 206 { P_GPLL0_OUT_MAIN, 3 }, 207 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 208 }; 209 210 static const struct clk_parent_data gcc_parent_data_5[] = { 211 { .index = DT_XO }, 212 { .hw = &gpll4.clkr.hw }, 213 { .hw = &gpll0.clkr.hw }, 214 { .hw = &gpll0_div2.hw }, 215 }; 216 217 static const struct parent_map gcc_parent_map_6[] = { 218 { P_SLEEP_CLK, 6 }, 219 }; 220 221 static const struct clk_parent_data gcc_parent_data_6[] = { 222 { .index = DT_SLEEP_CLK }, 223 }; 224 225 static const struct parent_map gcc_parent_map_7[] = { 226 { P_XO, 0 }, 227 { P_GPLL0_OUT_MAIN, 1 }, 228 { P_GPLL0_OUT_AUX, 2 }, 229 { P_SLEEP_CLK, 6 }, 230 }; 231 232 static const struct clk_parent_data gcc_parent_data_7[] = { 233 { .index = DT_XO }, 234 { .hw = &gpll0.clkr.hw }, 235 { .hw = &gpll0.clkr.hw }, 236 { .index = DT_SLEEP_CLK }, 237 }; 238 239 static const struct parent_map gcc_parent_map_8[] = { 240 { P_XO, 0 }, 241 { P_GPLL0_OUT_MAIN, 1 }, 242 { P_GPLL2_OUT_MAIN, 2 }, 243 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 244 }; 245 246 static const struct clk_parent_data gcc_parent_data_8[] = { 247 { .index = DT_XO }, 248 { .hw = &gpll0.clkr.hw }, 249 { .hw = &gpll2_out_main.clkr.hw }, 250 { .hw = &gpll0_div2.hw }, 251 }; 252 253 static const struct parent_map gcc_parent_map_9[] = { 254 { P_XO, 0 }, 255 { P_GPLL0_OUT_MAIN, 1 }, 256 { P_GPLL4_OUT_MAIN, 2 }, 257 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 258 }; 259 260 static const struct clk_parent_data gcc_parent_data_9[] = { 261 { .index = DT_XO }, 262 { .hw = &gpll0.clkr.hw }, 263 { .hw = &gpll4.clkr.hw }, 264 { .hw = &gpll0_div2.hw }, 265 }; 266 267 static const struct parent_map gcc_parent_map_10[] = { 268 { P_XO, 0 }, 269 { P_GPLL0_OUT_AUX, 2 }, 270 { P_SLEEP_CLK, 6 }, 271 }; 272 273 static const struct clk_parent_data gcc_parent_data_10[] = { 274 { .index = DT_XO }, 275 { .hw = &gpll0.clkr.hw }, 276 { .index = DT_SLEEP_CLK }, 277 }; 278 279 static const struct parent_map gcc_parent_map_11[] = { 280 { P_XO, 0 }, 281 { P_GPLL0_OUT_MAIN, 1 }, 282 { P_GPLL2_OUT_AUX, 2 }, 283 }; 284 285 static const struct clk_parent_data gcc_parent_data_11[] = { 286 { .index = DT_XO }, 287 { .hw = &gpll0.clkr.hw }, 288 { .hw = &gpll2.clkr.hw }, 289 }; 290 291 static const struct freq_tbl ftbl_gcc_adss_pwm_clk_src[] = { 292 F(24000000, P_XO, 1, 0, 0), 293 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 294 { } 295 }; 296 297 static struct clk_rcg2 gcc_adss_pwm_clk_src = { 298 .cmd_rcgr = 0x1c004, 299 .mnd_width = 0, 300 .hid_width = 5, 301 .parent_map = gcc_parent_map_1, 302 .freq_tbl = ftbl_gcc_adss_pwm_clk_src, 303 .clkr.hw.init = &(const struct clk_init_data) { 304 .name = "gcc_adss_pwm_clk_src", 305 .parent_data = gcc_parent_data_1, 306 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 307 .ops = &clk_rcg2_ops, 308 }, 309 }; 310 311 static const struct freq_tbl ftbl_gcc_nss_ts_clk_src[] = { 312 F(24000000, P_XO, 1, 0, 0), 313 { } 314 }; 315 316 static struct clk_rcg2 gcc_xo_clk_src = { 317 .cmd_rcgr = 0x34004, 318 .mnd_width = 0, 319 .hid_width = 5, 320 .parent_map = gcc_parent_map_xo, 321 .freq_tbl = ftbl_gcc_nss_ts_clk_src, 322 .clkr.hw.init = &(const struct clk_init_data) { 323 .name = "gcc_xo_clk_src", 324 .parent_data = &gcc_parent_data_xo, 325 .num_parents = 1, 326 .ops = &clk_rcg2_ops, 327 }, 328 }; 329 330 static struct clk_branch gcc_xo_clk = { 331 .halt_reg = 0x34018, 332 .halt_check = BRANCH_HALT, 333 .clkr = { 334 .enable_reg = 0x34018, 335 .enable_mask = BIT(0), 336 .hw.init = &(const struct clk_init_data) { 337 .name = "gcc_xo_clk", 338 .parent_hws = (const struct clk_hw*[]) { 339 &gcc_xo_clk_src.clkr.hw, 340 }, 341 .num_parents = 1, 342 .flags = CLK_SET_RATE_PARENT, 343 .ops = &clk_branch2_ops, 344 }, 345 }, 346 }; 347 348 static struct clk_fixed_factor gcc_xo_div4_clk_src = { 349 .mult = 1, 350 .div = 4, 351 .hw.init = &(const struct clk_init_data) { 352 .name = "gcc_xo_div4_clk_src", 353 .parent_hws = (const struct clk_hw *[]) { 354 &gcc_xo_clk_src.clkr.hw 355 }, 356 .num_parents = 1, 357 .flags = CLK_SET_RATE_PARENT, 358 .ops = &clk_fixed_factor_ops, 359 }, 360 }; 361 362 static struct clk_rcg2 gcc_nss_ts_clk_src = { 363 .cmd_rcgr = 0x17088, 364 .mnd_width = 0, 365 .hid_width = 5, 366 .parent_map = gcc_parent_map_4, 367 .freq_tbl = ftbl_gcc_nss_ts_clk_src, 368 .clkr.hw.init = &(const struct clk_init_data) { 369 .name = "gcc_nss_ts_clk_src", 370 .parent_data = gcc_parent_data_4, 371 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 372 .ops = &clk_rcg2_ops, 373 }, 374 }; 375 376 static const struct freq_tbl ftbl_gcc_pcie0_axi_m_clk_src[] = { 377 F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0), 378 { } 379 }; 380 381 static struct clk_rcg2 gcc_pcie0_axi_m_clk_src = { 382 .cmd_rcgr = 0x28018, 383 .mnd_width = 0, 384 .hid_width = 5, 385 .parent_map = gcc_parent_map_2, 386 .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src, 387 .clkr.hw.init = &(const struct clk_init_data) { 388 .name = "gcc_pcie0_axi_m_clk_src", 389 .parent_data = gcc_parent_data_2, 390 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 391 .ops = &clk_rcg2_ops, 392 }, 393 }; 394 395 static struct clk_rcg2 gcc_pcie0_axi_s_clk_src = { 396 .cmd_rcgr = 0x28020, 397 .mnd_width = 0, 398 .hid_width = 5, 399 .parent_map = gcc_parent_map_2, 400 .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src, 401 .clkr.hw.init = &(const struct clk_init_data) { 402 .name = "gcc_pcie0_axi_s_clk_src", 403 .parent_data = gcc_parent_data_2, 404 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 405 .ops = &clk_rcg2_ops, 406 }, 407 }; 408 409 static struct clk_rcg2 gcc_pcie1_axi_m_clk_src = { 410 .cmd_rcgr = 0x29018, 411 .mnd_width = 0, 412 .hid_width = 5, 413 .parent_map = gcc_parent_map_2, 414 .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src, 415 .clkr.hw.init = &(const struct clk_init_data) { 416 .name = "gcc_pcie1_axi_m_clk_src", 417 .parent_data = gcc_parent_data_2, 418 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 419 .ops = &clk_rcg2_ops, 420 }, 421 }; 422 423 static struct clk_rcg2 gcc_pcie1_axi_s_clk_src = { 424 .cmd_rcgr = 0x29020, 425 .mnd_width = 0, 426 .hid_width = 5, 427 .parent_map = gcc_parent_map_2, 428 .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src, 429 .clkr.hw.init = &(const struct clk_init_data) { 430 .name = "gcc_pcie1_axi_s_clk_src", 431 .parent_data = gcc_parent_data_2, 432 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 433 .ops = &clk_rcg2_ops, 434 }, 435 }; 436 437 static const struct freq_tbl ftbl_gcc_pcie2_axi_m_clk_src[] = { 438 F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0), 439 { } 440 }; 441 442 static struct clk_rcg2 gcc_pcie2_axi_m_clk_src = { 443 .cmd_rcgr = 0x2a018, 444 .mnd_width = 0, 445 .hid_width = 5, 446 .parent_map = gcc_parent_map_2, 447 .freq_tbl = ftbl_gcc_pcie2_axi_m_clk_src, 448 .clkr.hw.init = &(const struct clk_init_data) { 449 .name = "gcc_pcie2_axi_m_clk_src", 450 .parent_data = gcc_parent_data_2, 451 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 452 .ops = &clk_rcg2_ops, 453 }, 454 }; 455 456 static struct clk_rcg2 gcc_pcie2_axi_s_clk_src = { 457 .cmd_rcgr = 0x2a020, 458 .mnd_width = 0, 459 .hid_width = 5, 460 .parent_map = gcc_parent_map_2, 461 .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src, 462 .clkr.hw.init = &(const struct clk_init_data) { 463 .name = "gcc_pcie2_axi_s_clk_src", 464 .parent_data = gcc_parent_data_2, 465 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 466 .ops = &clk_rcg2_ops, 467 }, 468 }; 469 470 static struct clk_rcg2 gcc_pcie3_axi_m_clk_src = { 471 .cmd_rcgr = 0x2b018, 472 .mnd_width = 0, 473 .hid_width = 5, 474 .parent_map = gcc_parent_map_2, 475 .freq_tbl = ftbl_gcc_pcie2_axi_m_clk_src, 476 .clkr.hw.init = &(const struct clk_init_data) { 477 .name = "gcc_pcie3_axi_m_clk_src", 478 .parent_data = gcc_parent_data_2, 479 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 480 .ops = &clk_rcg2_ops, 481 }, 482 }; 483 484 static struct clk_rcg2 gcc_pcie3_axi_s_clk_src = { 485 .cmd_rcgr = 0x2b020, 486 .mnd_width = 0, 487 .hid_width = 5, 488 .parent_map = gcc_parent_map_2, 489 .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src, 490 .clkr.hw.init = &(const struct clk_init_data) { 491 .name = "gcc_pcie3_axi_s_clk_src", 492 .parent_data = gcc_parent_data_2, 493 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 494 .ops = &clk_rcg2_ops, 495 }, 496 }; 497 498 static const struct freq_tbl ftbl_gcc_pcie_aux_clk_src[] = { 499 F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4), 500 { } 501 }; 502 503 static struct clk_rcg2 gcc_pcie_aux_clk_src = { 504 .cmd_rcgr = 0x28004, 505 .mnd_width = 16, 506 .hid_width = 5, 507 .parent_map = gcc_parent_map_7, 508 .freq_tbl = ftbl_gcc_pcie_aux_clk_src, 509 .clkr.hw.init = &(const struct clk_init_data) { 510 .name = "gcc_pcie_aux_clk_src", 511 .parent_data = gcc_parent_data_7, 512 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 513 .ops = &clk_rcg2_ops, 514 }, 515 }; 516 517 static const struct freq_tbl ftbl_gcc_qupv3_i2c0_clk_src[] = { 518 F(4800000, P_XO, 5, 0, 0), 519 F(9600000, P_XO, 2.5, 0, 0), 520 F(24000000, P_XO, 1, 0, 0), 521 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), 522 F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), 523 { } 524 }; 525 526 static struct clk_rcg2 gcc_qupv3_i2c0_clk_src = { 527 .cmd_rcgr = 0x2018, 528 .mnd_width = 0, 529 .hid_width = 5, 530 .parent_map = gcc_parent_map_0, 531 .freq_tbl = ftbl_gcc_qupv3_i2c0_clk_src, 532 .clkr.hw.init = &(const struct clk_init_data) { 533 .name = "gcc_qupv3_i2c0_clk_src", 534 .parent_data = gcc_parent_data_0, 535 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 536 .ops = &clk_rcg2_ops, 537 }, 538 }; 539 540 static struct clk_rcg2 gcc_qupv3_i2c1_clk_src = { 541 .cmd_rcgr = 0x3018, 542 .mnd_width = 0, 543 .hid_width = 5, 544 .parent_map = gcc_parent_map_0, 545 .freq_tbl = ftbl_gcc_qupv3_i2c0_clk_src, 546 .clkr.hw.init = &(const struct clk_init_data) { 547 .name = "gcc_qupv3_i2c1_clk_src", 548 .parent_data = gcc_parent_data_0, 549 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 550 .ops = &clk_rcg2_ops, 551 }, 552 }; 553 554 static const struct freq_tbl ftbl_gcc_qupv3_spi0_clk_src[] = { 555 F(960000, P_XO, 10, 2, 5), 556 F(4800000, P_XO, 5, 0, 0), 557 F(9600000, P_XO, 2, 4, 5), 558 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5), 559 F(24000000, P_XO, 1, 0, 0), 560 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2), 561 F(32000000, P_GPLL0_OUT_MAIN, 10, 2, 5), 562 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), 563 { } 564 }; 565 566 static struct clk_rcg2 gcc_qupv3_spi0_clk_src = { 567 .cmd_rcgr = 0x4004, 568 .mnd_width = 8, 569 .hid_width = 5, 570 .parent_map = gcc_parent_map_0, 571 .freq_tbl = ftbl_gcc_qupv3_spi0_clk_src, 572 .clkr.hw.init = &(const struct clk_init_data) { 573 .name = "gcc_qupv3_spi0_clk_src", 574 .parent_data = gcc_parent_data_0, 575 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 576 .ops = &clk_rcg2_ops, 577 }, 578 }; 579 580 static struct clk_rcg2 gcc_qupv3_spi1_clk_src = { 581 .cmd_rcgr = 0x5004, 582 .mnd_width = 8, 583 .hid_width = 5, 584 .parent_map = gcc_parent_map_0, 585 .freq_tbl = ftbl_gcc_qupv3_spi0_clk_src, 586 .clkr.hw.init = &(const struct clk_init_data) { 587 .name = "gcc_qupv3_spi1_clk_src", 588 .parent_data = gcc_parent_data_0, 589 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 590 .ops = &clk_rcg2_ops, 591 }, 592 }; 593 594 static const struct freq_tbl ftbl_gcc_qupv3_uart0_clk_src[] = { 595 F(960000, P_XO, 10, 2, 5), 596 F(4800000, P_XO, 5, 0, 0), 597 F(9600000, P_XO, 2, 4, 5), 598 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5), 599 F(24000000, P_XO, 1, 0, 0), 600 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2), 601 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), 602 F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), 603 { } 604 }; 605 606 static struct clk_rcg2 gcc_qupv3_uart0_clk_src = { 607 .cmd_rcgr = 0x202c, 608 .mnd_width = 16, 609 .hid_width = 5, 610 .parent_map = gcc_parent_map_0, 611 .freq_tbl = ftbl_gcc_qupv3_uart0_clk_src, 612 .clkr.hw.init = &(const struct clk_init_data) { 613 .name = "gcc_qupv3_uart0_clk_src", 614 .parent_data = gcc_parent_data_0, 615 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 616 .ops = &clk_rcg2_ops, 617 }, 618 }; 619 620 static struct clk_rcg2 gcc_qupv3_uart1_clk_src = { 621 .cmd_rcgr = 0x302c, 622 .mnd_width = 16, 623 .hid_width = 5, 624 .parent_map = gcc_parent_map_0, 625 .freq_tbl = ftbl_gcc_qupv3_uart0_clk_src, 626 .clkr.hw.init = &(const struct clk_init_data) { 627 .name = "gcc_qupv3_uart1_clk_src", 628 .parent_data = gcc_parent_data_0, 629 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 630 .ops = &clk_rcg2_ops, 631 }, 632 }; 633 634 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 635 F(144000, P_XO, 16, 12, 125), 636 F(400000, P_XO, 12, 1, 5), 637 F(24000000, P_XO, 1, 0, 0), 638 F(48000000, P_GPLL2_OUT_MAIN, 12, 1, 2), 639 F(96000000, P_GPLL2_OUT_MAIN, 6, 1, 2), 640 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 641 F(192000000, P_GPLL2_OUT_MAIN, 6, 0, 0), 642 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 643 { } 644 }; 645 646 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 647 .cmd_rcgr = 0x33004, 648 .mnd_width = 8, 649 .hid_width = 5, 650 .parent_map = gcc_parent_map_8, 651 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 652 .clkr.hw.init = &(const struct clk_init_data) { 653 .name = "gcc_sdcc1_apps_clk_src", 654 .parent_data = gcc_parent_data_8, 655 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 656 .ops = &clk_rcg2_floor_ops, 657 }, 658 }; 659 660 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 661 F(300000000, P_GPLL4_OUT_MAIN, 4, 0, 0), 662 { } 663 }; 664 665 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 666 .cmd_rcgr = 0x33018, 667 .mnd_width = 8, 668 .hid_width = 5, 669 .parent_map = gcc_parent_map_9, 670 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 671 .clkr.hw.init = &(const struct clk_init_data) { 672 .name = "gcc_sdcc1_ice_core_clk_src", 673 .parent_data = gcc_parent_data_9, 674 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 675 .ops = &clk_rcg2_ops, 676 }, 677 }; 678 679 static struct clk_rcg2 gcc_uniphy_sys_clk_src = { 680 .cmd_rcgr = 0x17090, 681 .mnd_width = 0, 682 .hid_width = 5, 683 .parent_map = gcc_parent_map_4, 684 .freq_tbl = ftbl_gcc_nss_ts_clk_src, 685 .clkr.hw.init = &(const struct clk_init_data) { 686 .name = "gcc_uniphy_sys_clk_src", 687 .parent_data = &gcc_parent_data_xo, 688 .num_parents = 1, 689 .ops = &clk_rcg2_ops, 690 }, 691 }; 692 693 static struct clk_rcg2 gcc_usb0_aux_clk_src = { 694 .cmd_rcgr = 0x2c018, 695 .mnd_width = 16, 696 .hid_width = 5, 697 .parent_map = gcc_parent_map_10, 698 .freq_tbl = ftbl_gcc_nss_ts_clk_src, 699 .clkr.hw.init = &(const struct clk_init_data) { 700 .name = "gcc_usb0_aux_clk_src", 701 .parent_data = gcc_parent_data_10, 702 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 703 .ops = &clk_rcg2_ops, 704 }, 705 }; 706 707 static const struct freq_tbl ftbl_gcc_usb0_master_clk_src[] = { 708 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 709 { } 710 }; 711 712 static struct clk_rcg2 gcc_usb0_master_clk_src = { 713 .cmd_rcgr = 0x2c004, 714 .mnd_width = 8, 715 .hid_width = 5, 716 .parent_map = gcc_parent_map_0, 717 .freq_tbl = ftbl_gcc_usb0_master_clk_src, 718 .clkr.hw.init = &(const struct clk_init_data) { 719 .name = "gcc_usb0_master_clk_src", 720 .parent_data = gcc_parent_data_0, 721 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 722 .ops = &clk_rcg2_ops, 723 }, 724 }; 725 726 static const struct freq_tbl ftbl_gcc_usb0_mock_utmi_clk_src[] = { 727 F(24000000, P_XO, 1, 0, 0), 728 F(60000000, P_GPLL4_OUT_AUX, 10, 1, 2), 729 { } 730 }; 731 732 static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = { 733 .cmd_rcgr = 0x2c02c, 734 .mnd_width = 8, 735 .hid_width = 5, 736 .parent_map = gcc_parent_map_5, 737 .freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src, 738 .clkr.hw.init = &(const struct clk_init_data) { 739 .name = "gcc_usb0_mock_utmi_clk_src", 740 .parent_data = gcc_parent_data_5, 741 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 742 .ops = &clk_rcg2_ops, 743 }, 744 }; 745 746 static struct clk_rcg2 gcc_usb1_mock_utmi_clk_src = { 747 .cmd_rcgr = 0x3c004, 748 .mnd_width = 8, 749 .hid_width = 5, 750 .parent_map = gcc_parent_map_5, 751 .freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src, 752 .clkr.hw.init = &(const struct clk_init_data) { 753 .name = "gcc_usb1_mock_utmi_clk_src", 754 .parent_data = gcc_parent_data_5, 755 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 756 .ops = &clk_rcg2_ops, 757 }, 758 }; 759 760 static const struct freq_tbl ftbl_gcc_wcss_ahb_clk_src[] = { 761 F(24000000, P_XO, 1, 0, 0), 762 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0), 763 { } 764 }; 765 766 static struct clk_rcg2 gcc_wcss_ahb_clk_src = { 767 .cmd_rcgr = 0x25030, 768 .freq_tbl = ftbl_gcc_wcss_ahb_clk_src, 769 .hid_width = 5, 770 .parent_map = gcc_parent_map_1, 771 .clkr.hw.init = &(const struct clk_init_data) { 772 .name = "gcc_wcss_ahb_clk_src", 773 .parent_data = gcc_parent_data_1, 774 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 775 .ops = &clk_rcg2_ops, 776 }, 777 }; 778 779 static const struct freq_tbl ftbl_gcc_qdss_at_clk_src[] = { 780 F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0), 781 { } 782 }; 783 784 static struct clk_rcg2 gcc_qdss_at_clk_src = { 785 .cmd_rcgr = 0x2d004, 786 .freq_tbl = ftbl_gcc_qdss_at_clk_src, 787 .hid_width = 5, 788 .parent_map = gcc_parent_map_3, 789 .clkr.hw.init = &(const struct clk_init_data) { 790 .name = "gcc_qdss_at_clk_src", 791 .parent_data = gcc_parent_data_3, 792 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 793 .ops = &clk_rcg2_ops, 794 }, 795 }; 796 797 static const struct freq_tbl ftbl_gcc_qdss_tsctr_clk_src[] = { 798 F(600000000, P_GPLL4_OUT_MAIN, 2, 0, 0), 799 { } 800 }; 801 802 static struct clk_rcg2 gcc_qdss_tsctr_clk_src = { 803 .cmd_rcgr = 0x2d01c, 804 .freq_tbl = ftbl_gcc_qdss_tsctr_clk_src, 805 .hid_width = 5, 806 .parent_map = gcc_parent_map_3, 807 .clkr.hw.init = &(const struct clk_init_data) { 808 .name = "gcc_qdss_tsctr_clk_src", 809 .parent_data = gcc_parent_data_3, 810 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 811 .ops = &clk_rcg2_ops, 812 }, 813 }; 814 815 static struct clk_fixed_factor gcc_qdss_tsctr_div2_clk_src = { 816 .mult = 1, 817 .div = 2, 818 .hw.init = &(const struct clk_init_data) { 819 .name = "gcc_qdss_tsctr_div2_clk_src", 820 .parent_hws = (const struct clk_hw *[]) { 821 &gcc_qdss_tsctr_clk_src.clkr.hw 822 }, 823 .num_parents = 1, 824 .flags = CLK_SET_RATE_PARENT, 825 .ops = &clk_fixed_factor_ops, 826 }, 827 }; 828 829 static struct clk_fixed_factor gcc_qdss_dap_sync_clk_src = { 830 .mult = 1, 831 .div = 4, 832 .hw.init = &(const struct clk_init_data) { 833 .name = "gcc_qdss_dap_sync_clk_src", 834 .parent_hws = (const struct clk_hw *[]) { 835 &gcc_qdss_tsctr_clk_src.clkr.hw 836 }, 837 .num_parents = 1, 838 .ops = &clk_fixed_factor_ops, 839 }, 840 }; 841 842 static const struct freq_tbl ftbl_gcc_system_noc_bfdcd_clk_src[] = { 843 F(24000000, P_XO, 1, 0, 0), 844 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0), 845 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 846 F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0), 847 { } 848 }; 849 850 static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src = { 851 .cmd_rcgr = 0x2e004, 852 .freq_tbl = ftbl_gcc_system_noc_bfdcd_clk_src, 853 .hid_width = 5, 854 .parent_map = gcc_parent_map_9, 855 .clkr.hw.init = &(const struct clk_init_data) { 856 .name = "gcc_system_noc_bfdcd_clk_src", 857 .parent_data = gcc_parent_data_9, 858 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 859 .ops = &clk_rcg2_ops, 860 }, 861 }; 862 863 static const struct freq_tbl ftbl_gcc_pcnoc_bfdcd_clk_src[] = { 864 F(24000000, P_XO, 1, 0, 0), 865 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), 866 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 867 { } 868 }; 869 870 static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src = { 871 .cmd_rcgr = 0x31004, 872 .mnd_width = 0, 873 .hid_width = 5, 874 .parent_map = gcc_parent_map_0, 875 .freq_tbl = ftbl_gcc_pcnoc_bfdcd_clk_src, 876 .clkr.hw.init = &(const struct clk_init_data) { 877 .name = "gcc_pcnoc_bfdcd_clk_src", 878 .parent_data = gcc_parent_data_0, 879 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 880 .ops = &clk_rcg2_ops, 881 }, 882 }; 883 884 static const struct freq_tbl ftbl_gcc_lpass_sway_clk_src[] = { 885 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0), 886 { } 887 }; 888 889 static struct clk_rcg2 gcc_lpass_sway_clk_src = { 890 .cmd_rcgr = 0x27004, 891 .mnd_width = 0, 892 .hid_width = 5, 893 .parent_map = gcc_parent_map_1, 894 .freq_tbl = ftbl_gcc_lpass_sway_clk_src, 895 .clkr.hw.init = &(const struct clk_init_data) { 896 .name = "gcc_lpass_sway_clk_src", 897 .parent_data = gcc_parent_data_1, 898 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 899 .ops = &clk_rcg2_ops, 900 }, 901 }; 902 903 static struct clk_rcg2 gcc_lpass_axim_clk_src = { 904 .cmd_rcgr = 0x2700c, 905 .mnd_width = 0, 906 .hid_width = 5, 907 .parent_map = gcc_parent_map_1, 908 .freq_tbl = ftbl_gcc_lpass_sway_clk_src, 909 .clkr.hw.init = &(const struct clk_init_data) { 910 .name = "gcc_lpass_axim_clk_src", 911 .parent_data = gcc_parent_data_1, 912 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 913 .ops = &clk_rcg2_ops, 914 }, 915 }; 916 917 static struct clk_fixed_factor gcc_eud_at_div_clk_src = { 918 .mult = 1, 919 .div = 6, 920 .hw.init = &(const struct clk_init_data) { 921 .name = "gcc_eud_at_div_clk_src", 922 .parent_hws = (const struct clk_hw *[]) { 923 &gcc_qdss_at_clk_src.clkr.hw }, 924 .num_parents = 1, 925 .flags = CLK_SET_RATE_PARENT, 926 .ops = &clk_fixed_factor_ops, 927 }, 928 }; 929 930 static const struct freq_tbl ftbl_gcc_sleep_clk_src[] = { 931 F(32000, P_SLEEP_CLK, 1, 0, 0), 932 { } 933 }; 934 935 static struct clk_rcg2 gcc_sleep_clk_src = { 936 .cmd_rcgr = 0x3400c, 937 .mnd_width = 0, 938 .hid_width = 5, 939 .parent_map = gcc_parent_map_6, 940 .freq_tbl = ftbl_gcc_sleep_clk_src, 941 .clkr.hw.init = &(const struct clk_init_data) { 942 .name = "gcc_sleep_clk_src", 943 .parent_data = gcc_parent_data_6, 944 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 945 .ops = &clk_rcg2_ops, 946 }, 947 }; 948 949 static const struct freq_tbl ftbl_gcc_qpic_io_macro_clk_src[] = { 950 F(24000000, P_XO, 1, 0, 0), 951 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 952 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 953 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 954 F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 955 { } 956 }; 957 958 static struct clk_rcg2 gcc_qpic_io_macro_clk_src = { 959 .cmd_rcgr = 0x32004, 960 .mnd_width = 0, 961 .hid_width = 5, 962 .parent_map = gcc_parent_map_11, 963 .freq_tbl = ftbl_gcc_qpic_io_macro_clk_src, 964 .clkr.hw.init = &(const struct clk_init_data) { 965 .name = "gcc_qpic_io_macro_clk_src", 966 .parent_data = gcc_parent_data_11, 967 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 968 .ops = &clk_rcg2_ops, 969 }, 970 }; 971 972 static struct clk_rcg2 gcc_qpic_clk_src = { 973 .cmd_rcgr = 0x32020, 974 .mnd_width = 0, 975 .hid_width = 5, 976 .parent_map = gcc_parent_map_11, 977 .freq_tbl = ftbl_gcc_qpic_io_macro_clk_src, 978 .clkr.hw.init = &(const struct clk_init_data) { 979 .name = "gcc_qpic_clk_src", 980 .parent_data = gcc_parent_data_11, 981 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 982 .ops = &clk_rcg2_ops, 983 }, 984 }; 985 986 static struct clk_rcg2 gcc_pcie0_rchng_clk_src = { 987 .cmd_rcgr = 0x28028, 988 .mnd_width = 0, 989 .hid_width = 5, 990 .parent_map = gcc_parent_map_1, 991 .freq_tbl = ftbl_gcc_adss_pwm_clk_src, 992 .clkr.hw.init = &(const struct clk_init_data) { 993 .name = "gcc_pcie0_rchng_clk_src", 994 .parent_data = gcc_parent_data_1, 995 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 996 .ops = &clk_rcg2_ops, 997 }, 998 }; 999 1000 static struct clk_rcg2 gcc_pcie1_rchng_clk_src = { 1001 .cmd_rcgr = 0x29028, 1002 .mnd_width = 0, 1003 .hid_width = 5, 1004 .parent_map = gcc_parent_map_1, 1005 .freq_tbl = ftbl_gcc_adss_pwm_clk_src, 1006 .clkr.hw.init = &(const struct clk_init_data) { 1007 .name = "gcc_pcie1_rchng_clk_src", 1008 .parent_data = gcc_parent_data_1, 1009 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1010 .ops = &clk_rcg2_ops, 1011 }, 1012 }; 1013 1014 static struct clk_rcg2 gcc_pcie2_rchng_clk_src = { 1015 .cmd_rcgr = 0x2a028, 1016 .mnd_width = 0, 1017 .hid_width = 5, 1018 .parent_map = gcc_parent_map_1, 1019 .freq_tbl = ftbl_gcc_adss_pwm_clk_src, 1020 .clkr.hw.init = &(const struct clk_init_data) { 1021 .name = "gcc_pcie2_rchng_clk_src", 1022 .parent_data = gcc_parent_data_1, 1023 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1024 .ops = &clk_rcg2_ops, 1025 }, 1026 }; 1027 1028 static struct clk_rcg2 gcc_pcie3_rchng_clk_src = { 1029 .cmd_rcgr = 0x2b028, 1030 .mnd_width = 0, 1031 .hid_width = 5, 1032 .parent_map = gcc_parent_map_1, 1033 .freq_tbl = ftbl_gcc_adss_pwm_clk_src, 1034 .clkr.hw.init = &(const struct clk_init_data) { 1035 .name = "gcc_pcie3_rchng_clk_src", 1036 .parent_data = gcc_parent_data_1, 1037 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1038 .ops = &clk_rcg2_ops, 1039 }, 1040 }; 1041 1042 static struct clk_regmap_div gcc_qupv3_i2c0_div_clk_src = { 1043 .reg = 0x2020, 1044 .shift = 0, 1045 .width = 2, 1046 .clkr.hw.init = &(const struct clk_init_data) { 1047 .name = "gcc_qupv3_i2c0_div_clk_src", 1048 .parent_hws = (const struct clk_hw*[]) { 1049 &gcc_qupv3_i2c0_clk_src.clkr.hw, 1050 }, 1051 .num_parents = 1, 1052 .flags = CLK_SET_RATE_PARENT, 1053 .ops = &clk_regmap_div_ro_ops, 1054 }, 1055 }; 1056 1057 static struct clk_regmap_div gcc_qupv3_i2c1_div_clk_src = { 1058 .reg = 0x3020, 1059 .shift = 0, 1060 .width = 2, 1061 .clkr.hw.init = &(const struct clk_init_data) { 1062 .name = "gcc_qupv3_i2c1_div_clk_src", 1063 .parent_hws = (const struct clk_hw*[]) { 1064 &gcc_qupv3_i2c1_clk_src.clkr.hw, 1065 }, 1066 .num_parents = 1, 1067 .flags = CLK_SET_RATE_PARENT, 1068 .ops = &clk_regmap_div_ro_ops, 1069 }, 1070 }; 1071 1072 static struct clk_regmap_div gcc_usb0_mock_utmi_div_clk_src = { 1073 .reg = 0x2c040, 1074 .shift = 0, 1075 .width = 2, 1076 .clkr.hw.init = &(const struct clk_init_data) { 1077 .name = "gcc_usb0_mock_utmi_div_clk_src", 1078 .parent_hws = (const struct clk_hw*[]) { 1079 &gcc_usb0_mock_utmi_clk_src.clkr.hw, 1080 }, 1081 .num_parents = 1, 1082 .flags = CLK_SET_RATE_PARENT, 1083 .ops = &clk_regmap_div_ro_ops, 1084 }, 1085 }; 1086 1087 static struct clk_regmap_div gcc_usb1_mock_utmi_div_clk_src = { 1088 .reg = 0x3c018, 1089 .shift = 0, 1090 .width = 2, 1091 .clkr.hw.init = &(const struct clk_init_data) { 1092 .name = "gcc_usb1_mock_utmi_div_clk_src", 1093 .parent_hws = (const struct clk_hw*[]) { 1094 &gcc_usb1_mock_utmi_clk_src.clkr.hw, 1095 }, 1096 .num_parents = 1, 1097 .flags = CLK_SET_RATE_PARENT, 1098 .ops = &clk_regmap_div_ro_ops, 1099 }, 1100 }; 1101 1102 static struct clk_branch gcc_adss_pwm_clk = { 1103 .halt_reg = 0x1c00c, 1104 .halt_check = BRANCH_HALT, 1105 .clkr = { 1106 .enable_reg = 0x1c00c, 1107 .enable_mask = BIT(0), 1108 .hw.init = &(const struct clk_init_data) { 1109 .name = "gcc_adss_pwm_clk", 1110 .parent_hws = (const struct clk_hw*[]) { 1111 &gcc_adss_pwm_clk_src.clkr.hw, 1112 }, 1113 .num_parents = 1, 1114 .flags = CLK_SET_RATE_PARENT, 1115 .ops = &clk_branch2_ops, 1116 }, 1117 }, 1118 }; 1119 1120 static struct clk_branch gcc_cnoc_pcie0_1lane_s_clk = { 1121 .halt_reg = 0x31088, 1122 .halt_check = BRANCH_HALT, 1123 .clkr = { 1124 .enable_reg = 0x31088, 1125 .enable_mask = BIT(0), 1126 .hw.init = &(const struct clk_init_data) { 1127 .name = "gcc_cnoc_pcie0_1lane_s_clk", 1128 .parent_hws = (const struct clk_hw*[]) { 1129 &gcc_pcie0_axi_s_clk_src.clkr.hw, 1130 }, 1131 .num_parents = 1, 1132 .flags = CLK_SET_RATE_PARENT, 1133 .ops = &clk_branch2_ops, 1134 }, 1135 }, 1136 }; 1137 1138 static struct clk_branch gcc_cnoc_pcie1_1lane_s_clk = { 1139 .halt_reg = 0x3108c, 1140 .halt_check = BRANCH_HALT, 1141 .clkr = { 1142 .enable_reg = 0x3108c, 1143 .enable_mask = BIT(0), 1144 .hw.init = &(const struct clk_init_data) { 1145 .name = "gcc_cnoc_pcie1_1lane_s_clk", 1146 .parent_hws = (const struct clk_hw*[]) { 1147 &gcc_pcie1_axi_s_clk_src.clkr.hw, 1148 }, 1149 .num_parents = 1, 1150 .flags = CLK_SET_RATE_PARENT, 1151 .ops = &clk_branch2_ops, 1152 }, 1153 }, 1154 }; 1155 1156 static struct clk_branch gcc_cnoc_pcie2_2lane_s_clk = { 1157 .halt_reg = 0x31090, 1158 .halt_check = BRANCH_HALT, 1159 .clkr = { 1160 .enable_reg = 0x31090, 1161 .enable_mask = BIT(0), 1162 .hw.init = &(const struct clk_init_data) { 1163 .name = "gcc_cnoc_pcie2_2lane_s_clk", 1164 .parent_hws = (const struct clk_hw*[]) { 1165 &gcc_pcie2_axi_s_clk_src.clkr.hw, 1166 }, 1167 .num_parents = 1, 1168 .flags = CLK_SET_RATE_PARENT, 1169 .ops = &clk_branch2_ops, 1170 }, 1171 }, 1172 }; 1173 1174 static struct clk_branch gcc_cnoc_pcie3_2lane_s_clk = { 1175 .halt_reg = 0x31094, 1176 .halt_check = BRANCH_HALT, 1177 .clkr = { 1178 .enable_reg = 0x31094, 1179 .enable_mask = BIT(0), 1180 .hw.init = &(const struct clk_init_data) { 1181 .name = "gcc_cnoc_pcie3_2lane_s_clk", 1182 .parent_hws = (const struct clk_hw*[]) { 1183 &gcc_pcie3_axi_s_clk_src.clkr.hw, 1184 }, 1185 .num_parents = 1, 1186 .flags = CLK_SET_RATE_PARENT, 1187 .ops = &clk_branch2_ops, 1188 }, 1189 }, 1190 }; 1191 1192 static struct clk_branch gcc_cnoc_usb_clk = { 1193 .halt_reg = 0x310a8, 1194 .halt_check = BRANCH_HALT_VOTED, 1195 .clkr = { 1196 .enable_reg = 0x310a8, 1197 .enable_mask = BIT(0), 1198 .hw.init = &(const struct clk_init_data) { 1199 .name = "gcc_cnoc_usb_clk", 1200 .parent_hws = (const struct clk_hw*[]) { 1201 &gcc_usb0_master_clk_src.clkr.hw, 1202 }, 1203 .num_parents = 1, 1204 .flags = CLK_SET_RATE_PARENT, 1205 .ops = &clk_branch2_ops, 1206 }, 1207 }, 1208 }; 1209 1210 static struct clk_branch gcc_mdio_ahb_clk = { 1211 .halt_reg = 0x17040, 1212 .halt_check = BRANCH_HALT, 1213 .clkr = { 1214 .enable_reg = 0x17040, 1215 .enable_mask = BIT(0), 1216 .hw.init = &(const struct clk_init_data) { 1217 .name = "gcc_mdio_ahb_clk", 1218 .parent_hws = (const struct clk_hw*[]) { 1219 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1220 }, 1221 .num_parents = 1, 1222 .flags = CLK_SET_RATE_PARENT, 1223 .ops = &clk_branch2_ops, 1224 }, 1225 }, 1226 }; 1227 1228 static struct clk_branch gcc_nss_ts_clk = { 1229 .halt_reg = 0x17018, 1230 .halt_check = BRANCH_HALT_VOTED, 1231 .clkr = { 1232 .enable_reg = 0x17018, 1233 .enable_mask = BIT(0), 1234 .hw.init = &(const struct clk_init_data) { 1235 .name = "gcc_nss_ts_clk", 1236 .parent_hws = (const struct clk_hw*[]) { 1237 &gcc_nss_ts_clk_src.clkr.hw, 1238 }, 1239 .num_parents = 1, 1240 .flags = CLK_SET_RATE_PARENT, 1241 .ops = &clk_branch2_ops, 1242 }, 1243 }, 1244 }; 1245 1246 static struct clk_branch gcc_nsscc_clk = { 1247 .halt_reg = 0x17034, 1248 .halt_check = BRANCH_HALT, 1249 .clkr = { 1250 .enable_reg = 0x17034, 1251 .enable_mask = BIT(0), 1252 .hw.init = &(const struct clk_init_data) { 1253 .name = "gcc_nsscc_clk", 1254 .parent_hws = (const struct clk_hw*[]) { 1255 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1256 }, 1257 .num_parents = 1, 1258 .flags = CLK_SET_RATE_PARENT, 1259 .ops = &clk_branch2_ops, 1260 }, 1261 }, 1262 }; 1263 1264 static struct clk_branch gcc_nsscfg_clk = { 1265 .halt_reg = 0x1702c, 1266 .halt_check = BRANCH_HALT, 1267 .clkr = { 1268 .enable_reg = 0x1702c, 1269 .enable_mask = BIT(0), 1270 .hw.init = &(const struct clk_init_data) { 1271 .name = "gcc_nsscfg_clk", 1272 .parent_hws = (const struct clk_hw*[]) { 1273 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1274 }, 1275 .num_parents = 1, 1276 .flags = CLK_SET_RATE_PARENT, 1277 .ops = &clk_branch2_ops, 1278 }, 1279 }, 1280 }; 1281 1282 static struct clk_branch gcc_nssnoc_atb_clk = { 1283 .halt_reg = 0x17014, 1284 .halt_check = BRANCH_HALT, 1285 .clkr = { 1286 .enable_reg = 0x17014, 1287 .enable_mask = BIT(0), 1288 .hw.init = &(const struct clk_init_data) { 1289 .name = "gcc_nssnoc_atb_clk", 1290 .parent_hws = (const struct clk_hw*[]) { 1291 &gcc_qdss_at_clk_src.clkr.hw, 1292 }, 1293 .num_parents = 1, 1294 .flags = CLK_SET_RATE_PARENT, 1295 .ops = &clk_branch2_ops, 1296 }, 1297 }, 1298 }; 1299 1300 static struct clk_branch gcc_nssnoc_nsscc_clk = { 1301 .halt_reg = 0x17030, 1302 .halt_check = BRANCH_HALT, 1303 .clkr = { 1304 .enable_reg = 0x17030, 1305 .enable_mask = BIT(0), 1306 .hw.init = &(const struct clk_init_data) { 1307 .name = "gcc_nssnoc_nsscc_clk", 1308 .parent_hws = (const struct clk_hw*[]) { 1309 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1310 }, 1311 .num_parents = 1, 1312 .flags = CLK_SET_RATE_PARENT, 1313 .ops = &clk_branch2_ops, 1314 }, 1315 }, 1316 }; 1317 1318 static struct clk_branch gcc_nssnoc_pcnoc_1_clk = { 1319 .halt_reg = 0x17080, 1320 .halt_check = BRANCH_HALT, 1321 .clkr = { 1322 .enable_reg = 0x17080, 1323 .enable_mask = BIT(0), 1324 .hw.init = &(const struct clk_init_data) { 1325 .name = "gcc_nssnoc_pcnoc_1_clk", 1326 .parent_hws = (const struct clk_hw*[]) { 1327 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1328 }, 1329 .num_parents = 1, 1330 .flags = CLK_SET_RATE_PARENT, 1331 .ops = &clk_branch2_ops, 1332 }, 1333 }, 1334 }; 1335 1336 static struct clk_branch gcc_nssnoc_qosgen_ref_clk = { 1337 .halt_reg = 0x1701c, 1338 .halt_check = BRANCH_HALT, 1339 .clkr = { 1340 .enable_reg = 0x1701c, 1341 .enable_mask = BIT(0), 1342 .hw.init = &(const struct clk_init_data) { 1343 .name = "gcc_nssnoc_qosgen_ref_clk", 1344 .parent_hws = (const struct clk_hw *[]) { 1345 &gcc_xo_div4_clk_src.hw 1346 }, 1347 .num_parents = 1, 1348 .flags = CLK_SET_RATE_PARENT, 1349 .ops = &clk_branch2_ops, 1350 }, 1351 }, 1352 }; 1353 1354 static struct clk_branch gcc_nssnoc_snoc_1_clk = { 1355 .halt_reg = 0x1707c, 1356 .halt_check = BRANCH_HALT, 1357 .clkr = { 1358 .enable_reg = 0x1707c, 1359 .enable_mask = BIT(0), 1360 .hw.init = &(const struct clk_init_data) { 1361 .name = "gcc_nssnoc_snoc_1_clk", 1362 .parent_hws = (const struct clk_hw*[]) { 1363 &gcc_system_noc_bfdcd_clk_src.clkr.hw 1364 }, 1365 .num_parents = 1, 1366 .flags = CLK_SET_RATE_PARENT, 1367 .ops = &clk_branch2_ops, 1368 }, 1369 }, 1370 }; 1371 1372 static struct clk_branch gcc_nssnoc_snoc_clk = { 1373 .halt_reg = 0x17028, 1374 .halt_check = BRANCH_HALT, 1375 .clkr = { 1376 .enable_reg = 0x17028, 1377 .enable_mask = BIT(0), 1378 .hw.init = &(const struct clk_init_data) { 1379 .name = "gcc_nssnoc_snoc_clk", 1380 .parent_hws = (const struct clk_hw*[]) { 1381 &gcc_system_noc_bfdcd_clk_src.clkr.hw 1382 }, 1383 .num_parents = 1, 1384 .flags = CLK_SET_RATE_PARENT, 1385 .ops = &clk_branch2_ops, 1386 }, 1387 }, 1388 }; 1389 1390 static struct clk_branch gcc_nssnoc_timeout_ref_clk = { 1391 .halt_reg = 0x17020, 1392 .halt_check = BRANCH_HALT, 1393 .clkr = { 1394 .enable_reg = 0x17020, 1395 .enable_mask = BIT(0), 1396 .hw.init = &(const struct clk_init_data) { 1397 .name = "gcc_nssnoc_timeout_ref_clk", 1398 .parent_hws = (const struct clk_hw*[]) { 1399 &gcc_xo_div4_clk_src.hw, 1400 }, 1401 .num_parents = 1, 1402 .flags = CLK_SET_RATE_PARENT, 1403 .ops = &clk_branch2_ops, 1404 }, 1405 }, 1406 }; 1407 1408 static struct clk_branch gcc_nssnoc_xo_dcd_clk = { 1409 .halt_reg = 0x17074, 1410 .halt_check = BRANCH_HALT, 1411 .clkr = { 1412 .enable_reg = 0x17074, 1413 .enable_mask = BIT(0), 1414 .hw.init = &(const struct clk_init_data) { 1415 .name = "gcc_nssnoc_xo_dcd_clk", 1416 .parent_hws = (const struct clk_hw*[]) { 1417 &gcc_xo_clk_src.clkr.hw, 1418 }, 1419 .num_parents = 1, 1420 .flags = CLK_SET_RATE_PARENT, 1421 .ops = &clk_branch2_ops, 1422 }, 1423 }, 1424 }; 1425 1426 static struct clk_branch gcc_pcie0_ahb_clk = { 1427 .halt_reg = 0x28030, 1428 .halt_check = BRANCH_HALT, 1429 .clkr = { 1430 .enable_reg = 0x28030, 1431 .enable_mask = BIT(0), 1432 .hw.init = &(const struct clk_init_data) { 1433 .name = "gcc_pcie0_ahb_clk", 1434 .parent_hws = (const struct clk_hw*[]) { 1435 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1436 }, 1437 .num_parents = 1, 1438 .flags = CLK_SET_RATE_PARENT, 1439 .ops = &clk_branch2_ops, 1440 }, 1441 }, 1442 }; 1443 1444 static struct clk_branch gcc_pcie0_aux_clk = { 1445 .halt_reg = 0x28070, 1446 .halt_check = BRANCH_HALT, 1447 .clkr = { 1448 .enable_reg = 0x28070, 1449 .enable_mask = BIT(0), 1450 .hw.init = &(const struct clk_init_data) { 1451 .name = "gcc_pcie0_aux_clk", 1452 .parent_hws = (const struct clk_hw*[]) { 1453 &gcc_pcie_aux_clk_src.clkr.hw, 1454 }, 1455 .num_parents = 1, 1456 .flags = CLK_SET_RATE_PARENT, 1457 .ops = &clk_branch2_ops, 1458 }, 1459 }, 1460 }; 1461 1462 static struct clk_branch gcc_pcie0_axi_m_clk = { 1463 .halt_reg = 0x28038, 1464 .halt_check = BRANCH_HALT, 1465 .clkr = { 1466 .enable_reg = 0x28038, 1467 .enable_mask = BIT(0), 1468 .hw.init = &(const struct clk_init_data) { 1469 .name = "gcc_pcie0_axi_m_clk", 1470 .parent_hws = (const struct clk_hw*[]) { 1471 &gcc_pcie0_axi_m_clk_src.clkr.hw, 1472 }, 1473 .num_parents = 1, 1474 .flags = CLK_SET_RATE_PARENT, 1475 .ops = &clk_branch2_ops, 1476 }, 1477 }, 1478 }; 1479 1480 static struct clk_branch gcc_anoc_pcie0_1lane_m_clk = { 1481 .halt_reg = 0x2e07c, 1482 .halt_check = BRANCH_HALT, 1483 .clkr = { 1484 .enable_reg = 0x2e07c, 1485 .enable_mask = BIT(0), 1486 .hw.init = &(const struct clk_init_data) { 1487 .name = "gcc_anoc_pcie0_1lane_m_clk", 1488 .parent_hws = (const struct clk_hw*[]) { 1489 &gcc_pcie0_axi_m_clk_src.clkr.hw, 1490 }, 1491 .num_parents = 1, 1492 .flags = CLK_SET_RATE_PARENT, 1493 .ops = &clk_branch2_ops, 1494 }, 1495 }, 1496 }; 1497 1498 static struct clk_branch gcc_pcie0_axi_s_bridge_clk = { 1499 .halt_reg = 0x28048, 1500 .halt_check = BRANCH_HALT, 1501 .clkr = { 1502 .enable_reg = 0x28048, 1503 .enable_mask = BIT(0), 1504 .hw.init = &(const struct clk_init_data) { 1505 .name = "gcc_pcie0_axi_s_bridge_clk", 1506 .parent_hws = (const struct clk_hw*[]) { 1507 &gcc_pcie0_axi_s_clk_src.clkr.hw, 1508 }, 1509 .num_parents = 1, 1510 .flags = CLK_SET_RATE_PARENT, 1511 .ops = &clk_branch2_ops, 1512 }, 1513 }, 1514 }; 1515 1516 static struct clk_branch gcc_pcie0_axi_s_clk = { 1517 .halt_reg = 0x28040, 1518 .halt_check = BRANCH_HALT, 1519 .clkr = { 1520 .enable_reg = 0x28040, 1521 .enable_mask = BIT(0), 1522 .hw.init = &(const struct clk_init_data) { 1523 .name = "gcc_pcie0_axi_s_clk", 1524 .parent_hws = (const struct clk_hw*[]) { 1525 &gcc_pcie0_axi_s_clk_src.clkr.hw, 1526 }, 1527 .num_parents = 1, 1528 .flags = CLK_SET_RATE_PARENT, 1529 .ops = &clk_branch2_ops, 1530 }, 1531 }, 1532 }; 1533 1534 static struct clk_regmap_phy_mux gcc_pcie0_pipe_clk_src = { 1535 .reg = 0x28064, 1536 .clkr = { 1537 .hw.init = &(const struct clk_init_data) { 1538 .name = "pcie0_pipe_clk_src", 1539 .parent_data = &(const struct clk_parent_data) { 1540 .index = DT_PCIE30_PHY0_PIPE_CLK, 1541 }, 1542 .num_parents = 1, 1543 .ops = &clk_regmap_phy_mux_ops, 1544 }, 1545 }, 1546 }; 1547 1548 static struct clk_branch gcc_pcie0_pipe_clk = { 1549 .halt_reg = 0x28068, 1550 .halt_check = BRANCH_HALT_DELAY, 1551 .clkr = { 1552 .enable_reg = 0x28068, 1553 .enable_mask = BIT(0), 1554 .hw.init = &(const struct clk_init_data) { 1555 .name = "gcc_pcie0_pipe_clk", 1556 .parent_hws = (const struct clk_hw *[]) { 1557 &gcc_pcie0_pipe_clk_src.clkr.hw 1558 }, 1559 .num_parents = 1, 1560 .flags = CLK_SET_RATE_PARENT, 1561 .ops = &clk_branch2_ops, 1562 }, 1563 }, 1564 }; 1565 1566 static struct clk_branch gcc_pcie1_ahb_clk = { 1567 .halt_reg = 0x29030, 1568 .halt_check = BRANCH_HALT, 1569 .clkr = { 1570 .enable_reg = 0x29030, 1571 .enable_mask = BIT(0), 1572 .hw.init = &(const struct clk_init_data) { 1573 .name = "gcc_pcie1_ahb_clk", 1574 .parent_hws = (const struct clk_hw*[]) { 1575 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1576 }, 1577 .num_parents = 1, 1578 .flags = CLK_SET_RATE_PARENT, 1579 .ops = &clk_branch2_ops, 1580 }, 1581 }, 1582 }; 1583 1584 static struct clk_branch gcc_pcie1_aux_clk = { 1585 .halt_reg = 0x29074, 1586 .halt_check = BRANCH_HALT, 1587 .clkr = { 1588 .enable_reg = 0x29074, 1589 .enable_mask = BIT(0), 1590 .hw.init = &(const struct clk_init_data) { 1591 .name = "gcc_pcie1_aux_clk", 1592 .parent_hws = (const struct clk_hw*[]) { 1593 &gcc_pcie_aux_clk_src.clkr.hw, 1594 }, 1595 .num_parents = 1, 1596 .flags = CLK_SET_RATE_PARENT, 1597 .ops = &clk_branch2_ops, 1598 }, 1599 }, 1600 }; 1601 1602 static struct clk_branch gcc_pcie1_axi_m_clk = { 1603 .halt_reg = 0x29038, 1604 .halt_check = BRANCH_HALT, 1605 .clkr = { 1606 .enable_reg = 0x29038, 1607 .enable_mask = BIT(0), 1608 .hw.init = &(const struct clk_init_data) { 1609 .name = "gcc_pcie1_axi_m_clk", 1610 .parent_hws = (const struct clk_hw*[]) { 1611 &gcc_pcie1_axi_m_clk_src.clkr.hw, 1612 }, 1613 .num_parents = 1, 1614 .flags = CLK_SET_RATE_PARENT, 1615 .ops = &clk_branch2_ops, 1616 }, 1617 }, 1618 }; 1619 1620 static struct clk_branch gcc_anoc_pcie1_1lane_m_clk = { 1621 .halt_reg = 0x2e084, 1622 .halt_check = BRANCH_HALT, 1623 .clkr = { 1624 .enable_reg = 0x2e084, 1625 .enable_mask = BIT(0), 1626 .hw.init = &(const struct clk_init_data) { 1627 .name = "gcc_anoc_pcie1_1lane_m_clk", 1628 .parent_hws = (const struct clk_hw*[]) { 1629 &gcc_pcie1_axi_m_clk_src.clkr.hw, 1630 }, 1631 .num_parents = 1, 1632 .flags = CLK_SET_RATE_PARENT, 1633 .ops = &clk_branch2_ops, 1634 }, 1635 }, 1636 }; 1637 1638 static struct clk_branch gcc_pcie1_axi_s_bridge_clk = { 1639 .halt_reg = 0x29048, 1640 .halt_check = BRANCH_HALT, 1641 .clkr = { 1642 .enable_reg = 0x29048, 1643 .enable_mask = BIT(0), 1644 .hw.init = &(const struct clk_init_data) { 1645 .name = "gcc_pcie1_axi_s_bridge_clk", 1646 .parent_hws = (const struct clk_hw*[]) { 1647 &gcc_pcie1_axi_s_clk_src.clkr.hw, 1648 }, 1649 .num_parents = 1, 1650 .flags = CLK_SET_RATE_PARENT, 1651 .ops = &clk_branch2_ops, 1652 }, 1653 }, 1654 }; 1655 1656 static struct clk_branch gcc_pcie1_axi_s_clk = { 1657 .halt_reg = 0x29040, 1658 .halt_check = BRANCH_HALT, 1659 .clkr = { 1660 .enable_reg = 0x29040, 1661 .enable_mask = BIT(0), 1662 .hw.init = &(const struct clk_init_data) { 1663 .name = "gcc_pcie1_axi_s_clk", 1664 .parent_hws = (const struct clk_hw*[]) { 1665 &gcc_pcie1_axi_s_clk_src.clkr.hw, 1666 }, 1667 .num_parents = 1, 1668 .flags = CLK_SET_RATE_PARENT, 1669 .ops = &clk_branch2_ops, 1670 }, 1671 }, 1672 }; 1673 1674 static struct clk_regmap_phy_mux gcc_pcie1_pipe_clk_src = { 1675 .reg = 0x29064, 1676 .clkr = { 1677 .hw.init = &(const struct clk_init_data) { 1678 .name = "pcie1_pipe_clk_src", 1679 .parent_data = &(const struct clk_parent_data) { 1680 .index = DT_PCIE30_PHY1_PIPE_CLK, 1681 }, 1682 .num_parents = 1, 1683 .ops = &clk_regmap_phy_mux_ops, 1684 }, 1685 }, 1686 }; 1687 1688 static struct clk_branch gcc_pcie1_pipe_clk = { 1689 .halt_reg = 0x29068, 1690 .halt_check = BRANCH_HALT_DELAY, 1691 .clkr = { 1692 .enable_reg = 0x29068, 1693 .enable_mask = BIT(0), 1694 .hw.init = &(const struct clk_init_data) { 1695 .name = "gcc_pcie1_pipe_clk", 1696 .parent_hws = (const struct clk_hw *[]) { 1697 &gcc_pcie1_pipe_clk_src.clkr.hw 1698 }, 1699 .num_parents = 1, 1700 .flags = CLK_SET_RATE_PARENT, 1701 1702 .ops = &clk_branch2_ops, 1703 }, 1704 }, 1705 }; 1706 1707 static struct clk_branch gcc_pcie2_ahb_clk = { 1708 .halt_reg = 0x2a030, 1709 .halt_check = BRANCH_HALT, 1710 .clkr = { 1711 .enable_reg = 0x2a030, 1712 .enable_mask = BIT(0), 1713 .hw.init = &(const struct clk_init_data) { 1714 .name = "gcc_pcie2_ahb_clk", 1715 .parent_hws = (const struct clk_hw*[]) { 1716 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1717 }, 1718 .num_parents = 1, 1719 .flags = CLK_SET_RATE_PARENT, 1720 .ops = &clk_branch2_ops, 1721 }, 1722 }, 1723 }; 1724 1725 static struct clk_branch gcc_pcie2_aux_clk = { 1726 .halt_reg = 0x2a078, 1727 .halt_check = BRANCH_HALT, 1728 .clkr = { 1729 .enable_reg = 0x2a078, 1730 .enable_mask = BIT(0), 1731 .hw.init = &(const struct clk_init_data) { 1732 .name = "gcc_pcie2_aux_clk", 1733 .parent_hws = (const struct clk_hw*[]) { 1734 &gcc_pcie_aux_clk_src.clkr.hw, 1735 }, 1736 .num_parents = 1, 1737 .flags = CLK_SET_RATE_PARENT, 1738 .ops = &clk_branch2_ops, 1739 }, 1740 }, 1741 }; 1742 1743 static struct clk_branch gcc_pcie2_axi_m_clk = { 1744 .halt_reg = 0x2a038, 1745 .halt_check = BRANCH_HALT, 1746 .clkr = { 1747 .enable_reg = 0x2a038, 1748 .enable_mask = BIT(0), 1749 .hw.init = &(const struct clk_init_data) { 1750 .name = "gcc_pcie2_axi_m_clk", 1751 .parent_hws = (const struct clk_hw*[]) { 1752 &gcc_pcie2_axi_m_clk_src.clkr.hw, 1753 }, 1754 .num_parents = 1, 1755 .flags = CLK_SET_RATE_PARENT, 1756 .ops = &clk_branch2_ops, 1757 }, 1758 }, 1759 }; 1760 1761 static struct clk_branch gcc_anoc_pcie2_2lane_m_clk = { 1762 .halt_reg = 0x2e080, 1763 .halt_check = BRANCH_HALT, 1764 .clkr = { 1765 .enable_reg = 0x2e080, 1766 .enable_mask = BIT(0), 1767 .hw.init = &(const struct clk_init_data) { 1768 .name = "gcc_anoc_pcie2_2lane_m_clk", 1769 .parent_hws = (const struct clk_hw*[]) { 1770 &gcc_pcie2_axi_m_clk_src.clkr.hw, 1771 }, 1772 .num_parents = 1, 1773 .flags = CLK_SET_RATE_PARENT, 1774 .ops = &clk_branch2_ops, 1775 }, 1776 }, 1777 }; 1778 1779 static struct clk_branch gcc_pcie2_axi_s_bridge_clk = { 1780 .halt_reg = 0x2a048, 1781 .halt_check = BRANCH_HALT, 1782 .clkr = { 1783 .enable_reg = 0x2a048, 1784 .enable_mask = BIT(0), 1785 .hw.init = &(const struct clk_init_data) { 1786 .name = "gcc_pcie2_axi_s_bridge_clk", 1787 .parent_hws = (const struct clk_hw*[]) { 1788 &gcc_pcie2_axi_s_clk_src.clkr.hw, 1789 }, 1790 .num_parents = 1, 1791 .flags = CLK_SET_RATE_PARENT, 1792 .ops = &clk_branch2_ops, 1793 }, 1794 }, 1795 }; 1796 1797 static struct clk_branch gcc_pcie2_axi_s_clk = { 1798 .halt_reg = 0x2a040, 1799 .halt_check = BRANCH_HALT, 1800 .clkr = { 1801 .enable_reg = 0x2a040, 1802 .enable_mask = BIT(0), 1803 .hw.init = &(const struct clk_init_data) { 1804 .name = "gcc_pcie2_axi_s_clk", 1805 .parent_hws = (const struct clk_hw*[]) { 1806 &gcc_pcie2_axi_s_clk_src.clkr.hw, 1807 }, 1808 .num_parents = 1, 1809 .flags = CLK_SET_RATE_PARENT, 1810 .ops = &clk_branch2_ops, 1811 }, 1812 }, 1813 }; 1814 1815 static struct clk_regmap_phy_mux gcc_pcie2_pipe_clk_src = { 1816 .reg = 0x2a064, 1817 .clkr = { 1818 .hw.init = &(const struct clk_init_data) { 1819 .name = "pcie2_pipe_clk_src", 1820 .parent_data = &(const struct clk_parent_data) { 1821 .index = DT_PCIE30_PHY2_PIPE_CLK, 1822 }, 1823 .num_parents = 1, 1824 .ops = &clk_regmap_phy_mux_ops, 1825 }, 1826 }, 1827 }; 1828 1829 static struct clk_branch gcc_pcie2_pipe_clk = { 1830 .halt_reg = 0x2a068, 1831 .halt_check = BRANCH_HALT_DELAY, 1832 .clkr = { 1833 .enable_reg = 0x2a068, 1834 .enable_mask = BIT(0), 1835 .hw.init = &(const struct clk_init_data) { 1836 .name = "gcc_pcie2_pipe_clk", 1837 .parent_hws = (const struct clk_hw *[]) { 1838 &gcc_pcie2_pipe_clk_src.clkr.hw 1839 }, 1840 .num_parents = 1, 1841 .flags = CLK_SET_RATE_PARENT, 1842 .ops = &clk_branch2_ops, 1843 }, 1844 }, 1845 }; 1846 1847 static struct clk_branch gcc_pcie3_ahb_clk = { 1848 .halt_reg = 0x2b030, 1849 .halt_check = BRANCH_HALT, 1850 .clkr = { 1851 .enable_reg = 0x2b030, 1852 .enable_mask = BIT(0), 1853 .hw.init = &(const struct clk_init_data) { 1854 .name = "gcc_pcie3_ahb_clk", 1855 .parent_hws = (const struct clk_hw*[]) { 1856 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1857 }, 1858 .num_parents = 1, 1859 .flags = CLK_SET_RATE_PARENT, 1860 .ops = &clk_branch2_ops, 1861 }, 1862 }, 1863 }; 1864 1865 static struct clk_branch gcc_pcie3_aux_clk = { 1866 .halt_reg = 0x2b07c, 1867 .halt_check = BRANCH_HALT, 1868 .clkr = { 1869 .enable_reg = 0x2b07c, 1870 .enable_mask = BIT(0), 1871 .hw.init = &(const struct clk_init_data) { 1872 .name = "gcc_pcie3_aux_clk", 1873 .parent_hws = (const struct clk_hw*[]) { 1874 &gcc_pcie_aux_clk_src.clkr.hw, 1875 }, 1876 .num_parents = 1, 1877 .flags = CLK_SET_RATE_PARENT, 1878 .ops = &clk_branch2_ops, 1879 }, 1880 }, 1881 }; 1882 1883 static struct clk_branch gcc_pcie3_axi_m_clk = { 1884 .halt_reg = 0x2b038, 1885 .halt_check = BRANCH_HALT, 1886 .clkr = { 1887 .enable_reg = 0x2b038, 1888 .enable_mask = BIT(0), 1889 .hw.init = &(const struct clk_init_data) { 1890 .name = "gcc_pcie3_axi_m_clk", 1891 .parent_hws = (const struct clk_hw*[]) { 1892 &gcc_pcie3_axi_m_clk_src.clkr.hw, 1893 }, 1894 .num_parents = 1, 1895 .flags = CLK_SET_RATE_PARENT, 1896 .ops = &clk_branch2_ops, 1897 }, 1898 }, 1899 }; 1900 1901 static struct clk_branch gcc_anoc_pcie3_2lane_m_clk = { 1902 .halt_reg = 0x2e090, 1903 .halt_check = BRANCH_HALT, 1904 .clkr = { 1905 .enable_reg = 0x2e090, 1906 .enable_mask = BIT(0), 1907 .hw.init = &(const struct clk_init_data) { 1908 .name = "gcc_anoc_pcie3_2lane_m_clk", 1909 .parent_hws = (const struct clk_hw*[]) { 1910 &gcc_pcie3_axi_m_clk_src.clkr.hw, 1911 }, 1912 .num_parents = 1, 1913 .flags = CLK_SET_RATE_PARENT, 1914 .ops = &clk_branch2_ops, 1915 }, 1916 }, 1917 }; 1918 1919 static struct clk_branch gcc_pcie3_axi_s_bridge_clk = { 1920 .halt_reg = 0x2b048, 1921 .halt_check = BRANCH_HALT, 1922 .clkr = { 1923 .enable_reg = 0x2b048, 1924 .enable_mask = BIT(0), 1925 .hw.init = &(const struct clk_init_data) { 1926 .name = "gcc_pcie3_axi_s_bridge_clk", 1927 .parent_hws = (const struct clk_hw*[]) { 1928 &gcc_pcie3_axi_s_clk_src.clkr.hw, 1929 }, 1930 .num_parents = 1, 1931 .flags = CLK_SET_RATE_PARENT, 1932 .ops = &clk_branch2_ops, 1933 }, 1934 }, 1935 }; 1936 1937 static struct clk_branch gcc_pcie3_axi_s_clk = { 1938 .halt_reg = 0x2b040, 1939 .halt_check = BRANCH_HALT, 1940 .clkr = { 1941 .enable_reg = 0x2b040, 1942 .enable_mask = BIT(0), 1943 .hw.init = &(const struct clk_init_data) { 1944 .name = "gcc_pcie3_axi_s_clk", 1945 .parent_hws = (const struct clk_hw*[]) { 1946 &gcc_pcie3_axi_s_clk_src.clkr.hw, 1947 }, 1948 .num_parents = 1, 1949 .flags = CLK_SET_RATE_PARENT, 1950 .ops = &clk_branch2_ops, 1951 }, 1952 }, 1953 }; 1954 1955 static struct clk_regmap_phy_mux gcc_pcie3_pipe_clk_src = { 1956 .reg = 0x2b064, 1957 .clkr = { 1958 .hw.init = &(const struct clk_init_data) { 1959 .name = "pcie3_pipe_clk_src", 1960 .parent_data = &(const struct clk_parent_data) { 1961 .index = DT_PCIE30_PHY3_PIPE_CLK, 1962 }, 1963 .num_parents = 1, 1964 .ops = &clk_regmap_phy_mux_ops, 1965 }, 1966 }, 1967 }; 1968 1969 static struct clk_branch gcc_pcie3_pipe_clk = { 1970 .halt_reg = 0x2b068, 1971 .halt_check = BRANCH_HALT_DELAY, 1972 .clkr = { 1973 .enable_reg = 0x2b068, 1974 .enable_mask = BIT(0), 1975 .hw.init = &(const struct clk_init_data) { 1976 .name = "gcc_pcie3_pipe_clk", 1977 .parent_hws = (const struct clk_hw *[]) { 1978 &gcc_pcie3_pipe_clk_src.clkr.hw 1979 }, 1980 .num_parents = 1, 1981 .flags = CLK_SET_RATE_PARENT, 1982 .ops = &clk_branch2_ops, 1983 }, 1984 }, 1985 }; 1986 1987 static struct clk_branch gcc_prng_ahb_clk = { 1988 .halt_reg = 0x13024, 1989 .halt_check = BRANCH_HALT_VOTED, 1990 .clkr = { 1991 .enable_reg = 0xb004, 1992 .enable_mask = BIT(10), 1993 .hw.init = &(const struct clk_init_data) { 1994 .name = "gcc_prng_ahb_clk", 1995 .parent_hws = (const struct clk_hw*[]) { 1996 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1997 }, 1998 .num_parents = 1, 1999 .flags = CLK_SET_RATE_PARENT, 2000 .ops = &clk_branch2_ops, 2001 }, 2002 }, 2003 }; 2004 2005 static struct clk_branch gcc_qupv3_ahb_mst_clk = { 2006 .halt_reg = 0x1014, 2007 .halt_check = BRANCH_HALT_VOTED, 2008 .clkr = { 2009 .enable_reg = 0xb004, 2010 .enable_mask = BIT(14), 2011 .hw.init = &(const struct clk_init_data) { 2012 .name = "gcc_qupv3_ahb_mst_clk", 2013 .parent_hws = (const struct clk_hw*[]) { 2014 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2015 }, 2016 .num_parents = 1, 2017 .flags = CLK_SET_RATE_PARENT, 2018 .ops = &clk_branch2_ops, 2019 }, 2020 }, 2021 }; 2022 2023 static struct clk_branch gcc_qupv3_ahb_slv_clk = { 2024 .halt_reg = 0x102c, 2025 .halt_check = BRANCH_HALT_VOTED, 2026 .clkr = { 2027 .enable_reg = 0xb004, 2028 .enable_mask = BIT(4), 2029 .hw.init = &(const struct clk_init_data) { 2030 .name = "gcc_qupv3_ahb_slv_clk", 2031 .parent_hws = (const struct clk_hw*[]) { 2032 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2033 }, 2034 .num_parents = 1, 2035 .flags = CLK_SET_RATE_PARENT, 2036 .ops = &clk_branch2_ops, 2037 }, 2038 }, 2039 }; 2040 2041 static struct clk_branch gcc_qupv3_i2c0_clk = { 2042 .halt_reg = 0x2024, 2043 .halt_check = BRANCH_HALT, 2044 .clkr = { 2045 .enable_reg = 0x2024, 2046 .enable_mask = BIT(0), 2047 .hw.init = &(const struct clk_init_data) { 2048 .name = "gcc_qupv3_i2c0_clk", 2049 .parent_hws = (const struct clk_hw*[]) { 2050 &gcc_qupv3_i2c0_div_clk_src.clkr.hw, 2051 }, 2052 .num_parents = 1, 2053 .flags = CLK_SET_RATE_PARENT, 2054 .ops = &clk_branch2_ops, 2055 }, 2056 }, 2057 }; 2058 2059 static struct clk_branch gcc_qupv3_i2c1_clk = { 2060 .halt_reg = 0x3024, 2061 .halt_check = BRANCH_HALT, 2062 .clkr = { 2063 .enable_reg = 0x3024, 2064 .enable_mask = BIT(0), 2065 .hw.init = &(const struct clk_init_data) { 2066 .name = "gcc_qupv3_i2c1_clk", 2067 .parent_hws = (const struct clk_hw*[]) { 2068 &gcc_qupv3_i2c1_div_clk_src.clkr.hw, 2069 }, 2070 .num_parents = 1, 2071 .flags = CLK_SET_RATE_PARENT, 2072 .ops = &clk_branch2_ops, 2073 }, 2074 }, 2075 }; 2076 2077 static struct clk_branch gcc_qupv3_spi0_clk = { 2078 .halt_reg = 0x4020, 2079 .halt_check = BRANCH_HALT, 2080 .clkr = { 2081 .enable_reg = 0x4020, 2082 .enable_mask = BIT(0), 2083 .hw.init = &(const struct clk_init_data) { 2084 .name = "gcc_qupv3_spi0_clk", 2085 .parent_hws = (const struct clk_hw*[]) { 2086 &gcc_qupv3_spi0_clk_src.clkr.hw, 2087 }, 2088 .num_parents = 1, 2089 .flags = CLK_SET_RATE_PARENT, 2090 .ops = &clk_branch2_ops, 2091 }, 2092 }, 2093 }; 2094 2095 static struct clk_branch gcc_qupv3_spi1_clk = { 2096 .halt_reg = 0x5020, 2097 .halt_check = BRANCH_HALT, 2098 .clkr = { 2099 .enable_reg = 0x5020, 2100 .enable_mask = BIT(0), 2101 .hw.init = &(const struct clk_init_data) { 2102 .name = "gcc_qupv3_spi1_clk", 2103 .parent_hws = (const struct clk_hw*[]) { 2104 &gcc_qupv3_spi1_clk_src.clkr.hw, 2105 }, 2106 .num_parents = 1, 2107 .flags = CLK_SET_RATE_PARENT, 2108 .ops = &clk_branch2_ops, 2109 }, 2110 }, 2111 }; 2112 2113 static struct clk_branch gcc_qupv3_uart0_clk = { 2114 .halt_reg = 0x2040, 2115 .halt_check = BRANCH_HALT, 2116 .clkr = { 2117 .enable_reg = 0x2040, 2118 .enable_mask = BIT(0), 2119 .hw.init = &(const struct clk_init_data) { 2120 .name = "gcc_qupv3_uart0_clk", 2121 .parent_hws = (const struct clk_hw*[]) { 2122 &gcc_qupv3_uart0_clk_src.clkr.hw, 2123 }, 2124 .num_parents = 1, 2125 .flags = CLK_SET_RATE_PARENT, 2126 .ops = &clk_branch2_ops, 2127 }, 2128 }, 2129 }; 2130 2131 static struct clk_branch gcc_qupv3_uart1_clk = { 2132 .halt_reg = 0x3040, 2133 .halt_check = BRANCH_HALT, 2134 .clkr = { 2135 .enable_reg = 0x3040, 2136 .enable_mask = BIT(0), 2137 .hw.init = &(const struct clk_init_data) { 2138 .name = "gcc_qupv3_uart1_clk", 2139 .parent_hws = (const struct clk_hw*[]) { 2140 &gcc_qupv3_uart1_clk_src.clkr.hw, 2141 }, 2142 .num_parents = 1, 2143 .flags = CLK_SET_RATE_PARENT, 2144 .ops = &clk_branch2_ops, 2145 }, 2146 }, 2147 }; 2148 2149 static struct clk_branch gcc_sdcc1_ahb_clk = { 2150 .halt_reg = 0x3303c, 2151 .halt_check = BRANCH_HALT, 2152 .clkr = { 2153 .enable_reg = 0x3303c, 2154 .enable_mask = BIT(0), 2155 .hw.init = &(const struct clk_init_data) { 2156 .name = "gcc_sdcc1_ahb_clk", 2157 .parent_hws = (const struct clk_hw*[]) { 2158 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2159 }, 2160 .num_parents = 1, 2161 .flags = CLK_SET_RATE_PARENT, 2162 .ops = &clk_branch2_ops, 2163 }, 2164 }, 2165 }; 2166 2167 static struct clk_branch gcc_sdcc1_apps_clk = { 2168 .halt_reg = 0x3302c, 2169 .halt_check = BRANCH_HALT, 2170 .clkr = { 2171 .enable_reg = 0x3302c, 2172 .enable_mask = BIT(0), 2173 .hw.init = &(const struct clk_init_data) { 2174 .name = "gcc_sdcc1_apps_clk", 2175 .parent_hws = (const struct clk_hw*[]) { 2176 &gcc_sdcc1_apps_clk_src.clkr.hw, 2177 }, 2178 .num_parents = 1, 2179 .flags = CLK_SET_RATE_PARENT, 2180 .ops = &clk_branch2_ops, 2181 }, 2182 }, 2183 }; 2184 2185 static struct clk_branch gcc_sdcc1_ice_core_clk = { 2186 .halt_reg = 0x33034, 2187 .halt_check = BRANCH_HALT, 2188 .clkr = { 2189 .enable_reg = 0x33034, 2190 .enable_mask = BIT(0), 2191 .hw.init = &(const struct clk_init_data) { 2192 .name = "gcc_sdcc1_ice_core_clk", 2193 .parent_hws = (const struct clk_hw*[]) { 2194 &gcc_sdcc1_ice_core_clk_src.clkr.hw, 2195 }, 2196 .num_parents = 1, 2197 .flags = CLK_SET_RATE_PARENT, 2198 .ops = &clk_branch2_ops, 2199 }, 2200 }, 2201 }; 2202 2203 static struct clk_branch gcc_uniphy0_ahb_clk = { 2204 .halt_reg = 0x1704c, 2205 .halt_check = BRANCH_HALT, 2206 .clkr = { 2207 .enable_reg = 0x1704c, 2208 .enable_mask = BIT(0), 2209 .hw.init = &(const struct clk_init_data) { 2210 .name = "gcc_uniphy0_ahb_clk", 2211 .parent_hws = (const struct clk_hw*[]) { 2212 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2213 }, 2214 .num_parents = 1, 2215 .flags = CLK_SET_RATE_PARENT, 2216 .ops = &clk_branch2_ops, 2217 }, 2218 }, 2219 }; 2220 2221 static struct clk_branch gcc_uniphy0_sys_clk = { 2222 .halt_reg = 0x17048, 2223 .halt_check = BRANCH_HALT_VOTED, 2224 .clkr = { 2225 .enable_reg = 0x17048, 2226 .enable_mask = BIT(0), 2227 .hw.init = &(const struct clk_init_data) { 2228 .name = "gcc_uniphy0_sys_clk", 2229 .parent_hws = (const struct clk_hw*[]) { 2230 &gcc_uniphy_sys_clk_src.clkr.hw, 2231 }, 2232 .num_parents = 1, 2233 .flags = CLK_SET_RATE_PARENT, 2234 .ops = &clk_branch2_ops, 2235 }, 2236 }, 2237 }; 2238 2239 static struct clk_branch gcc_uniphy1_ahb_clk = { 2240 .halt_reg = 0x1705c, 2241 .halt_check = BRANCH_HALT, 2242 .clkr = { 2243 .enable_reg = 0x1705c, 2244 .enable_mask = BIT(0), 2245 .hw.init = &(const struct clk_init_data) { 2246 .name = "gcc_uniphy1_ahb_clk", 2247 .parent_hws = (const struct clk_hw*[]) { 2248 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2249 }, 2250 .num_parents = 1, 2251 .flags = CLK_SET_RATE_PARENT, 2252 .ops = &clk_branch2_ops, 2253 }, 2254 }, 2255 }; 2256 2257 static struct clk_branch gcc_uniphy1_sys_clk = { 2258 .halt_reg = 0x17058, 2259 .halt_check = BRANCH_HALT_VOTED, 2260 .clkr = { 2261 .enable_reg = 0x17058, 2262 .enable_mask = BIT(0), 2263 .hw.init = &(const struct clk_init_data) { 2264 .name = "gcc_uniphy1_sys_clk", 2265 .parent_hws = (const struct clk_hw*[]) { 2266 &gcc_uniphy_sys_clk_src.clkr.hw, 2267 }, 2268 .num_parents = 1, 2269 .flags = CLK_SET_RATE_PARENT, 2270 .ops = &clk_branch2_ops, 2271 }, 2272 }, 2273 }; 2274 2275 static struct clk_branch gcc_uniphy2_ahb_clk = { 2276 .halt_reg = 0x1706c, 2277 .halt_check = BRANCH_HALT, 2278 .clkr = { 2279 .enable_reg = 0x1706c, 2280 .enable_mask = BIT(0), 2281 .hw.init = &(const struct clk_init_data) { 2282 .name = "gcc_uniphy2_ahb_clk", 2283 .parent_hws = (const struct clk_hw*[]) { 2284 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2285 }, 2286 .num_parents = 1, 2287 .flags = CLK_SET_RATE_PARENT, 2288 .ops = &clk_branch2_ops, 2289 }, 2290 }, 2291 }; 2292 2293 static struct clk_branch gcc_uniphy2_sys_clk = { 2294 .halt_reg = 0x17068, 2295 .halt_check = BRANCH_HALT_VOTED, 2296 .clkr = { 2297 .enable_reg = 0x17068, 2298 .enable_mask = BIT(0), 2299 .hw.init = &(const struct clk_init_data) { 2300 .name = "gcc_uniphy2_sys_clk", 2301 .parent_hws = (const struct clk_hw*[]) { 2302 &gcc_uniphy_sys_clk_src.clkr.hw, 2303 }, 2304 .num_parents = 1, 2305 .flags = CLK_SET_RATE_PARENT, 2306 .ops = &clk_branch2_ops, 2307 }, 2308 }, 2309 }; 2310 2311 static struct clk_branch gcc_usb0_aux_clk = { 2312 .halt_reg = 0x2c04c, 2313 .halt_check = BRANCH_HALT_VOTED, 2314 .clkr = { 2315 .enable_reg = 0x2c04c, 2316 .enable_mask = BIT(0), 2317 .hw.init = &(const struct clk_init_data) { 2318 .name = "gcc_usb0_aux_clk", 2319 .parent_hws = (const struct clk_hw*[]) { 2320 &gcc_usb0_aux_clk_src.clkr.hw, 2321 }, 2322 .num_parents = 1, 2323 .flags = CLK_SET_RATE_PARENT, 2324 .ops = &clk_branch2_ops, 2325 }, 2326 }, 2327 }; 2328 2329 static struct clk_branch gcc_usb0_master_clk = { 2330 .halt_reg = 0x2c044, 2331 .halt_check = BRANCH_HALT_VOTED, 2332 .clkr = { 2333 .enable_reg = 0x2c044, 2334 .enable_mask = BIT(0), 2335 .hw.init = &(const struct clk_init_data) { 2336 .name = "gcc_usb0_master_clk", 2337 .parent_hws = (const struct clk_hw*[]) { 2338 &gcc_usb0_master_clk_src.clkr.hw, 2339 }, 2340 .num_parents = 1, 2341 .flags = CLK_SET_RATE_PARENT, 2342 .ops = &clk_branch2_ops, 2343 }, 2344 }, 2345 }; 2346 2347 static struct clk_branch gcc_usb0_mock_utmi_clk = { 2348 .halt_reg = 0x2c050, 2349 .halt_check = BRANCH_HALT_VOTED, 2350 .clkr = { 2351 .enable_reg = 0x2c050, 2352 .enable_mask = BIT(0), 2353 .hw.init = &(const struct clk_init_data) { 2354 .name = "gcc_usb0_mock_utmi_clk", 2355 .parent_hws = (const struct clk_hw*[]) { 2356 &gcc_usb0_mock_utmi_div_clk_src.clkr.hw, 2357 }, 2358 .num_parents = 1, 2359 .flags = CLK_SET_RATE_PARENT, 2360 .ops = &clk_branch2_ops, 2361 }, 2362 }, 2363 }; 2364 2365 static struct clk_branch gcc_usb1_mock_utmi_clk = { 2366 .halt_reg = 0x3c024, 2367 .halt_check = BRANCH_HALT_VOTED, 2368 .clkr = { 2369 .enable_reg = 0x3c024, 2370 .enable_mask = BIT(0), 2371 .hw.init = &(const struct clk_init_data) { 2372 .name = "gcc_usb1_mock_utmi_clk", 2373 .parent_hws = (const struct clk_hw*[]) { 2374 &gcc_usb1_mock_utmi_div_clk_src.clkr.hw, 2375 }, 2376 .num_parents = 1, 2377 .flags = CLK_SET_RATE_PARENT, 2378 .ops = &clk_branch2_ops, 2379 }, 2380 }, 2381 }; 2382 2383 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = { 2384 .halt_reg = 0x2c05c, 2385 .halt_check = BRANCH_HALT_VOTED, 2386 .clkr = { 2387 .enable_reg = 0x2c05c, 2388 .enable_mask = BIT(0), 2389 .hw.init = &(const struct clk_init_data) { 2390 .name = "gcc_usb0_phy_cfg_ahb_clk", 2391 .parent_hws = (const struct clk_hw*[]) { 2392 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2393 }, 2394 .num_parents = 1, 2395 .flags = CLK_SET_RATE_PARENT, 2396 .ops = &clk_branch2_ops, 2397 }, 2398 }, 2399 }; 2400 2401 static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = { 2402 .halt_reg = 0x3c01c, 2403 .halt_check = BRANCH_HALT_VOTED, 2404 .clkr = { 2405 .enable_reg = 0x3c01c, 2406 .enable_mask = BIT(0), 2407 .hw.init = &(const struct clk_init_data) { 2408 .name = "gcc_usb1_phy_cfg_ahb_clk", 2409 .parent_hws = (const struct clk_hw*[]) { 2410 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2411 }, 2412 .num_parents = 1, 2413 .flags = CLK_SET_RATE_PARENT, 2414 .ops = &clk_branch2_ops, 2415 }, 2416 }, 2417 }; 2418 2419 static struct clk_branch gcc_usb1_master_clk = { 2420 .halt_reg = 0x3c028, 2421 .halt_check = BRANCH_HALT_VOTED, 2422 .clkr = { 2423 .enable_reg = 0x3c028, 2424 .enable_mask = BIT(0), 2425 .hw.init = &(const struct clk_init_data) { 2426 .name = "gcc_usb1_master_clk", 2427 .parent_hws = (const struct clk_hw*[]) { 2428 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2429 }, 2430 .num_parents = 1, 2431 .flags = CLK_SET_RATE_PARENT, 2432 .ops = &clk_branch2_ops, 2433 }, 2434 }, 2435 }; 2436 2437 static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = { 2438 .reg = 0x2c074, 2439 .clkr = { 2440 .hw.init = &(const struct clk_init_data) { 2441 .name = "gcc_usb0_pipe_clk_src", 2442 .parent_data = &(const struct clk_parent_data) { 2443 .index = DT_USB_PCIE_WRAPPER_PIPE_CLK, 2444 }, 2445 .num_parents = 1, 2446 .ops = &clk_regmap_phy_mux_ops, 2447 }, 2448 }, 2449 }; 2450 2451 static struct clk_branch gcc_usb0_pipe_clk = { 2452 .halt_reg = 0x2c054, 2453 .halt_check = BRANCH_HALT_DELAY, 2454 .clkr = { 2455 .enable_reg = 0x2c054, 2456 .enable_mask = BIT(0), 2457 .hw.init = &(const struct clk_init_data) { 2458 .name = "gcc_usb0_pipe_clk", 2459 .parent_hws = (const struct clk_hw *[]) { 2460 &gcc_usb0_pipe_clk_src.clkr.hw 2461 }, 2462 .num_parents = 1, 2463 .flags = CLK_SET_RATE_PARENT, 2464 .ops = &clk_branch2_ops, 2465 }, 2466 }, 2467 }; 2468 2469 static struct clk_branch gcc_usb0_sleep_clk = { 2470 .halt_reg = 0x2c058, 2471 .halt_check = BRANCH_HALT_VOTED, 2472 .clkr = { 2473 .enable_reg = 0x2c058, 2474 .enable_mask = BIT(0), 2475 .hw.init = &(const struct clk_init_data) { 2476 .name = "gcc_usb0_sleep_clk", 2477 .parent_hws = (const struct clk_hw*[]) { 2478 &gcc_sleep_clk_src.clkr.hw, 2479 }, 2480 .num_parents = 1, 2481 .flags = CLK_SET_RATE_PARENT, 2482 .ops = &clk_branch2_ops, 2483 }, 2484 }, 2485 }; 2486 2487 static struct clk_branch gcc_usb1_sleep_clk = { 2488 .halt_reg = 0x3c020, 2489 .halt_check = BRANCH_HALT_VOTED, 2490 .clkr = { 2491 .enable_reg = 0x3c020, 2492 .enable_mask = BIT(0), 2493 .hw.init = &(const struct clk_init_data) { 2494 .name = "gcc_usb1_sleep_clk", 2495 .parent_hws = (const struct clk_hw*[]) { 2496 &gcc_sleep_clk_src.clkr.hw, 2497 }, 2498 .num_parents = 1, 2499 .flags = CLK_SET_RATE_PARENT, 2500 .ops = &clk_branch2_ops, 2501 }, 2502 }, 2503 }; 2504 2505 static struct clk_branch gcc_cmn_12gpll_ahb_clk = { 2506 .halt_reg = 0x3a004, 2507 .halt_check = BRANCH_HALT, 2508 .clkr = { 2509 .enable_reg = 0x3a004, 2510 .enable_mask = BIT(0), 2511 .hw.init = &(const struct clk_init_data) { 2512 .name = "gcc_cmn_12gpll_ahb_clk", 2513 .parent_hws = (const struct clk_hw*[]) { 2514 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2515 }, 2516 .num_parents = 1, 2517 .flags = CLK_SET_RATE_PARENT, 2518 .ops = &clk_branch2_ops, 2519 }, 2520 }, 2521 }; 2522 2523 static struct clk_branch gcc_cmn_12gpll_sys_clk = { 2524 .halt_reg = 0x3a008, 2525 .halt_check = BRANCH_HALT, 2526 .clkr = { 2527 .enable_reg = 0x3a008, 2528 .enable_mask = BIT(0), 2529 .hw.init = &(const struct clk_init_data) { 2530 .name = "gcc_cmn_12gpll_sys_clk", 2531 .parent_hws = (const struct clk_hw*[]) { 2532 &gcc_uniphy_sys_clk_src.clkr.hw, 2533 }, 2534 .num_parents = 1, 2535 .flags = CLK_SET_RATE_PARENT, 2536 .ops = &clk_branch2_ops, 2537 }, 2538 }, 2539 }; 2540 2541 static struct clk_branch gcc_lpass_sway_clk = { 2542 .halt_reg = 0x27014, 2543 .halt_check = BRANCH_HALT, 2544 .clkr = { 2545 .enable_reg = 0x27014, 2546 .enable_mask = BIT(0), 2547 .hw.init = &(const struct clk_init_data) { 2548 .name = "gcc_lpass_sway_clk", 2549 .parent_hws = (const struct clk_hw*[]) { 2550 &gcc_lpass_sway_clk_src.clkr.hw, 2551 }, 2552 .num_parents = 1, 2553 .flags = CLK_SET_RATE_PARENT, 2554 .ops = &clk_branch2_ops, 2555 }, 2556 }, 2557 }; 2558 2559 static struct clk_branch gcc_cnoc_lpass_cfg_clk = { 2560 .halt_reg = 0x2e028, 2561 .halt_check = BRANCH_HALT, 2562 .clkr = { 2563 .enable_reg = 0x2e028, 2564 .enable_mask = BIT(0), 2565 .hw.init = &(const struct clk_init_data) { 2566 .name = "gcc_cnoc_lpass_cfg_clk", 2567 .parent_hws = (const struct clk_hw*[]) { 2568 &gcc_lpass_sway_clk_src.clkr.hw, 2569 }, 2570 .num_parents = 1, 2571 .flags = CLK_SET_RATE_PARENT, 2572 .ops = &clk_branch2_ops, 2573 }, 2574 }, 2575 }; 2576 2577 static struct clk_branch gcc_lpass_core_axim_clk = { 2578 .halt_reg = 0x27018, 2579 .halt_check = BRANCH_HALT_VOTED, 2580 .clkr = { 2581 .enable_reg = 0x27018, 2582 .enable_mask = BIT(0), 2583 .hw.init = &(const struct clk_init_data) { 2584 .name = "gcc_lpass_core_axim_clk", 2585 .parent_hws = (const struct clk_hw*[]) { 2586 &gcc_lpass_axim_clk_src.clkr.hw, 2587 }, 2588 .num_parents = 1, 2589 .flags = CLK_SET_RATE_PARENT, 2590 .ops = &clk_branch2_ops, 2591 }, 2592 }, 2593 }; 2594 2595 static struct clk_branch gcc_snoc_lpass_clk = { 2596 .halt_reg = 0x31020, 2597 .halt_check = BRANCH_HALT_VOTED, 2598 .clkr = { 2599 .enable_reg = 0x31020, 2600 .enable_mask = BIT(0), 2601 .hw.init = &(const struct clk_init_data) { 2602 .name = "gcc_snoc_lpass_clk", 2603 .parent_hws = (const struct clk_hw*[]) { 2604 &gcc_lpass_axim_clk_src.clkr.hw, 2605 }, 2606 .num_parents = 1, 2607 .flags = CLK_SET_RATE_PARENT, 2608 .ops = &clk_branch2_ops, 2609 }, 2610 }, 2611 }; 2612 2613 static struct clk_branch gcc_usb0_eud_at_clk = { 2614 .halt_reg = 0x30004, 2615 .halt_check = BRANCH_HALT_VOTED, 2616 .clkr = { 2617 .enable_reg = 0x30004, 2618 .enable_mask = BIT(0), 2619 .hw.init = &(const struct clk_init_data) { 2620 .name = "gcc_usb0_eud_at_clk", 2621 .parent_hws = (const struct clk_hw*[]) { 2622 &gcc_eud_at_div_clk_src.hw, 2623 }, 2624 .num_parents = 1, 2625 .flags = CLK_SET_RATE_PARENT, 2626 .ops = &clk_branch2_ops, 2627 }, 2628 }, 2629 }; 2630 2631 static struct clk_branch gcc_qpic_ahb_clk = { 2632 .halt_reg = 0x32010, 2633 .halt_check = BRANCH_HALT, 2634 .clkr = { 2635 .enable_reg = 0x32010, 2636 .enable_mask = BIT(0), 2637 .hw.init = &(const struct clk_init_data) { 2638 .name = "gcc_qpic_ahb_clk", 2639 .parent_hws = (const struct clk_hw*[]) { 2640 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2641 }, 2642 .num_parents = 1, 2643 .flags = CLK_SET_RATE_PARENT, 2644 .ops = &clk_branch2_ops, 2645 }, 2646 }, 2647 }; 2648 2649 static struct clk_branch gcc_qpic_clk = { 2650 .halt_reg = 0x32028, 2651 .halt_check = BRANCH_HALT, 2652 .clkr = { 2653 .enable_reg = 0x32028, 2654 .enable_mask = BIT(0), 2655 .hw.init = &(const struct clk_init_data) { 2656 .name = "gcc_qpic_clk", 2657 .parent_hws = (const struct clk_hw*[]) { 2658 &gcc_qpic_clk_src.clkr.hw, 2659 }, 2660 .num_parents = 1, 2661 .flags = CLK_SET_RATE_PARENT, 2662 .ops = &clk_branch2_ops, 2663 }, 2664 }, 2665 }; 2666 2667 static struct clk_branch gcc_qpic_io_macro_clk = { 2668 .halt_reg = 0x3200c, 2669 .halt_check = BRANCH_HALT, 2670 .clkr = { 2671 .enable_reg = 0x3200c, 2672 .enable_mask = BIT(0), 2673 .hw.init = &(const struct clk_init_data) { 2674 .name = "gcc_qpic_io_macro_clk", 2675 .parent_hws = (const struct clk_hw*[]) { 2676 &gcc_qpic_io_macro_clk_src.clkr.hw, 2677 }, 2678 .num_parents = 1, 2679 .flags = CLK_SET_RATE_PARENT, 2680 .ops = &clk_branch2_ops, 2681 }, 2682 }, 2683 }; 2684 2685 static struct clk_branch gcc_qdss_dap_clk = { 2686 .halt_reg = 0x2d058, 2687 .clkr = { 2688 .enable_reg = 0x2d058, 2689 .enable_mask = BIT(0), 2690 .hw.init = &(const struct clk_init_data) { 2691 .name = "gcc_qdss_dap_clk", 2692 .parent_hws = (const struct clk_hw *[]) { 2693 &gcc_qdss_dap_sync_clk_src.hw 2694 }, 2695 .num_parents = 1, 2696 .flags = CLK_SET_RATE_PARENT, 2697 .ops = &clk_branch2_ops, 2698 }, 2699 }, 2700 }; 2701 2702 static struct clk_branch gcc_qdss_at_clk = { 2703 .halt_reg = 0x2d034, 2704 .clkr = { 2705 .enable_reg = 0x2d034, 2706 .enable_mask = BIT(0), 2707 .hw.init = &(const struct clk_init_data) { 2708 .name = "gcc_qdss_at_clk", 2709 .parent_hws = (const struct clk_hw *[]) { 2710 &gcc_qdss_at_clk_src.clkr.hw 2711 }, 2712 .num_parents = 1, 2713 .flags = CLK_SET_RATE_PARENT, 2714 .ops = &clk_branch2_ops, 2715 }, 2716 }, 2717 }; 2718 2719 static struct clk_branch gcc_pcie0_rchng_clk = { 2720 .halt_reg = 0x28028, 2721 .clkr = { 2722 .enable_reg = 0x28028, 2723 .enable_mask = BIT(1), 2724 .hw.init = &(const struct clk_init_data) { 2725 .name = "gcc_pcie0_rchng_clk", 2726 .parent_hws = (const struct clk_hw *[]) { 2727 &gcc_pcie0_rchng_clk_src.clkr.hw 2728 }, 2729 .num_parents = 1, 2730 .flags = CLK_SET_RATE_PARENT, 2731 .ops = &clk_branch2_ops, 2732 }, 2733 }, 2734 }; 2735 2736 static struct clk_branch gcc_pcie1_rchng_clk = { 2737 .halt_reg = 0x29028, 2738 .clkr = { 2739 .enable_reg = 0x29028, 2740 .enable_mask = BIT(1), 2741 .hw.init = &(const struct clk_init_data) { 2742 .name = "gcc_pcie1_rchng_clk", 2743 .parent_hws = (const struct clk_hw *[]) { 2744 &gcc_pcie1_rchng_clk_src.clkr.hw 2745 }, 2746 .num_parents = 1, 2747 .flags = CLK_SET_RATE_PARENT, 2748 .ops = &clk_branch2_ops, 2749 }, 2750 }, 2751 }; 2752 2753 static struct clk_branch gcc_pcie2_rchng_clk = { 2754 .halt_reg = 0x2a028, 2755 .clkr = { 2756 .enable_reg = 0x2a028, 2757 .enable_mask = BIT(1), 2758 .hw.init = &(const struct clk_init_data) { 2759 .name = "gcc_pcie2_rchng_clk", 2760 .parent_hws = (const struct clk_hw *[]) { 2761 &gcc_pcie2_rchng_clk_src.clkr.hw 2762 }, 2763 .num_parents = 1, 2764 .flags = CLK_SET_RATE_PARENT, 2765 .ops = &clk_branch2_ops, 2766 }, 2767 }, 2768 }; 2769 2770 static struct clk_branch gcc_pcie3_rchng_clk = { 2771 .halt_reg = 0x2b028, 2772 .clkr = { 2773 .enable_reg = 0x2b028, 2774 .enable_mask = BIT(1), 2775 .hw.init = &(const struct clk_init_data) { 2776 .name = "gcc_pcie3_rchng_clk", 2777 .parent_hws = (const struct clk_hw *[]) { 2778 &gcc_pcie3_rchng_clk_src.clkr.hw 2779 }, 2780 .num_parents = 1, 2781 .flags = CLK_SET_RATE_PARENT, 2782 .ops = &clk_branch2_ops, 2783 }, 2784 }, 2785 }; 2786 2787 static struct clk_regmap *gcc_ipq5424_clocks[] = { 2788 [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr, 2789 [GCC_ADSS_PWM_CLK_SRC] = &gcc_adss_pwm_clk_src.clkr, 2790 [GCC_CNOC_PCIE0_1LANE_S_CLK] = &gcc_cnoc_pcie0_1lane_s_clk.clkr, 2791 [GCC_CNOC_PCIE1_1LANE_S_CLK] = &gcc_cnoc_pcie1_1lane_s_clk.clkr, 2792 [GCC_CNOC_PCIE2_2LANE_S_CLK] = &gcc_cnoc_pcie2_2lane_s_clk.clkr, 2793 [GCC_CNOC_PCIE3_2LANE_S_CLK] = &gcc_cnoc_pcie3_2lane_s_clk.clkr, 2794 [GCC_CNOC_USB_CLK] = &gcc_cnoc_usb_clk.clkr, 2795 [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr, 2796 [GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr, 2797 [GCC_NSS_TS_CLK_SRC] = &gcc_nss_ts_clk_src.clkr, 2798 [GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr, 2799 [GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr, 2800 [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr, 2801 [GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr, 2802 [GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr, 2803 [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr, 2804 [GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr, 2805 [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr, 2806 [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr, 2807 [GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr, 2808 [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr, 2809 [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr, 2810 [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr, 2811 [GCC_PCIE0_AXI_M_CLK_SRC] = &gcc_pcie0_axi_m_clk_src.clkr, 2812 [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, 2813 [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr, 2814 [GCC_PCIE0_AXI_S_CLK_SRC] = &gcc_pcie0_axi_s_clk_src.clkr, 2815 [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr, 2816 [GCC_ANOC_PCIE0_1LANE_M_CLK] = &gcc_anoc_pcie0_1lane_m_clk.clkr, 2817 [GCC_PCIE0_PIPE_CLK_SRC] = &gcc_pcie0_pipe_clk_src.clkr, 2818 [GCC_PCIE0_RCHNG_CLK_SRC] = &gcc_pcie0_rchng_clk_src.clkr, 2819 [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr, 2820 [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr, 2821 [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr, 2822 [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr, 2823 [GCC_PCIE1_AXI_M_CLK_SRC] = &gcc_pcie1_axi_m_clk_src.clkr, 2824 [GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr, 2825 [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr, 2826 [GCC_PCIE1_AXI_S_CLK_SRC] = &gcc_pcie1_axi_s_clk_src.clkr, 2827 [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, 2828 [GCC_ANOC_PCIE1_1LANE_M_CLK] = &gcc_anoc_pcie1_1lane_m_clk.clkr, 2829 [GCC_PCIE1_PIPE_CLK_SRC] = &gcc_pcie1_pipe_clk_src.clkr, 2830 [GCC_PCIE1_RCHNG_CLK_SRC] = &gcc_pcie1_rchng_clk_src.clkr, 2831 [GCC_PCIE1_RCHNG_CLK] = &gcc_pcie1_rchng_clk.clkr, 2832 [GCC_PCIE2_AHB_CLK] = &gcc_pcie2_ahb_clk.clkr, 2833 [GCC_PCIE2_AUX_CLK] = &gcc_pcie2_aux_clk.clkr, 2834 [GCC_PCIE2_AXI_M_CLK] = &gcc_pcie2_axi_m_clk.clkr, 2835 [GCC_PCIE2_AXI_M_CLK_SRC] = &gcc_pcie2_axi_m_clk_src.clkr, 2836 [GCC_PCIE2_AXI_S_BRIDGE_CLK] = &gcc_pcie2_axi_s_bridge_clk.clkr, 2837 [GCC_PCIE2_AXI_S_CLK] = &gcc_pcie2_axi_s_clk.clkr, 2838 [GCC_PCIE2_AXI_S_CLK_SRC] = &gcc_pcie2_axi_s_clk_src.clkr, 2839 [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr, 2840 [GCC_ANOC_PCIE2_2LANE_M_CLK] = &gcc_anoc_pcie2_2lane_m_clk.clkr, 2841 [GCC_PCIE2_PIPE_CLK_SRC] = &gcc_pcie2_pipe_clk_src.clkr, 2842 [GCC_PCIE2_RCHNG_CLK_SRC] = &gcc_pcie2_rchng_clk_src.clkr, 2843 [GCC_PCIE2_RCHNG_CLK] = &gcc_pcie2_rchng_clk.clkr, 2844 [GCC_PCIE3_AHB_CLK] = &gcc_pcie3_ahb_clk.clkr, 2845 [GCC_PCIE3_AUX_CLK] = &gcc_pcie3_aux_clk.clkr, 2846 [GCC_PCIE3_AXI_M_CLK] = &gcc_pcie3_axi_m_clk.clkr, 2847 [GCC_PCIE3_AXI_M_CLK_SRC] = &gcc_pcie3_axi_m_clk_src.clkr, 2848 [GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr, 2849 [GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr, 2850 [GCC_PCIE3_AXI_S_CLK_SRC] = &gcc_pcie3_axi_s_clk_src.clkr, 2851 [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr, 2852 [GCC_ANOC_PCIE3_2LANE_M_CLK] = &gcc_anoc_pcie3_2lane_m_clk.clkr, 2853 [GCC_PCIE3_PIPE_CLK_SRC] = &gcc_pcie3_pipe_clk_src.clkr, 2854 [GCC_PCIE3_RCHNG_CLK_SRC] = &gcc_pcie3_rchng_clk_src.clkr, 2855 [GCC_PCIE3_RCHNG_CLK] = &gcc_pcie3_rchng_clk.clkr, 2856 [GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr, 2857 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 2858 [GCC_QUPV3_AHB_MST_CLK] = &gcc_qupv3_ahb_mst_clk.clkr, 2859 [GCC_QUPV3_AHB_SLV_CLK] = &gcc_qupv3_ahb_slv_clk.clkr, 2860 [GCC_QUPV3_I2C0_CLK] = &gcc_qupv3_i2c0_clk.clkr, 2861 [GCC_QUPV3_I2C0_CLK_SRC] = &gcc_qupv3_i2c0_clk_src.clkr, 2862 [GCC_QUPV3_I2C0_DIV_CLK_SRC] = &gcc_qupv3_i2c0_div_clk_src.clkr, 2863 [GCC_QUPV3_I2C1_CLK] = &gcc_qupv3_i2c1_clk.clkr, 2864 [GCC_QUPV3_I2C1_CLK_SRC] = &gcc_qupv3_i2c1_clk_src.clkr, 2865 [GCC_QUPV3_I2C1_DIV_CLK_SRC] = &gcc_qupv3_i2c1_div_clk_src.clkr, 2866 [GCC_QUPV3_SPI0_CLK] = &gcc_qupv3_spi0_clk.clkr, 2867 [GCC_QUPV3_SPI0_CLK_SRC] = &gcc_qupv3_spi0_clk_src.clkr, 2868 [GCC_QUPV3_SPI1_CLK] = &gcc_qupv3_spi1_clk.clkr, 2869 [GCC_QUPV3_SPI1_CLK_SRC] = &gcc_qupv3_spi1_clk_src.clkr, 2870 [GCC_QUPV3_UART0_CLK] = &gcc_qupv3_uart0_clk.clkr, 2871 [GCC_QUPV3_UART0_CLK_SRC] = &gcc_qupv3_uart0_clk_src.clkr, 2872 [GCC_QUPV3_UART1_CLK] = &gcc_qupv3_uart1_clk.clkr, 2873 [GCC_QUPV3_UART1_CLK_SRC] = &gcc_qupv3_uart1_clk_src.clkr, 2874 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2875 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2876 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 2877 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 2878 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 2879 [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr, 2880 [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr, 2881 [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr, 2882 [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr, 2883 [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr, 2884 [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr, 2885 [GCC_UNIPHY_SYS_CLK_SRC] = &gcc_uniphy_sys_clk_src.clkr, 2886 [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr, 2887 [GCC_USB0_AUX_CLK_SRC] = &gcc_usb0_aux_clk_src.clkr, 2888 [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr, 2889 [GCC_USB0_MASTER_CLK_SRC] = &gcc_usb0_master_clk_src.clkr, 2890 [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr, 2891 [GCC_USB0_MOCK_UTMI_CLK_SRC] = &gcc_usb0_mock_utmi_clk_src.clkr, 2892 [GCC_USB0_MOCK_UTMI_DIV_CLK_SRC] = &gcc_usb0_mock_utmi_div_clk_src.clkr, 2893 [GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr, 2894 [GCC_USB0_PIPE_CLK_SRC] = &gcc_usb0_pipe_clk_src.clkr, 2895 [GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr, 2896 [GCC_USB1_MOCK_UTMI_CLK_SRC] = &gcc_usb1_mock_utmi_clk_src.clkr, 2897 [GCC_USB1_MOCK_UTMI_DIV_CLK_SRC] = &gcc_usb1_mock_utmi_div_clk_src.clkr, 2898 [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr, 2899 [GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr, 2900 [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr, 2901 [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr, 2902 [GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr, 2903 [GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr, 2904 [GCC_WCSS_AHB_CLK_SRC] = &gcc_wcss_ahb_clk_src.clkr, 2905 [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr, 2906 [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr, 2907 [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr, 2908 [GCC_CNOC_LPASS_CFG_CLK] = &gcc_cnoc_lpass_cfg_clk.clkr, 2909 [GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr, 2910 [GCC_SNOC_LPASS_CLK] = &gcc_snoc_lpass_clk.clkr, 2911 [GCC_QDSS_AT_CLK_SRC] = &gcc_qdss_at_clk_src.clkr, 2912 [GCC_QDSS_TSCTR_CLK_SRC] = &gcc_qdss_tsctr_clk_src.clkr, 2913 [GCC_SYSTEM_NOC_BFDCD_CLK_SRC] = &gcc_system_noc_bfdcd_clk_src.clkr, 2914 [GCC_PCNOC_BFDCD_CLK_SRC] = &gcc_pcnoc_bfdcd_clk_src.clkr, 2915 [GCC_LPASS_SWAY_CLK_SRC] = &gcc_lpass_sway_clk_src.clkr, 2916 [GCC_LPASS_AXIM_CLK_SRC] = &gcc_lpass_axim_clk_src.clkr, 2917 [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr, 2918 [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr, 2919 [GCC_QPIC_IO_MACRO_CLK_SRC] = &gcc_qpic_io_macro_clk_src.clkr, 2920 [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr, 2921 [GCC_QPIC_CLK_SRC] = &gcc_qpic_clk_src.clkr, 2922 [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr, 2923 [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr, 2924 [GCC_XO_CLK] = &gcc_xo_clk.clkr, 2925 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, 2926 [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, 2927 [GPLL0] = &gpll0.clkr, 2928 [GPLL2] = &gpll2.clkr, 2929 [GPLL2_OUT_MAIN] = &gpll2_out_main.clkr, 2930 [GPLL4] = &gpll4.clkr, 2931 }; 2932 2933 static const struct qcom_reset_map gcc_ipq5424_resets[] = { 2934 [GCC_QUPV3_BCR] = { 0x01000, 0 }, 2935 [GCC_QUPV3_I2C0_BCR] = { 0x02000, 0 }, 2936 [GCC_QUPV3_UART0_BCR] = { 0x02020, 0 }, 2937 [GCC_QUPV3_I2C1_BCR] = { 0x03000, 0 }, 2938 [GCC_QUPV3_UART1_BCR] = { 0x03028, 0 }, 2939 [GCC_QUPV3_SPI0_BCR] = { 0x04000, 0 }, 2940 [GCC_QUPV3_SPI1_BCR] = { 0x05000, 0 }, 2941 [GCC_IMEM_BCR] = { 0x0e000, 0 }, 2942 [GCC_TME_BCR] = { 0x100000, 0 }, 2943 [GCC_DDRSS_BCR] = { 0x11000, 0 }, 2944 [GCC_PRNG_BCR] = { 0x13020, 0 }, 2945 [GCC_BOOT_ROM_BCR] = { 0x13028, 0 }, 2946 [GCC_NSS_BCR] = { 0x17000, 0 }, 2947 [GCC_MDIO_BCR] = { 0x1703c, 0 }, 2948 [GCC_UNIPHY0_BCR] = { 0x17044, 0 }, 2949 [GCC_UNIPHY1_BCR] = { 0x17054, 0 }, 2950 [GCC_UNIPHY2_BCR] = { 0x17064, 0 }, 2951 [GCC_WCSS_BCR] = { 0x18004, 0 }, 2952 [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 }, 2953 [GCC_TME_SEC_BUS_BCR] = { 0xa1030, 0 }, 2954 [GCC_ADSS_BCR] = { 0x1c000, 0 }, 2955 [GCC_LPASS_BCR] = { 0x27000, 0 }, 2956 [GCC_PCIE0_BCR] = { 0x28000, 0 }, 2957 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054, 0 }, 2958 [GCC_PCIE0PHY_PHY_BCR] = { 0x2805c, 0 }, 2959 [GCC_PCIE0_PHY_BCR] = { 0x28060, 0 }, 2960 [GCC_PCIE1_BCR] = { 0x29000, 0 }, 2961 [GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054, 0 }, 2962 [GCC_PCIE1PHY_PHY_BCR] = { 0x2905c, 0 }, 2963 [GCC_PCIE1_PHY_BCR] = { 0x29060, 0 }, 2964 [GCC_PCIE2_BCR] = { 0x2a000, 0 }, 2965 [GCC_PCIE2_LINK_DOWN_BCR] = { 0x2a054, 0 }, 2966 [GCC_PCIE2PHY_PHY_BCR] = { 0x2a05c, 0 }, 2967 [GCC_PCIE2_PHY_BCR] = { 0x2a060, 0 }, 2968 [GCC_PCIE3_BCR] = { 0x2b000, 0 }, 2969 [GCC_PCIE3_LINK_DOWN_BCR] = { 0x2b054, 0 }, 2970 [GCC_PCIE3PHY_PHY_BCR] = { 0x2b05c, 0 }, 2971 [GCC_PCIE3_PHY_BCR] = { 0x2b060, 0 }, 2972 [GCC_USB_BCR] = { 0x2c000, 0 }, 2973 [GCC_QUSB2_0_PHY_BCR] = { 0x2c068, 0 }, 2974 [GCC_USB0_PHY_BCR] = { 0x2c06c, 0 }, 2975 [GCC_USB3PHY_0_PHY_BCR] = { 0x2c070, 0 }, 2976 [GCC_QDSS_BCR] = { 0x2d000, 0 }, 2977 [GCC_SNOC_BCR] = { 0x2e000, 0 }, 2978 [GCC_ANOC_BCR] = { 0x2e074, 0 }, 2979 [GCC_PCNOC_BCR] = { 0x31000, 0 }, 2980 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x31030, 0 }, 2981 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x31038, 0 }, 2982 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x31040, 0 }, 2983 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x31048, 0 }, 2984 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x31050, 0 }, 2985 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x31058, 0 }, 2986 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x31060, 0 }, 2987 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x31068, 0 }, 2988 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x31070, 0 }, 2989 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x31078, 0 }, 2990 [GCC_QPIC_BCR] = { 0x32000, 0 }, 2991 [GCC_SDCC_BCR] = { 0x33000, 0 }, 2992 [GCC_DCC_BCR] = { 0x35000, 0 }, 2993 [GCC_SPDM_BCR] = { 0x36000, 0 }, 2994 [GCC_MPM_BCR] = { 0x37000, 0 }, 2995 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000, 0 }, 2996 [GCC_RBCPR_BCR] = { 0x39000, 0 }, 2997 [GCC_CMN_BLK_BCR] = { 0x3a000, 0 }, 2998 [GCC_TCSR_BCR] = { 0x3d000, 0 }, 2999 [GCC_TLMM_BCR] = { 0x3e000, 0 }, 3000 [GCC_QUPV3_AHB_MST_ARES] = { 0x01014, 2 }, 3001 [GCC_QUPV3_CORE_ARES] = { 0x01018, 2 }, 3002 [GCC_QUPV3_2X_CORE_ARES] = { 0x01020, 2 }, 3003 [GCC_QUPV3_SLEEP_ARES] = { 0x01028, 2 }, 3004 [GCC_QUPV3_AHB_SLV_ARES] = { 0x0102c, 2 }, 3005 [GCC_QUPV3_I2C0_ARES] = { 0x02024, 2 }, 3006 [GCC_QUPV3_UART0_ARES] = { 0x02040, 2 }, 3007 [GCC_QUPV3_I2C1_ARES] = { 0x03024, 2 }, 3008 [GCC_QUPV3_UART1_ARES] = { 0x03040, 2 }, 3009 [GCC_QUPV3_SPI0_ARES] = { 0x04020, 2 }, 3010 [GCC_QUPV3_SPI1_ARES] = { 0x05020, 2 }, 3011 [GCC_DEBUG_ARES] = { 0x06068, 2 }, 3012 [GCC_GP1_ARES] = { 0x08018, 2 }, 3013 [GCC_GP2_ARES] = { 0x09018, 2 }, 3014 [GCC_GP3_ARES] = { 0x0a018, 2 }, 3015 [GCC_IMEM_AXI_ARES] = { 0x0e004, 2 }, 3016 [GCC_IMEM_CFG_AHB_ARES] = { 0x0e00c, 2 }, 3017 [GCC_TME_ARES] = { 0x100b4, 2 }, 3018 [GCC_TME_TS_ARES] = { 0x100c0, 2 }, 3019 [GCC_TME_SLOW_ARES] = { 0x100d0, 2 }, 3020 [GCC_TME_RTC_TOGGLE_ARES] = { 0x100d8, 2 }, 3021 [GCC_TIC_ARES] = { 0x12004, 2 }, 3022 [GCC_PRNG_AHB_ARES] = { 0x13024, 2 }, 3023 [GCC_BOOT_ROM_AHB_ARES] = { 0x1302c, 2 }, 3024 [GCC_NSSNOC_ATB_ARES] = { 0x17014, 2 }, 3025 [GCC_NSS_TS_ARES] = { 0x17018, 2 }, 3026 [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x1701c, 2 }, 3027 [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17020, 2 }, 3028 [GCC_NSSNOC_MEMNOC_ARES] = { 0x17024, 2 }, 3029 [GCC_NSSNOC_SNOC_ARES] = { 0x17028, 2 }, 3030 [GCC_NSSCFG_ARES] = { 0x1702c, 2 }, 3031 [GCC_NSSNOC_NSSCC_ARES] = { 0x17030, 2 }, 3032 [GCC_NSSCC_ARES] = { 0x17034, 2 }, 3033 [GCC_MDIO_AHB_ARES] = { 0x17040, 2 }, 3034 [GCC_UNIPHY0_SYS_ARES] = { 0x17048, 2 }, 3035 [GCC_UNIPHY0_AHB_ARES] = { 0x1704c, 2 }, 3036 [GCC_UNIPHY1_SYS_ARES] = { 0x17058, 2 }, 3037 [GCC_UNIPHY1_AHB_ARES] = { 0x1705c, 2 }, 3038 [GCC_UNIPHY2_SYS_ARES] = { 0x17068, 2 }, 3039 [GCC_UNIPHY2_AHB_ARES] = { 0x1706c, 2 }, 3040 [GCC_NSSNOC_XO_DCD_ARES] = { 0x17074, 2 }, 3041 [GCC_NSSNOC_SNOC_1_ARES] = { 0x1707c, 2 }, 3042 [GCC_NSSNOC_PCNOC_1_ARES] = { 0x17080, 2 }, 3043 [GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17084, 2 }, 3044 [GCC_DDRSS_ATB_ARES] = { 0x19004, 2 }, 3045 [GCC_DDRSS_AHB_ARES] = { 0x19008, 2 }, 3046 [GCC_GEMNOC_AHB_ARES] = { 0x1900c, 2 }, 3047 [GCC_GEMNOC_Q6_AXI_ARES] = { 0x19010, 2 }, 3048 [GCC_GEMNOC_NSSNOC_ARES] = { 0x19014, 2 }, 3049 [GCC_GEMNOC_SNOC_ARES] = { 0x19018, 2 }, 3050 [GCC_GEMNOC_APSS_ARES] = { 0x1901c, 2 }, 3051 [GCC_GEMNOC_QOSGEN_EXTREF_ARES] = { 0x19024, 2 }, 3052 [GCC_GEMNOC_TS_ARES] = { 0x19028, 2 }, 3053 [GCC_DDRSS_SMS_SLOW_ARES] = { 0x1902c, 2 }, 3054 [GCC_GEMNOC_CNOC_ARES] = { 0x19038, 2 }, 3055 [GCC_GEMNOC_XO_DBG_ARES] = { 0x19040, 2 }, 3056 [GCC_GEMNOC_ANOC_ARES] = { 0x19048, 2 }, 3057 [GCC_DDRSS_LLCC_ATB_ARES] = { 0x1904c, 2 }, 3058 [GCC_LLCC_TPDM_CFG_ARES] = { 0x19050, 2 }, 3059 [GCC_TME_BUS_ARES] = { 0x1a014, 2 }, 3060 [GCC_SEC_CTRL_ACC_ARES] = { 0x1a018, 2 }, 3061 [GCC_SEC_CTRL_ARES] = { 0x1a020, 2 }, 3062 [GCC_SEC_CTRL_SENSE_ARES] = { 0x1a028, 2 }, 3063 [GCC_SEC_CTRL_AHB_ARES] = { 0x1a038, 2 }, 3064 [GCC_SEC_CTRL_BOOT_ROM_PATCH_ARES] = { 0x1a03c, 2 }, 3065 [GCC_ADSS_PWM_ARES] = { 0x1c00c, 2 }, 3066 [GCC_TME_ATB_ARES] = { 0x1e030, 2 }, 3067 [GCC_TME_DBGAPB_ARES] = { 0x1e034, 2 }, 3068 [GCC_TME_DEBUG_ARES] = { 0x1e038, 2 }, 3069 [GCC_TME_AT_ARES] = { 0x1e03C, 2 }, 3070 [GCC_TME_APB_ARES] = { 0x1e040, 2 }, 3071 [GCC_TME_DMI_DBG_HS_ARES] = { 0x1e044, 2 }, 3072 [GCC_APSS_AHB_ARES] = { 0x24014, 2 }, 3073 [GCC_APSS_AXI_ARES] = { 0x24018, 2 }, 3074 [GCC_CPUSS_TRIG_ARES] = { 0x2401c, 2 }, 3075 [GCC_APSS_DBG_ARES] = { 0x2402c, 2 }, 3076 [GCC_APSS_TS_ARES] = { 0x24030, 2 }, 3077 [GCC_APSS_ATB_ARES] = { 0x24034, 2 }, 3078 [GCC_Q6_AXIM_ARES] = { 0x2500c, 2 }, 3079 [GCC_Q6_AXIS_ARES] = { 0x25010, 2 }, 3080 [GCC_Q6_AHB_ARES] = { 0x25014, 2 }, 3081 [GCC_Q6_AHB_S_ARES] = { 0x25018, 2 }, 3082 [GCC_Q6SS_ATBM_ARES] = { 0x2501c, 2 }, 3083 [GCC_Q6_TSCTR_1TO2_ARES] = { 0x25020, 2 }, 3084 [GCC_Q6SS_PCLKDBG_ARES] = { 0x25024, 2 }, 3085 [GCC_Q6SS_TRIG_ARES] = { 0x25028, 2 }, 3086 [GCC_Q6SS_BOOT_CBCR_ARES] = { 0x2502c, 2 }, 3087 [GCC_WCSS_DBG_IFC_APB_ARES] = { 0x25038, 2 }, 3088 [GCC_WCSS_DBG_IFC_ATB_ARES] = { 0x2503c, 2 }, 3089 [GCC_WCSS_DBG_IFC_NTS_ARES] = { 0x25040, 2 }, 3090 [GCC_WCSS_DBG_IFC_DAPBUS_ARES] = { 0x25044, 2 }, 3091 [GCC_WCSS_DBG_IFC_APB_BDG_ARES] = { 0x25048, 2 }, 3092 [GCC_WCSS_DBG_IFC_NTS_BDG_ARES] = { 0x25050, 2 }, 3093 [GCC_WCSS_DBG_IFC_DAPBUS_BDG_ARES] = { 0x25054, 2 }, 3094 [GCC_WCSS_ECAHB_ARES] = { 0x25058, 2 }, 3095 [GCC_WCSS_ACMT_ARES] = { 0x2505c, 2 }, 3096 [GCC_WCSS_AHB_S_ARES] = { 0x25060, 2 }, 3097 [GCC_WCSS_AXI_M_ARES] = { 0x25064, 2 }, 3098 [GCC_PCNOC_WAPSS_ARES] = { 0x25080, 2 }, 3099 [GCC_SNOC_WAPSS_ARES] = { 0x25090, 2 }, 3100 [GCC_LPASS_SWAY_ARES] = { 0x27014, 2 }, 3101 [GCC_LPASS_CORE_AXIM_ARES] = { 0x27018, 2 }, 3102 [GCC_PCIE0_AHB_ARES] = { 0x28030, 2 }, 3103 [GCC_PCIE0_AXI_M_ARES] = { 0x28038, 2 }, 3104 [GCC_PCIE0_AXI_S_ARES] = { 0x28040, 2 }, 3105 [GCC_PCIE0_AXI_S_BRIDGE_ARES] = { 0x28048, 2}, 3106 [GCC_PCIE0_PIPE_ARES] = { 0x28068, 2}, 3107 [GCC_PCIE0_AUX_ARES] = { 0x28070, 2 }, 3108 [GCC_PCIE1_AHB_ARES] = { 0x29030, 2 }, 3109 [GCC_PCIE1_AXI_M_ARES] = { 0x29038, 2 }, 3110 [GCC_PCIE1_AXI_S_ARES] = { 0x29040, 2 }, 3111 [GCC_PCIE1_AXI_S_BRIDGE_ARES] = { 0x29048, 2 }, 3112 [GCC_PCIE1_PIPE_ARES] = { 0x29068, 2 }, 3113 [GCC_PCIE1_AUX_ARES] = { 0x29074, 2 }, 3114 [GCC_PCIE2_AHB_ARES] = { 0x2a030, 2 }, 3115 [GCC_PCIE2_AXI_M_ARES] = { 0x2a038, 2 }, 3116 [GCC_PCIE2_AXI_S_ARES] = { 0x2a040, 2 }, 3117 [GCC_PCIE2_AXI_S_BRIDGE_ARES] = { 0x2a048, 2 }, 3118 [GCC_PCIE2_PIPE_ARES] = { 0x2a068, 2 }, 3119 [GCC_PCIE2_AUX_ARES] = { 0x2a078, 2 }, 3120 [GCC_PCIE3_AHB_ARES] = { 0x2b030, 2 }, 3121 [GCC_PCIE3_AXI_M_ARES] = { 0x2b038, 2 }, 3122 [GCC_PCIE3_AXI_S_ARES] = { 0x2b040, 2 }, 3123 [GCC_PCIE3_AXI_S_BRIDGE_ARES] = { 0x2b048, 2 }, 3124 [GCC_PCIE3_PIPE_ARES] = { 0x2b068, 2 }, 3125 [GCC_PCIE3_AUX_ARES] = { 0x2b07C, 2 }, 3126 [GCC_USB0_MASTER_ARES] = { 0x2c044, 2 }, 3127 [GCC_USB0_AUX_ARES] = { 0x2c04c, 2 }, 3128 [GCC_USB0_MOCK_UTMI_ARES] = { 0x2c050, 2 }, 3129 [GCC_USB0_PIPE_ARES] = { 0x2c054, 2 }, 3130 [GCC_USB0_SLEEP_ARES] = { 0x2c058, 2 }, 3131 [GCC_USB0_PHY_CFG_AHB_ARES] = { 0x2c05c, 2 }, 3132 [GCC_QDSS_AT_ARES] = { 0x2d034, 2 }, 3133 [GCC_QDSS_STM_ARES] = { 0x2d03C, 2 }, 3134 [GCC_QDSS_TRACECLKIN_ARES] = { 0x2d040, 2 }, 3135 [GCC_QDSS_TSCTR_DIV2_ARES] = { 0x2d044, 2 }, 3136 [GCC_QDSS_TSCTR_DIV3_ARES] = { 0x2d048, 2 }, 3137 [GCC_QDSS_TSCTR_DIV4_ARES] = { 0x2d04c, 2 }, 3138 [GCC_QDSS_TSCTR_DIV8_ARES] = { 0x2d050, 2 }, 3139 [GCC_QDSS_TSCTR_DIV16_ARES] = { 0x2d054, 2 }, 3140 [GCC_QDSS_DAP_ARES] = { 0x2d058, 2 }, 3141 [GCC_QDSS_APB2JTAG_ARES] = { 0x2d05c, 2 }, 3142 [GCC_QDSS_ETR_USB_ARES] = { 0x2d060, 2 }, 3143 [GCC_QDSS_DAP_AHB_ARES] = { 0x2d064, 2 }, 3144 [GCC_QDSS_CFG_AHB_ARES] = { 0x2d068, 2 }, 3145 [GCC_QDSS_EUD_AT_ARES] = { 0x2d06c, 2 }, 3146 [GCC_QDSS_TS_ARES] = { 0x2d078, 2 }, 3147 [GCC_QDSS_USB_ARES] = { 0x2d07c, 2 }, 3148 [GCC_SYS_NOC_AXI_ARES] = { 0x2e01c, 2 }, 3149 [GCC_SNOC_QOSGEN_EXTREF_ARES] = { 0x2e020, 2 }, 3150 [GCC_CNOC_LPASS_CFG_ARES] = { 0x2e028, 2 }, 3151 [GCC_SYS_NOC_AT_ARES] = { 0x2e038, 2 }, 3152 [GCC_SNOC_PCNOC_AHB_ARES] = { 0x2e03c, 2 }, 3153 [GCC_SNOC_TME_ARES] = { 0x2e05c, 2 }, 3154 [GCC_SNOC_XO_DCD_ARES] = { 0x2e060, 2 }, 3155 [GCC_SNOC_TS_ARES] = { 0x2e068, 2 }, 3156 [GCC_ANOC0_AXI_ARES] = { 0x2e078, 2 }, 3157 [GCC_ANOC_PCIE0_1LANE_M_ARES] = { 0x2e07c, 2 }, 3158 [GCC_ANOC_PCIE2_2LANE_M_ARES] = { 0x2e080, 2 }, 3159 [GCC_ANOC_PCIE1_1LANE_M_ARES] = { 0x2e084, 2 }, 3160 [GCC_ANOC_PCIE3_2LANE_M_ARES] = { 0x2e090, 2 }, 3161 [GCC_ANOC_PCNOC_AHB_ARES] = { 0x2e094, 2 }, 3162 [GCC_ANOC_QOSGEN_EXTREF_ARES] = { 0x2e098, 2 }, 3163 [GCC_ANOC_XO_DCD_ARES] = { 0x2e09C, 2 }, 3164 [GCC_SNOC_XO_DBG_ARES] = { 0x2e0a0, 2 }, 3165 [GCC_AGGRNOC_ATB_ARES] = { 0x2e0ac, 2 }, 3166 [GCC_AGGRNOC_TS_ARES] = { 0x2e0b0, 2 }, 3167 [GCC_USB0_EUD_AT_ARES] = { 0x30004, 2 }, 3168 [GCC_PCNOC_TIC_ARES] = { 0x31014, 2 }, 3169 [GCC_PCNOC_AHB_ARES] = { 0x31018, 2 }, 3170 [GCC_PCNOC_XO_DBG_ARES] = { 0x3101c, 2 }, 3171 [GCC_SNOC_LPASS_ARES] = { 0x31020, 2 }, 3172 [GCC_PCNOC_AT_ARES] = { 0x31024, 2 }, 3173 [GCC_PCNOC_XO_DCD_ARES] = { 0x31028, 2 }, 3174 [GCC_PCNOC_TS_ARES] = { 0x3102c, 2 }, 3175 [GCC_PCNOC_BUS_TIMEOUT0_AHB_ARES] = { 0x31034, 2 }, 3176 [GCC_PCNOC_BUS_TIMEOUT1_AHB_ARES] = { 0x3103c, 2 }, 3177 [GCC_PCNOC_BUS_TIMEOUT2_AHB_ARES] = { 0x31044, 2 }, 3178 [GCC_PCNOC_BUS_TIMEOUT3_AHB_ARES] = { 0x3104c, 2 }, 3179 [GCC_PCNOC_BUS_TIMEOUT4_AHB_ARES] = { 0x31054, 2 }, 3180 [GCC_PCNOC_BUS_TIMEOUT5_AHB_ARES] = { 0x3105c, 2 }, 3181 [GCC_PCNOC_BUS_TIMEOUT6_AHB_ARES] = { 0x31064, 2 }, 3182 [GCC_PCNOC_BUS_TIMEOUT7_AHB_ARES] = { 0x3106c, 2 }, 3183 [GCC_Q6_AXIM_RESET] = { 0x2506c, 0 }, 3184 [GCC_Q6_AXIS_RESET] = { 0x2506c, 1 }, 3185 [GCC_Q6_AHB_S_RESET] = { 0x2506c, 2 }, 3186 [GCC_Q6_AHB_RESET] = { 0x2506c, 3 }, 3187 [GCC_Q6SS_DBG_RESET] = { 0x2506c, 4 }, 3188 [GCC_WCSS_ECAHB_RESET] = { 0x25070, 0 }, 3189 [GCC_WCSS_DBG_BDG_RESET] = { 0x25070, 1 }, 3190 [GCC_WCSS_DBG_RESET] = { 0x25070, 2 }, 3191 [GCC_WCSS_AXI_M_RESET] = { 0x25070, 3 }, 3192 [GCC_WCSS_AHB_S_RESET] = { 0x25070, 4 }, 3193 [GCC_WCSS_ACMT_RESET] = { 0x25070, 5 }, 3194 [GCC_WCSSAON_RESET] = { 0x25074, 0 }, 3195 [GCC_PCIE0_PIPE_RESET] = { 0x28058, 0 }, 3196 [GCC_PCIE0_CORE_STICKY_RESET] = { 0x28058, 1 }, 3197 [GCC_PCIE0_AXI_S_STICKY_RESET] = { 0x28058, 2 }, 3198 [GCC_PCIE0_AXI_S_RESET] = { 0x28058, 3 }, 3199 [GCC_PCIE0_AXI_M_STICKY_RESET] = { 0x28058, 4 }, 3200 [GCC_PCIE0_AXI_M_RESET] = { 0x28058, 5 }, 3201 [GCC_PCIE0_AUX_RESET] = { 0x28058, 6 }, 3202 [GCC_PCIE0_AHB_RESET] = { 0x28058, 7 }, 3203 [GCC_PCIE1_PIPE_RESET] = { 0x29058, 0 }, 3204 [GCC_PCIE1_CORE_STICKY_RESET] = { 0x29058, 1 }, 3205 [GCC_PCIE1_AXI_S_STICKY_RESET] = { 0x29058, 2 }, 3206 [GCC_PCIE1_AXI_S_RESET] = { 0x29058, 3 }, 3207 [GCC_PCIE1_AXI_M_STICKY_RESET] = { 0x29058, 4 }, 3208 [GCC_PCIE1_AXI_M_RESET] = { 0x29058, 5 }, 3209 [GCC_PCIE1_AUX_RESET] = { 0x29058, 6 }, 3210 [GCC_PCIE1_AHB_RESET] = { 0x29058, 7 }, 3211 [GCC_PCIE2_PIPE_RESET] = { 0x2a058, 0 }, 3212 [GCC_PCIE2_CORE_STICKY_RESET] = { 0x2a058, 1 }, 3213 [GCC_PCIE2_AXI_S_STICKY_RESET] = { 0x2a058, 2 }, 3214 [GCC_PCIE2_AXI_S_RESET] = { 0x2a058, 3 }, 3215 [GCC_PCIE2_AXI_M_STICKY_RESET] = { 0x2a058, 4 }, 3216 [GCC_PCIE2_AXI_M_RESET] = { 0x2a058, 5 }, 3217 [GCC_PCIE2_AUX_RESET] = { 0x2a058, 6 }, 3218 [GCC_PCIE2_AHB_RESET] = { 0x2a058, 7 }, 3219 [GCC_PCIE3_PIPE_RESET] = { 0x2b058, 0 }, 3220 [GCC_PCIE3_CORE_STICKY_RESET] = { 0x2b058, 1 }, 3221 [GCC_PCIE3_AXI_S_STICKY_RESET] = { 0x2b058, 2 }, 3222 [GCC_PCIE3_AXI_S_RESET] = { 0x2b058, 3 }, 3223 [GCC_PCIE3_AXI_M_STICKY_RESET] = { 0x2b058, 4 }, 3224 [GCC_PCIE3_AXI_M_RESET] = { 0x2b058, 5 }, 3225 [GCC_PCIE3_AUX_RESET] = { 0x2b058, 6 }, 3226 [GCC_PCIE3_AHB_RESET] = { 0x2b058, 7 }, 3227 [GCC_NSS_PARTIAL_RESET] = { 0x17078, 0 }, 3228 [GCC_UNIPHY0_XPCS_ARES] = { 0x17050, 2 }, 3229 [GCC_UNIPHY1_XPCS_ARES] = { 0x17060, 2 }, 3230 [GCC_UNIPHY2_XPCS_ARES] = { 0x17070, 2 }, 3231 [GCC_USB1_BCR] = { 0x3C000, 0 }, 3232 [GCC_QUSB2_1_PHY_BCR] = { 0x3C030, 0 }, 3233 }; 3234 3235 #define IPQ_APPS_ID 5424 /* some unique value */ 3236 3237 static const struct qcom_icc_hws_data icc_ipq5424_hws[] = { 3238 { MASTER_ANOC_PCIE0, SLAVE_ANOC_PCIE0, GCC_ANOC_PCIE0_1LANE_M_CLK }, 3239 { MASTER_CNOC_PCIE0, SLAVE_CNOC_PCIE0, GCC_CNOC_PCIE0_1LANE_S_CLK }, 3240 { MASTER_ANOC_PCIE1, SLAVE_ANOC_PCIE1, GCC_ANOC_PCIE1_1LANE_M_CLK }, 3241 { MASTER_CNOC_PCIE1, SLAVE_CNOC_PCIE1, GCC_CNOC_PCIE1_1LANE_S_CLK }, 3242 { MASTER_ANOC_PCIE2, SLAVE_ANOC_PCIE2, GCC_ANOC_PCIE2_2LANE_M_CLK }, 3243 { MASTER_CNOC_PCIE2, SLAVE_CNOC_PCIE2, GCC_CNOC_PCIE2_2LANE_S_CLK }, 3244 { MASTER_ANOC_PCIE3, SLAVE_ANOC_PCIE3, GCC_ANOC_PCIE3_2LANE_M_CLK }, 3245 { MASTER_CNOC_PCIE3, SLAVE_CNOC_PCIE3, GCC_CNOC_PCIE3_2LANE_S_CLK }, 3246 { MASTER_CNOC_USB, SLAVE_CNOC_USB, GCC_CNOC_USB_CLK }, 3247 }; 3248 3249 static const struct of_device_id gcc_ipq5424_match_table[] = { 3250 { .compatible = "qcom,ipq5424-gcc" }, 3251 { } 3252 }; 3253 MODULE_DEVICE_TABLE(of, gcc_ipq5424_match_table); 3254 3255 static const struct regmap_config gcc_ipq5424_regmap_config = { 3256 .reg_bits = 32, 3257 .reg_stride = 4, 3258 .val_bits = 32, 3259 .max_register = 0x3f024, 3260 .fast_io = true, 3261 }; 3262 3263 static struct clk_hw *gcc_ipq5424_hws[] = { 3264 &gpll0_div2.hw, 3265 &gcc_xo_div4_clk_src.hw, 3266 &gcc_qdss_tsctr_div2_clk_src.hw, 3267 &gcc_qdss_dap_sync_clk_src.hw, 3268 &gcc_eud_at_div_clk_src.hw, 3269 }; 3270 3271 static const struct qcom_cc_desc gcc_ipq5424_desc = { 3272 .config = &gcc_ipq5424_regmap_config, 3273 .clks = gcc_ipq5424_clocks, 3274 .num_clks = ARRAY_SIZE(gcc_ipq5424_clocks), 3275 .resets = gcc_ipq5424_resets, 3276 .num_resets = ARRAY_SIZE(gcc_ipq5424_resets), 3277 .clk_hws = gcc_ipq5424_hws, 3278 .num_clk_hws = ARRAY_SIZE(gcc_ipq5424_hws), 3279 .icc_hws = icc_ipq5424_hws, 3280 .num_icc_hws = ARRAY_SIZE(icc_ipq5424_hws), 3281 }; 3282 3283 static int gcc_ipq5424_probe(struct platform_device *pdev) 3284 { 3285 return qcom_cc_probe(pdev, &gcc_ipq5424_desc); 3286 } 3287 3288 static struct platform_driver gcc_ipq5424_driver = { 3289 .probe = gcc_ipq5424_probe, 3290 .driver = { 3291 .name = "qcom,gcc-ipq5424", 3292 .of_match_table = gcc_ipq5424_match_table, 3293 .sync_state = icc_sync_state, 3294 }, 3295 }; 3296 3297 static int __init gcc_ipq5424_init(void) 3298 { 3299 return platform_driver_register(&gcc_ipq5424_driver); 3300 } 3301 core_initcall(gcc_ipq5424_init); 3302 3303 static void __exit gcc_ipq5424_exit(void) 3304 { 3305 platform_driver_unregister(&gcc_ipq5424_driver); 3306 } 3307 module_exit(gcc_ipq5424_exit); 3308 3309 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ5424 Driver"); 3310 MODULE_LICENSE("GPL"); 3311