1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018,2020 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/interconnect-provider.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 15 #include <dt-bindings/clock/qcom,ipq5424-gcc.h> 16 #include <dt-bindings/interconnect/qcom,ipq5424.h> 17 #include <dt-bindings/reset/qcom,ipq5424-gcc.h> 18 19 #include "clk-alpha-pll.h" 20 #include "clk-branch.h" 21 #include "clk-rcg.h" 22 #include "clk-regmap.h" 23 #include "clk-regmap-divider.h" 24 #include "clk-regmap-mux.h" 25 #include "clk-regmap-phy-mux.h" 26 #include "common.h" 27 #include "reset.h" 28 29 enum { 30 DT_XO, 31 DT_SLEEP_CLK, 32 DT_PCIE30_PHY0_PIPE_CLK, 33 DT_PCIE30_PHY1_PIPE_CLK, 34 DT_PCIE30_PHY2_PIPE_CLK, 35 DT_PCIE30_PHY3_PIPE_CLK, 36 DT_USB_PCIE_WRAPPER_PIPE_CLK, 37 }; 38 39 enum { 40 P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 41 P_GPLL0_OUT_AUX, 42 P_GPLL0_OUT_MAIN, 43 P_GPLL2_OUT_AUX, 44 P_GPLL2_OUT_MAIN, 45 P_GPLL4_OUT_AUX, 46 P_GPLL4_OUT_MAIN, 47 P_SLEEP_CLK, 48 P_XO, 49 P_USB3PHY_0_PIPE, 50 }; 51 52 static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO }; 53 54 static struct clk_alpha_pll gpll0 = { 55 .offset = 0x20000, 56 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 57 .clkr = { 58 .enable_reg = 0xb000, 59 .enable_mask = BIT(0), 60 .hw.init = &(const struct clk_init_data) { 61 .name = "gpll0", 62 .parent_data = &gcc_parent_data_xo, 63 .num_parents = 1, 64 .ops = &clk_alpha_pll_ops, 65 }, 66 }, 67 }; 68 69 static struct clk_fixed_factor gpll0_div2 = { 70 .mult = 1, 71 .div = 2, 72 .hw.init = &(const struct clk_init_data) { 73 .name = "gpll0_div2", 74 .parent_hws = (const struct clk_hw *[]) { 75 &gpll0.clkr.hw 76 }, 77 .num_parents = 1, 78 .ops = &clk_fixed_factor_ops, 79 }, 80 }; 81 82 static struct clk_alpha_pll gpll2 = { 83 .offset = 0x21000, 84 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA], 85 .clkr = { 86 .enable_reg = 0xb000, 87 .enable_mask = BIT(1), 88 .hw.init = &(const struct clk_init_data) { 89 .name = "gpll2", 90 .parent_data = &gcc_parent_data_xo, 91 .num_parents = 1, 92 .ops = &clk_alpha_pll_ops, 93 }, 94 }, 95 }; 96 97 static const struct clk_div_table post_div_table_gpll2_out_main[] = { 98 { 0x1, 2 }, 99 { } 100 }; 101 102 static struct clk_alpha_pll_postdiv gpll2_out_main = { 103 .offset = 0x21000, 104 .post_div_table = post_div_table_gpll2_out_main, 105 .num_post_div = ARRAY_SIZE(post_div_table_gpll2_out_main), 106 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA], 107 .clkr.hw.init = &(const struct clk_init_data) { 108 .name = "gpll2_out_main", 109 .parent_hws = (const struct clk_hw*[]) { 110 &gpll2.clkr.hw, 111 }, 112 .num_parents = 1, 113 .ops = &clk_alpha_pll_postdiv_ro_ops, 114 }, 115 }; 116 117 static struct clk_alpha_pll gpll4 = { 118 .offset = 0x22000, 119 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 120 .clkr = { 121 .enable_reg = 0xb000, 122 .enable_mask = BIT(2), 123 .hw.init = &(const struct clk_init_data) { 124 .name = "gpll4", 125 .parent_data = &gcc_parent_data_xo, 126 .num_parents = 1, 127 .ops = &clk_alpha_pll_ops, 128 /* 129 * There are no consumers for this GPLL in kernel yet, 130 * (will be added soon), so the clock framework 131 * disables this source. But some of the clocks 132 * initialized by boot loaders uses this source. So we 133 * need to keep this clock ON. Add the 134 * CLK_IGNORE_UNUSED flag so the clock will not be 135 * disabled. Once the consumer in kernel is added, we 136 * can get rid of this flag. 137 */ 138 .flags = CLK_IGNORE_UNUSED, 139 }, 140 }, 141 }; 142 143 static const struct parent_map gcc_parent_map_xo[] = { 144 { P_XO, 0 }, 145 }; 146 147 static const struct parent_map gcc_parent_map_0[] = { 148 { P_XO, 0 }, 149 { P_GPLL0_OUT_MAIN, 1 }, 150 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 151 }; 152 153 static const struct clk_parent_data gcc_parent_data_0[] = { 154 { .index = DT_XO }, 155 { .hw = &gpll0.clkr.hw }, 156 { .hw = &gpll0_div2.hw }, 157 }; 158 159 static const struct parent_map gcc_parent_map_1[] = { 160 { P_XO, 0 }, 161 { P_GPLL0_OUT_MAIN, 1 }, 162 }; 163 164 static const struct clk_parent_data gcc_parent_data_1[] = { 165 { .index = DT_XO }, 166 { .hw = &gpll0.clkr.hw }, 167 }; 168 169 static const struct parent_map gcc_parent_map_2[] = { 170 { P_XO, 0 }, 171 { P_GPLL0_OUT_MAIN, 1 }, 172 { P_GPLL4_OUT_MAIN, 2 }, 173 }; 174 175 static const struct clk_parent_data gcc_parent_data_2[] = { 176 { .index = DT_XO }, 177 { .hw = &gpll0.clkr.hw }, 178 { .hw = &gpll4.clkr.hw }, 179 }; 180 181 static const struct parent_map gcc_parent_map_3[] = { 182 { P_XO, 0 }, 183 { P_GPLL4_OUT_MAIN, 1 }, 184 { P_GPLL0_OUT_AUX, 2 }, 185 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 186 }; 187 188 static const struct clk_parent_data gcc_parent_data_3[] = { 189 { .index = DT_XO }, 190 { .hw = &gpll4.clkr.hw }, 191 { .hw = &gpll0.clkr.hw }, 192 { .hw = &gpll0_div2.hw }, 193 }; 194 195 static const struct parent_map gcc_parent_map_4[] = { 196 { P_XO, 0 }, 197 }; 198 199 static const struct clk_parent_data gcc_parent_data_4[] = { 200 { .index = DT_XO }, 201 }; 202 203 static const struct parent_map gcc_parent_map_5[] = { 204 { P_XO, 0 }, 205 { P_GPLL4_OUT_AUX, 1 }, 206 { P_GPLL0_OUT_MAIN, 3 }, 207 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 208 }; 209 210 static const struct clk_parent_data gcc_parent_data_5[] = { 211 { .index = DT_XO }, 212 { .hw = &gpll4.clkr.hw }, 213 { .hw = &gpll0.clkr.hw }, 214 { .hw = &gpll0_div2.hw }, 215 }; 216 217 static const struct parent_map gcc_parent_map_6[] = { 218 { P_SLEEP_CLK, 6 }, 219 }; 220 221 static const struct clk_parent_data gcc_parent_data_6[] = { 222 { .index = DT_SLEEP_CLK }, 223 }; 224 225 static const struct parent_map gcc_parent_map_7[] = { 226 { P_XO, 0 }, 227 { P_GPLL0_OUT_MAIN, 1 }, 228 { P_GPLL0_OUT_AUX, 2 }, 229 { P_SLEEP_CLK, 6 }, 230 }; 231 232 static const struct clk_parent_data gcc_parent_data_7[] = { 233 { .index = DT_XO }, 234 { .hw = &gpll0.clkr.hw }, 235 { .hw = &gpll0.clkr.hw }, 236 { .index = DT_SLEEP_CLK }, 237 }; 238 239 static const struct parent_map gcc_parent_map_8[] = { 240 { P_XO, 0 }, 241 { P_GPLL0_OUT_MAIN, 1 }, 242 { P_GPLL2_OUT_MAIN, 2 }, 243 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 244 }; 245 246 static const struct clk_parent_data gcc_parent_data_8[] = { 247 { .index = DT_XO }, 248 { .hw = &gpll0.clkr.hw }, 249 { .hw = &gpll2_out_main.clkr.hw }, 250 { .hw = &gpll0_div2.hw }, 251 }; 252 253 static const struct parent_map gcc_parent_map_9[] = { 254 { P_XO, 0 }, 255 { P_GPLL0_OUT_MAIN, 1 }, 256 { P_GPLL4_OUT_MAIN, 2 }, 257 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 258 }; 259 260 static const struct clk_parent_data gcc_parent_data_9[] = { 261 { .index = DT_XO }, 262 { .hw = &gpll0.clkr.hw }, 263 { .hw = &gpll4.clkr.hw }, 264 { .hw = &gpll0_div2.hw }, 265 }; 266 267 static const struct parent_map gcc_parent_map_10[] = { 268 { P_XO, 0 }, 269 { P_GPLL0_OUT_AUX, 2 }, 270 { P_SLEEP_CLK, 6 }, 271 }; 272 273 static const struct clk_parent_data gcc_parent_data_10[] = { 274 { .index = DT_XO }, 275 { .hw = &gpll0.clkr.hw }, 276 { .index = DT_SLEEP_CLK }, 277 }; 278 279 static const struct parent_map gcc_parent_map_11[] = { 280 { P_XO, 0 }, 281 { P_GPLL0_OUT_MAIN, 1 }, 282 { P_GPLL2_OUT_AUX, 2 }, 283 }; 284 285 static const struct clk_parent_data gcc_parent_data_11[] = { 286 { .index = DT_XO }, 287 { .hw = &gpll0.clkr.hw }, 288 { .hw = &gpll2.clkr.hw }, 289 }; 290 291 static const struct freq_tbl ftbl_gcc_adss_pwm_clk_src[] = { 292 F(24000000, P_XO, 1, 0, 0), 293 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 294 { } 295 }; 296 297 static struct clk_rcg2 gcc_adss_pwm_clk_src = { 298 .cmd_rcgr = 0x1c004, 299 .mnd_width = 0, 300 .hid_width = 5, 301 .parent_map = gcc_parent_map_1, 302 .freq_tbl = ftbl_gcc_adss_pwm_clk_src, 303 .clkr.hw.init = &(const struct clk_init_data) { 304 .name = "gcc_adss_pwm_clk_src", 305 .parent_data = gcc_parent_data_1, 306 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 307 .ops = &clk_rcg2_ops, 308 }, 309 }; 310 311 static const struct freq_tbl ftbl_gcc_nss_ts_clk_src[] = { 312 F(24000000, P_XO, 1, 0, 0), 313 { } 314 }; 315 316 static struct clk_rcg2 gcc_xo_clk_src = { 317 .cmd_rcgr = 0x34004, 318 .mnd_width = 0, 319 .hid_width = 5, 320 .parent_map = gcc_parent_map_xo, 321 .freq_tbl = ftbl_gcc_nss_ts_clk_src, 322 .clkr.hw.init = &(const struct clk_init_data) { 323 .name = "gcc_xo_clk_src", 324 .parent_data = &gcc_parent_data_xo, 325 .num_parents = 1, 326 .ops = &clk_rcg2_ops, 327 }, 328 }; 329 330 static struct clk_branch gcc_xo_clk = { 331 .halt_reg = 0x34018, 332 .halt_check = BRANCH_HALT, 333 .clkr = { 334 .enable_reg = 0x34018, 335 .enable_mask = BIT(0), 336 .hw.init = &(const struct clk_init_data) { 337 .name = "gcc_xo_clk", 338 .parent_hws = (const struct clk_hw*[]) { 339 &gcc_xo_clk_src.clkr.hw, 340 }, 341 .num_parents = 1, 342 .flags = CLK_SET_RATE_PARENT, 343 .ops = &clk_branch2_ops, 344 }, 345 }, 346 }; 347 348 static struct clk_fixed_factor gcc_xo_div4_clk_src = { 349 .mult = 1, 350 .div = 4, 351 .hw.init = &(const struct clk_init_data) { 352 .name = "gcc_xo_div4_clk_src", 353 .parent_hws = (const struct clk_hw *[]) { 354 &gcc_xo_clk_src.clkr.hw 355 }, 356 .num_parents = 1, 357 .flags = CLK_SET_RATE_PARENT, 358 .ops = &clk_fixed_factor_ops, 359 }, 360 }; 361 362 static struct clk_rcg2 gcc_nss_ts_clk_src = { 363 .cmd_rcgr = 0x17088, 364 .mnd_width = 0, 365 .hid_width = 5, 366 .parent_map = gcc_parent_map_4, 367 .freq_tbl = ftbl_gcc_nss_ts_clk_src, 368 .clkr.hw.init = &(const struct clk_init_data) { 369 .name = "gcc_nss_ts_clk_src", 370 .parent_data = gcc_parent_data_4, 371 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 372 .ops = &clk_rcg2_ops, 373 }, 374 }; 375 376 static const struct freq_tbl ftbl_gcc_pcie0_axi_m_clk_src[] = { 377 F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0), 378 { } 379 }; 380 381 static struct clk_rcg2 gcc_pcie0_axi_m_clk_src = { 382 .cmd_rcgr = 0x28018, 383 .mnd_width = 0, 384 .hid_width = 5, 385 .parent_map = gcc_parent_map_2, 386 .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src, 387 .clkr.hw.init = &(const struct clk_init_data) { 388 .name = "gcc_pcie0_axi_m_clk_src", 389 .parent_data = gcc_parent_data_2, 390 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 391 .ops = &clk_rcg2_ops, 392 }, 393 }; 394 395 static struct clk_rcg2 gcc_pcie0_axi_s_clk_src = { 396 .cmd_rcgr = 0x28020, 397 .mnd_width = 0, 398 .hid_width = 5, 399 .parent_map = gcc_parent_map_2, 400 .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src, 401 .clkr.hw.init = &(const struct clk_init_data) { 402 .name = "gcc_pcie0_axi_s_clk_src", 403 .parent_data = gcc_parent_data_2, 404 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 405 .ops = &clk_rcg2_ops, 406 }, 407 }; 408 409 static struct clk_rcg2 gcc_pcie1_axi_m_clk_src = { 410 .cmd_rcgr = 0x29018, 411 .mnd_width = 0, 412 .hid_width = 5, 413 .parent_map = gcc_parent_map_2, 414 .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src, 415 .clkr.hw.init = &(const struct clk_init_data) { 416 .name = "gcc_pcie1_axi_m_clk_src", 417 .parent_data = gcc_parent_data_2, 418 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 419 .ops = &clk_rcg2_ops, 420 }, 421 }; 422 423 static struct clk_rcg2 gcc_pcie1_axi_s_clk_src = { 424 .cmd_rcgr = 0x29020, 425 .mnd_width = 0, 426 .hid_width = 5, 427 .parent_map = gcc_parent_map_2, 428 .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src, 429 .clkr.hw.init = &(const struct clk_init_data) { 430 .name = "gcc_pcie1_axi_s_clk_src", 431 .parent_data = gcc_parent_data_2, 432 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 433 .ops = &clk_rcg2_ops, 434 }, 435 }; 436 437 static const struct freq_tbl ftbl_gcc_pcie2_axi_m_clk_src[] = { 438 F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0), 439 { } 440 }; 441 442 static struct clk_rcg2 gcc_pcie2_axi_m_clk_src = { 443 .cmd_rcgr = 0x2a018, 444 .mnd_width = 0, 445 .hid_width = 5, 446 .parent_map = gcc_parent_map_2, 447 .freq_tbl = ftbl_gcc_pcie2_axi_m_clk_src, 448 .clkr.hw.init = &(const struct clk_init_data) { 449 .name = "gcc_pcie2_axi_m_clk_src", 450 .parent_data = gcc_parent_data_2, 451 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 452 .ops = &clk_rcg2_ops, 453 }, 454 }; 455 456 static struct clk_rcg2 gcc_pcie2_axi_s_clk_src = { 457 .cmd_rcgr = 0x2a020, 458 .mnd_width = 0, 459 .hid_width = 5, 460 .parent_map = gcc_parent_map_2, 461 .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src, 462 .clkr.hw.init = &(const struct clk_init_data) { 463 .name = "gcc_pcie2_axi_s_clk_src", 464 .parent_data = gcc_parent_data_2, 465 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 466 .ops = &clk_rcg2_ops, 467 }, 468 }; 469 470 static struct clk_rcg2 gcc_pcie3_axi_m_clk_src = { 471 .cmd_rcgr = 0x2b018, 472 .mnd_width = 0, 473 .hid_width = 5, 474 .parent_map = gcc_parent_map_2, 475 .freq_tbl = ftbl_gcc_pcie2_axi_m_clk_src, 476 .clkr.hw.init = &(const struct clk_init_data) { 477 .name = "gcc_pcie3_axi_m_clk_src", 478 .parent_data = gcc_parent_data_2, 479 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 480 .ops = &clk_rcg2_ops, 481 }, 482 }; 483 484 static struct clk_rcg2 gcc_pcie3_axi_s_clk_src = { 485 .cmd_rcgr = 0x2b020, 486 .mnd_width = 0, 487 .hid_width = 5, 488 .parent_map = gcc_parent_map_2, 489 .freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src, 490 .clkr.hw.init = &(const struct clk_init_data) { 491 .name = "gcc_pcie3_axi_s_clk_src", 492 .parent_data = gcc_parent_data_2, 493 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 494 .ops = &clk_rcg2_ops, 495 }, 496 }; 497 498 static const struct freq_tbl ftbl_gcc_pcie_aux_clk_src[] = { 499 F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4), 500 { } 501 }; 502 503 static struct clk_rcg2 gcc_pcie_aux_clk_src = { 504 .cmd_rcgr = 0x28004, 505 .mnd_width = 16, 506 .hid_width = 5, 507 .parent_map = gcc_parent_map_7, 508 .freq_tbl = ftbl_gcc_pcie_aux_clk_src, 509 .clkr.hw.init = &(const struct clk_init_data) { 510 .name = "gcc_pcie_aux_clk_src", 511 .parent_data = gcc_parent_data_7, 512 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 513 .ops = &clk_rcg2_ops, 514 }, 515 }; 516 517 static const struct freq_tbl ftbl_gcc_qupv3_i2c0_clk_src[] = { 518 F(4800000, P_XO, 5, 0, 0), 519 F(9600000, P_XO, 2.5, 0, 0), 520 F(24000000, P_XO, 1, 0, 0), 521 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), 522 F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), 523 { } 524 }; 525 526 static struct clk_rcg2 gcc_qupv3_i2c0_clk_src = { 527 .cmd_rcgr = 0x2018, 528 .mnd_width = 0, 529 .hid_width = 5, 530 .parent_map = gcc_parent_map_0, 531 .freq_tbl = ftbl_gcc_qupv3_i2c0_clk_src, 532 .clkr.hw.init = &(const struct clk_init_data) { 533 .name = "gcc_qupv3_i2c0_clk_src", 534 .parent_data = gcc_parent_data_0, 535 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 536 .ops = &clk_rcg2_ops, 537 }, 538 }; 539 540 static struct clk_rcg2 gcc_qupv3_i2c1_clk_src = { 541 .cmd_rcgr = 0x3018, 542 .mnd_width = 0, 543 .hid_width = 5, 544 .parent_map = gcc_parent_map_0, 545 .freq_tbl = ftbl_gcc_qupv3_i2c0_clk_src, 546 .clkr.hw.init = &(const struct clk_init_data) { 547 .name = "gcc_qupv3_i2c1_clk_src", 548 .parent_data = gcc_parent_data_0, 549 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 550 .ops = &clk_rcg2_ops, 551 }, 552 }; 553 554 static const struct freq_tbl ftbl_gcc_qupv3_spi0_clk_src[] = { 555 F(960000, P_XO, 10, 2, 5), 556 F(4800000, P_XO, 5, 0, 0), 557 F(9600000, P_XO, 2, 4, 5), 558 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5), 559 F(24000000, P_XO, 1, 0, 0), 560 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2), 561 F(32000000, P_GPLL0_OUT_MAIN, 10, 2, 5), 562 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), 563 { } 564 }; 565 566 static struct clk_rcg2 gcc_qupv3_spi0_clk_src = { 567 .cmd_rcgr = 0x4004, 568 .mnd_width = 8, 569 .hid_width = 5, 570 .parent_map = gcc_parent_map_0, 571 .freq_tbl = ftbl_gcc_qupv3_spi0_clk_src, 572 .clkr.hw.init = &(const struct clk_init_data) { 573 .name = "gcc_qupv3_spi0_clk_src", 574 .parent_data = gcc_parent_data_0, 575 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 576 .ops = &clk_rcg2_ops, 577 }, 578 }; 579 580 static struct clk_rcg2 gcc_qupv3_spi1_clk_src = { 581 .cmd_rcgr = 0x5004, 582 .mnd_width = 8, 583 .hid_width = 5, 584 .parent_map = gcc_parent_map_0, 585 .freq_tbl = ftbl_gcc_qupv3_spi0_clk_src, 586 .clkr.hw.init = &(const struct clk_init_data) { 587 .name = "gcc_qupv3_spi1_clk_src", 588 .parent_data = gcc_parent_data_0, 589 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 590 .ops = &clk_rcg2_ops, 591 }, 592 }; 593 594 static const struct freq_tbl ftbl_gcc_qupv3_uart0_clk_src[] = { 595 F(3686400, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 144, 15625), 596 F(7372800, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 288, 15625), 597 F(14745600, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 576, 15625), 598 F(24000000, P_XO, 1, 0, 0), 599 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2), 600 F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25), 601 F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20), 602 F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500), 603 F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50), 604 F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125), 605 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100), 606 F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625), 607 F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40), 608 F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), 609 { } 610 }; 611 612 static struct clk_rcg2 gcc_qupv3_uart0_clk_src = { 613 .cmd_rcgr = 0x202c, 614 .mnd_width = 16, 615 .hid_width = 5, 616 .parent_map = gcc_parent_map_0, 617 .freq_tbl = ftbl_gcc_qupv3_uart0_clk_src, 618 .clkr.hw.init = &(const struct clk_init_data) { 619 .name = "gcc_qupv3_uart0_clk_src", 620 .parent_data = gcc_parent_data_0, 621 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 622 .ops = &clk_rcg2_ops, 623 }, 624 }; 625 626 static struct clk_rcg2 gcc_qupv3_uart1_clk_src = { 627 .cmd_rcgr = 0x302c, 628 .mnd_width = 16, 629 .hid_width = 5, 630 .parent_map = gcc_parent_map_0, 631 .freq_tbl = ftbl_gcc_qupv3_uart0_clk_src, 632 .clkr.hw.init = &(const struct clk_init_data) { 633 .name = "gcc_qupv3_uart1_clk_src", 634 .parent_data = gcc_parent_data_0, 635 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 636 .ops = &clk_rcg2_ops, 637 }, 638 }; 639 640 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 641 F(144000, P_XO, 16, 12, 125), 642 F(400000, P_XO, 12, 1, 5), 643 F(24000000, P_GPLL2_OUT_MAIN, 12, 1, 2), 644 F(48000000, P_GPLL2_OUT_MAIN, 12, 0, 0), 645 F(96000000, P_GPLL2_OUT_MAIN, 6, 0, 0), 646 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 647 F(192000000, P_GPLL2_OUT_MAIN, 3, 0, 0), 648 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 649 { } 650 }; 651 652 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 653 .cmd_rcgr = 0x33004, 654 .mnd_width = 8, 655 .hid_width = 5, 656 .parent_map = gcc_parent_map_8, 657 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 658 .clkr.hw.init = &(const struct clk_init_data) { 659 .name = "gcc_sdcc1_apps_clk_src", 660 .parent_data = gcc_parent_data_8, 661 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 662 .ops = &clk_rcg2_floor_ops, 663 }, 664 }; 665 666 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 667 F(300000000, P_GPLL4_OUT_MAIN, 4, 0, 0), 668 { } 669 }; 670 671 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 672 .cmd_rcgr = 0x33018, 673 .mnd_width = 8, 674 .hid_width = 5, 675 .parent_map = gcc_parent_map_9, 676 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 677 .clkr.hw.init = &(const struct clk_init_data) { 678 .name = "gcc_sdcc1_ice_core_clk_src", 679 .parent_data = gcc_parent_data_9, 680 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 681 .ops = &clk_rcg2_ops, 682 }, 683 }; 684 685 static struct clk_rcg2 gcc_uniphy_sys_clk_src = { 686 .cmd_rcgr = 0x17090, 687 .mnd_width = 0, 688 .hid_width = 5, 689 .parent_map = gcc_parent_map_4, 690 .freq_tbl = ftbl_gcc_nss_ts_clk_src, 691 .clkr.hw.init = &(const struct clk_init_data) { 692 .name = "gcc_uniphy_sys_clk_src", 693 .parent_data = &gcc_parent_data_xo, 694 .num_parents = 1, 695 .ops = &clk_rcg2_ops, 696 }, 697 }; 698 699 static struct clk_rcg2 gcc_usb0_aux_clk_src = { 700 .cmd_rcgr = 0x2c018, 701 .mnd_width = 16, 702 .hid_width = 5, 703 .parent_map = gcc_parent_map_10, 704 .freq_tbl = ftbl_gcc_nss_ts_clk_src, 705 .clkr.hw.init = &(const struct clk_init_data) { 706 .name = "gcc_usb0_aux_clk_src", 707 .parent_data = gcc_parent_data_10, 708 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 709 .ops = &clk_rcg2_ops, 710 }, 711 }; 712 713 static const struct freq_tbl ftbl_gcc_usb0_master_clk_src[] = { 714 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 715 { } 716 }; 717 718 static struct clk_rcg2 gcc_usb0_master_clk_src = { 719 .cmd_rcgr = 0x2c004, 720 .mnd_width = 8, 721 .hid_width = 5, 722 .parent_map = gcc_parent_map_0, 723 .freq_tbl = ftbl_gcc_usb0_master_clk_src, 724 .clkr.hw.init = &(const struct clk_init_data) { 725 .name = "gcc_usb0_master_clk_src", 726 .parent_data = gcc_parent_data_0, 727 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 728 .ops = &clk_rcg2_ops, 729 }, 730 }; 731 732 static const struct freq_tbl ftbl_gcc_usb0_mock_utmi_clk_src[] = { 733 F(24000000, P_XO, 1, 0, 0), 734 F(60000000, P_GPLL4_OUT_AUX, 10, 1, 2), 735 { } 736 }; 737 738 static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = { 739 .cmd_rcgr = 0x2c02c, 740 .mnd_width = 8, 741 .hid_width = 5, 742 .parent_map = gcc_parent_map_5, 743 .freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src, 744 .clkr.hw.init = &(const struct clk_init_data) { 745 .name = "gcc_usb0_mock_utmi_clk_src", 746 .parent_data = gcc_parent_data_5, 747 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 748 .ops = &clk_rcg2_ops, 749 }, 750 }; 751 752 static struct clk_rcg2 gcc_usb1_mock_utmi_clk_src = { 753 .cmd_rcgr = 0x3c004, 754 .mnd_width = 8, 755 .hid_width = 5, 756 .parent_map = gcc_parent_map_5, 757 .freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src, 758 .clkr.hw.init = &(const struct clk_init_data) { 759 .name = "gcc_usb1_mock_utmi_clk_src", 760 .parent_data = gcc_parent_data_5, 761 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 762 .ops = &clk_rcg2_ops, 763 }, 764 }; 765 766 static const struct freq_tbl ftbl_gcc_wcss_ahb_clk_src[] = { 767 F(24000000, P_XO, 1, 0, 0), 768 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0), 769 { } 770 }; 771 772 static struct clk_rcg2 gcc_wcss_ahb_clk_src = { 773 .cmd_rcgr = 0x25030, 774 .freq_tbl = ftbl_gcc_wcss_ahb_clk_src, 775 .hid_width = 5, 776 .parent_map = gcc_parent_map_1, 777 .clkr.hw.init = &(const struct clk_init_data) { 778 .name = "gcc_wcss_ahb_clk_src", 779 .parent_data = gcc_parent_data_1, 780 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 781 .ops = &clk_rcg2_ops, 782 }, 783 }; 784 785 static const struct freq_tbl ftbl_gcc_qdss_at_clk_src[] = { 786 F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0), 787 { } 788 }; 789 790 static struct clk_rcg2 gcc_qdss_at_clk_src = { 791 .cmd_rcgr = 0x2d004, 792 .freq_tbl = ftbl_gcc_qdss_at_clk_src, 793 .hid_width = 5, 794 .parent_map = gcc_parent_map_3, 795 .clkr.hw.init = &(const struct clk_init_data) { 796 .name = "gcc_qdss_at_clk_src", 797 .parent_data = gcc_parent_data_3, 798 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 799 .ops = &clk_rcg2_ops, 800 }, 801 }; 802 803 static const struct freq_tbl ftbl_gcc_qdss_tsctr_clk_src[] = { 804 F(600000000, P_GPLL4_OUT_MAIN, 2, 0, 0), 805 { } 806 }; 807 808 static struct clk_rcg2 gcc_qdss_tsctr_clk_src = { 809 .cmd_rcgr = 0x2d01c, 810 .freq_tbl = ftbl_gcc_qdss_tsctr_clk_src, 811 .hid_width = 5, 812 .parent_map = gcc_parent_map_3, 813 .clkr.hw.init = &(const struct clk_init_data) { 814 .name = "gcc_qdss_tsctr_clk_src", 815 .parent_data = gcc_parent_data_3, 816 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 817 .ops = &clk_rcg2_ops, 818 }, 819 }; 820 821 static struct clk_fixed_factor gcc_qdss_tsctr_div2_clk_src = { 822 .mult = 1, 823 .div = 2, 824 .hw.init = &(const struct clk_init_data) { 825 .name = "gcc_qdss_tsctr_div2_clk_src", 826 .parent_hws = (const struct clk_hw *[]) { 827 &gcc_qdss_tsctr_clk_src.clkr.hw 828 }, 829 .num_parents = 1, 830 .flags = CLK_SET_RATE_PARENT, 831 .ops = &clk_fixed_factor_ops, 832 }, 833 }; 834 835 static struct clk_fixed_factor gcc_qdss_dap_sync_clk_src = { 836 .mult = 1, 837 .div = 4, 838 .hw.init = &(const struct clk_init_data) { 839 .name = "gcc_qdss_dap_sync_clk_src", 840 .parent_hws = (const struct clk_hw *[]) { 841 &gcc_qdss_tsctr_clk_src.clkr.hw 842 }, 843 .num_parents = 1, 844 .ops = &clk_fixed_factor_ops, 845 }, 846 }; 847 848 static const struct freq_tbl ftbl_gcc_system_noc_bfdcd_clk_src[] = { 849 F(24000000, P_XO, 1, 0, 0), 850 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0), 851 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 852 F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0), 853 { } 854 }; 855 856 static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src = { 857 .cmd_rcgr = 0x2e004, 858 .freq_tbl = ftbl_gcc_system_noc_bfdcd_clk_src, 859 .hid_width = 5, 860 .parent_map = gcc_parent_map_9, 861 .clkr.hw.init = &(const struct clk_init_data) { 862 .name = "gcc_system_noc_bfdcd_clk_src", 863 .parent_data = gcc_parent_data_9, 864 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 865 .ops = &clk_rcg2_ops, 866 }, 867 }; 868 869 static const struct freq_tbl ftbl_gcc_pcnoc_bfdcd_clk_src[] = { 870 F(24000000, P_XO, 1, 0, 0), 871 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), 872 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 873 { } 874 }; 875 876 static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src = { 877 .cmd_rcgr = 0x31004, 878 .mnd_width = 0, 879 .hid_width = 5, 880 .parent_map = gcc_parent_map_0, 881 .freq_tbl = ftbl_gcc_pcnoc_bfdcd_clk_src, 882 .clkr.hw.init = &(const struct clk_init_data) { 883 .name = "gcc_pcnoc_bfdcd_clk_src", 884 .parent_data = gcc_parent_data_0, 885 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 886 .ops = &clk_rcg2_ops, 887 }, 888 }; 889 890 static const struct freq_tbl ftbl_gcc_lpass_sway_clk_src[] = { 891 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0), 892 { } 893 }; 894 895 static struct clk_rcg2 gcc_lpass_sway_clk_src = { 896 .cmd_rcgr = 0x27004, 897 .mnd_width = 0, 898 .hid_width = 5, 899 .parent_map = gcc_parent_map_1, 900 .freq_tbl = ftbl_gcc_lpass_sway_clk_src, 901 .clkr.hw.init = &(const struct clk_init_data) { 902 .name = "gcc_lpass_sway_clk_src", 903 .parent_data = gcc_parent_data_1, 904 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 905 .ops = &clk_rcg2_ops, 906 }, 907 }; 908 909 static struct clk_rcg2 gcc_lpass_axim_clk_src = { 910 .cmd_rcgr = 0x2700c, 911 .mnd_width = 0, 912 .hid_width = 5, 913 .parent_map = gcc_parent_map_1, 914 .freq_tbl = ftbl_gcc_lpass_sway_clk_src, 915 .clkr.hw.init = &(const struct clk_init_data) { 916 .name = "gcc_lpass_axim_clk_src", 917 .parent_data = gcc_parent_data_1, 918 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 919 .ops = &clk_rcg2_ops, 920 }, 921 }; 922 923 static struct clk_fixed_factor gcc_eud_at_div_clk_src = { 924 .mult = 1, 925 .div = 6, 926 .hw.init = &(const struct clk_init_data) { 927 .name = "gcc_eud_at_div_clk_src", 928 .parent_hws = (const struct clk_hw *[]) { 929 &gcc_qdss_at_clk_src.clkr.hw }, 930 .num_parents = 1, 931 .flags = CLK_SET_RATE_PARENT, 932 .ops = &clk_fixed_factor_ops, 933 }, 934 }; 935 936 static const struct freq_tbl ftbl_gcc_sleep_clk_src[] = { 937 F(32000, P_SLEEP_CLK, 1, 0, 0), 938 { } 939 }; 940 941 static struct clk_rcg2 gcc_sleep_clk_src = { 942 .cmd_rcgr = 0x3400c, 943 .mnd_width = 0, 944 .hid_width = 5, 945 .parent_map = gcc_parent_map_6, 946 .freq_tbl = ftbl_gcc_sleep_clk_src, 947 .clkr.hw.init = &(const struct clk_init_data) { 948 .name = "gcc_sleep_clk_src", 949 .parent_data = gcc_parent_data_6, 950 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 951 .ops = &clk_rcg2_ops, 952 }, 953 }; 954 955 static const struct freq_tbl ftbl_gcc_qpic_io_macro_clk_src[] = { 956 F(24000000, P_XO, 1, 0, 0), 957 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 958 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 959 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 960 F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 961 { } 962 }; 963 964 static struct clk_rcg2 gcc_qpic_io_macro_clk_src = { 965 .cmd_rcgr = 0x32004, 966 .mnd_width = 0, 967 .hid_width = 5, 968 .parent_map = gcc_parent_map_11, 969 .freq_tbl = ftbl_gcc_qpic_io_macro_clk_src, 970 .clkr.hw.init = &(const struct clk_init_data) { 971 .name = "gcc_qpic_io_macro_clk_src", 972 .parent_data = gcc_parent_data_11, 973 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 974 .ops = &clk_rcg2_ops, 975 }, 976 }; 977 978 static struct clk_rcg2 gcc_qpic_clk_src = { 979 .cmd_rcgr = 0x32020, 980 .mnd_width = 0, 981 .hid_width = 5, 982 .parent_map = gcc_parent_map_11, 983 .freq_tbl = ftbl_gcc_qpic_io_macro_clk_src, 984 .clkr.hw.init = &(const struct clk_init_data) { 985 .name = "gcc_qpic_clk_src", 986 .parent_data = gcc_parent_data_11, 987 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 988 .ops = &clk_rcg2_ops, 989 }, 990 }; 991 992 static struct clk_rcg2 gcc_pcie0_rchng_clk_src = { 993 .cmd_rcgr = 0x28028, 994 .mnd_width = 0, 995 .hid_width = 5, 996 .parent_map = gcc_parent_map_1, 997 .freq_tbl = ftbl_gcc_adss_pwm_clk_src, 998 .clkr.hw.init = &(const struct clk_init_data) { 999 .name = "gcc_pcie0_rchng_clk_src", 1000 .parent_data = gcc_parent_data_1, 1001 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1002 .ops = &clk_rcg2_ops, 1003 }, 1004 }; 1005 1006 static struct clk_rcg2 gcc_pcie1_rchng_clk_src = { 1007 .cmd_rcgr = 0x29028, 1008 .mnd_width = 0, 1009 .hid_width = 5, 1010 .parent_map = gcc_parent_map_1, 1011 .freq_tbl = ftbl_gcc_adss_pwm_clk_src, 1012 .clkr.hw.init = &(const struct clk_init_data) { 1013 .name = "gcc_pcie1_rchng_clk_src", 1014 .parent_data = gcc_parent_data_1, 1015 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1016 .ops = &clk_rcg2_ops, 1017 }, 1018 }; 1019 1020 static struct clk_rcg2 gcc_pcie2_rchng_clk_src = { 1021 .cmd_rcgr = 0x2a028, 1022 .mnd_width = 0, 1023 .hid_width = 5, 1024 .parent_map = gcc_parent_map_1, 1025 .freq_tbl = ftbl_gcc_adss_pwm_clk_src, 1026 .clkr.hw.init = &(const struct clk_init_data) { 1027 .name = "gcc_pcie2_rchng_clk_src", 1028 .parent_data = gcc_parent_data_1, 1029 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1030 .ops = &clk_rcg2_ops, 1031 }, 1032 }; 1033 1034 static struct clk_rcg2 gcc_pcie3_rchng_clk_src = { 1035 .cmd_rcgr = 0x2b028, 1036 .mnd_width = 0, 1037 .hid_width = 5, 1038 .parent_map = gcc_parent_map_1, 1039 .freq_tbl = ftbl_gcc_adss_pwm_clk_src, 1040 .clkr.hw.init = &(const struct clk_init_data) { 1041 .name = "gcc_pcie3_rchng_clk_src", 1042 .parent_data = gcc_parent_data_1, 1043 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1044 .ops = &clk_rcg2_ops, 1045 }, 1046 }; 1047 1048 static struct clk_regmap_div gcc_qupv3_i2c0_div_clk_src = { 1049 .reg = 0x2020, 1050 .shift = 0, 1051 .width = 2, 1052 .clkr.hw.init = &(const struct clk_init_data) { 1053 .name = "gcc_qupv3_i2c0_div_clk_src", 1054 .parent_hws = (const struct clk_hw*[]) { 1055 &gcc_qupv3_i2c0_clk_src.clkr.hw, 1056 }, 1057 .num_parents = 1, 1058 .flags = CLK_SET_RATE_PARENT, 1059 .ops = &clk_regmap_div_ro_ops, 1060 }, 1061 }; 1062 1063 static struct clk_regmap_div gcc_qupv3_i2c1_div_clk_src = { 1064 .reg = 0x3020, 1065 .shift = 0, 1066 .width = 2, 1067 .clkr.hw.init = &(const struct clk_init_data) { 1068 .name = "gcc_qupv3_i2c1_div_clk_src", 1069 .parent_hws = (const struct clk_hw*[]) { 1070 &gcc_qupv3_i2c1_clk_src.clkr.hw, 1071 }, 1072 .num_parents = 1, 1073 .flags = CLK_SET_RATE_PARENT, 1074 .ops = &clk_regmap_div_ro_ops, 1075 }, 1076 }; 1077 1078 static struct clk_regmap_div gcc_usb0_mock_utmi_div_clk_src = { 1079 .reg = 0x2c040, 1080 .shift = 0, 1081 .width = 2, 1082 .clkr.hw.init = &(const struct clk_init_data) { 1083 .name = "gcc_usb0_mock_utmi_div_clk_src", 1084 .parent_hws = (const struct clk_hw*[]) { 1085 &gcc_usb0_mock_utmi_clk_src.clkr.hw, 1086 }, 1087 .num_parents = 1, 1088 .flags = CLK_SET_RATE_PARENT, 1089 .ops = &clk_regmap_div_ro_ops, 1090 }, 1091 }; 1092 1093 static struct clk_regmap_div gcc_usb1_mock_utmi_div_clk_src = { 1094 .reg = 0x3c018, 1095 .shift = 0, 1096 .width = 2, 1097 .clkr.hw.init = &(const struct clk_init_data) { 1098 .name = "gcc_usb1_mock_utmi_div_clk_src", 1099 .parent_hws = (const struct clk_hw*[]) { 1100 &gcc_usb1_mock_utmi_clk_src.clkr.hw, 1101 }, 1102 .num_parents = 1, 1103 .flags = CLK_SET_RATE_PARENT, 1104 .ops = &clk_regmap_div_ro_ops, 1105 }, 1106 }; 1107 1108 static struct clk_branch gcc_adss_pwm_clk = { 1109 .halt_reg = 0x1c00c, 1110 .halt_check = BRANCH_HALT, 1111 .clkr = { 1112 .enable_reg = 0x1c00c, 1113 .enable_mask = BIT(0), 1114 .hw.init = &(const struct clk_init_data) { 1115 .name = "gcc_adss_pwm_clk", 1116 .parent_hws = (const struct clk_hw*[]) { 1117 &gcc_adss_pwm_clk_src.clkr.hw, 1118 }, 1119 .num_parents = 1, 1120 .flags = CLK_SET_RATE_PARENT, 1121 .ops = &clk_branch2_ops, 1122 }, 1123 }, 1124 }; 1125 1126 static struct clk_branch gcc_cnoc_pcie0_1lane_s_clk = { 1127 .halt_reg = 0x31088, 1128 .halt_check = BRANCH_HALT, 1129 .clkr = { 1130 .enable_reg = 0x31088, 1131 .enable_mask = BIT(0), 1132 .hw.init = &(const struct clk_init_data) { 1133 .name = "gcc_cnoc_pcie0_1lane_s_clk", 1134 .parent_hws = (const struct clk_hw*[]) { 1135 &gcc_pcie0_axi_s_clk_src.clkr.hw, 1136 }, 1137 .num_parents = 1, 1138 .flags = CLK_SET_RATE_PARENT, 1139 .ops = &clk_branch2_ops, 1140 }, 1141 }, 1142 }; 1143 1144 static struct clk_branch gcc_cnoc_pcie1_1lane_s_clk = { 1145 .halt_reg = 0x3108c, 1146 .halt_check = BRANCH_HALT, 1147 .clkr = { 1148 .enable_reg = 0x3108c, 1149 .enable_mask = BIT(0), 1150 .hw.init = &(const struct clk_init_data) { 1151 .name = "gcc_cnoc_pcie1_1lane_s_clk", 1152 .parent_hws = (const struct clk_hw*[]) { 1153 &gcc_pcie1_axi_s_clk_src.clkr.hw, 1154 }, 1155 .num_parents = 1, 1156 .flags = CLK_SET_RATE_PARENT, 1157 .ops = &clk_branch2_ops, 1158 }, 1159 }, 1160 }; 1161 1162 static struct clk_branch gcc_cnoc_pcie2_2lane_s_clk = { 1163 .halt_reg = 0x31090, 1164 .halt_check = BRANCH_HALT, 1165 .clkr = { 1166 .enable_reg = 0x31090, 1167 .enable_mask = BIT(0), 1168 .hw.init = &(const struct clk_init_data) { 1169 .name = "gcc_cnoc_pcie2_2lane_s_clk", 1170 .parent_hws = (const struct clk_hw*[]) { 1171 &gcc_pcie2_axi_s_clk_src.clkr.hw, 1172 }, 1173 .num_parents = 1, 1174 .flags = CLK_SET_RATE_PARENT, 1175 .ops = &clk_branch2_ops, 1176 }, 1177 }, 1178 }; 1179 1180 static struct clk_branch gcc_cnoc_pcie3_2lane_s_clk = { 1181 .halt_reg = 0x31094, 1182 .halt_check = BRANCH_HALT, 1183 .clkr = { 1184 .enable_reg = 0x31094, 1185 .enable_mask = BIT(0), 1186 .hw.init = &(const struct clk_init_data) { 1187 .name = "gcc_cnoc_pcie3_2lane_s_clk", 1188 .parent_hws = (const struct clk_hw*[]) { 1189 &gcc_pcie3_axi_s_clk_src.clkr.hw, 1190 }, 1191 .num_parents = 1, 1192 .flags = CLK_SET_RATE_PARENT, 1193 .ops = &clk_branch2_ops, 1194 }, 1195 }, 1196 }; 1197 1198 static struct clk_branch gcc_cnoc_usb_clk = { 1199 .halt_reg = 0x310a8, 1200 .halt_check = BRANCH_HALT_VOTED, 1201 .clkr = { 1202 .enable_reg = 0x310a8, 1203 .enable_mask = BIT(0), 1204 .hw.init = &(const struct clk_init_data) { 1205 .name = "gcc_cnoc_usb_clk", 1206 .parent_hws = (const struct clk_hw*[]) { 1207 &gcc_usb0_master_clk_src.clkr.hw, 1208 }, 1209 .num_parents = 1, 1210 .flags = CLK_SET_RATE_PARENT, 1211 .ops = &clk_branch2_ops, 1212 }, 1213 }, 1214 }; 1215 1216 static struct clk_branch gcc_mdio_ahb_clk = { 1217 .halt_reg = 0x17040, 1218 .halt_check = BRANCH_HALT, 1219 .clkr = { 1220 .enable_reg = 0x17040, 1221 .enable_mask = BIT(0), 1222 .hw.init = &(const struct clk_init_data) { 1223 .name = "gcc_mdio_ahb_clk", 1224 .parent_hws = (const struct clk_hw*[]) { 1225 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1226 }, 1227 .num_parents = 1, 1228 .flags = CLK_SET_RATE_PARENT, 1229 .ops = &clk_branch2_ops, 1230 }, 1231 }, 1232 }; 1233 1234 static struct clk_branch gcc_nss_ts_clk = { 1235 .halt_reg = 0x17018, 1236 .halt_check = BRANCH_HALT_VOTED, 1237 .clkr = { 1238 .enable_reg = 0x17018, 1239 .enable_mask = BIT(0), 1240 .hw.init = &(const struct clk_init_data) { 1241 .name = "gcc_nss_ts_clk", 1242 .parent_hws = (const struct clk_hw*[]) { 1243 &gcc_nss_ts_clk_src.clkr.hw, 1244 }, 1245 .num_parents = 1, 1246 .flags = CLK_SET_RATE_PARENT, 1247 .ops = &clk_branch2_ops, 1248 }, 1249 }, 1250 }; 1251 1252 static struct clk_branch gcc_nsscc_clk = { 1253 .halt_reg = 0x17034, 1254 .halt_check = BRANCH_HALT, 1255 .clkr = { 1256 .enable_reg = 0x17034, 1257 .enable_mask = BIT(0), 1258 .hw.init = &(const struct clk_init_data) { 1259 .name = "gcc_nsscc_clk", 1260 .parent_hws = (const struct clk_hw*[]) { 1261 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1262 }, 1263 .num_parents = 1, 1264 .flags = CLK_SET_RATE_PARENT, 1265 .ops = &clk_branch2_ops, 1266 }, 1267 }, 1268 }; 1269 1270 static struct clk_branch gcc_nsscfg_clk = { 1271 .halt_reg = 0x1702c, 1272 .halt_check = BRANCH_HALT, 1273 .clkr = { 1274 .enable_reg = 0x1702c, 1275 .enable_mask = BIT(0), 1276 .hw.init = &(const struct clk_init_data) { 1277 .name = "gcc_nsscfg_clk", 1278 .parent_hws = (const struct clk_hw*[]) { 1279 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1280 }, 1281 .num_parents = 1, 1282 .flags = CLK_SET_RATE_PARENT, 1283 .ops = &clk_branch2_ops, 1284 }, 1285 }, 1286 }; 1287 1288 static struct clk_branch gcc_nssnoc_atb_clk = { 1289 .halt_reg = 0x17014, 1290 .halt_check = BRANCH_HALT, 1291 .clkr = { 1292 .enable_reg = 0x17014, 1293 .enable_mask = BIT(0), 1294 .hw.init = &(const struct clk_init_data) { 1295 .name = "gcc_nssnoc_atb_clk", 1296 .parent_hws = (const struct clk_hw*[]) { 1297 &gcc_qdss_at_clk_src.clkr.hw, 1298 }, 1299 .num_parents = 1, 1300 .flags = CLK_SET_RATE_PARENT, 1301 .ops = &clk_branch2_ops, 1302 }, 1303 }, 1304 }; 1305 1306 static struct clk_branch gcc_nssnoc_nsscc_clk = { 1307 .halt_reg = 0x17030, 1308 .halt_check = BRANCH_HALT, 1309 .clkr = { 1310 .enable_reg = 0x17030, 1311 .enable_mask = BIT(0), 1312 .hw.init = &(const struct clk_init_data) { 1313 .name = "gcc_nssnoc_nsscc_clk", 1314 .parent_hws = (const struct clk_hw*[]) { 1315 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1316 }, 1317 .num_parents = 1, 1318 .flags = CLK_SET_RATE_PARENT, 1319 .ops = &clk_branch2_ops, 1320 }, 1321 }, 1322 }; 1323 1324 static struct clk_branch gcc_nssnoc_pcnoc_1_clk = { 1325 .halt_reg = 0x17080, 1326 .halt_check = BRANCH_HALT, 1327 .clkr = { 1328 .enable_reg = 0x17080, 1329 .enable_mask = BIT(0), 1330 .hw.init = &(const struct clk_init_data) { 1331 .name = "gcc_nssnoc_pcnoc_1_clk", 1332 .parent_hws = (const struct clk_hw*[]) { 1333 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1334 }, 1335 .num_parents = 1, 1336 .flags = CLK_SET_RATE_PARENT, 1337 .ops = &clk_branch2_ops, 1338 }, 1339 }, 1340 }; 1341 1342 static struct clk_branch gcc_nssnoc_qosgen_ref_clk = { 1343 .halt_reg = 0x1701c, 1344 .halt_check = BRANCH_HALT, 1345 .clkr = { 1346 .enable_reg = 0x1701c, 1347 .enable_mask = BIT(0), 1348 .hw.init = &(const struct clk_init_data) { 1349 .name = "gcc_nssnoc_qosgen_ref_clk", 1350 .parent_hws = (const struct clk_hw *[]) { 1351 &gcc_xo_div4_clk_src.hw 1352 }, 1353 .num_parents = 1, 1354 .flags = CLK_SET_RATE_PARENT, 1355 .ops = &clk_branch2_ops, 1356 }, 1357 }, 1358 }; 1359 1360 static struct clk_branch gcc_nssnoc_snoc_1_clk = { 1361 .halt_reg = 0x1707c, 1362 .halt_check = BRANCH_HALT, 1363 .clkr = { 1364 .enable_reg = 0x1707c, 1365 .enable_mask = BIT(0), 1366 .hw.init = &(const struct clk_init_data) { 1367 .name = "gcc_nssnoc_snoc_1_clk", 1368 .parent_hws = (const struct clk_hw*[]) { 1369 &gcc_system_noc_bfdcd_clk_src.clkr.hw 1370 }, 1371 .num_parents = 1, 1372 .flags = CLK_SET_RATE_PARENT, 1373 .ops = &clk_branch2_ops, 1374 }, 1375 }, 1376 }; 1377 1378 static struct clk_branch gcc_nssnoc_snoc_clk = { 1379 .halt_reg = 0x17028, 1380 .halt_check = BRANCH_HALT, 1381 .clkr = { 1382 .enable_reg = 0x17028, 1383 .enable_mask = BIT(0), 1384 .hw.init = &(const struct clk_init_data) { 1385 .name = "gcc_nssnoc_snoc_clk", 1386 .parent_hws = (const struct clk_hw*[]) { 1387 &gcc_system_noc_bfdcd_clk_src.clkr.hw 1388 }, 1389 .num_parents = 1, 1390 .flags = CLK_SET_RATE_PARENT, 1391 .ops = &clk_branch2_ops, 1392 }, 1393 }, 1394 }; 1395 1396 static struct clk_branch gcc_nssnoc_timeout_ref_clk = { 1397 .halt_reg = 0x17020, 1398 .halt_check = BRANCH_HALT, 1399 .clkr = { 1400 .enable_reg = 0x17020, 1401 .enable_mask = BIT(0), 1402 .hw.init = &(const struct clk_init_data) { 1403 .name = "gcc_nssnoc_timeout_ref_clk", 1404 .parent_hws = (const struct clk_hw*[]) { 1405 &gcc_xo_div4_clk_src.hw, 1406 }, 1407 .num_parents = 1, 1408 .flags = CLK_SET_RATE_PARENT, 1409 .ops = &clk_branch2_ops, 1410 }, 1411 }, 1412 }; 1413 1414 static struct clk_branch gcc_nssnoc_xo_dcd_clk = { 1415 .halt_reg = 0x17074, 1416 .halt_check = BRANCH_HALT, 1417 .clkr = { 1418 .enable_reg = 0x17074, 1419 .enable_mask = BIT(0), 1420 .hw.init = &(const struct clk_init_data) { 1421 .name = "gcc_nssnoc_xo_dcd_clk", 1422 .parent_hws = (const struct clk_hw*[]) { 1423 &gcc_xo_clk_src.clkr.hw, 1424 }, 1425 .num_parents = 1, 1426 .flags = CLK_SET_RATE_PARENT, 1427 .ops = &clk_branch2_ops, 1428 }, 1429 }, 1430 }; 1431 1432 static struct clk_branch gcc_pcie0_ahb_clk = { 1433 .halt_reg = 0x28030, 1434 .halt_check = BRANCH_HALT, 1435 .clkr = { 1436 .enable_reg = 0x28030, 1437 .enable_mask = BIT(0), 1438 .hw.init = &(const struct clk_init_data) { 1439 .name = "gcc_pcie0_ahb_clk", 1440 .parent_hws = (const struct clk_hw*[]) { 1441 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1442 }, 1443 .num_parents = 1, 1444 .flags = CLK_SET_RATE_PARENT, 1445 .ops = &clk_branch2_ops, 1446 }, 1447 }, 1448 }; 1449 1450 static struct clk_branch gcc_pcie0_aux_clk = { 1451 .halt_reg = 0x28070, 1452 .halt_check = BRANCH_HALT, 1453 .clkr = { 1454 .enable_reg = 0x28070, 1455 .enable_mask = BIT(0), 1456 .hw.init = &(const struct clk_init_data) { 1457 .name = "gcc_pcie0_aux_clk", 1458 .parent_hws = (const struct clk_hw*[]) { 1459 &gcc_pcie_aux_clk_src.clkr.hw, 1460 }, 1461 .num_parents = 1, 1462 .flags = CLK_SET_RATE_PARENT, 1463 .ops = &clk_branch2_ops, 1464 }, 1465 }, 1466 }; 1467 1468 static struct clk_branch gcc_pcie0_axi_m_clk = { 1469 .halt_reg = 0x28038, 1470 .halt_check = BRANCH_HALT, 1471 .clkr = { 1472 .enable_reg = 0x28038, 1473 .enable_mask = BIT(0), 1474 .hw.init = &(const struct clk_init_data) { 1475 .name = "gcc_pcie0_axi_m_clk", 1476 .parent_hws = (const struct clk_hw*[]) { 1477 &gcc_pcie0_axi_m_clk_src.clkr.hw, 1478 }, 1479 .num_parents = 1, 1480 .flags = CLK_SET_RATE_PARENT, 1481 .ops = &clk_branch2_ops, 1482 }, 1483 }, 1484 }; 1485 1486 static struct clk_branch gcc_anoc_pcie0_1lane_m_clk = { 1487 .halt_reg = 0x2e07c, 1488 .halt_check = BRANCH_HALT, 1489 .clkr = { 1490 .enable_reg = 0x2e07c, 1491 .enable_mask = BIT(0), 1492 .hw.init = &(const struct clk_init_data) { 1493 .name = "gcc_anoc_pcie0_1lane_m_clk", 1494 .parent_hws = (const struct clk_hw*[]) { 1495 &gcc_pcie0_axi_m_clk_src.clkr.hw, 1496 }, 1497 .num_parents = 1, 1498 .flags = CLK_SET_RATE_PARENT, 1499 .ops = &clk_branch2_ops, 1500 }, 1501 }, 1502 }; 1503 1504 static struct clk_branch gcc_pcie0_axi_s_bridge_clk = { 1505 .halt_reg = 0x28048, 1506 .halt_check = BRANCH_HALT, 1507 .clkr = { 1508 .enable_reg = 0x28048, 1509 .enable_mask = BIT(0), 1510 .hw.init = &(const struct clk_init_data) { 1511 .name = "gcc_pcie0_axi_s_bridge_clk", 1512 .parent_hws = (const struct clk_hw*[]) { 1513 &gcc_pcie0_axi_s_clk_src.clkr.hw, 1514 }, 1515 .num_parents = 1, 1516 .flags = CLK_SET_RATE_PARENT, 1517 .ops = &clk_branch2_ops, 1518 }, 1519 }, 1520 }; 1521 1522 static struct clk_branch gcc_pcie0_axi_s_clk = { 1523 .halt_reg = 0x28040, 1524 .halt_check = BRANCH_HALT, 1525 .clkr = { 1526 .enable_reg = 0x28040, 1527 .enable_mask = BIT(0), 1528 .hw.init = &(const struct clk_init_data) { 1529 .name = "gcc_pcie0_axi_s_clk", 1530 .parent_hws = (const struct clk_hw*[]) { 1531 &gcc_pcie0_axi_s_clk_src.clkr.hw, 1532 }, 1533 .num_parents = 1, 1534 .flags = CLK_SET_RATE_PARENT, 1535 .ops = &clk_branch2_ops, 1536 }, 1537 }, 1538 }; 1539 1540 static struct clk_regmap_phy_mux gcc_pcie0_pipe_clk_src = { 1541 .reg = 0x28064, 1542 .clkr = { 1543 .hw.init = &(const struct clk_init_data) { 1544 .name = "pcie0_pipe_clk_src", 1545 .parent_data = &(const struct clk_parent_data) { 1546 .index = DT_PCIE30_PHY0_PIPE_CLK, 1547 }, 1548 .num_parents = 1, 1549 .ops = &clk_regmap_phy_mux_ops, 1550 }, 1551 }, 1552 }; 1553 1554 static struct clk_branch gcc_pcie0_pipe_clk = { 1555 .halt_reg = 0x28068, 1556 .halt_check = BRANCH_HALT_DELAY, 1557 .clkr = { 1558 .enable_reg = 0x28068, 1559 .enable_mask = BIT(0), 1560 .hw.init = &(const struct clk_init_data) { 1561 .name = "gcc_pcie0_pipe_clk", 1562 .parent_hws = (const struct clk_hw *[]) { 1563 &gcc_pcie0_pipe_clk_src.clkr.hw 1564 }, 1565 .num_parents = 1, 1566 .flags = CLK_SET_RATE_PARENT, 1567 .ops = &clk_branch2_ops, 1568 }, 1569 }, 1570 }; 1571 1572 static struct clk_branch gcc_pcie1_ahb_clk = { 1573 .halt_reg = 0x29030, 1574 .halt_check = BRANCH_HALT, 1575 .clkr = { 1576 .enable_reg = 0x29030, 1577 .enable_mask = BIT(0), 1578 .hw.init = &(const struct clk_init_data) { 1579 .name = "gcc_pcie1_ahb_clk", 1580 .parent_hws = (const struct clk_hw*[]) { 1581 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1582 }, 1583 .num_parents = 1, 1584 .flags = CLK_SET_RATE_PARENT, 1585 .ops = &clk_branch2_ops, 1586 }, 1587 }, 1588 }; 1589 1590 static struct clk_branch gcc_pcie1_aux_clk = { 1591 .halt_reg = 0x29074, 1592 .halt_check = BRANCH_HALT, 1593 .clkr = { 1594 .enable_reg = 0x29074, 1595 .enable_mask = BIT(0), 1596 .hw.init = &(const struct clk_init_data) { 1597 .name = "gcc_pcie1_aux_clk", 1598 .parent_hws = (const struct clk_hw*[]) { 1599 &gcc_pcie_aux_clk_src.clkr.hw, 1600 }, 1601 .num_parents = 1, 1602 .flags = CLK_SET_RATE_PARENT, 1603 .ops = &clk_branch2_ops, 1604 }, 1605 }, 1606 }; 1607 1608 static struct clk_branch gcc_pcie1_axi_m_clk = { 1609 .halt_reg = 0x29038, 1610 .halt_check = BRANCH_HALT, 1611 .clkr = { 1612 .enable_reg = 0x29038, 1613 .enable_mask = BIT(0), 1614 .hw.init = &(const struct clk_init_data) { 1615 .name = "gcc_pcie1_axi_m_clk", 1616 .parent_hws = (const struct clk_hw*[]) { 1617 &gcc_pcie1_axi_m_clk_src.clkr.hw, 1618 }, 1619 .num_parents = 1, 1620 .flags = CLK_SET_RATE_PARENT, 1621 .ops = &clk_branch2_ops, 1622 }, 1623 }, 1624 }; 1625 1626 static struct clk_branch gcc_anoc_pcie1_1lane_m_clk = { 1627 .halt_reg = 0x2e084, 1628 .halt_check = BRANCH_HALT, 1629 .clkr = { 1630 .enable_reg = 0x2e084, 1631 .enable_mask = BIT(0), 1632 .hw.init = &(const struct clk_init_data) { 1633 .name = "gcc_anoc_pcie1_1lane_m_clk", 1634 .parent_hws = (const struct clk_hw*[]) { 1635 &gcc_pcie1_axi_m_clk_src.clkr.hw, 1636 }, 1637 .num_parents = 1, 1638 .flags = CLK_SET_RATE_PARENT, 1639 .ops = &clk_branch2_ops, 1640 }, 1641 }, 1642 }; 1643 1644 static struct clk_branch gcc_pcie1_axi_s_bridge_clk = { 1645 .halt_reg = 0x29048, 1646 .halt_check = BRANCH_HALT, 1647 .clkr = { 1648 .enable_reg = 0x29048, 1649 .enable_mask = BIT(0), 1650 .hw.init = &(const struct clk_init_data) { 1651 .name = "gcc_pcie1_axi_s_bridge_clk", 1652 .parent_hws = (const struct clk_hw*[]) { 1653 &gcc_pcie1_axi_s_clk_src.clkr.hw, 1654 }, 1655 .num_parents = 1, 1656 .flags = CLK_SET_RATE_PARENT, 1657 .ops = &clk_branch2_ops, 1658 }, 1659 }, 1660 }; 1661 1662 static struct clk_branch gcc_pcie1_axi_s_clk = { 1663 .halt_reg = 0x29040, 1664 .halt_check = BRANCH_HALT, 1665 .clkr = { 1666 .enable_reg = 0x29040, 1667 .enable_mask = BIT(0), 1668 .hw.init = &(const struct clk_init_data) { 1669 .name = "gcc_pcie1_axi_s_clk", 1670 .parent_hws = (const struct clk_hw*[]) { 1671 &gcc_pcie1_axi_s_clk_src.clkr.hw, 1672 }, 1673 .num_parents = 1, 1674 .flags = CLK_SET_RATE_PARENT, 1675 .ops = &clk_branch2_ops, 1676 }, 1677 }, 1678 }; 1679 1680 static struct clk_regmap_phy_mux gcc_pcie1_pipe_clk_src = { 1681 .reg = 0x29064, 1682 .clkr = { 1683 .hw.init = &(const struct clk_init_data) { 1684 .name = "pcie1_pipe_clk_src", 1685 .parent_data = &(const struct clk_parent_data) { 1686 .index = DT_PCIE30_PHY1_PIPE_CLK, 1687 }, 1688 .num_parents = 1, 1689 .ops = &clk_regmap_phy_mux_ops, 1690 }, 1691 }, 1692 }; 1693 1694 static struct clk_branch gcc_pcie1_pipe_clk = { 1695 .halt_reg = 0x29068, 1696 .halt_check = BRANCH_HALT_DELAY, 1697 .clkr = { 1698 .enable_reg = 0x29068, 1699 .enable_mask = BIT(0), 1700 .hw.init = &(const struct clk_init_data) { 1701 .name = "gcc_pcie1_pipe_clk", 1702 .parent_hws = (const struct clk_hw *[]) { 1703 &gcc_pcie1_pipe_clk_src.clkr.hw 1704 }, 1705 .num_parents = 1, 1706 .flags = CLK_SET_RATE_PARENT, 1707 1708 .ops = &clk_branch2_ops, 1709 }, 1710 }, 1711 }; 1712 1713 static struct clk_branch gcc_pcie2_ahb_clk = { 1714 .halt_reg = 0x2a030, 1715 .halt_check = BRANCH_HALT, 1716 .clkr = { 1717 .enable_reg = 0x2a030, 1718 .enable_mask = BIT(0), 1719 .hw.init = &(const struct clk_init_data) { 1720 .name = "gcc_pcie2_ahb_clk", 1721 .parent_hws = (const struct clk_hw*[]) { 1722 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1723 }, 1724 .num_parents = 1, 1725 .flags = CLK_SET_RATE_PARENT, 1726 .ops = &clk_branch2_ops, 1727 }, 1728 }, 1729 }; 1730 1731 static struct clk_branch gcc_pcie2_aux_clk = { 1732 .halt_reg = 0x2a078, 1733 .halt_check = BRANCH_HALT, 1734 .clkr = { 1735 .enable_reg = 0x2a078, 1736 .enable_mask = BIT(0), 1737 .hw.init = &(const struct clk_init_data) { 1738 .name = "gcc_pcie2_aux_clk", 1739 .parent_hws = (const struct clk_hw*[]) { 1740 &gcc_pcie_aux_clk_src.clkr.hw, 1741 }, 1742 .num_parents = 1, 1743 .flags = CLK_SET_RATE_PARENT, 1744 .ops = &clk_branch2_ops, 1745 }, 1746 }, 1747 }; 1748 1749 static struct clk_branch gcc_pcie2_axi_m_clk = { 1750 .halt_reg = 0x2a038, 1751 .halt_check = BRANCH_HALT, 1752 .clkr = { 1753 .enable_reg = 0x2a038, 1754 .enable_mask = BIT(0), 1755 .hw.init = &(const struct clk_init_data) { 1756 .name = "gcc_pcie2_axi_m_clk", 1757 .parent_hws = (const struct clk_hw*[]) { 1758 &gcc_pcie2_axi_m_clk_src.clkr.hw, 1759 }, 1760 .num_parents = 1, 1761 .flags = CLK_SET_RATE_PARENT, 1762 .ops = &clk_branch2_ops, 1763 }, 1764 }, 1765 }; 1766 1767 static struct clk_branch gcc_anoc_pcie2_2lane_m_clk = { 1768 .halt_reg = 0x2e080, 1769 .halt_check = BRANCH_HALT, 1770 .clkr = { 1771 .enable_reg = 0x2e080, 1772 .enable_mask = BIT(0), 1773 .hw.init = &(const struct clk_init_data) { 1774 .name = "gcc_anoc_pcie2_2lane_m_clk", 1775 .parent_hws = (const struct clk_hw*[]) { 1776 &gcc_pcie2_axi_m_clk_src.clkr.hw, 1777 }, 1778 .num_parents = 1, 1779 .flags = CLK_SET_RATE_PARENT, 1780 .ops = &clk_branch2_ops, 1781 }, 1782 }, 1783 }; 1784 1785 static struct clk_branch gcc_pcie2_axi_s_bridge_clk = { 1786 .halt_reg = 0x2a048, 1787 .halt_check = BRANCH_HALT, 1788 .clkr = { 1789 .enable_reg = 0x2a048, 1790 .enable_mask = BIT(0), 1791 .hw.init = &(const struct clk_init_data) { 1792 .name = "gcc_pcie2_axi_s_bridge_clk", 1793 .parent_hws = (const struct clk_hw*[]) { 1794 &gcc_pcie2_axi_s_clk_src.clkr.hw, 1795 }, 1796 .num_parents = 1, 1797 .flags = CLK_SET_RATE_PARENT, 1798 .ops = &clk_branch2_ops, 1799 }, 1800 }, 1801 }; 1802 1803 static struct clk_branch gcc_pcie2_axi_s_clk = { 1804 .halt_reg = 0x2a040, 1805 .halt_check = BRANCH_HALT, 1806 .clkr = { 1807 .enable_reg = 0x2a040, 1808 .enable_mask = BIT(0), 1809 .hw.init = &(const struct clk_init_data) { 1810 .name = "gcc_pcie2_axi_s_clk", 1811 .parent_hws = (const struct clk_hw*[]) { 1812 &gcc_pcie2_axi_s_clk_src.clkr.hw, 1813 }, 1814 .num_parents = 1, 1815 .flags = CLK_SET_RATE_PARENT, 1816 .ops = &clk_branch2_ops, 1817 }, 1818 }, 1819 }; 1820 1821 static struct clk_regmap_phy_mux gcc_pcie2_pipe_clk_src = { 1822 .reg = 0x2a064, 1823 .clkr = { 1824 .hw.init = &(const struct clk_init_data) { 1825 .name = "pcie2_pipe_clk_src", 1826 .parent_data = &(const struct clk_parent_data) { 1827 .index = DT_PCIE30_PHY2_PIPE_CLK, 1828 }, 1829 .num_parents = 1, 1830 .ops = &clk_regmap_phy_mux_ops, 1831 }, 1832 }, 1833 }; 1834 1835 static struct clk_branch gcc_pcie2_pipe_clk = { 1836 .halt_reg = 0x2a068, 1837 .halt_check = BRANCH_HALT_DELAY, 1838 .clkr = { 1839 .enable_reg = 0x2a068, 1840 .enable_mask = BIT(0), 1841 .hw.init = &(const struct clk_init_data) { 1842 .name = "gcc_pcie2_pipe_clk", 1843 .parent_hws = (const struct clk_hw *[]) { 1844 &gcc_pcie2_pipe_clk_src.clkr.hw 1845 }, 1846 .num_parents = 1, 1847 .flags = CLK_SET_RATE_PARENT, 1848 .ops = &clk_branch2_ops, 1849 }, 1850 }, 1851 }; 1852 1853 static struct clk_branch gcc_pcie3_ahb_clk = { 1854 .halt_reg = 0x2b030, 1855 .halt_check = BRANCH_HALT, 1856 .clkr = { 1857 .enable_reg = 0x2b030, 1858 .enable_mask = BIT(0), 1859 .hw.init = &(const struct clk_init_data) { 1860 .name = "gcc_pcie3_ahb_clk", 1861 .parent_hws = (const struct clk_hw*[]) { 1862 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1863 }, 1864 .num_parents = 1, 1865 .flags = CLK_SET_RATE_PARENT, 1866 .ops = &clk_branch2_ops, 1867 }, 1868 }, 1869 }; 1870 1871 static struct clk_branch gcc_pcie3_aux_clk = { 1872 .halt_reg = 0x2b07c, 1873 .halt_check = BRANCH_HALT, 1874 .clkr = { 1875 .enable_reg = 0x2b07c, 1876 .enable_mask = BIT(0), 1877 .hw.init = &(const struct clk_init_data) { 1878 .name = "gcc_pcie3_aux_clk", 1879 .parent_hws = (const struct clk_hw*[]) { 1880 &gcc_pcie_aux_clk_src.clkr.hw, 1881 }, 1882 .num_parents = 1, 1883 .flags = CLK_SET_RATE_PARENT, 1884 .ops = &clk_branch2_ops, 1885 }, 1886 }, 1887 }; 1888 1889 static struct clk_branch gcc_pcie3_axi_m_clk = { 1890 .halt_reg = 0x2b038, 1891 .halt_check = BRANCH_HALT, 1892 .clkr = { 1893 .enable_reg = 0x2b038, 1894 .enable_mask = BIT(0), 1895 .hw.init = &(const struct clk_init_data) { 1896 .name = "gcc_pcie3_axi_m_clk", 1897 .parent_hws = (const struct clk_hw*[]) { 1898 &gcc_pcie3_axi_m_clk_src.clkr.hw, 1899 }, 1900 .num_parents = 1, 1901 .flags = CLK_SET_RATE_PARENT, 1902 .ops = &clk_branch2_ops, 1903 }, 1904 }, 1905 }; 1906 1907 static struct clk_branch gcc_anoc_pcie3_2lane_m_clk = { 1908 .halt_reg = 0x2e090, 1909 .halt_check = BRANCH_HALT, 1910 .clkr = { 1911 .enable_reg = 0x2e090, 1912 .enable_mask = BIT(0), 1913 .hw.init = &(const struct clk_init_data) { 1914 .name = "gcc_anoc_pcie3_2lane_m_clk", 1915 .parent_hws = (const struct clk_hw*[]) { 1916 &gcc_pcie3_axi_m_clk_src.clkr.hw, 1917 }, 1918 .num_parents = 1, 1919 .flags = CLK_SET_RATE_PARENT, 1920 .ops = &clk_branch2_ops, 1921 }, 1922 }, 1923 }; 1924 1925 static struct clk_branch gcc_pcie3_axi_s_bridge_clk = { 1926 .halt_reg = 0x2b048, 1927 .halt_check = BRANCH_HALT, 1928 .clkr = { 1929 .enable_reg = 0x2b048, 1930 .enable_mask = BIT(0), 1931 .hw.init = &(const struct clk_init_data) { 1932 .name = "gcc_pcie3_axi_s_bridge_clk", 1933 .parent_hws = (const struct clk_hw*[]) { 1934 &gcc_pcie3_axi_s_clk_src.clkr.hw, 1935 }, 1936 .num_parents = 1, 1937 .flags = CLK_SET_RATE_PARENT, 1938 .ops = &clk_branch2_ops, 1939 }, 1940 }, 1941 }; 1942 1943 static struct clk_branch gcc_pcie3_axi_s_clk = { 1944 .halt_reg = 0x2b040, 1945 .halt_check = BRANCH_HALT, 1946 .clkr = { 1947 .enable_reg = 0x2b040, 1948 .enable_mask = BIT(0), 1949 .hw.init = &(const struct clk_init_data) { 1950 .name = "gcc_pcie3_axi_s_clk", 1951 .parent_hws = (const struct clk_hw*[]) { 1952 &gcc_pcie3_axi_s_clk_src.clkr.hw, 1953 }, 1954 .num_parents = 1, 1955 .flags = CLK_SET_RATE_PARENT, 1956 .ops = &clk_branch2_ops, 1957 }, 1958 }, 1959 }; 1960 1961 static struct clk_regmap_phy_mux gcc_pcie3_pipe_clk_src = { 1962 .reg = 0x2b064, 1963 .clkr = { 1964 .hw.init = &(const struct clk_init_data) { 1965 .name = "pcie3_pipe_clk_src", 1966 .parent_data = &(const struct clk_parent_data) { 1967 .index = DT_PCIE30_PHY3_PIPE_CLK, 1968 }, 1969 .num_parents = 1, 1970 .ops = &clk_regmap_phy_mux_ops, 1971 }, 1972 }, 1973 }; 1974 1975 static struct clk_branch gcc_pcie3_pipe_clk = { 1976 .halt_reg = 0x2b068, 1977 .halt_check = BRANCH_HALT_DELAY, 1978 .clkr = { 1979 .enable_reg = 0x2b068, 1980 .enable_mask = BIT(0), 1981 .hw.init = &(const struct clk_init_data) { 1982 .name = "gcc_pcie3_pipe_clk", 1983 .parent_hws = (const struct clk_hw *[]) { 1984 &gcc_pcie3_pipe_clk_src.clkr.hw 1985 }, 1986 .num_parents = 1, 1987 .flags = CLK_SET_RATE_PARENT, 1988 .ops = &clk_branch2_ops, 1989 }, 1990 }, 1991 }; 1992 1993 static struct clk_branch gcc_prng_ahb_clk = { 1994 .halt_reg = 0x13024, 1995 .halt_check = BRANCH_HALT_VOTED, 1996 .clkr = { 1997 .enable_reg = 0xb004, 1998 .enable_mask = BIT(10), 1999 .hw.init = &(const struct clk_init_data) { 2000 .name = "gcc_prng_ahb_clk", 2001 .parent_hws = (const struct clk_hw*[]) { 2002 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2003 }, 2004 .num_parents = 1, 2005 .flags = CLK_SET_RATE_PARENT, 2006 .ops = &clk_branch2_ops, 2007 }, 2008 }, 2009 }; 2010 2011 static struct clk_branch gcc_qupv3_ahb_mst_clk = { 2012 .halt_reg = 0x1014, 2013 .halt_check = BRANCH_HALT_VOTED, 2014 .clkr = { 2015 .enable_reg = 0xb004, 2016 .enable_mask = BIT(14), 2017 .hw.init = &(const struct clk_init_data) { 2018 .name = "gcc_qupv3_ahb_mst_clk", 2019 .parent_hws = (const struct clk_hw*[]) { 2020 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2021 }, 2022 .num_parents = 1, 2023 .flags = CLK_SET_RATE_PARENT, 2024 .ops = &clk_branch2_ops, 2025 }, 2026 }, 2027 }; 2028 2029 static struct clk_branch gcc_qupv3_ahb_slv_clk = { 2030 .halt_reg = 0x102c, 2031 .halt_check = BRANCH_HALT_VOTED, 2032 .clkr = { 2033 .enable_reg = 0xb004, 2034 .enable_mask = BIT(4), 2035 .hw.init = &(const struct clk_init_data) { 2036 .name = "gcc_qupv3_ahb_slv_clk", 2037 .parent_hws = (const struct clk_hw*[]) { 2038 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2039 }, 2040 .num_parents = 1, 2041 .flags = CLK_SET_RATE_PARENT, 2042 .ops = &clk_branch2_ops, 2043 }, 2044 }, 2045 }; 2046 2047 static struct clk_branch gcc_qupv3_i2c0_clk = { 2048 .halt_reg = 0x2024, 2049 .halt_check = BRANCH_HALT, 2050 .clkr = { 2051 .enable_reg = 0x2024, 2052 .enable_mask = BIT(0), 2053 .hw.init = &(const struct clk_init_data) { 2054 .name = "gcc_qupv3_i2c0_clk", 2055 .parent_hws = (const struct clk_hw*[]) { 2056 &gcc_qupv3_i2c0_div_clk_src.clkr.hw, 2057 }, 2058 .num_parents = 1, 2059 .flags = CLK_SET_RATE_PARENT, 2060 .ops = &clk_branch2_ops, 2061 }, 2062 }, 2063 }; 2064 2065 static struct clk_branch gcc_qupv3_i2c1_clk = { 2066 .halt_reg = 0x3024, 2067 .halt_check = BRANCH_HALT, 2068 .clkr = { 2069 .enable_reg = 0x3024, 2070 .enable_mask = BIT(0), 2071 .hw.init = &(const struct clk_init_data) { 2072 .name = "gcc_qupv3_i2c1_clk", 2073 .parent_hws = (const struct clk_hw*[]) { 2074 &gcc_qupv3_i2c1_div_clk_src.clkr.hw, 2075 }, 2076 .num_parents = 1, 2077 .flags = CLK_SET_RATE_PARENT, 2078 .ops = &clk_branch2_ops, 2079 }, 2080 }, 2081 }; 2082 2083 static struct clk_branch gcc_qupv3_spi0_clk = { 2084 .halt_reg = 0x4020, 2085 .halt_check = BRANCH_HALT, 2086 .clkr = { 2087 .enable_reg = 0x4020, 2088 .enable_mask = BIT(0), 2089 .hw.init = &(const struct clk_init_data) { 2090 .name = "gcc_qupv3_spi0_clk", 2091 .parent_hws = (const struct clk_hw*[]) { 2092 &gcc_qupv3_spi0_clk_src.clkr.hw, 2093 }, 2094 .num_parents = 1, 2095 .flags = CLK_SET_RATE_PARENT, 2096 .ops = &clk_branch2_ops, 2097 }, 2098 }, 2099 }; 2100 2101 static struct clk_branch gcc_qupv3_spi1_clk = { 2102 .halt_reg = 0x5020, 2103 .halt_check = BRANCH_HALT, 2104 .clkr = { 2105 .enable_reg = 0x5020, 2106 .enable_mask = BIT(0), 2107 .hw.init = &(const struct clk_init_data) { 2108 .name = "gcc_qupv3_spi1_clk", 2109 .parent_hws = (const struct clk_hw*[]) { 2110 &gcc_qupv3_spi1_clk_src.clkr.hw, 2111 }, 2112 .num_parents = 1, 2113 .flags = CLK_SET_RATE_PARENT, 2114 .ops = &clk_branch2_ops, 2115 }, 2116 }, 2117 }; 2118 2119 static struct clk_branch gcc_qupv3_uart0_clk = { 2120 .halt_reg = 0x2040, 2121 .halt_check = BRANCH_HALT, 2122 .clkr = { 2123 .enable_reg = 0x2040, 2124 .enable_mask = BIT(0), 2125 .hw.init = &(const struct clk_init_data) { 2126 .name = "gcc_qupv3_uart0_clk", 2127 .parent_hws = (const struct clk_hw*[]) { 2128 &gcc_qupv3_uart0_clk_src.clkr.hw, 2129 }, 2130 .num_parents = 1, 2131 .flags = CLK_SET_RATE_PARENT, 2132 .ops = &clk_branch2_ops, 2133 }, 2134 }, 2135 }; 2136 2137 static struct clk_branch gcc_qupv3_uart1_clk = { 2138 .halt_reg = 0x3040, 2139 .halt_check = BRANCH_HALT, 2140 .clkr = { 2141 .enable_reg = 0x3040, 2142 .enable_mask = BIT(0), 2143 .hw.init = &(const struct clk_init_data) { 2144 .name = "gcc_qupv3_uart1_clk", 2145 .parent_hws = (const struct clk_hw*[]) { 2146 &gcc_qupv3_uart1_clk_src.clkr.hw, 2147 }, 2148 .num_parents = 1, 2149 .flags = CLK_SET_RATE_PARENT, 2150 .ops = &clk_branch2_ops, 2151 }, 2152 }, 2153 }; 2154 2155 static struct clk_branch gcc_sdcc1_ahb_clk = { 2156 .halt_reg = 0x3303c, 2157 .halt_check = BRANCH_HALT, 2158 .clkr = { 2159 .enable_reg = 0x3303c, 2160 .enable_mask = BIT(0), 2161 .hw.init = &(const struct clk_init_data) { 2162 .name = "gcc_sdcc1_ahb_clk", 2163 .parent_hws = (const struct clk_hw*[]) { 2164 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2165 }, 2166 .num_parents = 1, 2167 .flags = CLK_SET_RATE_PARENT, 2168 .ops = &clk_branch2_ops, 2169 }, 2170 }, 2171 }; 2172 2173 static struct clk_branch gcc_sdcc1_apps_clk = { 2174 .halt_reg = 0x3302c, 2175 .halt_check = BRANCH_HALT, 2176 .clkr = { 2177 .enable_reg = 0x3302c, 2178 .enable_mask = BIT(0), 2179 .hw.init = &(const struct clk_init_data) { 2180 .name = "gcc_sdcc1_apps_clk", 2181 .parent_hws = (const struct clk_hw*[]) { 2182 &gcc_sdcc1_apps_clk_src.clkr.hw, 2183 }, 2184 .num_parents = 1, 2185 .flags = CLK_SET_RATE_PARENT, 2186 .ops = &clk_branch2_ops, 2187 }, 2188 }, 2189 }; 2190 2191 static struct clk_branch gcc_sdcc1_ice_core_clk = { 2192 .halt_reg = 0x33034, 2193 .halt_check = BRANCH_HALT, 2194 .clkr = { 2195 .enable_reg = 0x33034, 2196 .enable_mask = BIT(0), 2197 .hw.init = &(const struct clk_init_data) { 2198 .name = "gcc_sdcc1_ice_core_clk", 2199 .parent_hws = (const struct clk_hw*[]) { 2200 &gcc_sdcc1_ice_core_clk_src.clkr.hw, 2201 }, 2202 .num_parents = 1, 2203 .flags = CLK_SET_RATE_PARENT, 2204 .ops = &clk_branch2_ops, 2205 }, 2206 }, 2207 }; 2208 2209 static struct clk_branch gcc_uniphy0_ahb_clk = { 2210 .halt_reg = 0x1704c, 2211 .halt_check = BRANCH_HALT, 2212 .clkr = { 2213 .enable_reg = 0x1704c, 2214 .enable_mask = BIT(0), 2215 .hw.init = &(const struct clk_init_data) { 2216 .name = "gcc_uniphy0_ahb_clk", 2217 .parent_hws = (const struct clk_hw*[]) { 2218 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2219 }, 2220 .num_parents = 1, 2221 .flags = CLK_SET_RATE_PARENT, 2222 .ops = &clk_branch2_ops, 2223 }, 2224 }, 2225 }; 2226 2227 static struct clk_branch gcc_uniphy0_sys_clk = { 2228 .halt_reg = 0x17048, 2229 .halt_check = BRANCH_HALT_VOTED, 2230 .clkr = { 2231 .enable_reg = 0x17048, 2232 .enable_mask = BIT(0), 2233 .hw.init = &(const struct clk_init_data) { 2234 .name = "gcc_uniphy0_sys_clk", 2235 .parent_hws = (const struct clk_hw*[]) { 2236 &gcc_uniphy_sys_clk_src.clkr.hw, 2237 }, 2238 .num_parents = 1, 2239 .flags = CLK_SET_RATE_PARENT, 2240 .ops = &clk_branch2_ops, 2241 }, 2242 }, 2243 }; 2244 2245 static struct clk_branch gcc_uniphy1_ahb_clk = { 2246 .halt_reg = 0x1705c, 2247 .halt_check = BRANCH_HALT, 2248 .clkr = { 2249 .enable_reg = 0x1705c, 2250 .enable_mask = BIT(0), 2251 .hw.init = &(const struct clk_init_data) { 2252 .name = "gcc_uniphy1_ahb_clk", 2253 .parent_hws = (const struct clk_hw*[]) { 2254 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2255 }, 2256 .num_parents = 1, 2257 .flags = CLK_SET_RATE_PARENT, 2258 .ops = &clk_branch2_ops, 2259 }, 2260 }, 2261 }; 2262 2263 static struct clk_branch gcc_uniphy1_sys_clk = { 2264 .halt_reg = 0x17058, 2265 .halt_check = BRANCH_HALT_VOTED, 2266 .clkr = { 2267 .enable_reg = 0x17058, 2268 .enable_mask = BIT(0), 2269 .hw.init = &(const struct clk_init_data) { 2270 .name = "gcc_uniphy1_sys_clk", 2271 .parent_hws = (const struct clk_hw*[]) { 2272 &gcc_uniphy_sys_clk_src.clkr.hw, 2273 }, 2274 .num_parents = 1, 2275 .flags = CLK_SET_RATE_PARENT, 2276 .ops = &clk_branch2_ops, 2277 }, 2278 }, 2279 }; 2280 2281 static struct clk_branch gcc_uniphy2_ahb_clk = { 2282 .halt_reg = 0x1706c, 2283 .halt_check = BRANCH_HALT, 2284 .clkr = { 2285 .enable_reg = 0x1706c, 2286 .enable_mask = BIT(0), 2287 .hw.init = &(const struct clk_init_data) { 2288 .name = "gcc_uniphy2_ahb_clk", 2289 .parent_hws = (const struct clk_hw*[]) { 2290 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2291 }, 2292 .num_parents = 1, 2293 .flags = CLK_SET_RATE_PARENT, 2294 .ops = &clk_branch2_ops, 2295 }, 2296 }, 2297 }; 2298 2299 static struct clk_branch gcc_uniphy2_sys_clk = { 2300 .halt_reg = 0x17068, 2301 .halt_check = BRANCH_HALT_VOTED, 2302 .clkr = { 2303 .enable_reg = 0x17068, 2304 .enable_mask = BIT(0), 2305 .hw.init = &(const struct clk_init_data) { 2306 .name = "gcc_uniphy2_sys_clk", 2307 .parent_hws = (const struct clk_hw*[]) { 2308 &gcc_uniphy_sys_clk_src.clkr.hw, 2309 }, 2310 .num_parents = 1, 2311 .flags = CLK_SET_RATE_PARENT, 2312 .ops = &clk_branch2_ops, 2313 }, 2314 }, 2315 }; 2316 2317 static struct clk_branch gcc_usb0_aux_clk = { 2318 .halt_reg = 0x2c04c, 2319 .halt_check = BRANCH_HALT_VOTED, 2320 .clkr = { 2321 .enable_reg = 0x2c04c, 2322 .enable_mask = BIT(0), 2323 .hw.init = &(const struct clk_init_data) { 2324 .name = "gcc_usb0_aux_clk", 2325 .parent_hws = (const struct clk_hw*[]) { 2326 &gcc_usb0_aux_clk_src.clkr.hw, 2327 }, 2328 .num_parents = 1, 2329 .flags = CLK_SET_RATE_PARENT, 2330 .ops = &clk_branch2_ops, 2331 }, 2332 }, 2333 }; 2334 2335 static struct clk_branch gcc_usb0_master_clk = { 2336 .halt_reg = 0x2c044, 2337 .halt_check = BRANCH_HALT_VOTED, 2338 .clkr = { 2339 .enable_reg = 0x2c044, 2340 .enable_mask = BIT(0), 2341 .hw.init = &(const struct clk_init_data) { 2342 .name = "gcc_usb0_master_clk", 2343 .parent_hws = (const struct clk_hw*[]) { 2344 &gcc_usb0_master_clk_src.clkr.hw, 2345 }, 2346 .num_parents = 1, 2347 .flags = CLK_SET_RATE_PARENT, 2348 .ops = &clk_branch2_ops, 2349 }, 2350 }, 2351 }; 2352 2353 static struct clk_branch gcc_usb0_mock_utmi_clk = { 2354 .halt_reg = 0x2c050, 2355 .halt_check = BRANCH_HALT_VOTED, 2356 .clkr = { 2357 .enable_reg = 0x2c050, 2358 .enable_mask = BIT(0), 2359 .hw.init = &(const struct clk_init_data) { 2360 .name = "gcc_usb0_mock_utmi_clk", 2361 .parent_hws = (const struct clk_hw*[]) { 2362 &gcc_usb0_mock_utmi_div_clk_src.clkr.hw, 2363 }, 2364 .num_parents = 1, 2365 .flags = CLK_SET_RATE_PARENT, 2366 .ops = &clk_branch2_ops, 2367 }, 2368 }, 2369 }; 2370 2371 static struct clk_branch gcc_usb1_mock_utmi_clk = { 2372 .halt_reg = 0x3c024, 2373 .halt_check = BRANCH_HALT_VOTED, 2374 .clkr = { 2375 .enable_reg = 0x3c024, 2376 .enable_mask = BIT(0), 2377 .hw.init = &(const struct clk_init_data) { 2378 .name = "gcc_usb1_mock_utmi_clk", 2379 .parent_hws = (const struct clk_hw*[]) { 2380 &gcc_usb1_mock_utmi_div_clk_src.clkr.hw, 2381 }, 2382 .num_parents = 1, 2383 .flags = CLK_SET_RATE_PARENT, 2384 .ops = &clk_branch2_ops, 2385 }, 2386 }, 2387 }; 2388 2389 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = { 2390 .halt_reg = 0x2c05c, 2391 .halt_check = BRANCH_HALT_VOTED, 2392 .clkr = { 2393 .enable_reg = 0x2c05c, 2394 .enable_mask = BIT(0), 2395 .hw.init = &(const struct clk_init_data) { 2396 .name = "gcc_usb0_phy_cfg_ahb_clk", 2397 .parent_hws = (const struct clk_hw*[]) { 2398 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2399 }, 2400 .num_parents = 1, 2401 .flags = CLK_SET_RATE_PARENT, 2402 .ops = &clk_branch2_ops, 2403 }, 2404 }, 2405 }; 2406 2407 static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = { 2408 .halt_reg = 0x3c01c, 2409 .halt_check = BRANCH_HALT_VOTED, 2410 .clkr = { 2411 .enable_reg = 0x3c01c, 2412 .enable_mask = BIT(0), 2413 .hw.init = &(const struct clk_init_data) { 2414 .name = "gcc_usb1_phy_cfg_ahb_clk", 2415 .parent_hws = (const struct clk_hw*[]) { 2416 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2417 }, 2418 .num_parents = 1, 2419 .flags = CLK_SET_RATE_PARENT, 2420 .ops = &clk_branch2_ops, 2421 }, 2422 }, 2423 }; 2424 2425 static struct clk_branch gcc_usb1_master_clk = { 2426 .halt_reg = 0x3c028, 2427 .halt_check = BRANCH_HALT_VOTED, 2428 .clkr = { 2429 .enable_reg = 0x3c028, 2430 .enable_mask = BIT(0), 2431 .hw.init = &(const struct clk_init_data) { 2432 .name = "gcc_usb1_master_clk", 2433 .parent_hws = (const struct clk_hw*[]) { 2434 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2435 }, 2436 .num_parents = 1, 2437 .flags = CLK_SET_RATE_PARENT, 2438 .ops = &clk_branch2_ops, 2439 }, 2440 }, 2441 }; 2442 2443 static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = { 2444 .reg = 0x2c074, 2445 .clkr = { 2446 .hw.init = &(const struct clk_init_data) { 2447 .name = "gcc_usb0_pipe_clk_src", 2448 .parent_data = &(const struct clk_parent_data) { 2449 .index = DT_USB_PCIE_WRAPPER_PIPE_CLK, 2450 }, 2451 .num_parents = 1, 2452 .ops = &clk_regmap_phy_mux_ops, 2453 }, 2454 }, 2455 }; 2456 2457 static struct clk_branch gcc_usb0_pipe_clk = { 2458 .halt_reg = 0x2c054, 2459 .halt_check = BRANCH_HALT_DELAY, 2460 .clkr = { 2461 .enable_reg = 0x2c054, 2462 .enable_mask = BIT(0), 2463 .hw.init = &(const struct clk_init_data) { 2464 .name = "gcc_usb0_pipe_clk", 2465 .parent_hws = (const struct clk_hw *[]) { 2466 &gcc_usb0_pipe_clk_src.clkr.hw 2467 }, 2468 .num_parents = 1, 2469 .flags = CLK_SET_RATE_PARENT, 2470 .ops = &clk_branch2_ops, 2471 }, 2472 }, 2473 }; 2474 2475 static struct clk_branch gcc_usb0_sleep_clk = { 2476 .halt_reg = 0x2c058, 2477 .halt_check = BRANCH_HALT_VOTED, 2478 .clkr = { 2479 .enable_reg = 0x2c058, 2480 .enable_mask = BIT(0), 2481 .hw.init = &(const struct clk_init_data) { 2482 .name = "gcc_usb0_sleep_clk", 2483 .parent_hws = (const struct clk_hw*[]) { 2484 &gcc_sleep_clk_src.clkr.hw, 2485 }, 2486 .num_parents = 1, 2487 .flags = CLK_SET_RATE_PARENT, 2488 .ops = &clk_branch2_ops, 2489 }, 2490 }, 2491 }; 2492 2493 static struct clk_branch gcc_usb1_sleep_clk = { 2494 .halt_reg = 0x3c020, 2495 .halt_check = BRANCH_HALT_VOTED, 2496 .clkr = { 2497 .enable_reg = 0x3c020, 2498 .enable_mask = BIT(0), 2499 .hw.init = &(const struct clk_init_data) { 2500 .name = "gcc_usb1_sleep_clk", 2501 .parent_hws = (const struct clk_hw*[]) { 2502 &gcc_sleep_clk_src.clkr.hw, 2503 }, 2504 .num_parents = 1, 2505 .flags = CLK_SET_RATE_PARENT, 2506 .ops = &clk_branch2_ops, 2507 }, 2508 }, 2509 }; 2510 2511 static struct clk_branch gcc_cmn_12gpll_ahb_clk = { 2512 .halt_reg = 0x3a004, 2513 .halt_check = BRANCH_HALT, 2514 .clkr = { 2515 .enable_reg = 0x3a004, 2516 .enable_mask = BIT(0), 2517 .hw.init = &(const struct clk_init_data) { 2518 .name = "gcc_cmn_12gpll_ahb_clk", 2519 .parent_hws = (const struct clk_hw*[]) { 2520 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2521 }, 2522 .num_parents = 1, 2523 .flags = CLK_SET_RATE_PARENT, 2524 .ops = &clk_branch2_ops, 2525 }, 2526 }, 2527 }; 2528 2529 static struct clk_branch gcc_cmn_12gpll_sys_clk = { 2530 .halt_reg = 0x3a008, 2531 .halt_check = BRANCH_HALT, 2532 .clkr = { 2533 .enable_reg = 0x3a008, 2534 .enable_mask = BIT(0), 2535 .hw.init = &(const struct clk_init_data) { 2536 .name = "gcc_cmn_12gpll_sys_clk", 2537 .parent_hws = (const struct clk_hw*[]) { 2538 &gcc_uniphy_sys_clk_src.clkr.hw, 2539 }, 2540 .num_parents = 1, 2541 .flags = CLK_SET_RATE_PARENT, 2542 .ops = &clk_branch2_ops, 2543 }, 2544 }, 2545 }; 2546 2547 static struct clk_branch gcc_lpass_sway_clk = { 2548 .halt_reg = 0x27014, 2549 .halt_check = BRANCH_HALT, 2550 .clkr = { 2551 .enable_reg = 0x27014, 2552 .enable_mask = BIT(0), 2553 .hw.init = &(const struct clk_init_data) { 2554 .name = "gcc_lpass_sway_clk", 2555 .parent_hws = (const struct clk_hw*[]) { 2556 &gcc_lpass_sway_clk_src.clkr.hw, 2557 }, 2558 .num_parents = 1, 2559 .flags = CLK_SET_RATE_PARENT, 2560 .ops = &clk_branch2_ops, 2561 }, 2562 }, 2563 }; 2564 2565 static struct clk_branch gcc_cnoc_lpass_cfg_clk = { 2566 .halt_reg = 0x2e028, 2567 .halt_check = BRANCH_HALT, 2568 .clkr = { 2569 .enable_reg = 0x2e028, 2570 .enable_mask = BIT(0), 2571 .hw.init = &(const struct clk_init_data) { 2572 .name = "gcc_cnoc_lpass_cfg_clk", 2573 .parent_hws = (const struct clk_hw*[]) { 2574 &gcc_lpass_sway_clk_src.clkr.hw, 2575 }, 2576 .num_parents = 1, 2577 .flags = CLK_SET_RATE_PARENT, 2578 .ops = &clk_branch2_ops, 2579 }, 2580 }, 2581 }; 2582 2583 static struct clk_branch gcc_lpass_core_axim_clk = { 2584 .halt_reg = 0x27018, 2585 .halt_check = BRANCH_HALT_VOTED, 2586 .clkr = { 2587 .enable_reg = 0x27018, 2588 .enable_mask = BIT(0), 2589 .hw.init = &(const struct clk_init_data) { 2590 .name = "gcc_lpass_core_axim_clk", 2591 .parent_hws = (const struct clk_hw*[]) { 2592 &gcc_lpass_axim_clk_src.clkr.hw, 2593 }, 2594 .num_parents = 1, 2595 .flags = CLK_SET_RATE_PARENT, 2596 .ops = &clk_branch2_ops, 2597 }, 2598 }, 2599 }; 2600 2601 static struct clk_branch gcc_snoc_lpass_clk = { 2602 .halt_reg = 0x31020, 2603 .halt_check = BRANCH_HALT_VOTED, 2604 .clkr = { 2605 .enable_reg = 0x31020, 2606 .enable_mask = BIT(0), 2607 .hw.init = &(const struct clk_init_data) { 2608 .name = "gcc_snoc_lpass_clk", 2609 .parent_hws = (const struct clk_hw*[]) { 2610 &gcc_lpass_axim_clk_src.clkr.hw, 2611 }, 2612 .num_parents = 1, 2613 .flags = CLK_SET_RATE_PARENT, 2614 .ops = &clk_branch2_ops, 2615 }, 2616 }, 2617 }; 2618 2619 static struct clk_branch gcc_usb0_eud_at_clk = { 2620 .halt_reg = 0x30004, 2621 .halt_check = BRANCH_HALT_VOTED, 2622 .clkr = { 2623 .enable_reg = 0x30004, 2624 .enable_mask = BIT(0), 2625 .hw.init = &(const struct clk_init_data) { 2626 .name = "gcc_usb0_eud_at_clk", 2627 .parent_hws = (const struct clk_hw*[]) { 2628 &gcc_eud_at_div_clk_src.hw, 2629 }, 2630 .num_parents = 1, 2631 .flags = CLK_SET_RATE_PARENT, 2632 .ops = &clk_branch2_ops, 2633 }, 2634 }, 2635 }; 2636 2637 static struct clk_branch gcc_qpic_ahb_clk = { 2638 .halt_reg = 0x32010, 2639 .halt_check = BRANCH_HALT, 2640 .clkr = { 2641 .enable_reg = 0x32010, 2642 .enable_mask = BIT(0), 2643 .hw.init = &(const struct clk_init_data) { 2644 .name = "gcc_qpic_ahb_clk", 2645 .parent_hws = (const struct clk_hw*[]) { 2646 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2647 }, 2648 .num_parents = 1, 2649 .flags = CLK_SET_RATE_PARENT, 2650 .ops = &clk_branch2_ops, 2651 }, 2652 }, 2653 }; 2654 2655 static struct clk_branch gcc_qpic_clk = { 2656 .halt_reg = 0x32028, 2657 .halt_check = BRANCH_HALT, 2658 .clkr = { 2659 .enable_reg = 0x32028, 2660 .enable_mask = BIT(0), 2661 .hw.init = &(const struct clk_init_data) { 2662 .name = "gcc_qpic_clk", 2663 .parent_hws = (const struct clk_hw*[]) { 2664 &gcc_qpic_clk_src.clkr.hw, 2665 }, 2666 .num_parents = 1, 2667 .flags = CLK_SET_RATE_PARENT, 2668 .ops = &clk_branch2_ops, 2669 }, 2670 }, 2671 }; 2672 2673 static struct clk_branch gcc_qpic_io_macro_clk = { 2674 .halt_reg = 0x3200c, 2675 .halt_check = BRANCH_HALT, 2676 .clkr = { 2677 .enable_reg = 0x3200c, 2678 .enable_mask = BIT(0), 2679 .hw.init = &(const struct clk_init_data) { 2680 .name = "gcc_qpic_io_macro_clk", 2681 .parent_hws = (const struct clk_hw*[]) { 2682 &gcc_qpic_io_macro_clk_src.clkr.hw, 2683 }, 2684 .num_parents = 1, 2685 .flags = CLK_SET_RATE_PARENT, 2686 .ops = &clk_branch2_ops, 2687 }, 2688 }, 2689 }; 2690 2691 static struct clk_branch gcc_qdss_dap_clk = { 2692 .halt_reg = 0x2d058, 2693 .clkr = { 2694 .enable_reg = 0x2d058, 2695 .enable_mask = BIT(0), 2696 .hw.init = &(const struct clk_init_data) { 2697 .name = "gcc_qdss_dap_clk", 2698 .parent_hws = (const struct clk_hw *[]) { 2699 &gcc_qdss_dap_sync_clk_src.hw 2700 }, 2701 .num_parents = 1, 2702 .flags = CLK_SET_RATE_PARENT, 2703 .ops = &clk_branch2_ops, 2704 }, 2705 }, 2706 }; 2707 2708 static struct clk_branch gcc_qdss_at_clk = { 2709 .halt_reg = 0x2d034, 2710 .clkr = { 2711 .enable_reg = 0x2d034, 2712 .enable_mask = BIT(0), 2713 .hw.init = &(const struct clk_init_data) { 2714 .name = "gcc_qdss_at_clk", 2715 .parent_hws = (const struct clk_hw *[]) { 2716 &gcc_qdss_at_clk_src.clkr.hw 2717 }, 2718 .num_parents = 1, 2719 .flags = CLK_SET_RATE_PARENT, 2720 .ops = &clk_branch2_ops, 2721 }, 2722 }, 2723 }; 2724 2725 static struct clk_branch gcc_pcie0_rchng_clk = { 2726 .halt_reg = 0x28028, 2727 .clkr = { 2728 .enable_reg = 0x28028, 2729 .enable_mask = BIT(1), 2730 .hw.init = &(const struct clk_init_data) { 2731 .name = "gcc_pcie0_rchng_clk", 2732 .parent_hws = (const struct clk_hw *[]) { 2733 &gcc_pcie0_rchng_clk_src.clkr.hw 2734 }, 2735 .num_parents = 1, 2736 .flags = CLK_SET_RATE_PARENT, 2737 .ops = &clk_branch2_ops, 2738 }, 2739 }, 2740 }; 2741 2742 static struct clk_branch gcc_pcie1_rchng_clk = { 2743 .halt_reg = 0x29028, 2744 .clkr = { 2745 .enable_reg = 0x29028, 2746 .enable_mask = BIT(1), 2747 .hw.init = &(const struct clk_init_data) { 2748 .name = "gcc_pcie1_rchng_clk", 2749 .parent_hws = (const struct clk_hw *[]) { 2750 &gcc_pcie1_rchng_clk_src.clkr.hw 2751 }, 2752 .num_parents = 1, 2753 .flags = CLK_SET_RATE_PARENT, 2754 .ops = &clk_branch2_ops, 2755 }, 2756 }, 2757 }; 2758 2759 static struct clk_branch gcc_pcie2_rchng_clk = { 2760 .halt_reg = 0x2a028, 2761 .clkr = { 2762 .enable_reg = 0x2a028, 2763 .enable_mask = BIT(1), 2764 .hw.init = &(const struct clk_init_data) { 2765 .name = "gcc_pcie2_rchng_clk", 2766 .parent_hws = (const struct clk_hw *[]) { 2767 &gcc_pcie2_rchng_clk_src.clkr.hw 2768 }, 2769 .num_parents = 1, 2770 .flags = CLK_SET_RATE_PARENT, 2771 .ops = &clk_branch2_ops, 2772 }, 2773 }, 2774 }; 2775 2776 static struct clk_branch gcc_pcie3_rchng_clk = { 2777 .halt_reg = 0x2b028, 2778 .clkr = { 2779 .enable_reg = 0x2b028, 2780 .enable_mask = BIT(1), 2781 .hw.init = &(const struct clk_init_data) { 2782 .name = "gcc_pcie3_rchng_clk", 2783 .parent_hws = (const struct clk_hw *[]) { 2784 &gcc_pcie3_rchng_clk_src.clkr.hw 2785 }, 2786 .num_parents = 1, 2787 .flags = CLK_SET_RATE_PARENT, 2788 .ops = &clk_branch2_ops, 2789 }, 2790 }, 2791 }; 2792 2793 static struct clk_regmap *gcc_ipq5424_clocks[] = { 2794 [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr, 2795 [GCC_ADSS_PWM_CLK_SRC] = &gcc_adss_pwm_clk_src.clkr, 2796 [GCC_CNOC_PCIE0_1LANE_S_CLK] = &gcc_cnoc_pcie0_1lane_s_clk.clkr, 2797 [GCC_CNOC_PCIE1_1LANE_S_CLK] = &gcc_cnoc_pcie1_1lane_s_clk.clkr, 2798 [GCC_CNOC_PCIE2_2LANE_S_CLK] = &gcc_cnoc_pcie2_2lane_s_clk.clkr, 2799 [GCC_CNOC_PCIE3_2LANE_S_CLK] = &gcc_cnoc_pcie3_2lane_s_clk.clkr, 2800 [GCC_CNOC_USB_CLK] = &gcc_cnoc_usb_clk.clkr, 2801 [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr, 2802 [GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr, 2803 [GCC_NSS_TS_CLK_SRC] = &gcc_nss_ts_clk_src.clkr, 2804 [GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr, 2805 [GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr, 2806 [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr, 2807 [GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr, 2808 [GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr, 2809 [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr, 2810 [GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr, 2811 [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr, 2812 [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr, 2813 [GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr, 2814 [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr, 2815 [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr, 2816 [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr, 2817 [GCC_PCIE0_AXI_M_CLK_SRC] = &gcc_pcie0_axi_m_clk_src.clkr, 2818 [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, 2819 [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr, 2820 [GCC_PCIE0_AXI_S_CLK_SRC] = &gcc_pcie0_axi_s_clk_src.clkr, 2821 [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr, 2822 [GCC_ANOC_PCIE0_1LANE_M_CLK] = &gcc_anoc_pcie0_1lane_m_clk.clkr, 2823 [GCC_PCIE0_PIPE_CLK_SRC] = &gcc_pcie0_pipe_clk_src.clkr, 2824 [GCC_PCIE0_RCHNG_CLK_SRC] = &gcc_pcie0_rchng_clk_src.clkr, 2825 [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr, 2826 [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr, 2827 [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr, 2828 [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr, 2829 [GCC_PCIE1_AXI_M_CLK_SRC] = &gcc_pcie1_axi_m_clk_src.clkr, 2830 [GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr, 2831 [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr, 2832 [GCC_PCIE1_AXI_S_CLK_SRC] = &gcc_pcie1_axi_s_clk_src.clkr, 2833 [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, 2834 [GCC_ANOC_PCIE1_1LANE_M_CLK] = &gcc_anoc_pcie1_1lane_m_clk.clkr, 2835 [GCC_PCIE1_PIPE_CLK_SRC] = &gcc_pcie1_pipe_clk_src.clkr, 2836 [GCC_PCIE1_RCHNG_CLK_SRC] = &gcc_pcie1_rchng_clk_src.clkr, 2837 [GCC_PCIE1_RCHNG_CLK] = &gcc_pcie1_rchng_clk.clkr, 2838 [GCC_PCIE2_AHB_CLK] = &gcc_pcie2_ahb_clk.clkr, 2839 [GCC_PCIE2_AUX_CLK] = &gcc_pcie2_aux_clk.clkr, 2840 [GCC_PCIE2_AXI_M_CLK] = &gcc_pcie2_axi_m_clk.clkr, 2841 [GCC_PCIE2_AXI_M_CLK_SRC] = &gcc_pcie2_axi_m_clk_src.clkr, 2842 [GCC_PCIE2_AXI_S_BRIDGE_CLK] = &gcc_pcie2_axi_s_bridge_clk.clkr, 2843 [GCC_PCIE2_AXI_S_CLK] = &gcc_pcie2_axi_s_clk.clkr, 2844 [GCC_PCIE2_AXI_S_CLK_SRC] = &gcc_pcie2_axi_s_clk_src.clkr, 2845 [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr, 2846 [GCC_ANOC_PCIE2_2LANE_M_CLK] = &gcc_anoc_pcie2_2lane_m_clk.clkr, 2847 [GCC_PCIE2_PIPE_CLK_SRC] = &gcc_pcie2_pipe_clk_src.clkr, 2848 [GCC_PCIE2_RCHNG_CLK_SRC] = &gcc_pcie2_rchng_clk_src.clkr, 2849 [GCC_PCIE2_RCHNG_CLK] = &gcc_pcie2_rchng_clk.clkr, 2850 [GCC_PCIE3_AHB_CLK] = &gcc_pcie3_ahb_clk.clkr, 2851 [GCC_PCIE3_AUX_CLK] = &gcc_pcie3_aux_clk.clkr, 2852 [GCC_PCIE3_AXI_M_CLK] = &gcc_pcie3_axi_m_clk.clkr, 2853 [GCC_PCIE3_AXI_M_CLK_SRC] = &gcc_pcie3_axi_m_clk_src.clkr, 2854 [GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr, 2855 [GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr, 2856 [GCC_PCIE3_AXI_S_CLK_SRC] = &gcc_pcie3_axi_s_clk_src.clkr, 2857 [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr, 2858 [GCC_ANOC_PCIE3_2LANE_M_CLK] = &gcc_anoc_pcie3_2lane_m_clk.clkr, 2859 [GCC_PCIE3_PIPE_CLK_SRC] = &gcc_pcie3_pipe_clk_src.clkr, 2860 [GCC_PCIE3_RCHNG_CLK_SRC] = &gcc_pcie3_rchng_clk_src.clkr, 2861 [GCC_PCIE3_RCHNG_CLK] = &gcc_pcie3_rchng_clk.clkr, 2862 [GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr, 2863 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 2864 [GCC_QUPV3_AHB_MST_CLK] = &gcc_qupv3_ahb_mst_clk.clkr, 2865 [GCC_QUPV3_AHB_SLV_CLK] = &gcc_qupv3_ahb_slv_clk.clkr, 2866 [GCC_QUPV3_I2C0_CLK] = &gcc_qupv3_i2c0_clk.clkr, 2867 [GCC_QUPV3_I2C0_CLK_SRC] = &gcc_qupv3_i2c0_clk_src.clkr, 2868 [GCC_QUPV3_I2C0_DIV_CLK_SRC] = &gcc_qupv3_i2c0_div_clk_src.clkr, 2869 [GCC_QUPV3_I2C1_CLK] = &gcc_qupv3_i2c1_clk.clkr, 2870 [GCC_QUPV3_I2C1_CLK_SRC] = &gcc_qupv3_i2c1_clk_src.clkr, 2871 [GCC_QUPV3_I2C1_DIV_CLK_SRC] = &gcc_qupv3_i2c1_div_clk_src.clkr, 2872 [GCC_QUPV3_SPI0_CLK] = &gcc_qupv3_spi0_clk.clkr, 2873 [GCC_QUPV3_SPI0_CLK_SRC] = &gcc_qupv3_spi0_clk_src.clkr, 2874 [GCC_QUPV3_SPI1_CLK] = &gcc_qupv3_spi1_clk.clkr, 2875 [GCC_QUPV3_SPI1_CLK_SRC] = &gcc_qupv3_spi1_clk_src.clkr, 2876 [GCC_QUPV3_UART0_CLK] = &gcc_qupv3_uart0_clk.clkr, 2877 [GCC_QUPV3_UART0_CLK_SRC] = &gcc_qupv3_uart0_clk_src.clkr, 2878 [GCC_QUPV3_UART1_CLK] = &gcc_qupv3_uart1_clk.clkr, 2879 [GCC_QUPV3_UART1_CLK_SRC] = &gcc_qupv3_uart1_clk_src.clkr, 2880 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2881 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2882 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 2883 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 2884 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 2885 [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr, 2886 [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr, 2887 [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr, 2888 [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr, 2889 [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr, 2890 [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr, 2891 [GCC_UNIPHY_SYS_CLK_SRC] = &gcc_uniphy_sys_clk_src.clkr, 2892 [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr, 2893 [GCC_USB0_AUX_CLK_SRC] = &gcc_usb0_aux_clk_src.clkr, 2894 [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr, 2895 [GCC_USB0_MASTER_CLK_SRC] = &gcc_usb0_master_clk_src.clkr, 2896 [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr, 2897 [GCC_USB0_MOCK_UTMI_CLK_SRC] = &gcc_usb0_mock_utmi_clk_src.clkr, 2898 [GCC_USB0_MOCK_UTMI_DIV_CLK_SRC] = &gcc_usb0_mock_utmi_div_clk_src.clkr, 2899 [GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr, 2900 [GCC_USB0_PIPE_CLK_SRC] = &gcc_usb0_pipe_clk_src.clkr, 2901 [GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr, 2902 [GCC_USB1_MOCK_UTMI_CLK_SRC] = &gcc_usb1_mock_utmi_clk_src.clkr, 2903 [GCC_USB1_MOCK_UTMI_DIV_CLK_SRC] = &gcc_usb1_mock_utmi_div_clk_src.clkr, 2904 [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr, 2905 [GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr, 2906 [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr, 2907 [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr, 2908 [GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr, 2909 [GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr, 2910 [GCC_WCSS_AHB_CLK_SRC] = &gcc_wcss_ahb_clk_src.clkr, 2911 [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr, 2912 [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr, 2913 [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr, 2914 [GCC_CNOC_LPASS_CFG_CLK] = &gcc_cnoc_lpass_cfg_clk.clkr, 2915 [GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr, 2916 [GCC_SNOC_LPASS_CLK] = &gcc_snoc_lpass_clk.clkr, 2917 [GCC_QDSS_AT_CLK_SRC] = &gcc_qdss_at_clk_src.clkr, 2918 [GCC_QDSS_TSCTR_CLK_SRC] = &gcc_qdss_tsctr_clk_src.clkr, 2919 [GCC_SYSTEM_NOC_BFDCD_CLK_SRC] = &gcc_system_noc_bfdcd_clk_src.clkr, 2920 [GCC_PCNOC_BFDCD_CLK_SRC] = &gcc_pcnoc_bfdcd_clk_src.clkr, 2921 [GCC_LPASS_SWAY_CLK_SRC] = &gcc_lpass_sway_clk_src.clkr, 2922 [GCC_LPASS_AXIM_CLK_SRC] = &gcc_lpass_axim_clk_src.clkr, 2923 [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr, 2924 [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr, 2925 [GCC_QPIC_IO_MACRO_CLK_SRC] = &gcc_qpic_io_macro_clk_src.clkr, 2926 [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr, 2927 [GCC_QPIC_CLK_SRC] = &gcc_qpic_clk_src.clkr, 2928 [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr, 2929 [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr, 2930 [GCC_XO_CLK] = &gcc_xo_clk.clkr, 2931 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, 2932 [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, 2933 [GPLL0] = &gpll0.clkr, 2934 [GPLL2] = &gpll2.clkr, 2935 [GPLL2_OUT_MAIN] = &gpll2_out_main.clkr, 2936 [GPLL4] = &gpll4.clkr, 2937 }; 2938 2939 static const struct qcom_reset_map gcc_ipq5424_resets[] = { 2940 [GCC_QUPV3_BCR] = { 0x01000, 0 }, 2941 [GCC_QUPV3_I2C0_BCR] = { 0x02000, 0 }, 2942 [GCC_QUPV3_UART0_BCR] = { 0x02020, 0 }, 2943 [GCC_QUPV3_I2C1_BCR] = { 0x03000, 0 }, 2944 [GCC_QUPV3_UART1_BCR] = { 0x03028, 0 }, 2945 [GCC_QUPV3_SPI0_BCR] = { 0x04000, 0 }, 2946 [GCC_QUPV3_SPI1_BCR] = { 0x05000, 0 }, 2947 [GCC_IMEM_BCR] = { 0x0e000, 0 }, 2948 [GCC_TME_BCR] = { 0x100000, 0 }, 2949 [GCC_DDRSS_BCR] = { 0x11000, 0 }, 2950 [GCC_PRNG_BCR] = { 0x13020, 0 }, 2951 [GCC_BOOT_ROM_BCR] = { 0x13028, 0 }, 2952 [GCC_NSS_BCR] = { 0x17000, 0 }, 2953 [GCC_MDIO_BCR] = { 0x1703c, 0 }, 2954 [GCC_UNIPHY0_BCR] = { 0x17044, 0 }, 2955 [GCC_UNIPHY1_BCR] = { 0x17054, 0 }, 2956 [GCC_UNIPHY2_BCR] = { 0x17064, 0 }, 2957 [GCC_WCSS_BCR] = { 0x18004, 0 }, 2958 [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 }, 2959 [GCC_TME_SEC_BUS_BCR] = { 0xa1030, 0 }, 2960 [GCC_ADSS_BCR] = { 0x1c000, 0 }, 2961 [GCC_LPASS_BCR] = { 0x27000, 0 }, 2962 [GCC_PCIE0_BCR] = { 0x28000, 0 }, 2963 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054, 0 }, 2964 [GCC_PCIE0PHY_PHY_BCR] = { 0x2805c, 0 }, 2965 [GCC_PCIE0_PHY_BCR] = { 0x28060, 0 }, 2966 [GCC_PCIE1_BCR] = { 0x29000, 0 }, 2967 [GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054, 0 }, 2968 [GCC_PCIE1PHY_PHY_BCR] = { 0x2905c, 0 }, 2969 [GCC_PCIE1_PHY_BCR] = { 0x29060, 0 }, 2970 [GCC_PCIE2_BCR] = { 0x2a000, 0 }, 2971 [GCC_PCIE2_LINK_DOWN_BCR] = { 0x2a054, 0 }, 2972 [GCC_PCIE2PHY_PHY_BCR] = { 0x2a05c, 0 }, 2973 [GCC_PCIE2_PHY_BCR] = { 0x2a060, 0 }, 2974 [GCC_PCIE3_BCR] = { 0x2b000, 0 }, 2975 [GCC_PCIE3_LINK_DOWN_BCR] = { 0x2b054, 0 }, 2976 [GCC_PCIE3PHY_PHY_BCR] = { 0x2b05c, 0 }, 2977 [GCC_PCIE3_PHY_BCR] = { 0x2b060, 0 }, 2978 [GCC_USB_BCR] = { 0x2c000, 0 }, 2979 [GCC_QUSB2_0_PHY_BCR] = { 0x2c068, 0 }, 2980 [GCC_USB0_PHY_BCR] = { 0x2c06c, 0 }, 2981 [GCC_USB3PHY_0_PHY_BCR] = { 0x2c070, 0 }, 2982 [GCC_QDSS_BCR] = { 0x2d000, 0 }, 2983 [GCC_SNOC_BCR] = { 0x2e000, 0 }, 2984 [GCC_ANOC_BCR] = { 0x2e074, 0 }, 2985 [GCC_PCNOC_BCR] = { 0x31000, 0 }, 2986 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x31030, 0 }, 2987 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x31038, 0 }, 2988 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x31040, 0 }, 2989 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x31048, 0 }, 2990 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x31050, 0 }, 2991 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x31058, 0 }, 2992 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x31060, 0 }, 2993 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x31068, 0 }, 2994 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x31070, 0 }, 2995 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x31078, 0 }, 2996 [GCC_QPIC_BCR] = { 0x32000, 0 }, 2997 [GCC_SDCC_BCR] = { 0x33000, 0 }, 2998 [GCC_DCC_BCR] = { 0x35000, 0 }, 2999 [GCC_SPDM_BCR] = { 0x36000, 0 }, 3000 [GCC_MPM_BCR] = { 0x37000, 0 }, 3001 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000, 0 }, 3002 [GCC_RBCPR_BCR] = { 0x39000, 0 }, 3003 [GCC_CMN_BLK_BCR] = { 0x3a000, 0 }, 3004 [GCC_TCSR_BCR] = { 0x3d000, 0 }, 3005 [GCC_TLMM_BCR] = { 0x3e000, 0 }, 3006 [GCC_QUPV3_AHB_MST_ARES] = { 0x01014, 2 }, 3007 [GCC_QUPV3_CORE_ARES] = { 0x01018, 2 }, 3008 [GCC_QUPV3_2X_CORE_ARES] = { 0x01020, 2 }, 3009 [GCC_QUPV3_SLEEP_ARES] = { 0x01028, 2 }, 3010 [GCC_QUPV3_AHB_SLV_ARES] = { 0x0102c, 2 }, 3011 [GCC_QUPV3_I2C0_ARES] = { 0x02024, 2 }, 3012 [GCC_QUPV3_UART0_ARES] = { 0x02040, 2 }, 3013 [GCC_QUPV3_I2C1_ARES] = { 0x03024, 2 }, 3014 [GCC_QUPV3_UART1_ARES] = { 0x03040, 2 }, 3015 [GCC_QUPV3_SPI0_ARES] = { 0x04020, 2 }, 3016 [GCC_QUPV3_SPI1_ARES] = { 0x05020, 2 }, 3017 [GCC_DEBUG_ARES] = { 0x06068, 2 }, 3018 [GCC_GP1_ARES] = { 0x08018, 2 }, 3019 [GCC_GP2_ARES] = { 0x09018, 2 }, 3020 [GCC_GP3_ARES] = { 0x0a018, 2 }, 3021 [GCC_IMEM_AXI_ARES] = { 0x0e004, 2 }, 3022 [GCC_IMEM_CFG_AHB_ARES] = { 0x0e00c, 2 }, 3023 [GCC_TME_ARES] = { 0x100b4, 2 }, 3024 [GCC_TME_TS_ARES] = { 0x100c0, 2 }, 3025 [GCC_TME_SLOW_ARES] = { 0x100d0, 2 }, 3026 [GCC_TME_RTC_TOGGLE_ARES] = { 0x100d8, 2 }, 3027 [GCC_TIC_ARES] = { 0x12004, 2 }, 3028 [GCC_PRNG_AHB_ARES] = { 0x13024, 2 }, 3029 [GCC_BOOT_ROM_AHB_ARES] = { 0x1302c, 2 }, 3030 [GCC_NSSNOC_ATB_ARES] = { 0x17014, 2 }, 3031 [GCC_NSS_TS_ARES] = { 0x17018, 2 }, 3032 [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x1701c, 2 }, 3033 [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17020, 2 }, 3034 [GCC_NSSNOC_MEMNOC_ARES] = { 0x17024, 2 }, 3035 [GCC_NSSNOC_SNOC_ARES] = { 0x17028, 2 }, 3036 [GCC_NSSCFG_ARES] = { 0x1702c, 2 }, 3037 [GCC_NSSNOC_NSSCC_ARES] = { 0x17030, 2 }, 3038 [GCC_NSSCC_ARES] = { 0x17034, 2 }, 3039 [GCC_MDIO_AHB_ARES] = { 0x17040, 2 }, 3040 [GCC_UNIPHY0_SYS_ARES] = { 0x17048, 2 }, 3041 [GCC_UNIPHY0_AHB_ARES] = { 0x1704c, 2 }, 3042 [GCC_UNIPHY1_SYS_ARES] = { 0x17058, 2 }, 3043 [GCC_UNIPHY1_AHB_ARES] = { 0x1705c, 2 }, 3044 [GCC_UNIPHY2_SYS_ARES] = { 0x17068, 2 }, 3045 [GCC_UNIPHY2_AHB_ARES] = { 0x1706c, 2 }, 3046 [GCC_NSSNOC_XO_DCD_ARES] = { 0x17074, 2 }, 3047 [GCC_NSSNOC_SNOC_1_ARES] = { 0x1707c, 2 }, 3048 [GCC_NSSNOC_PCNOC_1_ARES] = { 0x17080, 2 }, 3049 [GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17084, 2 }, 3050 [GCC_DDRSS_ATB_ARES] = { 0x19004, 2 }, 3051 [GCC_DDRSS_AHB_ARES] = { 0x19008, 2 }, 3052 [GCC_GEMNOC_AHB_ARES] = { 0x1900c, 2 }, 3053 [GCC_GEMNOC_Q6_AXI_ARES] = { 0x19010, 2 }, 3054 [GCC_GEMNOC_NSSNOC_ARES] = { 0x19014, 2 }, 3055 [GCC_GEMNOC_SNOC_ARES] = { 0x19018, 2 }, 3056 [GCC_GEMNOC_APSS_ARES] = { 0x1901c, 2 }, 3057 [GCC_GEMNOC_QOSGEN_EXTREF_ARES] = { 0x19024, 2 }, 3058 [GCC_GEMNOC_TS_ARES] = { 0x19028, 2 }, 3059 [GCC_DDRSS_SMS_SLOW_ARES] = { 0x1902c, 2 }, 3060 [GCC_GEMNOC_CNOC_ARES] = { 0x19038, 2 }, 3061 [GCC_GEMNOC_XO_DBG_ARES] = { 0x19040, 2 }, 3062 [GCC_GEMNOC_ANOC_ARES] = { 0x19048, 2 }, 3063 [GCC_DDRSS_LLCC_ATB_ARES] = { 0x1904c, 2 }, 3064 [GCC_LLCC_TPDM_CFG_ARES] = { 0x19050, 2 }, 3065 [GCC_TME_BUS_ARES] = { 0x1a014, 2 }, 3066 [GCC_SEC_CTRL_ACC_ARES] = { 0x1a018, 2 }, 3067 [GCC_SEC_CTRL_ARES] = { 0x1a020, 2 }, 3068 [GCC_SEC_CTRL_SENSE_ARES] = { 0x1a028, 2 }, 3069 [GCC_SEC_CTRL_AHB_ARES] = { 0x1a038, 2 }, 3070 [GCC_SEC_CTRL_BOOT_ROM_PATCH_ARES] = { 0x1a03c, 2 }, 3071 [GCC_ADSS_PWM_ARES] = { 0x1c00c, 2 }, 3072 [GCC_TME_ATB_ARES] = { 0x1e030, 2 }, 3073 [GCC_TME_DBGAPB_ARES] = { 0x1e034, 2 }, 3074 [GCC_TME_DEBUG_ARES] = { 0x1e038, 2 }, 3075 [GCC_TME_AT_ARES] = { 0x1e03C, 2 }, 3076 [GCC_TME_APB_ARES] = { 0x1e040, 2 }, 3077 [GCC_TME_DMI_DBG_HS_ARES] = { 0x1e044, 2 }, 3078 [GCC_APSS_AHB_ARES] = { 0x24014, 2 }, 3079 [GCC_APSS_AXI_ARES] = { 0x24018, 2 }, 3080 [GCC_CPUSS_TRIG_ARES] = { 0x2401c, 2 }, 3081 [GCC_APSS_DBG_ARES] = { 0x2402c, 2 }, 3082 [GCC_APSS_TS_ARES] = { 0x24030, 2 }, 3083 [GCC_APSS_ATB_ARES] = { 0x24034, 2 }, 3084 [GCC_Q6_AXIM_ARES] = { 0x2500c, 2 }, 3085 [GCC_Q6_AXIS_ARES] = { 0x25010, 2 }, 3086 [GCC_Q6_AHB_ARES] = { 0x25014, 2 }, 3087 [GCC_Q6_AHB_S_ARES] = { 0x25018, 2 }, 3088 [GCC_Q6SS_ATBM_ARES] = { 0x2501c, 2 }, 3089 [GCC_Q6_TSCTR_1TO2_ARES] = { 0x25020, 2 }, 3090 [GCC_Q6SS_PCLKDBG_ARES] = { 0x25024, 2 }, 3091 [GCC_Q6SS_TRIG_ARES] = { 0x25028, 2 }, 3092 [GCC_Q6SS_BOOT_CBCR_ARES] = { 0x2502c, 2 }, 3093 [GCC_WCSS_DBG_IFC_APB_ARES] = { 0x25038, 2 }, 3094 [GCC_WCSS_DBG_IFC_ATB_ARES] = { 0x2503c, 2 }, 3095 [GCC_WCSS_DBG_IFC_NTS_ARES] = { 0x25040, 2 }, 3096 [GCC_WCSS_DBG_IFC_DAPBUS_ARES] = { 0x25044, 2 }, 3097 [GCC_WCSS_DBG_IFC_APB_BDG_ARES] = { 0x25048, 2 }, 3098 [GCC_WCSS_DBG_IFC_NTS_BDG_ARES] = { 0x25050, 2 }, 3099 [GCC_WCSS_DBG_IFC_DAPBUS_BDG_ARES] = { 0x25054, 2 }, 3100 [GCC_WCSS_ECAHB_ARES] = { 0x25058, 2 }, 3101 [GCC_WCSS_ACMT_ARES] = { 0x2505c, 2 }, 3102 [GCC_WCSS_AHB_S_ARES] = { 0x25060, 2 }, 3103 [GCC_WCSS_AXI_M_ARES] = { 0x25064, 2 }, 3104 [GCC_PCNOC_WAPSS_ARES] = { 0x25080, 2 }, 3105 [GCC_SNOC_WAPSS_ARES] = { 0x25090, 2 }, 3106 [GCC_LPASS_SWAY_ARES] = { 0x27014, 2 }, 3107 [GCC_LPASS_CORE_AXIM_ARES] = { 0x27018, 2 }, 3108 [GCC_PCIE0_AHB_ARES] = { 0x28030, 2 }, 3109 [GCC_PCIE0_AXI_M_ARES] = { 0x28038, 2 }, 3110 [GCC_PCIE0_AXI_S_ARES] = { 0x28040, 2 }, 3111 [GCC_PCIE0_AXI_S_BRIDGE_ARES] = { 0x28048, 2}, 3112 [GCC_PCIE0_PIPE_ARES] = { 0x28068, 2}, 3113 [GCC_PCIE0_AUX_ARES] = { 0x28070, 2 }, 3114 [GCC_PCIE1_AHB_ARES] = { 0x29030, 2 }, 3115 [GCC_PCIE1_AXI_M_ARES] = { 0x29038, 2 }, 3116 [GCC_PCIE1_AXI_S_ARES] = { 0x29040, 2 }, 3117 [GCC_PCIE1_AXI_S_BRIDGE_ARES] = { 0x29048, 2 }, 3118 [GCC_PCIE1_PIPE_ARES] = { 0x29068, 2 }, 3119 [GCC_PCIE1_AUX_ARES] = { 0x29074, 2 }, 3120 [GCC_PCIE2_AHB_ARES] = { 0x2a030, 2 }, 3121 [GCC_PCIE2_AXI_M_ARES] = { 0x2a038, 2 }, 3122 [GCC_PCIE2_AXI_S_ARES] = { 0x2a040, 2 }, 3123 [GCC_PCIE2_AXI_S_BRIDGE_ARES] = { 0x2a048, 2 }, 3124 [GCC_PCIE2_PIPE_ARES] = { 0x2a068, 2 }, 3125 [GCC_PCIE2_AUX_ARES] = { 0x2a078, 2 }, 3126 [GCC_PCIE3_AHB_ARES] = { 0x2b030, 2 }, 3127 [GCC_PCIE3_AXI_M_ARES] = { 0x2b038, 2 }, 3128 [GCC_PCIE3_AXI_S_ARES] = { 0x2b040, 2 }, 3129 [GCC_PCIE3_AXI_S_BRIDGE_ARES] = { 0x2b048, 2 }, 3130 [GCC_PCIE3_PIPE_ARES] = { 0x2b068, 2 }, 3131 [GCC_PCIE3_AUX_ARES] = { 0x2b07C, 2 }, 3132 [GCC_USB0_MASTER_ARES] = { 0x2c044, 2 }, 3133 [GCC_USB0_AUX_ARES] = { 0x2c04c, 2 }, 3134 [GCC_USB0_MOCK_UTMI_ARES] = { 0x2c050, 2 }, 3135 [GCC_USB0_PIPE_ARES] = { 0x2c054, 2 }, 3136 [GCC_USB0_SLEEP_ARES] = { 0x2c058, 2 }, 3137 [GCC_USB0_PHY_CFG_AHB_ARES] = { 0x2c05c, 2 }, 3138 [GCC_QDSS_AT_ARES] = { 0x2d034, 2 }, 3139 [GCC_QDSS_STM_ARES] = { 0x2d03C, 2 }, 3140 [GCC_QDSS_TRACECLKIN_ARES] = { 0x2d040, 2 }, 3141 [GCC_QDSS_TSCTR_DIV2_ARES] = { 0x2d044, 2 }, 3142 [GCC_QDSS_TSCTR_DIV3_ARES] = { 0x2d048, 2 }, 3143 [GCC_QDSS_TSCTR_DIV4_ARES] = { 0x2d04c, 2 }, 3144 [GCC_QDSS_TSCTR_DIV8_ARES] = { 0x2d050, 2 }, 3145 [GCC_QDSS_TSCTR_DIV16_ARES] = { 0x2d054, 2 }, 3146 [GCC_QDSS_DAP_ARES] = { 0x2d058, 2 }, 3147 [GCC_QDSS_APB2JTAG_ARES] = { 0x2d05c, 2 }, 3148 [GCC_QDSS_ETR_USB_ARES] = { 0x2d060, 2 }, 3149 [GCC_QDSS_DAP_AHB_ARES] = { 0x2d064, 2 }, 3150 [GCC_QDSS_CFG_AHB_ARES] = { 0x2d068, 2 }, 3151 [GCC_QDSS_EUD_AT_ARES] = { 0x2d06c, 2 }, 3152 [GCC_QDSS_TS_ARES] = { 0x2d078, 2 }, 3153 [GCC_QDSS_USB_ARES] = { 0x2d07c, 2 }, 3154 [GCC_SYS_NOC_AXI_ARES] = { 0x2e01c, 2 }, 3155 [GCC_SNOC_QOSGEN_EXTREF_ARES] = { 0x2e020, 2 }, 3156 [GCC_CNOC_LPASS_CFG_ARES] = { 0x2e028, 2 }, 3157 [GCC_SYS_NOC_AT_ARES] = { 0x2e038, 2 }, 3158 [GCC_SNOC_PCNOC_AHB_ARES] = { 0x2e03c, 2 }, 3159 [GCC_SNOC_TME_ARES] = { 0x2e05c, 2 }, 3160 [GCC_SNOC_XO_DCD_ARES] = { 0x2e060, 2 }, 3161 [GCC_SNOC_TS_ARES] = { 0x2e068, 2 }, 3162 [GCC_ANOC0_AXI_ARES] = { 0x2e078, 2 }, 3163 [GCC_ANOC_PCIE0_1LANE_M_ARES] = { 0x2e07c, 2 }, 3164 [GCC_ANOC_PCIE2_2LANE_M_ARES] = { 0x2e080, 2 }, 3165 [GCC_ANOC_PCIE1_1LANE_M_ARES] = { 0x2e084, 2 }, 3166 [GCC_ANOC_PCIE3_2LANE_M_ARES] = { 0x2e090, 2 }, 3167 [GCC_ANOC_PCNOC_AHB_ARES] = { 0x2e094, 2 }, 3168 [GCC_ANOC_QOSGEN_EXTREF_ARES] = { 0x2e098, 2 }, 3169 [GCC_ANOC_XO_DCD_ARES] = { 0x2e09C, 2 }, 3170 [GCC_SNOC_XO_DBG_ARES] = { 0x2e0a0, 2 }, 3171 [GCC_AGGRNOC_ATB_ARES] = { 0x2e0ac, 2 }, 3172 [GCC_AGGRNOC_TS_ARES] = { 0x2e0b0, 2 }, 3173 [GCC_USB0_EUD_AT_ARES] = { 0x30004, 2 }, 3174 [GCC_PCNOC_TIC_ARES] = { 0x31014, 2 }, 3175 [GCC_PCNOC_AHB_ARES] = { 0x31018, 2 }, 3176 [GCC_PCNOC_XO_DBG_ARES] = { 0x3101c, 2 }, 3177 [GCC_SNOC_LPASS_ARES] = { 0x31020, 2 }, 3178 [GCC_PCNOC_AT_ARES] = { 0x31024, 2 }, 3179 [GCC_PCNOC_XO_DCD_ARES] = { 0x31028, 2 }, 3180 [GCC_PCNOC_TS_ARES] = { 0x3102c, 2 }, 3181 [GCC_PCNOC_BUS_TIMEOUT0_AHB_ARES] = { 0x31034, 2 }, 3182 [GCC_PCNOC_BUS_TIMEOUT1_AHB_ARES] = { 0x3103c, 2 }, 3183 [GCC_PCNOC_BUS_TIMEOUT2_AHB_ARES] = { 0x31044, 2 }, 3184 [GCC_PCNOC_BUS_TIMEOUT3_AHB_ARES] = { 0x3104c, 2 }, 3185 [GCC_PCNOC_BUS_TIMEOUT4_AHB_ARES] = { 0x31054, 2 }, 3186 [GCC_PCNOC_BUS_TIMEOUT5_AHB_ARES] = { 0x3105c, 2 }, 3187 [GCC_PCNOC_BUS_TIMEOUT6_AHB_ARES] = { 0x31064, 2 }, 3188 [GCC_PCNOC_BUS_TIMEOUT7_AHB_ARES] = { 0x3106c, 2 }, 3189 [GCC_Q6_AXIM_RESET] = { 0x2506c, 0 }, 3190 [GCC_Q6_AXIS_RESET] = { 0x2506c, 1 }, 3191 [GCC_Q6_AHB_S_RESET] = { 0x2506c, 2 }, 3192 [GCC_Q6_AHB_RESET] = { 0x2506c, 3 }, 3193 [GCC_Q6SS_DBG_RESET] = { 0x2506c, 4 }, 3194 [GCC_WCSS_ECAHB_RESET] = { 0x25070, 0 }, 3195 [GCC_WCSS_DBG_BDG_RESET] = { 0x25070, 1 }, 3196 [GCC_WCSS_DBG_RESET] = { 0x25070, 2 }, 3197 [GCC_WCSS_AXI_M_RESET] = { 0x25070, 3 }, 3198 [GCC_WCSS_AHB_S_RESET] = { 0x25070, 4 }, 3199 [GCC_WCSS_ACMT_RESET] = { 0x25070, 5 }, 3200 [GCC_WCSSAON_RESET] = { 0x25074, 0 }, 3201 [GCC_PCIE0_PIPE_RESET] = { 0x28058, 0 }, 3202 [GCC_PCIE0_CORE_STICKY_RESET] = { 0x28058, 1 }, 3203 [GCC_PCIE0_AXI_S_STICKY_RESET] = { 0x28058, 2 }, 3204 [GCC_PCIE0_AXI_S_RESET] = { 0x28058, 3 }, 3205 [GCC_PCIE0_AXI_M_STICKY_RESET] = { 0x28058, 4 }, 3206 [GCC_PCIE0_AXI_M_RESET] = { 0x28058, 5 }, 3207 [GCC_PCIE0_AUX_RESET] = { 0x28058, 6 }, 3208 [GCC_PCIE0_AHB_RESET] = { 0x28058, 7 }, 3209 [GCC_PCIE1_PIPE_RESET] = { 0x29058, 0 }, 3210 [GCC_PCIE1_CORE_STICKY_RESET] = { 0x29058, 1 }, 3211 [GCC_PCIE1_AXI_S_STICKY_RESET] = { 0x29058, 2 }, 3212 [GCC_PCIE1_AXI_S_RESET] = { 0x29058, 3 }, 3213 [GCC_PCIE1_AXI_M_STICKY_RESET] = { 0x29058, 4 }, 3214 [GCC_PCIE1_AXI_M_RESET] = { 0x29058, 5 }, 3215 [GCC_PCIE1_AUX_RESET] = { 0x29058, 6 }, 3216 [GCC_PCIE1_AHB_RESET] = { 0x29058, 7 }, 3217 [GCC_PCIE2_PIPE_RESET] = { 0x2a058, 0 }, 3218 [GCC_PCIE2_CORE_STICKY_RESET] = { 0x2a058, 1 }, 3219 [GCC_PCIE2_AXI_S_STICKY_RESET] = { 0x2a058, 2 }, 3220 [GCC_PCIE2_AXI_S_RESET] = { 0x2a058, 3 }, 3221 [GCC_PCIE2_AXI_M_STICKY_RESET] = { 0x2a058, 4 }, 3222 [GCC_PCIE2_AXI_M_RESET] = { 0x2a058, 5 }, 3223 [GCC_PCIE2_AUX_RESET] = { 0x2a058, 6 }, 3224 [GCC_PCIE2_AHB_RESET] = { 0x2a058, 7 }, 3225 [GCC_PCIE3_PIPE_RESET] = { 0x2b058, 0 }, 3226 [GCC_PCIE3_CORE_STICKY_RESET] = { 0x2b058, 1 }, 3227 [GCC_PCIE3_AXI_S_STICKY_RESET] = { 0x2b058, 2 }, 3228 [GCC_PCIE3_AXI_S_RESET] = { 0x2b058, 3 }, 3229 [GCC_PCIE3_AXI_M_STICKY_RESET] = { 0x2b058, 4 }, 3230 [GCC_PCIE3_AXI_M_RESET] = { 0x2b058, 5 }, 3231 [GCC_PCIE3_AUX_RESET] = { 0x2b058, 6 }, 3232 [GCC_PCIE3_AHB_RESET] = { 0x2b058, 7 }, 3233 [GCC_NSS_PARTIAL_RESET] = { 0x17078, 0 }, 3234 [GCC_UNIPHY0_XPCS_ARES] = { 0x17050, 2 }, 3235 [GCC_UNIPHY1_XPCS_ARES] = { 0x17060, 2 }, 3236 [GCC_UNIPHY2_XPCS_ARES] = { 0x17070, 2 }, 3237 [GCC_USB1_BCR] = { 0x3C000, 0 }, 3238 [GCC_QUSB2_1_PHY_BCR] = { 0x3C030, 0 }, 3239 }; 3240 3241 #define IPQ_APPS_ID 5424 /* some unique value */ 3242 3243 static const struct qcom_icc_hws_data icc_ipq5424_hws[] = { 3244 { MASTER_ANOC_PCIE0, SLAVE_ANOC_PCIE0, GCC_ANOC_PCIE0_1LANE_M_CLK }, 3245 { MASTER_CNOC_PCIE0, SLAVE_CNOC_PCIE0, GCC_CNOC_PCIE0_1LANE_S_CLK }, 3246 { MASTER_ANOC_PCIE1, SLAVE_ANOC_PCIE1, GCC_ANOC_PCIE1_1LANE_M_CLK }, 3247 { MASTER_CNOC_PCIE1, SLAVE_CNOC_PCIE1, GCC_CNOC_PCIE1_1LANE_S_CLK }, 3248 { MASTER_ANOC_PCIE2, SLAVE_ANOC_PCIE2, GCC_ANOC_PCIE2_2LANE_M_CLK }, 3249 { MASTER_CNOC_PCIE2, SLAVE_CNOC_PCIE2, GCC_CNOC_PCIE2_2LANE_S_CLK }, 3250 { MASTER_ANOC_PCIE3, SLAVE_ANOC_PCIE3, GCC_ANOC_PCIE3_2LANE_M_CLK }, 3251 { MASTER_CNOC_PCIE3, SLAVE_CNOC_PCIE3, GCC_CNOC_PCIE3_2LANE_S_CLK }, 3252 { MASTER_CNOC_USB, SLAVE_CNOC_USB, GCC_CNOC_USB_CLK }, 3253 }; 3254 3255 static const struct of_device_id gcc_ipq5424_match_table[] = { 3256 { .compatible = "qcom,ipq5424-gcc" }, 3257 { } 3258 }; 3259 MODULE_DEVICE_TABLE(of, gcc_ipq5424_match_table); 3260 3261 static const struct regmap_config gcc_ipq5424_regmap_config = { 3262 .reg_bits = 32, 3263 .reg_stride = 4, 3264 .val_bits = 32, 3265 .max_register = 0x3f024, 3266 .fast_io = true, 3267 }; 3268 3269 static struct clk_hw *gcc_ipq5424_hws[] = { 3270 &gpll0_div2.hw, 3271 &gcc_xo_div4_clk_src.hw, 3272 &gcc_qdss_tsctr_div2_clk_src.hw, 3273 &gcc_qdss_dap_sync_clk_src.hw, 3274 &gcc_eud_at_div_clk_src.hw, 3275 }; 3276 3277 static const struct qcom_cc_desc gcc_ipq5424_desc = { 3278 .config = &gcc_ipq5424_regmap_config, 3279 .clks = gcc_ipq5424_clocks, 3280 .num_clks = ARRAY_SIZE(gcc_ipq5424_clocks), 3281 .resets = gcc_ipq5424_resets, 3282 .num_resets = ARRAY_SIZE(gcc_ipq5424_resets), 3283 .clk_hws = gcc_ipq5424_hws, 3284 .num_clk_hws = ARRAY_SIZE(gcc_ipq5424_hws), 3285 .icc_hws = icc_ipq5424_hws, 3286 .num_icc_hws = ARRAY_SIZE(icc_ipq5424_hws), 3287 }; 3288 3289 static int gcc_ipq5424_probe(struct platform_device *pdev) 3290 { 3291 return qcom_cc_probe(pdev, &gcc_ipq5424_desc); 3292 } 3293 3294 static struct platform_driver gcc_ipq5424_driver = { 3295 .probe = gcc_ipq5424_probe, 3296 .driver = { 3297 .name = "qcom,gcc-ipq5424", 3298 .of_match_table = gcc_ipq5424_match_table, 3299 .sync_state = icc_sync_state, 3300 }, 3301 }; 3302 3303 static int __init gcc_ipq5424_init(void) 3304 { 3305 return platform_driver_register(&gcc_ipq5424_driver); 3306 } 3307 core_initcall(gcc_ipq5424_init); 3308 3309 static void __exit gcc_ipq5424_exit(void) 3310 { 3311 platform_driver_unregister(&gcc_ipq5424_driver); 3312 } 3313 module_exit(gcc_ipq5424_exit); 3314 3315 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ5424 Driver"); 3316 MODULE_LICENSE("GPL"); 3317