1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/interconnect-provider.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,ipq5332-gcc.h> 13 #include <dt-bindings/interconnect/qcom,ipq5332.h> 14 15 #include "clk-alpha-pll.h" 16 #include "clk-branch.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "clk-regmap-divider.h" 20 #include "clk-regmap-mux.h" 21 #include "clk-regmap-phy-mux.h" 22 #include "reset.h" 23 24 enum { 25 DT_XO, 26 DT_SLEEP_CLK, 27 DT_PCIE_2LANE_PHY_PIPE_CLK, 28 DT_PCIE_2LANE_PHY_PIPE_CLK_X1, 29 DT_USB_PCIE_WRAPPER_PIPE_CLK, 30 }; 31 32 enum { 33 P_PCIE3X2_PIPE, 34 P_PCIE3X1_0_PIPE, 35 P_PCIE3X1_1_PIPE, 36 P_USB3PHY_0_PIPE, 37 P_CORE_BI_PLL_TEST_SE, 38 P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 39 P_GPLL0_OUT_AUX, 40 P_GPLL0_OUT_MAIN, 41 P_GPLL2_OUT_AUX, 42 P_GPLL2_OUT_MAIN, 43 P_GPLL4_OUT_AUX, 44 P_GPLL4_OUT_MAIN, 45 P_SLEEP_CLK, 46 P_XO, 47 }; 48 49 static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO }; 50 51 static struct clk_alpha_pll gpll0_main = { 52 .offset = 0x20000, 53 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], 54 .clkr = { 55 .enable_reg = 0xb000, 56 .enable_mask = BIT(0), 57 .hw.init = &(const struct clk_init_data) { 58 .name = "gpll0_main", 59 .parent_data = &gcc_parent_data_xo, 60 .num_parents = 1, 61 .ops = &clk_alpha_pll_stromer_ops, 62 }, 63 }, 64 }; 65 66 static struct clk_fixed_factor gpll0_div2 = { 67 .mult = 1, 68 .div = 2, 69 .hw.init = &(struct clk_init_data) { 70 .name = "gpll0_div2", 71 .parent_hws = (const struct clk_hw *[]) { 72 &gpll0_main.clkr.hw }, 73 .num_parents = 1, 74 .ops = &clk_fixed_factor_ops, 75 }, 76 }; 77 78 static struct clk_alpha_pll_postdiv gpll0 = { 79 .offset = 0x20000, 80 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], 81 .width = 4, 82 .clkr.hw.init = &(struct clk_init_data) { 83 .name = "gpll0", 84 .parent_hws = (const struct clk_hw *[]) { 85 &gpll0_main.clkr.hw }, 86 .num_parents = 1, 87 .ops = &clk_alpha_pll_postdiv_ro_ops, 88 }, 89 }; 90 91 static struct clk_alpha_pll gpll2_main = { 92 .offset = 0x21000, 93 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], 94 .clkr = { 95 .enable_reg = 0xb000, 96 .enable_mask = BIT(1), 97 .hw.init = &(const struct clk_init_data) { 98 .name = "gpll2", 99 .parent_data = &gcc_parent_data_xo, 100 .num_parents = 1, 101 .ops = &clk_alpha_pll_stromer_ops, 102 }, 103 }, 104 }; 105 106 static struct clk_alpha_pll_postdiv gpll2 = { 107 .offset = 0x21000, 108 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], 109 .width = 4, 110 .clkr.hw.init = &(struct clk_init_data) { 111 .name = "gpll2_main", 112 .parent_hws = (const struct clk_hw *[]) { 113 &gpll2_main.clkr.hw }, 114 .num_parents = 1, 115 .ops = &clk_alpha_pll_postdiv_ro_ops, 116 }, 117 }; 118 119 static struct clk_alpha_pll gpll4_main = { 120 .offset = 0x22000, 121 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], 122 .clkr = { 123 .enable_reg = 0xb000, 124 .enable_mask = BIT(2), 125 .hw.init = &(const struct clk_init_data) { 126 .name = "gpll4_main", 127 .parent_data = &gcc_parent_data_xo, 128 .num_parents = 1, 129 .ops = &clk_alpha_pll_stromer_ops, 130 }, 131 }, 132 }; 133 134 static struct clk_alpha_pll_postdiv gpll4 = { 135 .offset = 0x22000, 136 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], 137 .width = 4, 138 .clkr.hw.init = &(struct clk_init_data) { 139 .name = "gpll4", 140 .parent_hws = (const struct clk_hw *[]) { 141 &gpll4_main.clkr.hw }, 142 .num_parents = 1, 143 .ops = &clk_alpha_pll_postdiv_ro_ops, 144 }, 145 }; 146 147 static const struct parent_map gcc_parent_map_xo[] = { 148 { P_XO, 0 }, 149 }; 150 151 static const struct parent_map gcc_parent_map_0[] = { 152 { P_XO, 0 }, 153 { P_GPLL0_OUT_MAIN, 1 }, 154 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 155 }; 156 157 static const struct clk_parent_data gcc_parent_data_0[] = { 158 { .index = DT_XO }, 159 { .hw = &gpll0.clkr.hw }, 160 { .hw = &gpll0_div2.hw }, 161 }; 162 163 static const struct parent_map gcc_parent_map_1[] = { 164 { P_XO, 0 }, 165 { P_GPLL0_OUT_MAIN, 1 }, 166 }; 167 168 static const struct clk_parent_data gcc_parent_data_1[] = { 169 { .index = DT_XO }, 170 { .hw = &gpll0.clkr.hw }, 171 }; 172 173 static const struct parent_map gcc_parent_map_2[] = { 174 { P_XO, 0 }, 175 { P_GPLL0_OUT_MAIN, 1 }, 176 { P_GPLL4_OUT_MAIN, 2 }, 177 }; 178 179 static const struct clk_parent_data gcc_parent_data_2[] = { 180 { .index = DT_XO }, 181 { .hw = &gpll0.clkr.hw }, 182 { .hw = &gpll4.clkr.hw }, 183 }; 184 185 static const struct parent_map gcc_parent_map_3[] = { 186 { P_XO, 0 }, 187 { P_GPLL0_OUT_MAIN, 1 }, 188 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 189 { P_SLEEP_CLK, 6 }, 190 }; 191 192 static const struct clk_parent_data gcc_parent_data_3[] = { 193 { .index = DT_XO }, 194 { .hw = &gpll0.clkr.hw }, 195 { .hw = &gpll0_div2.hw }, 196 { .index = DT_SLEEP_CLK }, 197 }; 198 199 static const struct parent_map gcc_parent_map_4[] = { 200 { P_XO, 0 }, 201 { P_GPLL4_OUT_MAIN, 1 }, 202 { P_GPLL0_OUT_AUX, 2 }, 203 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 204 }; 205 206 static const struct clk_parent_data gcc_parent_data_4[] = { 207 { .index = DT_XO }, 208 { .hw = &gpll4.clkr.hw }, 209 { .hw = &gpll0.clkr.hw }, 210 { .hw = &gpll0_div2.hw }, 211 }; 212 213 static const struct parent_map gcc_parent_map_5[] = { 214 { P_XO, 0 }, 215 { P_GPLL0_OUT_MAIN, 1 }, 216 { P_GPLL0_OUT_AUX, 2 }, 217 { P_SLEEP_CLK, 6 }, 218 }; 219 220 static const struct clk_parent_data gcc_parent_data_5[] = { 221 { .index = DT_XO }, 222 { .hw = &gpll0.clkr.hw }, 223 { .hw = &gpll0.clkr.hw }, 224 { .index = DT_SLEEP_CLK }, 225 }; 226 227 static const struct parent_map gcc_parent_map_6[] = { 228 { P_XO, 0 }, 229 { P_GPLL0_OUT_MAIN, 1 }, 230 { P_GPLL2_OUT_AUX, 2 }, 231 { P_GPLL4_OUT_AUX, 3 }, 232 { P_SLEEP_CLK, 6 }, 233 }; 234 235 static const struct clk_parent_data gcc_parent_data_6[] = { 236 { .index = DT_XO }, 237 { .hw = &gpll0.clkr.hw }, 238 { .hw = &gpll2.clkr.hw }, 239 { .hw = &gpll4.clkr.hw }, 240 { .index = DT_SLEEP_CLK }, 241 }; 242 243 static const struct parent_map gcc_parent_map_7[] = { 244 { P_XO, 0 }, 245 { P_GPLL0_OUT_MAIN, 1 }, 246 { P_GPLL2_OUT_AUX, 2 }, 247 }; 248 249 static const struct clk_parent_data gcc_parent_data_7[] = { 250 { .index = DT_XO }, 251 { .hw = &gpll0.clkr.hw }, 252 { .hw = &gpll2.clkr.hw }, 253 }; 254 255 static const struct parent_map gcc_parent_map_8[] = { 256 { P_XO, 0 }, 257 { P_GPLL0_OUT_MAIN, 1 }, 258 { P_GPLL2_OUT_MAIN, 2 }, 259 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 260 }; 261 262 static const struct clk_parent_data gcc_parent_data_8[] = { 263 { .index = DT_XO }, 264 { .hw = &gpll0.clkr.hw }, 265 { .hw = &gpll2.clkr.hw }, 266 { .hw = &gpll0_div2.hw }, 267 }; 268 269 static const struct parent_map gcc_parent_map_9[] = { 270 { P_SLEEP_CLK, 6 }, 271 }; 272 273 static const struct clk_parent_data gcc_parent_data_9[] = { 274 { .index = DT_SLEEP_CLK }, 275 }; 276 277 static const struct parent_map gcc_parent_map_10[] = { 278 { P_XO, 0 }, 279 { P_GPLL0_OUT_MAIN, 1 }, 280 { P_GPLL4_OUT_MAIN, 2 }, 281 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 3 }, 282 }; 283 284 static const struct clk_parent_data gcc_parent_data_10[] = { 285 { .index = DT_XO }, 286 { .hw = &gpll0.clkr.hw }, 287 { .hw = &gpll4.clkr.hw }, 288 { .hw = &gpll0_div2.hw }, 289 }; 290 291 static const struct parent_map gcc_parent_map_11[] = { 292 { P_XO, 0 }, 293 { P_GPLL0_OUT_AUX, 2 }, 294 { P_SLEEP_CLK, 6 }, 295 }; 296 297 static const struct clk_parent_data gcc_parent_data_11[] = { 298 { .index = DT_XO }, 299 { .hw = &gpll0.clkr.hw }, 300 { .index = DT_SLEEP_CLK }, 301 }; 302 303 static const struct parent_map gcc_parent_map_12[] = { 304 { P_XO, 0 }, 305 { P_GPLL4_OUT_AUX, 1 }, 306 { P_GPLL0_OUT_MAIN, 3 }, 307 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 }, 308 }; 309 310 static const struct clk_parent_data gcc_parent_data_12[] = { 311 { .index = DT_XO }, 312 { .hw = &gpll4.clkr.hw }, 313 { .hw = &gpll0.clkr.hw }, 314 { .hw = &gpll0_div2.hw }, 315 }; 316 317 static const struct freq_tbl ftbl_gcc_adss_pwm_clk_src[] = { 318 F(24000000, P_XO, 1, 0, 0), 319 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 320 { } 321 }; 322 323 static struct clk_rcg2 gcc_adss_pwm_clk_src = { 324 .cmd_rcgr = 0x1c004, 325 .mnd_width = 0, 326 .hid_width = 5, 327 .parent_map = gcc_parent_map_1, 328 .freq_tbl = ftbl_gcc_adss_pwm_clk_src, 329 .clkr.hw.init = &(const struct clk_init_data) { 330 .name = "gcc_adss_pwm_clk_src", 331 .parent_data = gcc_parent_data_1, 332 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 333 .ops = &clk_rcg2_ops, 334 }, 335 }; 336 337 static const struct freq_tbl ftbl_gcc_apss_axi_clk_src[] = { 338 F(480000000, P_GPLL4_OUT_AUX, 2.5, 0, 0), 339 F(533333333, P_GPLL0_OUT_MAIN, 1.5, 0, 0), 340 { } 341 }; 342 343 static const struct freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk_src[] = { 344 F(960000, P_XO, 1, 1, 25), 345 F(4800000, P_XO, 5, 0, 0), 346 F(9600000, P_XO, 2.5, 0, 0), 347 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5), 348 F(24000000, P_XO, 1, 0, 0), 349 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2), 350 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), 351 { } 352 }; 353 354 static struct clk_rcg2 gcc_blsp1_qup1_spi_apps_clk_src = { 355 .cmd_rcgr = 0x2004, 356 .mnd_width = 8, 357 .hid_width = 5, 358 .parent_map = gcc_parent_map_0, 359 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src, 360 .clkr.hw.init = &(const struct clk_init_data) { 361 .name = "gcc_blsp1_qup1_spi_apps_clk_src", 362 .parent_data = gcc_parent_data_0, 363 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 364 .ops = &clk_rcg2_ops, 365 }, 366 }; 367 368 static struct clk_rcg2 gcc_blsp1_qup2_spi_apps_clk_src = { 369 .cmd_rcgr = 0x3004, 370 .mnd_width = 8, 371 .hid_width = 5, 372 .parent_map = gcc_parent_map_0, 373 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src, 374 .clkr.hw.init = &(const struct clk_init_data) { 375 .name = "gcc_blsp1_qup2_spi_apps_clk_src", 376 .parent_data = gcc_parent_data_0, 377 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 378 .ops = &clk_rcg2_ops, 379 }, 380 }; 381 382 static struct clk_rcg2 gcc_blsp1_qup3_spi_apps_clk_src = { 383 .cmd_rcgr = 0x4004, 384 .mnd_width = 8, 385 .hid_width = 5, 386 .parent_map = gcc_parent_map_0, 387 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src, 388 .clkr.hw.init = &(const struct clk_init_data) { 389 .name = "gcc_blsp1_qup3_spi_apps_clk_src", 390 .parent_data = gcc_parent_data_0, 391 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 392 .ops = &clk_rcg2_ops, 393 }, 394 }; 395 396 static const struct freq_tbl ftbl_gcc_blsp1_uart1_apps_clk_src[] = { 397 F(3686400, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 144, 15625), 398 F(7372800, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 288, 15625), 399 F(14745600, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 576, 15625), 400 F(24000000, P_XO, 1, 0, 0), 401 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2), 402 F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25), 403 F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20), 404 F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500), 405 F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50), 406 F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125), 407 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100), 408 F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625), 409 F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40), 410 F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), 411 { } 412 }; 413 414 static struct clk_rcg2 gcc_blsp1_uart1_apps_clk_src = { 415 .cmd_rcgr = 0x202c, 416 .mnd_width = 16, 417 .hid_width = 5, 418 .parent_map = gcc_parent_map_0, 419 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src, 420 .clkr.hw.init = &(const struct clk_init_data) { 421 .name = "gcc_blsp1_uart1_apps_clk_src", 422 .parent_data = gcc_parent_data_0, 423 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 424 .ops = &clk_rcg2_ops, 425 }, 426 }; 427 428 static struct clk_rcg2 gcc_blsp1_uart2_apps_clk_src = { 429 .cmd_rcgr = 0x302c, 430 .mnd_width = 16, 431 .hid_width = 5, 432 .parent_map = gcc_parent_map_0, 433 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src, 434 .clkr.hw.init = &(const struct clk_init_data) { 435 .name = "gcc_blsp1_uart2_apps_clk_src", 436 .parent_data = gcc_parent_data_0, 437 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 438 .ops = &clk_rcg2_ops, 439 }, 440 }; 441 442 static struct clk_rcg2 gcc_blsp1_uart3_apps_clk_src = { 443 .cmd_rcgr = 0x402c, 444 .mnd_width = 16, 445 .hid_width = 5, 446 .parent_map = gcc_parent_map_0, 447 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src, 448 .clkr.hw.init = &(const struct clk_init_data) { 449 .name = "gcc_blsp1_uart3_apps_clk_src", 450 .parent_data = gcc_parent_data_0, 451 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 452 .ops = &clk_rcg2_ops, 453 }, 454 }; 455 456 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 457 F(24000000, P_XO, 1, 0, 0), 458 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 459 { } 460 }; 461 462 static struct clk_rcg2 gcc_gp1_clk_src = { 463 .cmd_rcgr = 0x8004, 464 .mnd_width = 8, 465 .hid_width = 5, 466 .parent_map = gcc_parent_map_3, 467 .freq_tbl = ftbl_gcc_gp1_clk_src, 468 .clkr.hw.init = &(const struct clk_init_data) { 469 .name = "gcc_gp1_clk_src", 470 .parent_data = gcc_parent_data_3, 471 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 472 .ops = &clk_rcg2_ops, 473 }, 474 }; 475 476 static struct clk_rcg2 gcc_gp2_clk_src = { 477 .cmd_rcgr = 0x9004, 478 .mnd_width = 8, 479 .hid_width = 5, 480 .parent_map = gcc_parent_map_3, 481 .freq_tbl = ftbl_gcc_gp1_clk_src, 482 .clkr.hw.init = &(const struct clk_init_data) { 483 .name = "gcc_gp2_clk_src", 484 .parent_data = gcc_parent_data_3, 485 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 486 .ops = &clk_rcg2_ops, 487 }, 488 }; 489 490 static const struct freq_tbl ftbl_gcc_lpass_sway_clk_src[] = { 491 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0), 492 { } 493 }; 494 495 static struct clk_rcg2 gcc_lpass_sway_clk_src = { 496 .cmd_rcgr = 0x27004, 497 .mnd_width = 0, 498 .hid_width = 5, 499 .parent_map = gcc_parent_map_1, 500 .freq_tbl = ftbl_gcc_lpass_sway_clk_src, 501 .clkr.hw.init = &(const struct clk_init_data) { 502 .name = "gcc_lpass_sway_clk_src", 503 .parent_data = gcc_parent_data_1, 504 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 505 .ops = &clk_rcg2_ops, 506 }, 507 }; 508 509 static const struct freq_tbl ftbl_gcc_nss_ts_clk_src[] = { 510 F(24000000, P_XO, 1, 0, 0), 511 { } 512 }; 513 514 static struct clk_rcg2 gcc_nss_ts_clk_src = { 515 .cmd_rcgr = 0x17088, 516 .mnd_width = 0, 517 .hid_width = 5, 518 .parent_map = gcc_parent_map_xo, 519 .freq_tbl = ftbl_gcc_nss_ts_clk_src, 520 .clkr.hw.init = &(const struct clk_init_data) { 521 .name = "gcc_nss_ts_clk_src", 522 .parent_data = &gcc_parent_data_xo, 523 .num_parents = 1, 524 .ops = &clk_rcg2_ops, 525 }, 526 }; 527 528 static const struct freq_tbl ftbl_gcc_pcie3x1_0_axi_clk_src[] = { 529 F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0), 530 { } 531 }; 532 533 static struct clk_rcg2 gcc_pcie3x1_0_axi_clk_src = { 534 .cmd_rcgr = 0x29018, 535 .mnd_width = 0, 536 .hid_width = 5, 537 .parent_map = gcc_parent_map_2, 538 .freq_tbl = ftbl_gcc_pcie3x1_0_axi_clk_src, 539 .clkr.hw.init = &(const struct clk_init_data) { 540 .name = "gcc_pcie3x1_0_axi_clk_src", 541 .parent_data = gcc_parent_data_2, 542 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 543 .ops = &clk_rcg2_ops, 544 }, 545 }; 546 547 static struct clk_rcg2 gcc_pcie3x1_0_rchg_clk_src = { 548 .cmd_rcgr = 0x2907c, 549 .hid_width = 5, 550 .parent_map = gcc_parent_map_0, 551 .freq_tbl = ftbl_gcc_adss_pwm_clk_src, 552 .clkr.hw.init = &(const struct clk_init_data) { 553 .name = "gcc_pcie3x1_0_rchg_clk_src", 554 .parent_data = gcc_parent_data_0, 555 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 556 .ops = &clk_rcg2_ops, 557 }, 558 }; 559 560 static struct clk_branch gcc_pcie3x1_0_rchg_clk = { 561 .halt_reg = 0x2907c, 562 .clkr = { 563 .enable_reg = 0x2907c, 564 .enable_mask = BIT(1), 565 .hw.init = &(struct clk_init_data) { 566 .name = "gcc_pcie3x1_0_rchg_clk", 567 .parent_hws = (const struct clk_hw *[]) { 568 &gcc_pcie3x1_0_rchg_clk_src.clkr.hw }, 569 .num_parents = 1, 570 .flags = CLK_SET_RATE_PARENT, 571 .ops = &clk_branch2_ops, 572 }, 573 }, 574 }; 575 576 static struct clk_rcg2 gcc_pcie3x1_1_axi_clk_src = { 577 .cmd_rcgr = 0x2a004, 578 .mnd_width = 0, 579 .hid_width = 5, 580 .parent_map = gcc_parent_map_2, 581 .freq_tbl = ftbl_gcc_pcie3x1_0_axi_clk_src, 582 .clkr.hw.init = &(const struct clk_init_data) { 583 .name = "gcc_pcie3x1_1_axi_clk_src", 584 .parent_data = gcc_parent_data_2, 585 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 586 .ops = &clk_rcg2_ops, 587 }, 588 }; 589 590 static struct clk_rcg2 gcc_pcie3x1_1_rchg_clk_src = { 591 .cmd_rcgr = 0x2a078, 592 .hid_width = 5, 593 .parent_map = gcc_parent_map_0, 594 .freq_tbl = ftbl_gcc_adss_pwm_clk_src, 595 .clkr.hw.init = &(const struct clk_init_data) { 596 .name = "gcc_pcie3x1_1_rchg_clk_src", 597 .parent_data = gcc_parent_data_0, 598 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 599 .ops = &clk_rcg2_ops, 600 }, 601 }; 602 603 static struct clk_branch gcc_pcie3x1_1_rchg_clk = { 604 .halt_reg = 0x2a078, 605 .clkr = { 606 .enable_reg = 0x2a078, 607 .enable_mask = BIT(1), 608 .hw.init = &(struct clk_init_data) { 609 .name = "gcc_pcie3x1_1_rchg_clk", 610 .parent_hws = (const struct clk_hw *[]) { 611 &gcc_pcie3x1_1_rchg_clk_src.clkr.hw }, 612 .num_parents = 1, 613 .flags = CLK_SET_RATE_PARENT, 614 .ops = &clk_branch2_ops, 615 }, 616 }, 617 }; 618 619 static const struct freq_tbl ftbl_gcc_pcie3x2_axi_m_clk_src[] = { 620 F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0), 621 { } 622 }; 623 624 static struct clk_rcg2 gcc_pcie3x2_axi_m_clk_src = { 625 .cmd_rcgr = 0x28018, 626 .mnd_width = 0, 627 .hid_width = 5, 628 .parent_map = gcc_parent_map_2, 629 .freq_tbl = ftbl_gcc_pcie3x2_axi_m_clk_src, 630 .clkr.hw.init = &(const struct clk_init_data) { 631 .name = "gcc_pcie3x2_axi_m_clk_src", 632 .parent_data = gcc_parent_data_2, 633 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 634 .ops = &clk_rcg2_ops, 635 }, 636 }; 637 638 static struct clk_rcg2 gcc_pcie3x2_axi_s_clk_src = { 639 .cmd_rcgr = 0x28084, 640 .mnd_width = 0, 641 .hid_width = 5, 642 .parent_map = gcc_parent_map_2, 643 .freq_tbl = ftbl_gcc_pcie3x1_0_axi_clk_src, 644 .clkr.hw.init = &(const struct clk_init_data) { 645 .name = "gcc_pcie3x2_axi_s_clk_src", 646 .parent_data = gcc_parent_data_2, 647 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 648 .ops = &clk_rcg2_ops, 649 }, 650 }; 651 652 static struct clk_rcg2 gcc_pcie3x2_rchg_clk_src = { 653 .cmd_rcgr = 0x28078, 654 .mnd_width = 0, 655 .hid_width = 5, 656 .parent_map = gcc_parent_map_0, 657 .freq_tbl = ftbl_gcc_adss_pwm_clk_src, 658 .clkr.hw.init = &(const struct clk_init_data) { 659 .name = "gcc_pcie3x2_rchg_clk_src", 660 .parent_data = gcc_parent_data_0, 661 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 662 .ops = &clk_rcg2_ops, 663 }, 664 }; 665 666 static struct clk_branch gcc_pcie3x2_rchg_clk = { 667 .halt_reg = 0x28078, 668 .clkr = { 669 .enable_reg = 0x28078, 670 .enable_mask = BIT(1), 671 .hw.init = &(struct clk_init_data) { 672 .name = "gcc_pcie3x2_rchg_clk", 673 .parent_hws = (const struct clk_hw *[]) { 674 &gcc_pcie3x2_rchg_clk_src.clkr.hw }, 675 .num_parents = 1, 676 .flags = CLK_SET_RATE_PARENT, 677 .ops = &clk_branch2_ops, 678 }, 679 }, 680 }; 681 682 static const struct freq_tbl ftbl_gcc_pcie_aux_clk_src[] = { 683 F(2000000, P_XO, 12, 0, 0), 684 { } 685 }; 686 687 static struct clk_rcg2 gcc_pcie_aux_clk_src = { 688 .cmd_rcgr = 0x28004, 689 .mnd_width = 16, 690 .hid_width = 5, 691 .parent_map = gcc_parent_map_5, 692 .freq_tbl = ftbl_gcc_pcie_aux_clk_src, 693 .clkr.hw.init = &(const struct clk_init_data) { 694 .name = "gcc_pcie_aux_clk_src", 695 .parent_data = gcc_parent_data_5, 696 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 697 .ops = &clk_rcg2_ops, 698 }, 699 }; 700 701 static struct clk_regmap_phy_mux gcc_pcie3x2_pipe_clk_src = { 702 .reg = 0x28064, 703 .clkr = { 704 .hw.init = &(struct clk_init_data) { 705 .name = "gcc_pcie3x2_pipe_clk_src", 706 .parent_data = &(const struct clk_parent_data) { 707 .index = DT_PCIE_2LANE_PHY_PIPE_CLK, 708 }, 709 .num_parents = 1, 710 .ops = &clk_regmap_phy_mux_ops, 711 }, 712 }, 713 }; 714 715 static struct clk_regmap_phy_mux gcc_pcie3x1_0_pipe_clk_src = { 716 .reg = 0x29064, 717 .clkr = { 718 .hw.init = &(struct clk_init_data) { 719 .name = "gcc_pcie3x1_0_pipe_clk_src", 720 .parent_data = &(const struct clk_parent_data) { 721 .index = DT_USB_PCIE_WRAPPER_PIPE_CLK, 722 }, 723 .num_parents = 1, 724 .ops = &clk_regmap_phy_mux_ops, 725 }, 726 }, 727 }; 728 729 static struct clk_regmap_phy_mux gcc_pcie3x1_1_pipe_clk_src = { 730 .reg = 0x2a064, 731 .clkr = { 732 .hw.init = &(struct clk_init_data) { 733 .name = "gcc_pcie3x1_1_pipe_clk_src", 734 .parent_data = &(const struct clk_parent_data) { 735 .index = DT_PCIE_2LANE_PHY_PIPE_CLK_X1, 736 }, 737 .num_parents = 1, 738 .ops = &clk_regmap_phy_mux_ops, 739 }, 740 }, 741 }; 742 743 static const struct freq_tbl ftbl_gcc_pcnoc_bfdcd_clk_src[] = { 744 F(24000000, P_XO, 1, 0, 0), 745 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), 746 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 747 { } 748 }; 749 750 static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src = { 751 .cmd_rcgr = 0x31004, 752 .mnd_width = 0, 753 .hid_width = 5, 754 .parent_map = gcc_parent_map_0, 755 .freq_tbl = ftbl_gcc_pcnoc_bfdcd_clk_src, 756 .clkr.hw.init = &(const struct clk_init_data) { 757 .name = "gcc_pcnoc_bfdcd_clk_src", 758 .parent_data = gcc_parent_data_0, 759 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 760 .ops = &clk_rcg2_ops, 761 }, 762 }; 763 764 static struct clk_rcg2 gcc_q6_axim_clk_src = { 765 .cmd_rcgr = 0x25004, 766 .mnd_width = 0, 767 .hid_width = 5, 768 .parent_map = gcc_parent_map_6, 769 .freq_tbl = ftbl_gcc_apss_axi_clk_src, 770 .clkr.hw.init = &(const struct clk_init_data) { 771 .name = "gcc_q6_axim_clk_src", 772 .parent_data = gcc_parent_data_6, 773 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 774 .ops = &clk_rcg2_ops, 775 }, 776 }; 777 778 static const struct freq_tbl ftbl_gcc_qdss_at_clk_src[] = { 779 F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0), 780 { } 781 }; 782 783 static struct clk_rcg2 gcc_qdss_at_clk_src = { 784 .cmd_rcgr = 0x2d004, 785 .mnd_width = 0, 786 .hid_width = 5, 787 .parent_map = gcc_parent_map_4, 788 .freq_tbl = ftbl_gcc_qdss_at_clk_src, 789 .clkr.hw.init = &(const struct clk_init_data) { 790 .name = "gcc_qdss_at_clk_src", 791 .parent_data = gcc_parent_data_4, 792 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 793 .ops = &clk_rcg2_ops, 794 }, 795 }; 796 797 static const struct freq_tbl ftbl_gcc_qdss_tsctr_clk_src[] = { 798 F(600000000, P_GPLL4_OUT_MAIN, 2, 0, 0), 799 { } 800 }; 801 802 static struct clk_rcg2 gcc_qdss_tsctr_clk_src = { 803 .cmd_rcgr = 0x2d01c, 804 .mnd_width = 0, 805 .hid_width = 5, 806 .parent_map = gcc_parent_map_4, 807 .freq_tbl = ftbl_gcc_qdss_tsctr_clk_src, 808 .clkr.hw.init = &(const struct clk_init_data) { 809 .name = "gcc_qdss_tsctr_clk_src", 810 .parent_data = gcc_parent_data_4, 811 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 812 .ops = &clk_rcg2_ops, 813 }, 814 }; 815 816 static struct clk_fixed_factor gcc_qdss_tsctr_div2_clk_src = { 817 .mult = 1, 818 .div = 2, 819 .hw.init = &(struct clk_init_data) { 820 .name = "gcc_qdss_tsctr_div2_clk_src", 821 .parent_hws = (const struct clk_hw *[]) { 822 &gcc_qdss_tsctr_clk_src.clkr.hw }, 823 .num_parents = 1, 824 .flags = CLK_SET_RATE_PARENT, 825 .ops = &clk_fixed_factor_ops, 826 }, 827 }; 828 829 static struct clk_fixed_factor gcc_qdss_tsctr_div3_clk_src = { 830 .mult = 1, 831 .div = 3, 832 .hw.init = &(struct clk_init_data) { 833 .name = "gcc_qdss_tsctr_div3_clk_src", 834 .parent_hws = (const struct clk_hw *[]) { 835 &gcc_qdss_tsctr_clk_src.clkr.hw }, 836 .num_parents = 1, 837 .ops = &clk_fixed_factor_ops, 838 }, 839 }; 840 841 static struct clk_fixed_factor gcc_qdss_tsctr_div4_clk_src = { 842 .mult = 1, 843 .div = 4, 844 .hw.init = &(struct clk_init_data) { 845 .name = "gcc_qdss_tsctr_div4_clk_src", 846 .parent_hws = (const struct clk_hw *[]) { 847 &gcc_qdss_tsctr_clk_src.clkr.hw }, 848 .num_parents = 1, 849 .ops = &clk_fixed_factor_ops, 850 }, 851 }; 852 853 static struct clk_fixed_factor gcc_qdss_tsctr_div8_clk_src = { 854 .mult = 1, 855 .div = 8, 856 .hw.init = &(struct clk_init_data) { 857 .name = "gcc_qdss_tsctr_div8_clk_src", 858 .parent_hws = (const struct clk_hw *[]) { 859 &gcc_qdss_tsctr_clk_src.clkr.hw }, 860 .num_parents = 1, 861 .ops = &clk_fixed_factor_ops, 862 }, 863 }; 864 865 static struct clk_fixed_factor gcc_qdss_tsctr_div16_clk_src = { 866 .mult = 1, 867 .div = 16, 868 .hw.init = &(struct clk_init_data) { 869 .name = "gcc_qdss_tsctr_div16_clk_src", 870 .parent_hws = (const struct clk_hw *[]) { 871 &gcc_qdss_tsctr_clk_src.clkr.hw }, 872 .num_parents = 1, 873 .ops = &clk_fixed_factor_ops, 874 }, 875 }; 876 877 static const struct freq_tbl ftbl_gcc_qpic_io_macro_clk_src[] = { 878 F(24000000, P_XO, 1, 0, 0), 879 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 880 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 881 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 882 { } 883 }; 884 885 static struct clk_rcg2 gcc_qpic_io_macro_clk_src = { 886 .cmd_rcgr = 0x32004, 887 .mnd_width = 0, 888 .hid_width = 5, 889 .parent_map = gcc_parent_map_7, 890 .freq_tbl = ftbl_gcc_qpic_io_macro_clk_src, 891 .clkr.hw.init = &(const struct clk_init_data) { 892 .name = "gcc_qpic_io_macro_clk_src", 893 .parent_data = gcc_parent_data_7, 894 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 895 .ops = &clk_rcg2_ops, 896 }, 897 }; 898 899 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 900 F(143713, P_XO, 1, 1, 167), 901 F(400000, P_XO, 1, 1, 60), 902 F(24000000, P_XO, 1, 0, 0), 903 F(48000000, P_GPLL2_OUT_MAIN, 12, 1, 2), 904 F(96000000, P_GPLL2_OUT_MAIN, 12, 0, 0), 905 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 906 F(192000000, P_GPLL2_OUT_MAIN, 6, 0, 0), 907 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 908 { } 909 }; 910 911 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 912 .cmd_rcgr = 0x33004, 913 .mnd_width = 8, 914 .hid_width = 5, 915 .parent_map = gcc_parent_map_8, 916 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 917 .clkr.hw.init = &(const struct clk_init_data) { 918 .name = "gcc_sdcc1_apps_clk_src", 919 .parent_data = gcc_parent_data_8, 920 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 921 .ops = &clk_rcg2_floor_ops, 922 }, 923 }; 924 925 static const struct freq_tbl ftbl_gcc_sleep_clk_src[] = { 926 F(32000, P_SLEEP_CLK, 1, 0, 0), 927 { } 928 }; 929 930 static struct clk_rcg2 gcc_sleep_clk_src = { 931 .cmd_rcgr = 0x3400c, 932 .mnd_width = 0, 933 .hid_width = 5, 934 .parent_map = gcc_parent_map_9, 935 .freq_tbl = ftbl_gcc_sleep_clk_src, 936 .clkr.hw.init = &(const struct clk_init_data) { 937 .name = "gcc_sleep_clk_src", 938 .parent_data = gcc_parent_data_9, 939 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 940 .ops = &clk_rcg2_ops, 941 }, 942 }; 943 944 static const struct freq_tbl ftbl_gcc_system_noc_bfdcd_clk_src[] = { 945 F(24000000, P_XO, 1, 0, 0), 946 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0), 947 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 948 F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0), 949 { } 950 }; 951 952 static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src = { 953 .cmd_rcgr = 0x2e004, 954 .mnd_width = 0, 955 .hid_width = 5, 956 .parent_map = gcc_parent_map_10, 957 .freq_tbl = ftbl_gcc_system_noc_bfdcd_clk_src, 958 .clkr.hw.init = &(const struct clk_init_data) { 959 .name = "gcc_system_noc_bfdcd_clk_src", 960 .parent_data = gcc_parent_data_10, 961 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 962 .ops = &clk_rcg2_ops, 963 }, 964 }; 965 966 static struct clk_fixed_factor gcc_system_noc_bfdcd_div2_clk_src = { 967 .mult = 1, 968 .div = 2, 969 .hw.init = &(struct clk_init_data) { 970 .name = "gcc_system_noc_bfdcd_div2_clk_src", 971 .parent_hws = (const struct clk_hw *[]) { 972 &gcc_system_noc_bfdcd_clk_src.clkr.hw }, 973 .num_parents = 1, 974 .ops = &clk_fixed_factor_ops, 975 .flags = CLK_SET_RATE_PARENT, 976 }, 977 }; 978 979 static struct clk_rcg2 gcc_uniphy_sys_clk_src = { 980 .cmd_rcgr = 0x16004, 981 .mnd_width = 0, 982 .hid_width = 5, 983 .parent_map = gcc_parent_map_xo, 984 .freq_tbl = ftbl_gcc_nss_ts_clk_src, 985 .clkr.hw.init = &(const struct clk_init_data) { 986 .name = "gcc_uniphy_sys_clk_src", 987 .parent_data = &gcc_parent_data_xo, 988 .num_parents = 1, 989 .ops = &clk_rcg2_ops, 990 }, 991 }; 992 993 static struct clk_rcg2 gcc_usb0_aux_clk_src = { 994 .cmd_rcgr = 0x2c018, 995 .mnd_width = 16, 996 .hid_width = 5, 997 .parent_map = gcc_parent_map_11, 998 .freq_tbl = ftbl_gcc_pcie_aux_clk_src, 999 .clkr.hw.init = &(const struct clk_init_data) { 1000 .name = "gcc_usb0_aux_clk_src", 1001 .parent_data = gcc_parent_data_11, 1002 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 1003 .ops = &clk_rcg2_ops, 1004 }, 1005 }; 1006 1007 static const struct freq_tbl ftbl_gcc_usb0_lfps_clk_src[] = { 1008 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2), 1009 { } 1010 }; 1011 1012 static struct clk_rcg2 gcc_usb0_lfps_clk_src = { 1013 .cmd_rcgr = 0x2c07c, 1014 .mnd_width = 8, 1015 .hid_width = 5, 1016 .parent_map = gcc_parent_map_1, 1017 .freq_tbl = ftbl_gcc_usb0_lfps_clk_src, 1018 .clkr.hw.init = &(const struct clk_init_data) { 1019 .name = "gcc_usb0_lfps_clk_src", 1020 .parent_data = gcc_parent_data_1, 1021 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1022 .ops = &clk_rcg2_ops, 1023 }, 1024 }; 1025 1026 static struct clk_rcg2 gcc_usb0_master_clk_src = { 1027 .cmd_rcgr = 0x2c004, 1028 .mnd_width = 8, 1029 .hid_width = 5, 1030 .parent_map = gcc_parent_map_0, 1031 .freq_tbl = ftbl_gcc_gp1_clk_src, 1032 .clkr.hw.init = &(const struct clk_init_data) { 1033 .name = "gcc_usb0_master_clk_src", 1034 .parent_data = gcc_parent_data_0, 1035 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1036 .ops = &clk_rcg2_ops, 1037 }, 1038 }; 1039 1040 static const struct freq_tbl ftbl_gcc_usb0_mock_utmi_clk_src[] = { 1041 F(60000000, P_GPLL4_OUT_AUX, 10, 1, 2), 1042 { } 1043 }; 1044 1045 static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = { 1046 .cmd_rcgr = 0x2c02c, 1047 .mnd_width = 8, 1048 .hid_width = 5, 1049 .parent_map = gcc_parent_map_12, 1050 .freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src, 1051 .clkr.hw.init = &(const struct clk_init_data) { 1052 .name = "gcc_usb0_mock_utmi_clk_src", 1053 .parent_data = gcc_parent_data_12, 1054 .num_parents = ARRAY_SIZE(gcc_parent_data_12), 1055 .ops = &clk_rcg2_ops, 1056 }, 1057 }; 1058 1059 static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = { 1060 .reg = 0x2c074, 1061 .clkr = { 1062 .hw.init = &(struct clk_init_data) { 1063 .name = "gcc_usb0_pipe_clk_src", 1064 .parent_data = &(const struct clk_parent_data) { 1065 .index = DT_USB_PCIE_WRAPPER_PIPE_CLK, 1066 }, 1067 .num_parents = 1, 1068 .ops = &clk_regmap_phy_mux_ops, 1069 }, 1070 }, 1071 }; 1072 1073 static struct clk_rcg2 gcc_wcss_ahb_clk_src = { 1074 .cmd_rcgr = 0x25030, 1075 .mnd_width = 0, 1076 .hid_width = 5, 1077 .parent_map = gcc_parent_map_1, 1078 .freq_tbl = ftbl_gcc_lpass_sway_clk_src, 1079 .clkr.hw.init = &(const struct clk_init_data) { 1080 .name = "gcc_wcss_ahb_clk_src", 1081 .parent_data = gcc_parent_data_1, 1082 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1083 .ops = &clk_rcg2_ops, 1084 }, 1085 }; 1086 1087 static struct clk_rcg2 gcc_xo_clk_src = { 1088 .cmd_rcgr = 0x34004, 1089 .mnd_width = 0, 1090 .hid_width = 5, 1091 .parent_map = gcc_parent_map_xo, 1092 .freq_tbl = ftbl_gcc_nss_ts_clk_src, 1093 .clkr.hw.init = &(const struct clk_init_data) { 1094 .name = "gcc_xo_clk_src", 1095 .parent_data = &gcc_parent_data_xo, 1096 .num_parents = 1, 1097 .ops = &clk_rcg2_ops, 1098 }, 1099 }; 1100 1101 static struct clk_fixed_factor gcc_xo_div4_clk_src = { 1102 .mult = 1, 1103 .div = 4, 1104 .hw.init = &(struct clk_init_data) { 1105 .name = "gcc_xo_div4_clk_src", 1106 .parent_hws = (const struct clk_hw *[]) { 1107 &gcc_xo_clk_src.clkr.hw }, 1108 .num_parents = 1, 1109 .ops = &clk_fixed_factor_ops, 1110 .flags = CLK_SET_RATE_PARENT, 1111 }, 1112 }; 1113 1114 static struct clk_regmap_div gcc_qdss_dap_div_clk_src = { 1115 .reg = 0x2d028, 1116 .shift = 0, 1117 .width = 4, 1118 .clkr.hw.init = &(const struct clk_init_data) { 1119 .name = "gcc_qdss_dap_div_clk_src", 1120 .parent_hws = (const struct clk_hw*[]) { 1121 &gcc_qdss_tsctr_clk_src.clkr.hw, 1122 }, 1123 .num_parents = 1, 1124 .ops = &clk_regmap_div_ro_ops, 1125 }, 1126 }; 1127 1128 static struct clk_regmap_div gcc_usb0_mock_utmi_div_clk_src = { 1129 .reg = 0x2c040, 1130 .shift = 0, 1131 .width = 2, 1132 .clkr.hw.init = &(const struct clk_init_data) { 1133 .name = "gcc_usb0_mock_utmi_div_clk_src", 1134 .parent_hws = (const struct clk_hw*[]) { 1135 &gcc_usb0_mock_utmi_clk_src.clkr.hw, 1136 }, 1137 .num_parents = 1, 1138 .flags = CLK_SET_RATE_PARENT, 1139 .ops = &clk_regmap_div_ro_ops, 1140 }, 1141 }; 1142 1143 static struct clk_branch gcc_adss_pwm_clk = { 1144 .halt_reg = 0x1c00c, 1145 .halt_check = BRANCH_HALT, 1146 .clkr = { 1147 .enable_reg = 0x1c00c, 1148 .enable_mask = BIT(0), 1149 .hw.init = &(const struct clk_init_data) { 1150 .name = "gcc_adss_pwm_clk", 1151 .parent_hws = (const struct clk_hw*[]) { 1152 &gcc_adss_pwm_clk_src.clkr.hw, 1153 }, 1154 .num_parents = 1, 1155 .flags = CLK_SET_RATE_PARENT, 1156 .ops = &clk_branch2_ops, 1157 }, 1158 }, 1159 }; 1160 1161 static struct clk_branch gcc_ahb_clk = { 1162 .halt_reg = 0x34024, 1163 .halt_check = BRANCH_HALT_VOTED, 1164 .clkr = { 1165 .enable_reg = 0x34024, 1166 .enable_mask = BIT(0), 1167 .hw.init = &(const struct clk_init_data) { 1168 .name = "gcc_ahb_clk", 1169 .parent_hws = (const struct clk_hw*[]) { 1170 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1171 }, 1172 .num_parents = 1, 1173 .flags = CLK_SET_RATE_PARENT, 1174 .ops = &clk_branch2_ops, 1175 }, 1176 }, 1177 }; 1178 1179 static struct clk_branch gcc_blsp1_ahb_clk = { 1180 .halt_reg = 0x1008, 1181 .halt_check = BRANCH_HALT_VOTED, 1182 .clkr = { 1183 .enable_reg = 0xb004, 1184 .enable_mask = BIT(4), 1185 .hw.init = &(const struct clk_init_data) { 1186 .name = "gcc_blsp1_ahb_clk", 1187 .parent_hws = (const struct clk_hw*[]) { 1188 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1189 }, 1190 .num_parents = 1, 1191 .flags = CLK_SET_RATE_PARENT, 1192 .ops = &clk_branch2_ops, 1193 }, 1194 }, 1195 }; 1196 1197 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1198 .halt_reg = 0x2024, 1199 .halt_check = BRANCH_HALT, 1200 .clkr = { 1201 .enable_reg = 0x2024, 1202 .enable_mask = BIT(0), 1203 .hw.init = &(const struct clk_init_data) { 1204 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1205 .parent_hws = (const struct clk_hw*[]) { 1206 &gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw, 1207 }, 1208 .num_parents = 1, 1209 .flags = CLK_SET_RATE_PARENT, 1210 .ops = &clk_branch2_ops, 1211 }, 1212 }, 1213 }; 1214 1215 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1216 .halt_reg = 0x2020, 1217 .halt_check = BRANCH_HALT, 1218 .clkr = { 1219 .enable_reg = 0x2020, 1220 .enable_mask = BIT(0), 1221 .hw.init = &(const struct clk_init_data) { 1222 .name = "gcc_blsp1_qup1_spi_apps_clk", 1223 .parent_hws = (const struct clk_hw*[]) { 1224 &gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw, 1225 }, 1226 .num_parents = 1, 1227 .flags = CLK_SET_RATE_PARENT, 1228 .ops = &clk_branch2_ops, 1229 }, 1230 }, 1231 }; 1232 1233 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1234 .halt_reg = 0x3024, 1235 .halt_check = BRANCH_HALT, 1236 .clkr = { 1237 .enable_reg = 0x3024, 1238 .enable_mask = BIT(0), 1239 .hw.init = &(const struct clk_init_data) { 1240 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1241 .parent_hws = (const struct clk_hw*[]) { 1242 &gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw, 1243 }, 1244 .num_parents = 1, 1245 .flags = CLK_SET_RATE_PARENT, 1246 .ops = &clk_branch2_ops, 1247 }, 1248 }, 1249 }; 1250 1251 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1252 .halt_reg = 0x3020, 1253 .halt_check = BRANCH_HALT, 1254 .clkr = { 1255 .enable_reg = 0x3020, 1256 .enable_mask = BIT(0), 1257 .hw.init = &(const struct clk_init_data) { 1258 .name = "gcc_blsp1_qup2_spi_apps_clk", 1259 .parent_hws = (const struct clk_hw*[]) { 1260 &gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw, 1261 }, 1262 .num_parents = 1, 1263 .flags = CLK_SET_RATE_PARENT, 1264 .ops = &clk_branch2_ops, 1265 }, 1266 }, 1267 }; 1268 1269 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1270 .halt_reg = 0x4024, 1271 .halt_check = BRANCH_HALT, 1272 .clkr = { 1273 .enable_reg = 0x4024, 1274 .enable_mask = BIT(0), 1275 .hw.init = &(const struct clk_init_data) { 1276 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1277 .parent_hws = (const struct clk_hw*[]) { 1278 &gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw, 1279 }, 1280 .num_parents = 1, 1281 .flags = CLK_SET_RATE_PARENT, 1282 .ops = &clk_branch2_ops, 1283 }, 1284 }, 1285 }; 1286 1287 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1288 .halt_reg = 0x4020, 1289 .halt_check = BRANCH_HALT, 1290 .clkr = { 1291 .enable_reg = 0x4020, 1292 .enable_mask = BIT(0), 1293 .hw.init = &(const struct clk_init_data) { 1294 .name = "gcc_blsp1_qup3_spi_apps_clk", 1295 .parent_hws = (const struct clk_hw*[]) { 1296 &gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw, 1297 }, 1298 .num_parents = 1, 1299 .flags = CLK_SET_RATE_PARENT, 1300 .ops = &clk_branch2_ops, 1301 }, 1302 }, 1303 }; 1304 1305 static struct clk_branch gcc_blsp1_sleep_clk = { 1306 .halt_reg = 0x1010, 1307 .halt_check = BRANCH_HALT_VOTED, 1308 .clkr = { 1309 .enable_reg = 0xb004, 1310 .enable_mask = BIT(5), 1311 .hw.init = &(const struct clk_init_data) { 1312 .name = "gcc_blsp1_sleep_clk", 1313 .parent_hws = (const struct clk_hw*[]) { 1314 &gcc_sleep_clk_src.clkr.hw, 1315 }, 1316 .num_parents = 1, 1317 .flags = CLK_SET_RATE_PARENT, 1318 .ops = &clk_branch2_ops, 1319 }, 1320 }, 1321 }; 1322 1323 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1324 .halt_reg = 0x2040, 1325 .halt_check = BRANCH_HALT, 1326 .clkr = { 1327 .enable_reg = 0x2040, 1328 .enable_mask = BIT(0), 1329 .hw.init = &(const struct clk_init_data) { 1330 .name = "gcc_blsp1_uart1_apps_clk", 1331 .parent_hws = (const struct clk_hw*[]) { 1332 &gcc_blsp1_uart1_apps_clk_src.clkr.hw, 1333 }, 1334 .num_parents = 1, 1335 .flags = CLK_SET_RATE_PARENT, 1336 .ops = &clk_branch2_ops, 1337 }, 1338 }, 1339 }; 1340 1341 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1342 .halt_reg = 0x3040, 1343 .halt_check = BRANCH_HALT, 1344 .clkr = { 1345 .enable_reg = 0x3040, 1346 .enable_mask = BIT(0), 1347 .hw.init = &(const struct clk_init_data) { 1348 .name = "gcc_blsp1_uart2_apps_clk", 1349 .parent_hws = (const struct clk_hw*[]) { 1350 &gcc_blsp1_uart2_apps_clk_src.clkr.hw, 1351 }, 1352 .num_parents = 1, 1353 .flags = CLK_SET_RATE_PARENT, 1354 .ops = &clk_branch2_ops, 1355 }, 1356 }, 1357 }; 1358 1359 static struct clk_branch gcc_blsp1_uart3_apps_clk = { 1360 .halt_reg = 0x4054, 1361 .halt_check = BRANCH_HALT, 1362 .clkr = { 1363 .enable_reg = 0x4054, 1364 .enable_mask = BIT(0), 1365 .hw.init = &(const struct clk_init_data) { 1366 .name = "gcc_blsp1_uart3_apps_clk", 1367 .parent_hws = (const struct clk_hw*[]) { 1368 &gcc_blsp1_uart3_apps_clk_src.clkr.hw, 1369 }, 1370 .num_parents = 1, 1371 .flags = CLK_SET_RATE_PARENT, 1372 .ops = &clk_branch2_ops, 1373 }, 1374 }, 1375 }; 1376 1377 static struct clk_branch gcc_ce_ahb_clk = { 1378 .halt_reg = 0x25074, 1379 .halt_check = BRANCH_HALT, 1380 .clkr = { 1381 .enable_reg = 0x25074, 1382 .enable_mask = BIT(0), 1383 .hw.init = &(const struct clk_init_data) { 1384 .name = "gcc_ce_ahb_clk", 1385 .parent_hws = (const struct clk_hw*[]) { 1386 &gcc_system_noc_bfdcd_div2_clk_src.hw, 1387 }, 1388 .num_parents = 1, 1389 .flags = CLK_SET_RATE_PARENT, 1390 .ops = &clk_branch2_ops, 1391 }, 1392 }, 1393 }; 1394 1395 static struct clk_branch gcc_ce_axi_clk = { 1396 .halt_reg = 0x25068, 1397 .halt_check = BRANCH_HALT, 1398 .clkr = { 1399 .enable_reg = 0x25068, 1400 .enable_mask = BIT(0), 1401 .hw.init = &(const struct clk_init_data) { 1402 .name = "gcc_ce_axi_clk", 1403 .parent_hws = (const struct clk_hw*[]) { 1404 &gcc_system_noc_bfdcd_clk_src.clkr.hw, 1405 }, 1406 .num_parents = 1, 1407 .flags = CLK_SET_RATE_PARENT, 1408 .ops = &clk_branch2_ops, 1409 }, 1410 }, 1411 }; 1412 1413 static struct clk_branch gcc_ce_pcnoc_ahb_clk = { 1414 .halt_reg = 0x25070, 1415 .halt_check = BRANCH_HALT, 1416 .clkr = { 1417 .enable_reg = 0x25070, 1418 .enable_mask = BIT(0), 1419 .hw.init = &(const struct clk_init_data) { 1420 .name = "gcc_ce_pcnoc_ahb_clk", 1421 .parent_hws = (const struct clk_hw*[]) { 1422 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1423 }, 1424 .num_parents = 1, 1425 .flags = CLK_SET_RATE_PARENT, 1426 .ops = &clk_branch2_ops, 1427 }, 1428 }, 1429 }; 1430 1431 static struct clk_branch gcc_cmn_12gpll_ahb_clk = { 1432 .halt_reg = 0x3a004, 1433 .halt_check = BRANCH_HALT, 1434 .clkr = { 1435 .enable_reg = 0x3a004, 1436 .enable_mask = BIT(0), 1437 .hw.init = &(const struct clk_init_data) { 1438 .name = "gcc_cmn_12gpll_ahb_clk", 1439 .parent_hws = (const struct clk_hw*[]) { 1440 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1441 }, 1442 .num_parents = 1, 1443 .flags = CLK_SET_RATE_PARENT, 1444 .ops = &clk_branch2_ops, 1445 }, 1446 }, 1447 }; 1448 1449 static struct clk_branch gcc_cmn_12gpll_apu_clk = { 1450 .halt_reg = 0x3a00c, 1451 .halt_check = BRANCH_HALT, 1452 .clkr = { 1453 .enable_reg = 0x3a00c, 1454 .enable_mask = BIT(0), 1455 .hw.init = &(const struct clk_init_data) { 1456 .name = "gcc_cmn_12gpll_apu_clk", 1457 .parent_hws = (const struct clk_hw*[]) { 1458 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1459 }, 1460 .num_parents = 1, 1461 .flags = CLK_SET_RATE_PARENT, 1462 .ops = &clk_branch2_ops, 1463 }, 1464 }, 1465 }; 1466 1467 static struct clk_branch gcc_cmn_12gpll_sys_clk = { 1468 .halt_reg = 0x3a008, 1469 .halt_check = BRANCH_HALT, 1470 .clkr = { 1471 .enable_reg = 0x3a008, 1472 .enable_mask = BIT(0), 1473 .hw.init = &(const struct clk_init_data) { 1474 .name = "gcc_cmn_12gpll_sys_clk", 1475 .parent_hws = (const struct clk_hw*[]) { 1476 &gcc_uniphy_sys_clk_src.clkr.hw, 1477 }, 1478 .num_parents = 1, 1479 .flags = CLK_SET_RATE_PARENT, 1480 .ops = &clk_branch2_ops, 1481 }, 1482 }, 1483 }; 1484 1485 static struct clk_branch gcc_gp1_clk = { 1486 .halt_reg = 0x8018, 1487 .halt_check = BRANCH_HALT, 1488 .clkr = { 1489 .enable_reg = 0x8018, 1490 .enable_mask = BIT(0), 1491 .hw.init = &(const struct clk_init_data) { 1492 .name = "gcc_gp1_clk", 1493 .parent_hws = (const struct clk_hw*[]) { 1494 &gcc_gp1_clk_src.clkr.hw, 1495 }, 1496 .num_parents = 1, 1497 .flags = CLK_SET_RATE_PARENT, 1498 .ops = &clk_branch2_ops, 1499 }, 1500 }, 1501 }; 1502 1503 static struct clk_branch gcc_gp2_clk = { 1504 .halt_reg = 0x9018, 1505 .halt_check = BRANCH_HALT, 1506 .clkr = { 1507 .enable_reg = 0x9018, 1508 .enable_mask = BIT(0), 1509 .hw.init = &(const struct clk_init_data) { 1510 .name = "gcc_gp2_clk", 1511 .parent_hws = (const struct clk_hw*[]) { 1512 &gcc_gp2_clk_src.clkr.hw, 1513 }, 1514 .num_parents = 1, 1515 .flags = CLK_SET_RATE_PARENT, 1516 .ops = &clk_branch2_ops, 1517 }, 1518 }, 1519 }; 1520 1521 static struct clk_branch gcc_lpass_core_axim_clk = { 1522 .halt_reg = 0x27018, 1523 .halt_check = BRANCH_HALT_VOTED, 1524 .clkr = { 1525 .enable_reg = 0x27018, 1526 .enable_mask = BIT(0), 1527 .hw.init = &(const struct clk_init_data) { 1528 .name = "gcc_lpass_core_axim_clk", 1529 .parent_hws = (const struct clk_hw*[]) { 1530 &gcc_lpass_sway_clk_src.clkr.hw, 1531 }, 1532 .num_parents = 1, 1533 .flags = CLK_SET_RATE_PARENT, 1534 .ops = &clk_branch2_ops, 1535 }, 1536 }, 1537 }; 1538 1539 static struct clk_branch gcc_lpass_sway_clk = { 1540 .halt_reg = 0x27014, 1541 .halt_check = BRANCH_HALT, 1542 .clkr = { 1543 .enable_reg = 0x27014, 1544 .enable_mask = BIT(0), 1545 .hw.init = &(const struct clk_init_data) { 1546 .name = "gcc_lpass_sway_clk", 1547 .parent_hws = (const struct clk_hw*[]) { 1548 &gcc_lpass_sway_clk_src.clkr.hw, 1549 }, 1550 .num_parents = 1, 1551 .flags = CLK_SET_RATE_PARENT, 1552 .ops = &clk_branch2_ops, 1553 }, 1554 }, 1555 }; 1556 1557 static struct clk_branch gcc_mdio_ahb_clk = { 1558 .halt_reg = 0x12004, 1559 .halt_check = BRANCH_HALT, 1560 .clkr = { 1561 .enable_reg = 0x12004, 1562 .enable_mask = BIT(0), 1563 .hw.init = &(const struct clk_init_data) { 1564 .name = "gcc_mdio_ahb_clk", 1565 .parent_hws = (const struct clk_hw*[]) { 1566 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1567 }, 1568 .num_parents = 1, 1569 .flags = CLK_SET_RATE_PARENT, 1570 .ops = &clk_branch2_ops, 1571 }, 1572 }, 1573 }; 1574 1575 static struct clk_branch gcc_mdio_slave_ahb_clk = { 1576 .halt_reg = 0x1200c, 1577 .halt_check = BRANCH_HALT, 1578 .clkr = { 1579 .enable_reg = 0x1200c, 1580 .enable_mask = BIT(0), 1581 .hw.init = &(const struct clk_init_data) { 1582 .name = "gcc_mdio_slave_ahb_clk", 1583 .parent_hws = (const struct clk_hw*[]) { 1584 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1585 }, 1586 .num_parents = 1, 1587 .flags = CLK_SET_RATE_PARENT, 1588 .ops = &clk_branch2_ops, 1589 }, 1590 }, 1591 }; 1592 1593 static struct clk_branch gcc_nss_ts_clk = { 1594 .halt_reg = 0x17018, 1595 .halt_check = BRANCH_HALT_VOTED, 1596 .clkr = { 1597 .enable_reg = 0x17018, 1598 .enable_mask = BIT(0), 1599 .hw.init = &(const struct clk_init_data) { 1600 .name = "gcc_nss_ts_clk", 1601 .parent_hws = (const struct clk_hw*[]) { 1602 &gcc_nss_ts_clk_src.clkr.hw, 1603 }, 1604 .num_parents = 1, 1605 .flags = CLK_SET_RATE_PARENT, 1606 .ops = &clk_branch2_ops, 1607 }, 1608 }, 1609 }; 1610 1611 static struct clk_branch gcc_nsscc_clk = { 1612 .halt_reg = 0x17034, 1613 .halt_check = BRANCH_HALT, 1614 .clkr = { 1615 .enable_reg = 0x17034, 1616 .enable_mask = BIT(0), 1617 .hw.init = &(const struct clk_init_data) { 1618 .name = "gcc_nsscc_clk", 1619 .parent_hws = (const struct clk_hw*[]) { 1620 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1621 }, 1622 .num_parents = 1, 1623 .flags = CLK_SET_RATE_PARENT, 1624 .ops = &clk_branch2_ops, 1625 }, 1626 }, 1627 }; 1628 1629 static struct clk_branch gcc_nsscfg_clk = { 1630 .halt_reg = 0x1702c, 1631 .halt_check = BRANCH_HALT, 1632 .clkr = { 1633 .enable_reg = 0x1702c, 1634 .enable_mask = BIT(0), 1635 .hw.init = &(const struct clk_init_data) { 1636 .name = "gcc_nsscfg_clk", 1637 .parent_hws = (const struct clk_hw*[]) { 1638 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1639 }, 1640 .num_parents = 1, 1641 .flags = CLK_SET_RATE_PARENT, 1642 .ops = &clk_branch2_ops, 1643 }, 1644 }, 1645 }; 1646 1647 static struct clk_branch gcc_nssnoc_atb_clk = { 1648 .halt_reg = 0x17014, 1649 .halt_check = BRANCH_HALT, 1650 .clkr = { 1651 .enable_reg = 0x17014, 1652 .enable_mask = BIT(0), 1653 .hw.init = &(const struct clk_init_data) { 1654 .name = "gcc_nssnoc_atb_clk", 1655 .parent_hws = (const struct clk_hw*[]) { 1656 &gcc_qdss_at_clk_src.clkr.hw, 1657 }, 1658 .num_parents = 1, 1659 .flags = CLK_SET_RATE_PARENT, 1660 .ops = &clk_branch2_ops, 1661 }, 1662 }, 1663 }; 1664 1665 static struct clk_branch gcc_nssnoc_nsscc_clk = { 1666 .halt_reg = 0x17030, 1667 .halt_check = BRANCH_HALT, 1668 .clkr = { 1669 .enable_reg = 0x17030, 1670 .enable_mask = BIT(0), 1671 .hw.init = &(const struct clk_init_data) { 1672 .name = "gcc_nssnoc_nsscc_clk", 1673 .parent_hws = (const struct clk_hw*[]) { 1674 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1675 }, 1676 .num_parents = 1, 1677 .flags = CLK_SET_RATE_PARENT, 1678 .ops = &clk_branch2_ops, 1679 }, 1680 }, 1681 }; 1682 1683 static struct clk_branch gcc_nssnoc_qosgen_ref_clk = { 1684 .halt_reg = 0x1701c, 1685 .halt_check = BRANCH_HALT, 1686 .clkr = { 1687 .enable_reg = 0x1701c, 1688 .enable_mask = BIT(0), 1689 .hw.init = &(const struct clk_init_data) { 1690 .name = "gcc_nssnoc_qosgen_ref_clk", 1691 .parent_hws = (const struct clk_hw*[]) { 1692 &gcc_xo_div4_clk_src.hw, 1693 }, 1694 .num_parents = 1, 1695 .flags = CLK_SET_RATE_PARENT, 1696 .ops = &clk_branch2_ops, 1697 }, 1698 }, 1699 }; 1700 1701 static struct clk_branch gcc_nssnoc_snoc_1_clk = { 1702 .halt_reg = 0x1707c, 1703 .halt_check = BRANCH_HALT, 1704 .clkr = { 1705 .enable_reg = 0x1707c, 1706 .enable_mask = BIT(0), 1707 .hw.init = &(const struct clk_init_data) { 1708 .name = "gcc_nssnoc_snoc_1_clk", 1709 .parent_hws = (const struct clk_hw*[]) { 1710 &gcc_system_noc_bfdcd_clk_src.clkr.hw, 1711 }, 1712 .num_parents = 1, 1713 .flags = CLK_SET_RATE_PARENT, 1714 .ops = &clk_branch2_ops, 1715 }, 1716 }, 1717 }; 1718 1719 static struct clk_branch gcc_nssnoc_snoc_clk = { 1720 .halt_reg = 0x17028, 1721 .halt_check = BRANCH_HALT, 1722 .clkr = { 1723 .enable_reg = 0x17028, 1724 .enable_mask = BIT(0), 1725 .hw.init = &(const struct clk_init_data) { 1726 .name = "gcc_nssnoc_snoc_clk", 1727 .parent_hws = (const struct clk_hw*[]) { 1728 &gcc_system_noc_bfdcd_clk_src.clkr.hw, 1729 }, 1730 .num_parents = 1, 1731 .flags = CLK_SET_RATE_PARENT, 1732 .ops = &clk_branch2_ops, 1733 }, 1734 }, 1735 }; 1736 1737 static struct clk_branch gcc_nssnoc_timeout_ref_clk = { 1738 .halt_reg = 0x17020, 1739 .halt_check = BRANCH_HALT, 1740 .clkr = { 1741 .enable_reg = 0x17020, 1742 .enable_mask = BIT(0), 1743 .hw.init = &(const struct clk_init_data) { 1744 .name = "gcc_nssnoc_timeout_ref_clk", 1745 .parent_hws = (const struct clk_hw*[]) { 1746 &gcc_xo_div4_clk_src.hw, 1747 }, 1748 .num_parents = 1, 1749 .flags = CLK_SET_RATE_PARENT, 1750 .ops = &clk_branch2_ops, 1751 }, 1752 }, 1753 }; 1754 1755 static struct clk_branch gcc_nssnoc_xo_dcd_clk = { 1756 .halt_reg = 0x17074, 1757 .halt_check = BRANCH_HALT, 1758 .clkr = { 1759 .enable_reg = 0x17074, 1760 .enable_mask = BIT(0), 1761 .hw.init = &(const struct clk_init_data) { 1762 .name = "gcc_nssnoc_xo_dcd_clk", 1763 .parent_hws = (const struct clk_hw*[]) { 1764 &gcc_xo_clk_src.clkr.hw, 1765 }, 1766 .num_parents = 1, 1767 .flags = CLK_SET_RATE_PARENT, 1768 .ops = &clk_branch2_ops, 1769 }, 1770 }, 1771 }; 1772 1773 static struct clk_branch gcc_pcie3x1_0_ahb_clk = { 1774 .halt_reg = 0x29030, 1775 .halt_check = BRANCH_HALT, 1776 .clkr = { 1777 .enable_reg = 0x29030, 1778 .enable_mask = BIT(0), 1779 .hw.init = &(const struct clk_init_data) { 1780 .name = "gcc_pcie3x1_0_ahb_clk", 1781 .parent_hws = (const struct clk_hw*[]) { 1782 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1783 }, 1784 .num_parents = 1, 1785 .flags = CLK_SET_RATE_PARENT, 1786 .ops = &clk_branch2_ops, 1787 }, 1788 }, 1789 }; 1790 1791 static struct clk_branch gcc_pcie3x1_0_aux_clk = { 1792 .halt_reg = 0x29070, 1793 .halt_check = BRANCH_HALT, 1794 .clkr = { 1795 .enable_reg = 0x29070, 1796 .enable_mask = BIT(0), 1797 .hw.init = &(const struct clk_init_data) { 1798 .name = "gcc_pcie3x1_0_aux_clk", 1799 .parent_hws = (const struct clk_hw*[]) { 1800 &gcc_pcie_aux_clk_src.clkr.hw, 1801 }, 1802 .num_parents = 1, 1803 .flags = CLK_SET_RATE_PARENT, 1804 .ops = &clk_branch2_ops, 1805 }, 1806 }, 1807 }; 1808 1809 static struct clk_branch gcc_pcie3x1_0_axi_m_clk = { 1810 .halt_reg = 0x29038, 1811 .halt_check = BRANCH_HALT, 1812 .clkr = { 1813 .enable_reg = 0x29038, 1814 .enable_mask = BIT(0), 1815 .hw.init = &(const struct clk_init_data) { 1816 .name = "gcc_pcie3x1_0_axi_m_clk", 1817 .parent_hws = (const struct clk_hw*[]) { 1818 &gcc_pcie3x1_0_axi_clk_src.clkr.hw, 1819 }, 1820 .num_parents = 1, 1821 .flags = CLK_SET_RATE_PARENT, 1822 .ops = &clk_branch2_ops, 1823 }, 1824 }, 1825 }; 1826 1827 static struct clk_branch gcc_pcie3x1_0_axi_s_bridge_clk = { 1828 .halt_reg = 0x29048, 1829 .halt_check = BRANCH_HALT, 1830 .clkr = { 1831 .enable_reg = 0x29048, 1832 .enable_mask = BIT(0), 1833 .hw.init = &(const struct clk_init_data) { 1834 .name = "gcc_pcie3x1_0_axi_s_bridge_clk", 1835 .parent_hws = (const struct clk_hw*[]) { 1836 &gcc_pcie3x1_0_axi_clk_src.clkr.hw, 1837 }, 1838 .num_parents = 1, 1839 .flags = CLK_SET_RATE_PARENT, 1840 .ops = &clk_branch2_ops, 1841 }, 1842 }, 1843 }; 1844 1845 static struct clk_branch gcc_pcie3x1_0_axi_s_clk = { 1846 .halt_reg = 0x29040, 1847 .halt_check = BRANCH_HALT, 1848 .clkr = { 1849 .enable_reg = 0x29040, 1850 .enable_mask = BIT(0), 1851 .hw.init = &(const struct clk_init_data) { 1852 .name = "gcc_pcie3x1_0_axi_s_clk", 1853 .parent_hws = (const struct clk_hw*[]) { 1854 &gcc_pcie3x1_0_axi_clk_src.clkr.hw, 1855 }, 1856 .num_parents = 1, 1857 .flags = CLK_SET_RATE_PARENT, 1858 .ops = &clk_branch2_ops, 1859 }, 1860 }, 1861 }; 1862 1863 static struct clk_branch gcc_pcie3x1_0_pipe_clk = { 1864 .halt_reg = 0x29068, 1865 .halt_check = BRANCH_HALT_DELAY, 1866 .clkr = { 1867 .enable_reg = 0x29068, 1868 .enable_mask = BIT(0), 1869 .hw.init = &(const struct clk_init_data) { 1870 .name = "gcc_pcie3x1_0_pipe_clk", 1871 .parent_hws = (const struct clk_hw*[]) { 1872 &gcc_pcie3x1_0_pipe_clk_src.clkr.hw, 1873 }, 1874 .num_parents = 1, 1875 .flags = CLK_SET_RATE_PARENT, 1876 .ops = &clk_branch2_ops, 1877 }, 1878 }, 1879 }; 1880 1881 static struct clk_branch gcc_pcie3x1_1_ahb_clk = { 1882 .halt_reg = 0x2a00c, 1883 .halt_check = BRANCH_HALT, 1884 .clkr = { 1885 .enable_reg = 0x2a00c, 1886 .enable_mask = BIT(0), 1887 .hw.init = &(const struct clk_init_data) { 1888 .name = "gcc_pcie3x1_1_ahb_clk", 1889 .parent_hws = (const struct clk_hw*[]) { 1890 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1891 }, 1892 .num_parents = 1, 1893 .flags = CLK_SET_RATE_PARENT, 1894 .ops = &clk_branch2_ops, 1895 }, 1896 }, 1897 }; 1898 1899 static struct clk_branch gcc_pcie3x1_1_aux_clk = { 1900 .halt_reg = 0x2a070, 1901 .halt_check = BRANCH_HALT, 1902 .clkr = { 1903 .enable_reg = 0x2a070, 1904 .enable_mask = BIT(0), 1905 .hw.init = &(const struct clk_init_data) { 1906 .name = "gcc_pcie3x1_1_aux_clk", 1907 .parent_hws = (const struct clk_hw*[]) { 1908 &gcc_pcie_aux_clk_src.clkr.hw, 1909 }, 1910 .num_parents = 1, 1911 .flags = CLK_SET_RATE_PARENT, 1912 .ops = &clk_branch2_ops, 1913 }, 1914 }, 1915 }; 1916 1917 static struct clk_branch gcc_pcie3x1_1_axi_m_clk = { 1918 .halt_reg = 0x2a014, 1919 .halt_check = BRANCH_HALT, 1920 .clkr = { 1921 .enable_reg = 0x2a014, 1922 .enable_mask = BIT(0), 1923 .hw.init = &(const struct clk_init_data) { 1924 .name = "gcc_pcie3x1_1_axi_m_clk", 1925 .parent_hws = (const struct clk_hw*[]) { 1926 &gcc_pcie3x1_1_axi_clk_src.clkr.hw, 1927 }, 1928 .num_parents = 1, 1929 .flags = CLK_SET_RATE_PARENT, 1930 .ops = &clk_branch2_ops, 1931 }, 1932 }, 1933 }; 1934 1935 static struct clk_branch gcc_pcie3x1_1_axi_s_bridge_clk = { 1936 .halt_reg = 0x2a024, 1937 .halt_check = BRANCH_HALT, 1938 .clkr = { 1939 .enable_reg = 0x2a024, 1940 .enable_mask = BIT(0), 1941 .hw.init = &(const struct clk_init_data) { 1942 .name = "gcc_pcie3x1_1_axi_s_bridge_clk", 1943 .parent_hws = (const struct clk_hw*[]) { 1944 &gcc_pcie3x1_1_axi_clk_src.clkr.hw, 1945 }, 1946 .num_parents = 1, 1947 .flags = CLK_SET_RATE_PARENT, 1948 .ops = &clk_branch2_ops, 1949 }, 1950 }, 1951 }; 1952 1953 static struct clk_branch gcc_pcie3x1_1_axi_s_clk = { 1954 .halt_reg = 0x2a01c, 1955 .halt_check = BRANCH_HALT, 1956 .clkr = { 1957 .enable_reg = 0x2a01c, 1958 .enable_mask = BIT(0), 1959 .hw.init = &(const struct clk_init_data) { 1960 .name = "gcc_pcie3x1_1_axi_s_clk", 1961 .parent_hws = (const struct clk_hw*[]) { 1962 &gcc_pcie3x1_1_axi_clk_src.clkr.hw, 1963 }, 1964 .num_parents = 1, 1965 .flags = CLK_SET_RATE_PARENT, 1966 .ops = &clk_branch2_ops, 1967 }, 1968 }, 1969 }; 1970 1971 static struct clk_branch gcc_pcie3x1_1_pipe_clk = { 1972 .halt_reg = 0x2a068, 1973 .halt_check = BRANCH_HALT_DELAY, 1974 .clkr = { 1975 .enable_reg = 0x2a068, 1976 .enable_mask = BIT(0), 1977 .hw.init = &(const struct clk_init_data) { 1978 .name = "gcc_pcie3x1_1_pipe_clk", 1979 .parent_hws = (const struct clk_hw*[]) { 1980 &gcc_pcie3x1_1_pipe_clk_src.clkr.hw, 1981 }, 1982 .num_parents = 1, 1983 .flags = CLK_SET_RATE_PARENT, 1984 .ops = &clk_branch2_ops, 1985 }, 1986 }, 1987 }; 1988 1989 static struct clk_branch gcc_pcie3x1_phy_ahb_clk = { 1990 .halt_reg = 0x29078, 1991 .halt_check = BRANCH_HALT, 1992 .clkr = { 1993 .enable_reg = 0x29078, 1994 .enable_mask = BIT(0), 1995 .hw.init = &(const struct clk_init_data) { 1996 .name = "gcc_pcie3x1_phy_ahb_clk", 1997 .parent_hws = (const struct clk_hw*[]) { 1998 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 1999 }, 2000 .num_parents = 1, 2001 .flags = CLK_SET_RATE_PARENT, 2002 .ops = &clk_branch2_ops, 2003 }, 2004 }, 2005 }; 2006 2007 static struct clk_branch gcc_pcie3x2_ahb_clk = { 2008 .halt_reg = 0x28030, 2009 .halt_check = BRANCH_HALT, 2010 .clkr = { 2011 .enable_reg = 0x28030, 2012 .enable_mask = BIT(0), 2013 .hw.init = &(const struct clk_init_data) { 2014 .name = "gcc_pcie3x2_ahb_clk", 2015 .parent_hws = (const struct clk_hw*[]) { 2016 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2017 }, 2018 .num_parents = 1, 2019 .flags = CLK_SET_RATE_PARENT, 2020 .ops = &clk_branch2_ops, 2021 }, 2022 }, 2023 }; 2024 2025 static struct clk_branch gcc_pcie3x2_aux_clk = { 2026 .halt_reg = 0x28070, 2027 .halt_check = BRANCH_HALT, 2028 .clkr = { 2029 .enable_reg = 0x28070, 2030 .enable_mask = BIT(0), 2031 .hw.init = &(const struct clk_init_data) { 2032 .name = "gcc_pcie3x2_aux_clk", 2033 .parent_hws = (const struct clk_hw*[]) { 2034 &gcc_pcie_aux_clk_src.clkr.hw, 2035 }, 2036 .num_parents = 1, 2037 .flags = CLK_SET_RATE_PARENT, 2038 .ops = &clk_branch2_ops, 2039 }, 2040 }, 2041 }; 2042 2043 static struct clk_branch gcc_pcie3x2_axi_m_clk = { 2044 .halt_reg = 0x28038, 2045 .halt_check = BRANCH_HALT, 2046 .clkr = { 2047 .enable_reg = 0x28038, 2048 .enable_mask = BIT(0), 2049 .hw.init = &(const struct clk_init_data) { 2050 .name = "gcc_pcie3x2_axi_m_clk", 2051 .parent_hws = (const struct clk_hw*[]) { 2052 &gcc_pcie3x2_axi_m_clk_src.clkr.hw, 2053 }, 2054 .num_parents = 1, 2055 .flags = CLK_SET_RATE_PARENT, 2056 .ops = &clk_branch2_ops, 2057 }, 2058 }, 2059 }; 2060 2061 static struct clk_branch gcc_pcie3x2_axi_s_bridge_clk = { 2062 .halt_reg = 0x28048, 2063 .halt_check = BRANCH_HALT, 2064 .clkr = { 2065 .enable_reg = 0x28048, 2066 .enable_mask = BIT(0), 2067 .hw.init = &(const struct clk_init_data) { 2068 .name = "gcc_pcie3x2_axi_s_bridge_clk", 2069 .parent_hws = (const struct clk_hw*[]) { 2070 &gcc_pcie3x2_axi_s_clk_src.clkr.hw, 2071 }, 2072 .num_parents = 1, 2073 .flags = CLK_SET_RATE_PARENT, 2074 .ops = &clk_branch2_ops, 2075 }, 2076 }, 2077 }; 2078 2079 static struct clk_branch gcc_pcie3x2_axi_s_clk = { 2080 .halt_reg = 0x28040, 2081 .halt_check = BRANCH_HALT, 2082 .clkr = { 2083 .enable_reg = 0x28040, 2084 .enable_mask = BIT(0), 2085 .hw.init = &(const struct clk_init_data) { 2086 .name = "gcc_pcie3x2_axi_s_clk", 2087 .parent_hws = (const struct clk_hw*[]) { 2088 &gcc_pcie3x2_axi_s_clk_src.clkr.hw, 2089 }, 2090 .num_parents = 1, 2091 .flags = CLK_SET_RATE_PARENT, 2092 .ops = &clk_branch2_ops, 2093 }, 2094 }, 2095 }; 2096 2097 static struct clk_branch gcc_pcie3x2_phy_ahb_clk = { 2098 .halt_reg = 0x28080, 2099 .halt_check = BRANCH_HALT, 2100 .clkr = { 2101 .enable_reg = 0x28080, 2102 .enable_mask = BIT(0), 2103 .hw.init = &(const struct clk_init_data) { 2104 .name = "gcc_pcie3x2_phy_ahb_clk", 2105 .parent_hws = (const struct clk_hw*[]) { 2106 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2107 }, 2108 .num_parents = 1, 2109 .flags = CLK_SET_RATE_PARENT, 2110 .ops = &clk_branch2_ops, 2111 }, 2112 }, 2113 }; 2114 2115 static struct clk_branch gcc_pcie3x2_pipe_clk = { 2116 .halt_reg = 0x28068, 2117 .halt_check = BRANCH_HALT_DELAY, 2118 .clkr = { 2119 .enable_reg = 0x28068, 2120 .enable_mask = BIT(0), 2121 .hw.init = &(const struct clk_init_data) { 2122 .name = "gcc_pcie3x2_pipe_clk", 2123 .parent_hws = (const struct clk_hw*[]) { 2124 &gcc_pcie3x2_pipe_clk_src.clkr.hw, 2125 }, 2126 .num_parents = 1, 2127 .flags = CLK_SET_RATE_PARENT, 2128 .ops = &clk_branch2_ops, 2129 }, 2130 }, 2131 }; 2132 2133 static struct clk_branch gcc_pcnoc_at_clk = { 2134 .halt_reg = 0x31024, 2135 .halt_check = BRANCH_HALT_VOTED, 2136 .clkr = { 2137 .enable_reg = 0x31024, 2138 .enable_mask = BIT(0), 2139 .hw.init = &(const struct clk_init_data) { 2140 .name = "gcc_pcnoc_at_clk", 2141 .parent_hws = (const struct clk_hw*[]) { 2142 &gcc_qdss_at_clk_src.clkr.hw, 2143 }, 2144 .num_parents = 1, 2145 .flags = CLK_SET_RATE_PARENT, 2146 .ops = &clk_branch2_ops, 2147 }, 2148 }, 2149 }; 2150 2151 static struct clk_branch gcc_pcnoc_lpass_clk = { 2152 .halt_reg = 0x31020, 2153 .halt_check = BRANCH_HALT, 2154 .clkr = { 2155 .enable_reg = 0x31020, 2156 .enable_mask = BIT(0), 2157 .hw.init = &(const struct clk_init_data) { 2158 .name = "gcc_pcnoc_lpass_clk", 2159 .parent_hws = (const struct clk_hw*[]) { 2160 &gcc_lpass_sway_clk_src.clkr.hw, 2161 }, 2162 .num_parents = 1, 2163 .flags = CLK_SET_RATE_PARENT, 2164 .ops = &clk_branch2_ops, 2165 }, 2166 }, 2167 }; 2168 2169 static struct clk_branch gcc_prng_ahb_clk = { 2170 .halt_reg = 0x13024, 2171 .halt_check = BRANCH_HALT_VOTED, 2172 .clkr = { 2173 .enable_reg = 0xb004, 2174 .enable_mask = BIT(10), 2175 .hw.init = &(const struct clk_init_data) { 2176 .name = "gcc_prng_ahb_clk", 2177 .parent_hws = (const struct clk_hw*[]) { 2178 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2179 }, 2180 .num_parents = 1, 2181 .flags = CLK_SET_RATE_PARENT, 2182 .ops = &clk_branch2_ops, 2183 }, 2184 }, 2185 }; 2186 2187 static struct clk_branch gcc_qdss_at_clk = { 2188 .halt_reg = 0x2d038, 2189 .halt_check = BRANCH_HALT_VOTED, 2190 .clkr = { 2191 .enable_reg = 0x2d038, 2192 .enable_mask = BIT(0), 2193 .hw.init = &(const struct clk_init_data) { 2194 .name = "gcc_qdss_at_clk", 2195 .parent_hws = (const struct clk_hw*[]) { 2196 &gcc_qdss_at_clk_src.clkr.hw, 2197 }, 2198 .num_parents = 1, 2199 .flags = CLK_SET_RATE_PARENT, 2200 .ops = &clk_branch2_ops, 2201 }, 2202 }, 2203 }; 2204 2205 static struct clk_branch gcc_qdss_cfg_ahb_clk = { 2206 .halt_reg = 0x2d06c, 2207 .halt_check = BRANCH_HALT_VOTED, 2208 .clkr = { 2209 .enable_reg = 0x2d06c, 2210 .enable_mask = BIT(0), 2211 .hw.init = &(const struct clk_init_data) { 2212 .name = "gcc_qdss_cfg_ahb_clk", 2213 .parent_hws = (const struct clk_hw*[]) { 2214 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2215 }, 2216 .num_parents = 1, 2217 .flags = CLK_SET_RATE_PARENT, 2218 .ops = &clk_branch2_ops, 2219 }, 2220 }, 2221 }; 2222 2223 static struct clk_branch gcc_qdss_dap_ahb_clk = { 2224 .halt_reg = 0x2d068, 2225 .halt_check = BRANCH_HALT_VOTED, 2226 .clkr = { 2227 .enable_reg = 0x2d068, 2228 .enable_mask = BIT(0), 2229 .hw.init = &(const struct clk_init_data) { 2230 .name = "gcc_qdss_dap_ahb_clk", 2231 .parent_hws = (const struct clk_hw*[]) { 2232 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2233 }, 2234 .num_parents = 1, 2235 .flags = CLK_SET_RATE_PARENT, 2236 .ops = &clk_branch2_ops, 2237 }, 2238 }, 2239 }; 2240 2241 static struct clk_branch gcc_qdss_dap_clk = { 2242 .halt_reg = 0x2d05c, 2243 .halt_check = BRANCH_HALT_VOTED, 2244 .clkr = { 2245 .enable_reg = 0xb004, 2246 .enable_mask = BIT(2), 2247 .hw.init = &(const struct clk_init_data) { 2248 .name = "gcc_qdss_dap_clk", 2249 .parent_hws = (const struct clk_hw*[]) { 2250 &gcc_qdss_dap_div_clk_src.clkr.hw, 2251 }, 2252 .num_parents = 1, 2253 .flags = CLK_SET_RATE_PARENT, 2254 .ops = &clk_branch2_ops, 2255 }, 2256 }, 2257 }; 2258 2259 static struct clk_branch gcc_qdss_etr_usb_clk = { 2260 .halt_reg = 0x2d064, 2261 .halt_check = BRANCH_HALT_VOTED, 2262 .clkr = { 2263 .enable_reg = 0x2d064, 2264 .enable_mask = BIT(0), 2265 .hw.init = &(const struct clk_init_data) { 2266 .name = "gcc_qdss_etr_usb_clk", 2267 .parent_hws = (const struct clk_hw*[]) { 2268 &gcc_system_noc_bfdcd_clk_src.clkr.hw, 2269 }, 2270 .num_parents = 1, 2271 .flags = CLK_SET_RATE_PARENT, 2272 .ops = &clk_branch2_ops, 2273 }, 2274 }, 2275 }; 2276 2277 static struct clk_fixed_factor gcc_eud_at_div_clk_src = { 2278 .mult = 1, 2279 .div = 6, 2280 .hw.init = &(struct clk_init_data) { 2281 .name = "gcc_eud_at_div_clk_src", 2282 .parent_hws = (const struct clk_hw *[]) { 2283 &gcc_qdss_at_clk_src.clkr.hw }, 2284 .num_parents = 1, 2285 .flags = CLK_SET_RATE_PARENT, 2286 .ops = &clk_fixed_factor_ops, 2287 }, 2288 }; 2289 2290 static struct clk_branch gcc_qdss_eud_at_clk = { 2291 .halt_reg = 0x2d070, 2292 .halt_check = BRANCH_HALT_VOTED, 2293 .clkr = { 2294 .enable_reg = 0x2d070, 2295 .enable_mask = BIT(0), 2296 .hw.init = &(const struct clk_init_data) { 2297 .name = "gcc_qdss_eud_at_clk", 2298 .parent_hws = (const struct clk_hw*[]) { 2299 &gcc_eud_at_div_clk_src.hw, 2300 }, 2301 .num_parents = 1, 2302 .flags = CLK_SET_RATE_PARENT, 2303 .ops = &clk_branch2_ops, 2304 }, 2305 }, 2306 }; 2307 2308 static struct clk_branch gcc_qpic_ahb_clk = { 2309 .halt_reg = 0x32010, 2310 .halt_check = BRANCH_HALT, 2311 .clkr = { 2312 .enable_reg = 0x32010, 2313 .enable_mask = BIT(0), 2314 .hw.init = &(const struct clk_init_data) { 2315 .name = "gcc_qpic_ahb_clk", 2316 .parent_hws = (const struct clk_hw*[]) { 2317 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2318 }, 2319 .num_parents = 1, 2320 .flags = CLK_SET_RATE_PARENT, 2321 .ops = &clk_branch2_ops, 2322 }, 2323 }, 2324 }; 2325 2326 static struct clk_branch gcc_qpic_clk = { 2327 .halt_reg = 0x32014, 2328 .halt_check = BRANCH_HALT, 2329 .clkr = { 2330 .enable_reg = 0x32014, 2331 .enable_mask = BIT(0), 2332 .hw.init = &(const struct clk_init_data) { 2333 .name = "gcc_qpic_clk", 2334 .parent_hws = (const struct clk_hw*[]) { 2335 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2336 }, 2337 .num_parents = 1, 2338 .flags = CLK_SET_RATE_PARENT, 2339 .ops = &clk_branch2_ops, 2340 }, 2341 }, 2342 }; 2343 2344 static struct clk_branch gcc_qpic_io_macro_clk = { 2345 .halt_reg = 0x3200c, 2346 .halt_check = BRANCH_HALT, 2347 .clkr = { 2348 .enable_reg = 0x3200c, 2349 .enable_mask = BIT(0), 2350 .hw.init = &(const struct clk_init_data) { 2351 .name = "gcc_qpic_io_macro_clk", 2352 .parent_hws = (const struct clk_hw*[]) { 2353 &gcc_qpic_io_macro_clk_src.clkr.hw, 2354 }, 2355 .num_parents = 1, 2356 .flags = CLK_SET_RATE_PARENT, 2357 .ops = &clk_branch2_ops, 2358 }, 2359 }, 2360 }; 2361 2362 static struct clk_branch gcc_qpic_sleep_clk = { 2363 .halt_reg = 0x3201c, 2364 .halt_check = BRANCH_HALT, 2365 .clkr = { 2366 .enable_reg = 0x3201c, 2367 .enable_mask = BIT(0), 2368 .hw.init = &(const struct clk_init_data) { 2369 .name = "gcc_qpic_sleep_clk", 2370 .parent_hws = (const struct clk_hw*[]) { 2371 &gcc_sleep_clk_src.clkr.hw, 2372 }, 2373 .num_parents = 1, 2374 .flags = CLK_SET_RATE_PARENT, 2375 .ops = &clk_branch2_ops, 2376 }, 2377 }, 2378 }; 2379 2380 static struct clk_branch gcc_sdcc1_ahb_clk = { 2381 .halt_reg = 0x33034, 2382 .halt_check = BRANCH_HALT, 2383 .clkr = { 2384 .enable_reg = 0x33034, 2385 .enable_mask = BIT(0), 2386 .hw.init = &(const struct clk_init_data) { 2387 .name = "gcc_sdcc1_ahb_clk", 2388 .parent_hws = (const struct clk_hw*[]) { 2389 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2390 }, 2391 .num_parents = 1, 2392 .flags = CLK_SET_RATE_PARENT, 2393 .ops = &clk_branch2_ops, 2394 }, 2395 }, 2396 }; 2397 2398 static struct clk_branch gcc_sdcc1_apps_clk = { 2399 .halt_reg = 0x3302c, 2400 .halt_check = BRANCH_HALT, 2401 .clkr = { 2402 .enable_reg = 0x3302c, 2403 .enable_mask = BIT(0), 2404 .hw.init = &(const struct clk_init_data) { 2405 .name = "gcc_sdcc1_apps_clk", 2406 .parent_hws = (const struct clk_hw*[]) { 2407 &gcc_sdcc1_apps_clk_src.clkr.hw, 2408 }, 2409 .num_parents = 1, 2410 .flags = CLK_SET_RATE_PARENT, 2411 .ops = &clk_branch2_ops, 2412 }, 2413 }, 2414 }; 2415 2416 static struct clk_branch gcc_snoc_lpass_cfg_clk = { 2417 .halt_reg = 0x2e028, 2418 .halt_check = BRANCH_HALT, 2419 .clkr = { 2420 .enable_reg = 0x2e028, 2421 .enable_mask = BIT(0), 2422 .hw.init = &(const struct clk_init_data) { 2423 .name = "gcc_snoc_lpass_cfg_clk", 2424 .parent_hws = (const struct clk_hw*[]) { 2425 &gcc_lpass_sway_clk_src.clkr.hw, 2426 }, 2427 .num_parents = 1, 2428 .flags = CLK_SET_RATE_PARENT, 2429 .ops = &clk_branch2_ops, 2430 }, 2431 }, 2432 }; 2433 2434 static struct clk_branch gcc_snoc_nssnoc_1_clk = { 2435 .halt_reg = 0x17090, 2436 .halt_check = BRANCH_HALT, 2437 .clkr = { 2438 .enable_reg = 0x17090, 2439 .enable_mask = BIT(0), 2440 .hw.init = &(const struct clk_init_data) { 2441 .name = "gcc_snoc_nssnoc_1_clk", 2442 .parent_hws = (const struct clk_hw*[]) { 2443 &gcc_system_noc_bfdcd_clk_src.clkr.hw, 2444 }, 2445 .num_parents = 1, 2446 .flags = CLK_SET_RATE_PARENT, 2447 .ops = &clk_branch2_ops, 2448 }, 2449 }, 2450 }; 2451 2452 static struct clk_branch gcc_snoc_nssnoc_clk = { 2453 .halt_reg = 0x17084, 2454 .halt_check = BRANCH_HALT, 2455 .clkr = { 2456 .enable_reg = 0x17084, 2457 .enable_mask = BIT(0), 2458 .hw.init = &(const struct clk_init_data) { 2459 .name = "gcc_snoc_nssnoc_clk", 2460 .parent_hws = (const struct clk_hw*[]) { 2461 &gcc_system_noc_bfdcd_clk_src.clkr.hw, 2462 }, 2463 .num_parents = 1, 2464 .flags = CLK_SET_RATE_PARENT, 2465 .ops = &clk_branch2_ops, 2466 }, 2467 }, 2468 }; 2469 2470 static struct clk_branch gcc_snoc_pcie3_1lane_1_m_clk = { 2471 .halt_reg = 0x2e050, 2472 .halt_check = BRANCH_HALT, 2473 .clkr = { 2474 .enable_reg = 0x2e050, 2475 .enable_mask = BIT(0), 2476 .hw.init = &(const struct clk_init_data) { 2477 .name = "gcc_snoc_pcie3_1lane_1_m_clk", 2478 .parent_hws = (const struct clk_hw*[]) { 2479 &gcc_pcie3x1_1_axi_clk_src.clkr.hw, 2480 }, 2481 .num_parents = 1, 2482 .flags = CLK_SET_RATE_PARENT, 2483 .ops = &clk_branch2_ops, 2484 }, 2485 }, 2486 }; 2487 2488 static struct clk_branch gcc_snoc_pcie3_1lane_1_s_clk = { 2489 .halt_reg = 0x2e0ac, 2490 .halt_check = BRANCH_HALT, 2491 .clkr = { 2492 .enable_reg = 0x2e0ac, 2493 .enable_mask = BIT(0), 2494 .hw.init = &(const struct clk_init_data) { 2495 .name = "gcc_snoc_pcie3_1lane_1_s_clk", 2496 .parent_hws = (const struct clk_hw*[]) { 2497 &gcc_pcie3x1_1_axi_clk_src.clkr.hw, 2498 }, 2499 .num_parents = 1, 2500 .flags = CLK_SET_RATE_PARENT, 2501 .ops = &clk_branch2_ops, 2502 }, 2503 }, 2504 }; 2505 2506 static struct clk_branch gcc_snoc_pcie3_1lane_m_clk = { 2507 .halt_reg = 0x2e080, 2508 .halt_check = BRANCH_HALT, 2509 .clkr = { 2510 .enable_reg = 0x2e080, 2511 .enable_mask = BIT(0), 2512 .hw.init = &(const struct clk_init_data) { 2513 .name = "gcc_snoc_pcie3_1lane_m_clk", 2514 .parent_hws = (const struct clk_hw*[]) { 2515 &gcc_pcie3x1_0_axi_clk_src.clkr.hw, 2516 }, 2517 .num_parents = 1, 2518 .flags = CLK_SET_RATE_PARENT, 2519 .ops = &clk_branch2_ops, 2520 }, 2521 }, 2522 }; 2523 2524 static struct clk_branch gcc_snoc_pcie3_1lane_s_clk = { 2525 .halt_reg = 0x2e04c, 2526 .halt_check = BRANCH_HALT, 2527 .clkr = { 2528 .enable_reg = 0x2e04c, 2529 .enable_mask = BIT(0), 2530 .hw.init = &(const struct clk_init_data) { 2531 .name = "gcc_snoc_pcie3_1lane_s_clk", 2532 .parent_hws = (const struct clk_hw*[]) { 2533 &gcc_pcie3x1_0_axi_clk_src.clkr.hw, 2534 }, 2535 .num_parents = 1, 2536 .flags = CLK_SET_RATE_PARENT, 2537 .ops = &clk_branch2_ops, 2538 }, 2539 }, 2540 }; 2541 2542 static struct clk_branch gcc_snoc_pcie3_2lane_m_clk = { 2543 .halt_reg = 0x2e07c, 2544 .halt_check = BRANCH_HALT, 2545 .clkr = { 2546 .enable_reg = 0x2e07c, 2547 .enable_mask = BIT(0), 2548 .hw.init = &(const struct clk_init_data) { 2549 .name = "gcc_snoc_pcie3_2lane_m_clk", 2550 .parent_hws = (const struct clk_hw*[]) { 2551 &gcc_pcie3x2_axi_m_clk_src.clkr.hw, 2552 }, 2553 .num_parents = 1, 2554 .flags = CLK_SET_RATE_PARENT, 2555 .ops = &clk_branch2_ops, 2556 }, 2557 }, 2558 }; 2559 2560 static struct clk_branch gcc_snoc_pcie3_2lane_s_clk = { 2561 .halt_reg = 0x2e048, 2562 .halt_check = BRANCH_HALT, 2563 .clkr = { 2564 .enable_reg = 0x2e048, 2565 .enable_mask = BIT(0), 2566 .hw.init = &(const struct clk_init_data) { 2567 .name = "gcc_snoc_pcie3_2lane_s_clk", 2568 .parent_hws = (const struct clk_hw*[]) { 2569 &gcc_pcie3x2_axi_s_clk_src.clkr.hw, 2570 }, 2571 .num_parents = 1, 2572 .flags = CLK_SET_RATE_PARENT, 2573 .ops = &clk_branch2_ops, 2574 }, 2575 }, 2576 }; 2577 2578 static struct clk_branch gcc_snoc_usb_clk = { 2579 .halt_reg = 0x2e058, 2580 .halt_check = BRANCH_HALT_VOTED, 2581 .clkr = { 2582 .enable_reg = 0x2e058, 2583 .enable_mask = BIT(0), 2584 .hw.init = &(const struct clk_init_data) { 2585 .name = "gcc_snoc_usb_clk", 2586 .parent_hws = (const struct clk_hw*[]) { 2587 &gcc_usb0_master_clk_src.clkr.hw, 2588 }, 2589 .num_parents = 1, 2590 .flags = CLK_SET_RATE_PARENT, 2591 .ops = &clk_branch2_ops, 2592 }, 2593 }, 2594 }; 2595 2596 static struct clk_branch gcc_sys_noc_at_clk = { 2597 .halt_reg = 0x2e038, 2598 .halt_check = BRANCH_HALT_VOTED, 2599 .clkr = { 2600 .enable_reg = 0x2e038, 2601 .enable_mask = BIT(0), 2602 .hw.init = &(const struct clk_init_data) { 2603 .name = "gcc_sys_noc_at_clk", 2604 .parent_hws = (const struct clk_hw*[]) { 2605 &gcc_qdss_at_clk_src.clkr.hw, 2606 }, 2607 .num_parents = 1, 2608 .flags = CLK_SET_RATE_PARENT, 2609 .ops = &clk_branch2_ops, 2610 }, 2611 }, 2612 }; 2613 2614 static struct clk_branch gcc_uniphy0_ahb_clk = { 2615 .halt_reg = 0x16010, 2616 .halt_check = BRANCH_HALT, 2617 .clkr = { 2618 .enable_reg = 0x16010, 2619 .enable_mask = BIT(0), 2620 .hw.init = &(const struct clk_init_data) { 2621 .name = "gcc_uniphy0_ahb_clk", 2622 .parent_hws = (const struct clk_hw*[]) { 2623 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2624 }, 2625 .num_parents = 1, 2626 .flags = CLK_SET_RATE_PARENT, 2627 .ops = &clk_branch2_ops, 2628 }, 2629 }, 2630 }; 2631 2632 static struct clk_branch gcc_uniphy0_sys_clk = { 2633 .halt_reg = 0x1600c, 2634 .halt_check = BRANCH_HALT, 2635 .clkr = { 2636 .enable_reg = 0x1600c, 2637 .enable_mask = BIT(0), 2638 .hw.init = &(const struct clk_init_data) { 2639 .name = "gcc_uniphy0_sys_clk", 2640 .parent_hws = (const struct clk_hw*[]) { 2641 &gcc_uniphy_sys_clk_src.clkr.hw, 2642 }, 2643 .num_parents = 1, 2644 .flags = CLK_SET_RATE_PARENT, 2645 .ops = &clk_branch2_ops, 2646 }, 2647 }, 2648 }; 2649 2650 static struct clk_branch gcc_uniphy1_ahb_clk = { 2651 .halt_reg = 0x1601c, 2652 .halt_check = BRANCH_HALT, 2653 .clkr = { 2654 .enable_reg = 0x1601c, 2655 .enable_mask = BIT(0), 2656 .hw.init = &(const struct clk_init_data) { 2657 .name = "gcc_uniphy1_ahb_clk", 2658 .parent_hws = (const struct clk_hw*[]) { 2659 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2660 }, 2661 .num_parents = 1, 2662 .flags = CLK_SET_RATE_PARENT, 2663 .ops = &clk_branch2_ops, 2664 }, 2665 }, 2666 }; 2667 2668 static struct clk_branch gcc_uniphy1_sys_clk = { 2669 .halt_reg = 0x16018, 2670 .halt_check = BRANCH_HALT, 2671 .clkr = { 2672 .enable_reg = 0x16018, 2673 .enable_mask = BIT(0), 2674 .hw.init = &(const struct clk_init_data) { 2675 .name = "gcc_uniphy1_sys_clk", 2676 .parent_hws = (const struct clk_hw*[]) { 2677 &gcc_uniphy_sys_clk_src.clkr.hw, 2678 }, 2679 .num_parents = 1, 2680 .flags = CLK_SET_RATE_PARENT, 2681 .ops = &clk_branch2_ops, 2682 }, 2683 }, 2684 }; 2685 2686 static struct clk_branch gcc_usb0_aux_clk = { 2687 .halt_reg = 0x2c050, 2688 .halt_check = BRANCH_HALT_VOTED, 2689 .clkr = { 2690 .enable_reg = 0x2c050, 2691 .enable_mask = BIT(0), 2692 .hw.init = &(const struct clk_init_data) { 2693 .name = "gcc_usb0_aux_clk", 2694 .parent_hws = (const struct clk_hw*[]) { 2695 &gcc_usb0_aux_clk_src.clkr.hw, 2696 }, 2697 .num_parents = 1, 2698 .flags = CLK_SET_RATE_PARENT, 2699 .ops = &clk_branch2_ops, 2700 }, 2701 }, 2702 }; 2703 2704 static struct clk_branch gcc_usb0_eud_at_clk = { 2705 .halt_reg = 0x30004, 2706 .halt_check = BRANCH_HALT_VOTED, 2707 .clkr = { 2708 .enable_reg = 0x30004, 2709 .enable_mask = BIT(0), 2710 .hw.init = &(const struct clk_init_data) { 2711 .name = "gcc_usb0_eud_at_clk", 2712 .parent_hws = (const struct clk_hw*[]) { 2713 &gcc_eud_at_div_clk_src.hw, 2714 }, 2715 .num_parents = 1, 2716 .flags = CLK_SET_RATE_PARENT, 2717 .ops = &clk_branch2_ops, 2718 }, 2719 }, 2720 }; 2721 2722 static struct clk_branch gcc_usb0_lfps_clk = { 2723 .halt_reg = 0x2c090, 2724 .halt_check = BRANCH_HALT_VOTED, 2725 .clkr = { 2726 .enable_reg = 0x2c090, 2727 .enable_mask = BIT(0), 2728 .hw.init = &(const struct clk_init_data) { 2729 .name = "gcc_usb0_lfps_clk", 2730 .parent_hws = (const struct clk_hw*[]) { 2731 &gcc_usb0_lfps_clk_src.clkr.hw, 2732 }, 2733 .num_parents = 1, 2734 .flags = CLK_SET_RATE_PARENT, 2735 .ops = &clk_branch2_ops, 2736 }, 2737 }, 2738 }; 2739 2740 static struct clk_branch gcc_usb0_master_clk = { 2741 .halt_reg = 0x2c048, 2742 .halt_check = BRANCH_HALT_VOTED, 2743 .clkr = { 2744 .enable_reg = 0x2c048, 2745 .enable_mask = BIT(0), 2746 .hw.init = &(const struct clk_init_data) { 2747 .name = "gcc_usb0_master_clk", 2748 .parent_hws = (const struct clk_hw*[]) { 2749 &gcc_usb0_master_clk_src.clkr.hw, 2750 }, 2751 .num_parents = 1, 2752 .flags = CLK_SET_RATE_PARENT, 2753 .ops = &clk_branch2_ops, 2754 }, 2755 }, 2756 }; 2757 2758 static struct clk_branch gcc_usb0_mock_utmi_clk = { 2759 .halt_reg = 0x2c054, 2760 .clkr = { 2761 .enable_reg = 0x2c054, 2762 .enable_mask = BIT(0), 2763 .hw.init = &(const struct clk_init_data) { 2764 .name = "gcc_usb0_mock_utmi_clk", 2765 .parent_hws = (const struct clk_hw*[]) { 2766 &gcc_usb0_mock_utmi_div_clk_src.clkr.hw, 2767 }, 2768 .num_parents = 1, 2769 .flags = CLK_SET_RATE_PARENT, 2770 .ops = &clk_branch2_ops, 2771 }, 2772 }, 2773 }; 2774 2775 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = { 2776 .halt_reg = 0x2c05c, 2777 .halt_check = BRANCH_HALT_VOTED, 2778 .clkr = { 2779 .enable_reg = 0x2c05c, 2780 .enable_mask = BIT(0), 2781 .hw.init = &(const struct clk_init_data) { 2782 .name = "gcc_usb0_phy_cfg_ahb_clk", 2783 .parent_hws = (const struct clk_hw*[]) { 2784 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2785 }, 2786 .num_parents = 1, 2787 .flags = CLK_SET_RATE_PARENT, 2788 .ops = &clk_branch2_ops, 2789 }, 2790 }, 2791 }; 2792 2793 static struct clk_branch gcc_usb0_pipe_clk = { 2794 .halt_reg = 0x2c078, 2795 .halt_check = BRANCH_HALT_DELAY, 2796 .clkr = { 2797 .enable_reg = 0x2c078, 2798 .enable_mask = BIT(0), 2799 .hw.init = &(const struct clk_init_data) { 2800 .name = "gcc_usb0_pipe_clk", 2801 .parent_hws = (const struct clk_hw*[]) { 2802 &gcc_usb0_pipe_clk_src.clkr.hw, 2803 }, 2804 .num_parents = 1, 2805 .flags = CLK_SET_RATE_PARENT, 2806 .ops = &clk_branch2_ops, 2807 }, 2808 }, 2809 }; 2810 2811 static struct clk_branch gcc_usb0_sleep_clk = { 2812 .halt_reg = 0x2c058, 2813 .halt_check = BRANCH_HALT_VOTED, 2814 .clkr = { 2815 .enable_reg = 0x2c058, 2816 .enable_mask = BIT(0), 2817 .hw.init = &(const struct clk_init_data) { 2818 .name = "gcc_usb0_sleep_clk", 2819 .parent_hws = (const struct clk_hw*[]) { 2820 &gcc_sleep_clk_src.clkr.hw, 2821 }, 2822 .num_parents = 1, 2823 .flags = CLK_SET_RATE_PARENT, 2824 .ops = &clk_branch2_ops, 2825 }, 2826 }, 2827 }; 2828 2829 static struct clk_branch gcc_xo_clk = { 2830 .halt_reg = 0x34018, 2831 .halt_check = BRANCH_HALT, 2832 .clkr = { 2833 .enable_reg = 0x34018, 2834 .enable_mask = BIT(0), 2835 .hw.init = &(const struct clk_init_data) { 2836 .name = "gcc_xo_clk", 2837 .parent_hws = (const struct clk_hw*[]) { 2838 &gcc_xo_clk_src.clkr.hw, 2839 }, 2840 .num_parents = 1, 2841 .flags = CLK_SET_RATE_PARENT, 2842 .ops = &clk_branch2_ops, 2843 }, 2844 }, 2845 }; 2846 2847 static struct clk_branch gcc_xo_div4_clk = { 2848 .halt_reg = 0x3401c, 2849 .halt_check = BRANCH_HALT, 2850 .clkr = { 2851 .enable_reg = 0x3401c, 2852 .enable_mask = BIT(0), 2853 .hw.init = &(const struct clk_init_data) { 2854 .name = "gcc_xo_div4_clk", 2855 .parent_hws = (const struct clk_hw*[]) { 2856 &gcc_xo_div4_clk_src.hw, 2857 }, 2858 .num_parents = 1, 2859 .flags = CLK_SET_RATE_PARENT, 2860 .ops = &clk_branch2_ops, 2861 }, 2862 }, 2863 }; 2864 2865 static struct clk_branch gcc_im_sleep_clk = { 2866 .halt_reg = 0x34020, 2867 .halt_check = BRANCH_HALT, 2868 .clkr = { 2869 .enable_reg = 0x34020, 2870 .enable_mask = BIT(0), 2871 .hw.init = &(const struct clk_init_data) { 2872 .name = "gcc_im_sleep_clk", 2873 .parent_hws = (const struct clk_hw*[]) { 2874 &gcc_sleep_clk_src.clkr.hw, 2875 }, 2876 .num_parents = 1, 2877 .flags = CLK_SET_RATE_PARENT, 2878 .ops = &clk_branch2_ops, 2879 }, 2880 }, 2881 }; 2882 2883 static struct clk_branch gcc_nssnoc_pcnoc_1_clk = { 2884 .halt_reg = 0x17080, 2885 .halt_check = BRANCH_HALT, 2886 .clkr = { 2887 .enable_reg = 0x17080, 2888 .enable_mask = BIT(0), 2889 .hw.init = &(const struct clk_init_data) { 2890 .name = "gcc_nssnoc_pcnoc_1_clk", 2891 .parent_hws = (const struct clk_hw*[]) { 2892 &gcc_pcnoc_bfdcd_clk_src.clkr.hw, 2893 }, 2894 .num_parents = 1, 2895 .flags = CLK_SET_RATE_PARENT, 2896 .ops = &clk_branch2_ops, 2897 }, 2898 }, 2899 }; 2900 2901 static struct clk_regmap_div gcc_snoc_qosgen_extref_div_clk_src = { 2902 .reg = 0x2e010, 2903 .shift = 0, 2904 .width = 2, 2905 .clkr.hw.init = &(const struct clk_init_data) { 2906 .name = "gcc_snoc_qosgen_extref_div_clk_src", 2907 .parent_hws = (const struct clk_hw*[]) { 2908 &gcc_xo_clk_src.clkr.hw, 2909 }, 2910 .num_parents = 1, 2911 .flags = CLK_SET_RATE_PARENT, 2912 .ops = &clk_regmap_div_ro_ops, 2913 }, 2914 }; 2915 2916 static struct clk_regmap *gcc_ipq5332_clocks[] = { 2917 [GPLL0_MAIN] = &gpll0_main.clkr, 2918 [GPLL0] = &gpll0.clkr, 2919 [GPLL2_MAIN] = &gpll2_main.clkr, 2920 [GPLL2] = &gpll2.clkr, 2921 [GPLL4_MAIN] = &gpll4_main.clkr, 2922 [GPLL4] = &gpll4.clkr, 2923 [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr, 2924 [GCC_ADSS_PWM_CLK_SRC] = &gcc_adss_pwm_clk_src.clkr, 2925 [GCC_AHB_CLK] = &gcc_ahb_clk.clkr, 2926 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 2927 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 2928 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 2929 [GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup1_spi_apps_clk_src.clkr, 2930 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 2931 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 2932 [GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup2_spi_apps_clk_src.clkr, 2933 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 2934 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 2935 [GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup3_spi_apps_clk_src.clkr, 2936 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr, 2937 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 2938 [GCC_BLSP1_UART1_APPS_CLK_SRC] = &gcc_blsp1_uart1_apps_clk_src.clkr, 2939 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 2940 [GCC_BLSP1_UART2_APPS_CLK_SRC] = &gcc_blsp1_uart2_apps_clk_src.clkr, 2941 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 2942 [GCC_BLSP1_UART3_APPS_CLK_SRC] = &gcc_blsp1_uart3_apps_clk_src.clkr, 2943 [GCC_CE_AHB_CLK] = &gcc_ce_ahb_clk.clkr, 2944 [GCC_CE_AXI_CLK] = &gcc_ce_axi_clk.clkr, 2945 [GCC_CE_PCNOC_AHB_CLK] = &gcc_ce_pcnoc_ahb_clk.clkr, 2946 [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr, 2947 [GCC_CMN_12GPLL_APU_CLK] = &gcc_cmn_12gpll_apu_clk.clkr, 2948 [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr, 2949 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2950 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 2951 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2952 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 2953 [GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr, 2954 [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr, 2955 [GCC_LPASS_SWAY_CLK_SRC] = &gcc_lpass_sway_clk_src.clkr, 2956 [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr, 2957 [GCC_MDIO_SLAVE_AHB_CLK] = &gcc_mdio_slave_ahb_clk.clkr, 2958 [GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr, 2959 [GCC_NSS_TS_CLK_SRC] = &gcc_nss_ts_clk_src.clkr, 2960 [GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr, 2961 [GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr, 2962 [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr, 2963 [GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr, 2964 [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr, 2965 [GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr, 2966 [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr, 2967 [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr, 2968 [GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr, 2969 [GCC_PCIE3X1_0_AHB_CLK] = &gcc_pcie3x1_0_ahb_clk.clkr, 2970 [GCC_PCIE3X1_0_AUX_CLK] = &gcc_pcie3x1_0_aux_clk.clkr, 2971 [GCC_PCIE3X1_0_AXI_CLK_SRC] = &gcc_pcie3x1_0_axi_clk_src.clkr, 2972 [GCC_PCIE3X1_0_AXI_M_CLK] = &gcc_pcie3x1_0_axi_m_clk.clkr, 2973 [GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK] = &gcc_pcie3x1_0_axi_s_bridge_clk.clkr, 2974 [GCC_PCIE3X1_0_AXI_S_CLK] = &gcc_pcie3x1_0_axi_s_clk.clkr, 2975 [GCC_PCIE3X1_0_PIPE_CLK] = &gcc_pcie3x1_0_pipe_clk.clkr, 2976 [GCC_PCIE3X1_0_RCHG_CLK] = &gcc_pcie3x1_0_rchg_clk.clkr, 2977 [GCC_PCIE3X1_0_RCHG_CLK_SRC] = &gcc_pcie3x1_0_rchg_clk_src.clkr, 2978 [GCC_PCIE3X1_1_AHB_CLK] = &gcc_pcie3x1_1_ahb_clk.clkr, 2979 [GCC_PCIE3X1_1_AUX_CLK] = &gcc_pcie3x1_1_aux_clk.clkr, 2980 [GCC_PCIE3X1_1_AXI_CLK_SRC] = &gcc_pcie3x1_1_axi_clk_src.clkr, 2981 [GCC_PCIE3X1_1_AXI_M_CLK] = &gcc_pcie3x1_1_axi_m_clk.clkr, 2982 [GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK] = &gcc_pcie3x1_1_axi_s_bridge_clk.clkr, 2983 [GCC_PCIE3X1_1_AXI_S_CLK] = &gcc_pcie3x1_1_axi_s_clk.clkr, 2984 [GCC_PCIE3X1_1_PIPE_CLK] = &gcc_pcie3x1_1_pipe_clk.clkr, 2985 [GCC_PCIE3X1_1_RCHG_CLK] = &gcc_pcie3x1_1_rchg_clk.clkr, 2986 [GCC_PCIE3X1_1_RCHG_CLK_SRC] = &gcc_pcie3x1_1_rchg_clk_src.clkr, 2987 [GCC_PCIE3X1_PHY_AHB_CLK] = &gcc_pcie3x1_phy_ahb_clk.clkr, 2988 [GCC_PCIE3X2_AHB_CLK] = &gcc_pcie3x2_ahb_clk.clkr, 2989 [GCC_PCIE3X2_AUX_CLK] = &gcc_pcie3x2_aux_clk.clkr, 2990 [GCC_PCIE3X2_AXI_M_CLK] = &gcc_pcie3x2_axi_m_clk.clkr, 2991 [GCC_PCIE3X2_AXI_M_CLK_SRC] = &gcc_pcie3x2_axi_m_clk_src.clkr, 2992 [GCC_PCIE3X2_AXI_S_BRIDGE_CLK] = &gcc_pcie3x2_axi_s_bridge_clk.clkr, 2993 [GCC_PCIE3X2_AXI_S_CLK] = &gcc_pcie3x2_axi_s_clk.clkr, 2994 [GCC_PCIE3X2_AXI_S_CLK_SRC] = &gcc_pcie3x2_axi_s_clk_src.clkr, 2995 [GCC_PCIE3X2_PHY_AHB_CLK] = &gcc_pcie3x2_phy_ahb_clk.clkr, 2996 [GCC_PCIE3X2_PIPE_CLK] = &gcc_pcie3x2_pipe_clk.clkr, 2997 [GCC_PCIE3X2_RCHG_CLK] = &gcc_pcie3x2_rchg_clk.clkr, 2998 [GCC_PCIE3X2_RCHG_CLK_SRC] = &gcc_pcie3x2_rchg_clk_src.clkr, 2999 [GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr, 3000 [GCC_PCNOC_AT_CLK] = &gcc_pcnoc_at_clk.clkr, 3001 [GCC_PCNOC_BFDCD_CLK_SRC] = &gcc_pcnoc_bfdcd_clk_src.clkr, 3002 [GCC_PCNOC_LPASS_CLK] = &gcc_pcnoc_lpass_clk.clkr, 3003 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3004 [GCC_Q6_AXIM_CLK_SRC] = &gcc_q6_axim_clk_src.clkr, 3005 [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, 3006 [GCC_QDSS_AT_CLK_SRC] = &gcc_qdss_at_clk_src.clkr, 3007 [GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr, 3008 [GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr, 3009 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, 3010 [GCC_QDSS_DAP_DIV_CLK_SRC] = &gcc_qdss_dap_div_clk_src.clkr, 3011 [GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr, 3012 [GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr, 3013 [GCC_QDSS_TSCTR_CLK_SRC] = &gcc_qdss_tsctr_clk_src.clkr, 3014 [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr, 3015 [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr, 3016 [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr, 3017 [GCC_QPIC_IO_MACRO_CLK_SRC] = &gcc_qpic_io_macro_clk_src.clkr, 3018 [GCC_QPIC_SLEEP_CLK] = &gcc_qpic_sleep_clk.clkr, 3019 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 3020 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 3021 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 3022 [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr, 3023 [GCC_SNOC_LPASS_CFG_CLK] = &gcc_snoc_lpass_cfg_clk.clkr, 3024 [GCC_SNOC_NSSNOC_1_CLK] = &gcc_snoc_nssnoc_1_clk.clkr, 3025 [GCC_SNOC_NSSNOC_CLK] = &gcc_snoc_nssnoc_clk.clkr, 3026 [GCC_SNOC_PCIE3_1LANE_1_M_CLK] = &gcc_snoc_pcie3_1lane_1_m_clk.clkr, 3027 [GCC_SNOC_PCIE3_1LANE_1_S_CLK] = &gcc_snoc_pcie3_1lane_1_s_clk.clkr, 3028 [GCC_SNOC_PCIE3_1LANE_M_CLK] = &gcc_snoc_pcie3_1lane_m_clk.clkr, 3029 [GCC_SNOC_PCIE3_1LANE_S_CLK] = &gcc_snoc_pcie3_1lane_s_clk.clkr, 3030 [GCC_SNOC_PCIE3_2LANE_M_CLK] = &gcc_snoc_pcie3_2lane_m_clk.clkr, 3031 [GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr, 3032 [GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr, 3033 [GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr, 3034 [GCC_SYSTEM_NOC_BFDCD_CLK_SRC] = &gcc_system_noc_bfdcd_clk_src.clkr, 3035 [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr, 3036 [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr, 3037 [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr, 3038 [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr, 3039 [GCC_UNIPHY_SYS_CLK_SRC] = &gcc_uniphy_sys_clk_src.clkr, 3040 [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr, 3041 [GCC_USB0_AUX_CLK_SRC] = &gcc_usb0_aux_clk_src.clkr, 3042 [GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr, 3043 [GCC_USB0_LFPS_CLK] = &gcc_usb0_lfps_clk.clkr, 3044 [GCC_USB0_LFPS_CLK_SRC] = &gcc_usb0_lfps_clk_src.clkr, 3045 [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr, 3046 [GCC_USB0_MASTER_CLK_SRC] = &gcc_usb0_master_clk_src.clkr, 3047 [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr, 3048 [GCC_USB0_MOCK_UTMI_CLK_SRC] = &gcc_usb0_mock_utmi_clk_src.clkr, 3049 [GCC_USB0_MOCK_UTMI_DIV_CLK_SRC] = &gcc_usb0_mock_utmi_div_clk_src.clkr, 3050 [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr, 3051 [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr, 3052 [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr, 3053 [GCC_WCSS_AHB_CLK_SRC] = &gcc_wcss_ahb_clk_src.clkr, 3054 [GCC_XO_CLK] = &gcc_xo_clk.clkr, 3055 [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr, 3056 [GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr, 3057 [GCC_IM_SLEEP_CLK] = &gcc_im_sleep_clk.clkr, 3058 [GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr, 3059 [GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC] = &gcc_snoc_qosgen_extref_div_clk_src.clkr, 3060 [GCC_PCIE3X2_PIPE_CLK_SRC] = &gcc_pcie3x2_pipe_clk_src.clkr, 3061 [GCC_PCIE3X1_0_PIPE_CLK_SRC] = &gcc_pcie3x1_0_pipe_clk_src.clkr, 3062 [GCC_PCIE3X1_1_PIPE_CLK_SRC] = &gcc_pcie3x1_1_pipe_clk_src.clkr, 3063 [GCC_USB0_PIPE_CLK_SRC] = &gcc_usb0_pipe_clk_src.clkr, 3064 }; 3065 3066 static const struct qcom_reset_map gcc_ipq5332_resets[] = { 3067 [GCC_ADSS_BCR] = { 0x1c000 }, 3068 [GCC_ADSS_PWM_CLK_ARES] = { 0x1c00c, 2 }, 3069 [GCC_AHB_CLK_ARES] = { 0x34024, 2 }, 3070 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000 }, 3071 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES] = { 0x3800c, 2 }, 3072 [GCC_APSS_AHB_CLK_ARES] = { 0x24018, 2 }, 3073 [GCC_APSS_AXI_CLK_ARES] = { 0x2401c, 2 }, 3074 [GCC_BLSP1_AHB_CLK_ARES] = { 0x1008, 2 }, 3075 [GCC_BLSP1_BCR] = { 0x1000 }, 3076 [GCC_BLSP1_QUP1_BCR] = { 0x2000 }, 3077 [GCC_BLSP1_QUP1_I2C_APPS_CLK_ARES] = { 0x2024, 2 }, 3078 [GCC_BLSP1_QUP1_SPI_APPS_CLK_ARES] = { 0x2020, 2 }, 3079 [GCC_BLSP1_QUP2_BCR] = { 0x3000 }, 3080 [GCC_BLSP1_QUP2_I2C_APPS_CLK_ARES] = { 0x3024, 2 }, 3081 [GCC_BLSP1_QUP2_SPI_APPS_CLK_ARES] = { 0x3020, 2 }, 3082 [GCC_BLSP1_QUP3_BCR] = { 0x4000 }, 3083 [GCC_BLSP1_QUP3_I2C_APPS_CLK_ARES] = { 0x4024, 2 }, 3084 [GCC_BLSP1_QUP3_SPI_APPS_CLK_ARES] = { 0x4020, 2 }, 3085 [GCC_BLSP1_SLEEP_CLK_ARES] = { 0x1010, 2 }, 3086 [GCC_BLSP1_UART1_APPS_CLK_ARES] = { 0x2040, 2 }, 3087 [GCC_BLSP1_UART1_BCR] = { 0x2028 }, 3088 [GCC_BLSP1_UART2_APPS_CLK_ARES] = { 0x3040, 2 }, 3089 [GCC_BLSP1_UART2_BCR] = { 0x3028 }, 3090 [GCC_BLSP1_UART3_APPS_CLK_ARES] = { 0x4054, 2 }, 3091 [GCC_BLSP1_UART3_BCR] = { 0x4028 }, 3092 [GCC_CE_BCR] = { 0x18008 }, 3093 [GCC_CMN_BLK_BCR] = { 0x3a000 }, 3094 [GCC_CMN_LDO0_BCR] = { 0x1d000 }, 3095 [GCC_CMN_LDO1_BCR] = { 0x1d008 }, 3096 [GCC_DCC_BCR] = { 0x35000 }, 3097 [GCC_GP1_CLK_ARES] = { 0x8018, 2 }, 3098 [GCC_GP2_CLK_ARES] = { 0x9018, 2 }, 3099 [GCC_LPASS_BCR] = { 0x27000 }, 3100 [GCC_LPASS_CORE_AXIM_CLK_ARES] = { 0x27018, 2 }, 3101 [GCC_LPASS_SWAY_CLK_ARES] = { 0x27014, 2 }, 3102 [GCC_MDIOM_BCR] = { 0x12000 }, 3103 [GCC_MDIOS_BCR] = { 0x12008 }, 3104 [GCC_NSS_BCR] = { 0x17000 }, 3105 [GCC_NSS_TS_CLK_ARES] = { 0x17018, 2 }, 3106 [GCC_NSSCC_CLK_ARES] = { 0x17034, 2 }, 3107 [GCC_NSSCFG_CLK_ARES] = { 0x1702c, 2 }, 3108 [GCC_NSSNOC_ATB_CLK_ARES] = { 0x17014, 2 }, 3109 [GCC_NSSNOC_NSSCC_CLK_ARES] = { 0x17030, 2 }, 3110 [GCC_NSSNOC_QOSGEN_REF_CLK_ARES] = { 0x1701c, 2 }, 3111 [GCC_NSSNOC_SNOC_1_CLK_ARES] = { 0x1707c, 2 }, 3112 [GCC_NSSNOC_SNOC_CLK_ARES] = { 0x17028, 2 }, 3113 [GCC_NSSNOC_TIMEOUT_REF_CLK_ARES] = { 0x17020, 2 }, 3114 [GCC_NSSNOC_XO_DCD_CLK_ARES] = { 0x17074, 2 }, 3115 [GCC_PCIE3X1_0_AHB_CLK_ARES] = { 0x29030, 2 }, 3116 [GCC_PCIE3X1_0_AUX_CLK_ARES] = { 0x29070, 2 }, 3117 [GCC_PCIE3X1_0_AXI_M_CLK_ARES] = { 0x29038, 2 }, 3118 [GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK_ARES] = { 0x29048, 2 }, 3119 [GCC_PCIE3X1_0_AXI_S_CLK_ARES] = { 0x29040, 2 }, 3120 [GCC_PCIE3X1_0_BCR] = { 0x29000 }, 3121 [GCC_PCIE3X1_0_LINK_DOWN_BCR] = { 0x29054 }, 3122 [GCC_PCIE3X1_0_PHY_BCR] = { 0x29060 }, 3123 [GCC_PCIE3X1_0_PHY_PHY_BCR] = { 0x2905c }, 3124 [GCC_PCIE3X1_1_AHB_CLK_ARES] = { 0x2a00c, 2 }, 3125 [GCC_PCIE3X1_1_AUX_CLK_ARES] = { 0x2a070, 2 }, 3126 [GCC_PCIE3X1_1_AXI_M_CLK_ARES] = { 0x2a014, 2 }, 3127 [GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK_ARES] = { 0x2a024, 2 }, 3128 [GCC_PCIE3X1_1_AXI_S_CLK_ARES] = { 0x2a01c, 2 }, 3129 [GCC_PCIE3X1_1_BCR] = { 0x2a000 }, 3130 [GCC_PCIE3X1_1_LINK_DOWN_BCR] = { 0x2a028 }, 3131 [GCC_PCIE3X1_1_PHY_BCR] = { 0x2a030 }, 3132 [GCC_PCIE3X1_1_PHY_PHY_BCR] = { 0x2a02c }, 3133 [GCC_PCIE3X1_PHY_AHB_CLK_ARES] = { 0x29078, 2 }, 3134 [GCC_PCIE3X2_AHB_CLK_ARES] = { 0x28030, 2 }, 3135 [GCC_PCIE3X2_AUX_CLK_ARES] = { 0x28070, 2 }, 3136 [GCC_PCIE3X2_AXI_M_CLK_ARES] = { 0x28038, 2 }, 3137 [GCC_PCIE3X2_AXI_S_BRIDGE_CLK_ARES] = { 0x28048, 2 }, 3138 [GCC_PCIE3X2_AXI_S_CLK_ARES] = { 0x28040, 2 }, 3139 [GCC_PCIE3X2_BCR] = { 0x28000 }, 3140 [GCC_PCIE3X2_LINK_DOWN_BCR] = { 0x28054 }, 3141 [GCC_PCIE3X2_PHY_AHB_CLK_ARES] = { 0x28080, 2 }, 3142 [GCC_PCIE3X2_PHY_BCR] = { 0x28060 }, 3143 [GCC_PCIE3X2PHY_PHY_BCR] = { 0x2805c }, 3144 [GCC_PCNOC_BCR] = { 0x31000 }, 3145 [GCC_PCNOC_LPASS_CLK_ARES] = { 0x31020, 2 }, 3146 [GCC_PRNG_AHB_CLK_ARES] = { 0x13024, 2 }, 3147 [GCC_PRNG_BCR] = { 0x13020 }, 3148 [GCC_Q6_AHB_CLK_ARES] = { 0x25014, 2 }, 3149 [GCC_Q6_AHB_S_CLK_ARES] = { 0x25018, 2 }, 3150 [GCC_Q6_AXIM_CLK_ARES] = { 0x2500c, 2 }, 3151 [GCC_Q6_AXIS_CLK_ARES] = { 0x25010, 2 }, 3152 [GCC_Q6_TSCTR_1TO2_CLK_ARES] = { 0x25020, 2 }, 3153 [GCC_Q6SS_ATBM_CLK_ARES] = { 0x2501c, 2 }, 3154 [GCC_Q6SS_PCLKDBG_CLK_ARES] = { 0x25024, 2 }, 3155 [GCC_Q6SS_TRIG_CLK_ARES] = { 0x250a0, 2 }, 3156 [GCC_QDSS_APB2JTAG_CLK_ARES] = { 0x2d060, 2 }, 3157 [GCC_QDSS_AT_CLK_ARES] = { 0x2d038, 2 }, 3158 [GCC_QDSS_BCR] = { 0x2d000 }, 3159 [GCC_QDSS_CFG_AHB_CLK_ARES] = { 0x2d06c, 2 }, 3160 [GCC_QDSS_DAP_AHB_CLK_ARES] = { 0x2d068, 2 }, 3161 [GCC_QDSS_DAP_CLK_ARES] = { 0x2d05c, 2 }, 3162 [GCC_QDSS_ETR_USB_CLK_ARES] = { 0x2d064, 2 }, 3163 [GCC_QDSS_EUD_AT_CLK_ARES] = { 0x2d070, 2 }, 3164 [GCC_QDSS_STM_CLK_ARES] = { 0x2d040, 2 }, 3165 [GCC_QDSS_TRACECLKIN_CLK_ARES] = { 0x2d044, 2 }, 3166 [GCC_QDSS_TS_CLK_ARES] = { 0x2d078, 2 }, 3167 [GCC_QDSS_TSCTR_DIV16_CLK_ARES] = { 0x2d058, 2 }, 3168 [GCC_QDSS_TSCTR_DIV2_CLK_ARES] = { 0x2d048, 2 }, 3169 [GCC_QDSS_TSCTR_DIV3_CLK_ARES] = { 0x2d04c, 2 }, 3170 [GCC_QDSS_TSCTR_DIV4_CLK_ARES] = { 0x2d050, 2 }, 3171 [GCC_QDSS_TSCTR_DIV8_CLK_ARES] = { 0x2d054, 2 }, 3172 [GCC_QPIC_AHB_CLK_ARES] = { 0x32010, 2 }, 3173 [GCC_QPIC_CLK_ARES] = { 0x32014, 2 }, 3174 [GCC_QPIC_BCR] = { 0x32000 }, 3175 [GCC_QPIC_IO_MACRO_CLK_ARES] = { 0x3200c, 2 }, 3176 [GCC_QPIC_SLEEP_CLK_ARES] = { 0x3201c, 2 }, 3177 [GCC_QUSB2_0_PHY_BCR] = { 0x2c068 }, 3178 [GCC_SDCC1_AHB_CLK_ARES] = { 0x33034, 2 }, 3179 [GCC_SDCC1_APPS_CLK_ARES] = { 0x3302c, 2 }, 3180 [GCC_SDCC_BCR] = { 0x33000 }, 3181 [GCC_SNOC_BCR] = { 0x2e000 }, 3182 [GCC_SNOC_LPASS_CFG_CLK_ARES] = { 0x2e028, 2 }, 3183 [GCC_SNOC_NSSNOC_1_CLK_ARES] = { 0x17090, 2 }, 3184 [GCC_SNOC_NSSNOC_CLK_ARES] = { 0x17084, 2 }, 3185 [GCC_SYS_NOC_QDSS_STM_AXI_CLK_ARES] = { 0x2e034, 2 }, 3186 [GCC_SYS_NOC_WCSS_AHB_CLK_ARES] = { 0x2e030, 2 }, 3187 [GCC_UNIPHY0_AHB_CLK_ARES] = { 0x16010, 2 }, 3188 [GCC_UNIPHY0_BCR] = { 0x16000 }, 3189 [GCC_UNIPHY0_SYS_CLK_ARES] = { 0x1600c, 2 }, 3190 [GCC_UNIPHY1_AHB_CLK_ARES] = { 0x1601c, 2 }, 3191 [GCC_UNIPHY1_BCR] = { 0x16014 }, 3192 [GCC_UNIPHY1_SYS_CLK_ARES] = { 0x16018, 2 }, 3193 [GCC_USB0_AUX_CLK_ARES] = { 0x2c050, 2 }, 3194 [GCC_USB0_EUD_AT_CLK_ARES] = { 0x30004, 2 }, 3195 [GCC_USB0_LFPS_CLK_ARES] = { 0x2c090, 2 }, 3196 [GCC_USB0_MASTER_CLK_ARES] = { 0x2c048, 2 }, 3197 [GCC_USB0_MOCK_UTMI_CLK_ARES] = { 0x2c054, 2 }, 3198 [GCC_USB0_PHY_BCR] = { 0x2c06c }, 3199 [GCC_USB0_PHY_CFG_AHB_CLK_ARES] = { 0x2c05c, 2 }, 3200 [GCC_USB0_SLEEP_CLK_ARES] = { 0x2c058, 2 }, 3201 [GCC_USB3PHY_0_PHY_BCR] = { 0x2c070 }, 3202 [GCC_USB_BCR] = { 0x2c000 }, 3203 [GCC_WCSS_AXIM_CLK_ARES] = { 0x2505c, 2 }, 3204 [GCC_WCSS_AXIS_CLK_ARES] = { 0x25060, 2 }, 3205 [GCC_WCSS_BCR] = { 0x18004 }, 3206 [GCC_WCSS_DBG_IFC_APB_BDG_CLK_ARES] = { 0x25048, 2 }, 3207 [GCC_WCSS_DBG_IFC_APB_CLK_ARES] = { 0x25038, 2 }, 3208 [GCC_WCSS_DBG_IFC_ATB_BDG_CLK_ARES] = { 0x2504c, 2 }, 3209 [GCC_WCSS_DBG_IFC_ATB_CLK_ARES] = { 0x2503c, 2 }, 3210 [GCC_WCSS_DBG_IFC_NTS_BDG_CLK_ARES] = { 0x25050, 2 }, 3211 [GCC_WCSS_DBG_IFC_NTS_CLK_ARES] = { 0x25040, 2 }, 3212 [GCC_WCSS_ECAHB_CLK_ARES] = { 0x25058, 2 }, 3213 [GCC_WCSS_MST_ASYNC_BDG_CLK_ARES] = { 0x2e0b0, 2 }, 3214 [GCC_WCSS_Q6_BCR] = { 0x18000 }, 3215 [GCC_WCSS_SLV_ASYNC_BDG_CLK_ARES] = { 0x2e0b4, 2 }, 3216 [GCC_XO_CLK_ARES] = { 0x34018, 2 }, 3217 [GCC_XO_DIV4_CLK_ARES] = { 0x3401c, 2 }, 3218 [GCC_Q6SS_DBG_ARES] = { 0x25094 }, 3219 [GCC_WCSS_DBG_BDG_ARES] = { 0x25098, 0 }, 3220 [GCC_WCSS_DBG_ARES] = { 0x25098, 1 }, 3221 [GCC_WCSS_AXI_S_ARES] = { 0x25098, 2 }, 3222 [GCC_WCSS_AXI_M_ARES] = { 0x25098, 3 }, 3223 [GCC_WCSSAON_ARES] = { 0x2509C }, 3224 [GCC_PCIE3X2_PIPE_ARES] = { 0x28058, 0 }, 3225 [GCC_PCIE3X2_CORE_STICKY_ARES] = { 0x28058, 1 }, 3226 [GCC_PCIE3X2_AXI_S_STICKY_ARES] = { 0x28058, 2 }, 3227 [GCC_PCIE3X2_AXI_M_STICKY_ARES] = { 0x28058, 3 }, 3228 [GCC_PCIE3X1_0_PIPE_ARES] = { 0x29058, 0 }, 3229 [GCC_PCIE3X1_0_CORE_STICKY_ARES] = { 0x29058, 1 }, 3230 [GCC_PCIE3X1_0_AXI_S_STICKY_ARES] = { 0x29058, 2 }, 3231 [GCC_PCIE3X1_0_AXI_M_STICKY_ARES] = { 0x29058, 3 }, 3232 [GCC_PCIE3X1_1_PIPE_ARES] = { 0x2a058, 0 }, 3233 [GCC_PCIE3X1_1_CORE_STICKY_ARES] = { 0x2a058, 1 }, 3234 [GCC_PCIE3X1_1_AXI_S_STICKY_ARES] = { 0x2a058, 2 }, 3235 [GCC_PCIE3X1_1_AXI_M_STICKY_ARES] = { 0x2a058, 3 }, 3236 [GCC_IM_SLEEP_CLK_ARES] = { 0x34020, 2 }, 3237 [GCC_NSSNOC_PCNOC_1_CLK_ARES] = { 0x17080, 2 }, 3238 [GCC_UNIPHY0_XPCS_ARES] = { 0x16050 }, 3239 [GCC_UNIPHY1_XPCS_ARES] = { 0x16060 }, 3240 }; 3241 3242 #define IPQ_APPS_ID 5332 /* some unique value */ 3243 3244 static const struct qcom_icc_hws_data icc_ipq5332_hws[] = { 3245 { MASTER_SNOC_PCIE3_1_M, SLAVE_SNOC_PCIE3_1_M, GCC_SNOC_PCIE3_1LANE_M_CLK }, 3246 { MASTER_ANOC_PCIE3_1_S, SLAVE_ANOC_PCIE3_1_S, GCC_SNOC_PCIE3_1LANE_S_CLK }, 3247 { MASTER_SNOC_PCIE3_2_M, SLAVE_SNOC_PCIE3_2_M, GCC_SNOC_PCIE3_2LANE_M_CLK }, 3248 { MASTER_ANOC_PCIE3_2_S, SLAVE_ANOC_PCIE3_2_S, GCC_SNOC_PCIE3_2LANE_S_CLK }, 3249 { MASTER_SNOC_USB, SLAVE_SNOC_USB, GCC_SNOC_USB_CLK }, 3250 { MASTER_NSSNOC_NSSCC, SLAVE_NSSNOC_NSSCC, GCC_NSSNOC_NSSCC_CLK }, 3251 { MASTER_NSSNOC_SNOC_0, SLAVE_NSSNOC_SNOC_0, GCC_NSSNOC_SNOC_CLK }, 3252 { MASTER_NSSNOC_SNOC_1, SLAVE_NSSNOC_SNOC_1, GCC_NSSNOC_SNOC_1_CLK }, 3253 { MASTER_NSSNOC_ATB, SLAVE_NSSNOC_ATB, GCC_NSSNOC_ATB_CLK }, 3254 { MASTER_NSSNOC_PCNOC_1, SLAVE_NSSNOC_PCNOC_1, GCC_NSSNOC_PCNOC_1_CLK }, 3255 { MASTER_NSSNOC_QOSGEN_REF, SLAVE_NSSNOC_QOSGEN_REF, GCC_NSSNOC_QOSGEN_REF_CLK }, 3256 { MASTER_NSSNOC_TIMEOUT_REF, SLAVE_NSSNOC_TIMEOUT_REF, GCC_NSSNOC_TIMEOUT_REF_CLK }, 3257 { MASTER_NSSNOC_XO_DCD, SLAVE_NSSNOC_XO_DCD, GCC_NSSNOC_XO_DCD_CLK }, 3258 }; 3259 3260 static const struct regmap_config gcc_ipq5332_regmap_config = { 3261 .reg_bits = 32, 3262 .reg_stride = 4, 3263 .val_bits = 32, 3264 .max_register = 0x3f024, 3265 .fast_io = true, 3266 }; 3267 3268 static struct clk_hw *gcc_ipq5332_hws[] = { 3269 &gpll0_div2.hw, 3270 &gcc_xo_div4_clk_src.hw, 3271 &gcc_system_noc_bfdcd_div2_clk_src.hw, 3272 &gcc_qdss_tsctr_div2_clk_src.hw, 3273 &gcc_qdss_tsctr_div3_clk_src.hw, 3274 &gcc_qdss_tsctr_div4_clk_src.hw, 3275 &gcc_qdss_tsctr_div8_clk_src.hw, 3276 &gcc_qdss_tsctr_div16_clk_src.hw, 3277 &gcc_eud_at_div_clk_src.hw, 3278 }; 3279 3280 static const struct qcom_cc_desc gcc_ipq5332_desc = { 3281 .config = &gcc_ipq5332_regmap_config, 3282 .clks = gcc_ipq5332_clocks, 3283 .num_clks = ARRAY_SIZE(gcc_ipq5332_clocks), 3284 .resets = gcc_ipq5332_resets, 3285 .num_resets = ARRAY_SIZE(gcc_ipq5332_resets), 3286 .clk_hws = gcc_ipq5332_hws, 3287 .num_clk_hws = ARRAY_SIZE(gcc_ipq5332_hws), 3288 .icc_hws = icc_ipq5332_hws, 3289 .num_icc_hws = ARRAY_SIZE(icc_ipq5332_hws), 3290 .icc_first_node_id = IPQ_APPS_ID, 3291 }; 3292 3293 static int gcc_ipq5332_probe(struct platform_device *pdev) 3294 { 3295 return qcom_cc_probe(pdev, &gcc_ipq5332_desc); 3296 } 3297 3298 static const struct of_device_id gcc_ipq5332_match_table[] = { 3299 { .compatible = "qcom,ipq5332-gcc" }, 3300 { } 3301 }; 3302 MODULE_DEVICE_TABLE(of, gcc_ipq5332_match_table); 3303 3304 static struct platform_driver gcc_ipq5332_driver = { 3305 .probe = gcc_ipq5332_probe, 3306 .driver = { 3307 .name = "gcc-ipq5332", 3308 .of_match_table = gcc_ipq5332_match_table, 3309 .sync_state = icc_sync_state, 3310 }, 3311 }; 3312 3313 static int __init gcc_ipq5332_init(void) 3314 { 3315 return platform_driver_register(&gcc_ipq5332_driver); 3316 } 3317 core_initcall(gcc_ipq5332_init); 3318 3319 static void __exit gcc_ipq5332_exit(void) 3320 { 3321 platform_driver_unregister(&gcc_ipq5332_driver); 3322 } 3323 module_exit(gcc_ipq5332_exit); 3324 3325 MODULE_DESCRIPTION("QTI GCC IPQ5332 Driver"); 3326 MODULE_LICENSE("GPL"); 3327