1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/err.h> 8 #include <linux/platform_device.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/clk-provider.h> 12 #include <linux/regmap.h> 13 #include <linux/reset-controller.h> 14 #include <linux/math64.h> 15 #include <linux/delay.h> 16 #include <linux/clk.h> 17 18 #include <dt-bindings/clock/qcom,gcc-ipq4019.h> 19 20 #include "common.h" 21 #include "clk-regmap.h" 22 #include "clk-rcg.h" 23 #include "clk-branch.h" 24 #include "reset.h" 25 #include "clk-regmap-divider.h" 26 27 #define to_clk_regmap_div(_hw) container_of(to_clk_regmap(_hw),\ 28 struct clk_regmap_div, clkr) 29 30 #define to_clk_fepll(_hw) container_of(to_clk_regmap_div(_hw),\ 31 struct clk_fepll, cdiv) 32 33 enum { 34 P_XO, 35 P_FEPLL200, 36 P_FEPLL500, 37 P_DDRPLL, 38 P_FEPLLWCSS2G, 39 P_FEPLLWCSS5G, 40 P_FEPLL125DLY, 41 P_DDRPLLAPSS, 42 }; 43 44 /* 45 * struct clk_fepll_vco - vco feedback divider corresponds for FEPLL clocks 46 * @fdbkdiv_shift: lowest bit for FDBKDIV 47 * @fdbkdiv_width: number of bits in FDBKDIV 48 * @refclkdiv_shift: lowest bit for REFCLKDIV 49 * @refclkdiv_width: number of bits in REFCLKDIV 50 * @reg: PLL_DIV register address 51 */ 52 struct clk_fepll_vco { 53 u32 fdbkdiv_shift; 54 u32 fdbkdiv_width; 55 u32 refclkdiv_shift; 56 u32 refclkdiv_width; 57 u32 reg; 58 }; 59 60 /* 61 * struct clk_fepll - clk divider corresponds to FEPLL clocks 62 * @fixed_div: fixed divider value if divider is fixed 63 * @parent_map: map from software's parent index to hardware's src_sel field 64 * @cdiv: divider values for PLL_DIV 65 * @pll_vco: vco feedback divider 66 * @div_table: mapping for actual divider value to register divider value 67 * in case of non fixed divider 68 * @freq_tbl: frequency table 69 */ 70 struct clk_fepll { 71 u32 fixed_div; 72 const u8 *parent_map; 73 struct clk_regmap_div cdiv; 74 const struct clk_fepll_vco *pll_vco; 75 const struct clk_div_table *div_table; 76 const struct freq_tbl *freq_tbl; 77 }; 78 79 /* 80 * Contains index for safe clock during APSS freq change. 81 * fepll500 is being used as safe clock so initialize it 82 * with its index in parents list gcc_xo_ddr_500_200. 83 */ 84 static const int gcc_ipq4019_cpu_safe_parent = 2; 85 86 /* Calculates the VCO rate for FEPLL. */ 87 static u64 clk_fepll_vco_calc_rate(struct clk_fepll *pll_div, 88 unsigned long parent_rate) 89 { 90 const struct clk_fepll_vco *pll_vco = pll_div->pll_vco; 91 u32 fdbkdiv, refclkdiv, cdiv; 92 u64 vco; 93 94 regmap_read(pll_div->cdiv.clkr.regmap, pll_vco->reg, &cdiv); 95 refclkdiv = (cdiv >> pll_vco->refclkdiv_shift) & 96 (BIT(pll_vco->refclkdiv_width) - 1); 97 fdbkdiv = (cdiv >> pll_vco->fdbkdiv_shift) & 98 (BIT(pll_vco->fdbkdiv_width) - 1); 99 100 vco = parent_rate / refclkdiv; 101 vco *= 2; 102 vco *= fdbkdiv; 103 104 return vco; 105 } 106 107 static const struct clk_fepll_vco gcc_apss_ddrpll_vco = { 108 .fdbkdiv_shift = 16, 109 .fdbkdiv_width = 8, 110 .refclkdiv_shift = 24, 111 .refclkdiv_width = 5, 112 .reg = 0x2e020, 113 }; 114 115 static const struct clk_fepll_vco gcc_fepll_vco = { 116 .fdbkdiv_shift = 16, 117 .fdbkdiv_width = 8, 118 .refclkdiv_shift = 24, 119 .refclkdiv_width = 5, 120 .reg = 0x2f020, 121 }; 122 123 /* 124 * Round rate function for APSS CPU PLL Clock divider. 125 * It looks up the frequency table and returns the next higher frequency 126 * supported in hardware. 127 */ 128 static int clk_cpu_div_determine_rate(struct clk_hw *hw, 129 struct clk_rate_request *req) 130 { 131 struct clk_fepll *pll = to_clk_fepll(hw); 132 struct clk_hw *p_hw; 133 const struct freq_tbl *f; 134 135 f = qcom_find_freq(pll->freq_tbl, req->rate); 136 if (!f) 137 return -EINVAL; 138 139 p_hw = clk_hw_get_parent_by_index(hw, f->src); 140 req->best_parent_rate = clk_hw_get_rate(p_hw); 141 142 req->rate = f->freq; 143 144 return 0; 145 }; 146 147 /* 148 * Clock set rate function for APSS CPU PLL Clock divider. 149 * It looks up the frequency table and updates the PLL divider to corresponding 150 * divider value. 151 */ 152 static int clk_cpu_div_set_rate(struct clk_hw *hw, unsigned long rate, 153 unsigned long parent_rate) 154 { 155 struct clk_fepll *pll = to_clk_fepll(hw); 156 const struct freq_tbl *f; 157 u32 mask; 158 159 f = qcom_find_freq(pll->freq_tbl, rate); 160 if (!f) 161 return -EINVAL; 162 163 mask = (BIT(pll->cdiv.width) - 1) << pll->cdiv.shift; 164 regmap_update_bits(pll->cdiv.clkr.regmap, 165 pll->cdiv.reg, mask, 166 f->pre_div << pll->cdiv.shift); 167 /* 168 * There is no status bit which can be checked for successful CPU 169 * divider update operation so using delay for the same. 170 */ 171 udelay(1); 172 173 return 0; 174 }; 175 176 /* 177 * Clock frequency calculation function for APSS CPU PLL Clock divider. 178 * This clock divider is nonlinear so this function calculates the actual 179 * divider and returns the output frequency by dividing VCO Frequency 180 * with this actual divider value. 181 */ 182 static unsigned long 183 clk_cpu_div_recalc_rate(struct clk_hw *hw, 184 unsigned long parent_rate) 185 { 186 struct clk_fepll *pll = to_clk_fepll(hw); 187 u32 cdiv, pre_div; 188 u64 rate; 189 190 regmap_read(pll->cdiv.clkr.regmap, pll->cdiv.reg, &cdiv); 191 cdiv = (cdiv >> pll->cdiv.shift) & (BIT(pll->cdiv.width) - 1); 192 193 /* 194 * Some dividers have value in 0.5 fraction so multiply both VCO 195 * frequency(parent_rate) and pre_div with 2 to make integer 196 * calculation. 197 */ 198 if (cdiv > 10) 199 pre_div = (cdiv + 1) * 2; 200 else 201 pre_div = cdiv + 12; 202 203 rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2; 204 do_div(rate, pre_div); 205 206 return rate; 207 }; 208 209 static const struct clk_ops clk_regmap_cpu_div_ops = { 210 .determine_rate = clk_cpu_div_determine_rate, 211 .set_rate = clk_cpu_div_set_rate, 212 .recalc_rate = clk_cpu_div_recalc_rate, 213 }; 214 215 static const struct freq_tbl ftbl_apss_ddr_pll[] = { 216 { 384000000, P_XO, 0xd, 0, 0 }, 217 { 413000000, P_XO, 0xc, 0, 0 }, 218 { 448000000, P_XO, 0xb, 0, 0 }, 219 { 488000000, P_XO, 0xa, 0, 0 }, 220 { 512000000, P_XO, 0x9, 0, 0 }, 221 { 537000000, P_XO, 0x8, 0, 0 }, 222 { 565000000, P_XO, 0x7, 0, 0 }, 223 { 597000000, P_XO, 0x6, 0, 0 }, 224 { 632000000, P_XO, 0x5, 0, 0 }, 225 { 672000000, P_XO, 0x4, 0, 0 }, 226 { 716000000, P_XO, 0x3, 0, 0 }, 227 { 768000000, P_XO, 0x2, 0, 0 }, 228 { 823000000, P_XO, 0x1, 0, 0 }, 229 { 896000000, P_XO, 0x0, 0, 0 }, 230 { } 231 }; 232 233 static struct clk_fepll gcc_apss_cpu_plldiv_clk = { 234 .cdiv.reg = 0x2e020, 235 .cdiv.shift = 4, 236 .cdiv.width = 4, 237 .cdiv.clkr = { 238 .enable_reg = 0x2e000, 239 .enable_mask = BIT(0), 240 .hw.init = &(struct clk_init_data){ 241 .name = "ddrpllapss", 242 .parent_data = &(const struct clk_parent_data){ 243 .fw_name = "xo", 244 .name = "xo", 245 }, 246 .num_parents = 1, 247 .ops = &clk_regmap_cpu_div_ops, 248 }, 249 }, 250 .freq_tbl = ftbl_apss_ddr_pll, 251 .pll_vco = &gcc_apss_ddrpll_vco, 252 }; 253 254 /* Calculates the rate for PLL divider. 255 * If the divider value is not fixed then it gets the actual divider value 256 * from divider table. Then, it calculate the clock rate by dividing the 257 * parent rate with actual divider value. 258 */ 259 static unsigned long 260 clk_regmap_clk_div_recalc_rate(struct clk_hw *hw, 261 unsigned long parent_rate) 262 { 263 struct clk_fepll *pll = to_clk_fepll(hw); 264 u32 cdiv, pre_div = 1; 265 u64 rate; 266 const struct clk_div_table *clkt; 267 268 if (pll->fixed_div) { 269 pre_div = pll->fixed_div; 270 } else { 271 regmap_read(pll->cdiv.clkr.regmap, pll->cdiv.reg, &cdiv); 272 cdiv = (cdiv >> pll->cdiv.shift) & (BIT(pll->cdiv.width) - 1); 273 274 for (clkt = pll->div_table; clkt->div; clkt++) { 275 if (clkt->val == cdiv) 276 pre_div = clkt->div; 277 } 278 } 279 280 rate = clk_fepll_vco_calc_rate(pll, parent_rate); 281 do_div(rate, pre_div); 282 283 return rate; 284 }; 285 286 static const struct clk_ops clk_fepll_div_ops = { 287 .recalc_rate = clk_regmap_clk_div_recalc_rate, 288 }; 289 290 static struct clk_fepll gcc_apss_sdcc_clk = { 291 .fixed_div = 28, 292 .cdiv.clkr = { 293 .hw.init = &(struct clk_init_data){ 294 .name = "ddrpllsdcc", 295 .parent_data = &(const struct clk_parent_data){ 296 .fw_name = "xo", 297 .name = "xo", 298 }, 299 .num_parents = 1, 300 .ops = &clk_fepll_div_ops, 301 }, 302 }, 303 .pll_vco = &gcc_apss_ddrpll_vco, 304 }; 305 306 static struct clk_fepll gcc_fepll125_clk = { 307 .fixed_div = 32, 308 .cdiv.clkr = { 309 .hw.init = &(struct clk_init_data){ 310 .name = "fepll125", 311 .parent_data = &(const struct clk_parent_data){ 312 .fw_name = "xo", 313 .name = "xo", 314 }, 315 .num_parents = 1, 316 .ops = &clk_fepll_div_ops, 317 }, 318 }, 319 .pll_vco = &gcc_fepll_vco, 320 }; 321 322 static struct clk_fepll gcc_fepll125dly_clk = { 323 .fixed_div = 32, 324 .cdiv.clkr = { 325 .hw.init = &(struct clk_init_data){ 326 .name = "fepll125dly", 327 .parent_data = &(const struct clk_parent_data){ 328 .fw_name = "xo", 329 .name = "xo", 330 }, 331 .num_parents = 1, 332 .ops = &clk_fepll_div_ops, 333 }, 334 }, 335 .pll_vco = &gcc_fepll_vco, 336 }; 337 338 static struct clk_fepll gcc_fepll200_clk = { 339 .fixed_div = 20, 340 .cdiv.clkr = { 341 .hw.init = &(struct clk_init_data){ 342 .name = "fepll200", 343 .parent_data = &(const struct clk_parent_data){ 344 .fw_name = "xo", 345 .name = "xo", 346 }, 347 .num_parents = 1, 348 .ops = &clk_fepll_div_ops, 349 }, 350 }, 351 .pll_vco = &gcc_fepll_vco, 352 }; 353 354 static struct clk_fepll gcc_fepll500_clk = { 355 .fixed_div = 8, 356 .cdiv.clkr = { 357 .hw.init = &(struct clk_init_data){ 358 .name = "fepll500", 359 .parent_data = &(const struct clk_parent_data){ 360 .fw_name = "xo", 361 .name = "xo", 362 }, 363 .num_parents = 1, 364 .ops = &clk_fepll_div_ops, 365 }, 366 }, 367 .pll_vco = &gcc_fepll_vco, 368 }; 369 370 static const struct clk_div_table fepllwcss_clk_div_table[] = { 371 { 0, 15 }, 372 { 1, 16 }, 373 { 2, 18 }, 374 { 3, 20 }, 375 { }, 376 }; 377 378 static struct clk_fepll gcc_fepllwcss2g_clk = { 379 .cdiv.reg = 0x2f020, 380 .cdiv.shift = 8, 381 .cdiv.width = 2, 382 .cdiv.clkr = { 383 .hw.init = &(struct clk_init_data){ 384 .name = "fepllwcss2g", 385 .parent_data = &(const struct clk_parent_data){ 386 .fw_name = "xo", 387 .name = "xo", 388 }, 389 .num_parents = 1, 390 .ops = &clk_fepll_div_ops, 391 }, 392 }, 393 .div_table = fepllwcss_clk_div_table, 394 .pll_vco = &gcc_fepll_vco, 395 }; 396 397 static struct clk_fepll gcc_fepllwcss5g_clk = { 398 .cdiv.reg = 0x2f020, 399 .cdiv.shift = 12, 400 .cdiv.width = 2, 401 .cdiv.clkr = { 402 .hw.init = &(struct clk_init_data){ 403 .name = "fepllwcss5g", 404 .parent_data = &(const struct clk_parent_data){ 405 .fw_name = "xo", 406 .name = "xo", 407 }, 408 .num_parents = 1, 409 .ops = &clk_fepll_div_ops, 410 }, 411 }, 412 .div_table = fepllwcss_clk_div_table, 413 .pll_vco = &gcc_fepll_vco, 414 }; 415 416 static struct parent_map gcc_xo_200_500_map[] = { 417 { P_XO, 0 }, 418 { P_FEPLL200, 1 }, 419 { P_FEPLL500, 2 }, 420 }; 421 422 static const struct clk_parent_data gcc_xo_200_500[] = { 423 { .fw_name = "xo", .name = "xo" }, 424 { .hw = &gcc_fepll200_clk.cdiv.clkr.hw }, 425 { .hw = &gcc_fepll500_clk.cdiv.clkr.hw }, 426 }; 427 428 static const struct freq_tbl ftbl_gcc_pcnoc_ahb_clk[] = { 429 F(48000000, P_XO, 1, 0, 0), 430 F(100000000, P_FEPLL200, 2, 0, 0), 431 { } 432 }; 433 434 static struct clk_rcg2 gcc_pcnoc_ahb_clk_src = { 435 .cmd_rcgr = 0x21024, 436 .hid_width = 5, 437 .parent_map = gcc_xo_200_500_map, 438 .freq_tbl = ftbl_gcc_pcnoc_ahb_clk, 439 .clkr.hw.init = &(struct clk_init_data){ 440 .name = "gcc_pcnoc_ahb_clk_src", 441 .parent_data = gcc_xo_200_500, 442 .num_parents = ARRAY_SIZE(gcc_xo_200_500), 443 .ops = &clk_rcg2_ops, 444 }, 445 }; 446 447 static struct clk_branch pcnoc_clk_src = { 448 .halt_reg = 0x21030, 449 .clkr = { 450 .enable_reg = 0x21030, 451 .enable_mask = BIT(0), 452 .hw.init = &(struct clk_init_data){ 453 .name = "pcnoc_clk_src", 454 .parent_hws = (const struct clk_hw *[]){ 455 &gcc_pcnoc_ahb_clk_src.clkr.hw }, 456 .num_parents = 1, 457 .ops = &clk_branch2_ops, 458 .flags = CLK_SET_RATE_PARENT | 459 CLK_IS_CRITICAL, 460 }, 461 }, 462 }; 463 464 static struct parent_map gcc_xo_200_map[] = { 465 { P_XO, 0 }, 466 { P_FEPLL200, 1 }, 467 }; 468 469 static const struct clk_parent_data gcc_xo_200[] = { 470 { .fw_name = "xo", .name = "xo" }, 471 { .hw = &gcc_fepll200_clk.cdiv.clkr.hw }, 472 }; 473 474 static const struct freq_tbl ftbl_gcc_audio_pwm_clk[] = { 475 F(48000000, P_XO, 1, 0, 0), 476 F(200000000, P_FEPLL200, 1, 0, 0), 477 { } 478 }; 479 480 static struct clk_rcg2 audio_clk_src = { 481 .cmd_rcgr = 0x1b000, 482 .hid_width = 5, 483 .parent_map = gcc_xo_200_map, 484 .freq_tbl = ftbl_gcc_audio_pwm_clk, 485 .clkr.hw.init = &(struct clk_init_data){ 486 .name = "audio_clk_src", 487 .parent_data = gcc_xo_200, 488 .num_parents = ARRAY_SIZE(gcc_xo_200), 489 .ops = &clk_rcg2_ops, 490 491 }, 492 }; 493 494 static struct clk_branch gcc_audio_ahb_clk = { 495 .halt_reg = 0x1b010, 496 .clkr = { 497 .enable_reg = 0x1b010, 498 .enable_mask = BIT(0), 499 .hw.init = &(struct clk_init_data){ 500 .name = "gcc_audio_ahb_clk", 501 .parent_hws = (const struct clk_hw *[]){ 502 &pcnoc_clk_src.clkr.hw }, 503 .flags = CLK_SET_RATE_PARENT, 504 .num_parents = 1, 505 .ops = &clk_branch2_ops, 506 }, 507 }, 508 }; 509 510 static struct clk_branch gcc_audio_pwm_clk = { 511 .halt_reg = 0x1b00C, 512 .clkr = { 513 .enable_reg = 0x1b00C, 514 .enable_mask = BIT(0), 515 .hw.init = &(struct clk_init_data){ 516 .name = "gcc_audio_pwm_clk", 517 .parent_hws = (const struct clk_hw *[]){ 518 &audio_clk_src.clkr.hw }, 519 .flags = CLK_SET_RATE_PARENT, 520 .num_parents = 1, 521 .ops = &clk_branch2_ops, 522 }, 523 }, 524 }; 525 526 static const struct freq_tbl ftbl_gcc_blsp1_qup1_2_i2c_apps_clk[] = { 527 F(19050000, P_FEPLL200, 10.5, 1, 1), 528 { } 529 }; 530 531 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 532 .cmd_rcgr = 0x200c, 533 .hid_width = 5, 534 .parent_map = gcc_xo_200_map, 535 .freq_tbl = ftbl_gcc_blsp1_qup1_2_i2c_apps_clk, 536 .clkr.hw.init = &(struct clk_init_data){ 537 .name = "blsp1_qup1_i2c_apps_clk_src", 538 .parent_data = gcc_xo_200, 539 .num_parents = ARRAY_SIZE(gcc_xo_200), 540 .ops = &clk_rcg2_ops, 541 }, 542 }; 543 544 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 545 .halt_reg = 0x2008, 546 .clkr = { 547 .enable_reg = 0x2008, 548 .enable_mask = BIT(0), 549 .hw.init = &(struct clk_init_data){ 550 .name = "gcc_blsp1_qup1_i2c_apps_clk", 551 .parent_hws = (const struct clk_hw *[]){ 552 &blsp1_qup1_i2c_apps_clk_src.clkr.hw }, 553 .num_parents = 1, 554 .ops = &clk_branch2_ops, 555 .flags = CLK_SET_RATE_PARENT, 556 }, 557 }, 558 }; 559 560 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 561 .cmd_rcgr = 0x3000, 562 .hid_width = 5, 563 .parent_map = gcc_xo_200_map, 564 .freq_tbl = ftbl_gcc_blsp1_qup1_2_i2c_apps_clk, 565 .clkr.hw.init = &(struct clk_init_data){ 566 .name = "blsp1_qup2_i2c_apps_clk_src", 567 .parent_data = gcc_xo_200, 568 .num_parents = ARRAY_SIZE(gcc_xo_200), 569 .ops = &clk_rcg2_ops, 570 }, 571 }; 572 573 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 574 .halt_reg = 0x3010, 575 .clkr = { 576 .enable_reg = 0x3010, 577 .enable_mask = BIT(0), 578 .hw.init = &(struct clk_init_data){ 579 .name = "gcc_blsp1_qup2_i2c_apps_clk", 580 .parent_hws = (const struct clk_hw *[]){ 581 &blsp1_qup2_i2c_apps_clk_src.clkr.hw }, 582 .num_parents = 1, 583 .ops = &clk_branch2_ops, 584 .flags = CLK_SET_RATE_PARENT, 585 }, 586 }, 587 }; 588 589 static struct parent_map gcc_xo_200_spi_map[] = { 590 { P_XO, 0 }, 591 { P_FEPLL200, 2 }, 592 }; 593 594 static const struct clk_parent_data gcc_xo_200_spi[] = { 595 { .fw_name = "xo", .name = "xo" }, 596 { .hw = &gcc_fepll200_clk.cdiv.clkr.hw }, 597 }; 598 599 static const struct freq_tbl ftbl_gcc_blsp1_qup1_2_spi_apps_clk[] = { 600 F(960000, P_XO, 12, 1, 4), 601 F(4800000, P_XO, 1, 1, 10), 602 F(9600000, P_XO, 1, 1, 5), 603 F(15000000, P_XO, 1, 1, 3), 604 F(19200000, P_XO, 1, 2, 5), 605 F(24000000, P_XO, 1, 1, 2), 606 F(48000000, P_XO, 1, 0, 0), 607 { } 608 }; 609 610 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 611 .cmd_rcgr = 0x2024, 612 .mnd_width = 8, 613 .hid_width = 5, 614 .parent_map = gcc_xo_200_spi_map, 615 .freq_tbl = ftbl_gcc_blsp1_qup1_2_spi_apps_clk, 616 .clkr.hw.init = &(struct clk_init_data){ 617 .name = "blsp1_qup1_spi_apps_clk_src", 618 .parent_data = gcc_xo_200_spi, 619 .num_parents = ARRAY_SIZE(gcc_xo_200_spi), 620 .ops = &clk_rcg2_ops, 621 }, 622 }; 623 624 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 625 .halt_reg = 0x2004, 626 .clkr = { 627 .enable_reg = 0x2004, 628 .enable_mask = BIT(0), 629 .hw.init = &(struct clk_init_data){ 630 .name = "gcc_blsp1_qup1_spi_apps_clk", 631 .parent_hws = (const struct clk_hw *[]){ 632 &blsp1_qup1_spi_apps_clk_src.clkr.hw }, 633 .num_parents = 1, 634 .ops = &clk_branch2_ops, 635 .flags = CLK_SET_RATE_PARENT, 636 }, 637 }, 638 }; 639 640 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 641 .cmd_rcgr = 0x3014, 642 .mnd_width = 8, 643 .hid_width = 5, 644 .freq_tbl = ftbl_gcc_blsp1_qup1_2_spi_apps_clk, 645 .parent_map = gcc_xo_200_spi_map, 646 .clkr.hw.init = &(struct clk_init_data){ 647 .name = "blsp1_qup2_spi_apps_clk_src", 648 .parent_data = gcc_xo_200_spi, 649 .num_parents = ARRAY_SIZE(gcc_xo_200_spi), 650 .ops = &clk_rcg2_ops, 651 }, 652 }; 653 654 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 655 .halt_reg = 0x300c, 656 .clkr = { 657 .enable_reg = 0x300c, 658 .enable_mask = BIT(0), 659 .hw.init = &(struct clk_init_data){ 660 .name = "gcc_blsp1_qup2_spi_apps_clk", 661 .parent_hws = (const struct clk_hw *[]){ 662 &blsp1_qup2_spi_apps_clk_src.clkr.hw }, 663 .num_parents = 1, 664 .ops = &clk_branch2_ops, 665 .flags = CLK_SET_RATE_PARENT, 666 }, 667 }, 668 }; 669 670 static const struct freq_tbl ftbl_gcc_blsp1_uart1_2_apps_clk[] = { 671 F(1843200, P_FEPLL200, 1, 144, 15625), 672 F(3686400, P_FEPLL200, 1, 288, 15625), 673 F(7372800, P_FEPLL200, 1, 576, 15625), 674 F(14745600, P_FEPLL200, 1, 1152, 15625), 675 F(16000000, P_FEPLL200, 1, 2, 25), 676 F(24000000, P_XO, 1, 1, 2), 677 F(32000000, P_FEPLL200, 1, 4, 25), 678 F(40000000, P_FEPLL200, 1, 1, 5), 679 F(46400000, P_FEPLL200, 1, 29, 125), 680 F(48000000, P_XO, 1, 0, 0), 681 { } 682 }; 683 684 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 685 .cmd_rcgr = 0x2044, 686 .mnd_width = 16, 687 .hid_width = 5, 688 .freq_tbl = ftbl_gcc_blsp1_uart1_2_apps_clk, 689 .parent_map = gcc_xo_200_spi_map, 690 .clkr.hw.init = &(struct clk_init_data){ 691 .name = "blsp1_uart1_apps_clk_src", 692 .parent_data = gcc_xo_200_spi, 693 .num_parents = ARRAY_SIZE(gcc_xo_200_spi), 694 .ops = &clk_rcg2_ops, 695 }, 696 }; 697 698 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 699 .halt_reg = 0x203c, 700 .clkr = { 701 .enable_reg = 0x203c, 702 .enable_mask = BIT(0), 703 .hw.init = &(struct clk_init_data){ 704 .name = "gcc_blsp1_uart1_apps_clk", 705 .parent_hws = (const struct clk_hw *[]){ 706 &blsp1_uart1_apps_clk_src.clkr.hw }, 707 .flags = CLK_SET_RATE_PARENT, 708 .num_parents = 1, 709 .ops = &clk_branch2_ops, 710 }, 711 }, 712 }; 713 714 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 715 .cmd_rcgr = 0x3034, 716 .mnd_width = 16, 717 .hid_width = 5, 718 .freq_tbl = ftbl_gcc_blsp1_uart1_2_apps_clk, 719 .parent_map = gcc_xo_200_spi_map, 720 .clkr.hw.init = &(struct clk_init_data){ 721 .name = "blsp1_uart2_apps_clk_src", 722 .parent_data = gcc_xo_200_spi, 723 .num_parents = ARRAY_SIZE(gcc_xo_200_spi), 724 .ops = &clk_rcg2_ops, 725 }, 726 }; 727 728 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 729 .halt_reg = 0x302c, 730 .clkr = { 731 .enable_reg = 0x302c, 732 .enable_mask = BIT(0), 733 .hw.init = &(struct clk_init_data){ 734 .name = "gcc_blsp1_uart2_apps_clk", 735 .parent_hws = (const struct clk_hw *[]){ 736 &blsp1_uart2_apps_clk_src.clkr.hw }, 737 .num_parents = 1, 738 .ops = &clk_branch2_ops, 739 .flags = CLK_SET_RATE_PARENT, 740 }, 741 }, 742 }; 743 744 static const struct freq_tbl ftbl_gcc_gp_clk[] = { 745 F(1250000, P_FEPLL200, 1, 16, 0), 746 F(2500000, P_FEPLL200, 1, 8, 0), 747 F(5000000, P_FEPLL200, 1, 4, 0), 748 { } 749 }; 750 751 static struct clk_rcg2 gp1_clk_src = { 752 .cmd_rcgr = 0x8004, 753 .mnd_width = 8, 754 .hid_width = 5, 755 .freq_tbl = ftbl_gcc_gp_clk, 756 .parent_map = gcc_xo_200_map, 757 .clkr.hw.init = &(struct clk_init_data){ 758 .name = "gp1_clk_src", 759 .parent_data = gcc_xo_200, 760 .num_parents = ARRAY_SIZE(gcc_xo_200), 761 .ops = &clk_rcg2_ops, 762 }, 763 }; 764 765 static struct clk_branch gcc_gp1_clk = { 766 .halt_reg = 0x8000, 767 .clkr = { 768 .enable_reg = 0x8000, 769 .enable_mask = BIT(0), 770 .hw.init = &(struct clk_init_data){ 771 .name = "gcc_gp1_clk", 772 .parent_hws = (const struct clk_hw *[]){ 773 &gp1_clk_src.clkr.hw }, 774 .num_parents = 1, 775 .ops = &clk_branch2_ops, 776 .flags = CLK_SET_RATE_PARENT, 777 }, 778 }, 779 }; 780 781 static struct clk_rcg2 gp2_clk_src = { 782 .cmd_rcgr = 0x9004, 783 .mnd_width = 8, 784 .hid_width = 5, 785 .freq_tbl = ftbl_gcc_gp_clk, 786 .parent_map = gcc_xo_200_map, 787 .clkr.hw.init = &(struct clk_init_data){ 788 .name = "gp2_clk_src", 789 .parent_data = gcc_xo_200, 790 .num_parents = ARRAY_SIZE(gcc_xo_200), 791 .ops = &clk_rcg2_ops, 792 }, 793 }; 794 795 static struct clk_branch gcc_gp2_clk = { 796 .halt_reg = 0x9000, 797 .clkr = { 798 .enable_reg = 0x9000, 799 .enable_mask = BIT(0), 800 .hw.init = &(struct clk_init_data){ 801 .name = "gcc_gp2_clk", 802 .parent_hws = (const struct clk_hw *[]){ 803 &gp2_clk_src.clkr.hw }, 804 .num_parents = 1, 805 .ops = &clk_branch2_ops, 806 .flags = CLK_SET_RATE_PARENT, 807 }, 808 }, 809 }; 810 811 static struct clk_rcg2 gp3_clk_src = { 812 .cmd_rcgr = 0xa004, 813 .mnd_width = 8, 814 .hid_width = 5, 815 .freq_tbl = ftbl_gcc_gp_clk, 816 .parent_map = gcc_xo_200_map, 817 .clkr.hw.init = &(struct clk_init_data){ 818 .name = "gp3_clk_src", 819 .parent_data = gcc_xo_200, 820 .num_parents = ARRAY_SIZE(gcc_xo_200), 821 .ops = &clk_rcg2_ops, 822 }, 823 }; 824 825 static struct clk_branch gcc_gp3_clk = { 826 .halt_reg = 0xa000, 827 .clkr = { 828 .enable_reg = 0xa000, 829 .enable_mask = BIT(0), 830 .hw.init = &(struct clk_init_data){ 831 .name = "gcc_gp3_clk", 832 .parent_hws = (const struct clk_hw *[]){ 833 &gp3_clk_src.clkr.hw }, 834 .num_parents = 1, 835 .ops = &clk_branch2_ops, 836 .flags = CLK_SET_RATE_PARENT, 837 }, 838 }, 839 }; 840 841 static struct parent_map gcc_xo_sdcc1_500_map[] = { 842 { P_XO, 0 }, 843 { P_DDRPLL, 1 }, 844 { P_FEPLL500, 2 }, 845 }; 846 847 static const struct clk_parent_data gcc_xo_sdcc1_500[] = { 848 { .fw_name = "xo", .name = "xo" }, 849 { .hw = &gcc_apss_sdcc_clk.cdiv.clkr.hw }, 850 { .hw = &gcc_fepll500_clk.cdiv.clkr.hw }, 851 }; 852 853 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = { 854 F(144000, P_XO, 1, 3, 240), 855 F(400000, P_XO, 1, 1, 0), 856 F(20000000, P_FEPLL500, 1, 1, 25), 857 F(25000000, P_FEPLL500, 1, 1, 20), 858 F(50000000, P_FEPLL500, 1, 1, 10), 859 F(100000000, P_FEPLL500, 1, 1, 5), 860 F(192000000, P_DDRPLL, 1, 0, 0), 861 { } 862 }; 863 864 static struct clk_rcg2 sdcc1_apps_clk_src = { 865 .cmd_rcgr = 0x18004, 866 .hid_width = 5, 867 .freq_tbl = ftbl_gcc_sdcc1_apps_clk, 868 .parent_map = gcc_xo_sdcc1_500_map, 869 .clkr.hw.init = &(struct clk_init_data){ 870 .name = "sdcc1_apps_clk_src", 871 .parent_data = gcc_xo_sdcc1_500, 872 .num_parents = ARRAY_SIZE(gcc_xo_sdcc1_500), 873 .ops = &clk_rcg2_ops, 874 .flags = CLK_SET_RATE_PARENT, 875 }, 876 }; 877 878 static const struct freq_tbl ftbl_gcc_apps_clk[] = { 879 F(48000000, P_XO, 1, 0, 0), 880 F(200000000, P_FEPLL200, 1, 0, 0), 881 F(384000000, P_DDRPLLAPSS, 1, 0, 0), 882 F(413000000, P_DDRPLLAPSS, 1, 0, 0), 883 F(448000000, P_DDRPLLAPSS, 1, 0, 0), 884 F(488000000, P_DDRPLLAPSS, 1, 0, 0), 885 F(500000000, P_FEPLL500, 1, 0, 0), 886 F(512000000, P_DDRPLLAPSS, 1, 0, 0), 887 F(537000000, P_DDRPLLAPSS, 1, 0, 0), 888 F(565000000, P_DDRPLLAPSS, 1, 0, 0), 889 F(597000000, P_DDRPLLAPSS, 1, 0, 0), 890 F(632000000, P_DDRPLLAPSS, 1, 0, 0), 891 F(672000000, P_DDRPLLAPSS, 1, 0, 0), 892 F(716000000, P_DDRPLLAPSS, 1, 0, 0), 893 { } 894 }; 895 896 static struct parent_map gcc_xo_ddr_500_200_map[] = { 897 { P_XO, 0 }, 898 { P_FEPLL200, 3 }, 899 { P_FEPLL500, 2 }, 900 { P_DDRPLLAPSS, 1 }, 901 }; 902 903 static const struct clk_parent_data gcc_xo_ddr_500_200[] = { 904 { .fw_name = "xo", .name = "xo" }, 905 { .hw = &gcc_fepll200_clk.cdiv.clkr.hw }, 906 { .hw = &gcc_fepll500_clk.cdiv.clkr.hw }, 907 { .hw = &gcc_apss_cpu_plldiv_clk.cdiv.clkr.hw }, 908 }; 909 910 static struct clk_rcg2 apps_clk_src = { 911 .cmd_rcgr = 0x1900c, 912 .hid_width = 5, 913 .freq_tbl = ftbl_gcc_apps_clk, 914 .parent_map = gcc_xo_ddr_500_200_map, 915 .clkr.hw.init = &(struct clk_init_data){ 916 .name = "apps_clk_src", 917 .parent_data = gcc_xo_ddr_500_200, 918 .num_parents = ARRAY_SIZE(gcc_xo_ddr_500_200), 919 .ops = &clk_rcg2_ops, 920 .flags = CLK_SET_RATE_PARENT, 921 }, 922 }; 923 924 static const struct freq_tbl ftbl_gcc_apps_ahb_clk[] = { 925 F(48000000, P_XO, 1, 0, 0), 926 F(100000000, P_FEPLL200, 2, 0, 0), 927 { } 928 }; 929 930 static struct clk_rcg2 apps_ahb_clk_src = { 931 .cmd_rcgr = 0x19014, 932 .hid_width = 5, 933 .parent_map = gcc_xo_200_500_map, 934 .freq_tbl = ftbl_gcc_apps_ahb_clk, 935 .clkr.hw.init = &(struct clk_init_data){ 936 .name = "apps_ahb_clk_src", 937 .parent_data = gcc_xo_200_500, 938 .num_parents = ARRAY_SIZE(gcc_xo_200_500), 939 .ops = &clk_rcg2_ops, 940 }, 941 }; 942 943 static struct clk_branch gcc_apss_ahb_clk = { 944 .halt_reg = 0x19004, 945 .halt_check = BRANCH_HALT_VOTED, 946 .clkr = { 947 .enable_reg = 0x6000, 948 .enable_mask = BIT(14), 949 .hw.init = &(struct clk_init_data){ 950 .name = "gcc_apss_ahb_clk", 951 .parent_hws = (const struct clk_hw *[]){ 952 &apps_ahb_clk_src.clkr.hw }, 953 .num_parents = 1, 954 .ops = &clk_branch2_ops, 955 .flags = CLK_SET_RATE_PARENT, 956 }, 957 }, 958 }; 959 960 static struct clk_branch gcc_blsp1_ahb_clk = { 961 .halt_reg = 0x1008, 962 .halt_check = BRANCH_HALT_VOTED, 963 .clkr = { 964 .enable_reg = 0x6000, 965 .enable_mask = BIT(10), 966 .hw.init = &(struct clk_init_data){ 967 .name = "gcc_blsp1_ahb_clk", 968 .parent_hws = (const struct clk_hw *[]){ 969 &pcnoc_clk_src.clkr.hw }, 970 .num_parents = 1, 971 .ops = &clk_branch2_ops, 972 }, 973 }, 974 }; 975 976 static struct clk_branch gcc_dcd_xo_clk = { 977 .halt_reg = 0x2103c, 978 .clkr = { 979 .enable_reg = 0x2103c, 980 .enable_mask = BIT(0), 981 .hw.init = &(struct clk_init_data){ 982 .name = "gcc_dcd_xo_clk", 983 .parent_data = &(const struct clk_parent_data){ 984 .fw_name = "xo", 985 .name = "xo", 986 }, 987 .num_parents = 1, 988 .ops = &clk_branch2_ops, 989 }, 990 }, 991 }; 992 993 static struct clk_branch gcc_boot_rom_ahb_clk = { 994 .halt_reg = 0x1300c, 995 .clkr = { 996 .enable_reg = 0x1300c, 997 .enable_mask = BIT(0), 998 .hw.init = &(struct clk_init_data){ 999 .name = "gcc_boot_rom_ahb_clk", 1000 .parent_hws = (const struct clk_hw *[]){ 1001 &pcnoc_clk_src.clkr.hw }, 1002 .num_parents = 1, 1003 .ops = &clk_branch2_ops, 1004 .flags = CLK_SET_RATE_PARENT, 1005 }, 1006 }, 1007 }; 1008 1009 static struct clk_branch gcc_crypto_ahb_clk = { 1010 .halt_reg = 0x16024, 1011 .halt_check = BRANCH_HALT_VOTED, 1012 .clkr = { 1013 .enable_reg = 0x6000, 1014 .enable_mask = BIT(0), 1015 .hw.init = &(struct clk_init_data){ 1016 .name = "gcc_crypto_ahb_clk", 1017 .parent_hws = (const struct clk_hw *[]){ 1018 &pcnoc_clk_src.clkr.hw }, 1019 .num_parents = 1, 1020 .ops = &clk_branch2_ops, 1021 }, 1022 }, 1023 }; 1024 1025 static struct clk_branch gcc_crypto_axi_clk = { 1026 .halt_reg = 0x16020, 1027 .halt_check = BRANCH_HALT_VOTED, 1028 .clkr = { 1029 .enable_reg = 0x6000, 1030 .enable_mask = BIT(1), 1031 .hw.init = &(struct clk_init_data){ 1032 .name = "gcc_crypto_axi_clk", 1033 .parent_hws = (const struct clk_hw *[]){ 1034 &gcc_fepll125_clk.cdiv.clkr.hw }, 1035 .num_parents = 1, 1036 .ops = &clk_branch2_ops, 1037 }, 1038 }, 1039 }; 1040 1041 static struct clk_branch gcc_crypto_clk = { 1042 .halt_reg = 0x1601c, 1043 .halt_check = BRANCH_HALT_VOTED, 1044 .clkr = { 1045 .enable_reg = 0x6000, 1046 .enable_mask = BIT(2), 1047 .hw.init = &(struct clk_init_data){ 1048 .name = "gcc_crypto_clk", 1049 .parent_hws = (const struct clk_hw *[]){ 1050 &gcc_fepll125_clk.cdiv.clkr.hw }, 1051 .num_parents = 1, 1052 .ops = &clk_branch2_ops, 1053 }, 1054 }, 1055 }; 1056 1057 static struct parent_map gcc_xo_125_dly_map[] = { 1058 { P_XO, 0 }, 1059 { P_FEPLL125DLY, 1 }, 1060 }; 1061 1062 static const struct clk_parent_data gcc_xo_125_dly[] = { 1063 { .fw_name = "xo", .name = "xo" }, 1064 { .hw = &gcc_fepll125dly_clk.cdiv.clkr.hw }, 1065 }; 1066 1067 static const struct freq_tbl ftbl_gcc_fephy_dly_clk[] = { 1068 F(125000000, P_FEPLL125DLY, 1, 0, 0), 1069 { } 1070 }; 1071 1072 static struct clk_rcg2 fephy_125m_dly_clk_src = { 1073 .cmd_rcgr = 0x12000, 1074 .hid_width = 5, 1075 .parent_map = gcc_xo_125_dly_map, 1076 .freq_tbl = ftbl_gcc_fephy_dly_clk, 1077 .clkr.hw.init = &(struct clk_init_data){ 1078 .name = "fephy_125m_dly_clk_src", 1079 .parent_data = gcc_xo_125_dly, 1080 .num_parents = ARRAY_SIZE(gcc_xo_125_dly), 1081 .ops = &clk_rcg2_ops, 1082 }, 1083 }; 1084 1085 static struct clk_branch gcc_ess_clk = { 1086 .halt_reg = 0x12010, 1087 .clkr = { 1088 .enable_reg = 0x12010, 1089 .enable_mask = BIT(0), 1090 .hw.init = &(struct clk_init_data){ 1091 .name = "gcc_ess_clk", 1092 .parent_hws = (const struct clk_hw *[]){ 1093 &fephy_125m_dly_clk_src.clkr.hw }, 1094 .num_parents = 1, 1095 .ops = &clk_branch2_ops, 1096 .flags = CLK_SET_RATE_PARENT, 1097 }, 1098 }, 1099 }; 1100 1101 static struct clk_branch gcc_imem_axi_clk = { 1102 .halt_reg = 0xe004, 1103 .halt_check = BRANCH_HALT_VOTED, 1104 .clkr = { 1105 .enable_reg = 0x6000, 1106 .enable_mask = BIT(17), 1107 .hw.init = &(struct clk_init_data){ 1108 .name = "gcc_imem_axi_clk", 1109 .parent_hws = (const struct clk_hw *[]){ 1110 &gcc_fepll200_clk.cdiv.clkr.hw }, 1111 .num_parents = 1, 1112 .ops = &clk_branch2_ops, 1113 }, 1114 }, 1115 }; 1116 1117 static struct clk_branch gcc_imem_cfg_ahb_clk = { 1118 .halt_reg = 0xe008, 1119 .clkr = { 1120 .enable_reg = 0xe008, 1121 .enable_mask = BIT(0), 1122 .hw.init = &(struct clk_init_data){ 1123 .name = "gcc_imem_cfg_ahb_clk", 1124 .parent_hws = (const struct clk_hw *[]){ 1125 &pcnoc_clk_src.clkr.hw }, 1126 .num_parents = 1, 1127 .ops = &clk_branch2_ops, 1128 }, 1129 }, 1130 }; 1131 1132 static struct clk_branch gcc_pcie_ahb_clk = { 1133 .halt_reg = 0x1d00c, 1134 .clkr = { 1135 .enable_reg = 0x1d00c, 1136 .enable_mask = BIT(0), 1137 .hw.init = &(struct clk_init_data){ 1138 .name = "gcc_pcie_ahb_clk", 1139 .parent_hws = (const struct clk_hw *[]){ 1140 &pcnoc_clk_src.clkr.hw }, 1141 .num_parents = 1, 1142 .ops = &clk_branch2_ops, 1143 }, 1144 }, 1145 }; 1146 1147 static struct clk_branch gcc_pcie_axi_m_clk = { 1148 .halt_reg = 0x1d004, 1149 .clkr = { 1150 .enable_reg = 0x1d004, 1151 .enable_mask = BIT(0), 1152 .hw.init = &(struct clk_init_data){ 1153 .name = "gcc_pcie_axi_m_clk", 1154 .parent_hws = (const struct clk_hw *[]){ 1155 &gcc_fepll200_clk.cdiv.clkr.hw }, 1156 .num_parents = 1, 1157 .ops = &clk_branch2_ops, 1158 }, 1159 }, 1160 }; 1161 1162 static struct clk_branch gcc_pcie_axi_s_clk = { 1163 .halt_reg = 0x1d008, 1164 .clkr = { 1165 .enable_reg = 0x1d008, 1166 .enable_mask = BIT(0), 1167 .hw.init = &(struct clk_init_data){ 1168 .name = "gcc_pcie_axi_s_clk", 1169 .parent_hws = (const struct clk_hw *[]){ 1170 &gcc_fepll200_clk.cdiv.clkr.hw }, 1171 .num_parents = 1, 1172 .ops = &clk_branch2_ops, 1173 }, 1174 }, 1175 }; 1176 1177 static struct clk_branch gcc_prng_ahb_clk = { 1178 .halt_reg = 0x13004, 1179 .halt_check = BRANCH_HALT_VOTED, 1180 .clkr = { 1181 .enable_reg = 0x6000, 1182 .enable_mask = BIT(8), 1183 .hw.init = &(struct clk_init_data){ 1184 .name = "gcc_prng_ahb_clk", 1185 .parent_hws = (const struct clk_hw *[]){ 1186 &pcnoc_clk_src.clkr.hw }, 1187 .num_parents = 1, 1188 .ops = &clk_branch2_ops, 1189 }, 1190 }, 1191 }; 1192 1193 static struct clk_branch gcc_qpic_ahb_clk = { 1194 .halt_reg = 0x1c008, 1195 .clkr = { 1196 .enable_reg = 0x1c008, 1197 .enable_mask = BIT(0), 1198 .hw.init = &(struct clk_init_data){ 1199 .name = "gcc_qpic_ahb_clk", 1200 .parent_hws = (const struct clk_hw *[]){ 1201 &pcnoc_clk_src.clkr.hw }, 1202 .num_parents = 1, 1203 .ops = &clk_branch2_ops, 1204 }, 1205 }, 1206 }; 1207 1208 static struct clk_branch gcc_qpic_clk = { 1209 .halt_reg = 0x1c004, 1210 .clkr = { 1211 .enable_reg = 0x1c004, 1212 .enable_mask = BIT(0), 1213 .hw.init = &(struct clk_init_data){ 1214 .name = "gcc_qpic_clk", 1215 .parent_hws = (const struct clk_hw *[]){ 1216 &pcnoc_clk_src.clkr.hw }, 1217 .num_parents = 1, 1218 .ops = &clk_branch2_ops, 1219 }, 1220 }, 1221 }; 1222 1223 static struct clk_branch gcc_sdcc1_ahb_clk = { 1224 .halt_reg = 0x18010, 1225 .clkr = { 1226 .enable_reg = 0x18010, 1227 .enable_mask = BIT(0), 1228 .hw.init = &(struct clk_init_data){ 1229 .name = "gcc_sdcc1_ahb_clk", 1230 .parent_hws = (const struct clk_hw *[]){ 1231 &pcnoc_clk_src.clkr.hw }, 1232 .num_parents = 1, 1233 .ops = &clk_branch2_ops, 1234 }, 1235 }, 1236 }; 1237 1238 static struct clk_branch gcc_sdcc1_apps_clk = { 1239 .halt_reg = 0x1800c, 1240 .clkr = { 1241 .enable_reg = 0x1800c, 1242 .enable_mask = BIT(0), 1243 .hw.init = &(struct clk_init_data){ 1244 .name = "gcc_sdcc1_apps_clk", 1245 .parent_hws = (const struct clk_hw *[]){ 1246 &sdcc1_apps_clk_src.clkr.hw }, 1247 .num_parents = 1, 1248 .ops = &clk_branch2_ops, 1249 .flags = CLK_SET_RATE_PARENT, 1250 }, 1251 }, 1252 }; 1253 1254 static struct clk_branch gcc_tlmm_ahb_clk = { 1255 .halt_reg = 0x5004, 1256 .halt_check = BRANCH_HALT_VOTED, 1257 .clkr = { 1258 .enable_reg = 0x6000, 1259 .enable_mask = BIT(5), 1260 .hw.init = &(struct clk_init_data){ 1261 .name = "gcc_tlmm_ahb_clk", 1262 .parent_hws = (const struct clk_hw *[]){ 1263 &pcnoc_clk_src.clkr.hw }, 1264 .num_parents = 1, 1265 .ops = &clk_branch2_ops, 1266 }, 1267 }, 1268 }; 1269 1270 static struct clk_branch gcc_usb2_master_clk = { 1271 .halt_reg = 0x1e00c, 1272 .clkr = { 1273 .enable_reg = 0x1e00c, 1274 .enable_mask = BIT(0), 1275 .hw.init = &(struct clk_init_data){ 1276 .name = "gcc_usb2_master_clk", 1277 .parent_hws = (const struct clk_hw *[]){ 1278 &pcnoc_clk_src.clkr.hw }, 1279 .num_parents = 1, 1280 .ops = &clk_branch2_ops, 1281 }, 1282 }, 1283 }; 1284 1285 static struct clk_branch gcc_usb2_sleep_clk = { 1286 .halt_reg = 0x1e010, 1287 .clkr = { 1288 .enable_reg = 0x1e010, 1289 .enable_mask = BIT(0), 1290 .hw.init = &(struct clk_init_data){ 1291 .name = "gcc_usb2_sleep_clk", 1292 .parent_data = &(const struct clk_parent_data){ 1293 .fw_name = "sleep_clk", 1294 .name = "gcc_sleep_clk_src", 1295 }, 1296 .num_parents = 1, 1297 .ops = &clk_branch2_ops, 1298 }, 1299 }, 1300 }; 1301 1302 static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = { 1303 F(2000000, P_FEPLL200, 10, 0, 0), 1304 { } 1305 }; 1306 1307 static struct clk_rcg2 usb30_mock_utmi_clk_src = { 1308 .cmd_rcgr = 0x1e000, 1309 .hid_width = 5, 1310 .parent_map = gcc_xo_200_map, 1311 .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk, 1312 .clkr.hw.init = &(struct clk_init_data){ 1313 .name = "usb30_mock_utmi_clk_src", 1314 .parent_data = gcc_xo_200, 1315 .num_parents = ARRAY_SIZE(gcc_xo_200), 1316 .ops = &clk_rcg2_ops, 1317 }, 1318 }; 1319 1320 static struct clk_branch gcc_usb2_mock_utmi_clk = { 1321 .halt_reg = 0x1e014, 1322 .clkr = { 1323 .enable_reg = 0x1e014, 1324 .enable_mask = BIT(0), 1325 .hw.init = &(struct clk_init_data){ 1326 .name = "gcc_usb2_mock_utmi_clk", 1327 .parent_hws = (const struct clk_hw *[]){ 1328 &usb30_mock_utmi_clk_src.clkr.hw }, 1329 .num_parents = 1, 1330 .ops = &clk_branch2_ops, 1331 .flags = CLK_SET_RATE_PARENT, 1332 }, 1333 }, 1334 }; 1335 1336 static struct clk_branch gcc_usb3_master_clk = { 1337 .halt_reg = 0x1e028, 1338 .clkr = { 1339 .enable_reg = 0x1e028, 1340 .enable_mask = BIT(0), 1341 .hw.init = &(struct clk_init_data){ 1342 .name = "gcc_usb3_master_clk", 1343 .parent_hws = (const struct clk_hw *[]){ 1344 &gcc_fepll125_clk.cdiv.clkr.hw }, 1345 .num_parents = 1, 1346 .ops = &clk_branch2_ops, 1347 }, 1348 }, 1349 }; 1350 1351 static struct clk_branch gcc_usb3_sleep_clk = { 1352 .halt_reg = 0x1e02C, 1353 .clkr = { 1354 .enable_reg = 0x1e02C, 1355 .enable_mask = BIT(0), 1356 .hw.init = &(struct clk_init_data){ 1357 .name = "gcc_usb3_sleep_clk", 1358 .parent_data = &(const struct clk_parent_data){ 1359 .fw_name = "sleep_clk", 1360 .name = "gcc_sleep_clk_src", 1361 }, 1362 .num_parents = 1, 1363 .ops = &clk_branch2_ops, 1364 }, 1365 }, 1366 }; 1367 1368 static struct clk_branch gcc_usb3_mock_utmi_clk = { 1369 .halt_reg = 0x1e030, 1370 .clkr = { 1371 .enable_reg = 0x1e030, 1372 .enable_mask = BIT(0), 1373 .hw.init = &(struct clk_init_data){ 1374 .name = "gcc_usb3_mock_utmi_clk", 1375 .parent_hws = (const struct clk_hw *[]){ 1376 &usb30_mock_utmi_clk_src.clkr.hw }, 1377 .num_parents = 1, 1378 .ops = &clk_branch2_ops, 1379 .flags = CLK_SET_RATE_PARENT, 1380 }, 1381 }, 1382 }; 1383 1384 static struct parent_map gcc_xo_wcss2g_map[] = { 1385 { P_XO, 0 }, 1386 { P_FEPLLWCSS2G, 1 }, 1387 }; 1388 1389 static const struct clk_parent_data gcc_xo_wcss2g[] = { 1390 { .fw_name = "xo", .name = "xo" }, 1391 { .hw = &gcc_fepllwcss2g_clk.cdiv.clkr.hw }, 1392 }; 1393 1394 static const struct freq_tbl ftbl_gcc_wcss2g_clk[] = { 1395 F(48000000, P_XO, 1, 0, 0), 1396 F(250000000, P_FEPLLWCSS2G, 1, 0, 0), 1397 { } 1398 }; 1399 1400 static struct clk_rcg2 wcss2g_clk_src = { 1401 .cmd_rcgr = 0x1f000, 1402 .hid_width = 5, 1403 .freq_tbl = ftbl_gcc_wcss2g_clk, 1404 .parent_map = gcc_xo_wcss2g_map, 1405 .clkr.hw.init = &(struct clk_init_data){ 1406 .name = "wcss2g_clk_src", 1407 .parent_data = gcc_xo_wcss2g, 1408 .num_parents = ARRAY_SIZE(gcc_xo_wcss2g), 1409 .ops = &clk_rcg2_ops, 1410 .flags = CLK_SET_RATE_PARENT, 1411 }, 1412 }; 1413 1414 static struct clk_branch gcc_wcss2g_clk = { 1415 .halt_reg = 0x1f00C, 1416 .clkr = { 1417 .enable_reg = 0x1f00C, 1418 .enable_mask = BIT(0), 1419 .hw.init = &(struct clk_init_data){ 1420 .name = "gcc_wcss2g_clk", 1421 .parent_hws = (const struct clk_hw *[]){ 1422 &wcss2g_clk_src.clkr.hw }, 1423 .num_parents = 1, 1424 .ops = &clk_branch2_ops, 1425 .flags = CLK_SET_RATE_PARENT, 1426 }, 1427 }, 1428 }; 1429 1430 static struct clk_branch gcc_wcss2g_ref_clk = { 1431 .halt_reg = 0x1f00C, 1432 .clkr = { 1433 .enable_reg = 0x1f00C, 1434 .enable_mask = BIT(0), 1435 .hw.init = &(struct clk_init_data){ 1436 .name = "gcc_wcss2g_ref_clk", 1437 .parent_data = &(const struct clk_parent_data){ 1438 .fw_name = "xo", 1439 .name = "xo", 1440 }, 1441 .num_parents = 1, 1442 .ops = &clk_branch2_ops, 1443 .flags = CLK_SET_RATE_PARENT, 1444 }, 1445 }, 1446 }; 1447 1448 static struct clk_branch gcc_wcss2g_rtc_clk = { 1449 .halt_reg = 0x1f010, 1450 .clkr = { 1451 .enable_reg = 0x1f010, 1452 .enable_mask = BIT(0), 1453 .hw.init = &(struct clk_init_data){ 1454 .name = "gcc_wcss2g_rtc_clk", 1455 .parent_data = &(const struct clk_parent_data){ 1456 .fw_name = "sleep_clk", 1457 .name = "gcc_sleep_clk_src", 1458 }, 1459 .num_parents = 1, 1460 .ops = &clk_branch2_ops, 1461 }, 1462 }, 1463 }; 1464 1465 static struct parent_map gcc_xo_wcss5g_map[] = { 1466 { P_XO, 0 }, 1467 { P_FEPLLWCSS5G, 1 }, 1468 }; 1469 1470 static const struct clk_parent_data gcc_xo_wcss5g[] = { 1471 { .fw_name = "xo", .name = "xo" }, 1472 { .hw = &gcc_fepllwcss5g_clk.cdiv.clkr.hw }, 1473 }; 1474 1475 static const struct freq_tbl ftbl_gcc_wcss5g_clk[] = { 1476 F(48000000, P_XO, 1, 0, 0), 1477 F(250000000, P_FEPLLWCSS5G, 1, 0, 0), 1478 { } 1479 }; 1480 1481 static struct clk_rcg2 wcss5g_clk_src = { 1482 .cmd_rcgr = 0x20000, 1483 .hid_width = 5, 1484 .parent_map = gcc_xo_wcss5g_map, 1485 .freq_tbl = ftbl_gcc_wcss5g_clk, 1486 .clkr.hw.init = &(struct clk_init_data){ 1487 .name = "wcss5g_clk_src", 1488 .parent_data = gcc_xo_wcss5g, 1489 .num_parents = ARRAY_SIZE(gcc_xo_wcss5g), 1490 .ops = &clk_rcg2_ops, 1491 }, 1492 }; 1493 1494 static struct clk_branch gcc_wcss5g_clk = { 1495 .halt_reg = 0x2000c, 1496 .clkr = { 1497 .enable_reg = 0x2000c, 1498 .enable_mask = BIT(0), 1499 .hw.init = &(struct clk_init_data){ 1500 .name = "gcc_wcss5g_clk", 1501 .parent_hws = (const struct clk_hw *[]){ 1502 &wcss5g_clk_src.clkr.hw }, 1503 .num_parents = 1, 1504 .ops = &clk_branch2_ops, 1505 .flags = CLK_SET_RATE_PARENT, 1506 }, 1507 }, 1508 }; 1509 1510 static struct clk_branch gcc_wcss5g_ref_clk = { 1511 .halt_reg = 0x2000c, 1512 .clkr = { 1513 .enable_reg = 0x2000c, 1514 .enable_mask = BIT(0), 1515 .hw.init = &(struct clk_init_data){ 1516 .name = "gcc_wcss5g_ref_clk", 1517 .parent_data = &(const struct clk_parent_data){ 1518 .fw_name = "xo", 1519 .name = "xo", 1520 }, 1521 .num_parents = 1, 1522 .ops = &clk_branch2_ops, 1523 .flags = CLK_SET_RATE_PARENT, 1524 }, 1525 }, 1526 }; 1527 1528 static struct clk_branch gcc_wcss5g_rtc_clk = { 1529 .halt_reg = 0x20010, 1530 .clkr = { 1531 .enable_reg = 0x20010, 1532 .enable_mask = BIT(0), 1533 .hw.init = &(struct clk_init_data){ 1534 .name = "gcc_wcss5g_rtc_clk", 1535 .parent_data = &(const struct clk_parent_data){ 1536 .fw_name = "sleep_clk", 1537 .name = "gcc_sleep_clk_src", 1538 }, 1539 .num_parents = 1, 1540 .ops = &clk_branch2_ops, 1541 .flags = CLK_SET_RATE_PARENT, 1542 }, 1543 }, 1544 }; 1545 1546 static struct clk_regmap *gcc_ipq4019_clocks[] = { 1547 [AUDIO_CLK_SRC] = &audio_clk_src.clkr, 1548 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 1549 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 1550 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 1551 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 1552 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 1553 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 1554 [GCC_USB3_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, 1555 [GCC_APPS_CLK_SRC] = &apps_clk_src.clkr, 1556 [GCC_APPS_AHB_CLK_SRC] = &apps_ahb_clk_src.clkr, 1557 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 1558 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 1559 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 1560 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 1561 [FEPHY_125M_DLY_CLK_SRC] = &fephy_125m_dly_clk_src.clkr, 1562 [WCSS2G_CLK_SRC] = &wcss2g_clk_src.clkr, 1563 [WCSS5G_CLK_SRC] = &wcss5g_clk_src.clkr, 1564 [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr, 1565 [GCC_AUDIO_AHB_CLK] = &gcc_audio_ahb_clk.clkr, 1566 [GCC_AUDIO_PWM_CLK] = &gcc_audio_pwm_clk.clkr, 1567 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 1568 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 1569 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 1570 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 1571 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 1572 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 1573 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 1574 [GCC_DCD_XO_CLK] = &gcc_dcd_xo_clk.clkr, 1575 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 1576 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 1577 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 1578 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 1579 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, 1580 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, 1581 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, 1582 [GCC_ESS_CLK] = &gcc_ess_clk.clkr, 1583 [GCC_IMEM_AXI_CLK] = &gcc_imem_axi_clk.clkr, 1584 [GCC_IMEM_CFG_AHB_CLK] = &gcc_imem_cfg_ahb_clk.clkr, 1585 [GCC_PCIE_AHB_CLK] = &gcc_pcie_ahb_clk.clkr, 1586 [GCC_PCIE_AXI_M_CLK] = &gcc_pcie_axi_m_clk.clkr, 1587 [GCC_PCIE_AXI_S_CLK] = &gcc_pcie_axi_s_clk.clkr, 1588 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 1589 [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr, 1590 [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr, 1591 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 1592 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 1593 [GCC_TLMM_AHB_CLK] = &gcc_tlmm_ahb_clk.clkr, 1594 [GCC_USB2_MASTER_CLK] = &gcc_usb2_master_clk.clkr, 1595 [GCC_USB2_SLEEP_CLK] = &gcc_usb2_sleep_clk.clkr, 1596 [GCC_USB2_MOCK_UTMI_CLK] = &gcc_usb2_mock_utmi_clk.clkr, 1597 [GCC_USB3_MASTER_CLK] = &gcc_usb3_master_clk.clkr, 1598 [GCC_USB3_SLEEP_CLK] = &gcc_usb3_sleep_clk.clkr, 1599 [GCC_USB3_MOCK_UTMI_CLK] = &gcc_usb3_mock_utmi_clk.clkr, 1600 [GCC_WCSS2G_CLK] = &gcc_wcss2g_clk.clkr, 1601 [GCC_WCSS2G_REF_CLK] = &gcc_wcss2g_ref_clk.clkr, 1602 [GCC_WCSS2G_RTC_CLK] = &gcc_wcss2g_rtc_clk.clkr, 1603 [GCC_WCSS5G_CLK] = &gcc_wcss5g_clk.clkr, 1604 [GCC_WCSS5G_REF_CLK] = &gcc_wcss5g_ref_clk.clkr, 1605 [GCC_WCSS5G_RTC_CLK] = &gcc_wcss5g_rtc_clk.clkr, 1606 [GCC_SDCC_PLLDIV_CLK] = &gcc_apss_sdcc_clk.cdiv.clkr, 1607 [GCC_FEPLL125_CLK] = &gcc_fepll125_clk.cdiv.clkr, 1608 [GCC_FEPLL125DLY_CLK] = &gcc_fepll125dly_clk.cdiv.clkr, 1609 [GCC_FEPLL200_CLK] = &gcc_fepll200_clk.cdiv.clkr, 1610 [GCC_FEPLL500_CLK] = &gcc_fepll500_clk.cdiv.clkr, 1611 [GCC_FEPLL_WCSS2G_CLK] = &gcc_fepllwcss2g_clk.cdiv.clkr, 1612 [GCC_FEPLL_WCSS5G_CLK] = &gcc_fepllwcss5g_clk.cdiv.clkr, 1613 [GCC_APSS_CPU_PLLDIV_CLK] = &gcc_apss_cpu_plldiv_clk.cdiv.clkr, 1614 [GCC_PCNOC_AHB_CLK_SRC] = &gcc_pcnoc_ahb_clk_src.clkr, 1615 [GCC_PCNOC_AHB_CLK] = &pcnoc_clk_src.clkr, 1616 }; 1617 1618 static const struct qcom_reset_map gcc_ipq4019_resets[] = { 1619 [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 }, 1620 [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 }, 1621 [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 }, 1622 [WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 }, 1623 [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 }, 1624 [WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 }, 1625 [WIFI1_CPU_INIT_RESET] = { 0x20008, 5 }, 1626 [WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 }, 1627 [WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 }, 1628 [WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 }, 1629 [WIFI1_CORE_WARM_RESET] = { 0x20008, 1 }, 1630 [WIFI1_CORE_COLD_RESET] = { 0x20008, 0 }, 1631 [USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 }, 1632 [USB3_HSPHY_POR_ARES] = { 0x1e038, 4 }, 1633 [USB3_HSPHY_S_ARES] = { 0x1e038, 2 }, 1634 [USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 }, 1635 [USB2_HSPHY_S_ARES] = { 0x1e01c, 2 }, 1636 [PCIE_PHY_AHB_ARES] = { 0x1d010, 11 }, 1637 [PCIE_AHB_ARES] = { 0x1d010, 10 }, 1638 [PCIE_PWR_ARES] = { 0x1d010, 9 }, 1639 [PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 }, 1640 [PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 }, 1641 [PCIE_PHY_ARES] = { 0x1d010, 6 }, 1642 [PCIE_PARF_XPU_ARES] = { 0x1d010, 5 }, 1643 [PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 }, 1644 [PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 }, 1645 [PCIE_PIPE_ARES] = { 0x1d010, 2 }, 1646 [PCIE_AXI_S_ARES] = { 0x1d010, 1 }, 1647 [PCIE_AXI_M_ARES] = { 0x1d010, 0 }, 1648 [ESS_RESET] = { 0x12008, 0}, 1649 [GCC_BLSP1_BCR] = {0x01000, 0}, 1650 [GCC_BLSP1_QUP1_BCR] = {0x02000, 0}, 1651 [GCC_BLSP1_UART1_BCR] = {0x02038, 0}, 1652 [GCC_BLSP1_QUP2_BCR] = {0x03008, 0}, 1653 [GCC_BLSP1_UART2_BCR] = {0x03028, 0}, 1654 [GCC_BIMC_BCR] = {0x04000, 0}, 1655 [GCC_TLMM_BCR] = {0x05000, 0}, 1656 [GCC_IMEM_BCR] = {0x0E000, 0}, 1657 [GCC_ESS_BCR] = {0x12008, 0}, 1658 [GCC_PRNG_BCR] = {0x13000, 0}, 1659 [GCC_BOOT_ROM_BCR] = {0x13008, 0}, 1660 [GCC_CRYPTO_BCR] = {0x16000, 0}, 1661 [GCC_SDCC1_BCR] = {0x18000, 0}, 1662 [GCC_SEC_CTRL_BCR] = {0x1A000, 0}, 1663 [GCC_AUDIO_BCR] = {0x1B008, 0}, 1664 [GCC_QPIC_BCR] = {0x1C000, 0}, 1665 [GCC_PCIE_BCR] = {0x1D000, 0}, 1666 [GCC_USB2_BCR] = {0x1E008, 0}, 1667 [GCC_USB2_PHY_BCR] = {0x1E018, 0}, 1668 [GCC_USB3_BCR] = {0x1E024, 0}, 1669 [GCC_USB3_PHY_BCR] = {0x1E034, 0}, 1670 [GCC_SYSTEM_NOC_BCR] = {0x21000, 0}, 1671 [GCC_PCNOC_BCR] = {0x2102C, 0}, 1672 [GCC_DCD_BCR] = {0x21038, 0}, 1673 [GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0}, 1674 [GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0}, 1675 [GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0}, 1676 [GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0}, 1677 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0}, 1678 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0}, 1679 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0}, 1680 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0}, 1681 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0}, 1682 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0}, 1683 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0}, 1684 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0}, 1685 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0}, 1686 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0}, 1687 [GCC_TCSR_BCR] = {0x22000, 0}, 1688 [GCC_MPM_BCR] = {0x24000, 0}, 1689 [GCC_SPDM_BCR] = {0x25000, 0}, 1690 [ESS_MAC1_ARES] = {0x1200C, 0}, 1691 [ESS_MAC2_ARES] = {0x1200C, 1}, 1692 [ESS_MAC3_ARES] = {0x1200C, 2}, 1693 [ESS_MAC4_ARES] = {0x1200C, 3}, 1694 [ESS_MAC5_ARES] = {0x1200C, 4}, 1695 [ESS_PSGMII_ARES] = {0x1200C, 5}, 1696 }; 1697 1698 static const struct regmap_config gcc_ipq4019_regmap_config = { 1699 .reg_bits = 32, 1700 .reg_stride = 4, 1701 .val_bits = 32, 1702 .max_register = 0x2ffff, 1703 .fast_io = true, 1704 }; 1705 1706 static const struct qcom_cc_desc gcc_ipq4019_desc = { 1707 .config = &gcc_ipq4019_regmap_config, 1708 .clks = gcc_ipq4019_clocks, 1709 .num_clks = ARRAY_SIZE(gcc_ipq4019_clocks), 1710 .resets = gcc_ipq4019_resets, 1711 .num_resets = ARRAY_SIZE(gcc_ipq4019_resets), 1712 }; 1713 1714 static const struct of_device_id gcc_ipq4019_match_table[] = { 1715 { .compatible = "qcom,gcc-ipq4019" }, 1716 { } 1717 }; 1718 MODULE_DEVICE_TABLE(of, gcc_ipq4019_match_table); 1719 1720 static int 1721 gcc_ipq4019_cpu_clk_notifier_fn(struct notifier_block *nb, 1722 unsigned long action, void *data) 1723 { 1724 int err = 0; 1725 1726 if (action == PRE_RATE_CHANGE) 1727 err = clk_rcg2_ops.set_parent(&apps_clk_src.clkr.hw, 1728 gcc_ipq4019_cpu_safe_parent); 1729 1730 return notifier_from_errno(err); 1731 } 1732 1733 static struct notifier_block gcc_ipq4019_cpu_clk_notifier = { 1734 .notifier_call = gcc_ipq4019_cpu_clk_notifier_fn, 1735 }; 1736 1737 static int gcc_ipq4019_probe(struct platform_device *pdev) 1738 { 1739 int err; 1740 1741 err = qcom_cc_probe(pdev, &gcc_ipq4019_desc); 1742 if (err) 1743 return err; 1744 1745 return devm_clk_notifier_register(&pdev->dev, apps_clk_src.clkr.hw.clk, 1746 &gcc_ipq4019_cpu_clk_notifier); 1747 } 1748 1749 static struct platform_driver gcc_ipq4019_driver = { 1750 .probe = gcc_ipq4019_probe, 1751 .driver = { 1752 .name = "qcom,gcc-ipq4019", 1753 .of_match_table = gcc_ipq4019_match_table, 1754 }, 1755 }; 1756 1757 static int __init gcc_ipq4019_init(void) 1758 { 1759 return platform_driver_register(&gcc_ipq4019_driver); 1760 } 1761 core_initcall(gcc_ipq4019_init); 1762 1763 static void __exit gcc_ipq4019_exit(void) 1764 { 1765 platform_driver_unregister(&gcc_ipq4019_driver); 1766 } 1767 module_exit(gcc_ipq4019_exit); 1768 1769 MODULE_ALIAS("platform:gcc-ipq4019"); 1770 MODULE_LICENSE("GPL v2"); 1771 MODULE_DESCRIPTION("QCOM GCC IPQ4019 driver"); 1772