1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2025, Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,glymur-gcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-pll.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "clk-regmap-divider.h" 20 #include "clk-regmap-mux.h" 21 #include "clk-regmap-phy-mux.h" 22 #include "common.h" 23 #include "gdsc.h" 24 #include "reset.h" 25 26 enum { 27 DT_BI_TCXO, 28 DT_BI_TCXO_AO, 29 DT_SLEEP_CLK, 30 DT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC, 31 DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC, 32 DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC, 33 DT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC, 34 DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC, 35 DT_GCC_USB4_1_PHY_DP0_GMUX_2_CLK_SRC, 36 DT_GCC_USB4_1_PHY_DP1_GMUX_2_CLK_SRC, 37 DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC, 38 DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, 39 DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 40 DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC, 41 DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC, 42 DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC, 43 DT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC, 44 DT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC, 45 DT_PCIE_3A_PIPE_CLK, 46 DT_PCIE_3B_PIPE_CLK, 47 DT_PCIE_4_PIPE_CLK, 48 DT_PCIE_5_PIPE_CLK, 49 DT_PCIE_6_PIPE_CLK, 50 DT_QUSB4PHY_0_GCC_USB4_RX0_CLK, 51 DT_QUSB4PHY_0_GCC_USB4_RX1_CLK, 52 DT_QUSB4PHY_1_GCC_USB4_RX0_CLK, 53 DT_QUSB4PHY_1_GCC_USB4_RX1_CLK, 54 DT_QUSB4PHY_2_GCC_USB4_RX0_CLK, 55 DT_QUSB4PHY_2_GCC_USB4_RX1_CLK, 56 DT_UFS_PHY_RX_SYMBOL_0_CLK, 57 DT_UFS_PHY_RX_SYMBOL_1_CLK, 58 DT_UFS_PHY_TX_SYMBOL_0_CLK, 59 DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 60 DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 61 DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 62 DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK, 63 DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK, 64 DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 65 DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 66 DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 67 DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 68 DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 69 DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 70 }; 71 72 enum { 73 P_BI_TCXO, 74 P_GCC_GPLL0_OUT_EVEN, 75 P_GCC_GPLL0_OUT_MAIN, 76 P_GCC_GPLL14_OUT_EVEN, 77 P_GCC_GPLL14_OUT_MAIN, 78 P_GCC_GPLL1_OUT_MAIN, 79 P_GCC_GPLL4_OUT_MAIN, 80 P_GCC_GPLL5_OUT_MAIN, 81 P_GCC_GPLL7_OUT_MAIN, 82 P_GCC_GPLL8_OUT_MAIN, 83 P_GCC_GPLL9_OUT_MAIN, 84 P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 85 P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC, 86 P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC, 87 P_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC, 88 P_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC, 89 P_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC, 90 P_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC, 91 P_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC, 92 P_GCC_USB4_1_PHY_DP0_GMUX_2_CLK_SRC, 93 P_GCC_USB4_1_PHY_DP1_GMUX_2_CLK_SRC, 94 P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC, 95 P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, 96 P_GCC_USB4_1_PHY_PLL_PIPE_CLK_SRC, 97 P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 98 P_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC, 99 P_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC, 100 P_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC, 101 P_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC, 102 P_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC, 103 P_PCIE_3A_PIPE_CLK, 104 P_PCIE_3B_PIPE_CLK, 105 P_PCIE_4_PIPE_CLK, 106 P_PCIE_5_PIPE_CLK, 107 P_PCIE_6_PIPE_CLK, 108 P_QUSB4PHY_0_GCC_USB4_RX0_CLK, 109 P_QUSB4PHY_0_GCC_USB4_RX1_CLK, 110 P_QUSB4PHY_1_GCC_USB4_RX0_CLK, 111 P_QUSB4PHY_1_GCC_USB4_RX1_CLK, 112 P_QUSB4PHY_2_GCC_USB4_RX0_CLK, 113 P_QUSB4PHY_2_GCC_USB4_RX1_CLK, 114 P_SLEEP_CLK, 115 P_UFS_PHY_RX_SYMBOL_0_CLK, 116 P_UFS_PHY_RX_SYMBOL_1_CLK, 117 P_UFS_PHY_TX_SYMBOL_0_CLK, 118 P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 119 P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 120 P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 121 P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK, 122 P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK, 123 P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 124 P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 125 P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 126 P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 127 P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 128 P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 129 }; 130 131 static struct clk_alpha_pll gcc_gpll0 = { 132 .offset = 0x0, 133 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 134 .clkr = { 135 .enable_reg = 0x62040, 136 .enable_mask = BIT(0), 137 .hw.init = &(const struct clk_init_data) { 138 .name = "gcc_gpll0", 139 .parent_data = &(const struct clk_parent_data) { 140 .index = DT_BI_TCXO, 141 }, 142 .num_parents = 1, 143 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 144 }, 145 }, 146 }; 147 148 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 149 { 0x1, 2 }, 150 { } 151 }; 152 153 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 154 .offset = 0x0, 155 .post_div_shift = 10, 156 .post_div_table = post_div_table_gcc_gpll0_out_even, 157 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 158 .width = 4, 159 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 160 .clkr.hw.init = &(const struct clk_init_data) { 161 .name = "gcc_gpll0_out_even", 162 .parent_hws = (const struct clk_hw*[]) { 163 &gcc_gpll0.clkr.hw, 164 }, 165 .num_parents = 1, 166 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 167 }, 168 }; 169 170 static struct clk_alpha_pll gcc_gpll1 = { 171 .offset = 0x1000, 172 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 173 .clkr = { 174 .enable_reg = 0x62040, 175 .enable_mask = BIT(1), 176 .hw.init = &(const struct clk_init_data) { 177 .name = "gcc_gpll1", 178 .parent_data = &(const struct clk_parent_data) { 179 .index = DT_BI_TCXO, 180 }, 181 .num_parents = 1, 182 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 183 }, 184 }, 185 }; 186 187 static struct clk_alpha_pll gcc_gpll14 = { 188 .offset = 0xe000, 189 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 190 .clkr = { 191 .enable_reg = 0x62040, 192 .enable_mask = BIT(14), 193 .hw.init = &(const struct clk_init_data) { 194 .name = "gcc_gpll14", 195 .parent_data = &(const struct clk_parent_data) { 196 .index = DT_BI_TCXO, 197 }, 198 .num_parents = 1, 199 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 200 }, 201 }, 202 }; 203 204 static const struct clk_div_table post_div_table_gcc_gpll14_out_even[] = { 205 { 0x1, 2 }, 206 { } 207 }; 208 209 static struct clk_alpha_pll_postdiv gcc_gpll14_out_even = { 210 .offset = 0xe000, 211 .post_div_shift = 10, 212 .post_div_table = post_div_table_gcc_gpll14_out_even, 213 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll14_out_even), 214 .width = 4, 215 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 216 .clkr.hw.init = &(const struct clk_init_data) { 217 .name = "gcc_gpll14_out_even", 218 .parent_hws = (const struct clk_hw*[]) { 219 &gcc_gpll14.clkr.hw, 220 }, 221 .num_parents = 1, 222 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 223 }, 224 }; 225 226 static struct clk_alpha_pll gcc_gpll4 = { 227 .offset = 0x4000, 228 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 229 .clkr = { 230 .enable_reg = 0x62040, 231 .enable_mask = BIT(4), 232 .hw.init = &(const struct clk_init_data) { 233 .name = "gcc_gpll4", 234 .parent_data = &(const struct clk_parent_data) { 235 .index = DT_BI_TCXO, 236 }, 237 .num_parents = 1, 238 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 239 }, 240 }, 241 }; 242 243 static struct clk_alpha_pll gcc_gpll5 = { 244 .offset = 0x5000, 245 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 246 .clkr = { 247 .enable_reg = 0x62040, 248 .enable_mask = BIT(5), 249 .hw.init = &(const struct clk_init_data) { 250 .name = "gcc_gpll5", 251 .parent_data = &(const struct clk_parent_data) { 252 .index = DT_BI_TCXO, 253 }, 254 .num_parents = 1, 255 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 256 }, 257 }, 258 }; 259 260 static struct clk_alpha_pll gcc_gpll7 = { 261 .offset = 0x7000, 262 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 263 .clkr = { 264 .enable_reg = 0x62040, 265 .enable_mask = BIT(7), 266 .hw.init = &(const struct clk_init_data) { 267 .name = "gcc_gpll7", 268 .parent_data = &(const struct clk_parent_data) { 269 .index = DT_BI_TCXO, 270 }, 271 .num_parents = 1, 272 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 273 }, 274 }, 275 }; 276 277 static struct clk_alpha_pll gcc_gpll8 = { 278 .offset = 0x8000, 279 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 280 .clkr = { 281 .enable_reg = 0x62040, 282 .enable_mask = BIT(8), 283 .hw.init = &(const struct clk_init_data) { 284 .name = "gcc_gpll8", 285 .parent_data = &(const struct clk_parent_data) { 286 .index = DT_BI_TCXO, 287 }, 288 .num_parents = 1, 289 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 290 }, 291 }, 292 }; 293 294 static struct clk_alpha_pll gcc_gpll9 = { 295 .offset = 0x9000, 296 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 297 .clkr = { 298 .enable_reg = 0x62040, 299 .enable_mask = BIT(9), 300 .hw.init = &(const struct clk_init_data) { 301 .name = "gcc_gpll9", 302 .parent_data = &(const struct clk_parent_data) { 303 .index = DT_BI_TCXO, 304 }, 305 .num_parents = 1, 306 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 307 }, 308 }, 309 }; 310 311 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src; 312 static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src; 313 static struct clk_regmap_mux gcc_usb3_tert_phy_pipe_clk_src; 314 315 static struct clk_rcg2 gcc_usb4_1_phy_pll_pipe_clk_src; 316 317 static const struct parent_map gcc_parent_map_0[] = { 318 { P_BI_TCXO, 0 }, 319 { P_GCC_GPLL0_OUT_MAIN, 1 }, 320 { P_GCC_GPLL0_OUT_EVEN, 6 }, 321 }; 322 323 static const struct clk_parent_data gcc_parent_data_0[] = { 324 { .index = DT_BI_TCXO }, 325 { .hw = &gcc_gpll0.clkr.hw }, 326 { .hw = &gcc_gpll0_out_even.clkr.hw }, 327 }; 328 329 static const struct parent_map gcc_parent_map_1[] = { 330 { P_BI_TCXO, 0 }, 331 { P_GCC_GPLL0_OUT_MAIN, 1 }, 332 { P_GCC_GPLL1_OUT_MAIN, 4 }, 333 { P_GCC_GPLL0_OUT_EVEN, 6 }, 334 }; 335 336 static const struct clk_parent_data gcc_parent_data_1[] = { 337 { .index = DT_BI_TCXO }, 338 { .hw = &gcc_gpll0.clkr.hw }, 339 { .hw = &gcc_gpll1.clkr.hw }, 340 { .hw = &gcc_gpll0_out_even.clkr.hw }, 341 }; 342 343 static const struct parent_map gcc_parent_map_2[] = { 344 { P_BI_TCXO, 0 }, 345 { P_SLEEP_CLK, 5 }, 346 }; 347 348 static const struct clk_parent_data gcc_parent_data_2[] = { 349 { .index = DT_BI_TCXO }, 350 { .index = DT_SLEEP_CLK }, 351 }; 352 353 static const struct parent_map gcc_parent_map_3[] = { 354 { P_BI_TCXO, 0 }, 355 { P_GCC_GPLL0_OUT_MAIN, 1 }, 356 { P_GCC_GPLL1_OUT_MAIN, 4 }, 357 { P_GCC_GPLL4_OUT_MAIN, 5 }, 358 { P_GCC_GPLL0_OUT_EVEN, 6 }, 359 }; 360 361 static const struct clk_parent_data gcc_parent_data_3[] = { 362 { .index = DT_BI_TCXO }, 363 { .hw = &gcc_gpll0.clkr.hw }, 364 { .hw = &gcc_gpll1.clkr.hw }, 365 { .hw = &gcc_gpll4.clkr.hw }, 366 { .hw = &gcc_gpll0_out_even.clkr.hw }, 367 }; 368 369 static const struct parent_map gcc_parent_map_4[] = { 370 { P_BI_TCXO, 0 }, 371 { P_GCC_GPLL0_OUT_MAIN, 1 }, 372 { P_SLEEP_CLK, 5 }, 373 { P_GCC_GPLL0_OUT_EVEN, 6 }, 374 }; 375 376 static const struct clk_parent_data gcc_parent_data_4[] = { 377 { .index = DT_BI_TCXO }, 378 { .hw = &gcc_gpll0.clkr.hw }, 379 { .index = DT_SLEEP_CLK }, 380 { .hw = &gcc_gpll0_out_even.clkr.hw }, 381 }; 382 383 static const struct parent_map gcc_parent_map_5[] = { 384 { P_BI_TCXO, 0 }, 385 }; 386 387 static const struct clk_parent_data gcc_parent_data_5[] = { 388 { .index = DT_BI_TCXO }, 389 }; 390 391 static const struct parent_map gcc_parent_map_6[] = { 392 { P_BI_TCXO, 0 }, 393 { P_GCC_GPLL0_OUT_MAIN, 1 }, 394 { P_GCC_GPLL4_OUT_MAIN, 5 }, 395 { P_GCC_GPLL0_OUT_EVEN, 6 }, 396 }; 397 398 static const struct clk_parent_data gcc_parent_data_6[] = { 399 { .index = DT_BI_TCXO }, 400 { .hw = &gcc_gpll0.clkr.hw }, 401 { .hw = &gcc_gpll4.clkr.hw }, 402 { .hw = &gcc_gpll0_out_even.clkr.hw }, 403 }; 404 405 static const struct parent_map gcc_parent_map_7[] = { 406 { P_BI_TCXO, 0 }, 407 { P_GCC_GPLL14_OUT_MAIN, 1 }, 408 { P_GCC_GPLL14_OUT_EVEN, 6 }, 409 }; 410 411 static const struct clk_parent_data gcc_parent_data_7[] = { 412 { .index = DT_BI_TCXO }, 413 { .hw = &gcc_gpll14.clkr.hw }, 414 { .hw = &gcc_gpll14_out_even.clkr.hw }, 415 }; 416 417 static const struct parent_map gcc_parent_map_8[] = { 418 { P_BI_TCXO, 0 }, 419 { P_GCC_GPLL4_OUT_MAIN, 5 }, 420 }; 421 422 static const struct clk_parent_data gcc_parent_data_8[] = { 423 { .index = DT_BI_TCXO }, 424 { .hw = &gcc_gpll4.clkr.hw }, 425 }; 426 427 static const struct parent_map gcc_parent_map_9[] = { 428 { P_BI_TCXO, 0 }, 429 { P_GCC_GPLL0_OUT_MAIN, 1 }, 430 { P_GCC_GPLL8_OUT_MAIN, 2 }, 431 { P_GCC_GPLL0_OUT_EVEN, 6 }, 432 }; 433 434 static const struct clk_parent_data gcc_parent_data_9[] = { 435 { .index = DT_BI_TCXO }, 436 { .hw = &gcc_gpll0.clkr.hw }, 437 { .hw = &gcc_gpll8.clkr.hw }, 438 { .hw = &gcc_gpll0_out_even.clkr.hw }, 439 }; 440 441 static const struct parent_map gcc_parent_map_10[] = { 442 { P_BI_TCXO, 0 }, 443 { P_GCC_GPLL0_OUT_MAIN, 1 }, 444 { P_GCC_GPLL7_OUT_MAIN, 2 }, 445 }; 446 447 static const struct clk_parent_data gcc_parent_data_10[] = { 448 { .index = DT_BI_TCXO }, 449 { .hw = &gcc_gpll0.clkr.hw }, 450 { .hw = &gcc_gpll7.clkr.hw }, 451 }; 452 453 static const struct parent_map gcc_parent_map_11[] = { 454 { P_BI_TCXO, 0 }, 455 { P_GCC_GPLL0_OUT_MAIN, 1 }, 456 { P_GCC_GPLL7_OUT_MAIN, 2 }, 457 { P_GCC_GPLL8_OUT_MAIN, 3 }, 458 { P_SLEEP_CLK, 5 }, 459 }; 460 461 static const struct clk_parent_data gcc_parent_data_11[] = { 462 { .index = DT_BI_TCXO }, 463 { .hw = &gcc_gpll0.clkr.hw }, 464 { .hw = &gcc_gpll7.clkr.hw }, 465 { .hw = &gcc_gpll8.clkr.hw }, 466 { .index = DT_SLEEP_CLK }, 467 }; 468 469 static const struct parent_map gcc_parent_map_17[] = { 470 { P_BI_TCXO, 0 }, 471 { P_GCC_GPLL0_OUT_MAIN, 1 }, 472 { P_GCC_GPLL9_OUT_MAIN, 2 }, 473 { P_GCC_GPLL4_OUT_MAIN, 5 }, 474 { P_GCC_GPLL0_OUT_EVEN, 6 }, 475 }; 476 477 static const struct clk_parent_data gcc_parent_data_17[] = { 478 { .index = DT_BI_TCXO }, 479 { .hw = &gcc_gpll0.clkr.hw }, 480 { .hw = &gcc_gpll9.clkr.hw }, 481 { .hw = &gcc_gpll4.clkr.hw }, 482 { .hw = &gcc_gpll0_out_even.clkr.hw }, 483 }; 484 485 static const struct parent_map gcc_parent_map_18[] = { 486 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 }, 487 { P_BI_TCXO, 2 }, 488 }; 489 490 static const struct clk_parent_data gcc_parent_data_18[] = { 491 { .index = DT_UFS_PHY_RX_SYMBOL_0_CLK }, 492 { .index = DT_BI_TCXO }, 493 }; 494 495 static const struct parent_map gcc_parent_map_19[] = { 496 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 }, 497 { P_BI_TCXO, 2 }, 498 }; 499 500 static const struct clk_parent_data gcc_parent_data_19[] = { 501 { .index = DT_UFS_PHY_RX_SYMBOL_1_CLK }, 502 { .index = DT_BI_TCXO }, 503 }; 504 505 static const struct parent_map gcc_parent_map_20[] = { 506 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 }, 507 { P_BI_TCXO, 2 }, 508 }; 509 510 static const struct clk_parent_data gcc_parent_data_20[] = { 511 { .index = DT_UFS_PHY_TX_SYMBOL_0_CLK }, 512 { .index = DT_BI_TCXO }, 513 }; 514 515 static const struct parent_map gcc_parent_map_21[] = { 516 { P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 0 }, 517 { P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 }, 518 { P_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC, 3 }, 519 }; 520 521 static const struct clk_parent_data gcc_parent_data_21[] = { 522 { .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw }, 523 { .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 524 { .index = DT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC }, 525 }; 526 527 static const struct parent_map gcc_parent_map_22[] = { 528 { P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC, 0 }, 529 { P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 }, 530 { P_GCC_USB4_1_PHY_PLL_PIPE_CLK_SRC, 2 }, 531 { P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, 3 }, 532 }; 533 534 static const struct clk_parent_data gcc_parent_data_22[] = { 535 { .hw = &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw }, 536 { .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 537 { .hw = &gcc_usb4_1_phy_pll_pipe_clk_src.clkr.hw }, 538 { .index = DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC }, 539 }; 540 541 static const struct parent_map gcc_parent_map_23[] = { 542 { P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC, 0 }, 543 { P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 }, 544 { P_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC, 3 }, 545 }; 546 547 static const struct clk_parent_data gcc_parent_data_23[] = { 548 { .hw = &gcc_usb3_tert_phy_pipe_clk_src.clkr.hw }, 549 { .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 550 { .index = DT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC }, 551 }; 552 553 static const struct parent_map gcc_parent_map_24[] = { 554 { P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK, 0 }, 555 { P_BI_TCXO, 2 }, 556 }; 557 558 static const struct clk_parent_data gcc_parent_data_24[] = { 559 { .index = DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK }, 560 { .index = DT_BI_TCXO }, 561 }; 562 563 static const struct parent_map gcc_parent_map_25[] = { 564 { P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK, 0 }, 565 { P_BI_TCXO, 2 }, 566 }; 567 568 static const struct clk_parent_data gcc_parent_data_25[] = { 569 { .index = DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK }, 570 { .index = DT_BI_TCXO }, 571 }; 572 573 static const struct parent_map gcc_parent_map_26[] = { 574 { P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 575 { P_BI_TCXO, 2 }, 576 }; 577 578 static const struct clk_parent_data gcc_parent_data_26[] = { 579 { .index = DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK }, 580 { .index = DT_BI_TCXO }, 581 }; 582 583 static const struct parent_map gcc_parent_map_27[] = { 584 { P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 585 { P_BI_TCXO, 2 }, 586 }; 587 588 static const struct clk_parent_data gcc_parent_data_27[] = { 589 { .index = DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK }, 590 { .index = DT_BI_TCXO }, 591 }; 592 593 static const struct parent_map gcc_parent_map_28[] = { 594 { P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 595 { P_BI_TCXO, 2 }, 596 }; 597 598 static const struct clk_parent_data gcc_parent_data_28[] = { 599 { .index = DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK }, 600 { .index = DT_BI_TCXO }, 601 }; 602 603 static const struct parent_map gcc_parent_map_29[] = { 604 { P_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC, 0 }, 605 { P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 }, 606 }; 607 608 static const struct clk_parent_data gcc_parent_data_29[] = { 609 { .index = DT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC }, 610 { .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 611 }; 612 613 static const struct parent_map gcc_parent_map_30[] = { 614 { P_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC, 0 }, 615 { P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 }, 616 }; 617 618 static const struct clk_parent_data gcc_parent_data_30[] = { 619 { .index = DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC }, 620 { .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 621 }; 622 623 static const struct parent_map gcc_parent_map_31[] = { 624 { P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 }, 625 { P_BI_TCXO, 2 }, 626 }; 627 628 static const struct clk_parent_data gcc_parent_data_31[] = { 629 { .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK }, 630 { .index = DT_BI_TCXO }, 631 }; 632 633 static const struct parent_map gcc_parent_map_32[] = { 634 { P_BI_TCXO, 0 }, 635 { P_GCC_GPLL0_OUT_MAIN, 1 }, 636 { P_GCC_GPLL7_OUT_MAIN, 2 }, 637 { P_SLEEP_CLK, 5 }, 638 }; 639 640 static const struct clk_parent_data gcc_parent_data_32[] = { 641 { .index = DT_BI_TCXO }, 642 { .hw = &gcc_gpll0.clkr.hw }, 643 { .hw = &gcc_gpll7.clkr.hw }, 644 { .index = DT_SLEEP_CLK }, 645 }; 646 647 static const struct parent_map gcc_parent_map_33[] = { 648 { P_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 }, 649 { P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 1 }, 650 }; 651 652 static const struct clk_parent_data gcc_parent_data_33[] = { 653 { .index = DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC }, 654 { .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK }, 655 }; 656 657 static const struct parent_map gcc_parent_map_34[] = { 658 { P_QUSB4PHY_0_GCC_USB4_RX0_CLK, 0 }, 659 { P_BI_TCXO, 2 }, 660 }; 661 662 static const struct clk_parent_data gcc_parent_data_34[] = { 663 { .index = DT_QUSB4PHY_0_GCC_USB4_RX0_CLK }, 664 { .index = DT_BI_TCXO }, 665 }; 666 667 static const struct parent_map gcc_parent_map_35[] = { 668 { P_QUSB4PHY_0_GCC_USB4_RX1_CLK, 0 }, 669 { P_BI_TCXO, 2 }, 670 }; 671 672 static const struct clk_parent_data gcc_parent_data_35[] = { 673 { .index = DT_QUSB4PHY_0_GCC_USB4_RX1_CLK }, 674 { .index = DT_BI_TCXO }, 675 }; 676 677 static const struct parent_map gcc_parent_map_36[] = { 678 { P_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC, 0 }, 679 { P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 }, 680 }; 681 682 static const struct clk_parent_data gcc_parent_data_36[] = { 683 { .index = DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC }, 684 { .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK }, 685 }; 686 687 static const struct parent_map gcc_parent_map_37[] = { 688 { P_GCC_USB4_1_PHY_DP0_GMUX_2_CLK_SRC, 0 }, 689 { P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 }, 690 }; 691 692 static const struct clk_parent_data gcc_parent_data_37[] = { 693 { .index = DT_GCC_USB4_1_PHY_DP0_GMUX_2_CLK_SRC }, 694 { .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 695 }; 696 697 static const struct parent_map gcc_parent_map_38[] = { 698 { P_GCC_USB4_1_PHY_DP1_GMUX_2_CLK_SRC, 0 }, 699 { P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 }, 700 }; 701 702 static const struct clk_parent_data gcc_parent_data_38[] = { 703 { .index = DT_GCC_USB4_1_PHY_DP1_GMUX_2_CLK_SRC }, 704 { .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 705 }; 706 707 static const struct parent_map gcc_parent_map_39[] = { 708 { P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 }, 709 { P_BI_TCXO, 2 }, 710 }; 711 712 static const struct clk_parent_data gcc_parent_data_39[] = { 713 { .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK }, 714 { .index = DT_BI_TCXO }, 715 }; 716 717 static const struct parent_map gcc_parent_map_40[] = { 718 { P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 }, 719 { P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 1 }, 720 }; 721 722 static const struct clk_parent_data gcc_parent_data_40[] = { 723 { .index = DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC }, 724 { .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK }, 725 }; 726 727 static const struct parent_map gcc_parent_map_41[] = { 728 { P_BI_TCXO, 0 }, 729 { P_GCC_GPLL0_OUT_MAIN, 1 }, 730 { P_GCC_GPLL5_OUT_MAIN, 3 }, 731 { P_GCC_GPLL0_OUT_EVEN, 6 }, 732 }; 733 734 static const struct clk_parent_data gcc_parent_data_41[] = { 735 { .index = DT_BI_TCXO }, 736 { .hw = &gcc_gpll0.clkr.hw }, 737 { .hw = &gcc_gpll5.clkr.hw }, 738 { .hw = &gcc_gpll0_out_even.clkr.hw }, 739 }; 740 741 static const struct parent_map gcc_parent_map_42[] = { 742 { P_QUSB4PHY_1_GCC_USB4_RX0_CLK, 0 }, 743 { P_BI_TCXO, 2 }, 744 }; 745 746 static const struct clk_parent_data gcc_parent_data_42[] = { 747 { .index = DT_QUSB4PHY_1_GCC_USB4_RX0_CLK }, 748 { .index = DT_BI_TCXO }, 749 }; 750 751 static const struct parent_map gcc_parent_map_43[] = { 752 { P_QUSB4PHY_1_GCC_USB4_RX1_CLK, 0 }, 753 { P_BI_TCXO, 2 }, 754 }; 755 756 static const struct clk_parent_data gcc_parent_data_43[] = { 757 { .index = DT_QUSB4PHY_1_GCC_USB4_RX1_CLK }, 758 { .index = DT_BI_TCXO }, 759 }; 760 761 static const struct parent_map gcc_parent_map_44[] = { 762 { P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 0 }, 763 { P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 }, 764 }; 765 766 static const struct clk_parent_data gcc_parent_data_44[] = { 767 { .index = DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC }, 768 { .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK }, 769 }; 770 771 static const struct parent_map gcc_parent_map_45[] = { 772 { P_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC, 0 }, 773 { P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 }, 774 }; 775 776 static const struct clk_parent_data gcc_parent_data_45[] = { 777 { .index = DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC }, 778 { .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 779 }; 780 781 static const struct parent_map gcc_parent_map_46[] = { 782 { P_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC, 0 }, 783 { P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 }, 784 }; 785 786 static const struct clk_parent_data gcc_parent_data_46[] = { 787 { .index = DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC }, 788 { .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 789 }; 790 791 static const struct parent_map gcc_parent_map_47[] = { 792 { P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 }, 793 { P_BI_TCXO, 2 }, 794 }; 795 796 static const struct clk_parent_data gcc_parent_data_47[] = { 797 { .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK }, 798 { .index = DT_BI_TCXO }, 799 }; 800 801 static const struct parent_map gcc_parent_map_48[] = { 802 { P_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 }, 803 { P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 1 }, 804 }; 805 806 static const struct clk_parent_data gcc_parent_data_48[] = { 807 { .index = DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC }, 808 { .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK }, 809 }; 810 811 static const struct parent_map gcc_parent_map_49[] = { 812 { P_QUSB4PHY_2_GCC_USB4_RX0_CLK, 0 }, 813 { P_BI_TCXO, 2 }, 814 }; 815 816 static const struct clk_parent_data gcc_parent_data_49[] = { 817 { .index = DT_QUSB4PHY_2_GCC_USB4_RX0_CLK }, 818 { .index = DT_BI_TCXO }, 819 }; 820 821 static const struct parent_map gcc_parent_map_50[] = { 822 { P_QUSB4PHY_2_GCC_USB4_RX1_CLK, 0 }, 823 { P_BI_TCXO, 2 }, 824 }; 825 826 static const struct clk_parent_data gcc_parent_data_50[] = { 827 { .index = DT_QUSB4PHY_2_GCC_USB4_RX1_CLK }, 828 { .index = DT_BI_TCXO }, 829 }; 830 831 static const struct parent_map gcc_parent_map_51[] = { 832 { P_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC, 0 }, 833 { P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 }, 834 }; 835 836 static const struct clk_parent_data gcc_parent_data_51[] = { 837 { .index = DT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC }, 838 { .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK }, 839 }; 840 841 static struct clk_regmap_phy_mux gcc_pcie_3a_pipe_clk_src = { 842 .reg = 0xdc088, 843 .clkr = { 844 .hw.init = &(const struct clk_init_data) { 845 .name = "gcc_pcie_3a_pipe_clk_src", 846 .parent_data = &(const struct clk_parent_data){ 847 .index = DT_PCIE_3A_PIPE_CLK, 848 }, 849 .num_parents = 1, 850 .ops = &clk_regmap_phy_mux_ops, 851 }, 852 }, 853 }; 854 855 static struct clk_regmap_phy_mux gcc_pcie_3b_pipe_clk_src = { 856 .reg = 0x941b4, 857 .clkr = { 858 .hw.init = &(const struct clk_init_data) { 859 .name = "gcc_pcie_3b_pipe_clk_src", 860 .parent_data = &(const struct clk_parent_data){ 861 .index = DT_PCIE_3B_PIPE_CLK, 862 }, 863 .num_parents = 1, 864 .ops = &clk_regmap_phy_mux_ops, 865 }, 866 }, 867 }; 868 869 static struct clk_regmap_phy_mux gcc_pcie_4_pipe_clk_src = { 870 .reg = 0x881a4, 871 .clkr = { 872 .hw.init = &(const struct clk_init_data) { 873 .name = "gcc_pcie_4_pipe_clk_src", 874 .parent_data = &(const struct clk_parent_data){ 875 .index = DT_PCIE_4_PIPE_CLK, 876 }, 877 .num_parents = 1, 878 .ops = &clk_regmap_phy_mux_ops, 879 }, 880 }, 881 }; 882 883 static struct clk_regmap_phy_mux gcc_pcie_5_pipe_clk_src = { 884 .reg = 0xc309c, 885 .clkr = { 886 .hw.init = &(const struct clk_init_data) { 887 .name = "gcc_pcie_5_pipe_clk_src", 888 .parent_data = &(const struct clk_parent_data){ 889 .index = DT_PCIE_5_PIPE_CLK, 890 }, 891 .num_parents = 1, 892 .ops = &clk_regmap_phy_mux_ops, 893 }, 894 }, 895 }; 896 897 static struct clk_regmap_phy_mux gcc_pcie_6_pipe_clk_src = { 898 .reg = 0x8a1a4, 899 .clkr = { 900 .hw.init = &(const struct clk_init_data) { 901 .name = "gcc_pcie_6_pipe_clk_src", 902 .parent_data = &(const struct clk_parent_data){ 903 .index = DT_PCIE_6_PIPE_CLK, 904 }, 905 .num_parents = 1, 906 .ops = &clk_regmap_phy_mux_ops, 907 }, 908 }, 909 }; 910 911 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = { 912 .reg = 0x7706c, 913 .shift = 0, 914 .width = 2, 915 .parent_map = gcc_parent_map_18, 916 .clkr = { 917 .hw.init = &(const struct clk_init_data) { 918 .name = "gcc_ufs_phy_rx_symbol_0_clk_src", 919 .parent_data = gcc_parent_data_18, 920 .num_parents = ARRAY_SIZE(gcc_parent_data_18), 921 .ops = &clk_regmap_mux_closest_ops, 922 }, 923 }, 924 }; 925 926 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = { 927 .reg = 0x770f0, 928 .shift = 0, 929 .width = 2, 930 .parent_map = gcc_parent_map_19, 931 .clkr = { 932 .hw.init = &(const struct clk_init_data) { 933 .name = "gcc_ufs_phy_rx_symbol_1_clk_src", 934 .parent_data = gcc_parent_data_19, 935 .num_parents = ARRAY_SIZE(gcc_parent_data_19), 936 .ops = &clk_regmap_mux_closest_ops, 937 }, 938 }, 939 }; 940 941 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = { 942 .reg = 0x7705c, 943 .shift = 0, 944 .width = 2, 945 .parent_map = gcc_parent_map_20, 946 .clkr = { 947 .hw.init = &(const struct clk_init_data) { 948 .name = "gcc_ufs_phy_tx_symbol_0_clk_src", 949 .parent_data = gcc_parent_data_20, 950 .num_parents = ARRAY_SIZE(gcc_parent_data_20), 951 .ops = &clk_regmap_mux_closest_ops, 952 }, 953 }, 954 }; 955 956 static struct clk_regmap_mux gcc_usb34_prim_phy_pipe_clk_src = { 957 .reg = 0x2b0b8, 958 .shift = 0, 959 .width = 2, 960 .parent_map = gcc_parent_map_21, 961 .clkr = { 962 .hw.init = &(const struct clk_init_data) { 963 .name = "gcc_usb34_prim_phy_pipe_clk_src", 964 .parent_data = gcc_parent_data_21, 965 .num_parents = ARRAY_SIZE(gcc_parent_data_21), 966 .ops = &clk_regmap_mux_closest_ops, 967 }, 968 }, 969 }; 970 971 static struct clk_regmap_mux gcc_usb34_sec_phy_pipe_clk_src = { 972 .reg = 0x2d0c4, 973 .shift = 0, 974 .width = 2, 975 .parent_map = gcc_parent_map_22, 976 .clkr = { 977 .hw.init = &(const struct clk_init_data) { 978 .name = "gcc_usb34_sec_phy_pipe_clk_src", 979 .parent_data = gcc_parent_data_22, 980 .num_parents = ARRAY_SIZE(gcc_parent_data_22), 981 .ops = &clk_regmap_mux_closest_ops, 982 }, 983 }, 984 }; 985 986 static struct clk_regmap_mux gcc_usb34_tert_phy_pipe_clk_src = { 987 .reg = 0xe00bc, 988 .shift = 0, 989 .width = 2, 990 .parent_map = gcc_parent_map_23, 991 .clkr = { 992 .hw.init = &(const struct clk_init_data) { 993 .name = "gcc_usb34_tert_phy_pipe_clk_src", 994 .parent_data = gcc_parent_data_23, 995 .num_parents = ARRAY_SIZE(gcc_parent_data_23), 996 .ops = &clk_regmap_mux_closest_ops, 997 }, 998 }, 999 }; 1000 1001 static struct clk_regmap_mux gcc_usb3_mp_phy_pipe_0_clk_src = { 1002 .reg = 0x9a07c, 1003 .shift = 0, 1004 .width = 2, 1005 .parent_map = gcc_parent_map_24, 1006 .clkr = { 1007 .hw.init = &(const struct clk_init_data) { 1008 .name = "gcc_usb3_mp_phy_pipe_0_clk_src", 1009 .parent_data = gcc_parent_data_24, 1010 .num_parents = ARRAY_SIZE(gcc_parent_data_24), 1011 .ops = &clk_regmap_mux_closest_ops, 1012 }, 1013 }, 1014 }; 1015 1016 static struct clk_regmap_mux gcc_usb3_mp_phy_pipe_1_clk_src = { 1017 .reg = 0x9a084, 1018 .shift = 0, 1019 .width = 2, 1020 .parent_map = gcc_parent_map_25, 1021 .clkr = { 1022 .hw.init = &(const struct clk_init_data) { 1023 .name = "gcc_usb3_mp_phy_pipe_1_clk_src", 1024 .parent_data = gcc_parent_data_25, 1025 .num_parents = ARRAY_SIZE(gcc_parent_data_25), 1026 .ops = &clk_regmap_mux_closest_ops, 1027 }, 1028 }, 1029 }; 1030 1031 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 1032 .reg = 0x3f08c, 1033 .shift = 0, 1034 .width = 2, 1035 .parent_map = gcc_parent_map_26, 1036 .clkr = { 1037 .hw.init = &(const struct clk_init_data) { 1038 .name = "gcc_usb3_prim_phy_pipe_clk_src", 1039 .parent_data = gcc_parent_data_26, 1040 .num_parents = ARRAY_SIZE(gcc_parent_data_26), 1041 .ops = &clk_regmap_mux_closest_ops, 1042 }, 1043 }, 1044 }; 1045 1046 static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = { 1047 .reg = 0xe207c, 1048 .shift = 0, 1049 .width = 2, 1050 .parent_map = gcc_parent_map_27, 1051 .clkr = { 1052 .hw.init = &(const struct clk_init_data) { 1053 .name = "gcc_usb3_sec_phy_pipe_clk_src", 1054 .parent_data = gcc_parent_data_27, 1055 .num_parents = ARRAY_SIZE(gcc_parent_data_27), 1056 .ops = &clk_regmap_mux_closest_ops, 1057 }, 1058 }, 1059 }; 1060 1061 static struct clk_regmap_mux gcc_usb3_tert_phy_pipe_clk_src = { 1062 .reg = 0xe107c, 1063 .shift = 0, 1064 .width = 2, 1065 .parent_map = gcc_parent_map_28, 1066 .clkr = { 1067 .hw.init = &(const struct clk_init_data) { 1068 .name = "gcc_usb3_tert_phy_pipe_clk_src", 1069 .parent_data = gcc_parent_data_28, 1070 .num_parents = ARRAY_SIZE(gcc_parent_data_28), 1071 .ops = &clk_regmap_mux_closest_ops, 1072 }, 1073 }, 1074 }; 1075 1076 static struct clk_regmap_mux gcc_usb4_0_phy_dp0_clk_src = { 1077 .reg = 0x2b080, 1078 .shift = 0, 1079 .width = 2, 1080 .parent_map = gcc_parent_map_29, 1081 .clkr = { 1082 .hw.init = &(const struct clk_init_data) { 1083 .name = "gcc_usb4_0_phy_dp0_clk_src", 1084 .parent_data = gcc_parent_data_29, 1085 .num_parents = ARRAY_SIZE(gcc_parent_data_29), 1086 .ops = &clk_regmap_mux_closest_ops, 1087 }, 1088 }, 1089 }; 1090 1091 static struct clk_regmap_mux gcc_usb4_0_phy_dp1_clk_src = { 1092 .reg = 0x2b134, 1093 .shift = 0, 1094 .width = 2, 1095 .parent_map = gcc_parent_map_30, 1096 .clkr = { 1097 .hw.init = &(const struct clk_init_data) { 1098 .name = "gcc_usb4_0_phy_dp1_clk_src", 1099 .parent_data = gcc_parent_data_30, 1100 .num_parents = ARRAY_SIZE(gcc_parent_data_30), 1101 .ops = &clk_regmap_mux_closest_ops, 1102 }, 1103 }, 1104 }; 1105 1106 static struct clk_regmap_mux gcc_usb4_0_phy_p2rr2p_pipe_clk_src = { 1107 .reg = 0x2b0f0, 1108 .shift = 0, 1109 .width = 2, 1110 .parent_map = gcc_parent_map_31, 1111 .clkr = { 1112 .hw.init = &(const struct clk_init_data) { 1113 .name = "gcc_usb4_0_phy_p2rr2p_pipe_clk_src", 1114 .parent_data = gcc_parent_data_31, 1115 .num_parents = ARRAY_SIZE(gcc_parent_data_31), 1116 .ops = &clk_regmap_mux_closest_ops, 1117 }, 1118 }, 1119 }; 1120 1121 static struct clk_regmap_mux gcc_usb4_0_phy_pcie_pipe_mux_clk_src = { 1122 .reg = 0x2b120, 1123 .shift = 0, 1124 .width = 1, 1125 .parent_map = gcc_parent_map_33, 1126 .clkr = { 1127 .hw.init = &(const struct clk_init_data) { 1128 .name = "gcc_usb4_0_phy_pcie_pipe_mux_clk_src", 1129 .parent_data = gcc_parent_data_33, 1130 .num_parents = ARRAY_SIZE(gcc_parent_data_33), 1131 .ops = &clk_regmap_mux_closest_ops, 1132 }, 1133 }, 1134 }; 1135 1136 static struct clk_regmap_mux gcc_usb4_0_phy_rx0_clk_src = { 1137 .reg = 0x2b0c0, 1138 .shift = 0, 1139 .width = 2, 1140 .parent_map = gcc_parent_map_34, 1141 .clkr = { 1142 .hw.init = &(const struct clk_init_data) { 1143 .name = "gcc_usb4_0_phy_rx0_clk_src", 1144 .parent_data = gcc_parent_data_34, 1145 .num_parents = ARRAY_SIZE(gcc_parent_data_34), 1146 .ops = &clk_regmap_mux_closest_ops, 1147 }, 1148 }, 1149 }; 1150 1151 static struct clk_regmap_mux gcc_usb4_0_phy_rx1_clk_src = { 1152 .reg = 0x2b0d4, 1153 .shift = 0, 1154 .width = 2, 1155 .parent_map = gcc_parent_map_35, 1156 .clkr = { 1157 .hw.init = &(const struct clk_init_data) { 1158 .name = "gcc_usb4_0_phy_rx1_clk_src", 1159 .parent_data = gcc_parent_data_35, 1160 .num_parents = ARRAY_SIZE(gcc_parent_data_35), 1161 .ops = &clk_regmap_mux_closest_ops, 1162 }, 1163 }, 1164 }; 1165 1166 static struct clk_regmap_mux gcc_usb4_0_phy_sys_clk_src = { 1167 .reg = 0x2b100, 1168 .shift = 0, 1169 .width = 2, 1170 .parent_map = gcc_parent_map_36, 1171 .clkr = { 1172 .hw.init = &(const struct clk_init_data) { 1173 .name = "gcc_usb4_0_phy_sys_clk_src", 1174 .parent_data = gcc_parent_data_36, 1175 .num_parents = ARRAY_SIZE(gcc_parent_data_36), 1176 .ops = &clk_regmap_mux_closest_ops, 1177 }, 1178 }, 1179 }; 1180 1181 static struct clk_regmap_mux gcc_usb4_1_phy_dp0_clk_src = { 1182 .reg = 0x2d08c, 1183 .shift = 0, 1184 .width = 2, 1185 .parent_map = gcc_parent_map_37, 1186 .clkr = { 1187 .hw.init = &(const struct clk_init_data) { 1188 .name = "gcc_usb4_1_phy_dp0_clk_src", 1189 .parent_data = gcc_parent_data_37, 1190 .num_parents = ARRAY_SIZE(gcc_parent_data_37), 1191 .ops = &clk_regmap_mux_closest_ops, 1192 }, 1193 }, 1194 }; 1195 1196 static struct clk_regmap_mux gcc_usb4_1_phy_dp1_clk_src = { 1197 .reg = 0x2d154, 1198 .shift = 0, 1199 .width = 2, 1200 .parent_map = gcc_parent_map_38, 1201 .clkr = { 1202 .hw.init = &(const struct clk_init_data) { 1203 .name = "gcc_usb4_1_phy_dp1_clk_src", 1204 .parent_data = gcc_parent_data_38, 1205 .num_parents = ARRAY_SIZE(gcc_parent_data_38), 1206 .ops = &clk_regmap_mux_closest_ops, 1207 }, 1208 }, 1209 }; 1210 1211 static struct clk_regmap_mux gcc_usb4_1_phy_p2rr2p_pipe_clk_src = { 1212 .reg = 0x2d114, 1213 .shift = 0, 1214 .width = 2, 1215 .parent_map = gcc_parent_map_39, 1216 .clkr = { 1217 .hw.init = &(const struct clk_init_data) { 1218 .name = "gcc_usb4_1_phy_p2rr2p_pipe_clk_src", 1219 .parent_data = gcc_parent_data_39, 1220 .num_parents = ARRAY_SIZE(gcc_parent_data_39), 1221 .ops = &clk_regmap_mux_closest_ops, 1222 }, 1223 }, 1224 }; 1225 1226 static struct clk_regmap_mux gcc_usb4_1_phy_pcie_pipe_mux_clk_src = { 1227 .reg = 0x2d140, 1228 .shift = 0, 1229 .width = 1, 1230 .parent_map = gcc_parent_map_40, 1231 .clkr = { 1232 .hw.init = &(const struct clk_init_data) { 1233 .name = "gcc_usb4_1_phy_pcie_pipe_mux_clk_src", 1234 .parent_data = gcc_parent_data_40, 1235 .num_parents = ARRAY_SIZE(gcc_parent_data_40), 1236 .ops = &clk_regmap_mux_closest_ops, 1237 }, 1238 }, 1239 }; 1240 1241 static struct clk_regmap_mux gcc_usb4_1_phy_rx0_clk_src = { 1242 .reg = 0x2d0e4, 1243 .shift = 0, 1244 .width = 2, 1245 .parent_map = gcc_parent_map_42, 1246 .clkr = { 1247 .hw.init = &(const struct clk_init_data) { 1248 .name = "gcc_usb4_1_phy_rx0_clk_src", 1249 .parent_data = gcc_parent_data_42, 1250 .num_parents = ARRAY_SIZE(gcc_parent_data_42), 1251 .ops = &clk_regmap_mux_closest_ops, 1252 }, 1253 }, 1254 }; 1255 1256 static struct clk_regmap_mux gcc_usb4_1_phy_rx1_clk_src = { 1257 .reg = 0x2d0f8, 1258 .shift = 0, 1259 .width = 2, 1260 .parent_map = gcc_parent_map_43, 1261 .clkr = { 1262 .hw.init = &(const struct clk_init_data) { 1263 .name = "gcc_usb4_1_phy_rx1_clk_src", 1264 .parent_data = gcc_parent_data_43, 1265 .num_parents = ARRAY_SIZE(gcc_parent_data_43), 1266 .ops = &clk_regmap_mux_closest_ops, 1267 }, 1268 }, 1269 }; 1270 1271 static struct clk_regmap_mux gcc_usb4_1_phy_sys_clk_src = { 1272 .reg = 0x2d124, 1273 .shift = 0, 1274 .width = 2, 1275 .parent_map = gcc_parent_map_44, 1276 .clkr = { 1277 .hw.init = &(const struct clk_init_data) { 1278 .name = "gcc_usb4_1_phy_sys_clk_src", 1279 .parent_data = gcc_parent_data_44, 1280 .num_parents = ARRAY_SIZE(gcc_parent_data_44), 1281 .ops = &clk_regmap_mux_closest_ops, 1282 }, 1283 }, 1284 }; 1285 1286 static struct clk_regmap_mux gcc_usb4_2_phy_dp0_clk_src = { 1287 .reg = 0xe0084, 1288 .shift = 0, 1289 .width = 2, 1290 .parent_map = gcc_parent_map_45, 1291 .clkr = { 1292 .hw.init = &(const struct clk_init_data) { 1293 .name = "gcc_usb4_2_phy_dp0_clk_src", 1294 .parent_data = gcc_parent_data_45, 1295 .num_parents = ARRAY_SIZE(gcc_parent_data_45), 1296 .ops = &clk_regmap_mux_closest_ops, 1297 }, 1298 }, 1299 }; 1300 1301 static struct clk_regmap_mux gcc_usb4_2_phy_dp1_clk_src = { 1302 .reg = 0xe013c, 1303 .shift = 0, 1304 .width = 2, 1305 .parent_map = gcc_parent_map_46, 1306 .clkr = { 1307 .hw.init = &(const struct clk_init_data) { 1308 .name = "gcc_usb4_2_phy_dp1_clk_src", 1309 .parent_data = gcc_parent_data_46, 1310 .num_parents = ARRAY_SIZE(gcc_parent_data_46), 1311 .ops = &clk_regmap_mux_closest_ops, 1312 }, 1313 }, 1314 }; 1315 1316 static struct clk_regmap_mux gcc_usb4_2_phy_p2rr2p_pipe_clk_src = { 1317 .reg = 0xe00f4, 1318 .shift = 0, 1319 .width = 2, 1320 .parent_map = gcc_parent_map_47, 1321 .clkr = { 1322 .hw.init = &(const struct clk_init_data) { 1323 .name = "gcc_usb4_2_phy_p2rr2p_pipe_clk_src", 1324 .parent_data = gcc_parent_data_47, 1325 .num_parents = ARRAY_SIZE(gcc_parent_data_47), 1326 .ops = &clk_regmap_mux_closest_ops, 1327 }, 1328 }, 1329 }; 1330 1331 static struct clk_regmap_mux gcc_usb4_2_phy_pcie_pipe_mux_clk_src = { 1332 .reg = 0xe0124, 1333 .shift = 0, 1334 .width = 1, 1335 .parent_map = gcc_parent_map_48, 1336 .clkr = { 1337 .hw.init = &(const struct clk_init_data) { 1338 .name = "gcc_usb4_2_phy_pcie_pipe_mux_clk_src", 1339 .parent_data = gcc_parent_data_48, 1340 .num_parents = ARRAY_SIZE(gcc_parent_data_48), 1341 .ops = &clk_regmap_mux_closest_ops, 1342 }, 1343 }, 1344 }; 1345 1346 static struct clk_regmap_mux gcc_usb4_2_phy_rx0_clk_src = { 1347 .reg = 0xe00c4, 1348 .shift = 0, 1349 .width = 2, 1350 .parent_map = gcc_parent_map_49, 1351 .clkr = { 1352 .hw.init = &(const struct clk_init_data) { 1353 .name = "gcc_usb4_2_phy_rx0_clk_src", 1354 .parent_data = gcc_parent_data_49, 1355 .num_parents = ARRAY_SIZE(gcc_parent_data_49), 1356 .ops = &clk_regmap_mux_closest_ops, 1357 }, 1358 }, 1359 }; 1360 1361 static struct clk_regmap_mux gcc_usb4_2_phy_rx1_clk_src = { 1362 .reg = 0xe00d8, 1363 .shift = 0, 1364 .width = 2, 1365 .parent_map = gcc_parent_map_50, 1366 .clkr = { 1367 .hw.init = &(const struct clk_init_data) { 1368 .name = "gcc_usb4_2_phy_rx1_clk_src", 1369 .parent_data = gcc_parent_data_50, 1370 .num_parents = ARRAY_SIZE(gcc_parent_data_50), 1371 .ops = &clk_regmap_mux_closest_ops, 1372 }, 1373 }, 1374 }; 1375 1376 static struct clk_regmap_mux gcc_usb4_2_phy_sys_clk_src = { 1377 .reg = 0xe0104, 1378 .shift = 0, 1379 .width = 2, 1380 .parent_map = gcc_parent_map_51, 1381 .clkr = { 1382 .hw.init = &(const struct clk_init_data) { 1383 .name = "gcc_usb4_2_phy_sys_clk_src", 1384 .parent_data = gcc_parent_data_51, 1385 .num_parents = ARRAY_SIZE(gcc_parent_data_51), 1386 .ops = &clk_regmap_mux_closest_ops, 1387 }, 1388 }, 1389 }; 1390 1391 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 1392 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 1393 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 1394 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1395 { } 1396 }; 1397 1398 static struct clk_rcg2 gcc_gp1_clk_src = { 1399 .cmd_rcgr = 0x64004, 1400 .mnd_width = 16, 1401 .hid_width = 5, 1402 .parent_map = gcc_parent_map_4, 1403 .freq_tbl = ftbl_gcc_gp1_clk_src, 1404 .clkr.hw.init = &(const struct clk_init_data) { 1405 .name = "gcc_gp1_clk_src", 1406 .parent_data = gcc_parent_data_4, 1407 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1408 .flags = CLK_SET_RATE_PARENT, 1409 .ops = &clk_rcg2_shared_no_init_park_ops, 1410 }, 1411 }; 1412 1413 static struct clk_rcg2 gcc_gp2_clk_src = { 1414 .cmd_rcgr = 0x92004, 1415 .mnd_width = 16, 1416 .hid_width = 5, 1417 .parent_map = gcc_parent_map_4, 1418 .freq_tbl = ftbl_gcc_gp1_clk_src, 1419 .clkr.hw.init = &(const struct clk_init_data) { 1420 .name = "gcc_gp2_clk_src", 1421 .parent_data = gcc_parent_data_4, 1422 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1423 .flags = CLK_SET_RATE_PARENT, 1424 .ops = &clk_rcg2_shared_no_init_park_ops, 1425 }, 1426 }; 1427 1428 static struct clk_rcg2 gcc_gp3_clk_src = { 1429 .cmd_rcgr = 0x93004, 1430 .mnd_width = 16, 1431 .hid_width = 5, 1432 .parent_map = gcc_parent_map_4, 1433 .freq_tbl = ftbl_gcc_gp1_clk_src, 1434 .clkr.hw.init = &(const struct clk_init_data) { 1435 .name = "gcc_gp3_clk_src", 1436 .parent_data = gcc_parent_data_4, 1437 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1438 .flags = CLK_SET_RATE_PARENT, 1439 .ops = &clk_rcg2_shared_no_init_park_ops, 1440 }, 1441 }; 1442 1443 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 1444 F(19200000, P_BI_TCXO, 1, 0, 0), 1445 { } 1446 }; 1447 1448 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 1449 .cmd_rcgr = 0xc8168, 1450 .mnd_width = 16, 1451 .hid_width = 5, 1452 .parent_map = gcc_parent_map_2, 1453 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1454 .clkr.hw.init = &(const struct clk_init_data) { 1455 .name = "gcc_pcie_0_aux_clk_src", 1456 .parent_data = gcc_parent_data_2, 1457 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1458 .flags = CLK_SET_RATE_PARENT, 1459 .ops = &clk_rcg2_shared_no_init_park_ops, 1460 }, 1461 }; 1462 1463 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 1464 F(19200000, P_BI_TCXO, 1, 0, 0), 1465 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1466 { } 1467 }; 1468 1469 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 1470 .cmd_rcgr = 0xc803c, 1471 .mnd_width = 0, 1472 .hid_width = 5, 1473 .parent_map = gcc_parent_map_0, 1474 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1475 .clkr.hw.init = &(const struct clk_init_data) { 1476 .name = "gcc_pcie_0_phy_rchng_clk_src", 1477 .parent_data = gcc_parent_data_0, 1478 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1479 .flags = CLK_SET_RATE_PARENT, 1480 .ops = &clk_rcg2_shared_no_init_park_ops, 1481 }, 1482 }; 1483 1484 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 1485 .cmd_rcgr = 0x2e168, 1486 .mnd_width = 16, 1487 .hid_width = 5, 1488 .parent_map = gcc_parent_map_2, 1489 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1490 .clkr.hw.init = &(const struct clk_init_data) { 1491 .name = "gcc_pcie_1_aux_clk_src", 1492 .parent_data = gcc_parent_data_2, 1493 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1494 .flags = CLK_SET_RATE_PARENT, 1495 .ops = &clk_rcg2_shared_no_init_park_ops, 1496 }, 1497 }; 1498 1499 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { 1500 .cmd_rcgr = 0x2e03c, 1501 .mnd_width = 0, 1502 .hid_width = 5, 1503 .parent_map = gcc_parent_map_0, 1504 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1505 .clkr.hw.init = &(const struct clk_init_data) { 1506 .name = "gcc_pcie_1_phy_rchng_clk_src", 1507 .parent_data = gcc_parent_data_0, 1508 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1509 .flags = CLK_SET_RATE_PARENT, 1510 .ops = &clk_rcg2_shared_no_init_park_ops, 1511 }, 1512 }; 1513 1514 static struct clk_rcg2 gcc_pcie_2_aux_clk_src = { 1515 .cmd_rcgr = 0xc0168, 1516 .mnd_width = 16, 1517 .hid_width = 5, 1518 .parent_map = gcc_parent_map_2, 1519 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1520 .clkr.hw.init = &(const struct clk_init_data) { 1521 .name = "gcc_pcie_2_aux_clk_src", 1522 .parent_data = gcc_parent_data_2, 1523 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1524 .flags = CLK_SET_RATE_PARENT, 1525 .ops = &clk_rcg2_shared_no_init_park_ops, 1526 }, 1527 }; 1528 1529 static struct clk_rcg2 gcc_pcie_2_phy_rchng_clk_src = { 1530 .cmd_rcgr = 0xc003c, 1531 .mnd_width = 0, 1532 .hid_width = 5, 1533 .parent_map = gcc_parent_map_0, 1534 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1535 .clkr.hw.init = &(const struct clk_init_data) { 1536 .name = "gcc_pcie_2_phy_rchng_clk_src", 1537 .parent_data = gcc_parent_data_0, 1538 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1539 .flags = CLK_SET_RATE_PARENT, 1540 .ops = &clk_rcg2_shared_no_init_park_ops, 1541 }, 1542 }; 1543 1544 static struct clk_rcg2 gcc_pcie_3a_aux_clk_src = { 1545 .cmd_rcgr = 0xdc08c, 1546 .mnd_width = 16, 1547 .hid_width = 5, 1548 .parent_map = gcc_parent_map_2, 1549 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1550 .clkr.hw.init = &(const struct clk_init_data) { 1551 .name = "gcc_pcie_3a_aux_clk_src", 1552 .parent_data = gcc_parent_data_2, 1553 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1554 .flags = CLK_SET_RATE_PARENT, 1555 .ops = &clk_rcg2_shared_no_init_park_ops, 1556 }, 1557 }; 1558 1559 static struct clk_rcg2 gcc_pcie_3a_phy_rchng_clk_src = { 1560 .cmd_rcgr = 0xdc070, 1561 .mnd_width = 0, 1562 .hid_width = 5, 1563 .parent_map = gcc_parent_map_0, 1564 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1565 .clkr.hw.init = &(const struct clk_init_data) { 1566 .name = "gcc_pcie_3a_phy_rchng_clk_src", 1567 .parent_data = gcc_parent_data_0, 1568 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1569 .flags = CLK_SET_RATE_PARENT, 1570 .ops = &clk_rcg2_shared_no_init_park_ops, 1571 }, 1572 }; 1573 1574 static struct clk_rcg2 gcc_pcie_3b_aux_clk_src = { 1575 .cmd_rcgr = 0x941b8, 1576 .mnd_width = 16, 1577 .hid_width = 5, 1578 .parent_map = gcc_parent_map_2, 1579 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1580 .clkr.hw.init = &(const struct clk_init_data) { 1581 .name = "gcc_pcie_3b_aux_clk_src", 1582 .parent_data = gcc_parent_data_2, 1583 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1584 .flags = CLK_SET_RATE_PARENT, 1585 .ops = &clk_rcg2_shared_no_init_park_ops, 1586 }, 1587 }; 1588 1589 static struct clk_rcg2 gcc_pcie_3b_phy_rchng_clk_src = { 1590 .cmd_rcgr = 0x94088, 1591 .mnd_width = 0, 1592 .hid_width = 5, 1593 .parent_map = gcc_parent_map_0, 1594 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1595 .clkr.hw.init = &(const struct clk_init_data) { 1596 .name = "gcc_pcie_3b_phy_rchng_clk_src", 1597 .parent_data = gcc_parent_data_0, 1598 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1599 .flags = CLK_SET_RATE_PARENT, 1600 .ops = &clk_rcg2_shared_no_init_park_ops, 1601 }, 1602 }; 1603 1604 static struct clk_rcg2 gcc_pcie_4_aux_clk_src = { 1605 .cmd_rcgr = 0x881a8, 1606 .mnd_width = 16, 1607 .hid_width = 5, 1608 .parent_map = gcc_parent_map_2, 1609 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1610 .clkr.hw.init = &(const struct clk_init_data) { 1611 .name = "gcc_pcie_4_aux_clk_src", 1612 .parent_data = gcc_parent_data_2, 1613 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1614 .flags = CLK_SET_RATE_PARENT, 1615 .ops = &clk_rcg2_shared_no_init_park_ops, 1616 }, 1617 }; 1618 1619 static struct clk_rcg2 gcc_pcie_4_phy_rchng_clk_src = { 1620 .cmd_rcgr = 0x88078, 1621 .mnd_width = 0, 1622 .hid_width = 5, 1623 .parent_map = gcc_parent_map_0, 1624 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1625 .clkr.hw.init = &(const struct clk_init_data) { 1626 .name = "gcc_pcie_4_phy_rchng_clk_src", 1627 .parent_data = gcc_parent_data_0, 1628 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1629 .flags = CLK_SET_RATE_PARENT, 1630 .ops = &clk_rcg2_shared_no_init_park_ops, 1631 }, 1632 }; 1633 1634 static struct clk_rcg2 gcc_pcie_5_aux_clk_src = { 1635 .cmd_rcgr = 0xc30a0, 1636 .mnd_width = 16, 1637 .hid_width = 5, 1638 .parent_map = gcc_parent_map_2, 1639 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1640 .clkr.hw.init = &(const struct clk_init_data) { 1641 .name = "gcc_pcie_5_aux_clk_src", 1642 .parent_data = gcc_parent_data_2, 1643 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1644 .flags = CLK_SET_RATE_PARENT, 1645 .ops = &clk_rcg2_shared_no_init_park_ops, 1646 }, 1647 }; 1648 1649 static struct clk_rcg2 gcc_pcie_5_phy_rchng_clk_src = { 1650 .cmd_rcgr = 0xc3084, 1651 .mnd_width = 0, 1652 .hid_width = 5, 1653 .parent_map = gcc_parent_map_0, 1654 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1655 .clkr.hw.init = &(const struct clk_init_data) { 1656 .name = "gcc_pcie_5_phy_rchng_clk_src", 1657 .parent_data = gcc_parent_data_0, 1658 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1659 .flags = CLK_SET_RATE_PARENT, 1660 .ops = &clk_rcg2_shared_no_init_park_ops, 1661 }, 1662 }; 1663 1664 static struct clk_rcg2 gcc_pcie_6_aux_clk_src = { 1665 .cmd_rcgr = 0x8a1a8, 1666 .mnd_width = 16, 1667 .hid_width = 5, 1668 .parent_map = gcc_parent_map_2, 1669 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1670 .clkr.hw.init = &(const struct clk_init_data) { 1671 .name = "gcc_pcie_6_aux_clk_src", 1672 .parent_data = gcc_parent_data_2, 1673 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1674 .flags = CLK_SET_RATE_PARENT, 1675 .ops = &clk_rcg2_shared_no_init_park_ops, 1676 }, 1677 }; 1678 1679 static struct clk_rcg2 gcc_pcie_6_phy_rchng_clk_src = { 1680 .cmd_rcgr = 0x8a078, 1681 .mnd_width = 0, 1682 .hid_width = 5, 1683 .parent_map = gcc_parent_map_0, 1684 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1685 .clkr.hw.init = &(const struct clk_init_data) { 1686 .name = "gcc_pcie_6_phy_rchng_clk_src", 1687 .parent_data = gcc_parent_data_0, 1688 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1689 .flags = CLK_SET_RATE_PARENT, 1690 .ops = &clk_rcg2_shared_no_init_park_ops, 1691 }, 1692 }; 1693 1694 static struct clk_rcg2 gcc_pcie_phy_3a_aux_clk_src = { 1695 .cmd_rcgr = 0x6c01c, 1696 .mnd_width = 16, 1697 .hid_width = 5, 1698 .parent_map = gcc_parent_map_2, 1699 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1700 .clkr.hw.init = &(const struct clk_init_data) { 1701 .name = "gcc_pcie_phy_3a_aux_clk_src", 1702 .parent_data = gcc_parent_data_2, 1703 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1704 .flags = CLK_SET_RATE_PARENT, 1705 .ops = &clk_rcg2_shared_no_init_park_ops, 1706 }, 1707 }; 1708 1709 static struct clk_rcg2 gcc_pcie_phy_3b_aux_clk_src = { 1710 .cmd_rcgr = 0x7501c, 1711 .mnd_width = 16, 1712 .hid_width = 5, 1713 .parent_map = gcc_parent_map_2, 1714 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1715 .clkr.hw.init = &(const struct clk_init_data) { 1716 .name = "gcc_pcie_phy_3b_aux_clk_src", 1717 .parent_data = gcc_parent_data_2, 1718 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1719 .flags = CLK_SET_RATE_PARENT, 1720 .ops = &clk_rcg2_shared_no_init_park_ops, 1721 }, 1722 }; 1723 1724 static struct clk_rcg2 gcc_pcie_phy_4_aux_clk_src = { 1725 .cmd_rcgr = 0xd3018, 1726 .mnd_width = 16, 1727 .hid_width = 5, 1728 .parent_map = gcc_parent_map_2, 1729 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1730 .clkr.hw.init = &(const struct clk_init_data) { 1731 .name = "gcc_pcie_phy_4_aux_clk_src", 1732 .parent_data = gcc_parent_data_2, 1733 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1734 .flags = CLK_SET_RATE_PARENT, 1735 .ops = &clk_rcg2_shared_no_init_park_ops, 1736 }, 1737 }; 1738 1739 static struct clk_rcg2 gcc_pcie_phy_5_aux_clk_src = { 1740 .cmd_rcgr = 0xd2018, 1741 .mnd_width = 16, 1742 .hid_width = 5, 1743 .parent_map = gcc_parent_map_2, 1744 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1745 .clkr.hw.init = &(const struct clk_init_data) { 1746 .name = "gcc_pcie_phy_5_aux_clk_src", 1747 .parent_data = gcc_parent_data_2, 1748 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1749 .flags = CLK_SET_RATE_PARENT, 1750 .ops = &clk_rcg2_shared_no_init_park_ops, 1751 }, 1752 }; 1753 1754 static struct clk_rcg2 gcc_pcie_phy_6_aux_clk_src = { 1755 .cmd_rcgr = 0xd4018, 1756 .mnd_width = 16, 1757 .hid_width = 5, 1758 .parent_map = gcc_parent_map_2, 1759 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1760 .clkr.hw.init = &(const struct clk_init_data) { 1761 .name = "gcc_pcie_phy_6_aux_clk_src", 1762 .parent_data = gcc_parent_data_2, 1763 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1764 .flags = CLK_SET_RATE_PARENT, 1765 .ops = &clk_rcg2_shared_no_init_park_ops, 1766 }, 1767 }; 1768 1769 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 1770 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 1771 { } 1772 }; 1773 1774 static struct clk_rcg2 gcc_pdm2_clk_src = { 1775 .cmd_rcgr = 0x33010, 1776 .mnd_width = 0, 1777 .hid_width = 5, 1778 .parent_map = gcc_parent_map_0, 1779 .freq_tbl = ftbl_gcc_pdm2_clk_src, 1780 .clkr.hw.init = &(const struct clk_init_data) { 1781 .name = "gcc_pdm2_clk_src", 1782 .parent_data = gcc_parent_data_0, 1783 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1784 .flags = CLK_SET_RATE_PARENT, 1785 .ops = &clk_rcg2_shared_no_init_park_ops, 1786 }, 1787 }; 1788 1789 static const struct freq_tbl ftbl_gcc_qupv3_oob_qspi_s0_clk_src[] = { 1790 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 1791 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 1792 F(19200000, P_BI_TCXO, 1, 0, 0), 1793 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 1794 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 1795 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 1796 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 1797 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1798 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 1799 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 1800 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 1801 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 1802 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 1803 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1804 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 1805 { } 1806 }; 1807 1808 static struct clk_init_data gcc_qupv3_oob_qspi_s0_clk_src_init = { 1809 .name = "gcc_qupv3_oob_qspi_s0_clk_src", 1810 .parent_data = gcc_parent_data_3, 1811 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1812 .flags = CLK_SET_RATE_PARENT, 1813 .ops = &clk_rcg2_shared_no_init_park_ops, 1814 }; 1815 1816 static struct clk_rcg2 gcc_qupv3_oob_qspi_s0_clk_src = { 1817 .cmd_rcgr = 0xe7044, 1818 .mnd_width = 16, 1819 .hid_width = 5, 1820 .parent_map = gcc_parent_map_3, 1821 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s0_clk_src, 1822 .clkr.hw.init = &gcc_qupv3_oob_qspi_s0_clk_src_init, 1823 }; 1824 1825 static const struct freq_tbl ftbl_gcc_qupv3_oob_qspi_s1_clk_src[] = { 1826 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 1827 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 1828 F(19200000, P_BI_TCXO, 1, 0, 0), 1829 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 1830 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 1831 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 1832 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 1833 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1834 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 1835 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 1836 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 1837 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 1838 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 1839 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1840 { } 1841 }; 1842 1843 static struct clk_init_data gcc_qupv3_oob_qspi_s1_clk_src_init = { 1844 .name = "gcc_qupv3_oob_qspi_s1_clk_src", 1845 .parent_data = gcc_parent_data_1, 1846 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1847 .flags = CLK_SET_RATE_PARENT, 1848 .ops = &clk_rcg2_shared_no_init_park_ops, 1849 }; 1850 1851 static struct clk_rcg2 gcc_qupv3_oob_qspi_s1_clk_src = { 1852 .cmd_rcgr = 0xe7170, 1853 .mnd_width = 16, 1854 .hid_width = 5, 1855 .parent_map = gcc_parent_map_1, 1856 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src, 1857 .clkr.hw.init = &gcc_qupv3_oob_qspi_s1_clk_src_init, 1858 }; 1859 1860 static struct clk_init_data gcc_qupv3_wrap0_qspi_s2_clk_src_init = { 1861 .name = "gcc_qupv3_wrap0_qspi_s2_clk_src", 1862 .parent_data = gcc_parent_data_1, 1863 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1864 .flags = CLK_SET_RATE_PARENT, 1865 .ops = &clk_rcg2_shared_no_init_park_ops, 1866 }; 1867 1868 static struct clk_rcg2 gcc_qupv3_wrap0_qspi_s2_clk_src = { 1869 .cmd_rcgr = 0x287a0, 1870 .mnd_width = 16, 1871 .hid_width = 5, 1872 .parent_map = gcc_parent_map_1, 1873 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src, 1874 .clkr.hw.init = &gcc_qupv3_wrap0_qspi_s2_clk_src_init, 1875 }; 1876 1877 static struct clk_init_data gcc_qupv3_wrap0_qspi_s3_clk_src_init = { 1878 .name = "gcc_qupv3_wrap0_qspi_s3_clk_src", 1879 .parent_data = gcc_parent_data_1, 1880 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1881 .flags = CLK_SET_RATE_PARENT, 1882 .ops = &clk_rcg2_shared_no_init_park_ops, 1883 }; 1884 1885 static struct clk_rcg2 gcc_qupv3_wrap0_qspi_s3_clk_src = { 1886 .cmd_rcgr = 0x288d0, 1887 .mnd_width = 16, 1888 .hid_width = 5, 1889 .parent_map = gcc_parent_map_1, 1890 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src, 1891 .clkr.hw.init = &gcc_qupv3_wrap0_qspi_s3_clk_src_init, 1892 }; 1893 1894 static struct clk_init_data gcc_qupv3_wrap0_qspi_s6_clk_src_init = { 1895 .name = "gcc_qupv3_wrap0_qspi_s6_clk_src", 1896 .parent_data = gcc_parent_data_1, 1897 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1898 .flags = CLK_SET_RATE_PARENT, 1899 .ops = &clk_rcg2_shared_no_init_park_ops, 1900 }; 1901 1902 static struct clk_rcg2 gcc_qupv3_wrap0_qspi_s6_clk_src = { 1903 .cmd_rcgr = 0x2866c, 1904 .mnd_width = 16, 1905 .hid_width = 5, 1906 .parent_map = gcc_parent_map_1, 1907 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src, 1908 .clkr.hw.init = &gcc_qupv3_wrap0_qspi_s6_clk_src_init, 1909 }; 1910 1911 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 1912 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 1913 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 1914 F(19200000, P_BI_TCXO, 1, 0, 0), 1915 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 1916 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 1917 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 1918 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 1919 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1920 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 1921 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 1922 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 1923 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 1924 { } 1925 }; 1926 1927 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 1928 .name = "gcc_qupv3_wrap0_s0_clk_src", 1929 .parent_data = gcc_parent_data_1, 1930 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1931 .flags = CLK_SET_RATE_PARENT, 1932 .ops = &clk_rcg2_shared_no_init_park_ops, 1933 }; 1934 1935 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 1936 .cmd_rcgr = 0x28014, 1937 .mnd_width = 16, 1938 .hid_width = 5, 1939 .parent_map = gcc_parent_map_1, 1940 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1941 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 1942 }; 1943 1944 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 1945 .name = "gcc_qupv3_wrap0_s1_clk_src", 1946 .parent_data = gcc_parent_data_1, 1947 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1948 .flags = CLK_SET_RATE_PARENT, 1949 .ops = &clk_rcg2_shared_no_init_park_ops, 1950 }; 1951 1952 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 1953 .cmd_rcgr = 0x28150, 1954 .mnd_width = 16, 1955 .hid_width = 5, 1956 .parent_map = gcc_parent_map_1, 1957 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1958 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 1959 }; 1960 1961 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s4_clk_src[] = { 1962 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 1963 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 1964 F(19200000, P_BI_TCXO, 1, 0, 0), 1965 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 1966 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 1967 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 1968 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 1969 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1970 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 1971 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 1972 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 1973 { } 1974 }; 1975 1976 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 1977 .name = "gcc_qupv3_wrap0_s4_clk_src", 1978 .parent_data = gcc_parent_data_1, 1979 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1980 .flags = CLK_SET_RATE_PARENT, 1981 .ops = &clk_rcg2_shared_no_init_park_ops, 1982 }; 1983 1984 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 1985 .cmd_rcgr = 0x282b4, 1986 .mnd_width = 16, 1987 .hid_width = 5, 1988 .parent_map = gcc_parent_map_1, 1989 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 1990 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 1991 }; 1992 1993 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 1994 .name = "gcc_qupv3_wrap0_s5_clk_src", 1995 .parent_data = gcc_parent_data_1, 1996 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1997 .flags = CLK_SET_RATE_PARENT, 1998 .ops = &clk_rcg2_shared_no_init_park_ops, 1999 }; 2000 2001 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 2002 .cmd_rcgr = 0x283f0, 2003 .mnd_width = 16, 2004 .hid_width = 5, 2005 .parent_map = gcc_parent_map_1, 2006 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 2007 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 2008 }; 2009 2010 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 2011 .name = "gcc_qupv3_wrap0_s7_clk_src", 2012 .parent_data = gcc_parent_data_1, 2013 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2014 .flags = CLK_SET_RATE_PARENT, 2015 .ops = &clk_rcg2_shared_no_init_park_ops, 2016 }; 2017 2018 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 2019 .cmd_rcgr = 0x28540, 2020 .mnd_width = 16, 2021 .hid_width = 5, 2022 .parent_map = gcc_parent_map_1, 2023 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 2024 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 2025 }; 2026 2027 static struct clk_init_data gcc_qupv3_wrap1_qspi_s2_clk_src_init = { 2028 .name = "gcc_qupv3_wrap1_qspi_s2_clk_src", 2029 .parent_data = gcc_parent_data_1, 2030 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2031 .flags = CLK_SET_RATE_PARENT, 2032 .ops = &clk_rcg2_shared_no_init_park_ops, 2033 }; 2034 2035 static struct clk_rcg2 gcc_qupv3_wrap1_qspi_s2_clk_src = { 2036 .cmd_rcgr = 0xb37a0, 2037 .mnd_width = 16, 2038 .hid_width = 5, 2039 .parent_map = gcc_parent_map_1, 2040 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src, 2041 .clkr.hw.init = &gcc_qupv3_wrap1_qspi_s2_clk_src_init, 2042 }; 2043 2044 static struct clk_init_data gcc_qupv3_wrap1_qspi_s3_clk_src_init = { 2045 .name = "gcc_qupv3_wrap1_qspi_s3_clk_src", 2046 .parent_data = gcc_parent_data_1, 2047 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2048 .flags = CLK_SET_RATE_PARENT, 2049 .ops = &clk_rcg2_shared_no_init_park_ops, 2050 }; 2051 2052 static struct clk_rcg2 gcc_qupv3_wrap1_qspi_s3_clk_src = { 2053 .cmd_rcgr = 0xb38d0, 2054 .mnd_width = 16, 2055 .hid_width = 5, 2056 .parent_map = gcc_parent_map_1, 2057 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src, 2058 .clkr.hw.init = &gcc_qupv3_wrap1_qspi_s3_clk_src_init, 2059 }; 2060 2061 static struct clk_init_data gcc_qupv3_wrap1_qspi_s6_clk_src_init = { 2062 .name = "gcc_qupv3_wrap1_qspi_s6_clk_src", 2063 .parent_data = gcc_parent_data_1, 2064 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2065 .flags = CLK_SET_RATE_PARENT, 2066 .ops = &clk_rcg2_shared_no_init_park_ops, 2067 }; 2068 2069 static struct clk_rcg2 gcc_qupv3_wrap1_qspi_s6_clk_src = { 2070 .cmd_rcgr = 0xb366c, 2071 .mnd_width = 16, 2072 .hid_width = 5, 2073 .parent_map = gcc_parent_map_1, 2074 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src, 2075 .clkr.hw.init = &gcc_qupv3_wrap1_qspi_s6_clk_src_init, 2076 }; 2077 2078 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 2079 .name = "gcc_qupv3_wrap1_s0_clk_src", 2080 .parent_data = gcc_parent_data_1, 2081 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2082 .flags = CLK_SET_RATE_PARENT, 2083 .ops = &clk_rcg2_shared_no_init_park_ops, 2084 }; 2085 2086 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 2087 .cmd_rcgr = 0xb3014, 2088 .mnd_width = 16, 2089 .hid_width = 5, 2090 .parent_map = gcc_parent_map_1, 2091 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 2092 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 2093 }; 2094 2095 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 2096 .name = "gcc_qupv3_wrap1_s1_clk_src", 2097 .parent_data = gcc_parent_data_1, 2098 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2099 .flags = CLK_SET_RATE_PARENT, 2100 .ops = &clk_rcg2_shared_no_init_park_ops, 2101 }; 2102 2103 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 2104 .cmd_rcgr = 0xb3150, 2105 .mnd_width = 16, 2106 .hid_width = 5, 2107 .parent_map = gcc_parent_map_1, 2108 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 2109 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 2110 }; 2111 2112 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 2113 .name = "gcc_qupv3_wrap1_s4_clk_src", 2114 .parent_data = gcc_parent_data_1, 2115 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2116 .flags = CLK_SET_RATE_PARENT, 2117 .ops = &clk_rcg2_shared_no_init_park_ops, 2118 }; 2119 2120 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 2121 .cmd_rcgr = 0xb32b4, 2122 .mnd_width = 16, 2123 .hid_width = 5, 2124 .parent_map = gcc_parent_map_1, 2125 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 2126 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 2127 }; 2128 2129 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 2130 .name = "gcc_qupv3_wrap1_s5_clk_src", 2131 .parent_data = gcc_parent_data_1, 2132 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2133 .flags = CLK_SET_RATE_PARENT, 2134 .ops = &clk_rcg2_shared_no_init_park_ops, 2135 }; 2136 2137 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 2138 .cmd_rcgr = 0xb33f0, 2139 .mnd_width = 16, 2140 .hid_width = 5, 2141 .parent_map = gcc_parent_map_1, 2142 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 2143 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 2144 }; 2145 2146 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 2147 .name = "gcc_qupv3_wrap1_s7_clk_src", 2148 .parent_data = gcc_parent_data_1, 2149 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2150 .flags = CLK_SET_RATE_PARENT, 2151 .ops = &clk_rcg2_shared_no_init_park_ops, 2152 }; 2153 2154 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 2155 .cmd_rcgr = 0xb3540, 2156 .mnd_width = 16, 2157 .hid_width = 5, 2158 .parent_map = gcc_parent_map_1, 2159 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 2160 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 2161 }; 2162 2163 static struct clk_init_data gcc_qupv3_wrap2_qspi_s2_clk_src_init = { 2164 .name = "gcc_qupv3_wrap2_qspi_s2_clk_src", 2165 .parent_data = gcc_parent_data_1, 2166 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2167 .flags = CLK_SET_RATE_PARENT, 2168 .ops = &clk_rcg2_shared_no_init_park_ops, 2169 }; 2170 2171 static struct clk_rcg2 gcc_qupv3_wrap2_qspi_s2_clk_src = { 2172 .cmd_rcgr = 0xb47a0, 2173 .mnd_width = 16, 2174 .hid_width = 5, 2175 .parent_map = gcc_parent_map_1, 2176 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src, 2177 .clkr.hw.init = &gcc_qupv3_wrap2_qspi_s2_clk_src_init, 2178 }; 2179 2180 static struct clk_init_data gcc_qupv3_wrap2_qspi_s3_clk_src_init = { 2181 .name = "gcc_qupv3_wrap2_qspi_s3_clk_src", 2182 .parent_data = gcc_parent_data_1, 2183 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2184 .flags = CLK_SET_RATE_PARENT, 2185 .ops = &clk_rcg2_shared_no_init_park_ops, 2186 }; 2187 2188 static struct clk_rcg2 gcc_qupv3_wrap2_qspi_s3_clk_src = { 2189 .cmd_rcgr = 0xb48d0, 2190 .mnd_width = 16, 2191 .hid_width = 5, 2192 .parent_map = gcc_parent_map_1, 2193 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src, 2194 .clkr.hw.init = &gcc_qupv3_wrap2_qspi_s3_clk_src_init, 2195 }; 2196 2197 static struct clk_init_data gcc_qupv3_wrap2_qspi_s6_clk_src_init = { 2198 .name = "gcc_qupv3_wrap2_qspi_s6_clk_src", 2199 .parent_data = gcc_parent_data_1, 2200 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2201 .flags = CLK_SET_RATE_PARENT, 2202 .ops = &clk_rcg2_shared_no_init_park_ops, 2203 }; 2204 2205 static struct clk_rcg2 gcc_qupv3_wrap2_qspi_s6_clk_src = { 2206 .cmd_rcgr = 0xb466c, 2207 .mnd_width = 16, 2208 .hid_width = 5, 2209 .parent_map = gcc_parent_map_1, 2210 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src, 2211 .clkr.hw.init = &gcc_qupv3_wrap2_qspi_s6_clk_src_init, 2212 }; 2213 2214 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 2215 .name = "gcc_qupv3_wrap2_s0_clk_src", 2216 .parent_data = gcc_parent_data_1, 2217 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2218 .flags = CLK_SET_RATE_PARENT, 2219 .ops = &clk_rcg2_shared_no_init_park_ops, 2220 }; 2221 2222 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 2223 .cmd_rcgr = 0xb4014, 2224 .mnd_width = 16, 2225 .hid_width = 5, 2226 .parent_map = gcc_parent_map_1, 2227 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 2228 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 2229 }; 2230 2231 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 2232 .name = "gcc_qupv3_wrap2_s1_clk_src", 2233 .parent_data = gcc_parent_data_1, 2234 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2235 .flags = CLK_SET_RATE_PARENT, 2236 .ops = &clk_rcg2_shared_no_init_park_ops, 2237 }; 2238 2239 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 2240 .cmd_rcgr = 0xb4150, 2241 .mnd_width = 16, 2242 .hid_width = 5, 2243 .parent_map = gcc_parent_map_1, 2244 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 2245 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 2246 }; 2247 2248 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 2249 .name = "gcc_qupv3_wrap2_s4_clk_src", 2250 .parent_data = gcc_parent_data_1, 2251 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2252 .flags = CLK_SET_RATE_PARENT, 2253 .ops = &clk_rcg2_shared_no_init_park_ops, 2254 }; 2255 2256 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 2257 .cmd_rcgr = 0xb42b4, 2258 .mnd_width = 16, 2259 .hid_width = 5, 2260 .parent_map = gcc_parent_map_1, 2261 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 2262 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 2263 }; 2264 2265 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { 2266 .name = "gcc_qupv3_wrap2_s5_clk_src", 2267 .parent_data = gcc_parent_data_1, 2268 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2269 .flags = CLK_SET_RATE_PARENT, 2270 .ops = &clk_rcg2_shared_no_init_park_ops, 2271 }; 2272 2273 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { 2274 .cmd_rcgr = 0xb43f0, 2275 .mnd_width = 16, 2276 .hid_width = 5, 2277 .parent_map = gcc_parent_map_1, 2278 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 2279 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, 2280 }; 2281 2282 static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = { 2283 .name = "gcc_qupv3_wrap2_s7_clk_src", 2284 .parent_data = gcc_parent_data_1, 2285 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2286 .flags = CLK_SET_RATE_PARENT, 2287 .ops = &clk_rcg2_shared_no_init_park_ops, 2288 }; 2289 2290 static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = { 2291 .cmd_rcgr = 0xb4540, 2292 .mnd_width = 16, 2293 .hid_width = 5, 2294 .parent_map = gcc_parent_map_1, 2295 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 2296 .clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init, 2297 }; 2298 2299 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 2300 F(400000, P_BI_TCXO, 12, 1, 4), 2301 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 2302 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 2303 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 2304 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), 2305 { } 2306 }; 2307 2308 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 2309 .cmd_rcgr = 0xb001c, 2310 .mnd_width = 8, 2311 .hid_width = 5, 2312 .parent_map = gcc_parent_map_17, 2313 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 2314 .clkr.hw.init = &(const struct clk_init_data) { 2315 .name = "gcc_sdcc2_apps_clk_src", 2316 .parent_data = gcc_parent_data_17, 2317 .num_parents = ARRAY_SIZE(gcc_parent_data_17), 2318 .flags = CLK_SET_RATE_PARENT, 2319 .ops = &clk_rcg2_shared_floor_ops, 2320 }, 2321 }; 2322 2323 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 2324 F(400000, P_BI_TCXO, 12, 1, 4), 2325 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 2326 F(75000000, P_GCC_GPLL0_OUT_MAIN, 8, 0, 0), 2327 { } 2328 }; 2329 2330 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 2331 .cmd_rcgr = 0xdf01c, 2332 .mnd_width = 8, 2333 .hid_width = 5, 2334 .parent_map = gcc_parent_map_3, 2335 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 2336 .clkr.hw.init = &(const struct clk_init_data) { 2337 .name = "gcc_sdcc4_apps_clk_src", 2338 .parent_data = gcc_parent_data_3, 2339 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 2340 .flags = CLK_SET_RATE_PARENT, 2341 .ops = &clk_rcg2_shared_floor_ops, 2342 }, 2343 }; 2344 2345 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 2346 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 2347 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 2348 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), 2349 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 2350 { } 2351 }; 2352 2353 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 2354 .cmd_rcgr = 0x77038, 2355 .mnd_width = 8, 2356 .hid_width = 5, 2357 .parent_map = gcc_parent_map_6, 2358 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 2359 .clkr.hw.init = &(const struct clk_init_data) { 2360 .name = "gcc_ufs_phy_axi_clk_src", 2361 .parent_data = gcc_parent_data_6, 2362 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 2363 .flags = CLK_SET_RATE_PARENT, 2364 .ops = &clk_rcg2_shared_no_init_park_ops, 2365 }, 2366 }; 2367 2368 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 2369 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 2370 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), 2371 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 2372 { } 2373 }; 2374 2375 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 2376 .cmd_rcgr = 0x77090, 2377 .mnd_width = 0, 2378 .hid_width = 5, 2379 .parent_map = gcc_parent_map_6, 2380 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 2381 .clkr.hw.init = &(const struct clk_init_data) { 2382 .name = "gcc_ufs_phy_ice_core_clk_src", 2383 .parent_data = gcc_parent_data_6, 2384 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 2385 .flags = CLK_SET_RATE_PARENT, 2386 .ops = &clk_rcg2_shared_no_init_park_ops, 2387 }, 2388 }; 2389 2390 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 2391 .cmd_rcgr = 0x770c4, 2392 .mnd_width = 0, 2393 .hid_width = 5, 2394 .parent_map = gcc_parent_map_5, 2395 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2396 .clkr.hw.init = &(const struct clk_init_data) { 2397 .name = "gcc_ufs_phy_phy_aux_clk_src", 2398 .parent_data = gcc_parent_data_5, 2399 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 2400 .flags = CLK_SET_RATE_PARENT, 2401 .ops = &clk_rcg2_shared_no_init_park_ops, 2402 }, 2403 }; 2404 2405 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 2406 .cmd_rcgr = 0x770a8, 2407 .mnd_width = 0, 2408 .hid_width = 5, 2409 .parent_map = gcc_parent_map_6, 2410 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 2411 .clkr.hw.init = &(const struct clk_init_data) { 2412 .name = "gcc_ufs_phy_unipro_core_clk_src", 2413 .parent_data = gcc_parent_data_6, 2414 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 2415 .flags = CLK_SET_RATE_PARENT, 2416 .ops = &clk_rcg2_shared_no_init_park_ops, 2417 }, 2418 }; 2419 2420 static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = { 2421 F(60000000, P_GCC_GPLL14_OUT_MAIN, 10, 0, 0), 2422 F(120000000, P_GCC_GPLL14_OUT_MAIN, 5, 0, 0), 2423 { } 2424 }; 2425 2426 static struct clk_rcg2 gcc_usb20_master_clk_src = { 2427 .cmd_rcgr = 0xbc030, 2428 .mnd_width = 8, 2429 .hid_width = 5, 2430 .parent_map = gcc_parent_map_7, 2431 .freq_tbl = ftbl_gcc_usb20_master_clk_src, 2432 .clkr.hw.init = &(const struct clk_init_data) { 2433 .name = "gcc_usb20_master_clk_src", 2434 .parent_data = gcc_parent_data_7, 2435 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 2436 .flags = CLK_SET_RATE_PARENT, 2437 .ops = &clk_rcg2_shared_no_init_park_ops, 2438 }, 2439 }; 2440 2441 static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = { 2442 .cmd_rcgr = 0xbc048, 2443 .mnd_width = 0, 2444 .hid_width = 5, 2445 .parent_map = gcc_parent_map_7, 2446 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2447 .clkr.hw.init = &(const struct clk_init_data) { 2448 .name = "gcc_usb20_mock_utmi_clk_src", 2449 .parent_data = gcc_parent_data_7, 2450 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 2451 .flags = CLK_SET_RATE_PARENT, 2452 .ops = &clk_rcg2_shared_no_init_park_ops, 2453 }, 2454 }; 2455 2456 static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = { 2457 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), 2458 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 2459 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 2460 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 2461 { } 2462 }; 2463 2464 static struct clk_rcg2 gcc_usb30_mp_master_clk_src = { 2465 .cmd_rcgr = 0x9a03c, 2466 .mnd_width = 8, 2467 .hid_width = 5, 2468 .parent_map = gcc_parent_map_0, 2469 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 2470 .clkr.hw.init = &(const struct clk_init_data) { 2471 .name = "gcc_usb30_mp_master_clk_src", 2472 .parent_data = gcc_parent_data_0, 2473 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2474 .flags = CLK_SET_RATE_PARENT, 2475 .ops = &clk_rcg2_shared_no_init_park_ops, 2476 }, 2477 }; 2478 2479 static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = { 2480 .cmd_rcgr = 0x9a054, 2481 .mnd_width = 0, 2482 .hid_width = 5, 2483 .parent_map = gcc_parent_map_0, 2484 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2485 .clkr.hw.init = &(const struct clk_init_data) { 2486 .name = "gcc_usb30_mp_mock_utmi_clk_src", 2487 .parent_data = gcc_parent_data_0, 2488 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2489 .flags = CLK_SET_RATE_PARENT, 2490 .ops = &clk_rcg2_shared_no_init_park_ops, 2491 }, 2492 }; 2493 2494 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 2495 .cmd_rcgr = 0x3f04c, 2496 .mnd_width = 8, 2497 .hid_width = 5, 2498 .parent_map = gcc_parent_map_0, 2499 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 2500 .clkr.hw.init = &(const struct clk_init_data) { 2501 .name = "gcc_usb30_prim_master_clk_src", 2502 .parent_data = gcc_parent_data_0, 2503 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2504 .flags = CLK_SET_RATE_PARENT, 2505 .ops = &clk_rcg2_shared_no_init_park_ops, 2506 }, 2507 }; 2508 2509 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 2510 .cmd_rcgr = 0x3f064, 2511 .mnd_width = 0, 2512 .hid_width = 5, 2513 .parent_map = gcc_parent_map_0, 2514 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2515 .clkr.hw.init = &(const struct clk_init_data) { 2516 .name = "gcc_usb30_prim_mock_utmi_clk_src", 2517 .parent_data = gcc_parent_data_0, 2518 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2519 .flags = CLK_SET_RATE_PARENT, 2520 .ops = &clk_rcg2_shared_no_init_park_ops, 2521 }, 2522 }; 2523 2524 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { 2525 .cmd_rcgr = 0xe203c, 2526 .mnd_width = 8, 2527 .hid_width = 5, 2528 .parent_map = gcc_parent_map_0, 2529 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 2530 .clkr.hw.init = &(const struct clk_init_data) { 2531 .name = "gcc_usb30_sec_master_clk_src", 2532 .parent_data = gcc_parent_data_0, 2533 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2534 .flags = CLK_SET_RATE_PARENT, 2535 .ops = &clk_rcg2_shared_no_init_park_ops, 2536 }, 2537 }; 2538 2539 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { 2540 .cmd_rcgr = 0xe2054, 2541 .mnd_width = 0, 2542 .hid_width = 5, 2543 .parent_map = gcc_parent_map_0, 2544 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2545 .clkr.hw.init = &(const struct clk_init_data) { 2546 .name = "gcc_usb30_sec_mock_utmi_clk_src", 2547 .parent_data = gcc_parent_data_0, 2548 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2549 .flags = CLK_SET_RATE_PARENT, 2550 .ops = &clk_rcg2_shared_no_init_park_ops, 2551 }, 2552 }; 2553 2554 static struct clk_rcg2 gcc_usb30_tert_master_clk_src = { 2555 .cmd_rcgr = 0xe103c, 2556 .mnd_width = 8, 2557 .hid_width = 5, 2558 .parent_map = gcc_parent_map_0, 2559 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 2560 .clkr.hw.init = &(const struct clk_init_data) { 2561 .name = "gcc_usb30_tert_master_clk_src", 2562 .parent_data = gcc_parent_data_0, 2563 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2564 .flags = CLK_SET_RATE_PARENT, 2565 .ops = &clk_rcg2_shared_no_init_park_ops, 2566 }, 2567 }; 2568 2569 static struct clk_rcg2 gcc_usb30_tert_mock_utmi_clk_src = { 2570 .cmd_rcgr = 0xe1054, 2571 .mnd_width = 0, 2572 .hid_width = 5, 2573 .parent_map = gcc_parent_map_0, 2574 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2575 .clkr.hw.init = &(const struct clk_init_data) { 2576 .name = "gcc_usb30_tert_mock_utmi_clk_src", 2577 .parent_data = gcc_parent_data_0, 2578 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2579 .flags = CLK_SET_RATE_PARENT, 2580 .ops = &clk_rcg2_shared_no_init_park_ops, 2581 }, 2582 }; 2583 2584 static struct clk_rcg2 gcc_usb3_mp_phy_aux_clk_src = { 2585 .cmd_rcgr = 0x9a088, 2586 .mnd_width = 0, 2587 .hid_width = 5, 2588 .parent_map = gcc_parent_map_8, 2589 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2590 .clkr.hw.init = &(const struct clk_init_data) { 2591 .name = "gcc_usb3_mp_phy_aux_clk_src", 2592 .parent_data = gcc_parent_data_8, 2593 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 2594 .flags = CLK_SET_RATE_PARENT, 2595 .ops = &clk_rcg2_shared_no_init_park_ops, 2596 }, 2597 }; 2598 2599 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 2600 .cmd_rcgr = 0x3f090, 2601 .mnd_width = 0, 2602 .hid_width = 5, 2603 .parent_map = gcc_parent_map_8, 2604 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2605 .clkr.hw.init = &(const struct clk_init_data) { 2606 .name = "gcc_usb3_prim_phy_aux_clk_src", 2607 .parent_data = gcc_parent_data_8, 2608 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 2609 .flags = CLK_SET_RATE_PARENT, 2610 .ops = &clk_rcg2_shared_no_init_park_ops, 2611 }, 2612 }; 2613 2614 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { 2615 .cmd_rcgr = 0xe2080, 2616 .mnd_width = 0, 2617 .hid_width = 5, 2618 .parent_map = gcc_parent_map_8, 2619 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2620 .clkr.hw.init = &(const struct clk_init_data) { 2621 .name = "gcc_usb3_sec_phy_aux_clk_src", 2622 .parent_data = gcc_parent_data_8, 2623 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 2624 .flags = CLK_SET_RATE_PARENT, 2625 .ops = &clk_rcg2_shared_no_init_park_ops, 2626 }, 2627 }; 2628 2629 static struct clk_rcg2 gcc_usb3_tert_phy_aux_clk_src = { 2630 .cmd_rcgr = 0xe1080, 2631 .mnd_width = 0, 2632 .hid_width = 5, 2633 .parent_map = gcc_parent_map_8, 2634 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2635 .clkr.hw.init = &(const struct clk_init_data) { 2636 .name = "gcc_usb3_tert_phy_aux_clk_src", 2637 .parent_data = gcc_parent_data_8, 2638 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 2639 .flags = CLK_SET_RATE_PARENT, 2640 .ops = &clk_rcg2_shared_no_init_park_ops, 2641 }, 2642 }; 2643 2644 static const struct freq_tbl ftbl_gcc_usb4_0_master_clk_src[] = { 2645 F(177666750, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0), 2646 F(355333500, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0), 2647 { } 2648 }; 2649 2650 static struct clk_rcg2 gcc_usb4_0_master_clk_src = { 2651 .cmd_rcgr = 0x2b02c, 2652 .mnd_width = 8, 2653 .hid_width = 5, 2654 .parent_map = gcc_parent_map_9, 2655 .freq_tbl = ftbl_gcc_usb4_0_master_clk_src, 2656 .clkr.hw.init = &(const struct clk_init_data) { 2657 .name = "gcc_usb4_0_master_clk_src", 2658 .parent_data = gcc_parent_data_9, 2659 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 2660 .flags = CLK_SET_RATE_PARENT, 2661 .ops = &clk_rcg2_shared_no_init_park_ops, 2662 }, 2663 }; 2664 2665 static const struct freq_tbl ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src[] = { 2666 F(19200000, P_BI_TCXO, 1, 0, 0), 2667 F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0), 2668 F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0), 2669 { } 2670 }; 2671 2672 static struct clk_rcg2 gcc_usb4_0_phy_pcie_pipe_clk_src = { 2673 .cmd_rcgr = 0x2b104, 2674 .mnd_width = 0, 2675 .hid_width = 5, 2676 .parent_map = gcc_parent_map_32, 2677 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src, 2678 .clkr.hw.init = &(const struct clk_init_data) { 2679 .name = "gcc_usb4_0_phy_pcie_pipe_clk_src", 2680 .parent_data = gcc_parent_data_32, 2681 .num_parents = ARRAY_SIZE(gcc_parent_data_32), 2682 .flags = CLK_SET_RATE_PARENT, 2683 .ops = &clk_rcg2_shared_no_init_park_ops, 2684 }, 2685 }; 2686 2687 static struct clk_rcg2 gcc_usb4_0_sb_if_clk_src = { 2688 .cmd_rcgr = 0x2b0a0, 2689 .mnd_width = 0, 2690 .hid_width = 5, 2691 .parent_map = gcc_parent_map_5, 2692 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2693 .clkr.hw.init = &(const struct clk_init_data) { 2694 .name = "gcc_usb4_0_sb_if_clk_src", 2695 .parent_data = gcc_parent_data_5, 2696 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 2697 .flags = CLK_SET_RATE_PARENT, 2698 .ops = &clk_rcg2_shared_no_init_park_ops, 2699 }, 2700 }; 2701 2702 static struct clk_rcg2 gcc_usb4_0_tmu_clk_src = { 2703 .cmd_rcgr = 0x2b084, 2704 .mnd_width = 0, 2705 .hid_width = 5, 2706 .parent_map = gcc_parent_map_10, 2707 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src, 2708 .clkr.hw.init = &(const struct clk_init_data) { 2709 .name = "gcc_usb4_0_tmu_clk_src", 2710 .parent_data = gcc_parent_data_10, 2711 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 2712 .flags = CLK_SET_RATE_PARENT, 2713 .ops = &clk_rcg2_shared_no_init_park_ops, 2714 }, 2715 }; 2716 2717 static struct clk_rcg2 gcc_usb4_1_master_clk_src = { 2718 .cmd_rcgr = 0x2d02c, 2719 .mnd_width = 8, 2720 .hid_width = 5, 2721 .parent_map = gcc_parent_map_9, 2722 .freq_tbl = ftbl_gcc_usb4_0_master_clk_src, 2723 .clkr.hw.init = &(const struct clk_init_data) { 2724 .name = "gcc_usb4_1_master_clk_src", 2725 .parent_data = gcc_parent_data_9, 2726 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 2727 .flags = CLK_SET_RATE_PARENT, 2728 .ops = &clk_rcg2_shared_no_init_park_ops, 2729 }, 2730 }; 2731 2732 static const struct freq_tbl ftbl_gcc_usb4_1_phy_pcie_pipe_clk_src[] = { 2733 F(19200000, P_BI_TCXO, 1, 0, 0), 2734 F(177666750, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0), 2735 F(355333500, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0), 2736 { } 2737 }; 2738 2739 static struct clk_rcg2 gcc_usb4_1_phy_pcie_pipe_clk_src = { 2740 .cmd_rcgr = 0x2d128, 2741 .mnd_width = 0, 2742 .hid_width = 5, 2743 .parent_map = gcc_parent_map_11, 2744 .freq_tbl = ftbl_gcc_usb4_1_phy_pcie_pipe_clk_src, 2745 .clkr.hw.init = &(const struct clk_init_data) { 2746 .name = "gcc_usb4_1_phy_pcie_pipe_clk_src", 2747 .parent_data = gcc_parent_data_11, 2748 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 2749 .flags = CLK_SET_RATE_PARENT, 2750 .ops = &clk_rcg2_shared_no_init_park_ops, 2751 }, 2752 }; 2753 2754 static const struct freq_tbl ftbl_gcc_usb4_1_phy_pll_pipe_clk_src[] = { 2755 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 2756 F(311000000, P_GCC_GPLL5_OUT_MAIN, 3, 0, 0), 2757 { } 2758 }; 2759 2760 static struct clk_rcg2 gcc_usb4_1_phy_pll_pipe_clk_src = { 2761 .cmd_rcgr = 0x2d0c8, 2762 .mnd_width = 0, 2763 .hid_width = 5, 2764 .parent_map = gcc_parent_map_41, 2765 .freq_tbl = ftbl_gcc_usb4_1_phy_pll_pipe_clk_src, 2766 .clkr.hw.init = &(const struct clk_init_data) { 2767 .name = "gcc_usb4_1_phy_pll_pipe_clk_src", 2768 .parent_data = gcc_parent_data_41, 2769 .num_parents = ARRAY_SIZE(gcc_parent_data_41), 2770 .flags = CLK_SET_RATE_PARENT, 2771 .ops = &clk_rcg2_shared_no_init_park_ops, 2772 }, 2773 }; 2774 2775 static struct clk_rcg2 gcc_usb4_1_sb_if_clk_src = { 2776 .cmd_rcgr = 0x2d0ac, 2777 .mnd_width = 0, 2778 .hid_width = 5, 2779 .parent_map = gcc_parent_map_5, 2780 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2781 .clkr.hw.init = &(const struct clk_init_data) { 2782 .name = "gcc_usb4_1_sb_if_clk_src", 2783 .parent_data = gcc_parent_data_5, 2784 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 2785 .flags = CLK_SET_RATE_PARENT, 2786 .ops = &clk_rcg2_shared_no_init_park_ops, 2787 }, 2788 }; 2789 2790 static struct clk_rcg2 gcc_usb4_1_tmu_clk_src = { 2791 .cmd_rcgr = 0x2d090, 2792 .mnd_width = 0, 2793 .hid_width = 5, 2794 .parent_map = gcc_parent_map_10, 2795 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src, 2796 .clkr.hw.init = &(const struct clk_init_data) { 2797 .name = "gcc_usb4_1_tmu_clk_src", 2798 .parent_data = gcc_parent_data_10, 2799 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 2800 .flags = CLK_SET_RATE_PARENT, 2801 .ops = &clk_rcg2_shared_no_init_park_ops, 2802 }, 2803 }; 2804 2805 static struct clk_rcg2 gcc_usb4_2_master_clk_src = { 2806 .cmd_rcgr = 0xe002c, 2807 .mnd_width = 8, 2808 .hid_width = 5, 2809 .parent_map = gcc_parent_map_9, 2810 .freq_tbl = ftbl_gcc_usb4_0_master_clk_src, 2811 .clkr.hw.init = &(const struct clk_init_data) { 2812 .name = "gcc_usb4_2_master_clk_src", 2813 .parent_data = gcc_parent_data_9, 2814 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 2815 .flags = CLK_SET_RATE_PARENT, 2816 .ops = &clk_rcg2_shared_no_init_park_ops, 2817 }, 2818 }; 2819 2820 static struct clk_rcg2 gcc_usb4_2_phy_pcie_pipe_clk_src = { 2821 .cmd_rcgr = 0xe0108, 2822 .mnd_width = 0, 2823 .hid_width = 5, 2824 .parent_map = gcc_parent_map_11, 2825 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src, 2826 .clkr.hw.init = &(const struct clk_init_data) { 2827 .name = "gcc_usb4_2_phy_pcie_pipe_clk_src", 2828 .parent_data = gcc_parent_data_11, 2829 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 2830 .flags = CLK_SET_RATE_PARENT, 2831 .ops = &clk_rcg2_shared_no_init_park_ops, 2832 }, 2833 }; 2834 2835 static struct clk_rcg2 gcc_usb4_2_sb_if_clk_src = { 2836 .cmd_rcgr = 0xe00a4, 2837 .mnd_width = 0, 2838 .hid_width = 5, 2839 .parent_map = gcc_parent_map_5, 2840 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2841 .clkr.hw.init = &(const struct clk_init_data) { 2842 .name = "gcc_usb4_2_sb_if_clk_src", 2843 .parent_data = gcc_parent_data_5, 2844 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 2845 .flags = CLK_SET_RATE_PARENT, 2846 .ops = &clk_rcg2_shared_no_init_park_ops, 2847 }, 2848 }; 2849 2850 static struct clk_rcg2 gcc_usb4_2_tmu_clk_src = { 2851 .cmd_rcgr = 0xe0088, 2852 .mnd_width = 0, 2853 .hid_width = 5, 2854 .parent_map = gcc_parent_map_10, 2855 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src, 2856 .clkr.hw.init = &(const struct clk_init_data) { 2857 .name = "gcc_usb4_2_tmu_clk_src", 2858 .parent_data = gcc_parent_data_10, 2859 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 2860 .flags = CLK_SET_RATE_PARENT, 2861 .ops = &clk_rcg2_shared_no_init_park_ops, 2862 }, 2863 }; 2864 2865 static struct clk_regmap_div gcc_pcie_3b_pipe_div_clk_src = { 2866 .reg = 0x94070, 2867 .shift = 0, 2868 .width = 4, 2869 .clkr.hw.init = &(const struct clk_init_data) { 2870 .name = "gcc_pcie_3b_pipe_div_clk_src", 2871 .parent_hws = (const struct clk_hw*[]) { 2872 &gcc_pcie_3b_pipe_clk_src.clkr.hw, 2873 }, 2874 .num_parents = 1, 2875 .flags = CLK_SET_RATE_PARENT, 2876 .ops = &clk_regmap_div_ro_ops, 2877 }, 2878 }; 2879 2880 static struct clk_regmap_div gcc_pcie_4_pipe_div_clk_src = { 2881 .reg = 0x88060, 2882 .shift = 0, 2883 .width = 4, 2884 .clkr.hw.init = &(const struct clk_init_data) { 2885 .name = "gcc_pcie_4_pipe_div_clk_src", 2886 .parent_hws = (const struct clk_hw*[]) { 2887 &gcc_pcie_4_pipe_clk_src.clkr.hw, 2888 }, 2889 .num_parents = 1, 2890 .flags = CLK_SET_RATE_PARENT, 2891 .ops = &clk_regmap_div_ro_ops, 2892 }, 2893 }; 2894 2895 static struct clk_regmap_div gcc_pcie_5_pipe_div_clk_src = { 2896 .reg = 0xc306c, 2897 .shift = 0, 2898 .width = 4, 2899 .clkr.hw.init = &(const struct clk_init_data) { 2900 .name = "gcc_pcie_5_pipe_div_clk_src", 2901 .parent_hws = (const struct clk_hw*[]) { 2902 &gcc_pcie_5_pipe_clk_src.clkr.hw, 2903 }, 2904 .num_parents = 1, 2905 .flags = CLK_SET_RATE_PARENT, 2906 .ops = &clk_regmap_div_ro_ops, 2907 }, 2908 }; 2909 2910 static struct clk_regmap_div gcc_pcie_6_pipe_div_clk_src = { 2911 .reg = 0x8a060, 2912 .shift = 0, 2913 .width = 4, 2914 .clkr.hw.init = &(const struct clk_init_data) { 2915 .name = "gcc_pcie_6_pipe_div_clk_src", 2916 .parent_hws = (const struct clk_hw*[]) { 2917 &gcc_pcie_6_pipe_clk_src.clkr.hw, 2918 }, 2919 .num_parents = 1, 2920 .flags = CLK_SET_RATE_PARENT, 2921 .ops = &clk_regmap_div_ro_ops, 2922 }, 2923 }; 2924 2925 static struct clk_regmap_div gcc_qupv3_oob_s0_clk_src = { 2926 .reg = 0xe7024, 2927 .shift = 0, 2928 .width = 4, 2929 .clkr.hw.init = &(const struct clk_init_data) { 2930 .name = "gcc_qupv3_oob_s0_clk_src", 2931 .parent_hws = (const struct clk_hw*[]) { 2932 &gcc_qupv3_oob_qspi_s0_clk_src.clkr.hw, 2933 }, 2934 .num_parents = 1, 2935 .flags = CLK_SET_RATE_PARENT, 2936 .ops = &clk_regmap_div_ro_ops, 2937 }, 2938 }; 2939 2940 static struct clk_regmap_div gcc_qupv3_oob_s1_clk_src = { 2941 .reg = 0xe7038, 2942 .shift = 0, 2943 .width = 4, 2944 .clkr.hw.init = &(const struct clk_init_data) { 2945 .name = "gcc_qupv3_oob_s1_clk_src", 2946 .parent_hws = (const struct clk_hw*[]) { 2947 &gcc_qupv3_oob_qspi_s1_clk_src.clkr.hw, 2948 }, 2949 .num_parents = 1, 2950 .flags = CLK_SET_RATE_PARENT, 2951 .ops = &clk_regmap_div_ro_ops, 2952 }, 2953 }; 2954 2955 static struct clk_regmap_div gcc_qupv3_wrap0_s2_clk_src = { 2956 .reg = 0x2828c, 2957 .shift = 0, 2958 .width = 4, 2959 .clkr.hw.init = &(const struct clk_init_data) { 2960 .name = "gcc_qupv3_wrap0_s2_clk_src", 2961 .parent_hws = (const struct clk_hw*[]) { 2962 &gcc_qupv3_wrap0_qspi_s2_clk_src.clkr.hw, 2963 }, 2964 .num_parents = 1, 2965 .flags = CLK_SET_RATE_PARENT, 2966 .ops = &clk_regmap_div_ro_ops, 2967 }, 2968 }; 2969 2970 static struct clk_regmap_div gcc_qupv3_wrap0_s3_clk_src = { 2971 .reg = 0x282a0, 2972 .shift = 0, 2973 .width = 4, 2974 .clkr.hw.init = &(const struct clk_init_data) { 2975 .name = "gcc_qupv3_wrap0_s3_clk_src", 2976 .parent_hws = (const struct clk_hw*[]) { 2977 &gcc_qupv3_wrap0_qspi_s3_clk_src.clkr.hw, 2978 }, 2979 .num_parents = 1, 2980 .flags = CLK_SET_RATE_PARENT, 2981 .ops = &clk_regmap_div_ro_ops, 2982 }, 2983 }; 2984 2985 static struct clk_regmap_div gcc_qupv3_wrap0_s6_clk_src = { 2986 .reg = 0x2852c, 2987 .shift = 0, 2988 .width = 4, 2989 .clkr.hw.init = &(const struct clk_init_data) { 2990 .name = "gcc_qupv3_wrap0_s6_clk_src", 2991 .parent_hws = (const struct clk_hw*[]) { 2992 &gcc_qupv3_wrap0_qspi_s6_clk_src.clkr.hw, 2993 }, 2994 .num_parents = 1, 2995 .flags = CLK_SET_RATE_PARENT, 2996 .ops = &clk_regmap_div_ro_ops, 2997 }, 2998 }; 2999 3000 static struct clk_regmap_div gcc_qupv3_wrap1_s2_clk_src = { 3001 .reg = 0xb328c, 3002 .shift = 0, 3003 .width = 4, 3004 .clkr.hw.init = &(const struct clk_init_data) { 3005 .name = "gcc_qupv3_wrap1_s2_clk_src", 3006 .parent_hws = (const struct clk_hw*[]) { 3007 &gcc_qupv3_wrap1_qspi_s2_clk_src.clkr.hw, 3008 }, 3009 .num_parents = 1, 3010 .flags = CLK_SET_RATE_PARENT, 3011 .ops = &clk_regmap_div_ro_ops, 3012 }, 3013 }; 3014 3015 static struct clk_regmap_div gcc_qupv3_wrap1_s3_clk_src = { 3016 .reg = 0xb32a0, 3017 .shift = 0, 3018 .width = 4, 3019 .clkr.hw.init = &(const struct clk_init_data) { 3020 .name = "gcc_qupv3_wrap1_s3_clk_src", 3021 .parent_hws = (const struct clk_hw*[]) { 3022 &gcc_qupv3_wrap1_qspi_s3_clk_src.clkr.hw, 3023 }, 3024 .num_parents = 1, 3025 .flags = CLK_SET_RATE_PARENT, 3026 .ops = &clk_regmap_div_ro_ops, 3027 }, 3028 }; 3029 3030 static struct clk_regmap_div gcc_qupv3_wrap1_s6_clk_src = { 3031 .reg = 0xb352c, 3032 .shift = 0, 3033 .width = 4, 3034 .clkr.hw.init = &(const struct clk_init_data) { 3035 .name = "gcc_qupv3_wrap1_s6_clk_src", 3036 .parent_hws = (const struct clk_hw*[]) { 3037 &gcc_qupv3_wrap1_qspi_s6_clk_src.clkr.hw, 3038 }, 3039 .num_parents = 1, 3040 .flags = CLK_SET_RATE_PARENT, 3041 .ops = &clk_regmap_div_ro_ops, 3042 }, 3043 }; 3044 3045 static struct clk_regmap_div gcc_qupv3_wrap2_s2_clk_src = { 3046 .reg = 0xb428c, 3047 .shift = 0, 3048 .width = 4, 3049 .clkr.hw.init = &(const struct clk_init_data) { 3050 .name = "gcc_qupv3_wrap2_s2_clk_src", 3051 .parent_hws = (const struct clk_hw*[]) { 3052 &gcc_qupv3_wrap2_qspi_s2_clk_src.clkr.hw, 3053 }, 3054 .num_parents = 1, 3055 .flags = CLK_SET_RATE_PARENT, 3056 .ops = &clk_regmap_div_ro_ops, 3057 }, 3058 }; 3059 3060 static struct clk_regmap_div gcc_qupv3_wrap2_s3_clk_src = { 3061 .reg = 0xb42a0, 3062 .shift = 0, 3063 .width = 4, 3064 .clkr.hw.init = &(const struct clk_init_data) { 3065 .name = "gcc_qupv3_wrap2_s3_clk_src", 3066 .parent_hws = (const struct clk_hw*[]) { 3067 &gcc_qupv3_wrap2_qspi_s3_clk_src.clkr.hw, 3068 }, 3069 .num_parents = 1, 3070 .flags = CLK_SET_RATE_PARENT, 3071 .ops = &clk_regmap_div_ro_ops, 3072 }, 3073 }; 3074 3075 static struct clk_regmap_div gcc_qupv3_wrap2_s6_clk_src = { 3076 .reg = 0xb452c, 3077 .shift = 0, 3078 .width = 4, 3079 .clkr.hw.init = &(const struct clk_init_data) { 3080 .name = "gcc_qupv3_wrap2_s6_clk_src", 3081 .parent_hws = (const struct clk_hw*[]) { 3082 &gcc_qupv3_wrap2_qspi_s6_clk_src.clkr.hw, 3083 }, 3084 .num_parents = 1, 3085 .flags = CLK_SET_RATE_PARENT, 3086 .ops = &clk_regmap_div_ro_ops, 3087 }, 3088 }; 3089 3090 static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src = { 3091 .reg = 0xbc174, 3092 .shift = 0, 3093 .width = 4, 3094 .clkr.hw.init = &(const struct clk_init_data) { 3095 .name = "gcc_usb20_mock_utmi_postdiv_clk_src", 3096 .parent_hws = (const struct clk_hw*[]) { 3097 &gcc_usb20_mock_utmi_clk_src.clkr.hw, 3098 }, 3099 .num_parents = 1, 3100 .flags = CLK_SET_RATE_PARENT, 3101 .ops = &clk_regmap_div_ro_ops, 3102 }, 3103 }; 3104 3105 static struct clk_regmap_div gcc_usb30_mp_mock_utmi_postdiv_clk_src = { 3106 .reg = 0x9a06c, 3107 .shift = 0, 3108 .width = 4, 3109 .clkr.hw.init = &(const struct clk_init_data) { 3110 .name = "gcc_usb30_mp_mock_utmi_postdiv_clk_src", 3111 .parent_hws = (const struct clk_hw*[]) { 3112 &gcc_usb30_mp_mock_utmi_clk_src.clkr.hw, 3113 }, 3114 .num_parents = 1, 3115 .flags = CLK_SET_RATE_PARENT, 3116 .ops = &clk_regmap_div_ro_ops, 3117 }, 3118 }; 3119 3120 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 3121 .reg = 0x3f07c, 3122 .shift = 0, 3123 .width = 4, 3124 .clkr.hw.init = &(const struct clk_init_data) { 3125 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 3126 .parent_hws = (const struct clk_hw*[]) { 3127 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 3128 }, 3129 .num_parents = 1, 3130 .flags = CLK_SET_RATE_PARENT, 3131 .ops = &clk_regmap_div_ro_ops, 3132 }, 3133 }; 3134 3135 static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = { 3136 .reg = 0xe206c, 3137 .shift = 0, 3138 .width = 4, 3139 .clkr.hw.init = &(const struct clk_init_data) { 3140 .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src", 3141 .parent_hws = (const struct clk_hw*[]) { 3142 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, 3143 }, 3144 .num_parents = 1, 3145 .flags = CLK_SET_RATE_PARENT, 3146 .ops = &clk_regmap_div_ro_ops, 3147 }, 3148 }; 3149 3150 static struct clk_regmap_div gcc_usb30_tert_mock_utmi_postdiv_clk_src = { 3151 .reg = 0xe106c, 3152 .shift = 0, 3153 .width = 4, 3154 .clkr.hw.init = &(const struct clk_init_data) { 3155 .name = "gcc_usb30_tert_mock_utmi_postdiv_clk_src", 3156 .parent_hws = (const struct clk_hw*[]) { 3157 &gcc_usb30_tert_mock_utmi_clk_src.clkr.hw, 3158 }, 3159 .num_parents = 1, 3160 .flags = CLK_SET_RATE_PARENT, 3161 .ops = &clk_regmap_div_ro_ops, 3162 }, 3163 }; 3164 3165 static struct clk_branch gcc_aggre_noc_pcie_3a_west_sf_axi_clk = { 3166 .halt_reg = 0xdc0bc, 3167 .halt_check = BRANCH_HALT_VOTED, 3168 .clkr = { 3169 .enable_reg = 0x62008, 3170 .enable_mask = BIT(27), 3171 .hw.init = &(const struct clk_init_data) { 3172 .name = "gcc_aggre_noc_pcie_3a_west_sf_axi_clk", 3173 .ops = &clk_branch2_ops, 3174 }, 3175 }, 3176 }; 3177 3178 static struct clk_branch gcc_aggre_noc_pcie_3b_west_sf_axi_clk = { 3179 .halt_reg = 0x941ec, 3180 .halt_check = BRANCH_HALT_VOTED, 3181 .clkr = { 3182 .enable_reg = 0x62008, 3183 .enable_mask = BIT(28), 3184 .hw.init = &(const struct clk_init_data) { 3185 .name = "gcc_aggre_noc_pcie_3b_west_sf_axi_clk", 3186 .ops = &clk_branch2_ops, 3187 }, 3188 }, 3189 }; 3190 3191 static struct clk_branch gcc_aggre_noc_pcie_4_west_sf_axi_clk = { 3192 .halt_reg = 0x881d0, 3193 .halt_check = BRANCH_HALT_VOTED, 3194 .clkr = { 3195 .enable_reg = 0x62008, 3196 .enable_mask = BIT(29), 3197 .hw.init = &(const struct clk_init_data) { 3198 .name = "gcc_aggre_noc_pcie_4_west_sf_axi_clk", 3199 .ops = &clk_branch2_ops, 3200 }, 3201 }, 3202 }; 3203 3204 static struct clk_branch gcc_aggre_noc_pcie_5_east_sf_axi_clk = { 3205 .halt_reg = 0xc30d0, 3206 .halt_check = BRANCH_HALT_VOTED, 3207 .clkr = { 3208 .enable_reg = 0x62008, 3209 .enable_mask = BIT(30), 3210 .hw.init = &(const struct clk_init_data) { 3211 .name = "gcc_aggre_noc_pcie_5_east_sf_axi_clk", 3212 .ops = &clk_branch2_ops, 3213 }, 3214 }, 3215 }; 3216 3217 static struct clk_branch gcc_aggre_noc_pcie_6_west_sf_axi_clk = { 3218 .halt_reg = 0x8a1d0, 3219 .halt_check = BRANCH_HALT_VOTED, 3220 .clkr = { 3221 .enable_reg = 0x62008, 3222 .enable_mask = BIT(31), 3223 .hw.init = &(const struct clk_init_data) { 3224 .name = "gcc_aggre_noc_pcie_6_west_sf_axi_clk", 3225 .ops = &clk_branch2_ops, 3226 }, 3227 }, 3228 }; 3229 3230 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 3231 .halt_reg = 0x77000, 3232 .halt_check = BRANCH_HALT_VOTED, 3233 .hwcg_reg = 0x77000, 3234 .hwcg_bit = 1, 3235 .clkr = { 3236 .enable_reg = 0x77000, 3237 .enable_mask = BIT(0), 3238 .hw.init = &(const struct clk_init_data) { 3239 .name = "gcc_aggre_ufs_phy_axi_clk", 3240 .parent_hws = (const struct clk_hw*[]) { 3241 &gcc_ufs_phy_axi_clk_src.clkr.hw, 3242 }, 3243 .num_parents = 1, 3244 .flags = CLK_SET_RATE_PARENT, 3245 .ops = &clk_branch2_ops, 3246 }, 3247 }, 3248 }; 3249 3250 static struct clk_branch gcc_aggre_usb2_prim_axi_clk = { 3251 .halt_reg = 0xbc17c, 3252 .halt_check = BRANCH_HALT_VOTED, 3253 .hwcg_reg = 0xbc17c, 3254 .hwcg_bit = 1, 3255 .clkr = { 3256 .enable_reg = 0xbc17c, 3257 .enable_mask = BIT(0), 3258 .hw.init = &(const struct clk_init_data) { 3259 .name = "gcc_aggre_usb2_prim_axi_clk", 3260 .parent_hws = (const struct clk_hw*[]) { 3261 &gcc_usb20_master_clk_src.clkr.hw, 3262 }, 3263 .num_parents = 1, 3264 .flags = CLK_SET_RATE_PARENT, 3265 .ops = &clk_branch2_ops, 3266 }, 3267 }, 3268 }; 3269 3270 static struct clk_branch gcc_aggre_usb3_mp_axi_clk = { 3271 .halt_reg = 0x9a004, 3272 .halt_check = BRANCH_HALT_VOTED, 3273 .hwcg_reg = 0x9a004, 3274 .hwcg_bit = 1, 3275 .clkr = { 3276 .enable_reg = 0x9a004, 3277 .enable_mask = BIT(0), 3278 .hw.init = &(const struct clk_init_data) { 3279 .name = "gcc_aggre_usb3_mp_axi_clk", 3280 .parent_hws = (const struct clk_hw*[]) { 3281 &gcc_usb30_mp_master_clk_src.clkr.hw, 3282 }, 3283 .num_parents = 1, 3284 .flags = CLK_SET_RATE_PARENT, 3285 .ops = &clk_branch2_ops, 3286 }, 3287 }, 3288 }; 3289 3290 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 3291 .halt_reg = 0x3f00c, 3292 .halt_check = BRANCH_HALT_VOTED, 3293 .hwcg_reg = 0x3f00c, 3294 .hwcg_bit = 1, 3295 .clkr = { 3296 .enable_reg = 0x3f00c, 3297 .enable_mask = BIT(0), 3298 .hw.init = &(const struct clk_init_data) { 3299 .name = "gcc_aggre_usb3_prim_axi_clk", 3300 .parent_hws = (const struct clk_hw*[]) { 3301 &gcc_usb30_prim_master_clk_src.clkr.hw, 3302 }, 3303 .num_parents = 1, 3304 .flags = CLK_SET_RATE_PARENT, 3305 .ops = &clk_branch2_ops, 3306 }, 3307 }, 3308 }; 3309 3310 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { 3311 .halt_reg = 0xe2004, 3312 .halt_check = BRANCH_HALT_VOTED, 3313 .hwcg_reg = 0xe2004, 3314 .hwcg_bit = 1, 3315 .clkr = { 3316 .enable_reg = 0xe2004, 3317 .enable_mask = BIT(0), 3318 .hw.init = &(const struct clk_init_data) { 3319 .name = "gcc_aggre_usb3_sec_axi_clk", 3320 .parent_hws = (const struct clk_hw*[]) { 3321 &gcc_usb30_sec_master_clk_src.clkr.hw, 3322 }, 3323 .num_parents = 1, 3324 .flags = CLK_SET_RATE_PARENT, 3325 .ops = &clk_branch2_ops, 3326 }, 3327 }, 3328 }; 3329 3330 static struct clk_branch gcc_aggre_usb3_tert_axi_clk = { 3331 .halt_reg = 0xe1004, 3332 .halt_check = BRANCH_HALT_VOTED, 3333 .hwcg_reg = 0xe1004, 3334 .hwcg_bit = 1, 3335 .clkr = { 3336 .enable_reg = 0xe1004, 3337 .enable_mask = BIT(0), 3338 .hw.init = &(const struct clk_init_data) { 3339 .name = "gcc_aggre_usb3_tert_axi_clk", 3340 .parent_hws = (const struct clk_hw*[]) { 3341 &gcc_usb30_tert_master_clk_src.clkr.hw, 3342 }, 3343 .num_parents = 1, 3344 .flags = CLK_SET_RATE_PARENT, 3345 .ops = &clk_branch2_ops, 3346 }, 3347 }, 3348 }; 3349 3350 static struct clk_branch gcc_aggre_usb4_0_axi_clk = { 3351 .halt_reg = 0x2b000, 3352 .halt_check = BRANCH_HALT_VOTED, 3353 .hwcg_reg = 0x2b000, 3354 .hwcg_bit = 1, 3355 .clkr = { 3356 .enable_reg = 0x2b000, 3357 .enable_mask = BIT(0), 3358 .hw.init = &(const struct clk_init_data) { 3359 .name = "gcc_aggre_usb4_0_axi_clk", 3360 .parent_hws = (const struct clk_hw*[]) { 3361 &gcc_usb4_0_master_clk_src.clkr.hw, 3362 }, 3363 .num_parents = 1, 3364 .flags = CLK_SET_RATE_PARENT, 3365 .ops = &clk_branch2_ops, 3366 }, 3367 }, 3368 }; 3369 3370 static struct clk_branch gcc_aggre_usb4_1_axi_clk = { 3371 .halt_reg = 0x2d000, 3372 .halt_check = BRANCH_HALT_VOTED, 3373 .hwcg_reg = 0x2d000, 3374 .hwcg_bit = 1, 3375 .clkr = { 3376 .enable_reg = 0x2d000, 3377 .enable_mask = BIT(0), 3378 .hw.init = &(const struct clk_init_data) { 3379 .name = "gcc_aggre_usb4_1_axi_clk", 3380 .parent_hws = (const struct clk_hw*[]) { 3381 &gcc_usb4_1_master_clk_src.clkr.hw, 3382 }, 3383 .num_parents = 1, 3384 .flags = CLK_SET_RATE_PARENT, 3385 .ops = &clk_branch2_ops, 3386 }, 3387 }, 3388 }; 3389 3390 static struct clk_branch gcc_aggre_usb4_2_axi_clk = { 3391 .halt_reg = 0xe0000, 3392 .halt_check = BRANCH_HALT_VOTED, 3393 .hwcg_reg = 0xe0000, 3394 .hwcg_bit = 1, 3395 .clkr = { 3396 .enable_reg = 0xe0000, 3397 .enable_mask = BIT(0), 3398 .hw.init = &(const struct clk_init_data) { 3399 .name = "gcc_aggre_usb4_2_axi_clk", 3400 .parent_hws = (const struct clk_hw*[]) { 3401 &gcc_usb4_2_master_clk_src.clkr.hw, 3402 }, 3403 .num_parents = 1, 3404 .flags = CLK_SET_RATE_PARENT, 3405 .ops = &clk_branch2_ops, 3406 }, 3407 }, 3408 }; 3409 3410 static struct clk_branch gcc_av1e_ahb_clk = { 3411 .halt_reg = 0x9b02c, 3412 .halt_check = BRANCH_HALT_VOTED, 3413 .hwcg_reg = 0x9b02c, 3414 .hwcg_bit = 1, 3415 .clkr = { 3416 .enable_reg = 0x9b02c, 3417 .enable_mask = BIT(0), 3418 .hw.init = &(const struct clk_init_data) { 3419 .name = "gcc_av1e_ahb_clk", 3420 .ops = &clk_branch2_ops, 3421 }, 3422 }, 3423 }; 3424 3425 static struct clk_branch gcc_av1e_axi_clk = { 3426 .halt_reg = 0x9b030, 3427 .halt_check = BRANCH_HALT_SKIP, 3428 .hwcg_reg = 0x9b030, 3429 .hwcg_bit = 1, 3430 .clkr = { 3431 .enable_reg = 0x9b030, 3432 .enable_mask = BIT(0), 3433 .hw.init = &(const struct clk_init_data) { 3434 .name = "gcc_av1e_axi_clk", 3435 .ops = &clk_branch2_ops, 3436 }, 3437 }, 3438 }; 3439 3440 static struct clk_branch gcc_av1e_xo_clk = { 3441 .halt_reg = 0x9b044, 3442 .halt_check = BRANCH_HALT, 3443 .clkr = { 3444 .enable_reg = 0x9b044, 3445 .enable_mask = BIT(0), 3446 .hw.init = &(const struct clk_init_data) { 3447 .name = "gcc_av1e_xo_clk", 3448 .ops = &clk_branch2_ops, 3449 }, 3450 }, 3451 }; 3452 3453 static struct clk_branch gcc_boot_rom_ahb_clk = { 3454 .halt_reg = 0x34038, 3455 .halt_check = BRANCH_HALT_VOTED, 3456 .hwcg_reg = 0x34038, 3457 .hwcg_bit = 1, 3458 .clkr = { 3459 .enable_reg = 0x62020, 3460 .enable_mask = BIT(27), 3461 .hw.init = &(const struct clk_init_data) { 3462 .name = "gcc_boot_rom_ahb_clk", 3463 .ops = &clk_branch2_ops, 3464 }, 3465 }, 3466 }; 3467 3468 static struct clk_branch gcc_camera_hf_axi_clk = { 3469 .halt_reg = 0x26014, 3470 .halt_check = BRANCH_HALT_SKIP, 3471 .hwcg_reg = 0x26014, 3472 .hwcg_bit = 1, 3473 .clkr = { 3474 .enable_reg = 0x26014, 3475 .enable_mask = BIT(0), 3476 .hw.init = &(const struct clk_init_data) { 3477 .name = "gcc_camera_hf_axi_clk", 3478 .ops = &clk_branch2_ops, 3479 }, 3480 }, 3481 }; 3482 3483 static struct clk_branch gcc_camera_sf_axi_clk = { 3484 .halt_reg = 0x26028, 3485 .halt_check = BRANCH_HALT_SKIP, 3486 .hwcg_reg = 0x26028, 3487 .hwcg_bit = 1, 3488 .clkr = { 3489 .enable_reg = 0x26028, 3490 .enable_mask = BIT(0), 3491 .hw.init = &(const struct clk_init_data) { 3492 .name = "gcc_camera_sf_axi_clk", 3493 .ops = &clk_branch2_ops, 3494 }, 3495 }, 3496 }; 3497 3498 static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = { 3499 .halt_reg = 0x82004, 3500 .halt_check = BRANCH_HALT_VOTED, 3501 .hwcg_reg = 0x82004, 3502 .hwcg_bit = 1, 3503 .clkr = { 3504 .enable_reg = 0x62008, 3505 .enable_mask = BIT(19), 3506 .hw.init = &(const struct clk_init_data) { 3507 .name = "gcc_cfg_noc_pcie_anoc_ahb_clk", 3508 .ops = &clk_branch2_ops, 3509 }, 3510 }, 3511 }; 3512 3513 static struct clk_branch gcc_cfg_noc_pcie_anoc_south_ahb_clk = { 3514 .halt_reg = 0xba2ec, 3515 .halt_check = BRANCH_HALT_VOTED, 3516 .hwcg_reg = 0xba2ec, 3517 .hwcg_bit = 1, 3518 .clkr = { 3519 .enable_reg = 0x62008, 3520 .enable_mask = BIT(16), 3521 .hw.init = &(const struct clk_init_data) { 3522 .name = "gcc_cfg_noc_pcie_anoc_south_ahb_clk", 3523 .ops = &clk_branch2_ops, 3524 }, 3525 }, 3526 }; 3527 3528 static struct clk_branch gcc_cfg_noc_usb2_prim_axi_clk = { 3529 .halt_reg = 0xbc178, 3530 .halt_check = BRANCH_HALT_VOTED, 3531 .hwcg_reg = 0xbc178, 3532 .hwcg_bit = 1, 3533 .clkr = { 3534 .enable_reg = 0xbc178, 3535 .enable_mask = BIT(0), 3536 .hw.init = &(const struct clk_init_data) { 3537 .name = "gcc_cfg_noc_usb2_prim_axi_clk", 3538 .parent_hws = (const struct clk_hw*[]) { 3539 &gcc_usb20_master_clk_src.clkr.hw, 3540 }, 3541 .num_parents = 1, 3542 .flags = CLK_SET_RATE_PARENT, 3543 .ops = &clk_branch2_ops, 3544 }, 3545 }, 3546 }; 3547 3548 static struct clk_branch gcc_cfg_noc_usb3_mp_axi_clk = { 3549 .halt_reg = 0x9a000, 3550 .halt_check = BRANCH_HALT_VOTED, 3551 .hwcg_reg = 0x9a000, 3552 .hwcg_bit = 1, 3553 .clkr = { 3554 .enable_reg = 0x9a000, 3555 .enable_mask = BIT(0), 3556 .hw.init = &(const struct clk_init_data) { 3557 .name = "gcc_cfg_noc_usb3_mp_axi_clk", 3558 .parent_hws = (const struct clk_hw*[]) { 3559 &gcc_usb30_mp_master_clk_src.clkr.hw, 3560 }, 3561 .num_parents = 1, 3562 .flags = CLK_SET_RATE_PARENT, 3563 .ops = &clk_branch2_ops, 3564 }, 3565 }, 3566 }; 3567 3568 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 3569 .halt_reg = 0x3f000, 3570 .halt_check = BRANCH_HALT_VOTED, 3571 .hwcg_reg = 0x3f000, 3572 .hwcg_bit = 1, 3573 .clkr = { 3574 .enable_reg = 0x3f000, 3575 .enable_mask = BIT(0), 3576 .hw.init = &(const struct clk_init_data) { 3577 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 3578 .parent_hws = (const struct clk_hw*[]) { 3579 &gcc_usb30_prim_master_clk_src.clkr.hw, 3580 }, 3581 .num_parents = 1, 3582 .flags = CLK_SET_RATE_PARENT, 3583 .ops = &clk_branch2_ops, 3584 }, 3585 }, 3586 }; 3587 3588 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { 3589 .halt_reg = 0xe2000, 3590 .halt_check = BRANCH_HALT_VOTED, 3591 .hwcg_reg = 0xe2000, 3592 .hwcg_bit = 1, 3593 .clkr = { 3594 .enable_reg = 0xe2000, 3595 .enable_mask = BIT(0), 3596 .hw.init = &(const struct clk_init_data) { 3597 .name = "gcc_cfg_noc_usb3_sec_axi_clk", 3598 .parent_hws = (const struct clk_hw*[]) { 3599 &gcc_usb30_sec_master_clk_src.clkr.hw, 3600 }, 3601 .num_parents = 1, 3602 .flags = CLK_SET_RATE_PARENT, 3603 .ops = &clk_branch2_ops, 3604 }, 3605 }, 3606 }; 3607 3608 static struct clk_branch gcc_cfg_noc_usb3_tert_axi_clk = { 3609 .halt_reg = 0xe1000, 3610 .halt_check = BRANCH_HALT_VOTED, 3611 .hwcg_reg = 0xe1000, 3612 .hwcg_bit = 1, 3613 .clkr = { 3614 .enable_reg = 0xe1000, 3615 .enable_mask = BIT(0), 3616 .hw.init = &(const struct clk_init_data) { 3617 .name = "gcc_cfg_noc_usb3_tert_axi_clk", 3618 .parent_hws = (const struct clk_hw*[]) { 3619 &gcc_usb30_tert_master_clk_src.clkr.hw, 3620 }, 3621 .num_parents = 1, 3622 .flags = CLK_SET_RATE_PARENT, 3623 .ops = &clk_branch2_ops, 3624 }, 3625 }, 3626 }; 3627 3628 static struct clk_branch gcc_cfg_noc_usb_anoc_ahb_clk = { 3629 .halt_reg = 0x3f004, 3630 .halt_check = BRANCH_HALT_VOTED, 3631 .hwcg_reg = 0x3f004, 3632 .hwcg_bit = 1, 3633 .clkr = { 3634 .enable_reg = 0x62008, 3635 .enable_mask = BIT(17), 3636 .hw.init = &(const struct clk_init_data) { 3637 .name = "gcc_cfg_noc_usb_anoc_ahb_clk", 3638 .ops = &clk_branch2_ops, 3639 }, 3640 }, 3641 }; 3642 3643 static struct clk_branch gcc_cfg_noc_usb_anoc_south_ahb_clk = { 3644 .halt_reg = 0x3f008, 3645 .halt_check = BRANCH_HALT_VOTED, 3646 .hwcg_reg = 0x3f008, 3647 .hwcg_bit = 1, 3648 .clkr = { 3649 .enable_reg = 0x62008, 3650 .enable_mask = BIT(18), 3651 .hw.init = &(const struct clk_init_data) { 3652 .name = "gcc_cfg_noc_usb_anoc_south_ahb_clk", 3653 .ops = &clk_branch2_ops, 3654 }, 3655 }, 3656 }; 3657 3658 static struct clk_branch gcc_disp_hf_axi_clk = { 3659 .halt_reg = 0x27008, 3660 .halt_check = BRANCH_HALT_SKIP, 3661 .clkr = { 3662 .enable_reg = 0x27008, 3663 .enable_mask = BIT(0), 3664 .hw.init = &(const struct clk_init_data) { 3665 .name = "gcc_disp_hf_axi_clk", 3666 .ops = &clk_branch2_ops, 3667 .flags = CLK_IS_CRITICAL, 3668 }, 3669 }, 3670 }; 3671 3672 static struct clk_branch gcc_eva_ahb_clk = { 3673 .halt_reg = 0x9b004, 3674 .halt_check = BRANCH_HALT_VOTED, 3675 .hwcg_reg = 0x9b004, 3676 .hwcg_bit = 1, 3677 .clkr = { 3678 .enable_reg = 0x9b004, 3679 .enable_mask = BIT(0), 3680 .hw.init = &(const struct clk_init_data) { 3681 .name = "gcc_eva_ahb_clk", 3682 .ops = &clk_branch2_ops, 3683 }, 3684 }, 3685 }; 3686 3687 static struct clk_branch gcc_eva_axi0_clk = { 3688 .halt_reg = 0x9b008, 3689 .halt_check = BRANCH_HALT_SKIP, 3690 .hwcg_reg = 0x9b008, 3691 .hwcg_bit = 1, 3692 .clkr = { 3693 .enable_reg = 0x9b008, 3694 .enable_mask = BIT(0), 3695 .hw.init = &(const struct clk_init_data) { 3696 .name = "gcc_eva_axi0_clk", 3697 .ops = &clk_branch2_ops, 3698 }, 3699 }, 3700 }; 3701 3702 static struct clk_branch gcc_eva_axi0c_clk = { 3703 .halt_reg = 0x9b01c, 3704 .halt_check = BRANCH_HALT_VOTED, 3705 .hwcg_reg = 0x9b01c, 3706 .hwcg_bit = 1, 3707 .clkr = { 3708 .enable_reg = 0x9b01c, 3709 .enable_mask = BIT(0), 3710 .hw.init = &(const struct clk_init_data) { 3711 .name = "gcc_eva_axi0c_clk", 3712 .ops = &clk_branch2_ops, 3713 }, 3714 }, 3715 }; 3716 3717 static struct clk_branch gcc_eva_xo_clk = { 3718 .halt_reg = 0x9b024, 3719 .halt_check = BRANCH_HALT, 3720 .clkr = { 3721 .enable_reg = 0x9b024, 3722 .enable_mask = BIT(0), 3723 .hw.init = &(const struct clk_init_data) { 3724 .name = "gcc_eva_xo_clk", 3725 .ops = &clk_branch2_ops, 3726 }, 3727 }, 3728 }; 3729 3730 static struct clk_branch gcc_gp1_clk = { 3731 .halt_reg = 0x64000, 3732 .halt_check = BRANCH_HALT, 3733 .clkr = { 3734 .enable_reg = 0x64000, 3735 .enable_mask = BIT(0), 3736 .hw.init = &(const struct clk_init_data) { 3737 .name = "gcc_gp1_clk", 3738 .parent_hws = (const struct clk_hw*[]) { 3739 &gcc_gp1_clk_src.clkr.hw, 3740 }, 3741 .num_parents = 1, 3742 .flags = CLK_SET_RATE_PARENT, 3743 .ops = &clk_branch2_ops, 3744 }, 3745 }, 3746 }; 3747 3748 static struct clk_branch gcc_gp2_clk = { 3749 .halt_reg = 0x92000, 3750 .halt_check = BRANCH_HALT, 3751 .clkr = { 3752 .enable_reg = 0x92000, 3753 .enable_mask = BIT(0), 3754 .hw.init = &(const struct clk_init_data) { 3755 .name = "gcc_gp2_clk", 3756 .parent_hws = (const struct clk_hw*[]) { 3757 &gcc_gp2_clk_src.clkr.hw, 3758 }, 3759 .num_parents = 1, 3760 .flags = CLK_SET_RATE_PARENT, 3761 .ops = &clk_branch2_ops, 3762 }, 3763 }, 3764 }; 3765 3766 static struct clk_branch gcc_gp3_clk = { 3767 .halt_reg = 0x93000, 3768 .halt_check = BRANCH_HALT, 3769 .clkr = { 3770 .enable_reg = 0x93000, 3771 .enable_mask = BIT(0), 3772 .hw.init = &(const struct clk_init_data) { 3773 .name = "gcc_gp3_clk", 3774 .parent_hws = (const struct clk_hw*[]) { 3775 &gcc_gp3_clk_src.clkr.hw, 3776 }, 3777 .num_parents = 1, 3778 .flags = CLK_SET_RATE_PARENT, 3779 .ops = &clk_branch2_ops, 3780 }, 3781 }, 3782 }; 3783 3784 static struct clk_branch gcc_gpu_gemnoc_gfx_clk = { 3785 .halt_reg = 0x71010, 3786 .halt_check = BRANCH_HALT_VOTED, 3787 .hwcg_reg = 0x71010, 3788 .hwcg_bit = 1, 3789 .clkr = { 3790 .enable_reg = 0x71010, 3791 .enable_mask = BIT(0), 3792 .hw.init = &(const struct clk_init_data) { 3793 .name = "gcc_gpu_gemnoc_gfx_clk", 3794 .ops = &clk_branch2_ops, 3795 }, 3796 }, 3797 }; 3798 3799 static struct clk_branch gcc_gpu_gpll0_clk_src = { 3800 .halt_reg = 0x71024, 3801 .halt_check = BRANCH_HALT_VOTED, 3802 .hwcg_reg = 0x71024, 3803 .hwcg_bit = 1, 3804 .clkr = { 3805 .enable_reg = 0x62038, 3806 .enable_mask = BIT(0), 3807 .hw.init = &(const struct clk_init_data) { 3808 .name = "gcc_gpu_gpll0_clk_src", 3809 .parent_hws = (const struct clk_hw*[]) { 3810 &gcc_gpll0.clkr.hw, 3811 }, 3812 .num_parents = 1, 3813 .flags = CLK_SET_RATE_PARENT, 3814 .ops = &clk_branch2_ops, 3815 }, 3816 }, 3817 }; 3818 3819 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 3820 .halt_reg = 0x7102c, 3821 .halt_check = BRANCH_HALT_VOTED, 3822 .hwcg_reg = 0x7102c, 3823 .hwcg_bit = 1, 3824 .clkr = { 3825 .enable_reg = 0x62038, 3826 .enable_mask = BIT(1), 3827 .hw.init = &(const struct clk_init_data) { 3828 .name = "gcc_gpu_gpll0_div_clk_src", 3829 .parent_hws = (const struct clk_hw*[]) { 3830 &gcc_gpll0_out_even.clkr.hw, 3831 }, 3832 .num_parents = 1, 3833 .flags = CLK_SET_RATE_PARENT, 3834 .ops = &clk_branch2_ops, 3835 }, 3836 }, 3837 }; 3838 3839 static struct clk_branch gcc_pcie_0_aux_clk = { 3840 .halt_reg = 0xc8018, 3841 .halt_check = BRANCH_HALT_VOTED, 3842 .clkr = { 3843 .enable_reg = 0x62010, 3844 .enable_mask = BIT(25), 3845 .hw.init = &(const struct clk_init_data) { 3846 .name = "gcc_pcie_0_aux_clk", 3847 .parent_hws = (const struct clk_hw*[]) { 3848 &gcc_pcie_0_aux_clk_src.clkr.hw, 3849 }, 3850 .num_parents = 1, 3851 .flags = CLK_SET_RATE_PARENT, 3852 .ops = &clk_branch2_ops, 3853 }, 3854 }, 3855 }; 3856 3857 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 3858 .halt_reg = 0xba4a8, 3859 .halt_check = BRANCH_HALT_VOTED, 3860 .hwcg_reg = 0xba4a8, 3861 .hwcg_bit = 1, 3862 .clkr = { 3863 .enable_reg = 0x62010, 3864 .enable_mask = BIT(24), 3865 .hw.init = &(const struct clk_init_data) { 3866 .name = "gcc_pcie_0_cfg_ahb_clk", 3867 .ops = &clk_branch2_ops, 3868 }, 3869 }, 3870 }; 3871 3872 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 3873 .halt_reg = 0xba498, 3874 .halt_check = BRANCH_HALT_SKIP, 3875 .hwcg_reg = 0xba498, 3876 .hwcg_bit = 1, 3877 .clkr = { 3878 .enable_reg = 0x62010, 3879 .enable_mask = BIT(23), 3880 .hw.init = &(const struct clk_init_data) { 3881 .name = "gcc_pcie_0_mstr_axi_clk", 3882 .ops = &clk_branch2_ops, 3883 }, 3884 }, 3885 }; 3886 3887 static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 3888 .halt_reg = 0xc8038, 3889 .halt_check = BRANCH_HALT_VOTED, 3890 .clkr = { 3891 .enable_reg = 0x62010, 3892 .enable_mask = BIT(27), 3893 .hw.init = &(const struct clk_init_data) { 3894 .name = "gcc_pcie_0_phy_rchng_clk", 3895 .parent_hws = (const struct clk_hw*[]) { 3896 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 3897 }, 3898 .num_parents = 1, 3899 .flags = CLK_SET_RATE_PARENT, 3900 .ops = &clk_branch2_ops, 3901 }, 3902 }, 3903 }; 3904 3905 static struct clk_branch gcc_pcie_0_pipe_clk = { 3906 .halt_reg = 0xc8028, 3907 .halt_check = BRANCH_HALT_SKIP, 3908 .clkr = { 3909 .enable_reg = 0x62010, 3910 .enable_mask = BIT(26), 3911 .hw.init = &(const struct clk_init_data) { 3912 .name = "gcc_pcie_0_pipe_clk", 3913 .parent_hws = (const struct clk_hw*[]) { 3914 &gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr.hw, 3915 }, 3916 .num_parents = 1, 3917 .flags = CLK_SET_RATE_PARENT, 3918 .ops = &clk_branch2_ops, 3919 }, 3920 }, 3921 }; 3922 3923 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 3924 .halt_reg = 0xba488, 3925 .halt_check = BRANCH_HALT_VOTED, 3926 .hwcg_reg = 0xba488, 3927 .hwcg_bit = 1, 3928 .clkr = { 3929 .enable_reg = 0x62010, 3930 .enable_mask = BIT(22), 3931 .hw.init = &(const struct clk_init_data) { 3932 .name = "gcc_pcie_0_slv_axi_clk", 3933 .ops = &clk_branch2_ops, 3934 }, 3935 }, 3936 }; 3937 3938 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 3939 .halt_reg = 0xba484, 3940 .halt_check = BRANCH_HALT_VOTED, 3941 .clkr = { 3942 .enable_reg = 0x62010, 3943 .enable_mask = BIT(21), 3944 .hw.init = &(const struct clk_init_data) { 3945 .name = "gcc_pcie_0_slv_q2a_axi_clk", 3946 .ops = &clk_branch2_ops, 3947 }, 3948 }, 3949 }; 3950 3951 static struct clk_branch gcc_pcie_1_aux_clk = { 3952 .halt_reg = 0x2e018, 3953 .halt_check = BRANCH_HALT_VOTED, 3954 .clkr = { 3955 .enable_reg = 0x62010, 3956 .enable_mask = BIT(18), 3957 .hw.init = &(const struct clk_init_data) { 3958 .name = "gcc_pcie_1_aux_clk", 3959 .parent_hws = (const struct clk_hw*[]) { 3960 &gcc_pcie_1_aux_clk_src.clkr.hw, 3961 }, 3962 .num_parents = 1, 3963 .flags = CLK_SET_RATE_PARENT, 3964 .ops = &clk_branch2_ops, 3965 }, 3966 }, 3967 }; 3968 3969 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 3970 .halt_reg = 0xba480, 3971 .halt_check = BRANCH_HALT_VOTED, 3972 .hwcg_reg = 0xba480, 3973 .hwcg_bit = 1, 3974 .clkr = { 3975 .enable_reg = 0x62010, 3976 .enable_mask = BIT(17), 3977 .hw.init = &(const struct clk_init_data) { 3978 .name = "gcc_pcie_1_cfg_ahb_clk", 3979 .ops = &clk_branch2_ops, 3980 }, 3981 }, 3982 }; 3983 3984 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 3985 .halt_reg = 0xba470, 3986 .halt_check = BRANCH_HALT_SKIP, 3987 .hwcg_reg = 0xba470, 3988 .hwcg_bit = 1, 3989 .clkr = { 3990 .enable_reg = 0x62010, 3991 .enable_mask = BIT(16), 3992 .hw.init = &(const struct clk_init_data) { 3993 .name = "gcc_pcie_1_mstr_axi_clk", 3994 .ops = &clk_branch2_ops, 3995 }, 3996 }, 3997 }; 3998 3999 static struct clk_branch gcc_pcie_1_phy_rchng_clk = { 4000 .halt_reg = 0x2e038, 4001 .halt_check = BRANCH_HALT_VOTED, 4002 .clkr = { 4003 .enable_reg = 0x62010, 4004 .enable_mask = BIT(20), 4005 .hw.init = &(const struct clk_init_data) { 4006 .name = "gcc_pcie_1_phy_rchng_clk", 4007 .parent_hws = (const struct clk_hw*[]) { 4008 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, 4009 }, 4010 .num_parents = 1, 4011 .flags = CLK_SET_RATE_PARENT, 4012 .ops = &clk_branch2_ops, 4013 }, 4014 }, 4015 }; 4016 4017 static struct clk_branch gcc_pcie_1_pipe_clk = { 4018 .halt_reg = 0x2e028, 4019 .halt_check = BRANCH_HALT_SKIP, 4020 .clkr = { 4021 .enable_reg = 0x62010, 4022 .enable_mask = BIT(19), 4023 .hw.init = &(const struct clk_init_data) { 4024 .name = "gcc_pcie_1_pipe_clk", 4025 .parent_hws = (const struct clk_hw*[]) { 4026 &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw, 4027 }, 4028 .num_parents = 1, 4029 .flags = CLK_SET_RATE_PARENT, 4030 .ops = &clk_branch2_ops, 4031 }, 4032 }, 4033 }; 4034 4035 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 4036 .halt_reg = 0xba460, 4037 .halt_check = BRANCH_HALT_VOTED, 4038 .hwcg_reg = 0xba460, 4039 .hwcg_bit = 1, 4040 .clkr = { 4041 .enable_reg = 0x62010, 4042 .enable_mask = BIT(15), 4043 .hw.init = &(const struct clk_init_data) { 4044 .name = "gcc_pcie_1_slv_axi_clk", 4045 .ops = &clk_branch2_ops, 4046 }, 4047 }, 4048 }; 4049 4050 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 4051 .halt_reg = 0xba45c, 4052 .halt_check = BRANCH_HALT_VOTED, 4053 .clkr = { 4054 .enable_reg = 0x62010, 4055 .enable_mask = BIT(14), 4056 .hw.init = &(const struct clk_init_data) { 4057 .name = "gcc_pcie_1_slv_q2a_axi_clk", 4058 .ops = &clk_branch2_ops, 4059 }, 4060 }, 4061 }; 4062 4063 static struct clk_branch gcc_pcie_2_aux_clk = { 4064 .halt_reg = 0xc0018, 4065 .halt_check = BRANCH_HALT_VOTED, 4066 .clkr = { 4067 .enable_reg = 0x62018, 4068 .enable_mask = BIT(0), 4069 .hw.init = &(const struct clk_init_data) { 4070 .name = "gcc_pcie_2_aux_clk", 4071 .parent_hws = (const struct clk_hw*[]) { 4072 &gcc_pcie_2_aux_clk_src.clkr.hw, 4073 }, 4074 .num_parents = 1, 4075 .flags = CLK_SET_RATE_PARENT, 4076 .ops = &clk_branch2_ops, 4077 }, 4078 }, 4079 }; 4080 4081 static struct clk_branch gcc_pcie_2_cfg_ahb_clk = { 4082 .halt_reg = 0xba4d0, 4083 .halt_check = BRANCH_HALT_VOTED, 4084 .hwcg_reg = 0xba4d0, 4085 .hwcg_bit = 1, 4086 .clkr = { 4087 .enable_reg = 0x62010, 4088 .enable_mask = BIT(31), 4089 .hw.init = &(const struct clk_init_data) { 4090 .name = "gcc_pcie_2_cfg_ahb_clk", 4091 .ops = &clk_branch2_ops, 4092 }, 4093 }, 4094 }; 4095 4096 static struct clk_branch gcc_pcie_2_mstr_axi_clk = { 4097 .halt_reg = 0xba4c0, 4098 .halt_check = BRANCH_HALT_SKIP, 4099 .hwcg_reg = 0xba4c0, 4100 .hwcg_bit = 1, 4101 .clkr = { 4102 .enable_reg = 0x62010, 4103 .enable_mask = BIT(30), 4104 .hw.init = &(const struct clk_init_data) { 4105 .name = "gcc_pcie_2_mstr_axi_clk", 4106 .ops = &clk_branch2_ops, 4107 }, 4108 }, 4109 }; 4110 4111 static struct clk_branch gcc_pcie_2_phy_rchng_clk = { 4112 .halt_reg = 0xc0038, 4113 .halt_check = BRANCH_HALT_VOTED, 4114 .clkr = { 4115 .enable_reg = 0x62018, 4116 .enable_mask = BIT(2), 4117 .hw.init = &(const struct clk_init_data) { 4118 .name = "gcc_pcie_2_phy_rchng_clk", 4119 .parent_hws = (const struct clk_hw*[]) { 4120 &gcc_pcie_2_phy_rchng_clk_src.clkr.hw, 4121 }, 4122 .num_parents = 1, 4123 .flags = CLK_SET_RATE_PARENT, 4124 .ops = &clk_branch2_ops, 4125 }, 4126 }, 4127 }; 4128 4129 static struct clk_branch gcc_pcie_2_pipe_clk = { 4130 .halt_reg = 0xc0028, 4131 .halt_check = BRANCH_HALT_SKIP, 4132 .clkr = { 4133 .enable_reg = 0x62018, 4134 .enable_mask = BIT(1), 4135 .hw.init = &(const struct clk_init_data) { 4136 .name = "gcc_pcie_2_pipe_clk", 4137 .parent_hws = (const struct clk_hw*[]) { 4138 &gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr.hw, 4139 }, 4140 .num_parents = 1, 4141 .flags = CLK_SET_RATE_PARENT, 4142 .ops = &clk_branch2_ops, 4143 }, 4144 }, 4145 }; 4146 4147 static struct clk_branch gcc_pcie_2_slv_axi_clk = { 4148 .halt_reg = 0xba4b0, 4149 .halt_check = BRANCH_HALT_VOTED, 4150 .hwcg_reg = 0xba4b0, 4151 .hwcg_bit = 1, 4152 .clkr = { 4153 .enable_reg = 0x62010, 4154 .enable_mask = BIT(29), 4155 .hw.init = &(const struct clk_init_data) { 4156 .name = "gcc_pcie_2_slv_axi_clk", 4157 .ops = &clk_branch2_ops, 4158 }, 4159 }, 4160 }; 4161 4162 static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = { 4163 .halt_reg = 0xba4ac, 4164 .halt_check = BRANCH_HALT_VOTED, 4165 .clkr = { 4166 .enable_reg = 0x62010, 4167 .enable_mask = BIT(28), 4168 .hw.init = &(const struct clk_init_data) { 4169 .name = "gcc_pcie_2_slv_q2a_axi_clk", 4170 .ops = &clk_branch2_ops, 4171 }, 4172 }, 4173 }; 4174 4175 static struct clk_branch gcc_pcie_3a_aux_clk = { 4176 .halt_reg = 0xdc04c, 4177 .halt_check = BRANCH_HALT_VOTED, 4178 .hwcg_reg = 0xdc04c, 4179 .hwcg_bit = 1, 4180 .clkr = { 4181 .enable_reg = 0x62028, 4182 .enable_mask = BIT(16), 4183 .hw.init = &(const struct clk_init_data) { 4184 .name = "gcc_pcie_3a_aux_clk", 4185 .parent_hws = (const struct clk_hw*[]) { 4186 &gcc_pcie_3a_aux_clk_src.clkr.hw, 4187 }, 4188 .num_parents = 1, 4189 .flags = CLK_SET_RATE_PARENT, 4190 .ops = &clk_branch2_ops, 4191 }, 4192 }, 4193 }; 4194 4195 static struct clk_branch gcc_pcie_3a_cfg_ahb_clk = { 4196 .halt_reg = 0xba4f0, 4197 .halt_check = BRANCH_HALT_VOTED, 4198 .hwcg_reg = 0xba4f0, 4199 .hwcg_bit = 1, 4200 .clkr = { 4201 .enable_reg = 0x62028, 4202 .enable_mask = BIT(15), 4203 .hw.init = &(const struct clk_init_data) { 4204 .name = "gcc_pcie_3a_cfg_ahb_clk", 4205 .ops = &clk_branch2_ops, 4206 }, 4207 }, 4208 }; 4209 4210 static struct clk_branch gcc_pcie_3a_mstr_axi_clk = { 4211 .halt_reg = 0xdc038, 4212 .halt_check = BRANCH_HALT_SKIP, 4213 .hwcg_reg = 0xdc038, 4214 .hwcg_bit = 1, 4215 .clkr = { 4216 .enable_reg = 0x62028, 4217 .enable_mask = BIT(14), 4218 .hw.init = &(const struct clk_init_data) { 4219 .name = "gcc_pcie_3a_mstr_axi_clk", 4220 .ops = &clk_branch2_ops, 4221 }, 4222 }, 4223 }; 4224 4225 static struct clk_branch gcc_pcie_3a_phy_rchng_clk = { 4226 .halt_reg = 0xdc06c, 4227 .halt_check = BRANCH_HALT_VOTED, 4228 .hwcg_reg = 0xdc06c, 4229 .hwcg_bit = 1, 4230 .clkr = { 4231 .enable_reg = 0x62028, 4232 .enable_mask = BIT(18), 4233 .hw.init = &(const struct clk_init_data) { 4234 .name = "gcc_pcie_3a_phy_rchng_clk", 4235 .parent_hws = (const struct clk_hw*[]) { 4236 &gcc_pcie_3a_phy_rchng_clk_src.clkr.hw, 4237 }, 4238 .num_parents = 1, 4239 .flags = CLK_SET_RATE_PARENT, 4240 .ops = &clk_branch2_ops, 4241 }, 4242 }, 4243 }; 4244 4245 static struct clk_branch gcc_pcie_3a_pipe_clk = { 4246 .halt_reg = 0xdc05c, 4247 .halt_check = BRANCH_HALT_SKIP, 4248 .hwcg_reg = 0xdc05c, 4249 .hwcg_bit = 1, 4250 .clkr = { 4251 .enable_reg = 0x62028, 4252 .enable_mask = BIT(17), 4253 .hw.init = &(const struct clk_init_data) { 4254 .name = "gcc_pcie_3a_pipe_clk", 4255 .parent_hws = (const struct clk_hw*[]) { 4256 &gcc_pcie_3a_pipe_clk_src.clkr.hw, 4257 }, 4258 .num_parents = 1, 4259 .flags = CLK_SET_RATE_PARENT, 4260 .ops = &clk_branch2_ops, 4261 }, 4262 }, 4263 }; 4264 4265 static struct clk_branch gcc_pcie_3a_slv_axi_clk = { 4266 .halt_reg = 0xdc024, 4267 .halt_check = BRANCH_HALT_VOTED, 4268 .hwcg_reg = 0xdc024, 4269 .hwcg_bit = 1, 4270 .clkr = { 4271 .enable_reg = 0x62028, 4272 .enable_mask = BIT(13), 4273 .hw.init = &(const struct clk_init_data) { 4274 .name = "gcc_pcie_3a_slv_axi_clk", 4275 .ops = &clk_branch2_ops, 4276 }, 4277 }, 4278 }; 4279 4280 static struct clk_branch gcc_pcie_3a_slv_q2a_axi_clk = { 4281 .halt_reg = 0xdc01c, 4282 .halt_check = BRANCH_HALT_VOTED, 4283 .hwcg_reg = 0xdc01c, 4284 .hwcg_bit = 1, 4285 .clkr = { 4286 .enable_reg = 0x62028, 4287 .enable_mask = BIT(12), 4288 .hw.init = &(const struct clk_init_data) { 4289 .name = "gcc_pcie_3a_slv_q2a_axi_clk", 4290 .ops = &clk_branch2_ops, 4291 }, 4292 }, 4293 }; 4294 4295 static struct clk_branch gcc_pcie_3b_aux_clk = { 4296 .halt_reg = 0x94050, 4297 .halt_check = BRANCH_HALT_VOTED, 4298 .clkr = { 4299 .enable_reg = 0x62028, 4300 .enable_mask = BIT(25), 4301 .hw.init = &(const struct clk_init_data) { 4302 .name = "gcc_pcie_3b_aux_clk", 4303 .parent_hws = (const struct clk_hw*[]) { 4304 &gcc_pcie_3b_aux_clk_src.clkr.hw, 4305 }, 4306 .num_parents = 1, 4307 .flags = CLK_SET_RATE_PARENT, 4308 .ops = &clk_branch2_ops, 4309 }, 4310 }, 4311 }; 4312 4313 static struct clk_branch gcc_pcie_3b_cfg_ahb_clk = { 4314 .halt_reg = 0xba4f4, 4315 .halt_check = BRANCH_HALT_VOTED, 4316 .hwcg_reg = 0xba4f4, 4317 .hwcg_bit = 1, 4318 .clkr = { 4319 .enable_reg = 0x62028, 4320 .enable_mask = BIT(24), 4321 .hw.init = &(const struct clk_init_data) { 4322 .name = "gcc_pcie_3b_cfg_ahb_clk", 4323 .ops = &clk_branch2_ops, 4324 }, 4325 }, 4326 }; 4327 4328 static struct clk_branch gcc_pcie_3b_mstr_axi_clk = { 4329 .halt_reg = 0x94038, 4330 .halt_check = BRANCH_HALT_SKIP, 4331 .hwcg_reg = 0x94038, 4332 .hwcg_bit = 1, 4333 .clkr = { 4334 .enable_reg = 0x62028, 4335 .enable_mask = BIT(23), 4336 .hw.init = &(const struct clk_init_data) { 4337 .name = "gcc_pcie_3b_mstr_axi_clk", 4338 .ops = &clk_branch2_ops, 4339 }, 4340 }, 4341 }; 4342 4343 static struct clk_branch gcc_pcie_3b_phy_rchng_clk = { 4344 .halt_reg = 0x94084, 4345 .halt_check = BRANCH_HALT_VOTED, 4346 .clkr = { 4347 .enable_reg = 0x62028, 4348 .enable_mask = BIT(28), 4349 .hw.init = &(const struct clk_init_data) { 4350 .name = "gcc_pcie_3b_phy_rchng_clk", 4351 .parent_hws = (const struct clk_hw*[]) { 4352 &gcc_pcie_3b_phy_rchng_clk_src.clkr.hw, 4353 }, 4354 .num_parents = 1, 4355 .flags = CLK_SET_RATE_PARENT, 4356 .ops = &clk_branch2_ops, 4357 }, 4358 }, 4359 }; 4360 4361 static struct clk_branch gcc_pcie_3b_pipe_clk = { 4362 .halt_reg = 0x94060, 4363 .halt_check = BRANCH_HALT_SKIP, 4364 .clkr = { 4365 .enable_reg = 0x62028, 4366 .enable_mask = BIT(26), 4367 .hw.init = &(const struct clk_init_data) { 4368 .name = "gcc_pcie_3b_pipe_clk", 4369 .parent_hws = (const struct clk_hw*[]) { 4370 &gcc_pcie_3b_pipe_clk_src.clkr.hw, 4371 }, 4372 .num_parents = 1, 4373 .flags = CLK_SET_RATE_PARENT, 4374 .ops = &clk_branch2_ops, 4375 }, 4376 }, 4377 }; 4378 4379 static struct clk_branch gcc_pcie_3b_pipe_div2_clk = { 4380 .halt_reg = 0x94074, 4381 .halt_check = BRANCH_HALT_SKIP, 4382 .clkr = { 4383 .enable_reg = 0x62028, 4384 .enable_mask = BIT(27), 4385 .hw.init = &(const struct clk_init_data) { 4386 .name = "gcc_pcie_3b_pipe_div2_clk", 4387 .parent_hws = (const struct clk_hw*[]) { 4388 &gcc_pcie_3b_pipe_div_clk_src.clkr.hw, 4389 }, 4390 .num_parents = 1, 4391 .flags = CLK_SET_RATE_PARENT, 4392 .ops = &clk_branch2_ops, 4393 }, 4394 }, 4395 }; 4396 4397 static struct clk_branch gcc_pcie_3b_slv_axi_clk = { 4398 .halt_reg = 0x94024, 4399 .halt_check = BRANCH_HALT_VOTED, 4400 .hwcg_reg = 0x94024, 4401 .hwcg_bit = 1, 4402 .clkr = { 4403 .enable_reg = 0x62028, 4404 .enable_mask = BIT(22), 4405 .hw.init = &(const struct clk_init_data) { 4406 .name = "gcc_pcie_3b_slv_axi_clk", 4407 .ops = &clk_branch2_ops, 4408 }, 4409 }, 4410 }; 4411 4412 static struct clk_branch gcc_pcie_3b_slv_q2a_axi_clk = { 4413 .halt_reg = 0x9401c, 4414 .halt_check = BRANCH_HALT_VOTED, 4415 .clkr = { 4416 .enable_reg = 0x62028, 4417 .enable_mask = BIT(21), 4418 .hw.init = &(const struct clk_init_data) { 4419 .name = "gcc_pcie_3b_slv_q2a_axi_clk", 4420 .ops = &clk_branch2_ops, 4421 }, 4422 }, 4423 }; 4424 4425 static struct clk_branch gcc_pcie_4_aux_clk = { 4426 .halt_reg = 0x88040, 4427 .halt_check = BRANCH_HALT_VOTED, 4428 .clkr = { 4429 .enable_reg = 0x62030, 4430 .enable_mask = BIT(17), 4431 .hw.init = &(const struct clk_init_data) { 4432 .name = "gcc_pcie_4_aux_clk", 4433 .parent_hws = (const struct clk_hw*[]) { 4434 &gcc_pcie_4_aux_clk_src.clkr.hw, 4435 }, 4436 .num_parents = 1, 4437 .flags = CLK_SET_RATE_PARENT, 4438 .ops = &clk_branch2_ops, 4439 }, 4440 }, 4441 }; 4442 4443 static struct clk_branch gcc_pcie_4_cfg_ahb_clk = { 4444 .halt_reg = 0xba4fc, 4445 .halt_check = BRANCH_HALT_VOTED, 4446 .hwcg_reg = 0xba4fc, 4447 .hwcg_bit = 1, 4448 .clkr = { 4449 .enable_reg = 0x62030, 4450 .enable_mask = BIT(16), 4451 .hw.init = &(const struct clk_init_data) { 4452 .name = "gcc_pcie_4_cfg_ahb_clk", 4453 .ops = &clk_branch2_ops, 4454 }, 4455 }, 4456 }; 4457 4458 static struct clk_branch gcc_pcie_4_mstr_axi_clk = { 4459 .halt_reg = 0x88030, 4460 .halt_check = BRANCH_HALT_SKIP, 4461 .hwcg_reg = 0x88030, 4462 .hwcg_bit = 1, 4463 .clkr = { 4464 .enable_reg = 0x62030, 4465 .enable_mask = BIT(15), 4466 .hw.init = &(const struct clk_init_data) { 4467 .name = "gcc_pcie_4_mstr_axi_clk", 4468 .ops = &clk_branch2_ops, 4469 }, 4470 }, 4471 }; 4472 4473 static struct clk_branch gcc_pcie_4_phy_rchng_clk = { 4474 .halt_reg = 0x88074, 4475 .halt_check = BRANCH_HALT_VOTED, 4476 .clkr = { 4477 .enable_reg = 0x62030, 4478 .enable_mask = BIT(20), 4479 .hw.init = &(const struct clk_init_data) { 4480 .name = "gcc_pcie_4_phy_rchng_clk", 4481 .parent_hws = (const struct clk_hw*[]) { 4482 &gcc_pcie_4_phy_rchng_clk_src.clkr.hw, 4483 }, 4484 .num_parents = 1, 4485 .flags = CLK_SET_RATE_PARENT, 4486 .ops = &clk_branch2_ops, 4487 }, 4488 }, 4489 }; 4490 4491 static struct clk_branch gcc_pcie_4_pipe_clk = { 4492 .halt_reg = 0x88050, 4493 .halt_check = BRANCH_HALT_SKIP, 4494 .clkr = { 4495 .enable_reg = 0x62030, 4496 .enable_mask = BIT(18), 4497 .hw.init = &(const struct clk_init_data) { 4498 .name = "gcc_pcie_4_pipe_clk", 4499 .parent_hws = (const struct clk_hw*[]) { 4500 &gcc_pcie_4_pipe_clk_src.clkr.hw, 4501 }, 4502 .num_parents = 1, 4503 .flags = CLK_SET_RATE_PARENT, 4504 .ops = &clk_branch2_ops, 4505 }, 4506 }, 4507 }; 4508 4509 static struct clk_branch gcc_pcie_4_pipe_div2_clk = { 4510 .halt_reg = 0x88064, 4511 .halt_check = BRANCH_HALT_SKIP, 4512 .clkr = { 4513 .enable_reg = 0x62030, 4514 .enable_mask = BIT(19), 4515 .hw.init = &(const struct clk_init_data) { 4516 .name = "gcc_pcie_4_pipe_div2_clk", 4517 .parent_hws = (const struct clk_hw*[]) { 4518 &gcc_pcie_4_pipe_div_clk_src.clkr.hw, 4519 }, 4520 .num_parents = 1, 4521 .flags = CLK_SET_RATE_PARENT, 4522 .ops = &clk_branch2_ops, 4523 }, 4524 }, 4525 }; 4526 4527 static struct clk_branch gcc_pcie_4_slv_axi_clk = { 4528 .halt_reg = 0x88020, 4529 .halt_check = BRANCH_HALT_VOTED, 4530 .hwcg_reg = 0x88020, 4531 .hwcg_bit = 1, 4532 .clkr = { 4533 .enable_reg = 0x62030, 4534 .enable_mask = BIT(14), 4535 .hw.init = &(const struct clk_init_data) { 4536 .name = "gcc_pcie_4_slv_axi_clk", 4537 .ops = &clk_branch2_ops, 4538 }, 4539 }, 4540 }; 4541 4542 static struct clk_branch gcc_pcie_4_slv_q2a_axi_clk = { 4543 .halt_reg = 0x8801c, 4544 .halt_check = BRANCH_HALT_VOTED, 4545 .clkr = { 4546 .enable_reg = 0x62030, 4547 .enable_mask = BIT(13), 4548 .hw.init = &(const struct clk_init_data) { 4549 .name = "gcc_pcie_4_slv_q2a_axi_clk", 4550 .ops = &clk_branch2_ops, 4551 }, 4552 }, 4553 }; 4554 4555 static struct clk_branch gcc_pcie_5_aux_clk = { 4556 .halt_reg = 0xc304c, 4557 .halt_check = BRANCH_HALT_VOTED, 4558 .clkr = { 4559 .enable_reg = 0x62030, 4560 .enable_mask = BIT(5), 4561 .hw.init = &(const struct clk_init_data) { 4562 .name = "gcc_pcie_5_aux_clk", 4563 .parent_hws = (const struct clk_hw*[]) { 4564 &gcc_pcie_5_aux_clk_src.clkr.hw, 4565 }, 4566 .num_parents = 1, 4567 .flags = CLK_SET_RATE_PARENT, 4568 .ops = &clk_branch2_ops, 4569 }, 4570 }, 4571 }; 4572 4573 static struct clk_branch gcc_pcie_5_cfg_ahb_clk = { 4574 .halt_reg = 0xba4f8, 4575 .halt_check = BRANCH_HALT_VOTED, 4576 .hwcg_reg = 0xba4f8, 4577 .hwcg_bit = 1, 4578 .clkr = { 4579 .enable_reg = 0x62030, 4580 .enable_mask = BIT(4), 4581 .hw.init = &(const struct clk_init_data) { 4582 .name = "gcc_pcie_5_cfg_ahb_clk", 4583 .ops = &clk_branch2_ops, 4584 }, 4585 }, 4586 }; 4587 4588 static struct clk_branch gcc_pcie_5_mstr_axi_clk = { 4589 .halt_reg = 0xc3038, 4590 .halt_check = BRANCH_HALT_SKIP, 4591 .hwcg_reg = 0xc3038, 4592 .hwcg_bit = 1, 4593 .clkr = { 4594 .enable_reg = 0x62030, 4595 .enable_mask = BIT(3), 4596 .hw.init = &(const struct clk_init_data) { 4597 .name = "gcc_pcie_5_mstr_axi_clk", 4598 .ops = &clk_branch2_ops, 4599 }, 4600 }, 4601 }; 4602 4603 static struct clk_branch gcc_pcie_5_phy_rchng_clk = { 4604 .halt_reg = 0xc3080, 4605 .halt_check = BRANCH_HALT_VOTED, 4606 .clkr = { 4607 .enable_reg = 0x62030, 4608 .enable_mask = BIT(8), 4609 .hw.init = &(const struct clk_init_data) { 4610 .name = "gcc_pcie_5_phy_rchng_clk", 4611 .parent_hws = (const struct clk_hw*[]) { 4612 &gcc_pcie_5_phy_rchng_clk_src.clkr.hw, 4613 }, 4614 .num_parents = 1, 4615 .flags = CLK_SET_RATE_PARENT, 4616 .ops = &clk_branch2_ops, 4617 }, 4618 }, 4619 }; 4620 4621 static struct clk_branch gcc_pcie_5_pipe_clk = { 4622 .halt_reg = 0xc305c, 4623 .halt_check = BRANCH_HALT_SKIP, 4624 .clkr = { 4625 .enable_reg = 0x62030, 4626 .enable_mask = BIT(6), 4627 .hw.init = &(const struct clk_init_data) { 4628 .name = "gcc_pcie_5_pipe_clk", 4629 .parent_hws = (const struct clk_hw*[]) { 4630 &gcc_pcie_5_pipe_clk_src.clkr.hw, 4631 }, 4632 .num_parents = 1, 4633 .flags = CLK_SET_RATE_PARENT, 4634 .ops = &clk_branch2_ops, 4635 }, 4636 }, 4637 }; 4638 4639 static struct clk_branch gcc_pcie_5_pipe_div2_clk = { 4640 .halt_reg = 0xc3070, 4641 .halt_check = BRANCH_HALT_SKIP, 4642 .clkr = { 4643 .enable_reg = 0x62030, 4644 .enable_mask = BIT(7), 4645 .hw.init = &(const struct clk_init_data) { 4646 .name = "gcc_pcie_5_pipe_div2_clk", 4647 .parent_hws = (const struct clk_hw*[]) { 4648 &gcc_pcie_5_pipe_div_clk_src.clkr.hw, 4649 }, 4650 .num_parents = 1, 4651 .flags = CLK_SET_RATE_PARENT, 4652 .ops = &clk_branch2_ops, 4653 }, 4654 }, 4655 }; 4656 4657 static struct clk_branch gcc_pcie_5_slv_axi_clk = { 4658 .halt_reg = 0xc3024, 4659 .halt_check = BRANCH_HALT_VOTED, 4660 .hwcg_reg = 0xc3024, 4661 .hwcg_bit = 1, 4662 .clkr = { 4663 .enable_reg = 0x62030, 4664 .enable_mask = BIT(2), 4665 .hw.init = &(const struct clk_init_data) { 4666 .name = "gcc_pcie_5_slv_axi_clk", 4667 .ops = &clk_branch2_ops, 4668 }, 4669 }, 4670 }; 4671 4672 static struct clk_branch gcc_pcie_5_slv_q2a_axi_clk = { 4673 .halt_reg = 0xc301c, 4674 .halt_check = BRANCH_HALT_VOTED, 4675 .clkr = { 4676 .enable_reg = 0x62030, 4677 .enable_mask = BIT(1), 4678 .hw.init = &(const struct clk_init_data) { 4679 .name = "gcc_pcie_5_slv_q2a_axi_clk", 4680 .ops = &clk_branch2_ops, 4681 }, 4682 }, 4683 }; 4684 4685 static struct clk_branch gcc_pcie_6_aux_clk = { 4686 .halt_reg = 0x8a040, 4687 .halt_check = BRANCH_HALT_VOTED, 4688 .clkr = { 4689 .enable_reg = 0x62030, 4690 .enable_mask = BIT(27), 4691 .hw.init = &(const struct clk_init_data) { 4692 .name = "gcc_pcie_6_aux_clk", 4693 .parent_hws = (const struct clk_hw*[]) { 4694 &gcc_pcie_6_aux_clk_src.clkr.hw, 4695 }, 4696 .num_parents = 1, 4697 .flags = CLK_SET_RATE_PARENT, 4698 .ops = &clk_branch2_ops, 4699 }, 4700 }, 4701 }; 4702 4703 static struct clk_branch gcc_pcie_6_cfg_ahb_clk = { 4704 .halt_reg = 0xba500, 4705 .halt_check = BRANCH_HALT_VOTED, 4706 .hwcg_reg = 0xba500, 4707 .hwcg_bit = 1, 4708 .clkr = { 4709 .enable_reg = 0x62030, 4710 .enable_mask = BIT(26), 4711 .hw.init = &(const struct clk_init_data) { 4712 .name = "gcc_pcie_6_cfg_ahb_clk", 4713 .ops = &clk_branch2_ops, 4714 }, 4715 }, 4716 }; 4717 4718 static struct clk_branch gcc_pcie_6_mstr_axi_clk = { 4719 .halt_reg = 0x8a030, 4720 .halt_check = BRANCH_HALT_SKIP, 4721 .hwcg_reg = 0x8a030, 4722 .hwcg_bit = 1, 4723 .clkr = { 4724 .enable_reg = 0x62030, 4725 .enable_mask = BIT(25), 4726 .hw.init = &(const struct clk_init_data) { 4727 .name = "gcc_pcie_6_mstr_axi_clk", 4728 .ops = &clk_branch2_ops, 4729 }, 4730 }, 4731 }; 4732 4733 static struct clk_branch gcc_pcie_6_phy_rchng_clk = { 4734 .halt_reg = 0x8a074, 4735 .halt_check = BRANCH_HALT_VOTED, 4736 .clkr = { 4737 .enable_reg = 0x62030, 4738 .enable_mask = BIT(30), 4739 .hw.init = &(const struct clk_init_data) { 4740 .name = "gcc_pcie_6_phy_rchng_clk", 4741 .parent_hws = (const struct clk_hw*[]) { 4742 &gcc_pcie_6_phy_rchng_clk_src.clkr.hw, 4743 }, 4744 .num_parents = 1, 4745 .flags = CLK_SET_RATE_PARENT, 4746 .ops = &clk_branch2_ops, 4747 }, 4748 }, 4749 }; 4750 4751 static struct clk_branch gcc_pcie_6_pipe_clk = { 4752 .halt_reg = 0x8a050, 4753 .halt_check = BRANCH_HALT_SKIP, 4754 .clkr = { 4755 .enable_reg = 0x62030, 4756 .enable_mask = BIT(28), 4757 .hw.init = &(const struct clk_init_data) { 4758 .name = "gcc_pcie_6_pipe_clk", 4759 .parent_hws = (const struct clk_hw*[]) { 4760 &gcc_pcie_6_pipe_clk_src.clkr.hw, 4761 }, 4762 .num_parents = 1, 4763 .flags = CLK_SET_RATE_PARENT, 4764 .ops = &clk_branch2_ops, 4765 }, 4766 }, 4767 }; 4768 4769 static struct clk_branch gcc_pcie_6_pipe_div2_clk = { 4770 .halt_reg = 0x8a064, 4771 .halt_check = BRANCH_HALT_SKIP, 4772 .clkr = { 4773 .enable_reg = 0x62030, 4774 .enable_mask = BIT(29), 4775 .hw.init = &(const struct clk_init_data) { 4776 .name = "gcc_pcie_6_pipe_div2_clk", 4777 .parent_hws = (const struct clk_hw*[]) { 4778 &gcc_pcie_6_pipe_div_clk_src.clkr.hw, 4779 }, 4780 .num_parents = 1, 4781 .flags = CLK_SET_RATE_PARENT, 4782 .ops = &clk_branch2_ops, 4783 }, 4784 }, 4785 }; 4786 4787 static struct clk_branch gcc_pcie_6_slv_axi_clk = { 4788 .halt_reg = 0x8a020, 4789 .halt_check = BRANCH_HALT_VOTED, 4790 .hwcg_reg = 0x8a020, 4791 .hwcg_bit = 1, 4792 .clkr = { 4793 .enable_reg = 0x62030, 4794 .enable_mask = BIT(24), 4795 .hw.init = &(const struct clk_init_data) { 4796 .name = "gcc_pcie_6_slv_axi_clk", 4797 .ops = &clk_branch2_ops, 4798 }, 4799 }, 4800 }; 4801 4802 static struct clk_branch gcc_pcie_6_slv_q2a_axi_clk = { 4803 .halt_reg = 0x8a01c, 4804 .halt_check = BRANCH_HALT_VOTED, 4805 .clkr = { 4806 .enable_reg = 0x62030, 4807 .enable_mask = BIT(23), 4808 .hw.init = &(const struct clk_init_data) { 4809 .name = "gcc_pcie_6_slv_q2a_axi_clk", 4810 .ops = &clk_branch2_ops, 4811 }, 4812 }, 4813 }; 4814 4815 static struct clk_branch gcc_pcie_noc_pwrctl_clk = { 4816 .halt_reg = 0xba2ac, 4817 .halt_check = BRANCH_HALT_VOTED, 4818 .clkr = { 4819 .enable_reg = 0x62008, 4820 .enable_mask = BIT(7), 4821 .hw.init = &(const struct clk_init_data) { 4822 .name = "gcc_pcie_noc_pwrctl_clk", 4823 .ops = &clk_branch2_ops, 4824 }, 4825 }, 4826 }; 4827 4828 static struct clk_branch gcc_pcie_noc_qosgen_extref_clk = { 4829 .halt_reg = 0xba2a8, 4830 .halt_check = BRANCH_HALT_VOTED, 4831 .clkr = { 4832 .enable_reg = 0x62008, 4833 .enable_mask = BIT(6), 4834 .hw.init = &(const struct clk_init_data) { 4835 .name = "gcc_pcie_noc_qosgen_extref_clk", 4836 .ops = &clk_branch2_ops, 4837 }, 4838 }, 4839 }; 4840 4841 static struct clk_branch gcc_pcie_noc_sf_center_clk = { 4842 .halt_reg = 0xba2b0, 4843 .halt_check = BRANCH_HALT_VOTED, 4844 .hwcg_reg = 0xba2b0, 4845 .hwcg_bit = 1, 4846 .clkr = { 4847 .enable_reg = 0x62008, 4848 .enable_mask = BIT(8), 4849 .hw.init = &(const struct clk_init_data) { 4850 .name = "gcc_pcie_noc_sf_center_clk", 4851 .ops = &clk_branch2_ops, 4852 }, 4853 }, 4854 }; 4855 4856 static struct clk_branch gcc_pcie_noc_slave_sf_east_clk = { 4857 .halt_reg = 0xba2b8, 4858 .halt_check = BRANCH_HALT_VOTED, 4859 .hwcg_reg = 0xba2b8, 4860 .hwcg_bit = 1, 4861 .clkr = { 4862 .enable_reg = 0x62008, 4863 .enable_mask = BIT(9), 4864 .hw.init = &(const struct clk_init_data) { 4865 .name = "gcc_pcie_noc_slave_sf_east_clk", 4866 .ops = &clk_branch2_ops, 4867 }, 4868 }, 4869 }; 4870 4871 static struct clk_branch gcc_pcie_noc_slave_sf_west_clk = { 4872 .halt_reg = 0xba2c0, 4873 .halt_check = BRANCH_HALT_VOTED, 4874 .hwcg_reg = 0xba2c0, 4875 .hwcg_bit = 1, 4876 .clkr = { 4877 .enable_reg = 0x62008, 4878 .enable_mask = BIT(10), 4879 .hw.init = &(const struct clk_init_data) { 4880 .name = "gcc_pcie_noc_slave_sf_west_clk", 4881 .ops = &clk_branch2_ops, 4882 }, 4883 }, 4884 }; 4885 4886 static struct clk_branch gcc_pcie_noc_tsctr_clk = { 4887 .halt_reg = 0xba2a4, 4888 .halt_check = BRANCH_HALT_VOTED, 4889 .hwcg_reg = 0xba2a4, 4890 .hwcg_bit = 1, 4891 .clkr = { 4892 .enable_reg = 0x62008, 4893 .enable_mask = BIT(5), 4894 .hw.init = &(const struct clk_init_data) { 4895 .name = "gcc_pcie_noc_tsctr_clk", 4896 .ops = &clk_branch2_ops, 4897 }, 4898 }, 4899 }; 4900 4901 static struct clk_branch gcc_pcie_phy_3a_aux_clk = { 4902 .halt_reg = 0x6c038, 4903 .halt_check = BRANCH_HALT_VOTED, 4904 .hwcg_reg = 0x6c038, 4905 .hwcg_bit = 1, 4906 .clkr = { 4907 .enable_reg = 0x62028, 4908 .enable_mask = BIT(19), 4909 .hw.init = &(const struct clk_init_data) { 4910 .name = "gcc_pcie_phy_3a_aux_clk", 4911 .parent_hws = (const struct clk_hw*[]) { 4912 &gcc_pcie_phy_3a_aux_clk_src.clkr.hw, 4913 }, 4914 .num_parents = 1, 4915 .flags = CLK_SET_RATE_PARENT, 4916 .ops = &clk_branch2_ops, 4917 }, 4918 }, 4919 }; 4920 4921 static struct clk_branch gcc_pcie_phy_3b_aux_clk = { 4922 .halt_reg = 0x75034, 4923 .halt_check = BRANCH_HALT_VOTED, 4924 .clkr = { 4925 .enable_reg = 0x62028, 4926 .enable_mask = BIT(31), 4927 .hw.init = &(const struct clk_init_data) { 4928 .name = "gcc_pcie_phy_3b_aux_clk", 4929 .parent_hws = (const struct clk_hw*[]) { 4930 &gcc_pcie_phy_3b_aux_clk_src.clkr.hw, 4931 }, 4932 .num_parents = 1, 4933 .flags = CLK_SET_RATE_PARENT, 4934 .ops = &clk_branch2_ops, 4935 }, 4936 }, 4937 }; 4938 4939 static struct clk_branch gcc_pcie_phy_4_aux_clk = { 4940 .halt_reg = 0xd3030, 4941 .halt_check = BRANCH_HALT_VOTED, 4942 .clkr = { 4943 .enable_reg = 0x62030, 4944 .enable_mask = BIT(21), 4945 .hw.init = &(const struct clk_init_data) { 4946 .name = "gcc_pcie_phy_4_aux_clk", 4947 .parent_hws = (const struct clk_hw*[]) { 4948 &gcc_pcie_phy_4_aux_clk_src.clkr.hw, 4949 }, 4950 .num_parents = 1, 4951 .flags = CLK_SET_RATE_PARENT, 4952 .ops = &clk_branch2_ops, 4953 }, 4954 }, 4955 }; 4956 4957 static struct clk_branch gcc_pcie_phy_5_aux_clk = { 4958 .halt_reg = 0xd2030, 4959 .halt_check = BRANCH_HALT_VOTED, 4960 .clkr = { 4961 .enable_reg = 0x62030, 4962 .enable_mask = BIT(11), 4963 .hw.init = &(const struct clk_init_data) { 4964 .name = "gcc_pcie_phy_5_aux_clk", 4965 .parent_hws = (const struct clk_hw*[]) { 4966 &gcc_pcie_phy_5_aux_clk_src.clkr.hw, 4967 }, 4968 .num_parents = 1, 4969 .flags = CLK_SET_RATE_PARENT, 4970 .ops = &clk_branch2_ops, 4971 }, 4972 }, 4973 }; 4974 4975 static struct clk_branch gcc_pcie_phy_6_aux_clk = { 4976 .halt_reg = 0xd4030, 4977 .halt_check = BRANCH_HALT_VOTED, 4978 .clkr = { 4979 .enable_reg = 0x62030, 4980 .enable_mask = BIT(31), 4981 .hw.init = &(const struct clk_init_data) { 4982 .name = "gcc_pcie_phy_6_aux_clk", 4983 .parent_hws = (const struct clk_hw*[]) { 4984 &gcc_pcie_phy_6_aux_clk_src.clkr.hw, 4985 }, 4986 .num_parents = 1, 4987 .flags = CLK_SET_RATE_PARENT, 4988 .ops = &clk_branch2_ops, 4989 }, 4990 }, 4991 }; 4992 4993 static struct clk_branch gcc_pcie_rscc_cfg_ahb_clk = { 4994 .halt_reg = 0xb8004, 4995 .halt_check = BRANCH_HALT_VOTED, 4996 .hwcg_reg = 0xb8004, 4997 .hwcg_bit = 1, 4998 .clkr = { 4999 .enable_reg = 0x62038, 5000 .enable_mask = BIT(2), 5001 .hw.init = &(const struct clk_init_data) { 5002 .name = "gcc_pcie_rscc_cfg_ahb_clk", 5003 .ops = &clk_branch2_ops, 5004 }, 5005 }, 5006 }; 5007 5008 static struct clk_branch gcc_pcie_rscc_xo_clk = { 5009 .halt_reg = 0xb8008, 5010 .halt_check = BRANCH_HALT_VOTED, 5011 .clkr = { 5012 .enable_reg = 0x62038, 5013 .enable_mask = BIT(3), 5014 .hw.init = &(const struct clk_init_data) { 5015 .name = "gcc_pcie_rscc_xo_clk", 5016 .ops = &clk_branch2_ops, 5017 }, 5018 }, 5019 }; 5020 5021 static struct clk_branch gcc_pdm2_clk = { 5022 .halt_reg = 0x3300c, 5023 .halt_check = BRANCH_HALT, 5024 .clkr = { 5025 .enable_reg = 0x3300c, 5026 .enable_mask = BIT(0), 5027 .hw.init = &(const struct clk_init_data) { 5028 .name = "gcc_pdm2_clk", 5029 .parent_hws = (const struct clk_hw*[]) { 5030 &gcc_pdm2_clk_src.clkr.hw, 5031 }, 5032 .num_parents = 1, 5033 .flags = CLK_SET_RATE_PARENT, 5034 .ops = &clk_branch2_ops, 5035 }, 5036 }, 5037 }; 5038 5039 static struct clk_branch gcc_pdm_ahb_clk = { 5040 .halt_reg = 0x33004, 5041 .halt_check = BRANCH_HALT_VOTED, 5042 .hwcg_reg = 0x33004, 5043 .hwcg_bit = 1, 5044 .clkr = { 5045 .enable_reg = 0x33004, 5046 .enable_mask = BIT(0), 5047 .hw.init = &(const struct clk_init_data) { 5048 .name = "gcc_pdm_ahb_clk", 5049 .ops = &clk_branch2_ops, 5050 }, 5051 }, 5052 }; 5053 5054 static struct clk_branch gcc_pdm_xo4_clk = { 5055 .halt_reg = 0x33008, 5056 .halt_check = BRANCH_HALT, 5057 .clkr = { 5058 .enable_reg = 0x33008, 5059 .enable_mask = BIT(0), 5060 .hw.init = &(const struct clk_init_data) { 5061 .name = "gcc_pdm_xo4_clk", 5062 .ops = &clk_branch2_ops, 5063 }, 5064 }, 5065 }; 5066 5067 static struct clk_branch gcc_qmip_av1e_ahb_clk = { 5068 .halt_reg = 0x9b048, 5069 .halt_check = BRANCH_HALT_VOTED, 5070 .hwcg_reg = 0x9b048, 5071 .hwcg_bit = 1, 5072 .clkr = { 5073 .enable_reg = 0x9b048, 5074 .enable_mask = BIT(0), 5075 .hw.init = &(const struct clk_init_data) { 5076 .name = "gcc_qmip_av1e_ahb_clk", 5077 .ops = &clk_branch2_ops, 5078 }, 5079 }, 5080 }; 5081 5082 static struct clk_branch gcc_qmip_camera_cmd_ahb_clk = { 5083 .halt_reg = 0x26010, 5084 .halt_check = BRANCH_HALT_VOTED, 5085 .hwcg_reg = 0x26010, 5086 .hwcg_bit = 1, 5087 .clkr = { 5088 .enable_reg = 0x26010, 5089 .enable_mask = BIT(0), 5090 .hw.init = &(const struct clk_init_data) { 5091 .name = "gcc_qmip_camera_cmd_ahb_clk", 5092 .ops = &clk_branch2_ops, 5093 }, 5094 }, 5095 }; 5096 5097 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 5098 .halt_reg = 0x26008, 5099 .halt_check = BRANCH_HALT_VOTED, 5100 .hwcg_reg = 0x26008, 5101 .hwcg_bit = 1, 5102 .clkr = { 5103 .enable_reg = 0x26008, 5104 .enable_mask = BIT(0), 5105 .hw.init = &(const struct clk_init_data) { 5106 .name = "gcc_qmip_camera_nrt_ahb_clk", 5107 .ops = &clk_branch2_ops, 5108 }, 5109 }, 5110 }; 5111 5112 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 5113 .halt_reg = 0x2600c, 5114 .halt_check = BRANCH_HALT_VOTED, 5115 .hwcg_reg = 0x2600c, 5116 .hwcg_bit = 1, 5117 .clkr = { 5118 .enable_reg = 0x2600c, 5119 .enable_mask = BIT(0), 5120 .hw.init = &(const struct clk_init_data) { 5121 .name = "gcc_qmip_camera_rt_ahb_clk", 5122 .ops = &clk_branch2_ops, 5123 }, 5124 }, 5125 }; 5126 5127 static struct clk_branch gcc_qmip_gpu_ahb_clk = { 5128 .halt_reg = 0x71008, 5129 .halt_check = BRANCH_HALT_VOTED, 5130 .hwcg_reg = 0x71008, 5131 .hwcg_bit = 1, 5132 .clkr = { 5133 .enable_reg = 0x71008, 5134 .enable_mask = BIT(0), 5135 .hw.init = &(const struct clk_init_data) { 5136 .name = "gcc_qmip_gpu_ahb_clk", 5137 .ops = &clk_branch2_ops, 5138 }, 5139 }, 5140 }; 5141 5142 static struct clk_branch gcc_qmip_pcie_3a_ahb_clk = { 5143 .halt_reg = 0xdc018, 5144 .halt_check = BRANCH_HALT_VOTED, 5145 .hwcg_reg = 0xdc018, 5146 .hwcg_bit = 1, 5147 .clkr = { 5148 .enable_reg = 0x62028, 5149 .enable_mask = BIT(11), 5150 .hw.init = &(const struct clk_init_data) { 5151 .name = "gcc_qmip_pcie_3a_ahb_clk", 5152 .ops = &clk_branch2_ops, 5153 }, 5154 }, 5155 }; 5156 5157 static struct clk_branch gcc_qmip_pcie_3b_ahb_clk = { 5158 .halt_reg = 0x94018, 5159 .halt_check = BRANCH_HALT_VOTED, 5160 .hwcg_reg = 0x94018, 5161 .hwcg_bit = 1, 5162 .clkr = { 5163 .enable_reg = 0x62028, 5164 .enable_mask = BIT(20), 5165 .hw.init = &(const struct clk_init_data) { 5166 .name = "gcc_qmip_pcie_3b_ahb_clk", 5167 .ops = &clk_branch2_ops, 5168 }, 5169 }, 5170 }; 5171 5172 static struct clk_branch gcc_qmip_pcie_4_ahb_clk = { 5173 .halt_reg = 0x88018, 5174 .halt_check = BRANCH_HALT_VOTED, 5175 .hwcg_reg = 0x88018, 5176 .hwcg_bit = 1, 5177 .clkr = { 5178 .enable_reg = 0x62030, 5179 .enable_mask = BIT(12), 5180 .hw.init = &(const struct clk_init_data) { 5181 .name = "gcc_qmip_pcie_4_ahb_clk", 5182 .ops = &clk_branch2_ops, 5183 }, 5184 }, 5185 }; 5186 5187 static struct clk_branch gcc_qmip_pcie_5_ahb_clk = { 5188 .halt_reg = 0xc3018, 5189 .halt_check = BRANCH_HALT_VOTED, 5190 .hwcg_reg = 0xc3018, 5191 .hwcg_bit = 1, 5192 .clkr = { 5193 .enable_reg = 0x62030, 5194 .enable_mask = BIT(0), 5195 .hw.init = &(const struct clk_init_data) { 5196 .name = "gcc_qmip_pcie_5_ahb_clk", 5197 .ops = &clk_branch2_ops, 5198 }, 5199 }, 5200 }; 5201 5202 static struct clk_branch gcc_qmip_pcie_6_ahb_clk = { 5203 .halt_reg = 0x8a018, 5204 .halt_check = BRANCH_HALT_VOTED, 5205 .hwcg_reg = 0x8a018, 5206 .hwcg_bit = 1, 5207 .clkr = { 5208 .enable_reg = 0x62030, 5209 .enable_mask = BIT(22), 5210 .hw.init = &(const struct clk_init_data) { 5211 .name = "gcc_qmip_pcie_6_ahb_clk", 5212 .ops = &clk_branch2_ops, 5213 }, 5214 }, 5215 }; 5216 5217 static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = { 5218 .halt_reg = 0x32018, 5219 .halt_check = BRANCH_HALT_VOTED, 5220 .hwcg_reg = 0x32018, 5221 .hwcg_bit = 1, 5222 .clkr = { 5223 .enable_reg = 0x32018, 5224 .enable_mask = BIT(0), 5225 .hw.init = &(const struct clk_init_data) { 5226 .name = "gcc_qmip_video_cv_cpu_ahb_clk", 5227 .ops = &clk_branch2_ops, 5228 }, 5229 }, 5230 }; 5231 5232 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 5233 .halt_reg = 0x32008, 5234 .halt_check = BRANCH_HALT_VOTED, 5235 .hwcg_reg = 0x32008, 5236 .hwcg_bit = 1, 5237 .clkr = { 5238 .enable_reg = 0x32008, 5239 .enable_mask = BIT(0), 5240 .hw.init = &(const struct clk_init_data) { 5241 .name = "gcc_qmip_video_cvp_ahb_clk", 5242 .ops = &clk_branch2_ops, 5243 }, 5244 }, 5245 }; 5246 5247 static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = { 5248 .halt_reg = 0x32014, 5249 .halt_check = BRANCH_HALT_VOTED, 5250 .hwcg_reg = 0x32014, 5251 .hwcg_bit = 1, 5252 .clkr = { 5253 .enable_reg = 0x32014, 5254 .enable_mask = BIT(0), 5255 .hw.init = &(const struct clk_init_data) { 5256 .name = "gcc_qmip_video_v_cpu_ahb_clk", 5257 .ops = &clk_branch2_ops, 5258 }, 5259 }, 5260 }; 5261 5262 static struct clk_branch gcc_qmip_video_vcodec1_ahb_clk = { 5263 .halt_reg = 0x32010, 5264 .halt_check = BRANCH_HALT_VOTED, 5265 .hwcg_reg = 0x32010, 5266 .hwcg_bit = 1, 5267 .clkr = { 5268 .enable_reg = 0x32010, 5269 .enable_mask = BIT(0), 5270 .hw.init = &(const struct clk_init_data) { 5271 .name = "gcc_qmip_video_vcodec1_ahb_clk", 5272 .ops = &clk_branch2_ops, 5273 }, 5274 }, 5275 }; 5276 5277 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 5278 .halt_reg = 0x3200c, 5279 .halt_check = BRANCH_HALT_VOTED, 5280 .hwcg_reg = 0x3200c, 5281 .hwcg_bit = 1, 5282 .clkr = { 5283 .enable_reg = 0x3200c, 5284 .enable_mask = BIT(0), 5285 .hw.init = &(const struct clk_init_data) { 5286 .name = "gcc_qmip_video_vcodec_ahb_clk", 5287 .ops = &clk_branch2_ops, 5288 }, 5289 }, 5290 }; 5291 5292 static struct clk_branch gcc_qupv3_oob_core_2x_clk = { 5293 .halt_reg = 0xc5040, 5294 .halt_check = BRANCH_HALT_VOTED, 5295 .clkr = { 5296 .enable_reg = 0x62018, 5297 .enable_mask = BIT(5), 5298 .hw.init = &(const struct clk_init_data) { 5299 .name = "gcc_qupv3_oob_core_2x_clk", 5300 .ops = &clk_branch2_ops, 5301 }, 5302 }, 5303 }; 5304 5305 static struct clk_branch gcc_qupv3_oob_core_clk = { 5306 .halt_reg = 0xc502c, 5307 .halt_check = BRANCH_HALT_VOTED, 5308 .clkr = { 5309 .enable_reg = 0x62018, 5310 .enable_mask = BIT(4), 5311 .hw.init = &(const struct clk_init_data) { 5312 .name = "gcc_qupv3_oob_core_clk", 5313 .ops = &clk_branch2_ops, 5314 }, 5315 }, 5316 }; 5317 5318 static struct clk_branch gcc_qupv3_oob_m_ahb_clk = { 5319 .halt_reg = 0xe7004, 5320 .halt_check = BRANCH_HALT_VOTED, 5321 .hwcg_reg = 0xe7004, 5322 .hwcg_bit = 1, 5323 .clkr = { 5324 .enable_reg = 0xe7004, 5325 .enable_mask = BIT(0), 5326 .hw.init = &(const struct clk_init_data) { 5327 .name = "gcc_qupv3_oob_m_ahb_clk", 5328 .ops = &clk_branch2_ops, 5329 }, 5330 }, 5331 }; 5332 5333 static struct clk_branch gcc_qupv3_oob_qspi_s0_clk = { 5334 .halt_reg = 0xe7040, 5335 .halt_check = BRANCH_HALT_VOTED, 5336 .clkr = { 5337 .enable_reg = 0x62018, 5338 .enable_mask = BIT(9), 5339 .hw.init = &(const struct clk_init_data) { 5340 .name = "gcc_qupv3_oob_qspi_s0_clk", 5341 .parent_hws = (const struct clk_hw*[]) { 5342 &gcc_qupv3_oob_qspi_s0_clk_src.clkr.hw, 5343 }, 5344 .num_parents = 1, 5345 .flags = CLK_SET_RATE_PARENT, 5346 .ops = &clk_branch2_ops, 5347 }, 5348 }, 5349 }; 5350 5351 static struct clk_branch gcc_qupv3_oob_qspi_s1_clk = { 5352 .halt_reg = 0xe729c, 5353 .halt_check = BRANCH_HALT_VOTED, 5354 .clkr = { 5355 .enable_reg = 0x62018, 5356 .enable_mask = BIT(10), 5357 .hw.init = &(const struct clk_init_data) { 5358 .name = "gcc_qupv3_oob_qspi_s1_clk", 5359 .parent_hws = (const struct clk_hw*[]) { 5360 &gcc_qupv3_oob_qspi_s1_clk_src.clkr.hw, 5361 }, 5362 .num_parents = 1, 5363 .flags = CLK_SET_RATE_PARENT, 5364 .ops = &clk_branch2_ops, 5365 }, 5366 }, 5367 }; 5368 5369 static struct clk_branch gcc_qupv3_oob_s0_clk = { 5370 .halt_reg = 0xe7014, 5371 .halt_check = BRANCH_HALT_VOTED, 5372 .clkr = { 5373 .enable_reg = 0x62018, 5374 .enable_mask = BIT(6), 5375 .hw.init = &(const struct clk_init_data) { 5376 .name = "gcc_qupv3_oob_s0_clk", 5377 .parent_hws = (const struct clk_hw*[]) { 5378 &gcc_qupv3_oob_s0_clk_src.clkr.hw, 5379 }, 5380 .num_parents = 1, 5381 .flags = CLK_SET_RATE_PARENT, 5382 .ops = &clk_branch2_ops, 5383 }, 5384 }, 5385 }; 5386 5387 static struct clk_branch gcc_qupv3_oob_s1_clk = { 5388 .halt_reg = 0xe7028, 5389 .halt_check = BRANCH_HALT_VOTED, 5390 .clkr = { 5391 .enable_reg = 0x62018, 5392 .enable_mask = BIT(7), 5393 .hw.init = &(const struct clk_init_data) { 5394 .name = "gcc_qupv3_oob_s1_clk", 5395 .parent_hws = (const struct clk_hw*[]) { 5396 &gcc_qupv3_oob_s1_clk_src.clkr.hw, 5397 }, 5398 .num_parents = 1, 5399 .flags = CLK_SET_RATE_PARENT, 5400 .ops = &clk_branch2_ops, 5401 }, 5402 }, 5403 }; 5404 5405 static struct clk_branch gcc_qupv3_oob_s_ahb_clk = { 5406 .halt_reg = 0xc5028, 5407 .halt_check = BRANCH_HALT_VOTED, 5408 .hwcg_reg = 0xc5028, 5409 .hwcg_bit = 1, 5410 .clkr = { 5411 .enable_reg = 0x62018, 5412 .enable_mask = BIT(3), 5413 .hw.init = &(const struct clk_init_data) { 5414 .name = "gcc_qupv3_oob_s_ahb_clk", 5415 .ops = &clk_branch2_ops, 5416 }, 5417 }, 5418 }; 5419 5420 static struct clk_branch gcc_qupv3_oob_tcxo_clk = { 5421 .halt_reg = 0xe703c, 5422 .halt_check = BRANCH_HALT_VOTED, 5423 .clkr = { 5424 .enable_reg = 0x62018, 5425 .enable_mask = BIT(8), 5426 .hw.init = &(const struct clk_init_data) { 5427 .name = "gcc_qupv3_oob_tcxo_clk", 5428 .ops = &clk_branch2_ops, 5429 }, 5430 }, 5431 }; 5432 5433 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 5434 .halt_reg = 0xc5448, 5435 .halt_check = BRANCH_HALT_VOTED, 5436 .clkr = { 5437 .enable_reg = 0x62020, 5438 .enable_mask = BIT(12), 5439 .hw.init = &(const struct clk_init_data) { 5440 .name = "gcc_qupv3_wrap0_core_2x_clk", 5441 .ops = &clk_branch2_ops, 5442 }, 5443 }, 5444 }; 5445 5446 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 5447 .halt_reg = 0xc5434, 5448 .halt_check = BRANCH_HALT_VOTED, 5449 .clkr = { 5450 .enable_reg = 0x62020, 5451 .enable_mask = BIT(11), 5452 .hw.init = &(const struct clk_init_data) { 5453 .name = "gcc_qupv3_wrap0_core_clk", 5454 .ops = &clk_branch2_ops, 5455 }, 5456 }, 5457 }; 5458 5459 static struct clk_branch gcc_qupv3_wrap0_qspi_s2_clk = { 5460 .halt_reg = 0x2879c, 5461 .halt_check = BRANCH_HALT_VOTED, 5462 .clkr = { 5463 .enable_reg = 0x62020, 5464 .enable_mask = BIT(22), 5465 .hw.init = &(const struct clk_init_data) { 5466 .name = "gcc_qupv3_wrap0_qspi_s2_clk", 5467 .parent_hws = (const struct clk_hw*[]) { 5468 &gcc_qupv3_wrap0_qspi_s2_clk_src.clkr.hw, 5469 }, 5470 .num_parents = 1, 5471 .flags = CLK_SET_RATE_PARENT, 5472 .ops = &clk_branch2_ops, 5473 }, 5474 }, 5475 }; 5476 5477 static struct clk_branch gcc_qupv3_wrap0_qspi_s3_clk = { 5478 .halt_reg = 0x288cc, 5479 .halt_check = BRANCH_HALT_VOTED, 5480 .clkr = { 5481 .enable_reg = 0x62020, 5482 .enable_mask = BIT(23), 5483 .hw.init = &(const struct clk_init_data) { 5484 .name = "gcc_qupv3_wrap0_qspi_s3_clk", 5485 .parent_hws = (const struct clk_hw*[]) { 5486 &gcc_qupv3_wrap0_qspi_s3_clk_src.clkr.hw, 5487 }, 5488 .num_parents = 1, 5489 .flags = CLK_SET_RATE_PARENT, 5490 .ops = &clk_branch2_ops, 5491 }, 5492 }, 5493 }; 5494 5495 static struct clk_branch gcc_qupv3_wrap0_qspi_s6_clk = { 5496 .halt_reg = 0x28798, 5497 .halt_check = BRANCH_HALT_VOTED, 5498 .clkr = { 5499 .enable_reg = 0x62020, 5500 .enable_mask = BIT(21), 5501 .hw.init = &(const struct clk_init_data) { 5502 .name = "gcc_qupv3_wrap0_qspi_s6_clk", 5503 .parent_hws = (const struct clk_hw*[]) { 5504 &gcc_qupv3_wrap0_qspi_s6_clk_src.clkr.hw, 5505 }, 5506 .num_parents = 1, 5507 .flags = CLK_SET_RATE_PARENT, 5508 .ops = &clk_branch2_ops, 5509 }, 5510 }, 5511 }; 5512 5513 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 5514 .halt_reg = 0x28004, 5515 .halt_check = BRANCH_HALT_VOTED, 5516 .clkr = { 5517 .enable_reg = 0x62020, 5518 .enable_mask = BIT(13), 5519 .hw.init = &(const struct clk_init_data) { 5520 .name = "gcc_qupv3_wrap0_s0_clk", 5521 .parent_hws = (const struct clk_hw*[]) { 5522 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 5523 }, 5524 .num_parents = 1, 5525 .flags = CLK_SET_RATE_PARENT, 5526 .ops = &clk_branch2_ops, 5527 }, 5528 }, 5529 }; 5530 5531 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 5532 .halt_reg = 0x28140, 5533 .halt_check = BRANCH_HALT_VOTED, 5534 .clkr = { 5535 .enable_reg = 0x62020, 5536 .enable_mask = BIT(14), 5537 .hw.init = &(const struct clk_init_data) { 5538 .name = "gcc_qupv3_wrap0_s1_clk", 5539 .parent_hws = (const struct clk_hw*[]) { 5540 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 5541 }, 5542 .num_parents = 1, 5543 .flags = CLK_SET_RATE_PARENT, 5544 .ops = &clk_branch2_ops, 5545 }, 5546 }, 5547 }; 5548 5549 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 5550 .halt_reg = 0x2827c, 5551 .halt_check = BRANCH_HALT_VOTED, 5552 .clkr = { 5553 .enable_reg = 0x62020, 5554 .enable_mask = BIT(15), 5555 .hw.init = &(const struct clk_init_data) { 5556 .name = "gcc_qupv3_wrap0_s2_clk", 5557 .parent_hws = (const struct clk_hw*[]) { 5558 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 5559 }, 5560 .num_parents = 1, 5561 .flags = CLK_SET_RATE_PARENT, 5562 .ops = &clk_branch2_ops, 5563 }, 5564 }, 5565 }; 5566 5567 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 5568 .halt_reg = 0x28290, 5569 .halt_check = BRANCH_HALT_VOTED, 5570 .clkr = { 5571 .enable_reg = 0x62020, 5572 .enable_mask = BIT(16), 5573 .hw.init = &(const struct clk_init_data) { 5574 .name = "gcc_qupv3_wrap0_s3_clk", 5575 .parent_hws = (const struct clk_hw*[]) { 5576 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 5577 }, 5578 .num_parents = 1, 5579 .flags = CLK_SET_RATE_PARENT, 5580 .ops = &clk_branch2_ops, 5581 }, 5582 }, 5583 }; 5584 5585 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 5586 .halt_reg = 0x282a4, 5587 .halt_check = BRANCH_HALT_VOTED, 5588 .clkr = { 5589 .enable_reg = 0x62020, 5590 .enable_mask = BIT(17), 5591 .hw.init = &(const struct clk_init_data) { 5592 .name = "gcc_qupv3_wrap0_s4_clk", 5593 .parent_hws = (const struct clk_hw*[]) { 5594 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 5595 }, 5596 .num_parents = 1, 5597 .flags = CLK_SET_RATE_PARENT, 5598 .ops = &clk_branch2_ops, 5599 }, 5600 }, 5601 }; 5602 5603 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 5604 .halt_reg = 0x283e0, 5605 .halt_check = BRANCH_HALT_VOTED, 5606 .clkr = { 5607 .enable_reg = 0x62020, 5608 .enable_mask = BIT(18), 5609 .hw.init = &(const struct clk_init_data) { 5610 .name = "gcc_qupv3_wrap0_s5_clk", 5611 .parent_hws = (const struct clk_hw*[]) { 5612 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 5613 }, 5614 .num_parents = 1, 5615 .flags = CLK_SET_RATE_PARENT, 5616 .ops = &clk_branch2_ops, 5617 }, 5618 }, 5619 }; 5620 5621 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 5622 .halt_reg = 0x2851c, 5623 .halt_check = BRANCH_HALT_VOTED, 5624 .clkr = { 5625 .enable_reg = 0x62020, 5626 .enable_mask = BIT(19), 5627 .hw.init = &(const struct clk_init_data) { 5628 .name = "gcc_qupv3_wrap0_s6_clk", 5629 .parent_hws = (const struct clk_hw*[]) { 5630 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 5631 }, 5632 .num_parents = 1, 5633 .flags = CLK_SET_RATE_PARENT, 5634 .ops = &clk_branch2_ops, 5635 }, 5636 }, 5637 }; 5638 5639 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 5640 .halt_reg = 0x28530, 5641 .halt_check = BRANCH_HALT_VOTED, 5642 .clkr = { 5643 .enable_reg = 0x62020, 5644 .enable_mask = BIT(20), 5645 .hw.init = &(const struct clk_init_data) { 5646 .name = "gcc_qupv3_wrap0_s7_clk", 5647 .parent_hws = (const struct clk_hw*[]) { 5648 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, 5649 }, 5650 .num_parents = 1, 5651 .flags = CLK_SET_RATE_PARENT, 5652 .ops = &clk_branch2_ops, 5653 }, 5654 }, 5655 }; 5656 5657 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 5658 .halt_reg = 0xc5198, 5659 .halt_check = BRANCH_HALT_VOTED, 5660 .clkr = { 5661 .enable_reg = 0x62018, 5662 .enable_mask = BIT(14), 5663 .hw.init = &(const struct clk_init_data) { 5664 .name = "gcc_qupv3_wrap1_core_2x_clk", 5665 .ops = &clk_branch2_ops, 5666 }, 5667 }, 5668 }; 5669 5670 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 5671 .halt_reg = 0xc5184, 5672 .halt_check = BRANCH_HALT_VOTED, 5673 .clkr = { 5674 .enable_reg = 0x62018, 5675 .enable_mask = BIT(13), 5676 .hw.init = &(const struct clk_init_data) { 5677 .name = "gcc_qupv3_wrap1_core_clk", 5678 .ops = &clk_branch2_ops, 5679 }, 5680 }, 5681 }; 5682 5683 static struct clk_branch gcc_qupv3_wrap1_qspi_s2_clk = { 5684 .halt_reg = 0xb379c, 5685 .halt_check = BRANCH_HALT_VOTED, 5686 .clkr = { 5687 .enable_reg = 0x62018, 5688 .enable_mask = BIT(24), 5689 .hw.init = &(const struct clk_init_data) { 5690 .name = "gcc_qupv3_wrap1_qspi_s2_clk", 5691 .parent_hws = (const struct clk_hw*[]) { 5692 &gcc_qupv3_wrap1_qspi_s2_clk_src.clkr.hw, 5693 }, 5694 .num_parents = 1, 5695 .flags = CLK_SET_RATE_PARENT, 5696 .ops = &clk_branch2_ops, 5697 }, 5698 }, 5699 }; 5700 5701 static struct clk_branch gcc_qupv3_wrap1_qspi_s3_clk = { 5702 .halt_reg = 0xb38cc, 5703 .halt_check = BRANCH_HALT_VOTED, 5704 .clkr = { 5705 .enable_reg = 0x62018, 5706 .enable_mask = BIT(25), 5707 .hw.init = &(const struct clk_init_data) { 5708 .name = "gcc_qupv3_wrap1_qspi_s3_clk", 5709 .parent_hws = (const struct clk_hw*[]) { 5710 &gcc_qupv3_wrap1_qspi_s3_clk_src.clkr.hw, 5711 }, 5712 .num_parents = 1, 5713 .flags = CLK_SET_RATE_PARENT, 5714 .ops = &clk_branch2_ops, 5715 }, 5716 }, 5717 }; 5718 5719 static struct clk_branch gcc_qupv3_wrap1_qspi_s6_clk = { 5720 .halt_reg = 0xb3798, 5721 .halt_check = BRANCH_HALT_VOTED, 5722 .clkr = { 5723 .enable_reg = 0x62018, 5724 .enable_mask = BIT(23), 5725 .hw.init = &(const struct clk_init_data) { 5726 .name = "gcc_qupv3_wrap1_qspi_s6_clk", 5727 .parent_hws = (const struct clk_hw*[]) { 5728 &gcc_qupv3_wrap1_qspi_s6_clk_src.clkr.hw, 5729 }, 5730 .num_parents = 1, 5731 .flags = CLK_SET_RATE_PARENT, 5732 .ops = &clk_branch2_ops, 5733 }, 5734 }, 5735 }; 5736 5737 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 5738 .halt_reg = 0xb3004, 5739 .halt_check = BRANCH_HALT_VOTED, 5740 .clkr = { 5741 .enable_reg = 0x62018, 5742 .enable_mask = BIT(15), 5743 .hw.init = &(const struct clk_init_data) { 5744 .name = "gcc_qupv3_wrap1_s0_clk", 5745 .parent_hws = (const struct clk_hw*[]) { 5746 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 5747 }, 5748 .num_parents = 1, 5749 .flags = CLK_SET_RATE_PARENT, 5750 .ops = &clk_branch2_ops, 5751 }, 5752 }, 5753 }; 5754 5755 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 5756 .halt_reg = 0xb3140, 5757 .halt_check = BRANCH_HALT_VOTED, 5758 .clkr = { 5759 .enable_reg = 0x62018, 5760 .enable_mask = BIT(16), 5761 .hw.init = &(const struct clk_init_data) { 5762 .name = "gcc_qupv3_wrap1_s1_clk", 5763 .parent_hws = (const struct clk_hw*[]) { 5764 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 5765 }, 5766 .num_parents = 1, 5767 .flags = CLK_SET_RATE_PARENT, 5768 .ops = &clk_branch2_ops, 5769 }, 5770 }, 5771 }; 5772 5773 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 5774 .halt_reg = 0xb327c, 5775 .halt_check = BRANCH_HALT_VOTED, 5776 .clkr = { 5777 .enable_reg = 0x62018, 5778 .enable_mask = BIT(17), 5779 .hw.init = &(const struct clk_init_data) { 5780 .name = "gcc_qupv3_wrap1_s2_clk", 5781 .parent_hws = (const struct clk_hw*[]) { 5782 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 5783 }, 5784 .num_parents = 1, 5785 .flags = CLK_SET_RATE_PARENT, 5786 .ops = &clk_branch2_ops, 5787 }, 5788 }, 5789 }; 5790 5791 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 5792 .halt_reg = 0xb3290, 5793 .halt_check = BRANCH_HALT_VOTED, 5794 .clkr = { 5795 .enable_reg = 0x62018, 5796 .enable_mask = BIT(18), 5797 .hw.init = &(const struct clk_init_data) { 5798 .name = "gcc_qupv3_wrap1_s3_clk", 5799 .parent_hws = (const struct clk_hw*[]) { 5800 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 5801 }, 5802 .num_parents = 1, 5803 .flags = CLK_SET_RATE_PARENT, 5804 .ops = &clk_branch2_ops, 5805 }, 5806 }, 5807 }; 5808 5809 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 5810 .halt_reg = 0xb32a4, 5811 .halt_check = BRANCH_HALT_VOTED, 5812 .clkr = { 5813 .enable_reg = 0x62018, 5814 .enable_mask = BIT(19), 5815 .hw.init = &(const struct clk_init_data) { 5816 .name = "gcc_qupv3_wrap1_s4_clk", 5817 .parent_hws = (const struct clk_hw*[]) { 5818 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 5819 }, 5820 .num_parents = 1, 5821 .flags = CLK_SET_RATE_PARENT, 5822 .ops = &clk_branch2_ops, 5823 }, 5824 }, 5825 }; 5826 5827 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 5828 .halt_reg = 0xb33e0, 5829 .halt_check = BRANCH_HALT_VOTED, 5830 .clkr = { 5831 .enable_reg = 0x62018, 5832 .enable_mask = BIT(20), 5833 .hw.init = &(const struct clk_init_data) { 5834 .name = "gcc_qupv3_wrap1_s5_clk", 5835 .parent_hws = (const struct clk_hw*[]) { 5836 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 5837 }, 5838 .num_parents = 1, 5839 .flags = CLK_SET_RATE_PARENT, 5840 .ops = &clk_branch2_ops, 5841 }, 5842 }, 5843 }; 5844 5845 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 5846 .halt_reg = 0xb351c, 5847 .halt_check = BRANCH_HALT_VOTED, 5848 .clkr = { 5849 .enable_reg = 0x62018, 5850 .enable_mask = BIT(21), 5851 .hw.init = &(const struct clk_init_data) { 5852 .name = "gcc_qupv3_wrap1_s6_clk", 5853 .parent_hws = (const struct clk_hw*[]) { 5854 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 5855 }, 5856 .num_parents = 1, 5857 .flags = CLK_SET_RATE_PARENT, 5858 .ops = &clk_branch2_ops, 5859 }, 5860 }, 5861 }; 5862 5863 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 5864 .halt_reg = 0xb3530, 5865 .halt_check = BRANCH_HALT_VOTED, 5866 .clkr = { 5867 .enable_reg = 0x62018, 5868 .enable_mask = BIT(22), 5869 .hw.init = &(const struct clk_init_data) { 5870 .name = "gcc_qupv3_wrap1_s7_clk", 5871 .parent_hws = (const struct clk_hw*[]) { 5872 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 5873 }, 5874 .num_parents = 1, 5875 .flags = CLK_SET_RATE_PARENT, 5876 .ops = &clk_branch2_ops, 5877 }, 5878 }, 5879 }; 5880 5881 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { 5882 .halt_reg = 0xc52f0, 5883 .halt_check = BRANCH_HALT_VOTED, 5884 .clkr = { 5885 .enable_reg = 0x62018, 5886 .enable_mask = BIT(29), 5887 .hw.init = &(const struct clk_init_data) { 5888 .name = "gcc_qupv3_wrap2_core_2x_clk", 5889 .ops = &clk_branch2_ops, 5890 }, 5891 }, 5892 }; 5893 5894 static struct clk_branch gcc_qupv3_wrap2_core_clk = { 5895 .halt_reg = 0xc52dc, 5896 .halt_check = BRANCH_HALT_VOTED, 5897 .clkr = { 5898 .enable_reg = 0x62018, 5899 .enable_mask = BIT(28), 5900 .hw.init = &(const struct clk_init_data) { 5901 .name = "gcc_qupv3_wrap2_core_clk", 5902 .ops = &clk_branch2_ops, 5903 }, 5904 }, 5905 }; 5906 5907 static struct clk_branch gcc_qupv3_wrap2_qspi_s2_clk = { 5908 .halt_reg = 0xb479c, 5909 .halt_check = BRANCH_HALT_VOTED, 5910 .clkr = { 5911 .enable_reg = 0x62020, 5912 .enable_mask = BIT(7), 5913 .hw.init = &(const struct clk_init_data) { 5914 .name = "gcc_qupv3_wrap2_qspi_s2_clk", 5915 .parent_hws = (const struct clk_hw*[]) { 5916 &gcc_qupv3_wrap2_qspi_s2_clk_src.clkr.hw, 5917 }, 5918 .num_parents = 1, 5919 .flags = CLK_SET_RATE_PARENT, 5920 .ops = &clk_branch2_ops, 5921 }, 5922 }, 5923 }; 5924 5925 static struct clk_branch gcc_qupv3_wrap2_qspi_s3_clk = { 5926 .halt_reg = 0xb48cc, 5927 .halt_check = BRANCH_HALT_VOTED, 5928 .clkr = { 5929 .enable_reg = 0x62020, 5930 .enable_mask = BIT(8), 5931 .hw.init = &(const struct clk_init_data) { 5932 .name = "gcc_qupv3_wrap2_qspi_s3_clk", 5933 .parent_hws = (const struct clk_hw*[]) { 5934 &gcc_qupv3_wrap2_qspi_s3_clk_src.clkr.hw, 5935 }, 5936 .num_parents = 1, 5937 .flags = CLK_SET_RATE_PARENT, 5938 .ops = &clk_branch2_ops, 5939 }, 5940 }, 5941 }; 5942 5943 static struct clk_branch gcc_qupv3_wrap2_qspi_s6_clk = { 5944 .halt_reg = 0xb4798, 5945 .halt_check = BRANCH_HALT_VOTED, 5946 .clkr = { 5947 .enable_reg = 0x62020, 5948 .enable_mask = BIT(6), 5949 .hw.init = &(const struct clk_init_data) { 5950 .name = "gcc_qupv3_wrap2_qspi_s6_clk", 5951 .parent_hws = (const struct clk_hw*[]) { 5952 &gcc_qupv3_wrap2_qspi_s6_clk_src.clkr.hw, 5953 }, 5954 .num_parents = 1, 5955 .flags = CLK_SET_RATE_PARENT, 5956 .ops = &clk_branch2_ops, 5957 }, 5958 }, 5959 }; 5960 5961 static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 5962 .halt_reg = 0xb4004, 5963 .halt_check = BRANCH_HALT_VOTED, 5964 .clkr = { 5965 .enable_reg = 0x62018, 5966 .enable_mask = BIT(30), 5967 .hw.init = &(const struct clk_init_data) { 5968 .name = "gcc_qupv3_wrap2_s0_clk", 5969 .parent_hws = (const struct clk_hw*[]) { 5970 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 5971 }, 5972 .num_parents = 1, 5973 .flags = CLK_SET_RATE_PARENT, 5974 .ops = &clk_branch2_ops, 5975 }, 5976 }, 5977 }; 5978 5979 static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 5980 .halt_reg = 0xb4140, 5981 .halt_check = BRANCH_HALT_VOTED, 5982 .clkr = { 5983 .enable_reg = 0x62018, 5984 .enable_mask = BIT(31), 5985 .hw.init = &(const struct clk_init_data) { 5986 .name = "gcc_qupv3_wrap2_s1_clk", 5987 .parent_hws = (const struct clk_hw*[]) { 5988 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 5989 }, 5990 .num_parents = 1, 5991 .flags = CLK_SET_RATE_PARENT, 5992 .ops = &clk_branch2_ops, 5993 }, 5994 }, 5995 }; 5996 5997 static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 5998 .halt_reg = 0xb427c, 5999 .halt_check = BRANCH_HALT_VOTED, 6000 .clkr = { 6001 .enable_reg = 0x62020, 6002 .enable_mask = BIT(0), 6003 .hw.init = &(const struct clk_init_data) { 6004 .name = "gcc_qupv3_wrap2_s2_clk", 6005 .parent_hws = (const struct clk_hw*[]) { 6006 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 6007 }, 6008 .num_parents = 1, 6009 .flags = CLK_SET_RATE_PARENT, 6010 .ops = &clk_branch2_ops, 6011 }, 6012 }, 6013 }; 6014 6015 static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 6016 .halt_reg = 0xb4290, 6017 .halt_check = BRANCH_HALT_VOTED, 6018 .clkr = { 6019 .enable_reg = 0x62020, 6020 .enable_mask = BIT(1), 6021 .hw.init = &(const struct clk_init_data) { 6022 .name = "gcc_qupv3_wrap2_s3_clk", 6023 .parent_hws = (const struct clk_hw*[]) { 6024 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 6025 }, 6026 .num_parents = 1, 6027 .flags = CLK_SET_RATE_PARENT, 6028 .ops = &clk_branch2_ops, 6029 }, 6030 }, 6031 }; 6032 6033 static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 6034 .halt_reg = 0xb42a4, 6035 .halt_check = BRANCH_HALT_VOTED, 6036 .clkr = { 6037 .enable_reg = 0x62020, 6038 .enable_mask = BIT(2), 6039 .hw.init = &(const struct clk_init_data) { 6040 .name = "gcc_qupv3_wrap2_s4_clk", 6041 .parent_hws = (const struct clk_hw*[]) { 6042 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 6043 }, 6044 .num_parents = 1, 6045 .flags = CLK_SET_RATE_PARENT, 6046 .ops = &clk_branch2_ops, 6047 }, 6048 }, 6049 }; 6050 6051 static struct clk_branch gcc_qupv3_wrap2_s5_clk = { 6052 .halt_reg = 0xb43e0, 6053 .halt_check = BRANCH_HALT_VOTED, 6054 .clkr = { 6055 .enable_reg = 0x62020, 6056 .enable_mask = BIT(3), 6057 .hw.init = &(const struct clk_init_data) { 6058 .name = "gcc_qupv3_wrap2_s5_clk", 6059 .parent_hws = (const struct clk_hw*[]) { 6060 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, 6061 }, 6062 .num_parents = 1, 6063 .flags = CLK_SET_RATE_PARENT, 6064 .ops = &clk_branch2_ops, 6065 }, 6066 }, 6067 }; 6068 6069 static struct clk_branch gcc_qupv3_wrap2_s6_clk = { 6070 .halt_reg = 0xb451c, 6071 .halt_check = BRANCH_HALT_VOTED, 6072 .clkr = { 6073 .enable_reg = 0x62020, 6074 .enable_mask = BIT(4), 6075 .hw.init = &(const struct clk_init_data) { 6076 .name = "gcc_qupv3_wrap2_s6_clk", 6077 .parent_hws = (const struct clk_hw*[]) { 6078 &gcc_qupv3_wrap2_s6_clk_src.clkr.hw, 6079 }, 6080 .num_parents = 1, 6081 .flags = CLK_SET_RATE_PARENT, 6082 .ops = &clk_branch2_ops, 6083 }, 6084 }, 6085 }; 6086 6087 static struct clk_branch gcc_qupv3_wrap2_s7_clk = { 6088 .halt_reg = 0xb4530, 6089 .halt_check = BRANCH_HALT_VOTED, 6090 .clkr = { 6091 .enable_reg = 0x62020, 6092 .enable_mask = BIT(5), 6093 .hw.init = &(const struct clk_init_data) { 6094 .name = "gcc_qupv3_wrap2_s7_clk", 6095 .parent_hws = (const struct clk_hw*[]) { 6096 &gcc_qupv3_wrap2_s7_clk_src.clkr.hw, 6097 }, 6098 .num_parents = 1, 6099 .flags = CLK_SET_RATE_PARENT, 6100 .ops = &clk_branch2_ops, 6101 }, 6102 }, 6103 }; 6104 6105 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 6106 .halt_reg = 0xc542c, 6107 .halt_check = BRANCH_HALT_VOTED, 6108 .hwcg_reg = 0xc542c, 6109 .hwcg_bit = 1, 6110 .clkr = { 6111 .enable_reg = 0x62020, 6112 .enable_mask = BIT(9), 6113 .hw.init = &(const struct clk_init_data) { 6114 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 6115 .ops = &clk_branch2_ops, 6116 }, 6117 }, 6118 }; 6119 6120 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 6121 .halt_reg = 0xc5430, 6122 .halt_check = BRANCH_HALT_VOTED, 6123 .hwcg_reg = 0xc5430, 6124 .hwcg_bit = 1, 6125 .clkr = { 6126 .enable_reg = 0x62020, 6127 .enable_mask = BIT(10), 6128 .hw.init = &(const struct clk_init_data) { 6129 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 6130 .ops = &clk_branch2_ops, 6131 }, 6132 }, 6133 }; 6134 6135 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 6136 .halt_reg = 0xc517c, 6137 .halt_check = BRANCH_HALT_VOTED, 6138 .hwcg_reg = 0xc517c, 6139 .hwcg_bit = 1, 6140 .clkr = { 6141 .enable_reg = 0x62018, 6142 .enable_mask = BIT(11), 6143 .hw.init = &(const struct clk_init_data) { 6144 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 6145 .ops = &clk_branch2_ops, 6146 }, 6147 }, 6148 }; 6149 6150 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 6151 .halt_reg = 0xc5180, 6152 .halt_check = BRANCH_HALT_VOTED, 6153 .hwcg_reg = 0xc5180, 6154 .hwcg_bit = 1, 6155 .clkr = { 6156 .enable_reg = 0x62018, 6157 .enable_mask = BIT(12), 6158 .hw.init = &(const struct clk_init_data) { 6159 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 6160 .ops = &clk_branch2_ops, 6161 }, 6162 }, 6163 }; 6164 6165 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 6166 .halt_reg = 0xc52d4, 6167 .halt_check = BRANCH_HALT_VOTED, 6168 .hwcg_reg = 0xc52d4, 6169 .hwcg_bit = 1, 6170 .clkr = { 6171 .enable_reg = 0x62018, 6172 .enable_mask = BIT(26), 6173 .hw.init = &(const struct clk_init_data) { 6174 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 6175 .ops = &clk_branch2_ops, 6176 }, 6177 }, 6178 }; 6179 6180 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 6181 .halt_reg = 0xc52d8, 6182 .halt_check = BRANCH_HALT_VOTED, 6183 .hwcg_reg = 0xc52d8, 6184 .hwcg_bit = 1, 6185 .clkr = { 6186 .enable_reg = 0x62018, 6187 .enable_mask = BIT(27), 6188 .hw.init = &(const struct clk_init_data) { 6189 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 6190 .ops = &clk_branch2_ops, 6191 }, 6192 }, 6193 }; 6194 6195 static struct clk_branch gcc_sdcc2_ahb_clk = { 6196 .halt_reg = 0xb0014, 6197 .halt_check = BRANCH_HALT, 6198 .clkr = { 6199 .enable_reg = 0xb0014, 6200 .enable_mask = BIT(0), 6201 .hw.init = &(const struct clk_init_data) { 6202 .name = "gcc_sdcc2_ahb_clk", 6203 .ops = &clk_branch2_ops, 6204 }, 6205 }, 6206 }; 6207 6208 static struct clk_branch gcc_sdcc2_apps_clk = { 6209 .halt_reg = 0xb0004, 6210 .halt_check = BRANCH_HALT, 6211 .clkr = { 6212 .enable_reg = 0xb0004, 6213 .enable_mask = BIT(0), 6214 .hw.init = &(const struct clk_init_data) { 6215 .name = "gcc_sdcc2_apps_clk", 6216 .parent_hws = (const struct clk_hw*[]) { 6217 &gcc_sdcc2_apps_clk_src.clkr.hw, 6218 }, 6219 .num_parents = 1, 6220 .flags = CLK_SET_RATE_PARENT, 6221 .ops = &clk_branch2_ops, 6222 }, 6223 }, 6224 }; 6225 6226 static struct clk_branch gcc_sdcc4_ahb_clk = { 6227 .halt_reg = 0xdf014, 6228 .halt_check = BRANCH_HALT, 6229 .clkr = { 6230 .enable_reg = 0xdf014, 6231 .enable_mask = BIT(0), 6232 .hw.init = &(const struct clk_init_data) { 6233 .name = "gcc_sdcc4_ahb_clk", 6234 .ops = &clk_branch2_ops, 6235 }, 6236 }, 6237 }; 6238 6239 static struct clk_branch gcc_sdcc4_apps_clk = { 6240 .halt_reg = 0xdf004, 6241 .halt_check = BRANCH_HALT, 6242 .clkr = { 6243 .enable_reg = 0xdf004, 6244 .enable_mask = BIT(0), 6245 .hw.init = &(const struct clk_init_data) { 6246 .name = "gcc_sdcc4_apps_clk", 6247 .parent_hws = (const struct clk_hw*[]) { 6248 &gcc_sdcc4_apps_clk_src.clkr.hw, 6249 }, 6250 .num_parents = 1, 6251 .flags = CLK_SET_RATE_PARENT, 6252 .ops = &clk_branch2_ops, 6253 }, 6254 }, 6255 }; 6256 6257 static struct clk_branch gcc_ufs_phy_ahb_clk = { 6258 .halt_reg = 0xba504, 6259 .halt_check = BRANCH_HALT_VOTED, 6260 .hwcg_reg = 0xba504, 6261 .hwcg_bit = 1, 6262 .clkr = { 6263 .enable_reg = 0xba504, 6264 .enable_mask = BIT(0), 6265 .hw.init = &(const struct clk_init_data) { 6266 .name = "gcc_ufs_phy_ahb_clk", 6267 .ops = &clk_branch2_ops, 6268 }, 6269 }, 6270 }; 6271 6272 static struct clk_branch gcc_ufs_phy_axi_clk = { 6273 .halt_reg = 0x7701c, 6274 .halt_check = BRANCH_HALT_VOTED, 6275 .hwcg_reg = 0x7701c, 6276 .hwcg_bit = 1, 6277 .clkr = { 6278 .enable_reg = 0x7701c, 6279 .enable_mask = BIT(0), 6280 .hw.init = &(const struct clk_init_data) { 6281 .name = "gcc_ufs_phy_axi_clk", 6282 .parent_hws = (const struct clk_hw*[]) { 6283 &gcc_ufs_phy_axi_clk_src.clkr.hw, 6284 }, 6285 .num_parents = 1, 6286 .flags = CLK_SET_RATE_PARENT, 6287 .ops = &clk_branch2_ops, 6288 }, 6289 }, 6290 }; 6291 6292 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 6293 .halt_reg = 0x77080, 6294 .halt_check = BRANCH_HALT_VOTED, 6295 .hwcg_reg = 0x77080, 6296 .hwcg_bit = 1, 6297 .clkr = { 6298 .enable_reg = 0x77080, 6299 .enable_mask = BIT(0), 6300 .hw.init = &(const struct clk_init_data) { 6301 .name = "gcc_ufs_phy_ice_core_clk", 6302 .parent_hws = (const struct clk_hw*[]) { 6303 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 6304 }, 6305 .num_parents = 1, 6306 .flags = CLK_SET_RATE_PARENT, 6307 .ops = &clk_branch2_ops, 6308 }, 6309 }, 6310 }; 6311 6312 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 6313 .halt_reg = 0x770c0, 6314 .halt_check = BRANCH_HALT_VOTED, 6315 .hwcg_reg = 0x770c0, 6316 .hwcg_bit = 1, 6317 .clkr = { 6318 .enable_reg = 0x770c0, 6319 .enable_mask = BIT(0), 6320 .hw.init = &(const struct clk_init_data) { 6321 .name = "gcc_ufs_phy_phy_aux_clk", 6322 .parent_hws = (const struct clk_hw*[]) { 6323 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 6324 }, 6325 .num_parents = 1, 6326 .flags = CLK_SET_RATE_PARENT, 6327 .ops = &clk_branch2_ops, 6328 }, 6329 }, 6330 }; 6331 6332 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 6333 .halt_reg = 0x77034, 6334 .halt_check = BRANCH_HALT_DELAY, 6335 .clkr = { 6336 .enable_reg = 0x77034, 6337 .enable_mask = BIT(0), 6338 .hw.init = &(const struct clk_init_data) { 6339 .name = "gcc_ufs_phy_rx_symbol_0_clk", 6340 .parent_hws = (const struct clk_hw*[]) { 6341 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, 6342 }, 6343 .num_parents = 1, 6344 .flags = CLK_SET_RATE_PARENT, 6345 .ops = &clk_branch2_ops, 6346 }, 6347 }, 6348 }; 6349 6350 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 6351 .halt_reg = 0x770dc, 6352 .halt_check = BRANCH_HALT_DELAY, 6353 .clkr = { 6354 .enable_reg = 0x770dc, 6355 .enable_mask = BIT(0), 6356 .hw.init = &(const struct clk_init_data) { 6357 .name = "gcc_ufs_phy_rx_symbol_1_clk", 6358 .parent_hws = (const struct clk_hw*[]) { 6359 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, 6360 }, 6361 .num_parents = 1, 6362 .flags = CLK_SET_RATE_PARENT, 6363 .ops = &clk_branch2_ops, 6364 }, 6365 }, 6366 }; 6367 6368 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 6369 .halt_reg = 0x77030, 6370 .halt_check = BRANCH_HALT_DELAY, 6371 .clkr = { 6372 .enable_reg = 0x77030, 6373 .enable_mask = BIT(0), 6374 .hw.init = &(const struct clk_init_data) { 6375 .name = "gcc_ufs_phy_tx_symbol_0_clk", 6376 .parent_hws = (const struct clk_hw*[]) { 6377 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, 6378 }, 6379 .num_parents = 1, 6380 .flags = CLK_SET_RATE_PARENT, 6381 .ops = &clk_branch2_ops, 6382 }, 6383 }, 6384 }; 6385 6386 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 6387 .halt_reg = 0x77070, 6388 .halt_check = BRANCH_HALT_VOTED, 6389 .hwcg_reg = 0x77070, 6390 .hwcg_bit = 1, 6391 .clkr = { 6392 .enable_reg = 0x77070, 6393 .enable_mask = BIT(0), 6394 .hw.init = &(const struct clk_init_data) { 6395 .name = "gcc_ufs_phy_unipro_core_clk", 6396 .parent_hws = (const struct clk_hw*[]) { 6397 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 6398 }, 6399 .num_parents = 1, 6400 .flags = CLK_SET_RATE_PARENT, 6401 .ops = &clk_branch2_ops, 6402 }, 6403 }, 6404 }; 6405 6406 static struct clk_branch gcc_usb20_master_clk = { 6407 .halt_reg = 0xbc018, 6408 .halt_check = BRANCH_HALT, 6409 .clkr = { 6410 .enable_reg = 0xbc018, 6411 .enable_mask = BIT(0), 6412 .hw.init = &(const struct clk_init_data) { 6413 .name = "gcc_usb20_master_clk", 6414 .parent_hws = (const struct clk_hw*[]) { 6415 &gcc_usb20_master_clk_src.clkr.hw, 6416 }, 6417 .num_parents = 1, 6418 .flags = CLK_SET_RATE_PARENT, 6419 .ops = &clk_branch2_ops, 6420 }, 6421 }, 6422 }; 6423 6424 static struct clk_branch gcc_usb20_mock_utmi_clk = { 6425 .halt_reg = 0xbc02c, 6426 .halt_check = BRANCH_HALT, 6427 .clkr = { 6428 .enable_reg = 0xbc02c, 6429 .enable_mask = BIT(0), 6430 .hw.init = &(const struct clk_init_data) { 6431 .name = "gcc_usb20_mock_utmi_clk", 6432 .parent_hws = (const struct clk_hw*[]) { 6433 &gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw, 6434 }, 6435 .num_parents = 1, 6436 .flags = CLK_SET_RATE_PARENT, 6437 .ops = &clk_branch2_ops, 6438 }, 6439 }, 6440 }; 6441 6442 static struct clk_branch gcc_usb20_sleep_clk = { 6443 .halt_reg = 0xbc028, 6444 .halt_check = BRANCH_HALT, 6445 .clkr = { 6446 .enable_reg = 0xbc028, 6447 .enable_mask = BIT(0), 6448 .hw.init = &(const struct clk_init_data) { 6449 .name = "gcc_usb20_sleep_clk", 6450 .ops = &clk_branch2_ops, 6451 }, 6452 }, 6453 }; 6454 6455 static struct clk_branch gcc_usb30_mp_master_clk = { 6456 .halt_reg = 0x9a024, 6457 .halt_check = BRANCH_HALT, 6458 .clkr = { 6459 .enable_reg = 0x9a024, 6460 .enable_mask = BIT(0), 6461 .hw.init = &(const struct clk_init_data) { 6462 .name = "gcc_usb30_mp_master_clk", 6463 .parent_hws = (const struct clk_hw*[]) { 6464 &gcc_usb30_mp_master_clk_src.clkr.hw, 6465 }, 6466 .num_parents = 1, 6467 .flags = CLK_SET_RATE_PARENT, 6468 .ops = &clk_branch2_ops, 6469 }, 6470 }, 6471 }; 6472 6473 static struct clk_branch gcc_usb30_mp_mock_utmi_clk = { 6474 .halt_reg = 0x9a038, 6475 .halt_check = BRANCH_HALT, 6476 .clkr = { 6477 .enable_reg = 0x9a038, 6478 .enable_mask = BIT(0), 6479 .hw.init = &(const struct clk_init_data) { 6480 .name = "gcc_usb30_mp_mock_utmi_clk", 6481 .parent_hws = (const struct clk_hw*[]) { 6482 &gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr.hw, 6483 }, 6484 .num_parents = 1, 6485 .flags = CLK_SET_RATE_PARENT, 6486 .ops = &clk_branch2_ops, 6487 }, 6488 }, 6489 }; 6490 6491 static struct clk_branch gcc_usb30_mp_sleep_clk = { 6492 .halt_reg = 0x9a034, 6493 .halt_check = BRANCH_HALT, 6494 .clkr = { 6495 .enable_reg = 0x9a034, 6496 .enable_mask = BIT(0), 6497 .hw.init = &(const struct clk_init_data) { 6498 .name = "gcc_usb30_mp_sleep_clk", 6499 .ops = &clk_branch2_ops, 6500 }, 6501 }, 6502 }; 6503 6504 static struct clk_branch gcc_usb30_prim_master_clk = { 6505 .halt_reg = 0x3f030, 6506 .halt_check = BRANCH_HALT, 6507 .clkr = { 6508 .enable_reg = 0x3f030, 6509 .enable_mask = BIT(0), 6510 .hw.init = &(const struct clk_init_data) { 6511 .name = "gcc_usb30_prim_master_clk", 6512 .parent_hws = (const struct clk_hw*[]) { 6513 &gcc_usb30_prim_master_clk_src.clkr.hw, 6514 }, 6515 .num_parents = 1, 6516 .flags = CLK_SET_RATE_PARENT, 6517 .ops = &clk_branch2_ops, 6518 }, 6519 }, 6520 }; 6521 6522 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 6523 .halt_reg = 0x3f048, 6524 .halt_check = BRANCH_HALT, 6525 .clkr = { 6526 .enable_reg = 0x3f048, 6527 .enable_mask = BIT(0), 6528 .hw.init = &(const struct clk_init_data) { 6529 .name = "gcc_usb30_prim_mock_utmi_clk", 6530 .parent_hws = (const struct clk_hw*[]) { 6531 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 6532 }, 6533 .num_parents = 1, 6534 .flags = CLK_SET_RATE_PARENT, 6535 .ops = &clk_branch2_ops, 6536 }, 6537 }, 6538 }; 6539 6540 static struct clk_branch gcc_usb30_prim_sleep_clk = { 6541 .halt_reg = 0x3f044, 6542 .halt_check = BRANCH_HALT, 6543 .clkr = { 6544 .enable_reg = 0x3f044, 6545 .enable_mask = BIT(0), 6546 .hw.init = &(const struct clk_init_data) { 6547 .name = "gcc_usb30_prim_sleep_clk", 6548 .ops = &clk_branch2_ops, 6549 }, 6550 }, 6551 }; 6552 6553 static struct clk_branch gcc_usb30_sec_master_clk = { 6554 .halt_reg = 0xe2024, 6555 .halt_check = BRANCH_HALT, 6556 .clkr = { 6557 .enable_reg = 0xe2024, 6558 .enable_mask = BIT(0), 6559 .hw.init = &(const struct clk_init_data) { 6560 .name = "gcc_usb30_sec_master_clk", 6561 .parent_hws = (const struct clk_hw*[]) { 6562 &gcc_usb30_sec_master_clk_src.clkr.hw, 6563 }, 6564 .num_parents = 1, 6565 .flags = CLK_SET_RATE_PARENT, 6566 .ops = &clk_branch2_ops, 6567 }, 6568 }, 6569 }; 6570 6571 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { 6572 .halt_reg = 0xe2038, 6573 .halt_check = BRANCH_HALT, 6574 .clkr = { 6575 .enable_reg = 0xe2038, 6576 .enable_mask = BIT(0), 6577 .hw.init = &(const struct clk_init_data) { 6578 .name = "gcc_usb30_sec_mock_utmi_clk", 6579 .parent_hws = (const struct clk_hw*[]) { 6580 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw, 6581 }, 6582 .num_parents = 1, 6583 .flags = CLK_SET_RATE_PARENT, 6584 .ops = &clk_branch2_ops, 6585 }, 6586 }, 6587 }; 6588 6589 static struct clk_branch gcc_usb30_sec_sleep_clk = { 6590 .halt_reg = 0xe2034, 6591 .halt_check = BRANCH_HALT, 6592 .clkr = { 6593 .enable_reg = 0xe2034, 6594 .enable_mask = BIT(0), 6595 .hw.init = &(const struct clk_init_data) { 6596 .name = "gcc_usb30_sec_sleep_clk", 6597 .ops = &clk_branch2_ops, 6598 }, 6599 }, 6600 }; 6601 6602 static struct clk_branch gcc_usb30_tert_master_clk = { 6603 .halt_reg = 0xe1024, 6604 .halt_check = BRANCH_HALT, 6605 .clkr = { 6606 .enable_reg = 0xe1024, 6607 .enable_mask = BIT(0), 6608 .hw.init = &(const struct clk_init_data) { 6609 .name = "gcc_usb30_tert_master_clk", 6610 .parent_hws = (const struct clk_hw*[]) { 6611 &gcc_usb30_tert_master_clk_src.clkr.hw, 6612 }, 6613 .num_parents = 1, 6614 .flags = CLK_SET_RATE_PARENT, 6615 .ops = &clk_branch2_ops, 6616 }, 6617 }, 6618 }; 6619 6620 static struct clk_branch gcc_usb30_tert_mock_utmi_clk = { 6621 .halt_reg = 0xe1038, 6622 .halt_check = BRANCH_HALT, 6623 .clkr = { 6624 .enable_reg = 0xe1038, 6625 .enable_mask = BIT(0), 6626 .hw.init = &(const struct clk_init_data) { 6627 .name = "gcc_usb30_tert_mock_utmi_clk", 6628 .parent_hws = (const struct clk_hw*[]) { 6629 &gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr.hw, 6630 }, 6631 .num_parents = 1, 6632 .flags = CLK_SET_RATE_PARENT, 6633 .ops = &clk_branch2_ops, 6634 }, 6635 }, 6636 }; 6637 6638 static struct clk_branch gcc_usb30_tert_sleep_clk = { 6639 .halt_reg = 0xe1034, 6640 .halt_check = BRANCH_HALT, 6641 .clkr = { 6642 .enable_reg = 0xe1034, 6643 .enable_mask = BIT(0), 6644 .hw.init = &(const struct clk_init_data) { 6645 .name = "gcc_usb30_tert_sleep_clk", 6646 .ops = &clk_branch2_ops, 6647 }, 6648 }, 6649 }; 6650 6651 static struct clk_branch gcc_usb3_mp_phy_aux_clk = { 6652 .halt_reg = 0x9a070, 6653 .halt_check = BRANCH_HALT, 6654 .clkr = { 6655 .enable_reg = 0x9a070, 6656 .enable_mask = BIT(0), 6657 .hw.init = &(const struct clk_init_data) { 6658 .name = "gcc_usb3_mp_phy_aux_clk", 6659 .parent_hws = (const struct clk_hw*[]) { 6660 &gcc_usb3_mp_phy_aux_clk_src.clkr.hw, 6661 }, 6662 .num_parents = 1, 6663 .flags = CLK_SET_RATE_PARENT, 6664 .ops = &clk_branch2_ops, 6665 }, 6666 }, 6667 }; 6668 6669 static struct clk_branch gcc_usb3_mp_phy_com_aux_clk = { 6670 .halt_reg = 0x9a074, 6671 .halt_check = BRANCH_HALT, 6672 .clkr = { 6673 .enable_reg = 0x9a074, 6674 .enable_mask = BIT(0), 6675 .hw.init = &(const struct clk_init_data) { 6676 .name = "gcc_usb3_mp_phy_com_aux_clk", 6677 .parent_hws = (const struct clk_hw*[]) { 6678 &gcc_usb3_mp_phy_aux_clk_src.clkr.hw, 6679 }, 6680 .num_parents = 1, 6681 .flags = CLK_SET_RATE_PARENT, 6682 .ops = &clk_branch2_ops, 6683 }, 6684 }, 6685 }; 6686 6687 static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = { 6688 .halt_reg = 0x9a078, 6689 .halt_check = BRANCH_HALT_SKIP, 6690 .clkr = { 6691 .enable_reg = 0x9a078, 6692 .enable_mask = BIT(0), 6693 .hw.init = &(const struct clk_init_data) { 6694 .name = "gcc_usb3_mp_phy_pipe_0_clk", 6695 .parent_hws = (const struct clk_hw*[]) { 6696 &gcc_usb3_mp_phy_pipe_0_clk_src.clkr.hw, 6697 }, 6698 .num_parents = 1, 6699 .flags = CLK_SET_RATE_PARENT, 6700 .ops = &clk_branch2_ops, 6701 }, 6702 }, 6703 }; 6704 6705 static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = { 6706 .halt_reg = 0x9a080, 6707 .halt_check = BRANCH_HALT_SKIP, 6708 .clkr = { 6709 .enable_reg = 0x9a080, 6710 .enable_mask = BIT(0), 6711 .hw.init = &(const struct clk_init_data) { 6712 .name = "gcc_usb3_mp_phy_pipe_1_clk", 6713 .parent_hws = (const struct clk_hw*[]) { 6714 &gcc_usb3_mp_phy_pipe_1_clk_src.clkr.hw, 6715 }, 6716 .num_parents = 1, 6717 .flags = CLK_SET_RATE_PARENT, 6718 .ops = &clk_branch2_ops, 6719 }, 6720 }, 6721 }; 6722 6723 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 6724 .halt_reg = 0x3f080, 6725 .halt_check = BRANCH_HALT, 6726 .clkr = { 6727 .enable_reg = 0x3f080, 6728 .enable_mask = BIT(0), 6729 .hw.init = &(const struct clk_init_data) { 6730 .name = "gcc_usb3_prim_phy_aux_clk", 6731 .parent_hws = (const struct clk_hw*[]) { 6732 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 6733 }, 6734 .num_parents = 1, 6735 .flags = CLK_SET_RATE_PARENT, 6736 .ops = &clk_branch2_ops, 6737 }, 6738 }, 6739 }; 6740 6741 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 6742 .halt_reg = 0x3f084, 6743 .halt_check = BRANCH_HALT, 6744 .clkr = { 6745 .enable_reg = 0x3f084, 6746 .enable_mask = BIT(0), 6747 .hw.init = &(const struct clk_init_data) { 6748 .name = "gcc_usb3_prim_phy_com_aux_clk", 6749 .parent_hws = (const struct clk_hw*[]) { 6750 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 6751 }, 6752 .num_parents = 1, 6753 .flags = CLK_SET_RATE_PARENT, 6754 .ops = &clk_branch2_ops, 6755 }, 6756 }, 6757 }; 6758 6759 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 6760 .halt_reg = 0x3f088, 6761 .halt_check = BRANCH_HALT_SKIP, 6762 .hwcg_reg = 0x3f088, 6763 .hwcg_bit = 1, 6764 .clkr = { 6765 .enable_reg = 0x3f088, 6766 .enable_mask = BIT(0), 6767 .hw.init = &(const struct clk_init_data) { 6768 .name = "gcc_usb3_prim_phy_pipe_clk", 6769 .parent_hws = (const struct clk_hw*[]) { 6770 &gcc_usb34_prim_phy_pipe_clk_src.clkr.hw, 6771 }, 6772 .num_parents = 1, 6773 .flags = CLK_SET_RATE_PARENT, 6774 .ops = &clk_branch2_ops, 6775 }, 6776 }, 6777 }; 6778 6779 static struct clk_branch gcc_usb3_sec_phy_aux_clk = { 6780 .halt_reg = 0xe2070, 6781 .halt_check = BRANCH_HALT, 6782 .clkr = { 6783 .enable_reg = 0xe2070, 6784 .enable_mask = BIT(0), 6785 .hw.init = &(const struct clk_init_data) { 6786 .name = "gcc_usb3_sec_phy_aux_clk", 6787 .parent_hws = (const struct clk_hw*[]) { 6788 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 6789 }, 6790 .num_parents = 1, 6791 .flags = CLK_SET_RATE_PARENT, 6792 .ops = &clk_branch2_ops, 6793 }, 6794 }, 6795 }; 6796 6797 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { 6798 .halt_reg = 0xe2074, 6799 .halt_check = BRANCH_HALT, 6800 .clkr = { 6801 .enable_reg = 0xe2074, 6802 .enable_mask = BIT(0), 6803 .hw.init = &(const struct clk_init_data) { 6804 .name = "gcc_usb3_sec_phy_com_aux_clk", 6805 .parent_hws = (const struct clk_hw*[]) { 6806 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 6807 }, 6808 .num_parents = 1, 6809 .flags = CLK_SET_RATE_PARENT, 6810 .ops = &clk_branch2_ops, 6811 }, 6812 }, 6813 }; 6814 6815 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { 6816 .halt_reg = 0xe2078, 6817 .halt_check = BRANCH_HALT_SKIP, 6818 .hwcg_reg = 0xe2078, 6819 .hwcg_bit = 1, 6820 .clkr = { 6821 .enable_reg = 0xe2078, 6822 .enable_mask = BIT(0), 6823 .hw.init = &(const struct clk_init_data) { 6824 .name = "gcc_usb3_sec_phy_pipe_clk", 6825 .parent_hws = (const struct clk_hw*[]) { 6826 &gcc_usb34_sec_phy_pipe_clk_src.clkr.hw, 6827 }, 6828 .num_parents = 1, 6829 .flags = CLK_SET_RATE_PARENT, 6830 .ops = &clk_branch2_ops, 6831 }, 6832 }, 6833 }; 6834 6835 static struct clk_branch gcc_usb3_tert_phy_aux_clk = { 6836 .halt_reg = 0xe1070, 6837 .halt_check = BRANCH_HALT, 6838 .clkr = { 6839 .enable_reg = 0xe1070, 6840 .enable_mask = BIT(0), 6841 .hw.init = &(const struct clk_init_data) { 6842 .name = "gcc_usb3_tert_phy_aux_clk", 6843 .parent_hws = (const struct clk_hw*[]) { 6844 &gcc_usb3_tert_phy_aux_clk_src.clkr.hw, 6845 }, 6846 .num_parents = 1, 6847 .flags = CLK_SET_RATE_PARENT, 6848 .ops = &clk_branch2_ops, 6849 }, 6850 }, 6851 }; 6852 6853 static struct clk_branch gcc_usb3_tert_phy_com_aux_clk = { 6854 .halt_reg = 0xe1074, 6855 .halt_check = BRANCH_HALT, 6856 .clkr = { 6857 .enable_reg = 0xe1074, 6858 .enable_mask = BIT(0), 6859 .hw.init = &(const struct clk_init_data) { 6860 .name = "gcc_usb3_tert_phy_com_aux_clk", 6861 .parent_hws = (const struct clk_hw*[]) { 6862 &gcc_usb3_tert_phy_aux_clk_src.clkr.hw, 6863 }, 6864 .num_parents = 1, 6865 .flags = CLK_SET_RATE_PARENT, 6866 .ops = &clk_branch2_ops, 6867 }, 6868 }, 6869 }; 6870 6871 static struct clk_branch gcc_usb3_tert_phy_pipe_clk = { 6872 .halt_reg = 0xe1078, 6873 .halt_check = BRANCH_HALT_SKIP, 6874 .hwcg_reg = 0xe1078, 6875 .hwcg_bit = 1, 6876 .clkr = { 6877 .enable_reg = 0xe1078, 6878 .enable_mask = BIT(0), 6879 .hw.init = &(const struct clk_init_data) { 6880 .name = "gcc_usb3_tert_phy_pipe_clk", 6881 .parent_hws = (const struct clk_hw*[]) { 6882 &gcc_usb34_tert_phy_pipe_clk_src.clkr.hw, 6883 }, 6884 .num_parents = 1, 6885 .flags = CLK_SET_RATE_PARENT, 6886 .ops = &clk_branch2_ops, 6887 }, 6888 }, 6889 }; 6890 6891 static struct clk_branch gcc_usb4_0_cfg_ahb_clk = { 6892 .halt_reg = 0xba450, 6893 .halt_check = BRANCH_HALT_VOTED, 6894 .hwcg_reg = 0xba450, 6895 .hwcg_bit = 1, 6896 .clkr = { 6897 .enable_reg = 0xba450, 6898 .enable_mask = BIT(0), 6899 .hw.init = &(const struct clk_init_data) { 6900 .name = "gcc_usb4_0_cfg_ahb_clk", 6901 .ops = &clk_branch2_ops, 6902 }, 6903 }, 6904 }; 6905 6906 static struct clk_branch gcc_usb4_0_dp0_clk = { 6907 .halt_reg = 0x2b070, 6908 .halt_check = BRANCH_HALT, 6909 .clkr = { 6910 .enable_reg = 0x2b070, 6911 .enable_mask = BIT(0), 6912 .hw.init = &(const struct clk_init_data) { 6913 .name = "gcc_usb4_0_dp0_clk", 6914 .parent_hws = (const struct clk_hw*[]) { 6915 &gcc_usb4_0_phy_dp0_clk_src.clkr.hw, 6916 }, 6917 .num_parents = 1, 6918 .flags = CLK_SET_RATE_PARENT, 6919 .ops = &clk_branch2_ops, 6920 }, 6921 }, 6922 }; 6923 6924 static struct clk_branch gcc_usb4_0_dp1_clk = { 6925 .halt_reg = 0x2b124, 6926 .halt_check = BRANCH_HALT, 6927 .clkr = { 6928 .enable_reg = 0x2b124, 6929 .enable_mask = BIT(0), 6930 .hw.init = &(const struct clk_init_data) { 6931 .name = "gcc_usb4_0_dp1_clk", 6932 .parent_hws = (const struct clk_hw*[]) { 6933 &gcc_usb4_0_phy_dp1_clk_src.clkr.hw, 6934 }, 6935 .num_parents = 1, 6936 .flags = CLK_SET_RATE_PARENT, 6937 .ops = &clk_branch2_ops, 6938 }, 6939 }, 6940 }; 6941 6942 static struct clk_branch gcc_usb4_0_master_clk = { 6943 .halt_reg = 0x2b01c, 6944 .halt_check = BRANCH_HALT, 6945 .clkr = { 6946 .enable_reg = 0x2b01c, 6947 .enable_mask = BIT(0), 6948 .hw.init = &(const struct clk_init_data) { 6949 .name = "gcc_usb4_0_master_clk", 6950 .parent_hws = (const struct clk_hw*[]) { 6951 &gcc_usb4_0_master_clk_src.clkr.hw, 6952 }, 6953 .num_parents = 1, 6954 .flags = CLK_SET_RATE_PARENT, 6955 .ops = &clk_branch2_ops, 6956 }, 6957 }, 6958 }; 6959 6960 static struct clk_branch gcc_usb4_0_phy_p2rr2p_pipe_clk = { 6961 .halt_reg = 0x2b0f4, 6962 .halt_check = BRANCH_HALT_SKIP, 6963 .clkr = { 6964 .enable_reg = 0x2b0f4, 6965 .enable_mask = BIT(0), 6966 .hw.init = &(const struct clk_init_data) { 6967 .name = "gcc_usb4_0_phy_p2rr2p_pipe_clk", 6968 .parent_hws = (const struct clk_hw*[]) { 6969 &gcc_usb4_0_phy_p2rr2p_pipe_clk_src.clkr.hw, 6970 }, 6971 .num_parents = 1, 6972 .flags = CLK_SET_RATE_PARENT, 6973 .ops = &clk_branch2_ops, 6974 }, 6975 }, 6976 }; 6977 6978 static struct clk_branch gcc_usb4_0_phy_pcie_pipe_clk = { 6979 .halt_reg = 0x2b04c, 6980 .halt_check = BRANCH_HALT_SKIP, 6981 .clkr = { 6982 .enable_reg = 0x62010, 6983 .enable_mask = BIT(11), 6984 .hw.init = &(const struct clk_init_data) { 6985 .name = "gcc_usb4_0_phy_pcie_pipe_clk", 6986 .parent_hws = (const struct clk_hw*[]) { 6987 &gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr.hw, 6988 }, 6989 .num_parents = 1, 6990 .flags = CLK_SET_RATE_PARENT, 6991 .ops = &clk_branch2_ops, 6992 }, 6993 }, 6994 }; 6995 6996 static struct clk_branch gcc_usb4_0_phy_rx0_clk = { 6997 .halt_reg = 0x2b0c4, 6998 .halt_check = BRANCH_HALT, 6999 .clkr = { 7000 .enable_reg = 0x2b0c4, 7001 .enable_mask = BIT(0), 7002 .hw.init = &(const struct clk_init_data) { 7003 .name = "gcc_usb4_0_phy_rx0_clk", 7004 .parent_hws = (const struct clk_hw*[]) { 7005 &gcc_usb4_0_phy_rx0_clk_src.clkr.hw, 7006 }, 7007 .num_parents = 1, 7008 .flags = CLK_SET_RATE_PARENT, 7009 .ops = &clk_branch2_ops, 7010 }, 7011 }, 7012 }; 7013 7014 static struct clk_branch gcc_usb4_0_phy_rx1_clk = { 7015 .halt_reg = 0x2b0d8, 7016 .halt_check = BRANCH_HALT, 7017 .clkr = { 7018 .enable_reg = 0x2b0d8, 7019 .enable_mask = BIT(0), 7020 .hw.init = &(const struct clk_init_data) { 7021 .name = "gcc_usb4_0_phy_rx1_clk", 7022 .parent_hws = (const struct clk_hw*[]) { 7023 &gcc_usb4_0_phy_rx1_clk_src.clkr.hw, 7024 }, 7025 .num_parents = 1, 7026 .flags = CLK_SET_RATE_PARENT, 7027 .ops = &clk_branch2_ops, 7028 }, 7029 }, 7030 }; 7031 7032 static struct clk_branch gcc_usb4_0_phy_usb_pipe_clk = { 7033 .halt_reg = 0x2b0bc, 7034 .halt_check = BRANCH_HALT_SKIP, 7035 .hwcg_reg = 0x2b0bc, 7036 .hwcg_bit = 1, 7037 .clkr = { 7038 .enable_reg = 0x2b0bc, 7039 .enable_mask = BIT(0), 7040 .hw.init = &(const struct clk_init_data) { 7041 .name = "gcc_usb4_0_phy_usb_pipe_clk", 7042 .parent_hws = (const struct clk_hw*[]) { 7043 &gcc_usb34_prim_phy_pipe_clk_src.clkr.hw, 7044 }, 7045 .num_parents = 1, 7046 .flags = CLK_SET_RATE_PARENT, 7047 .ops = &clk_branch2_ops, 7048 }, 7049 }, 7050 }; 7051 7052 static struct clk_branch gcc_usb4_0_sb_if_clk = { 7053 .halt_reg = 0x2b048, 7054 .halt_check = BRANCH_HALT, 7055 .clkr = { 7056 .enable_reg = 0x2b048, 7057 .enable_mask = BIT(0), 7058 .hw.init = &(const struct clk_init_data) { 7059 .name = "gcc_usb4_0_sb_if_clk", 7060 .parent_hws = (const struct clk_hw*[]) { 7061 &gcc_usb4_0_sb_if_clk_src.clkr.hw, 7062 }, 7063 .num_parents = 1, 7064 .flags = CLK_SET_RATE_PARENT, 7065 .ops = &clk_branch2_ops, 7066 }, 7067 }, 7068 }; 7069 7070 static struct clk_branch gcc_usb4_0_sys_clk = { 7071 .halt_reg = 0x2b05c, 7072 .halt_check = BRANCH_HALT, 7073 .clkr = { 7074 .enable_reg = 0x2b05c, 7075 .enable_mask = BIT(0), 7076 .hw.init = &(const struct clk_init_data) { 7077 .name = "gcc_usb4_0_sys_clk", 7078 .parent_hws = (const struct clk_hw*[]) { 7079 &gcc_usb4_0_phy_sys_clk_src.clkr.hw, 7080 }, 7081 .num_parents = 1, 7082 .flags = CLK_SET_RATE_PARENT, 7083 .ops = &clk_branch2_ops, 7084 }, 7085 }, 7086 }; 7087 7088 static struct clk_branch gcc_usb4_0_tmu_clk = { 7089 .halt_reg = 0x2b09c, 7090 .halt_check = BRANCH_HALT_VOTED, 7091 .hwcg_reg = 0x2b09c, 7092 .hwcg_bit = 1, 7093 .clkr = { 7094 .enable_reg = 0x2b09c, 7095 .enable_mask = BIT(0), 7096 .hw.init = &(const struct clk_init_data) { 7097 .name = "gcc_usb4_0_tmu_clk", 7098 .parent_hws = (const struct clk_hw*[]) { 7099 &gcc_usb4_0_tmu_clk_src.clkr.hw, 7100 }, 7101 .num_parents = 1, 7102 .flags = CLK_SET_RATE_PARENT, 7103 .ops = &clk_branch2_ops, 7104 }, 7105 }, 7106 }; 7107 7108 static struct clk_branch gcc_usb4_0_uc_hrr_clk = { 7109 .halt_reg = 0x2b06c, 7110 .halt_check = BRANCH_HALT, 7111 .clkr = { 7112 .enable_reg = 0x2b06c, 7113 .enable_mask = BIT(0), 7114 .hw.init = &(const struct clk_init_data) { 7115 .name = "gcc_usb4_0_uc_hrr_clk", 7116 .parent_hws = (const struct clk_hw*[]) { 7117 &gcc_usb4_0_phy_sys_clk_src.clkr.hw, 7118 }, 7119 .num_parents = 1, 7120 .flags = CLK_SET_RATE_PARENT, 7121 .ops = &clk_branch2_ops, 7122 }, 7123 }, 7124 }; 7125 7126 static struct clk_branch gcc_usb4_1_cfg_ahb_clk = { 7127 .halt_reg = 0xba454, 7128 .halt_check = BRANCH_HALT_VOTED, 7129 .hwcg_reg = 0xba454, 7130 .hwcg_bit = 1, 7131 .clkr = { 7132 .enable_reg = 0xba454, 7133 .enable_mask = BIT(0), 7134 .hw.init = &(const struct clk_init_data) { 7135 .name = "gcc_usb4_1_cfg_ahb_clk", 7136 .ops = &clk_branch2_ops, 7137 }, 7138 }, 7139 }; 7140 7141 static struct clk_branch gcc_usb4_1_dp0_clk = { 7142 .halt_reg = 0x2d07c, 7143 .halt_check = BRANCH_HALT, 7144 .clkr = { 7145 .enable_reg = 0x2d07c, 7146 .enable_mask = BIT(0), 7147 .hw.init = &(const struct clk_init_data) { 7148 .name = "gcc_usb4_1_dp0_clk", 7149 .parent_hws = (const struct clk_hw*[]) { 7150 &gcc_usb4_1_phy_dp0_clk_src.clkr.hw, 7151 }, 7152 .num_parents = 1, 7153 .flags = CLK_SET_RATE_PARENT, 7154 .ops = &clk_branch2_ops, 7155 }, 7156 }, 7157 }; 7158 7159 static struct clk_branch gcc_usb4_1_dp1_clk = { 7160 .halt_reg = 0x2d144, 7161 .halt_check = BRANCH_HALT, 7162 .clkr = { 7163 .enable_reg = 0x2d144, 7164 .enable_mask = BIT(0), 7165 .hw.init = &(const struct clk_init_data) { 7166 .name = "gcc_usb4_1_dp1_clk", 7167 .parent_hws = (const struct clk_hw*[]) { 7168 &gcc_usb4_1_phy_dp1_clk_src.clkr.hw, 7169 }, 7170 .num_parents = 1, 7171 .flags = CLK_SET_RATE_PARENT, 7172 .ops = &clk_branch2_ops, 7173 }, 7174 }, 7175 }; 7176 7177 static struct clk_branch gcc_usb4_1_master_clk = { 7178 .halt_reg = 0x2d01c, 7179 .halt_check = BRANCH_HALT, 7180 .clkr = { 7181 .enable_reg = 0x2d01c, 7182 .enable_mask = BIT(0), 7183 .hw.init = &(const struct clk_init_data) { 7184 .name = "gcc_usb4_1_master_clk", 7185 .parent_hws = (const struct clk_hw*[]) { 7186 &gcc_usb4_1_master_clk_src.clkr.hw, 7187 }, 7188 .num_parents = 1, 7189 .flags = CLK_SET_RATE_PARENT, 7190 .ops = &clk_branch2_ops, 7191 }, 7192 }, 7193 }; 7194 7195 static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = { 7196 .halt_reg = 0x2d118, 7197 .halt_check = BRANCH_HALT_SKIP, 7198 .clkr = { 7199 .enable_reg = 0x2d118, 7200 .enable_mask = BIT(0), 7201 .hw.init = &(const struct clk_init_data) { 7202 .name = "gcc_usb4_1_phy_p2rr2p_pipe_clk", 7203 .parent_hws = (const struct clk_hw*[]) { 7204 &gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr.hw, 7205 }, 7206 .num_parents = 1, 7207 .flags = CLK_SET_RATE_PARENT, 7208 .ops = &clk_branch2_ops, 7209 }, 7210 }, 7211 }; 7212 7213 static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk = { 7214 .halt_reg = 0x2d04c, 7215 .halt_check = BRANCH_HALT_SKIP, 7216 .clkr = { 7217 .enable_reg = 0x62010, 7218 .enable_mask = BIT(12), 7219 .hw.init = &(const struct clk_init_data) { 7220 .name = "gcc_usb4_1_phy_pcie_pipe_clk", 7221 .parent_hws = (const struct clk_hw*[]) { 7222 &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw, 7223 }, 7224 .num_parents = 1, 7225 .flags = CLK_SET_RATE_PARENT, 7226 .ops = &clk_branch2_ops, 7227 }, 7228 }, 7229 }; 7230 7231 static struct clk_branch gcc_usb4_1_phy_rx0_clk = { 7232 .halt_reg = 0x2d0e8, 7233 .halt_check = BRANCH_HALT, 7234 .clkr = { 7235 .enable_reg = 0x2d0e8, 7236 .enable_mask = BIT(0), 7237 .hw.init = &(const struct clk_init_data) { 7238 .name = "gcc_usb4_1_phy_rx0_clk", 7239 .parent_hws = (const struct clk_hw*[]) { 7240 &gcc_usb4_1_phy_rx0_clk_src.clkr.hw, 7241 }, 7242 .num_parents = 1, 7243 .flags = CLK_SET_RATE_PARENT, 7244 .ops = &clk_branch2_ops, 7245 }, 7246 }, 7247 }; 7248 7249 static struct clk_branch gcc_usb4_1_phy_rx1_clk = { 7250 .halt_reg = 0x2d0fc, 7251 .halt_check = BRANCH_HALT, 7252 .clkr = { 7253 .enable_reg = 0x2d0fc, 7254 .enable_mask = BIT(0), 7255 .hw.init = &(const struct clk_init_data) { 7256 .name = "gcc_usb4_1_phy_rx1_clk", 7257 .parent_hws = (const struct clk_hw*[]) { 7258 &gcc_usb4_1_phy_rx1_clk_src.clkr.hw, 7259 }, 7260 .num_parents = 1, 7261 .flags = CLK_SET_RATE_PARENT, 7262 .ops = &clk_branch2_ops, 7263 }, 7264 }, 7265 }; 7266 7267 static struct clk_branch gcc_usb4_1_phy_usb_pipe_clk = { 7268 .halt_reg = 0x2d0e0, 7269 .halt_check = BRANCH_HALT_SKIP, 7270 .hwcg_reg = 0x2d0e0, 7271 .hwcg_bit = 1, 7272 .clkr = { 7273 .enable_reg = 0x2d0e0, 7274 .enable_mask = BIT(0), 7275 .hw.init = &(const struct clk_init_data) { 7276 .name = "gcc_usb4_1_phy_usb_pipe_clk", 7277 .parent_hws = (const struct clk_hw*[]) { 7278 &gcc_usb34_sec_phy_pipe_clk_src.clkr.hw, 7279 }, 7280 .num_parents = 1, 7281 .flags = CLK_SET_RATE_PARENT, 7282 .ops = &clk_branch2_ops, 7283 }, 7284 }, 7285 }; 7286 7287 static struct clk_branch gcc_usb4_1_sb_if_clk = { 7288 .halt_reg = 0x2d048, 7289 .halt_check = BRANCH_HALT, 7290 .clkr = { 7291 .enable_reg = 0x2d048, 7292 .enable_mask = BIT(0), 7293 .hw.init = &(const struct clk_init_data) { 7294 .name = "gcc_usb4_1_sb_if_clk", 7295 .parent_hws = (const struct clk_hw*[]) { 7296 &gcc_usb4_1_sb_if_clk_src.clkr.hw, 7297 }, 7298 .num_parents = 1, 7299 .flags = CLK_SET_RATE_PARENT, 7300 .ops = &clk_branch2_ops, 7301 }, 7302 }, 7303 }; 7304 7305 static struct clk_branch gcc_usb4_1_sys_clk = { 7306 .halt_reg = 0x2d05c, 7307 .halt_check = BRANCH_HALT, 7308 .clkr = { 7309 .enable_reg = 0x2d05c, 7310 .enable_mask = BIT(0), 7311 .hw.init = &(const struct clk_init_data) { 7312 .name = "gcc_usb4_1_sys_clk", 7313 .parent_hws = (const struct clk_hw*[]) { 7314 &gcc_usb4_1_phy_sys_clk_src.clkr.hw, 7315 }, 7316 .num_parents = 1, 7317 .flags = CLK_SET_RATE_PARENT, 7318 .ops = &clk_branch2_ops, 7319 }, 7320 }, 7321 }; 7322 7323 static struct clk_branch gcc_usb4_1_tmu_clk = { 7324 .halt_reg = 0x2d0a8, 7325 .halt_check = BRANCH_HALT_VOTED, 7326 .hwcg_reg = 0x2d0a8, 7327 .hwcg_bit = 1, 7328 .clkr = { 7329 .enable_reg = 0x2d0a8, 7330 .enable_mask = BIT(0), 7331 .hw.init = &(const struct clk_init_data) { 7332 .name = "gcc_usb4_1_tmu_clk", 7333 .parent_hws = (const struct clk_hw*[]) { 7334 &gcc_usb4_1_tmu_clk_src.clkr.hw, 7335 }, 7336 .num_parents = 1, 7337 .flags = CLK_SET_RATE_PARENT, 7338 .ops = &clk_branch2_ops, 7339 }, 7340 }, 7341 }; 7342 7343 static struct clk_branch gcc_usb4_1_uc_hrr_clk = { 7344 .halt_reg = 0x2d06c, 7345 .halt_check = BRANCH_HALT, 7346 .clkr = { 7347 .enable_reg = 0x2d06c, 7348 .enable_mask = BIT(0), 7349 .hw.init = &(const struct clk_init_data) { 7350 .name = "gcc_usb4_1_uc_hrr_clk", 7351 .parent_hws = (const struct clk_hw*[]) { 7352 &gcc_usb4_1_phy_sys_clk_src.clkr.hw, 7353 }, 7354 .num_parents = 1, 7355 .flags = CLK_SET_RATE_PARENT, 7356 .ops = &clk_branch2_ops, 7357 }, 7358 }, 7359 }; 7360 7361 static struct clk_branch gcc_usb4_2_cfg_ahb_clk = { 7362 .halt_reg = 0xba458, 7363 .halt_check = BRANCH_HALT_VOTED, 7364 .hwcg_reg = 0xba458, 7365 .hwcg_bit = 1, 7366 .clkr = { 7367 .enable_reg = 0xba458, 7368 .enable_mask = BIT(0), 7369 .hw.init = &(const struct clk_init_data) { 7370 .name = "gcc_usb4_2_cfg_ahb_clk", 7371 .ops = &clk_branch2_ops, 7372 }, 7373 }, 7374 }; 7375 7376 static struct clk_branch gcc_usb4_2_dp0_clk = { 7377 .halt_reg = 0xe0070, 7378 .halt_check = BRANCH_HALT, 7379 .clkr = { 7380 .enable_reg = 0xe0070, 7381 .enable_mask = BIT(0), 7382 .hw.init = &(const struct clk_init_data) { 7383 .name = "gcc_usb4_2_dp0_clk", 7384 .parent_hws = (const struct clk_hw*[]) { 7385 &gcc_usb4_2_phy_dp0_clk_src.clkr.hw, 7386 }, 7387 .num_parents = 1, 7388 .flags = CLK_SET_RATE_PARENT, 7389 .ops = &clk_branch2_ops, 7390 }, 7391 }, 7392 }; 7393 7394 static struct clk_branch gcc_usb4_2_dp1_clk = { 7395 .halt_reg = 0xe0128, 7396 .halt_check = BRANCH_HALT, 7397 .clkr = { 7398 .enable_reg = 0xe0128, 7399 .enable_mask = BIT(0), 7400 .hw.init = &(const struct clk_init_data) { 7401 .name = "gcc_usb4_2_dp1_clk", 7402 .parent_hws = (const struct clk_hw*[]) { 7403 &gcc_usb4_2_phy_dp1_clk_src.clkr.hw, 7404 }, 7405 .num_parents = 1, 7406 .flags = CLK_SET_RATE_PARENT, 7407 .ops = &clk_branch2_ops, 7408 }, 7409 }, 7410 }; 7411 7412 static struct clk_branch gcc_usb4_2_master_clk = { 7413 .halt_reg = 0xe001c, 7414 .halt_check = BRANCH_HALT, 7415 .clkr = { 7416 .enable_reg = 0xe001c, 7417 .enable_mask = BIT(0), 7418 .hw.init = &(const struct clk_init_data) { 7419 .name = "gcc_usb4_2_master_clk", 7420 .parent_hws = (const struct clk_hw*[]) { 7421 &gcc_usb4_2_master_clk_src.clkr.hw, 7422 }, 7423 .num_parents = 1, 7424 .flags = CLK_SET_RATE_PARENT, 7425 .ops = &clk_branch2_ops, 7426 }, 7427 }, 7428 }; 7429 7430 static struct clk_branch gcc_usb4_2_phy_p2rr2p_pipe_clk = { 7431 .halt_reg = 0xe00f8, 7432 .halt_check = BRANCH_HALT_SKIP, 7433 .clkr = { 7434 .enable_reg = 0xe00f8, 7435 .enable_mask = BIT(0), 7436 .hw.init = &(const struct clk_init_data) { 7437 .name = "gcc_usb4_2_phy_p2rr2p_pipe_clk", 7438 .parent_hws = (const struct clk_hw*[]) { 7439 &gcc_usb4_2_phy_p2rr2p_pipe_clk_src.clkr.hw, 7440 }, 7441 .num_parents = 1, 7442 .flags = CLK_SET_RATE_PARENT, 7443 .ops = &clk_branch2_ops, 7444 }, 7445 }, 7446 }; 7447 7448 static struct clk_branch gcc_usb4_2_phy_pcie_pipe_clk = { 7449 .halt_reg = 0xe004c, 7450 .halt_check = BRANCH_HALT_SKIP, 7451 .clkr = { 7452 .enable_reg = 0x62010, 7453 .enable_mask = BIT(13), 7454 .hw.init = &(const struct clk_init_data) { 7455 .name = "gcc_usb4_2_phy_pcie_pipe_clk", 7456 .parent_hws = (const struct clk_hw*[]) { 7457 &gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr.hw, 7458 }, 7459 .num_parents = 1, 7460 .flags = CLK_SET_RATE_PARENT, 7461 .ops = &clk_branch2_ops, 7462 }, 7463 }, 7464 }; 7465 7466 static struct clk_branch gcc_usb4_2_phy_rx0_clk = { 7467 .halt_reg = 0xe00c8, 7468 .halt_check = BRANCH_HALT, 7469 .clkr = { 7470 .enable_reg = 0xe00c8, 7471 .enable_mask = BIT(0), 7472 .hw.init = &(const struct clk_init_data) { 7473 .name = "gcc_usb4_2_phy_rx0_clk", 7474 .parent_hws = (const struct clk_hw*[]) { 7475 &gcc_usb4_2_phy_rx0_clk_src.clkr.hw, 7476 }, 7477 .num_parents = 1, 7478 .flags = CLK_SET_RATE_PARENT, 7479 .ops = &clk_branch2_ops, 7480 }, 7481 }, 7482 }; 7483 7484 static struct clk_branch gcc_usb4_2_phy_rx1_clk = { 7485 .halt_reg = 0xe00dc, 7486 .halt_check = BRANCH_HALT, 7487 .clkr = { 7488 .enable_reg = 0xe00dc, 7489 .enable_mask = BIT(0), 7490 .hw.init = &(const struct clk_init_data) { 7491 .name = "gcc_usb4_2_phy_rx1_clk", 7492 .parent_hws = (const struct clk_hw*[]) { 7493 &gcc_usb4_2_phy_rx1_clk_src.clkr.hw, 7494 }, 7495 .num_parents = 1, 7496 .flags = CLK_SET_RATE_PARENT, 7497 .ops = &clk_branch2_ops, 7498 }, 7499 }, 7500 }; 7501 7502 static struct clk_branch gcc_usb4_2_phy_usb_pipe_clk = { 7503 .halt_reg = 0xe00c0, 7504 .halt_check = BRANCH_HALT_SKIP, 7505 .hwcg_reg = 0xe00c0, 7506 .hwcg_bit = 1, 7507 .clkr = { 7508 .enable_reg = 0xe00c0, 7509 .enable_mask = BIT(0), 7510 .hw.init = &(const struct clk_init_data) { 7511 .name = "gcc_usb4_2_phy_usb_pipe_clk", 7512 .parent_hws = (const struct clk_hw*[]) { 7513 &gcc_usb34_tert_phy_pipe_clk_src.clkr.hw, 7514 }, 7515 .num_parents = 1, 7516 .flags = CLK_SET_RATE_PARENT, 7517 .ops = &clk_branch2_ops, 7518 }, 7519 }, 7520 }; 7521 7522 static struct clk_branch gcc_usb4_2_sb_if_clk = { 7523 .halt_reg = 0xe0048, 7524 .halt_check = BRANCH_HALT, 7525 .clkr = { 7526 .enable_reg = 0xe0048, 7527 .enable_mask = BIT(0), 7528 .hw.init = &(const struct clk_init_data) { 7529 .name = "gcc_usb4_2_sb_if_clk", 7530 .parent_hws = (const struct clk_hw*[]) { 7531 &gcc_usb4_2_sb_if_clk_src.clkr.hw, 7532 }, 7533 .num_parents = 1, 7534 .flags = CLK_SET_RATE_PARENT, 7535 .ops = &clk_branch2_ops, 7536 }, 7537 }, 7538 }; 7539 7540 static struct clk_branch gcc_usb4_2_sys_clk = { 7541 .halt_reg = 0xe005c, 7542 .halt_check = BRANCH_HALT, 7543 .clkr = { 7544 .enable_reg = 0xe005c, 7545 .enable_mask = BIT(0), 7546 .hw.init = &(const struct clk_init_data) { 7547 .name = "gcc_usb4_2_sys_clk", 7548 .parent_hws = (const struct clk_hw*[]) { 7549 &gcc_usb4_2_phy_sys_clk_src.clkr.hw, 7550 }, 7551 .num_parents = 1, 7552 .flags = CLK_SET_RATE_PARENT, 7553 .ops = &clk_branch2_ops, 7554 }, 7555 }, 7556 }; 7557 7558 static struct clk_branch gcc_usb4_2_tmu_clk = { 7559 .halt_reg = 0xe00a0, 7560 .halt_check = BRANCH_HALT_VOTED, 7561 .hwcg_reg = 0xe00a0, 7562 .hwcg_bit = 1, 7563 .clkr = { 7564 .enable_reg = 0xe00a0, 7565 .enable_mask = BIT(0), 7566 .hw.init = &(const struct clk_init_data) { 7567 .name = "gcc_usb4_2_tmu_clk", 7568 .parent_hws = (const struct clk_hw*[]) { 7569 &gcc_usb4_2_tmu_clk_src.clkr.hw, 7570 }, 7571 .num_parents = 1, 7572 .flags = CLK_SET_RATE_PARENT, 7573 .ops = &clk_branch2_ops, 7574 }, 7575 }, 7576 }; 7577 7578 static struct clk_branch gcc_usb4_2_uc_hrr_clk = { 7579 .halt_reg = 0xe006c, 7580 .halt_check = BRANCH_HALT, 7581 .clkr = { 7582 .enable_reg = 0xe006c, 7583 .enable_mask = BIT(0), 7584 .hw.init = &(const struct clk_init_data) { 7585 .name = "gcc_usb4_2_uc_hrr_clk", 7586 .parent_hws = (const struct clk_hw*[]) { 7587 &gcc_usb4_2_phy_sys_clk_src.clkr.hw, 7588 }, 7589 .num_parents = 1, 7590 .flags = CLK_SET_RATE_PARENT, 7591 .ops = &clk_branch2_ops, 7592 }, 7593 }, 7594 }; 7595 7596 static struct clk_branch gcc_video_axi0_clk = { 7597 .halt_reg = 0x3201c, 7598 .halt_check = BRANCH_HALT_SKIP, 7599 .hwcg_reg = 0x3201c, 7600 .hwcg_bit = 1, 7601 .clkr = { 7602 .enable_reg = 0x3201c, 7603 .enable_mask = BIT(0), 7604 .hw.init = &(const struct clk_init_data) { 7605 .name = "gcc_video_axi0_clk", 7606 .ops = &clk_branch2_ops, 7607 }, 7608 }, 7609 }; 7610 7611 static struct clk_branch gcc_video_axi0c_clk = { 7612 .halt_reg = 0x32030, 7613 .halt_check = BRANCH_HALT_SKIP, 7614 .hwcg_reg = 0x32030, 7615 .hwcg_bit = 1, 7616 .clkr = { 7617 .enable_reg = 0x32030, 7618 .enable_mask = BIT(0), 7619 .hw.init = &(const struct clk_init_data) { 7620 .name = "gcc_video_axi0c_clk", 7621 .ops = &clk_branch2_ops, 7622 }, 7623 }, 7624 }; 7625 7626 static struct clk_branch gcc_video_axi1_clk = { 7627 .halt_reg = 0x32044, 7628 .halt_check = BRANCH_HALT_SKIP, 7629 .hwcg_reg = 0x32044, 7630 .hwcg_bit = 1, 7631 .clkr = { 7632 .enable_reg = 0x32044, 7633 .enable_mask = BIT(0), 7634 .hw.init = &(const struct clk_init_data) { 7635 .name = "gcc_video_axi1_clk", 7636 .ops = &clk_branch2_ops, 7637 }, 7638 }, 7639 }; 7640 7641 static struct gdsc gcc_pcie_0_tunnel_gdsc = { 7642 .gdscr = 0xc8004, 7643 .en_rest_wait_val = 0x2, 7644 .en_few_wait_val = 0x2, 7645 .clk_dis_wait_val = 0xf, 7646 .pd = { 7647 .name = "gcc_pcie_0_tunnel_gdsc", 7648 }, 7649 .pwrsts = PWRSTS_OFF_ON, 7650 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7651 }; 7652 7653 static struct gdsc gcc_pcie_1_tunnel_gdsc = { 7654 .gdscr = 0x2e004, 7655 .en_rest_wait_val = 0x2, 7656 .en_few_wait_val = 0x2, 7657 .clk_dis_wait_val = 0xf, 7658 .pd = { 7659 .name = "gcc_pcie_1_tunnel_gdsc", 7660 }, 7661 .pwrsts = PWRSTS_OFF_ON, 7662 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7663 }; 7664 7665 static struct gdsc gcc_pcie_2_tunnel_gdsc = { 7666 .gdscr = 0xc0004, 7667 .en_rest_wait_val = 0x2, 7668 .en_few_wait_val = 0x2, 7669 .clk_dis_wait_val = 0xf, 7670 .pd = { 7671 .name = "gcc_pcie_2_tunnel_gdsc", 7672 }, 7673 .pwrsts = PWRSTS_OFF_ON, 7674 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7675 }; 7676 7677 static struct gdsc gcc_pcie_3a_gdsc = { 7678 .gdscr = 0xdc004, 7679 .en_rest_wait_val = 0x2, 7680 .en_few_wait_val = 0x2, 7681 .clk_dis_wait_val = 0xf, 7682 .pd = { 7683 .name = "gcc_pcie_3a_gdsc", 7684 }, 7685 .pwrsts = PWRSTS_OFF_ON, 7686 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7687 }; 7688 7689 static struct gdsc gcc_pcie_3a_phy_gdsc = { 7690 .gdscr = 0x6c004, 7691 .en_rest_wait_val = 0x2, 7692 .en_few_wait_val = 0x2, 7693 .clk_dis_wait_val = 0x2, 7694 .pd = { 7695 .name = "gcc_pcie_3a_phy_gdsc", 7696 }, 7697 .pwrsts = PWRSTS_OFF_ON, 7698 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7699 }; 7700 7701 static struct gdsc gcc_pcie_3b_gdsc = { 7702 .gdscr = 0x94004, 7703 .en_rest_wait_val = 0x2, 7704 .en_few_wait_val = 0x2, 7705 .clk_dis_wait_val = 0xf, 7706 .pd = { 7707 .name = "gcc_pcie_3b_gdsc", 7708 }, 7709 .pwrsts = PWRSTS_OFF_ON, 7710 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7711 }; 7712 7713 static struct gdsc gcc_pcie_3b_phy_gdsc = { 7714 .gdscr = 0x75004, 7715 .en_rest_wait_val = 0x2, 7716 .en_few_wait_val = 0x2, 7717 .clk_dis_wait_val = 0x2, 7718 .pd = { 7719 .name = "gcc_pcie_3b_phy_gdsc", 7720 }, 7721 .pwrsts = PWRSTS_OFF_ON, 7722 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7723 }; 7724 7725 static struct gdsc gcc_pcie_4_gdsc = { 7726 .gdscr = 0x88004, 7727 .en_rest_wait_val = 0x2, 7728 .en_few_wait_val = 0x2, 7729 .clk_dis_wait_val = 0xf, 7730 .pd = { 7731 .name = "gcc_pcie_4_gdsc", 7732 }, 7733 .pwrsts = PWRSTS_OFF_ON, 7734 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7735 }; 7736 7737 static struct gdsc gcc_pcie_4_phy_gdsc = { 7738 .gdscr = 0xd3004, 7739 .en_rest_wait_val = 0x2, 7740 .en_few_wait_val = 0x2, 7741 .clk_dis_wait_val = 0x2, 7742 .pd = { 7743 .name = "gcc_pcie_4_phy_gdsc", 7744 }, 7745 .pwrsts = PWRSTS_OFF_ON, 7746 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7747 }; 7748 7749 static struct gdsc gcc_pcie_5_gdsc = { 7750 .gdscr = 0xc3004, 7751 .en_rest_wait_val = 0x2, 7752 .en_few_wait_val = 0x2, 7753 .clk_dis_wait_val = 0xf, 7754 .pd = { 7755 .name = "gcc_pcie_5_gdsc", 7756 }, 7757 .pwrsts = PWRSTS_OFF_ON, 7758 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7759 }; 7760 7761 static struct gdsc gcc_pcie_5_phy_gdsc = { 7762 .gdscr = 0xd2004, 7763 .en_rest_wait_val = 0x2, 7764 .en_few_wait_val = 0x2, 7765 .clk_dis_wait_val = 0x2, 7766 .pd = { 7767 .name = "gcc_pcie_5_phy_gdsc", 7768 }, 7769 .pwrsts = PWRSTS_OFF_ON, 7770 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7771 }; 7772 7773 static struct gdsc gcc_pcie_6_gdsc = { 7774 .gdscr = 0x8a004, 7775 .en_rest_wait_val = 0x2, 7776 .en_few_wait_val = 0x2, 7777 .clk_dis_wait_val = 0xf, 7778 .pd = { 7779 .name = "gcc_pcie_6_gdsc", 7780 }, 7781 .pwrsts = PWRSTS_OFF_ON, 7782 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7783 }; 7784 7785 static struct gdsc gcc_pcie_6_phy_gdsc = { 7786 .gdscr = 0xd4004, 7787 .en_rest_wait_val = 0x2, 7788 .en_few_wait_val = 0x2, 7789 .clk_dis_wait_val = 0x2, 7790 .pd = { 7791 .name = "gcc_pcie_6_phy_gdsc", 7792 }, 7793 .pwrsts = PWRSTS_OFF_ON, 7794 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7795 }; 7796 7797 static struct gdsc gcc_ufs_phy_gdsc = { 7798 .gdscr = 0x77008, 7799 .en_rest_wait_val = 0x2, 7800 .en_few_wait_val = 0x2, 7801 .clk_dis_wait_val = 0xf, 7802 .pd = { 7803 .name = "gcc_ufs_phy_gdsc", 7804 }, 7805 .pwrsts = PWRSTS_OFF_ON, 7806 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7807 }; 7808 7809 static struct gdsc gcc_usb20_prim_gdsc = { 7810 .gdscr = 0xbc004, 7811 .en_rest_wait_val = 0x2, 7812 .en_few_wait_val = 0x2, 7813 .clk_dis_wait_val = 0xf, 7814 .pd = { 7815 .name = "gcc_usb20_prim_gdsc", 7816 }, 7817 .pwrsts = PWRSTS_OFF_ON, 7818 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7819 }; 7820 7821 static struct gdsc gcc_usb30_mp_gdsc = { 7822 .gdscr = 0x9a010, 7823 .en_rest_wait_val = 0x2, 7824 .en_few_wait_val = 0x2, 7825 .clk_dis_wait_val = 0xf, 7826 .pd = { 7827 .name = "gcc_usb30_mp_gdsc", 7828 }, 7829 .pwrsts = PWRSTS_OFF_ON, 7830 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7831 }; 7832 7833 static struct gdsc gcc_usb30_prim_gdsc = { 7834 .gdscr = 0x3f01c, 7835 .en_rest_wait_val = 0x2, 7836 .en_few_wait_val = 0x2, 7837 .clk_dis_wait_val = 0xf, 7838 .pd = { 7839 .name = "gcc_usb30_prim_gdsc", 7840 }, 7841 .pwrsts = PWRSTS_OFF_ON, 7842 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7843 }; 7844 7845 static struct gdsc gcc_usb30_sec_gdsc = { 7846 .gdscr = 0xe2010, 7847 .en_rest_wait_val = 0x2, 7848 .en_few_wait_val = 0x2, 7849 .clk_dis_wait_val = 0xf, 7850 .pd = { 7851 .name = "gcc_usb30_sec_gdsc", 7852 }, 7853 .pwrsts = PWRSTS_OFF_ON, 7854 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7855 }; 7856 7857 static struct gdsc gcc_usb30_tert_gdsc = { 7858 .gdscr = 0xe1010, 7859 .en_rest_wait_val = 0x2, 7860 .en_few_wait_val = 0x2, 7861 .clk_dis_wait_val = 0xf, 7862 .pd = { 7863 .name = "gcc_usb30_tert_gdsc", 7864 }, 7865 .pwrsts = PWRSTS_OFF_ON, 7866 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7867 }; 7868 7869 static struct gdsc gcc_usb3_mp_ss0_phy_gdsc = { 7870 .gdscr = 0x5400c, 7871 .en_rest_wait_val = 0x2, 7872 .en_few_wait_val = 0x2, 7873 .clk_dis_wait_val = 0x2, 7874 .pd = { 7875 .name = "gcc_usb3_mp_ss0_phy_gdsc", 7876 }, 7877 .pwrsts = PWRSTS_OFF_ON, 7878 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7879 }; 7880 7881 static struct gdsc gcc_usb3_mp_ss1_phy_gdsc = { 7882 .gdscr = 0x5402c, 7883 .en_rest_wait_val = 0x2, 7884 .en_few_wait_val = 0x2, 7885 .clk_dis_wait_val = 0x2, 7886 .pd = { 7887 .name = "gcc_usb3_mp_ss1_phy_gdsc", 7888 }, 7889 .pwrsts = PWRSTS_OFF_ON, 7890 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7891 }; 7892 7893 static struct gdsc gcc_usb4_0_gdsc = { 7894 .gdscr = 0x2b008, 7895 .en_rest_wait_val = 0x2, 7896 .en_few_wait_val = 0x2, 7897 .clk_dis_wait_val = 0xf, 7898 .pd = { 7899 .name = "gcc_usb4_0_gdsc", 7900 }, 7901 .pwrsts = PWRSTS_OFF_ON, 7902 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7903 }; 7904 7905 static struct gdsc gcc_usb4_1_gdsc = { 7906 .gdscr = 0x2d008, 7907 .en_rest_wait_val = 0x2, 7908 .en_few_wait_val = 0x2, 7909 .clk_dis_wait_val = 0xf, 7910 .pd = { 7911 .name = "gcc_usb4_1_gdsc", 7912 }, 7913 .pwrsts = PWRSTS_OFF_ON, 7914 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7915 }; 7916 7917 static struct gdsc gcc_usb4_2_gdsc = { 7918 .gdscr = 0xe0008, 7919 .en_rest_wait_val = 0x2, 7920 .en_few_wait_val = 0x2, 7921 .clk_dis_wait_val = 0xf, 7922 .pd = { 7923 .name = "gcc_usb4_2_gdsc", 7924 }, 7925 .pwrsts = PWRSTS_OFF_ON, 7926 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7927 }; 7928 7929 static struct gdsc gcc_usb_0_phy_gdsc = { 7930 .gdscr = 0xdb024, 7931 .en_rest_wait_val = 0x2, 7932 .en_few_wait_val = 0x2, 7933 .clk_dis_wait_val = 0x2, 7934 .pd = { 7935 .name = "gcc_usb_0_phy_gdsc", 7936 }, 7937 .pwrsts = PWRSTS_OFF_ON, 7938 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7939 }; 7940 7941 static struct gdsc gcc_usb_1_phy_gdsc = { 7942 .gdscr = 0x2c024, 7943 .en_rest_wait_val = 0x2, 7944 .en_few_wait_val = 0x2, 7945 .clk_dis_wait_val = 0x2, 7946 .pd = { 7947 .name = "gcc_usb_1_phy_gdsc", 7948 }, 7949 .pwrsts = PWRSTS_OFF_ON, 7950 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7951 }; 7952 7953 static struct gdsc gcc_usb_2_phy_gdsc = { 7954 .gdscr = 0xbe024, 7955 .en_rest_wait_val = 0x2, 7956 .en_few_wait_val = 0x2, 7957 .clk_dis_wait_val = 0x2, 7958 .pd = { 7959 .name = "gcc_usb_2_phy_gdsc", 7960 }, 7961 .pwrsts = PWRSTS_OFF_ON, 7962 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7963 }; 7964 7965 static struct clk_regmap *gcc_glymur_clocks[] = { 7966 [GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK] = &gcc_aggre_noc_pcie_3a_west_sf_axi_clk.clkr, 7967 [GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK] = &gcc_aggre_noc_pcie_3b_west_sf_axi_clk.clkr, 7968 [GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK] = &gcc_aggre_noc_pcie_4_west_sf_axi_clk.clkr, 7969 [GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK] = &gcc_aggre_noc_pcie_5_east_sf_axi_clk.clkr, 7970 [GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK] = &gcc_aggre_noc_pcie_6_west_sf_axi_clk.clkr, 7971 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 7972 [GCC_AGGRE_USB2_PRIM_AXI_CLK] = &gcc_aggre_usb2_prim_axi_clk.clkr, 7973 [GCC_AGGRE_USB3_MP_AXI_CLK] = &gcc_aggre_usb3_mp_axi_clk.clkr, 7974 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 7975 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, 7976 [GCC_AGGRE_USB3_TERT_AXI_CLK] = &gcc_aggre_usb3_tert_axi_clk.clkr, 7977 [GCC_AGGRE_USB4_0_AXI_CLK] = &gcc_aggre_usb4_0_axi_clk.clkr, 7978 [GCC_AGGRE_USB4_1_AXI_CLK] = &gcc_aggre_usb4_1_axi_clk.clkr, 7979 [GCC_AGGRE_USB4_2_AXI_CLK] = &gcc_aggre_usb4_2_axi_clk.clkr, 7980 [GCC_AV1E_AHB_CLK] = &gcc_av1e_ahb_clk.clkr, 7981 [GCC_AV1E_AXI_CLK] = &gcc_av1e_axi_clk.clkr, 7982 [GCC_AV1E_XO_CLK] = &gcc_av1e_xo_clk.clkr, 7983 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 7984 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 7985 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 7986 [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr, 7987 [GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_south_ahb_clk.clkr, 7988 [GCC_CFG_NOC_USB2_PRIM_AXI_CLK] = &gcc_cfg_noc_usb2_prim_axi_clk.clkr, 7989 [GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr, 7990 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 7991 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, 7992 [GCC_CFG_NOC_USB3_TERT_AXI_CLK] = &gcc_cfg_noc_usb3_tert_axi_clk.clkr, 7993 [GCC_CFG_NOC_USB_ANOC_AHB_CLK] = &gcc_cfg_noc_usb_anoc_ahb_clk.clkr, 7994 [GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK] = &gcc_cfg_noc_usb_anoc_south_ahb_clk.clkr, 7995 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 7996 [GCC_EVA_AHB_CLK] = &gcc_eva_ahb_clk.clkr, 7997 [GCC_EVA_AXI0_CLK] = &gcc_eva_axi0_clk.clkr, 7998 [GCC_EVA_AXI0C_CLK] = &gcc_eva_axi0c_clk.clkr, 7999 [GCC_EVA_XO_CLK] = &gcc_eva_xo_clk.clkr, 8000 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 8001 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 8002 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 8003 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 8004 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 8005 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 8006 [GCC_GPLL0] = &gcc_gpll0.clkr, 8007 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 8008 [GCC_GPLL1] = &gcc_gpll1.clkr, 8009 [GCC_GPLL14] = &gcc_gpll14.clkr, 8010 [GCC_GPLL14_OUT_EVEN] = &gcc_gpll14_out_even.clkr, 8011 [GCC_GPLL4] = &gcc_gpll4.clkr, 8012 [GCC_GPLL5] = &gcc_gpll5.clkr, 8013 [GCC_GPLL7] = &gcc_gpll7.clkr, 8014 [GCC_GPLL8] = &gcc_gpll8.clkr, 8015 [GCC_GPLL9] = &gcc_gpll9.clkr, 8016 [GCC_GPU_GEMNOC_GFX_CLK] = &gcc_gpu_gemnoc_gfx_clk.clkr, 8017 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 8018 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 8019 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 8020 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 8021 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 8022 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 8023 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 8024 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 8025 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 8026 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 8027 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 8028 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 8029 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 8030 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 8031 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 8032 [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr, 8033 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, 8034 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 8035 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 8036 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 8037 [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr, 8038 [GCC_PCIE_2_AUX_CLK_SRC] = &gcc_pcie_2_aux_clk_src.clkr, 8039 [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr, 8040 [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr, 8041 [GCC_PCIE_2_PHY_RCHNG_CLK] = &gcc_pcie_2_phy_rchng_clk.clkr, 8042 [GCC_PCIE_2_PHY_RCHNG_CLK_SRC] = &gcc_pcie_2_phy_rchng_clk_src.clkr, 8043 [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr, 8044 [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr, 8045 [GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr, 8046 [GCC_PCIE_3A_AUX_CLK] = &gcc_pcie_3a_aux_clk.clkr, 8047 [GCC_PCIE_3A_AUX_CLK_SRC] = &gcc_pcie_3a_aux_clk_src.clkr, 8048 [GCC_PCIE_3A_CFG_AHB_CLK] = &gcc_pcie_3a_cfg_ahb_clk.clkr, 8049 [GCC_PCIE_3A_MSTR_AXI_CLK] = &gcc_pcie_3a_mstr_axi_clk.clkr, 8050 [GCC_PCIE_3A_PHY_RCHNG_CLK] = &gcc_pcie_3a_phy_rchng_clk.clkr, 8051 [GCC_PCIE_3A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_3a_phy_rchng_clk_src.clkr, 8052 [GCC_PCIE_3A_PIPE_CLK] = &gcc_pcie_3a_pipe_clk.clkr, 8053 [GCC_PCIE_3A_PIPE_CLK_SRC] = &gcc_pcie_3a_pipe_clk_src.clkr, 8054 [GCC_PCIE_3A_SLV_AXI_CLK] = &gcc_pcie_3a_slv_axi_clk.clkr, 8055 [GCC_PCIE_3A_SLV_Q2A_AXI_CLK] = &gcc_pcie_3a_slv_q2a_axi_clk.clkr, 8056 [GCC_PCIE_3B_AUX_CLK] = &gcc_pcie_3b_aux_clk.clkr, 8057 [GCC_PCIE_3B_AUX_CLK_SRC] = &gcc_pcie_3b_aux_clk_src.clkr, 8058 [GCC_PCIE_3B_CFG_AHB_CLK] = &gcc_pcie_3b_cfg_ahb_clk.clkr, 8059 [GCC_PCIE_3B_MSTR_AXI_CLK] = &gcc_pcie_3b_mstr_axi_clk.clkr, 8060 [GCC_PCIE_3B_PHY_RCHNG_CLK] = &gcc_pcie_3b_phy_rchng_clk.clkr, 8061 [GCC_PCIE_3B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_3b_phy_rchng_clk_src.clkr, 8062 [GCC_PCIE_3B_PIPE_CLK] = &gcc_pcie_3b_pipe_clk.clkr, 8063 [GCC_PCIE_3B_PIPE_CLK_SRC] = &gcc_pcie_3b_pipe_clk_src.clkr, 8064 [GCC_PCIE_3B_PIPE_DIV2_CLK] = &gcc_pcie_3b_pipe_div2_clk.clkr, 8065 [GCC_PCIE_3B_PIPE_DIV_CLK_SRC] = &gcc_pcie_3b_pipe_div_clk_src.clkr, 8066 [GCC_PCIE_3B_SLV_AXI_CLK] = &gcc_pcie_3b_slv_axi_clk.clkr, 8067 [GCC_PCIE_3B_SLV_Q2A_AXI_CLK] = &gcc_pcie_3b_slv_q2a_axi_clk.clkr, 8068 [GCC_PCIE_4_AUX_CLK] = &gcc_pcie_4_aux_clk.clkr, 8069 [GCC_PCIE_4_AUX_CLK_SRC] = &gcc_pcie_4_aux_clk_src.clkr, 8070 [GCC_PCIE_4_CFG_AHB_CLK] = &gcc_pcie_4_cfg_ahb_clk.clkr, 8071 [GCC_PCIE_4_MSTR_AXI_CLK] = &gcc_pcie_4_mstr_axi_clk.clkr, 8072 [GCC_PCIE_4_PHY_RCHNG_CLK] = &gcc_pcie_4_phy_rchng_clk.clkr, 8073 [GCC_PCIE_4_PHY_RCHNG_CLK_SRC] = &gcc_pcie_4_phy_rchng_clk_src.clkr, 8074 [GCC_PCIE_4_PIPE_CLK] = &gcc_pcie_4_pipe_clk.clkr, 8075 [GCC_PCIE_4_PIPE_CLK_SRC] = &gcc_pcie_4_pipe_clk_src.clkr, 8076 [GCC_PCIE_4_PIPE_DIV2_CLK] = &gcc_pcie_4_pipe_div2_clk.clkr, 8077 [GCC_PCIE_4_PIPE_DIV_CLK_SRC] = &gcc_pcie_4_pipe_div_clk_src.clkr, 8078 [GCC_PCIE_4_SLV_AXI_CLK] = &gcc_pcie_4_slv_axi_clk.clkr, 8079 [GCC_PCIE_4_SLV_Q2A_AXI_CLK] = &gcc_pcie_4_slv_q2a_axi_clk.clkr, 8080 [GCC_PCIE_5_AUX_CLK] = &gcc_pcie_5_aux_clk.clkr, 8081 [GCC_PCIE_5_AUX_CLK_SRC] = &gcc_pcie_5_aux_clk_src.clkr, 8082 [GCC_PCIE_5_CFG_AHB_CLK] = &gcc_pcie_5_cfg_ahb_clk.clkr, 8083 [GCC_PCIE_5_MSTR_AXI_CLK] = &gcc_pcie_5_mstr_axi_clk.clkr, 8084 [GCC_PCIE_5_PHY_RCHNG_CLK] = &gcc_pcie_5_phy_rchng_clk.clkr, 8085 [GCC_PCIE_5_PHY_RCHNG_CLK_SRC] = &gcc_pcie_5_phy_rchng_clk_src.clkr, 8086 [GCC_PCIE_5_PIPE_CLK] = &gcc_pcie_5_pipe_clk.clkr, 8087 [GCC_PCIE_5_PIPE_CLK_SRC] = &gcc_pcie_5_pipe_clk_src.clkr, 8088 [GCC_PCIE_5_PIPE_DIV2_CLK] = &gcc_pcie_5_pipe_div2_clk.clkr, 8089 [GCC_PCIE_5_PIPE_DIV_CLK_SRC] = &gcc_pcie_5_pipe_div_clk_src.clkr, 8090 [GCC_PCIE_5_SLV_AXI_CLK] = &gcc_pcie_5_slv_axi_clk.clkr, 8091 [GCC_PCIE_5_SLV_Q2A_AXI_CLK] = &gcc_pcie_5_slv_q2a_axi_clk.clkr, 8092 [GCC_PCIE_6_AUX_CLK] = &gcc_pcie_6_aux_clk.clkr, 8093 [GCC_PCIE_6_AUX_CLK_SRC] = &gcc_pcie_6_aux_clk_src.clkr, 8094 [GCC_PCIE_6_CFG_AHB_CLK] = &gcc_pcie_6_cfg_ahb_clk.clkr, 8095 [GCC_PCIE_6_MSTR_AXI_CLK] = &gcc_pcie_6_mstr_axi_clk.clkr, 8096 [GCC_PCIE_6_PHY_RCHNG_CLK] = &gcc_pcie_6_phy_rchng_clk.clkr, 8097 [GCC_PCIE_6_PHY_RCHNG_CLK_SRC] = &gcc_pcie_6_phy_rchng_clk_src.clkr, 8098 [GCC_PCIE_6_PIPE_CLK] = &gcc_pcie_6_pipe_clk.clkr, 8099 [GCC_PCIE_6_PIPE_CLK_SRC] = &gcc_pcie_6_pipe_clk_src.clkr, 8100 [GCC_PCIE_6_PIPE_DIV2_CLK] = &gcc_pcie_6_pipe_div2_clk.clkr, 8101 [GCC_PCIE_6_PIPE_DIV_CLK_SRC] = &gcc_pcie_6_pipe_div_clk_src.clkr, 8102 [GCC_PCIE_6_SLV_AXI_CLK] = &gcc_pcie_6_slv_axi_clk.clkr, 8103 [GCC_PCIE_6_SLV_Q2A_AXI_CLK] = &gcc_pcie_6_slv_q2a_axi_clk.clkr, 8104 [GCC_PCIE_NOC_PWRCTL_CLK] = &gcc_pcie_noc_pwrctl_clk.clkr, 8105 [GCC_PCIE_NOC_QOSGEN_EXTREF_CLK] = &gcc_pcie_noc_qosgen_extref_clk.clkr, 8106 [GCC_PCIE_NOC_SF_CENTER_CLK] = &gcc_pcie_noc_sf_center_clk.clkr, 8107 [GCC_PCIE_NOC_SLAVE_SF_EAST_CLK] = &gcc_pcie_noc_slave_sf_east_clk.clkr, 8108 [GCC_PCIE_NOC_SLAVE_SF_WEST_CLK] = &gcc_pcie_noc_slave_sf_west_clk.clkr, 8109 [GCC_PCIE_NOC_TSCTR_CLK] = &gcc_pcie_noc_tsctr_clk.clkr, 8110 [GCC_PCIE_PHY_3A_AUX_CLK] = &gcc_pcie_phy_3a_aux_clk.clkr, 8111 [GCC_PCIE_PHY_3A_AUX_CLK_SRC] = &gcc_pcie_phy_3a_aux_clk_src.clkr, 8112 [GCC_PCIE_PHY_3B_AUX_CLK] = &gcc_pcie_phy_3b_aux_clk.clkr, 8113 [GCC_PCIE_PHY_3B_AUX_CLK_SRC] = &gcc_pcie_phy_3b_aux_clk_src.clkr, 8114 [GCC_PCIE_PHY_4_AUX_CLK] = &gcc_pcie_phy_4_aux_clk.clkr, 8115 [GCC_PCIE_PHY_4_AUX_CLK_SRC] = &gcc_pcie_phy_4_aux_clk_src.clkr, 8116 [GCC_PCIE_PHY_5_AUX_CLK] = &gcc_pcie_phy_5_aux_clk.clkr, 8117 [GCC_PCIE_PHY_5_AUX_CLK_SRC] = &gcc_pcie_phy_5_aux_clk_src.clkr, 8118 [GCC_PCIE_PHY_6_AUX_CLK] = &gcc_pcie_phy_6_aux_clk.clkr, 8119 [GCC_PCIE_PHY_6_AUX_CLK_SRC] = &gcc_pcie_phy_6_aux_clk_src.clkr, 8120 [GCC_PCIE_RSCC_CFG_AHB_CLK] = &gcc_pcie_rscc_cfg_ahb_clk.clkr, 8121 [GCC_PCIE_RSCC_XO_CLK] = &gcc_pcie_rscc_xo_clk.clkr, 8122 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 8123 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 8124 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 8125 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 8126 [GCC_QMIP_AV1E_AHB_CLK] = &gcc_qmip_av1e_ahb_clk.clkr, 8127 [GCC_QMIP_CAMERA_CMD_AHB_CLK] = &gcc_qmip_camera_cmd_ahb_clk.clkr, 8128 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 8129 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 8130 [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr, 8131 [GCC_QMIP_PCIE_3A_AHB_CLK] = &gcc_qmip_pcie_3a_ahb_clk.clkr, 8132 [GCC_QMIP_PCIE_3B_AHB_CLK] = &gcc_qmip_pcie_3b_ahb_clk.clkr, 8133 [GCC_QMIP_PCIE_4_AHB_CLK] = &gcc_qmip_pcie_4_ahb_clk.clkr, 8134 [GCC_QMIP_PCIE_5_AHB_CLK] = &gcc_qmip_pcie_5_ahb_clk.clkr, 8135 [GCC_QMIP_PCIE_6_AHB_CLK] = &gcc_qmip_pcie_6_ahb_clk.clkr, 8136 [GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr, 8137 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 8138 [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr, 8139 [GCC_QMIP_VIDEO_VCODEC1_AHB_CLK] = &gcc_qmip_video_vcodec1_ahb_clk.clkr, 8140 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 8141 [GCC_QUPV3_OOB_CORE_2X_CLK] = &gcc_qupv3_oob_core_2x_clk.clkr, 8142 [GCC_QUPV3_OOB_CORE_CLK] = &gcc_qupv3_oob_core_clk.clkr, 8143 [GCC_QUPV3_OOB_M_AHB_CLK] = &gcc_qupv3_oob_m_ahb_clk.clkr, 8144 [GCC_QUPV3_OOB_QSPI_S0_CLK] = &gcc_qupv3_oob_qspi_s0_clk.clkr, 8145 [GCC_QUPV3_OOB_QSPI_S0_CLK_SRC] = &gcc_qupv3_oob_qspi_s0_clk_src.clkr, 8146 [GCC_QUPV3_OOB_QSPI_S1_CLK] = &gcc_qupv3_oob_qspi_s1_clk.clkr, 8147 [GCC_QUPV3_OOB_QSPI_S1_CLK_SRC] = &gcc_qupv3_oob_qspi_s1_clk_src.clkr, 8148 [GCC_QUPV3_OOB_S0_CLK] = &gcc_qupv3_oob_s0_clk.clkr, 8149 [GCC_QUPV3_OOB_S0_CLK_SRC] = &gcc_qupv3_oob_s0_clk_src.clkr, 8150 [GCC_QUPV3_OOB_S1_CLK] = &gcc_qupv3_oob_s1_clk.clkr, 8151 [GCC_QUPV3_OOB_S1_CLK_SRC] = &gcc_qupv3_oob_s1_clk_src.clkr, 8152 [GCC_QUPV3_OOB_S_AHB_CLK] = &gcc_qupv3_oob_s_ahb_clk.clkr, 8153 [GCC_QUPV3_OOB_TCXO_CLK] = &gcc_qupv3_oob_tcxo_clk.clkr, 8154 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 8155 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 8156 [GCC_QUPV3_WRAP0_QSPI_S2_CLK] = &gcc_qupv3_wrap0_qspi_s2_clk.clkr, 8157 [GCC_QUPV3_WRAP0_QSPI_S2_CLK_SRC] = &gcc_qupv3_wrap0_qspi_s2_clk_src.clkr, 8158 [GCC_QUPV3_WRAP0_QSPI_S3_CLK] = &gcc_qupv3_wrap0_qspi_s3_clk.clkr, 8159 [GCC_QUPV3_WRAP0_QSPI_S3_CLK_SRC] = &gcc_qupv3_wrap0_qspi_s3_clk_src.clkr, 8160 [GCC_QUPV3_WRAP0_QSPI_S6_CLK] = &gcc_qupv3_wrap0_qspi_s6_clk.clkr, 8161 [GCC_QUPV3_WRAP0_QSPI_S6_CLK_SRC] = &gcc_qupv3_wrap0_qspi_s6_clk_src.clkr, 8162 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 8163 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 8164 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 8165 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 8166 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 8167 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 8168 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 8169 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 8170 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 8171 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 8172 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 8173 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 8174 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 8175 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 8176 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 8177 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 8178 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 8179 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 8180 [GCC_QUPV3_WRAP1_QSPI_S2_CLK] = &gcc_qupv3_wrap1_qspi_s2_clk.clkr, 8181 [GCC_QUPV3_WRAP1_QSPI_S2_CLK_SRC] = &gcc_qupv3_wrap1_qspi_s2_clk_src.clkr, 8182 [GCC_QUPV3_WRAP1_QSPI_S3_CLK] = &gcc_qupv3_wrap1_qspi_s3_clk.clkr, 8183 [GCC_QUPV3_WRAP1_QSPI_S3_CLK_SRC] = &gcc_qupv3_wrap1_qspi_s3_clk_src.clkr, 8184 [GCC_QUPV3_WRAP1_QSPI_S6_CLK] = &gcc_qupv3_wrap1_qspi_s6_clk.clkr, 8185 [GCC_QUPV3_WRAP1_QSPI_S6_CLK_SRC] = &gcc_qupv3_wrap1_qspi_s6_clk_src.clkr, 8186 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 8187 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 8188 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 8189 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 8190 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 8191 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 8192 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 8193 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 8194 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 8195 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 8196 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 8197 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 8198 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 8199 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 8200 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 8201 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 8202 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, 8203 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, 8204 [GCC_QUPV3_WRAP2_QSPI_S2_CLK] = &gcc_qupv3_wrap2_qspi_s2_clk.clkr, 8205 [GCC_QUPV3_WRAP2_QSPI_S2_CLK_SRC] = &gcc_qupv3_wrap2_qspi_s2_clk_src.clkr, 8206 [GCC_QUPV3_WRAP2_QSPI_S3_CLK] = &gcc_qupv3_wrap2_qspi_s3_clk.clkr, 8207 [GCC_QUPV3_WRAP2_QSPI_S3_CLK_SRC] = &gcc_qupv3_wrap2_qspi_s3_clk_src.clkr, 8208 [GCC_QUPV3_WRAP2_QSPI_S6_CLK] = &gcc_qupv3_wrap2_qspi_s6_clk.clkr, 8209 [GCC_QUPV3_WRAP2_QSPI_S6_CLK_SRC] = &gcc_qupv3_wrap2_qspi_s6_clk_src.clkr, 8210 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 8211 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 8212 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 8213 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 8214 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 8215 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 8216 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 8217 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 8218 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 8219 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 8220 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, 8221 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, 8222 [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr, 8223 [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr, 8224 [GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr, 8225 [GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr, 8226 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 8227 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 8228 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 8229 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 8230 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 8231 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 8232 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 8233 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 8234 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 8235 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 8236 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 8237 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 8238 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 8239 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 8240 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 8241 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 8242 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 8243 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 8244 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 8245 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 8246 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr, 8247 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 8248 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr, 8249 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 8250 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr, 8251 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 8252 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 8253 [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr, 8254 [GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr, 8255 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr, 8256 [GCC_USB20_MOCK_UTMI_CLK_SRC] = &gcc_usb20_mock_utmi_clk_src.clkr, 8257 [GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb20_mock_utmi_postdiv_clk_src.clkr, 8258 [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr, 8259 [GCC_USB30_MP_MASTER_CLK] = &gcc_usb30_mp_master_clk.clkr, 8260 [GCC_USB30_MP_MASTER_CLK_SRC] = &gcc_usb30_mp_master_clk_src.clkr, 8261 [GCC_USB30_MP_MOCK_UTMI_CLK] = &gcc_usb30_mp_mock_utmi_clk.clkr, 8262 [GCC_USB30_MP_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mp_mock_utmi_clk_src.clkr, 8263 [GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr, 8264 [GCC_USB30_MP_SLEEP_CLK] = &gcc_usb30_mp_sleep_clk.clkr, 8265 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 8266 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 8267 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 8268 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 8269 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 8270 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 8271 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, 8272 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, 8273 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, 8274 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr, 8275 [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr, 8276 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, 8277 [GCC_USB30_TERT_MASTER_CLK] = &gcc_usb30_tert_master_clk.clkr, 8278 [GCC_USB30_TERT_MASTER_CLK_SRC] = &gcc_usb30_tert_master_clk_src.clkr, 8279 [GCC_USB30_TERT_MOCK_UTMI_CLK] = &gcc_usb30_tert_mock_utmi_clk.clkr, 8280 [GCC_USB30_TERT_MOCK_UTMI_CLK_SRC] = &gcc_usb30_tert_mock_utmi_clk_src.clkr, 8281 [GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr, 8282 [GCC_USB30_TERT_SLEEP_CLK] = &gcc_usb30_tert_sleep_clk.clkr, 8283 [GCC_USB34_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb34_prim_phy_pipe_clk_src.clkr, 8284 [GCC_USB34_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb34_sec_phy_pipe_clk_src.clkr, 8285 [GCC_USB34_TERT_PHY_PIPE_CLK_SRC] = &gcc_usb34_tert_phy_pipe_clk_src.clkr, 8286 [GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr, 8287 [GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr, 8288 [GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr, 8289 [GCC_USB3_MP_PHY_PIPE_0_CLK] = &gcc_usb3_mp_phy_pipe_0_clk.clkr, 8290 [GCC_USB3_MP_PHY_PIPE_0_CLK_SRC] = &gcc_usb3_mp_phy_pipe_0_clk_src.clkr, 8291 [GCC_USB3_MP_PHY_PIPE_1_CLK] = &gcc_usb3_mp_phy_pipe_1_clk.clkr, 8292 [GCC_USB3_MP_PHY_PIPE_1_CLK_SRC] = &gcc_usb3_mp_phy_pipe_1_clk_src.clkr, 8293 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 8294 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 8295 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 8296 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 8297 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 8298 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, 8299 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, 8300 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, 8301 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, 8302 [GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr, 8303 [GCC_USB3_TERT_PHY_AUX_CLK] = &gcc_usb3_tert_phy_aux_clk.clkr, 8304 [GCC_USB3_TERT_PHY_AUX_CLK_SRC] = &gcc_usb3_tert_phy_aux_clk_src.clkr, 8305 [GCC_USB3_TERT_PHY_COM_AUX_CLK] = &gcc_usb3_tert_phy_com_aux_clk.clkr, 8306 [GCC_USB3_TERT_PHY_PIPE_CLK] = &gcc_usb3_tert_phy_pipe_clk.clkr, 8307 [GCC_USB3_TERT_PHY_PIPE_CLK_SRC] = &gcc_usb3_tert_phy_pipe_clk_src.clkr, 8308 [GCC_USB4_0_CFG_AHB_CLK] = &gcc_usb4_0_cfg_ahb_clk.clkr, 8309 [GCC_USB4_0_DP0_CLK] = &gcc_usb4_0_dp0_clk.clkr, 8310 [GCC_USB4_0_DP1_CLK] = &gcc_usb4_0_dp1_clk.clkr, 8311 [GCC_USB4_0_MASTER_CLK] = &gcc_usb4_0_master_clk.clkr, 8312 [GCC_USB4_0_MASTER_CLK_SRC] = &gcc_usb4_0_master_clk_src.clkr, 8313 [GCC_USB4_0_PHY_DP0_CLK_SRC] = &gcc_usb4_0_phy_dp0_clk_src.clkr, 8314 [GCC_USB4_0_PHY_DP1_CLK_SRC] = &gcc_usb4_0_phy_dp1_clk_src.clkr, 8315 [GCC_USB4_0_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_0_phy_p2rr2p_pipe_clk.clkr, 8316 [GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_0_phy_p2rr2p_pipe_clk_src.clkr, 8317 [GCC_USB4_0_PHY_PCIE_PIPE_CLK] = &gcc_usb4_0_phy_pcie_pipe_clk.clkr, 8318 [GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_clk_src.clkr, 8319 [GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr, 8320 [GCC_USB4_0_PHY_RX0_CLK] = &gcc_usb4_0_phy_rx0_clk.clkr, 8321 [GCC_USB4_0_PHY_RX0_CLK_SRC] = &gcc_usb4_0_phy_rx0_clk_src.clkr, 8322 [GCC_USB4_0_PHY_RX1_CLK] = &gcc_usb4_0_phy_rx1_clk.clkr, 8323 [GCC_USB4_0_PHY_RX1_CLK_SRC] = &gcc_usb4_0_phy_rx1_clk_src.clkr, 8324 [GCC_USB4_0_PHY_SYS_CLK_SRC] = &gcc_usb4_0_phy_sys_clk_src.clkr, 8325 [GCC_USB4_0_PHY_USB_PIPE_CLK] = &gcc_usb4_0_phy_usb_pipe_clk.clkr, 8326 [GCC_USB4_0_SB_IF_CLK] = &gcc_usb4_0_sb_if_clk.clkr, 8327 [GCC_USB4_0_SB_IF_CLK_SRC] = &gcc_usb4_0_sb_if_clk_src.clkr, 8328 [GCC_USB4_0_SYS_CLK] = &gcc_usb4_0_sys_clk.clkr, 8329 [GCC_USB4_0_TMU_CLK] = &gcc_usb4_0_tmu_clk.clkr, 8330 [GCC_USB4_0_TMU_CLK_SRC] = &gcc_usb4_0_tmu_clk_src.clkr, 8331 [GCC_USB4_0_UC_HRR_CLK] = &gcc_usb4_0_uc_hrr_clk.clkr, 8332 [GCC_USB4_1_CFG_AHB_CLK] = &gcc_usb4_1_cfg_ahb_clk.clkr, 8333 [GCC_USB4_1_DP0_CLK] = &gcc_usb4_1_dp0_clk.clkr, 8334 [GCC_USB4_1_DP1_CLK] = &gcc_usb4_1_dp1_clk.clkr, 8335 [GCC_USB4_1_MASTER_CLK] = &gcc_usb4_1_master_clk.clkr, 8336 [GCC_USB4_1_MASTER_CLK_SRC] = &gcc_usb4_1_master_clk_src.clkr, 8337 [GCC_USB4_1_PHY_DP0_CLK_SRC] = &gcc_usb4_1_phy_dp0_clk_src.clkr, 8338 [GCC_USB4_1_PHY_DP1_CLK_SRC] = &gcc_usb4_1_phy_dp1_clk_src.clkr, 8339 [GCC_USB4_1_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_1_phy_p2rr2p_pipe_clk.clkr, 8340 [GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr, 8341 [GCC_USB4_1_PHY_PCIE_PIPE_CLK] = &gcc_usb4_1_phy_pcie_pipe_clk.clkr, 8342 [GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_clk_src.clkr, 8343 [GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr, 8344 [GCC_USB4_1_PHY_PLL_PIPE_CLK_SRC] = &gcc_usb4_1_phy_pll_pipe_clk_src.clkr, 8345 [GCC_USB4_1_PHY_RX0_CLK] = &gcc_usb4_1_phy_rx0_clk.clkr, 8346 [GCC_USB4_1_PHY_RX0_CLK_SRC] = &gcc_usb4_1_phy_rx0_clk_src.clkr, 8347 [GCC_USB4_1_PHY_RX1_CLK] = &gcc_usb4_1_phy_rx1_clk.clkr, 8348 [GCC_USB4_1_PHY_RX1_CLK_SRC] = &gcc_usb4_1_phy_rx1_clk_src.clkr, 8349 [GCC_USB4_1_PHY_SYS_CLK_SRC] = &gcc_usb4_1_phy_sys_clk_src.clkr, 8350 [GCC_USB4_1_PHY_USB_PIPE_CLK] = &gcc_usb4_1_phy_usb_pipe_clk.clkr, 8351 [GCC_USB4_1_SB_IF_CLK] = &gcc_usb4_1_sb_if_clk.clkr, 8352 [GCC_USB4_1_SB_IF_CLK_SRC] = &gcc_usb4_1_sb_if_clk_src.clkr, 8353 [GCC_USB4_1_SYS_CLK] = &gcc_usb4_1_sys_clk.clkr, 8354 [GCC_USB4_1_TMU_CLK] = &gcc_usb4_1_tmu_clk.clkr, 8355 [GCC_USB4_1_TMU_CLK_SRC] = &gcc_usb4_1_tmu_clk_src.clkr, 8356 [GCC_USB4_1_UC_HRR_CLK] = &gcc_usb4_1_uc_hrr_clk.clkr, 8357 [GCC_USB4_2_CFG_AHB_CLK] = &gcc_usb4_2_cfg_ahb_clk.clkr, 8358 [GCC_USB4_2_DP0_CLK] = &gcc_usb4_2_dp0_clk.clkr, 8359 [GCC_USB4_2_DP1_CLK] = &gcc_usb4_2_dp1_clk.clkr, 8360 [GCC_USB4_2_MASTER_CLK] = &gcc_usb4_2_master_clk.clkr, 8361 [GCC_USB4_2_MASTER_CLK_SRC] = &gcc_usb4_2_master_clk_src.clkr, 8362 [GCC_USB4_2_PHY_DP0_CLK_SRC] = &gcc_usb4_2_phy_dp0_clk_src.clkr, 8363 [GCC_USB4_2_PHY_DP1_CLK_SRC] = &gcc_usb4_2_phy_dp1_clk_src.clkr, 8364 [GCC_USB4_2_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_2_phy_p2rr2p_pipe_clk.clkr, 8365 [GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_2_phy_p2rr2p_pipe_clk_src.clkr, 8366 [GCC_USB4_2_PHY_PCIE_PIPE_CLK] = &gcc_usb4_2_phy_pcie_pipe_clk.clkr, 8367 [GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_clk_src.clkr, 8368 [GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr, 8369 [GCC_USB4_2_PHY_RX0_CLK] = &gcc_usb4_2_phy_rx0_clk.clkr, 8370 [GCC_USB4_2_PHY_RX0_CLK_SRC] = &gcc_usb4_2_phy_rx0_clk_src.clkr, 8371 [GCC_USB4_2_PHY_RX1_CLK] = &gcc_usb4_2_phy_rx1_clk.clkr, 8372 [GCC_USB4_2_PHY_RX1_CLK_SRC] = &gcc_usb4_2_phy_rx1_clk_src.clkr, 8373 [GCC_USB4_2_PHY_SYS_CLK_SRC] = &gcc_usb4_2_phy_sys_clk_src.clkr, 8374 [GCC_USB4_2_PHY_USB_PIPE_CLK] = &gcc_usb4_2_phy_usb_pipe_clk.clkr, 8375 [GCC_USB4_2_SB_IF_CLK] = &gcc_usb4_2_sb_if_clk.clkr, 8376 [GCC_USB4_2_SB_IF_CLK_SRC] = &gcc_usb4_2_sb_if_clk_src.clkr, 8377 [GCC_USB4_2_SYS_CLK] = &gcc_usb4_2_sys_clk.clkr, 8378 [GCC_USB4_2_TMU_CLK] = &gcc_usb4_2_tmu_clk.clkr, 8379 [GCC_USB4_2_TMU_CLK_SRC] = &gcc_usb4_2_tmu_clk_src.clkr, 8380 [GCC_USB4_2_UC_HRR_CLK] = &gcc_usb4_2_uc_hrr_clk.clkr, 8381 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 8382 [GCC_VIDEO_AXI0C_CLK] = &gcc_video_axi0c_clk.clkr, 8383 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 8384 }; 8385 8386 static struct gdsc *gcc_glymur_gdscs[] = { 8387 [GCC_PCIE_0_TUNNEL_GDSC] = &gcc_pcie_0_tunnel_gdsc, 8388 [GCC_PCIE_1_TUNNEL_GDSC] = &gcc_pcie_1_tunnel_gdsc, 8389 [GCC_PCIE_2_TUNNEL_GDSC] = &gcc_pcie_2_tunnel_gdsc, 8390 [GCC_PCIE_3A_GDSC] = &gcc_pcie_3a_gdsc, 8391 [GCC_PCIE_3A_PHY_GDSC] = &gcc_pcie_3a_phy_gdsc, 8392 [GCC_PCIE_3B_GDSC] = &gcc_pcie_3b_gdsc, 8393 [GCC_PCIE_3B_PHY_GDSC] = &gcc_pcie_3b_phy_gdsc, 8394 [GCC_PCIE_4_GDSC] = &gcc_pcie_4_gdsc, 8395 [GCC_PCIE_4_PHY_GDSC] = &gcc_pcie_4_phy_gdsc, 8396 [GCC_PCIE_5_GDSC] = &gcc_pcie_5_gdsc, 8397 [GCC_PCIE_5_PHY_GDSC] = &gcc_pcie_5_phy_gdsc, 8398 [GCC_PCIE_6_GDSC] = &gcc_pcie_6_gdsc, 8399 [GCC_PCIE_6_PHY_GDSC] = &gcc_pcie_6_phy_gdsc, 8400 [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc, 8401 [GCC_USB20_PRIM_GDSC] = &gcc_usb20_prim_gdsc, 8402 [GCC_USB30_MP_GDSC] = &gcc_usb30_mp_gdsc, 8403 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, 8404 [GCC_USB30_SEC_GDSC] = &gcc_usb30_sec_gdsc, 8405 [GCC_USB30_TERT_GDSC] = &gcc_usb30_tert_gdsc, 8406 [GCC_USB3_MP_SS0_PHY_GDSC] = &gcc_usb3_mp_ss0_phy_gdsc, 8407 [GCC_USB3_MP_SS1_PHY_GDSC] = &gcc_usb3_mp_ss1_phy_gdsc, 8408 [GCC_USB4_0_GDSC] = &gcc_usb4_0_gdsc, 8409 [GCC_USB4_1_GDSC] = &gcc_usb4_1_gdsc, 8410 [GCC_USB4_2_GDSC] = &gcc_usb4_2_gdsc, 8411 [GCC_USB_0_PHY_GDSC] = &gcc_usb_0_phy_gdsc, 8412 [GCC_USB_1_PHY_GDSC] = &gcc_usb_1_phy_gdsc, 8413 [GCC_USB_2_PHY_GDSC] = &gcc_usb_2_phy_gdsc, 8414 }; 8415 8416 static const struct qcom_reset_map gcc_glymur_resets[] = { 8417 [GCC_AV1E_BCR] = { 0x9b028 }, 8418 [GCC_CAMERA_BCR] = { 0x26000 }, 8419 [GCC_DISPLAY_BCR] = { 0x27000 }, 8420 [GCC_EVA_BCR] = { 0x9b000 }, 8421 [GCC_GPU_BCR] = { 0x71000 }, 8422 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0xbc2d0 }, 8423 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0xbc2dc }, 8424 [GCC_PCIE_0_PHY_BCR] = { 0xbc2d8 }, 8425 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0xbc2e0 }, 8426 [GCC_PCIE_0_TUNNEL_BCR] = { 0xc8000 }, 8427 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x7f018 }, 8428 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x7f024 }, 8429 [GCC_PCIE_1_PHY_BCR] = { 0x7f020 }, 8430 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x7f028 }, 8431 [GCC_PCIE_1_TUNNEL_BCR] = { 0x2e000 }, 8432 [GCC_PCIE_2_LINK_DOWN_BCR] = { 0x281d0 }, 8433 [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0x281dc }, 8434 [GCC_PCIE_2_PHY_BCR] = { 0x281d8 }, 8435 [GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0x281e0 }, 8436 [GCC_PCIE_2_TUNNEL_BCR] = { 0xc0000 }, 8437 [GCC_PCIE_3A_BCR] = { 0xdc000 }, 8438 [GCC_PCIE_3A_LINK_DOWN_BCR] = { 0x7b0a0 }, 8439 [GCC_PCIE_3A_NOCSR_COM_PHY_BCR] = { 0x7b0ac }, 8440 [GCC_PCIE_3A_PHY_BCR] = { 0x6c000 }, 8441 [GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR] = { 0x7b0b0 }, 8442 [GCC_PCIE_3B_BCR] = { 0x94000 }, 8443 [GCC_PCIE_3B_LINK_DOWN_BCR] = { 0x7a0c0 }, 8444 [GCC_PCIE_3B_NOCSR_COM_PHY_BCR] = { 0x7a0cc }, 8445 [GCC_PCIE_3B_PHY_BCR] = { 0x75000 }, 8446 [GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR] = { 0x7a0c8 }, 8447 [GCC_PCIE_4_BCR] = { 0x88000 }, 8448 [GCC_PCIE_4_LINK_DOWN_BCR] = { 0x980c0 }, 8449 [GCC_PCIE_4_NOCSR_COM_PHY_BCR] = { 0x980cc }, 8450 [GCC_PCIE_4_PHY_BCR] = { 0xd3000 }, 8451 [GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] = { 0x980d0 }, 8452 [GCC_PCIE_5_BCR] = { 0xc3000 }, 8453 [GCC_PCIE_5_LINK_DOWN_BCR] = { 0x850c0 }, 8454 [GCC_PCIE_5_NOCSR_COM_PHY_BCR] = { 0x850cc }, 8455 [GCC_PCIE_5_PHY_BCR] = { 0xd2000 }, 8456 [GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR] = { 0x850d0 }, 8457 [GCC_PCIE_6_BCR] = { 0x8a000 }, 8458 [GCC_PCIE_6_LINK_DOWN_BCR] = { 0x3a0b0 }, 8459 [GCC_PCIE_6_NOCSR_COM_PHY_BCR] = { 0x3a0bc }, 8460 [GCC_PCIE_6_PHY_BCR] = { 0xd4000 }, 8461 [GCC_PCIE_6_PHY_NOCSR_COM_PHY_BCR] = { 0x3a0c0 }, 8462 [GCC_PCIE_NOC_BCR] = { 0xba294 }, 8463 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 8464 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c }, 8465 [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 }, 8466 [GCC_PCIE_RSCC_BCR] = { 0xb8000 }, 8467 [GCC_PDM_BCR] = { 0x33000 }, 8468 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x28000 }, 8469 [GCC_QUPV3_WRAPPER_1_BCR] = { 0xb3000 }, 8470 [GCC_QUPV3_WRAPPER_2_BCR] = { 0xb4000 }, 8471 [GCC_QUPV3_WRAPPER_OOB_BCR] = { 0xe7000 }, 8472 [GCC_QUSB2PHY_HS0_MP_BCR] = { 0xca000 }, 8473 [GCC_QUSB2PHY_HS1_MP_BCR] = { 0xe6000 }, 8474 [GCC_QUSB2PHY_PRIM_BCR] = { 0xad024 }, 8475 [GCC_QUSB2PHY_SEC_BCR] = { 0xae000 }, 8476 [GCC_QUSB2PHY_TERT_BCR] = { 0xc9000 }, 8477 [GCC_QUSB2PHY_USB20_HS_BCR] = { 0xe9000 }, 8478 [GCC_SDCC2_BCR] = { 0xb0000 }, 8479 [GCC_SDCC4_BCR] = { 0xdf000 }, 8480 [GCC_TCSR_PCIE_BCR] = { 0x281e4 }, 8481 [GCC_UFS_PHY_BCR] = { 0x77004 }, 8482 [GCC_USB20_PRIM_BCR] = { 0xbc000 }, 8483 [GCC_USB30_MP_BCR] = { 0x9a00c }, 8484 [GCC_USB30_PRIM_BCR] = { 0x3f018 }, 8485 [GCC_USB30_SEC_BCR] = { 0xe200c }, 8486 [GCC_USB30_TERT_BCR] = { 0xe100c }, 8487 [GCC_USB3_MP_SS0_PHY_BCR] = { 0x54008 }, 8488 [GCC_USB3_MP_SS1_PHY_BCR] = { 0x54028 }, 8489 [GCC_USB3_PHY_PRIM_BCR] = { 0xdb000 }, 8490 [GCC_USB3_PHY_SEC_BCR] = { 0x2c000 }, 8491 [GCC_USB3_PHY_TERT_BCR] = { 0xbe000 }, 8492 [GCC_USB3_UNIPHY_MP0_BCR] = { 0x54000 }, 8493 [GCC_USB3_UNIPHY_MP1_BCR] = { 0x54020 }, 8494 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0xdb004 }, 8495 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x2c004 }, 8496 [GCC_USB3PHY_PHY_TERT_BCR] = { 0xbe004 }, 8497 [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x54004 }, 8498 [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x54024 }, 8499 [GCC_USB4_0_BCR] = { 0x2b004 }, 8500 [GCC_USB4_0_DP0_PHY_PRIM_BCR] = { 0xdb010 }, 8501 [GCC_USB4_1_BCR] = { 0x2d004 }, 8502 [GCC_USB4_2_BCR] = { 0xe0004 }, 8503 [GCC_USB_0_PHY_BCR] = { 0xdb020 }, 8504 [GCC_USB_1_PHY_BCR] = { 0x2c020 }, 8505 [GCC_USB_2_PHY_BCR] = { 0xbe020 }, 8506 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x3201c, 2 }, 8507 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x32044, 2 }, 8508 [GCC_VIDEO_BCR] = { 0x32000 }, 8509 [GCC_VIDEO_AXI0C_CLK_ARES] = { 0x32030, 2 }, 8510 }; 8511 8512 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 8513 DEFINE_RCG_DFS(gcc_qupv3_oob_qspi_s0_clk_src), 8514 DEFINE_RCG_DFS(gcc_qupv3_oob_qspi_s1_clk_src), 8515 DEFINE_RCG_DFS(gcc_qupv3_wrap0_qspi_s2_clk_src), 8516 DEFINE_RCG_DFS(gcc_qupv3_wrap0_qspi_s3_clk_src), 8517 DEFINE_RCG_DFS(gcc_qupv3_wrap0_qspi_s6_clk_src), 8518 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 8519 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 8520 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 8521 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 8522 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 8523 DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_s2_clk_src), 8524 DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_s3_clk_src), 8525 DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_s6_clk_src), 8526 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 8527 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 8528 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 8529 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 8530 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 8531 DEFINE_RCG_DFS(gcc_qupv3_wrap2_qspi_s2_clk_src), 8532 DEFINE_RCG_DFS(gcc_qupv3_wrap2_qspi_s3_clk_src), 8533 DEFINE_RCG_DFS(gcc_qupv3_wrap2_qspi_s6_clk_src), 8534 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 8535 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 8536 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 8537 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), 8538 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src), 8539 }; 8540 8541 static const u32 gcc_glymur_critical_cbcrs[] = { 8542 0x26004, /* GCC_CAMERA_AHB_CLK */ 8543 0x26040, /* GCC_CAMERA_XO_CLK */ 8544 0x27004, /* GCC_DISP_AHB_CLK */ 8545 0x71004, /* GCC_GPU_CFG_AHB_CLK */ 8546 0x32004, /* GCC_VIDEO_AHB_CLK */ 8547 0x32058, /* GCC_VIDEO_XO_CLK */ 8548 }; 8549 8550 static const struct regmap_config gcc_glymur_regmap_config = { 8551 .reg_bits = 32, 8552 .reg_stride = 4, 8553 .val_bits = 32, 8554 .max_register = 0x1f8ff0, 8555 .fast_io = true, 8556 }; 8557 8558 static void clk_glymur_regs_configure(struct device *dev, struct regmap *regmap) 8559 { 8560 /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ 8561 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); 8562 } 8563 8564 static const struct qcom_cc_driver_data gcc_glymur_driver_data = { 8565 .clk_cbcrs = gcc_glymur_critical_cbcrs, 8566 .num_clk_cbcrs = ARRAY_SIZE(gcc_glymur_critical_cbcrs), 8567 .dfs_rcgs = gcc_dfs_clocks, 8568 .num_dfs_rcgs = ARRAY_SIZE(gcc_dfs_clocks), 8569 .clk_regs_configure = clk_glymur_regs_configure, 8570 }; 8571 8572 static const struct qcom_cc_desc gcc_glymur_desc = { 8573 .config = &gcc_glymur_regmap_config, 8574 .clks = gcc_glymur_clocks, 8575 .num_clks = ARRAY_SIZE(gcc_glymur_clocks), 8576 .resets = gcc_glymur_resets, 8577 .num_resets = ARRAY_SIZE(gcc_glymur_resets), 8578 .gdscs = gcc_glymur_gdscs, 8579 .num_gdscs = ARRAY_SIZE(gcc_glymur_gdscs), 8580 .driver_data = &gcc_glymur_driver_data, 8581 }; 8582 8583 static const struct of_device_id gcc_glymur_match_table[] = { 8584 { .compatible = "qcom,glymur-gcc" }, 8585 { } 8586 }; 8587 MODULE_DEVICE_TABLE(of, gcc_glymur_match_table); 8588 8589 static int gcc_glymur_probe(struct platform_device *pdev) 8590 { 8591 return qcom_cc_probe(pdev, &gcc_glymur_desc); 8592 } 8593 8594 static struct platform_driver gcc_glymur_driver = { 8595 .probe = gcc_glymur_probe, 8596 .driver = { 8597 .name = "gcc-glymur", 8598 .of_match_table = gcc_glymur_match_table, 8599 }, 8600 }; 8601 8602 static int __init gcc_glymur_init(void) 8603 { 8604 return platform_driver_register(&gcc_glymur_driver); 8605 } 8606 subsys_initcall(gcc_glymur_init); 8607 8608 static void __exit gcc_glymur_exit(void) 8609 { 8610 platform_driver_unregister(&gcc_glymur_driver); 8611 } 8612 module_exit(gcc_glymur_exit); 8613 8614 MODULE_DESCRIPTION("QTI GCC Glymur Driver"); 8615 MODULE_LICENSE("GPL"); 8616