1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2025, Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,glymur-gcc.h> 12 13 #include "clk-alpha-pll.h" 14 #include "clk-branch.h" 15 #include "clk-pll.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "clk-regmap-divider.h" 19 #include "clk-regmap-mux.h" 20 #include "clk-regmap-phy-mux.h" 21 #include "common.h" 22 #include "gdsc.h" 23 #include "reset.h" 24 25 enum { 26 DT_BI_TCXO, 27 DT_BI_TCXO_AO, 28 DT_SLEEP_CLK, 29 DT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC, 30 DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC, 31 DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC, 32 DT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC, 33 DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC, 34 DT_GCC_USB4_1_PHY_DP0_GMUX_2_CLK_SRC, 35 DT_GCC_USB4_1_PHY_DP1_GMUX_2_CLK_SRC, 36 DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC, 37 DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, 38 DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 39 DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC, 40 DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC, 41 DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC, 42 DT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC, 43 DT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC, 44 DT_PCIE_3A_PIPE_CLK, 45 DT_PCIE_3B_PIPE_CLK, 46 DT_PCIE_4_PIPE_CLK, 47 DT_PCIE_5_PIPE_CLK, 48 DT_PCIE_6_PIPE_CLK, 49 DT_QUSB4PHY_0_GCC_USB4_RX0_CLK, 50 DT_QUSB4PHY_0_GCC_USB4_RX1_CLK, 51 DT_QUSB4PHY_1_GCC_USB4_RX0_CLK, 52 DT_QUSB4PHY_1_GCC_USB4_RX1_CLK, 53 DT_QUSB4PHY_2_GCC_USB4_RX0_CLK, 54 DT_QUSB4PHY_2_GCC_USB4_RX1_CLK, 55 DT_UFS_PHY_RX_SYMBOL_0_CLK, 56 DT_UFS_PHY_RX_SYMBOL_1_CLK, 57 DT_UFS_PHY_TX_SYMBOL_0_CLK, 58 DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 59 DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 60 DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 61 DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK, 62 DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK, 63 DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 64 DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 65 DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 66 DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 67 DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 68 DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 69 }; 70 71 enum { 72 P_BI_TCXO, 73 P_GCC_GPLL0_OUT_EVEN, 74 P_GCC_GPLL0_OUT_MAIN, 75 P_GCC_GPLL14_OUT_EVEN, 76 P_GCC_GPLL14_OUT_MAIN, 77 P_GCC_GPLL1_OUT_MAIN, 78 P_GCC_GPLL4_OUT_MAIN, 79 P_GCC_GPLL5_OUT_MAIN, 80 P_GCC_GPLL7_OUT_MAIN, 81 P_GCC_GPLL8_OUT_MAIN, 82 P_GCC_GPLL9_OUT_MAIN, 83 P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 84 P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC, 85 P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC, 86 P_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC, 87 P_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC, 88 P_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC, 89 P_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC, 90 P_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC, 91 P_GCC_USB4_1_PHY_DP0_GMUX_2_CLK_SRC, 92 P_GCC_USB4_1_PHY_DP1_GMUX_2_CLK_SRC, 93 P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC, 94 P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, 95 P_GCC_USB4_1_PHY_PLL_PIPE_CLK_SRC, 96 P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 97 P_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC, 98 P_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC, 99 P_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC, 100 P_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC, 101 P_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC, 102 P_PCIE_3A_PIPE_CLK, 103 P_PCIE_3B_PIPE_CLK, 104 P_PCIE_4_PIPE_CLK, 105 P_PCIE_5_PIPE_CLK, 106 P_PCIE_6_PIPE_CLK, 107 P_QUSB4PHY_0_GCC_USB4_RX0_CLK, 108 P_QUSB4PHY_0_GCC_USB4_RX1_CLK, 109 P_QUSB4PHY_1_GCC_USB4_RX0_CLK, 110 P_QUSB4PHY_1_GCC_USB4_RX1_CLK, 111 P_QUSB4PHY_2_GCC_USB4_RX0_CLK, 112 P_QUSB4PHY_2_GCC_USB4_RX1_CLK, 113 P_SLEEP_CLK, 114 P_UFS_PHY_RX_SYMBOL_0_CLK, 115 P_UFS_PHY_RX_SYMBOL_1_CLK, 116 P_UFS_PHY_TX_SYMBOL_0_CLK, 117 P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 118 P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 119 P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 120 P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK, 121 P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK, 122 P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 123 P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 124 P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 125 P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 126 P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 127 P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 128 }; 129 130 static struct clk_alpha_pll gcc_gpll0 = { 131 .offset = 0x0, 132 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 133 .clkr = { 134 .enable_reg = 0x62040, 135 .enable_mask = BIT(0), 136 .hw.init = &(const struct clk_init_data) { 137 .name = "gcc_gpll0", 138 .parent_data = &(const struct clk_parent_data) { 139 .index = DT_BI_TCXO, 140 }, 141 .num_parents = 1, 142 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 143 }, 144 }, 145 }; 146 147 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 148 { 0x1, 2 }, 149 { } 150 }; 151 152 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 153 .offset = 0x0, 154 .post_div_shift = 10, 155 .post_div_table = post_div_table_gcc_gpll0_out_even, 156 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 157 .width = 4, 158 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 159 .clkr.hw.init = &(const struct clk_init_data) { 160 .name = "gcc_gpll0_out_even", 161 .parent_hws = (const struct clk_hw*[]) { 162 &gcc_gpll0.clkr.hw, 163 }, 164 .num_parents = 1, 165 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 166 }, 167 }; 168 169 static struct clk_alpha_pll gcc_gpll1 = { 170 .offset = 0x1000, 171 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 172 .clkr = { 173 .enable_reg = 0x62040, 174 .enable_mask = BIT(1), 175 .hw.init = &(const struct clk_init_data) { 176 .name = "gcc_gpll1", 177 .parent_data = &(const struct clk_parent_data) { 178 .index = DT_BI_TCXO, 179 }, 180 .num_parents = 1, 181 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 182 }, 183 }, 184 }; 185 186 static struct clk_alpha_pll gcc_gpll14 = { 187 .offset = 0xe000, 188 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 189 .clkr = { 190 .enable_reg = 0x62040, 191 .enable_mask = BIT(14), 192 .hw.init = &(const struct clk_init_data) { 193 .name = "gcc_gpll14", 194 .parent_data = &(const struct clk_parent_data) { 195 .index = DT_BI_TCXO, 196 }, 197 .num_parents = 1, 198 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 199 }, 200 }, 201 }; 202 203 static const struct clk_div_table post_div_table_gcc_gpll14_out_even[] = { 204 { 0x1, 2 }, 205 { } 206 }; 207 208 static struct clk_alpha_pll_postdiv gcc_gpll14_out_even = { 209 .offset = 0xe000, 210 .post_div_shift = 10, 211 .post_div_table = post_div_table_gcc_gpll14_out_even, 212 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll14_out_even), 213 .width = 4, 214 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 215 .clkr.hw.init = &(const struct clk_init_data) { 216 .name = "gcc_gpll14_out_even", 217 .parent_hws = (const struct clk_hw*[]) { 218 &gcc_gpll14.clkr.hw, 219 }, 220 .num_parents = 1, 221 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 222 }, 223 }; 224 225 static struct clk_alpha_pll gcc_gpll4 = { 226 .offset = 0x4000, 227 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 228 .clkr = { 229 .enable_reg = 0x62040, 230 .enable_mask = BIT(4), 231 .hw.init = &(const struct clk_init_data) { 232 .name = "gcc_gpll4", 233 .parent_data = &(const struct clk_parent_data) { 234 .index = DT_BI_TCXO, 235 }, 236 .num_parents = 1, 237 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 238 }, 239 }, 240 }; 241 242 static struct clk_alpha_pll gcc_gpll5 = { 243 .offset = 0x5000, 244 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 245 .clkr = { 246 .enable_reg = 0x62040, 247 .enable_mask = BIT(5), 248 .hw.init = &(const struct clk_init_data) { 249 .name = "gcc_gpll5", 250 .parent_data = &(const struct clk_parent_data) { 251 .index = DT_BI_TCXO, 252 }, 253 .num_parents = 1, 254 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 255 }, 256 }, 257 }; 258 259 static struct clk_alpha_pll gcc_gpll7 = { 260 .offset = 0x7000, 261 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 262 .clkr = { 263 .enable_reg = 0x62040, 264 .enable_mask = BIT(7), 265 .hw.init = &(const struct clk_init_data) { 266 .name = "gcc_gpll7", 267 .parent_data = &(const struct clk_parent_data) { 268 .index = DT_BI_TCXO, 269 }, 270 .num_parents = 1, 271 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 272 }, 273 }, 274 }; 275 276 static struct clk_alpha_pll gcc_gpll8 = { 277 .offset = 0x8000, 278 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 279 .clkr = { 280 .enable_reg = 0x62040, 281 .enable_mask = BIT(8), 282 .hw.init = &(const struct clk_init_data) { 283 .name = "gcc_gpll8", 284 .parent_data = &(const struct clk_parent_data) { 285 .index = DT_BI_TCXO, 286 }, 287 .num_parents = 1, 288 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 289 }, 290 }, 291 }; 292 293 static struct clk_alpha_pll gcc_gpll9 = { 294 .offset = 0x9000, 295 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 296 .clkr = { 297 .enable_reg = 0x62040, 298 .enable_mask = BIT(9), 299 .hw.init = &(const struct clk_init_data) { 300 .name = "gcc_gpll9", 301 .parent_data = &(const struct clk_parent_data) { 302 .index = DT_BI_TCXO, 303 }, 304 .num_parents = 1, 305 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 306 }, 307 }, 308 }; 309 310 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src; 311 static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src; 312 static struct clk_regmap_mux gcc_usb3_tert_phy_pipe_clk_src; 313 314 static struct clk_rcg2 gcc_usb4_1_phy_pll_pipe_clk_src; 315 316 static const struct parent_map gcc_parent_map_0[] = { 317 { P_BI_TCXO, 0 }, 318 { P_GCC_GPLL0_OUT_MAIN, 1 }, 319 { P_GCC_GPLL0_OUT_EVEN, 6 }, 320 }; 321 322 static const struct clk_parent_data gcc_parent_data_0[] = { 323 { .index = DT_BI_TCXO }, 324 { .hw = &gcc_gpll0.clkr.hw }, 325 { .hw = &gcc_gpll0_out_even.clkr.hw }, 326 }; 327 328 static const struct parent_map gcc_parent_map_1[] = { 329 { P_BI_TCXO, 0 }, 330 { P_GCC_GPLL0_OUT_MAIN, 1 }, 331 { P_GCC_GPLL1_OUT_MAIN, 4 }, 332 { P_GCC_GPLL0_OUT_EVEN, 6 }, 333 }; 334 335 static const struct clk_parent_data gcc_parent_data_1[] = { 336 { .index = DT_BI_TCXO }, 337 { .hw = &gcc_gpll0.clkr.hw }, 338 { .hw = &gcc_gpll1.clkr.hw }, 339 { .hw = &gcc_gpll0_out_even.clkr.hw }, 340 }; 341 342 static const struct parent_map gcc_parent_map_2[] = { 343 { P_BI_TCXO, 0 }, 344 { P_SLEEP_CLK, 5 }, 345 }; 346 347 static const struct clk_parent_data gcc_parent_data_2[] = { 348 { .index = DT_BI_TCXO }, 349 { .index = DT_SLEEP_CLK }, 350 }; 351 352 static const struct parent_map gcc_parent_map_3[] = { 353 { P_BI_TCXO, 0 }, 354 { P_GCC_GPLL0_OUT_MAIN, 1 }, 355 { P_GCC_GPLL1_OUT_MAIN, 4 }, 356 { P_GCC_GPLL4_OUT_MAIN, 5 }, 357 { P_GCC_GPLL0_OUT_EVEN, 6 }, 358 }; 359 360 static const struct clk_parent_data gcc_parent_data_3[] = { 361 { .index = DT_BI_TCXO }, 362 { .hw = &gcc_gpll0.clkr.hw }, 363 { .hw = &gcc_gpll1.clkr.hw }, 364 { .hw = &gcc_gpll4.clkr.hw }, 365 { .hw = &gcc_gpll0_out_even.clkr.hw }, 366 }; 367 368 static const struct parent_map gcc_parent_map_4[] = { 369 { P_BI_TCXO, 0 }, 370 { P_GCC_GPLL0_OUT_MAIN, 1 }, 371 { P_SLEEP_CLK, 5 }, 372 { P_GCC_GPLL0_OUT_EVEN, 6 }, 373 }; 374 375 static const struct clk_parent_data gcc_parent_data_4[] = { 376 { .index = DT_BI_TCXO }, 377 { .hw = &gcc_gpll0.clkr.hw }, 378 { .index = DT_SLEEP_CLK }, 379 { .hw = &gcc_gpll0_out_even.clkr.hw }, 380 }; 381 382 static const struct parent_map gcc_parent_map_5[] = { 383 { P_BI_TCXO, 0 }, 384 }; 385 386 static const struct clk_parent_data gcc_parent_data_5[] = { 387 { .index = DT_BI_TCXO }, 388 }; 389 390 static const struct parent_map gcc_parent_map_6[] = { 391 { P_BI_TCXO, 0 }, 392 { P_GCC_GPLL0_OUT_MAIN, 1 }, 393 { P_GCC_GPLL4_OUT_MAIN, 5 }, 394 { P_GCC_GPLL0_OUT_EVEN, 6 }, 395 }; 396 397 static const struct clk_parent_data gcc_parent_data_6[] = { 398 { .index = DT_BI_TCXO }, 399 { .hw = &gcc_gpll0.clkr.hw }, 400 { .hw = &gcc_gpll4.clkr.hw }, 401 { .hw = &gcc_gpll0_out_even.clkr.hw }, 402 }; 403 404 static const struct parent_map gcc_parent_map_7[] = { 405 { P_BI_TCXO, 0 }, 406 { P_GCC_GPLL14_OUT_MAIN, 1 }, 407 { P_GCC_GPLL14_OUT_EVEN, 6 }, 408 }; 409 410 static const struct clk_parent_data gcc_parent_data_7[] = { 411 { .index = DT_BI_TCXO }, 412 { .hw = &gcc_gpll14.clkr.hw }, 413 { .hw = &gcc_gpll14_out_even.clkr.hw }, 414 }; 415 416 static const struct parent_map gcc_parent_map_8[] = { 417 { P_BI_TCXO, 0 }, 418 { P_GCC_GPLL4_OUT_MAIN, 5 }, 419 }; 420 421 static const struct clk_parent_data gcc_parent_data_8[] = { 422 { .index = DT_BI_TCXO }, 423 { .hw = &gcc_gpll4.clkr.hw }, 424 }; 425 426 static const struct parent_map gcc_parent_map_9[] = { 427 { P_BI_TCXO, 0 }, 428 { P_GCC_GPLL0_OUT_MAIN, 1 }, 429 { P_GCC_GPLL8_OUT_MAIN, 2 }, 430 { P_GCC_GPLL0_OUT_EVEN, 6 }, 431 }; 432 433 static const struct clk_parent_data gcc_parent_data_9[] = { 434 { .index = DT_BI_TCXO }, 435 { .hw = &gcc_gpll0.clkr.hw }, 436 { .hw = &gcc_gpll8.clkr.hw }, 437 { .hw = &gcc_gpll0_out_even.clkr.hw }, 438 }; 439 440 static const struct parent_map gcc_parent_map_10[] = { 441 { P_BI_TCXO, 0 }, 442 { P_GCC_GPLL0_OUT_MAIN, 1 }, 443 { P_GCC_GPLL7_OUT_MAIN, 2 }, 444 }; 445 446 static const struct clk_parent_data gcc_parent_data_10[] = { 447 { .index = DT_BI_TCXO }, 448 { .hw = &gcc_gpll0.clkr.hw }, 449 { .hw = &gcc_gpll7.clkr.hw }, 450 }; 451 452 static const struct parent_map gcc_parent_map_11[] = { 453 { P_BI_TCXO, 0 }, 454 { P_GCC_GPLL0_OUT_MAIN, 1 }, 455 { P_GCC_GPLL7_OUT_MAIN, 2 }, 456 { P_GCC_GPLL8_OUT_MAIN, 3 }, 457 { P_SLEEP_CLK, 5 }, 458 }; 459 460 static const struct clk_parent_data gcc_parent_data_11[] = { 461 { .index = DT_BI_TCXO }, 462 { .hw = &gcc_gpll0.clkr.hw }, 463 { .hw = &gcc_gpll7.clkr.hw }, 464 { .hw = &gcc_gpll8.clkr.hw }, 465 { .index = DT_SLEEP_CLK }, 466 }; 467 468 static const struct parent_map gcc_parent_map_17[] = { 469 { P_BI_TCXO, 0 }, 470 { P_GCC_GPLL0_OUT_MAIN, 1 }, 471 { P_GCC_GPLL9_OUT_MAIN, 2 }, 472 { P_GCC_GPLL4_OUT_MAIN, 5 }, 473 { P_GCC_GPLL0_OUT_EVEN, 6 }, 474 }; 475 476 static const struct clk_parent_data gcc_parent_data_17[] = { 477 { .index = DT_BI_TCXO }, 478 { .hw = &gcc_gpll0.clkr.hw }, 479 { .hw = &gcc_gpll9.clkr.hw }, 480 { .hw = &gcc_gpll4.clkr.hw }, 481 { .hw = &gcc_gpll0_out_even.clkr.hw }, 482 }; 483 484 static const struct parent_map gcc_parent_map_18[] = { 485 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 }, 486 { P_BI_TCXO, 2 }, 487 }; 488 489 static const struct clk_parent_data gcc_parent_data_18[] = { 490 { .index = DT_UFS_PHY_RX_SYMBOL_0_CLK }, 491 { .index = DT_BI_TCXO }, 492 }; 493 494 static const struct parent_map gcc_parent_map_19[] = { 495 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 }, 496 { P_BI_TCXO, 2 }, 497 }; 498 499 static const struct clk_parent_data gcc_parent_data_19[] = { 500 { .index = DT_UFS_PHY_RX_SYMBOL_1_CLK }, 501 { .index = DT_BI_TCXO }, 502 }; 503 504 static const struct parent_map gcc_parent_map_20[] = { 505 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 }, 506 { P_BI_TCXO, 2 }, 507 }; 508 509 static const struct clk_parent_data gcc_parent_data_20[] = { 510 { .index = DT_UFS_PHY_TX_SYMBOL_0_CLK }, 511 { .index = DT_BI_TCXO }, 512 }; 513 514 static const struct parent_map gcc_parent_map_21[] = { 515 { P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 0 }, 516 { P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 }, 517 { P_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC, 3 }, 518 }; 519 520 static const struct clk_parent_data gcc_parent_data_21[] = { 521 { .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw }, 522 { .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 523 { .index = DT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC }, 524 }; 525 526 static const struct parent_map gcc_parent_map_22[] = { 527 { P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC, 0 }, 528 { P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 }, 529 { P_GCC_USB4_1_PHY_PLL_PIPE_CLK_SRC, 2 }, 530 { P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, 3 }, 531 }; 532 533 static const struct clk_parent_data gcc_parent_data_22[] = { 534 { .hw = &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw }, 535 { .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 536 { .hw = &gcc_usb4_1_phy_pll_pipe_clk_src.clkr.hw }, 537 { .index = DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC }, 538 }; 539 540 static const struct parent_map gcc_parent_map_23[] = { 541 { P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC, 0 }, 542 { P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 }, 543 { P_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC, 3 }, 544 }; 545 546 static const struct clk_parent_data gcc_parent_data_23[] = { 547 { .hw = &gcc_usb3_tert_phy_pipe_clk_src.clkr.hw }, 548 { .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 549 { .index = DT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC }, 550 }; 551 552 static const struct parent_map gcc_parent_map_24[] = { 553 { P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK, 0 }, 554 { P_BI_TCXO, 2 }, 555 }; 556 557 static const struct clk_parent_data gcc_parent_data_24[] = { 558 { .index = DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK }, 559 { .index = DT_BI_TCXO }, 560 }; 561 562 static const struct parent_map gcc_parent_map_25[] = { 563 { P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK, 0 }, 564 { P_BI_TCXO, 2 }, 565 }; 566 567 static const struct clk_parent_data gcc_parent_data_25[] = { 568 { .index = DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK }, 569 { .index = DT_BI_TCXO }, 570 }; 571 572 static const struct parent_map gcc_parent_map_26[] = { 573 { P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 574 { P_BI_TCXO, 2 }, 575 }; 576 577 static const struct clk_parent_data gcc_parent_data_26[] = { 578 { .index = DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK }, 579 { .index = DT_BI_TCXO }, 580 }; 581 582 static const struct parent_map gcc_parent_map_27[] = { 583 { P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 584 { P_BI_TCXO, 2 }, 585 }; 586 587 static const struct clk_parent_data gcc_parent_data_27[] = { 588 { .index = DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK }, 589 { .index = DT_BI_TCXO }, 590 }; 591 592 static const struct parent_map gcc_parent_map_28[] = { 593 { P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 594 { P_BI_TCXO, 2 }, 595 }; 596 597 static const struct clk_parent_data gcc_parent_data_28[] = { 598 { .index = DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK }, 599 { .index = DT_BI_TCXO }, 600 }; 601 602 static const struct parent_map gcc_parent_map_29[] = { 603 { P_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC, 0 }, 604 { P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 }, 605 }; 606 607 static const struct clk_parent_data gcc_parent_data_29[] = { 608 { .index = DT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC }, 609 { .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 610 }; 611 612 static const struct parent_map gcc_parent_map_30[] = { 613 { P_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC, 0 }, 614 { P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 }, 615 }; 616 617 static const struct clk_parent_data gcc_parent_data_30[] = { 618 { .index = DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC }, 619 { .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 620 }; 621 622 static const struct parent_map gcc_parent_map_31[] = { 623 { P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 }, 624 { P_BI_TCXO, 2 }, 625 }; 626 627 static const struct clk_parent_data gcc_parent_data_31[] = { 628 { .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK }, 629 { .index = DT_BI_TCXO }, 630 }; 631 632 static const struct parent_map gcc_parent_map_32[] = { 633 { P_BI_TCXO, 0 }, 634 { P_GCC_GPLL0_OUT_MAIN, 1 }, 635 { P_GCC_GPLL7_OUT_MAIN, 2 }, 636 { P_SLEEP_CLK, 5 }, 637 }; 638 639 static const struct clk_parent_data gcc_parent_data_32[] = { 640 { .index = DT_BI_TCXO }, 641 { .hw = &gcc_gpll0.clkr.hw }, 642 { .hw = &gcc_gpll7.clkr.hw }, 643 { .index = DT_SLEEP_CLK }, 644 }; 645 646 static const struct parent_map gcc_parent_map_33[] = { 647 { P_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 }, 648 { P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 1 }, 649 }; 650 651 static const struct clk_parent_data gcc_parent_data_33[] = { 652 { .index = DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC }, 653 { .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK }, 654 }; 655 656 static const struct parent_map gcc_parent_map_34[] = { 657 { P_QUSB4PHY_0_GCC_USB4_RX0_CLK, 0 }, 658 { P_BI_TCXO, 2 }, 659 }; 660 661 static const struct clk_parent_data gcc_parent_data_34[] = { 662 { .index = DT_QUSB4PHY_0_GCC_USB4_RX0_CLK }, 663 { .index = DT_BI_TCXO }, 664 }; 665 666 static const struct parent_map gcc_parent_map_35[] = { 667 { P_QUSB4PHY_0_GCC_USB4_RX1_CLK, 0 }, 668 { P_BI_TCXO, 2 }, 669 }; 670 671 static const struct clk_parent_data gcc_parent_data_35[] = { 672 { .index = DT_QUSB4PHY_0_GCC_USB4_RX1_CLK }, 673 { .index = DT_BI_TCXO }, 674 }; 675 676 static const struct parent_map gcc_parent_map_36[] = { 677 { P_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC, 0 }, 678 { P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 }, 679 }; 680 681 static const struct clk_parent_data gcc_parent_data_36[] = { 682 { .index = DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC }, 683 { .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK }, 684 }; 685 686 static const struct parent_map gcc_parent_map_37[] = { 687 { P_GCC_USB4_1_PHY_DP0_GMUX_2_CLK_SRC, 0 }, 688 { P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 }, 689 }; 690 691 static const struct clk_parent_data gcc_parent_data_37[] = { 692 { .index = DT_GCC_USB4_1_PHY_DP0_GMUX_2_CLK_SRC }, 693 { .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 694 }; 695 696 static const struct parent_map gcc_parent_map_38[] = { 697 { P_GCC_USB4_1_PHY_DP1_GMUX_2_CLK_SRC, 0 }, 698 { P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 }, 699 }; 700 701 static const struct clk_parent_data gcc_parent_data_38[] = { 702 { .index = DT_GCC_USB4_1_PHY_DP1_GMUX_2_CLK_SRC }, 703 { .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 704 }; 705 706 static const struct parent_map gcc_parent_map_39[] = { 707 { P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 }, 708 { P_BI_TCXO, 2 }, 709 }; 710 711 static const struct clk_parent_data gcc_parent_data_39[] = { 712 { .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK }, 713 { .index = DT_BI_TCXO }, 714 }; 715 716 static const struct parent_map gcc_parent_map_40[] = { 717 { P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 }, 718 { P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 1 }, 719 }; 720 721 static const struct clk_parent_data gcc_parent_data_40[] = { 722 { .index = DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC }, 723 { .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK }, 724 }; 725 726 static const struct parent_map gcc_parent_map_41[] = { 727 { P_BI_TCXO, 0 }, 728 { P_GCC_GPLL0_OUT_MAIN, 1 }, 729 { P_GCC_GPLL5_OUT_MAIN, 3 }, 730 { P_GCC_GPLL0_OUT_EVEN, 6 }, 731 }; 732 733 static const struct clk_parent_data gcc_parent_data_41[] = { 734 { .index = DT_BI_TCXO }, 735 { .hw = &gcc_gpll0.clkr.hw }, 736 { .hw = &gcc_gpll5.clkr.hw }, 737 { .hw = &gcc_gpll0_out_even.clkr.hw }, 738 }; 739 740 static const struct parent_map gcc_parent_map_42[] = { 741 { P_QUSB4PHY_1_GCC_USB4_RX0_CLK, 0 }, 742 { P_BI_TCXO, 2 }, 743 }; 744 745 static const struct clk_parent_data gcc_parent_data_42[] = { 746 { .index = DT_QUSB4PHY_1_GCC_USB4_RX0_CLK }, 747 { .index = DT_BI_TCXO }, 748 }; 749 750 static const struct parent_map gcc_parent_map_43[] = { 751 { P_QUSB4PHY_1_GCC_USB4_RX1_CLK, 0 }, 752 { P_BI_TCXO, 2 }, 753 }; 754 755 static const struct clk_parent_data gcc_parent_data_43[] = { 756 { .index = DT_QUSB4PHY_1_GCC_USB4_RX1_CLK }, 757 { .index = DT_BI_TCXO }, 758 }; 759 760 static const struct parent_map gcc_parent_map_44[] = { 761 { P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 0 }, 762 { P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 }, 763 }; 764 765 static const struct clk_parent_data gcc_parent_data_44[] = { 766 { .index = DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC }, 767 { .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK }, 768 }; 769 770 static const struct parent_map gcc_parent_map_45[] = { 771 { P_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC, 0 }, 772 { P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 }, 773 }; 774 775 static const struct clk_parent_data gcc_parent_data_45[] = { 776 { .index = DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC }, 777 { .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 778 }; 779 780 static const struct parent_map gcc_parent_map_46[] = { 781 { P_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC, 0 }, 782 { P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 }, 783 }; 784 785 static const struct clk_parent_data gcc_parent_data_46[] = { 786 { .index = DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC }, 787 { .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, 788 }; 789 790 static const struct parent_map gcc_parent_map_47[] = { 791 { P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 }, 792 { P_BI_TCXO, 2 }, 793 }; 794 795 static const struct clk_parent_data gcc_parent_data_47[] = { 796 { .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK }, 797 { .index = DT_BI_TCXO }, 798 }; 799 800 static const struct parent_map gcc_parent_map_48[] = { 801 { P_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 }, 802 { P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 1 }, 803 }; 804 805 static const struct clk_parent_data gcc_parent_data_48[] = { 806 { .index = DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC }, 807 { .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK }, 808 }; 809 810 static const struct parent_map gcc_parent_map_49[] = { 811 { P_QUSB4PHY_2_GCC_USB4_RX0_CLK, 0 }, 812 { P_BI_TCXO, 2 }, 813 }; 814 815 static const struct clk_parent_data gcc_parent_data_49[] = { 816 { .index = DT_QUSB4PHY_2_GCC_USB4_RX0_CLK }, 817 { .index = DT_BI_TCXO }, 818 }; 819 820 static const struct parent_map gcc_parent_map_50[] = { 821 { P_QUSB4PHY_2_GCC_USB4_RX1_CLK, 0 }, 822 { P_BI_TCXO, 2 }, 823 }; 824 825 static const struct clk_parent_data gcc_parent_data_50[] = { 826 { .index = DT_QUSB4PHY_2_GCC_USB4_RX1_CLK }, 827 { .index = DT_BI_TCXO }, 828 }; 829 830 static const struct parent_map gcc_parent_map_51[] = { 831 { P_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC, 0 }, 832 { P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 }, 833 }; 834 835 static const struct clk_parent_data gcc_parent_data_51[] = { 836 { .index = DT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC }, 837 { .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK }, 838 }; 839 840 static struct clk_regmap_phy_mux gcc_pcie_3a_pipe_clk_src = { 841 .reg = 0xdc088, 842 .clkr = { 843 .hw.init = &(const struct clk_init_data) { 844 .name = "gcc_pcie_3a_pipe_clk_src", 845 .parent_data = &(const struct clk_parent_data){ 846 .index = DT_PCIE_3A_PIPE_CLK, 847 }, 848 .num_parents = 1, 849 .ops = &clk_regmap_phy_mux_ops, 850 }, 851 }, 852 }; 853 854 static struct clk_regmap_phy_mux gcc_pcie_3b_pipe_clk_src = { 855 .reg = 0x941b4, 856 .clkr = { 857 .hw.init = &(const struct clk_init_data) { 858 .name = "gcc_pcie_3b_pipe_clk_src", 859 .parent_data = &(const struct clk_parent_data){ 860 .index = DT_PCIE_3B_PIPE_CLK, 861 }, 862 .num_parents = 1, 863 .ops = &clk_regmap_phy_mux_ops, 864 }, 865 }, 866 }; 867 868 static struct clk_regmap_phy_mux gcc_pcie_4_pipe_clk_src = { 869 .reg = 0x881a4, 870 .clkr = { 871 .hw.init = &(const struct clk_init_data) { 872 .name = "gcc_pcie_4_pipe_clk_src", 873 .parent_data = &(const struct clk_parent_data){ 874 .index = DT_PCIE_4_PIPE_CLK, 875 }, 876 .num_parents = 1, 877 .ops = &clk_regmap_phy_mux_ops, 878 }, 879 }, 880 }; 881 882 static struct clk_regmap_phy_mux gcc_pcie_5_pipe_clk_src = { 883 .reg = 0xc309c, 884 .clkr = { 885 .hw.init = &(const struct clk_init_data) { 886 .name = "gcc_pcie_5_pipe_clk_src", 887 .parent_data = &(const struct clk_parent_data){ 888 .index = DT_PCIE_5_PIPE_CLK, 889 }, 890 .num_parents = 1, 891 .ops = &clk_regmap_phy_mux_ops, 892 }, 893 }, 894 }; 895 896 static struct clk_regmap_phy_mux gcc_pcie_6_pipe_clk_src = { 897 .reg = 0x8a1a4, 898 .clkr = { 899 .hw.init = &(const struct clk_init_data) { 900 .name = "gcc_pcie_6_pipe_clk_src", 901 .parent_data = &(const struct clk_parent_data){ 902 .index = DT_PCIE_6_PIPE_CLK, 903 }, 904 .num_parents = 1, 905 .ops = &clk_regmap_phy_mux_ops, 906 }, 907 }, 908 }; 909 910 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = { 911 .reg = 0x7706c, 912 .shift = 0, 913 .width = 2, 914 .parent_map = gcc_parent_map_18, 915 .clkr = { 916 .hw.init = &(const struct clk_init_data) { 917 .name = "gcc_ufs_phy_rx_symbol_0_clk_src", 918 .parent_data = gcc_parent_data_18, 919 .num_parents = ARRAY_SIZE(gcc_parent_data_18), 920 .ops = &clk_regmap_mux_closest_ops, 921 }, 922 }, 923 }; 924 925 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = { 926 .reg = 0x770f0, 927 .shift = 0, 928 .width = 2, 929 .parent_map = gcc_parent_map_19, 930 .clkr = { 931 .hw.init = &(const struct clk_init_data) { 932 .name = "gcc_ufs_phy_rx_symbol_1_clk_src", 933 .parent_data = gcc_parent_data_19, 934 .num_parents = ARRAY_SIZE(gcc_parent_data_19), 935 .ops = &clk_regmap_mux_closest_ops, 936 }, 937 }, 938 }; 939 940 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = { 941 .reg = 0x7705c, 942 .shift = 0, 943 .width = 2, 944 .parent_map = gcc_parent_map_20, 945 .clkr = { 946 .hw.init = &(const struct clk_init_data) { 947 .name = "gcc_ufs_phy_tx_symbol_0_clk_src", 948 .parent_data = gcc_parent_data_20, 949 .num_parents = ARRAY_SIZE(gcc_parent_data_20), 950 .ops = &clk_regmap_mux_closest_ops, 951 }, 952 }, 953 }; 954 955 static struct clk_regmap_mux gcc_usb34_prim_phy_pipe_clk_src = { 956 .reg = 0x2b0b8, 957 .shift = 0, 958 .width = 2, 959 .parent_map = gcc_parent_map_21, 960 .clkr = { 961 .hw.init = &(const struct clk_init_data) { 962 .name = "gcc_usb34_prim_phy_pipe_clk_src", 963 .parent_data = gcc_parent_data_21, 964 .num_parents = ARRAY_SIZE(gcc_parent_data_21), 965 .ops = &clk_regmap_mux_closest_ops, 966 }, 967 }, 968 }; 969 970 static struct clk_regmap_mux gcc_usb34_sec_phy_pipe_clk_src = { 971 .reg = 0x2d0c4, 972 .shift = 0, 973 .width = 2, 974 .parent_map = gcc_parent_map_22, 975 .clkr = { 976 .hw.init = &(const struct clk_init_data) { 977 .name = "gcc_usb34_sec_phy_pipe_clk_src", 978 .parent_data = gcc_parent_data_22, 979 .num_parents = ARRAY_SIZE(gcc_parent_data_22), 980 .ops = &clk_regmap_mux_closest_ops, 981 }, 982 }, 983 }; 984 985 static struct clk_regmap_mux gcc_usb34_tert_phy_pipe_clk_src = { 986 .reg = 0xe00bc, 987 .shift = 0, 988 .width = 2, 989 .parent_map = gcc_parent_map_23, 990 .clkr = { 991 .hw.init = &(const struct clk_init_data) { 992 .name = "gcc_usb34_tert_phy_pipe_clk_src", 993 .parent_data = gcc_parent_data_23, 994 .num_parents = ARRAY_SIZE(gcc_parent_data_23), 995 .ops = &clk_regmap_mux_closest_ops, 996 }, 997 }, 998 }; 999 1000 static struct clk_regmap_mux gcc_usb3_mp_phy_pipe_0_clk_src = { 1001 .reg = 0x9a07c, 1002 .shift = 0, 1003 .width = 2, 1004 .parent_map = gcc_parent_map_24, 1005 .clkr = { 1006 .hw.init = &(const struct clk_init_data) { 1007 .name = "gcc_usb3_mp_phy_pipe_0_clk_src", 1008 .parent_data = gcc_parent_data_24, 1009 .num_parents = ARRAY_SIZE(gcc_parent_data_24), 1010 .ops = &clk_regmap_mux_closest_ops, 1011 }, 1012 }, 1013 }; 1014 1015 static struct clk_regmap_mux gcc_usb3_mp_phy_pipe_1_clk_src = { 1016 .reg = 0x9a084, 1017 .shift = 0, 1018 .width = 2, 1019 .parent_map = gcc_parent_map_25, 1020 .clkr = { 1021 .hw.init = &(const struct clk_init_data) { 1022 .name = "gcc_usb3_mp_phy_pipe_1_clk_src", 1023 .parent_data = gcc_parent_data_25, 1024 .num_parents = ARRAY_SIZE(gcc_parent_data_25), 1025 .ops = &clk_regmap_mux_closest_ops, 1026 }, 1027 }, 1028 }; 1029 1030 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 1031 .reg = 0x3f08c, 1032 .shift = 0, 1033 .width = 2, 1034 .parent_map = gcc_parent_map_26, 1035 .clkr = { 1036 .hw.init = &(const struct clk_init_data) { 1037 .name = "gcc_usb3_prim_phy_pipe_clk_src", 1038 .parent_data = gcc_parent_data_26, 1039 .num_parents = ARRAY_SIZE(gcc_parent_data_26), 1040 .ops = &clk_regmap_mux_closest_ops, 1041 }, 1042 }, 1043 }; 1044 1045 static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = { 1046 .reg = 0xe207c, 1047 .shift = 0, 1048 .width = 2, 1049 .parent_map = gcc_parent_map_27, 1050 .clkr = { 1051 .hw.init = &(const struct clk_init_data) { 1052 .name = "gcc_usb3_sec_phy_pipe_clk_src", 1053 .parent_data = gcc_parent_data_27, 1054 .num_parents = ARRAY_SIZE(gcc_parent_data_27), 1055 .ops = &clk_regmap_mux_closest_ops, 1056 }, 1057 }, 1058 }; 1059 1060 static struct clk_regmap_mux gcc_usb3_tert_phy_pipe_clk_src = { 1061 .reg = 0xe107c, 1062 .shift = 0, 1063 .width = 2, 1064 .parent_map = gcc_parent_map_28, 1065 .clkr = { 1066 .hw.init = &(const struct clk_init_data) { 1067 .name = "gcc_usb3_tert_phy_pipe_clk_src", 1068 .parent_data = gcc_parent_data_28, 1069 .num_parents = ARRAY_SIZE(gcc_parent_data_28), 1070 .ops = &clk_regmap_mux_closest_ops, 1071 }, 1072 }, 1073 }; 1074 1075 static struct clk_regmap_mux gcc_usb4_0_phy_dp0_clk_src = { 1076 .reg = 0x2b080, 1077 .shift = 0, 1078 .width = 2, 1079 .parent_map = gcc_parent_map_29, 1080 .clkr = { 1081 .hw.init = &(const struct clk_init_data) { 1082 .name = "gcc_usb4_0_phy_dp0_clk_src", 1083 .parent_data = gcc_parent_data_29, 1084 .num_parents = ARRAY_SIZE(gcc_parent_data_29), 1085 .ops = &clk_regmap_mux_closest_ops, 1086 }, 1087 }, 1088 }; 1089 1090 static struct clk_regmap_mux gcc_usb4_0_phy_dp1_clk_src = { 1091 .reg = 0x2b134, 1092 .shift = 0, 1093 .width = 2, 1094 .parent_map = gcc_parent_map_30, 1095 .clkr = { 1096 .hw.init = &(const struct clk_init_data) { 1097 .name = "gcc_usb4_0_phy_dp1_clk_src", 1098 .parent_data = gcc_parent_data_30, 1099 .num_parents = ARRAY_SIZE(gcc_parent_data_30), 1100 .ops = &clk_regmap_mux_closest_ops, 1101 }, 1102 }, 1103 }; 1104 1105 static struct clk_regmap_mux gcc_usb4_0_phy_p2rr2p_pipe_clk_src = { 1106 .reg = 0x2b0f0, 1107 .shift = 0, 1108 .width = 2, 1109 .parent_map = gcc_parent_map_31, 1110 .clkr = { 1111 .hw.init = &(const struct clk_init_data) { 1112 .name = "gcc_usb4_0_phy_p2rr2p_pipe_clk_src", 1113 .parent_data = gcc_parent_data_31, 1114 .num_parents = ARRAY_SIZE(gcc_parent_data_31), 1115 .ops = &clk_regmap_mux_closest_ops, 1116 }, 1117 }, 1118 }; 1119 1120 static struct clk_regmap_mux gcc_usb4_0_phy_pcie_pipe_mux_clk_src = { 1121 .reg = 0x2b120, 1122 .shift = 0, 1123 .width = 1, 1124 .parent_map = gcc_parent_map_33, 1125 .clkr = { 1126 .hw.init = &(const struct clk_init_data) { 1127 .name = "gcc_usb4_0_phy_pcie_pipe_mux_clk_src", 1128 .parent_data = gcc_parent_data_33, 1129 .num_parents = ARRAY_SIZE(gcc_parent_data_33), 1130 .ops = &clk_regmap_mux_closest_ops, 1131 }, 1132 }, 1133 }; 1134 1135 static struct clk_regmap_mux gcc_usb4_0_phy_rx0_clk_src = { 1136 .reg = 0x2b0c0, 1137 .shift = 0, 1138 .width = 2, 1139 .parent_map = gcc_parent_map_34, 1140 .clkr = { 1141 .hw.init = &(const struct clk_init_data) { 1142 .name = "gcc_usb4_0_phy_rx0_clk_src", 1143 .parent_data = gcc_parent_data_34, 1144 .num_parents = ARRAY_SIZE(gcc_parent_data_34), 1145 .ops = &clk_regmap_mux_closest_ops, 1146 }, 1147 }, 1148 }; 1149 1150 static struct clk_regmap_mux gcc_usb4_0_phy_rx1_clk_src = { 1151 .reg = 0x2b0d4, 1152 .shift = 0, 1153 .width = 2, 1154 .parent_map = gcc_parent_map_35, 1155 .clkr = { 1156 .hw.init = &(const struct clk_init_data) { 1157 .name = "gcc_usb4_0_phy_rx1_clk_src", 1158 .parent_data = gcc_parent_data_35, 1159 .num_parents = ARRAY_SIZE(gcc_parent_data_35), 1160 .ops = &clk_regmap_mux_closest_ops, 1161 }, 1162 }, 1163 }; 1164 1165 static struct clk_regmap_mux gcc_usb4_0_phy_sys_clk_src = { 1166 .reg = 0x2b100, 1167 .shift = 0, 1168 .width = 2, 1169 .parent_map = gcc_parent_map_36, 1170 .clkr = { 1171 .hw.init = &(const struct clk_init_data) { 1172 .name = "gcc_usb4_0_phy_sys_clk_src", 1173 .parent_data = gcc_parent_data_36, 1174 .num_parents = ARRAY_SIZE(gcc_parent_data_36), 1175 .ops = &clk_regmap_mux_closest_ops, 1176 }, 1177 }, 1178 }; 1179 1180 static struct clk_regmap_mux gcc_usb4_1_phy_dp0_clk_src = { 1181 .reg = 0x2d08c, 1182 .shift = 0, 1183 .width = 2, 1184 .parent_map = gcc_parent_map_37, 1185 .clkr = { 1186 .hw.init = &(const struct clk_init_data) { 1187 .name = "gcc_usb4_1_phy_dp0_clk_src", 1188 .parent_data = gcc_parent_data_37, 1189 .num_parents = ARRAY_SIZE(gcc_parent_data_37), 1190 .ops = &clk_regmap_mux_closest_ops, 1191 }, 1192 }, 1193 }; 1194 1195 static struct clk_regmap_mux gcc_usb4_1_phy_dp1_clk_src = { 1196 .reg = 0x2d154, 1197 .shift = 0, 1198 .width = 2, 1199 .parent_map = gcc_parent_map_38, 1200 .clkr = { 1201 .hw.init = &(const struct clk_init_data) { 1202 .name = "gcc_usb4_1_phy_dp1_clk_src", 1203 .parent_data = gcc_parent_data_38, 1204 .num_parents = ARRAY_SIZE(gcc_parent_data_38), 1205 .ops = &clk_regmap_mux_closest_ops, 1206 }, 1207 }, 1208 }; 1209 1210 static struct clk_regmap_mux gcc_usb4_1_phy_p2rr2p_pipe_clk_src = { 1211 .reg = 0x2d114, 1212 .shift = 0, 1213 .width = 2, 1214 .parent_map = gcc_parent_map_39, 1215 .clkr = { 1216 .hw.init = &(const struct clk_init_data) { 1217 .name = "gcc_usb4_1_phy_p2rr2p_pipe_clk_src", 1218 .parent_data = gcc_parent_data_39, 1219 .num_parents = ARRAY_SIZE(gcc_parent_data_39), 1220 .ops = &clk_regmap_mux_closest_ops, 1221 }, 1222 }, 1223 }; 1224 1225 static struct clk_regmap_mux gcc_usb4_1_phy_pcie_pipe_mux_clk_src = { 1226 .reg = 0x2d140, 1227 .shift = 0, 1228 .width = 1, 1229 .parent_map = gcc_parent_map_40, 1230 .clkr = { 1231 .hw.init = &(const struct clk_init_data) { 1232 .name = "gcc_usb4_1_phy_pcie_pipe_mux_clk_src", 1233 .parent_data = gcc_parent_data_40, 1234 .num_parents = ARRAY_SIZE(gcc_parent_data_40), 1235 .ops = &clk_regmap_mux_closest_ops, 1236 }, 1237 }, 1238 }; 1239 1240 static struct clk_regmap_mux gcc_usb4_1_phy_rx0_clk_src = { 1241 .reg = 0x2d0e4, 1242 .shift = 0, 1243 .width = 2, 1244 .parent_map = gcc_parent_map_42, 1245 .clkr = { 1246 .hw.init = &(const struct clk_init_data) { 1247 .name = "gcc_usb4_1_phy_rx0_clk_src", 1248 .parent_data = gcc_parent_data_42, 1249 .num_parents = ARRAY_SIZE(gcc_parent_data_42), 1250 .ops = &clk_regmap_mux_closest_ops, 1251 }, 1252 }, 1253 }; 1254 1255 static struct clk_regmap_mux gcc_usb4_1_phy_rx1_clk_src = { 1256 .reg = 0x2d0f8, 1257 .shift = 0, 1258 .width = 2, 1259 .parent_map = gcc_parent_map_43, 1260 .clkr = { 1261 .hw.init = &(const struct clk_init_data) { 1262 .name = "gcc_usb4_1_phy_rx1_clk_src", 1263 .parent_data = gcc_parent_data_43, 1264 .num_parents = ARRAY_SIZE(gcc_parent_data_43), 1265 .ops = &clk_regmap_mux_closest_ops, 1266 }, 1267 }, 1268 }; 1269 1270 static struct clk_regmap_mux gcc_usb4_1_phy_sys_clk_src = { 1271 .reg = 0x2d124, 1272 .shift = 0, 1273 .width = 2, 1274 .parent_map = gcc_parent_map_44, 1275 .clkr = { 1276 .hw.init = &(const struct clk_init_data) { 1277 .name = "gcc_usb4_1_phy_sys_clk_src", 1278 .parent_data = gcc_parent_data_44, 1279 .num_parents = ARRAY_SIZE(gcc_parent_data_44), 1280 .ops = &clk_regmap_mux_closest_ops, 1281 }, 1282 }, 1283 }; 1284 1285 static struct clk_regmap_mux gcc_usb4_2_phy_dp0_clk_src = { 1286 .reg = 0xe0084, 1287 .shift = 0, 1288 .width = 2, 1289 .parent_map = gcc_parent_map_45, 1290 .clkr = { 1291 .hw.init = &(const struct clk_init_data) { 1292 .name = "gcc_usb4_2_phy_dp0_clk_src", 1293 .parent_data = gcc_parent_data_45, 1294 .num_parents = ARRAY_SIZE(gcc_parent_data_45), 1295 .ops = &clk_regmap_mux_closest_ops, 1296 }, 1297 }, 1298 }; 1299 1300 static struct clk_regmap_mux gcc_usb4_2_phy_dp1_clk_src = { 1301 .reg = 0xe013c, 1302 .shift = 0, 1303 .width = 2, 1304 .parent_map = gcc_parent_map_46, 1305 .clkr = { 1306 .hw.init = &(const struct clk_init_data) { 1307 .name = "gcc_usb4_2_phy_dp1_clk_src", 1308 .parent_data = gcc_parent_data_46, 1309 .num_parents = ARRAY_SIZE(gcc_parent_data_46), 1310 .ops = &clk_regmap_mux_closest_ops, 1311 }, 1312 }, 1313 }; 1314 1315 static struct clk_regmap_mux gcc_usb4_2_phy_p2rr2p_pipe_clk_src = { 1316 .reg = 0xe00f4, 1317 .shift = 0, 1318 .width = 2, 1319 .parent_map = gcc_parent_map_47, 1320 .clkr = { 1321 .hw.init = &(const struct clk_init_data) { 1322 .name = "gcc_usb4_2_phy_p2rr2p_pipe_clk_src", 1323 .parent_data = gcc_parent_data_47, 1324 .num_parents = ARRAY_SIZE(gcc_parent_data_47), 1325 .ops = &clk_regmap_mux_closest_ops, 1326 }, 1327 }, 1328 }; 1329 1330 static struct clk_regmap_mux gcc_usb4_2_phy_pcie_pipe_mux_clk_src = { 1331 .reg = 0xe0124, 1332 .shift = 0, 1333 .width = 1, 1334 .parent_map = gcc_parent_map_48, 1335 .clkr = { 1336 .hw.init = &(const struct clk_init_data) { 1337 .name = "gcc_usb4_2_phy_pcie_pipe_mux_clk_src", 1338 .parent_data = gcc_parent_data_48, 1339 .num_parents = ARRAY_SIZE(gcc_parent_data_48), 1340 .ops = &clk_regmap_mux_closest_ops, 1341 }, 1342 }, 1343 }; 1344 1345 static struct clk_regmap_mux gcc_usb4_2_phy_rx0_clk_src = { 1346 .reg = 0xe00c4, 1347 .shift = 0, 1348 .width = 2, 1349 .parent_map = gcc_parent_map_49, 1350 .clkr = { 1351 .hw.init = &(const struct clk_init_data) { 1352 .name = "gcc_usb4_2_phy_rx0_clk_src", 1353 .parent_data = gcc_parent_data_49, 1354 .num_parents = ARRAY_SIZE(gcc_parent_data_49), 1355 .ops = &clk_regmap_mux_closest_ops, 1356 }, 1357 }, 1358 }; 1359 1360 static struct clk_regmap_mux gcc_usb4_2_phy_rx1_clk_src = { 1361 .reg = 0xe00d8, 1362 .shift = 0, 1363 .width = 2, 1364 .parent_map = gcc_parent_map_50, 1365 .clkr = { 1366 .hw.init = &(const struct clk_init_data) { 1367 .name = "gcc_usb4_2_phy_rx1_clk_src", 1368 .parent_data = gcc_parent_data_50, 1369 .num_parents = ARRAY_SIZE(gcc_parent_data_50), 1370 .ops = &clk_regmap_mux_closest_ops, 1371 }, 1372 }, 1373 }; 1374 1375 static struct clk_regmap_mux gcc_usb4_2_phy_sys_clk_src = { 1376 .reg = 0xe0104, 1377 .shift = 0, 1378 .width = 2, 1379 .parent_map = gcc_parent_map_51, 1380 .clkr = { 1381 .hw.init = &(const struct clk_init_data) { 1382 .name = "gcc_usb4_2_phy_sys_clk_src", 1383 .parent_data = gcc_parent_data_51, 1384 .num_parents = ARRAY_SIZE(gcc_parent_data_51), 1385 .ops = &clk_regmap_mux_closest_ops, 1386 }, 1387 }, 1388 }; 1389 1390 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 1391 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 1392 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 1393 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1394 { } 1395 }; 1396 1397 static struct clk_rcg2 gcc_gp1_clk_src = { 1398 .cmd_rcgr = 0x64004, 1399 .mnd_width = 16, 1400 .hid_width = 5, 1401 .parent_map = gcc_parent_map_4, 1402 .freq_tbl = ftbl_gcc_gp1_clk_src, 1403 .clkr.hw.init = &(const struct clk_init_data) { 1404 .name = "gcc_gp1_clk_src", 1405 .parent_data = gcc_parent_data_4, 1406 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1407 .flags = CLK_SET_RATE_PARENT, 1408 .ops = &clk_rcg2_shared_no_init_park_ops, 1409 }, 1410 }; 1411 1412 static struct clk_rcg2 gcc_gp2_clk_src = { 1413 .cmd_rcgr = 0x92004, 1414 .mnd_width = 16, 1415 .hid_width = 5, 1416 .parent_map = gcc_parent_map_4, 1417 .freq_tbl = ftbl_gcc_gp1_clk_src, 1418 .clkr.hw.init = &(const struct clk_init_data) { 1419 .name = "gcc_gp2_clk_src", 1420 .parent_data = gcc_parent_data_4, 1421 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1422 .flags = CLK_SET_RATE_PARENT, 1423 .ops = &clk_rcg2_shared_no_init_park_ops, 1424 }, 1425 }; 1426 1427 static struct clk_rcg2 gcc_gp3_clk_src = { 1428 .cmd_rcgr = 0x93004, 1429 .mnd_width = 16, 1430 .hid_width = 5, 1431 .parent_map = gcc_parent_map_4, 1432 .freq_tbl = ftbl_gcc_gp1_clk_src, 1433 .clkr.hw.init = &(const struct clk_init_data) { 1434 .name = "gcc_gp3_clk_src", 1435 .parent_data = gcc_parent_data_4, 1436 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1437 .flags = CLK_SET_RATE_PARENT, 1438 .ops = &clk_rcg2_shared_no_init_park_ops, 1439 }, 1440 }; 1441 1442 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 1443 F(19200000, P_BI_TCXO, 1, 0, 0), 1444 { } 1445 }; 1446 1447 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 1448 .cmd_rcgr = 0xc8168, 1449 .mnd_width = 16, 1450 .hid_width = 5, 1451 .parent_map = gcc_parent_map_2, 1452 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1453 .clkr.hw.init = &(const struct clk_init_data) { 1454 .name = "gcc_pcie_0_aux_clk_src", 1455 .parent_data = gcc_parent_data_2, 1456 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1457 .flags = CLK_SET_RATE_PARENT, 1458 .ops = &clk_rcg2_shared_no_init_park_ops, 1459 }, 1460 }; 1461 1462 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 1463 F(19200000, P_BI_TCXO, 1, 0, 0), 1464 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1465 { } 1466 }; 1467 1468 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 1469 .cmd_rcgr = 0xc803c, 1470 .mnd_width = 0, 1471 .hid_width = 5, 1472 .parent_map = gcc_parent_map_0, 1473 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1474 .clkr.hw.init = &(const struct clk_init_data) { 1475 .name = "gcc_pcie_0_phy_rchng_clk_src", 1476 .parent_data = gcc_parent_data_0, 1477 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1478 .flags = CLK_SET_RATE_PARENT, 1479 .ops = &clk_rcg2_shared_no_init_park_ops, 1480 }, 1481 }; 1482 1483 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 1484 .cmd_rcgr = 0x2e168, 1485 .mnd_width = 16, 1486 .hid_width = 5, 1487 .parent_map = gcc_parent_map_2, 1488 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1489 .clkr.hw.init = &(const struct clk_init_data) { 1490 .name = "gcc_pcie_1_aux_clk_src", 1491 .parent_data = gcc_parent_data_2, 1492 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1493 .flags = CLK_SET_RATE_PARENT, 1494 .ops = &clk_rcg2_shared_no_init_park_ops, 1495 }, 1496 }; 1497 1498 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { 1499 .cmd_rcgr = 0x2e03c, 1500 .mnd_width = 0, 1501 .hid_width = 5, 1502 .parent_map = gcc_parent_map_0, 1503 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1504 .clkr.hw.init = &(const struct clk_init_data) { 1505 .name = "gcc_pcie_1_phy_rchng_clk_src", 1506 .parent_data = gcc_parent_data_0, 1507 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1508 .flags = CLK_SET_RATE_PARENT, 1509 .ops = &clk_rcg2_shared_no_init_park_ops, 1510 }, 1511 }; 1512 1513 static struct clk_rcg2 gcc_pcie_2_aux_clk_src = { 1514 .cmd_rcgr = 0xc0168, 1515 .mnd_width = 16, 1516 .hid_width = 5, 1517 .parent_map = gcc_parent_map_2, 1518 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1519 .clkr.hw.init = &(const struct clk_init_data) { 1520 .name = "gcc_pcie_2_aux_clk_src", 1521 .parent_data = gcc_parent_data_2, 1522 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1523 .flags = CLK_SET_RATE_PARENT, 1524 .ops = &clk_rcg2_shared_no_init_park_ops, 1525 }, 1526 }; 1527 1528 static struct clk_rcg2 gcc_pcie_2_phy_rchng_clk_src = { 1529 .cmd_rcgr = 0xc003c, 1530 .mnd_width = 0, 1531 .hid_width = 5, 1532 .parent_map = gcc_parent_map_0, 1533 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1534 .clkr.hw.init = &(const struct clk_init_data) { 1535 .name = "gcc_pcie_2_phy_rchng_clk_src", 1536 .parent_data = gcc_parent_data_0, 1537 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1538 .flags = CLK_SET_RATE_PARENT, 1539 .ops = &clk_rcg2_shared_no_init_park_ops, 1540 }, 1541 }; 1542 1543 static struct clk_rcg2 gcc_pcie_3a_aux_clk_src = { 1544 .cmd_rcgr = 0xdc08c, 1545 .mnd_width = 16, 1546 .hid_width = 5, 1547 .parent_map = gcc_parent_map_2, 1548 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1549 .clkr.hw.init = &(const struct clk_init_data) { 1550 .name = "gcc_pcie_3a_aux_clk_src", 1551 .parent_data = gcc_parent_data_2, 1552 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1553 .flags = CLK_SET_RATE_PARENT, 1554 .ops = &clk_rcg2_shared_no_init_park_ops, 1555 }, 1556 }; 1557 1558 static struct clk_rcg2 gcc_pcie_3a_phy_rchng_clk_src = { 1559 .cmd_rcgr = 0xdc070, 1560 .mnd_width = 0, 1561 .hid_width = 5, 1562 .parent_map = gcc_parent_map_0, 1563 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1564 .clkr.hw.init = &(const struct clk_init_data) { 1565 .name = "gcc_pcie_3a_phy_rchng_clk_src", 1566 .parent_data = gcc_parent_data_0, 1567 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1568 .flags = CLK_SET_RATE_PARENT, 1569 .ops = &clk_rcg2_shared_no_init_park_ops, 1570 }, 1571 }; 1572 1573 static struct clk_rcg2 gcc_pcie_3b_aux_clk_src = { 1574 .cmd_rcgr = 0x941b8, 1575 .mnd_width = 16, 1576 .hid_width = 5, 1577 .parent_map = gcc_parent_map_2, 1578 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1579 .clkr.hw.init = &(const struct clk_init_data) { 1580 .name = "gcc_pcie_3b_aux_clk_src", 1581 .parent_data = gcc_parent_data_2, 1582 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1583 .flags = CLK_SET_RATE_PARENT, 1584 .ops = &clk_rcg2_shared_no_init_park_ops, 1585 }, 1586 }; 1587 1588 static struct clk_rcg2 gcc_pcie_3b_phy_rchng_clk_src = { 1589 .cmd_rcgr = 0x94088, 1590 .mnd_width = 0, 1591 .hid_width = 5, 1592 .parent_map = gcc_parent_map_0, 1593 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1594 .clkr.hw.init = &(const struct clk_init_data) { 1595 .name = "gcc_pcie_3b_phy_rchng_clk_src", 1596 .parent_data = gcc_parent_data_0, 1597 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1598 .flags = CLK_SET_RATE_PARENT, 1599 .ops = &clk_rcg2_shared_no_init_park_ops, 1600 }, 1601 }; 1602 1603 static struct clk_rcg2 gcc_pcie_4_aux_clk_src = { 1604 .cmd_rcgr = 0x881a8, 1605 .mnd_width = 16, 1606 .hid_width = 5, 1607 .parent_map = gcc_parent_map_2, 1608 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1609 .clkr.hw.init = &(const struct clk_init_data) { 1610 .name = "gcc_pcie_4_aux_clk_src", 1611 .parent_data = gcc_parent_data_2, 1612 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1613 .flags = CLK_SET_RATE_PARENT, 1614 .ops = &clk_rcg2_shared_no_init_park_ops, 1615 }, 1616 }; 1617 1618 static struct clk_rcg2 gcc_pcie_4_phy_rchng_clk_src = { 1619 .cmd_rcgr = 0x88078, 1620 .mnd_width = 0, 1621 .hid_width = 5, 1622 .parent_map = gcc_parent_map_0, 1623 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1624 .clkr.hw.init = &(const struct clk_init_data) { 1625 .name = "gcc_pcie_4_phy_rchng_clk_src", 1626 .parent_data = gcc_parent_data_0, 1627 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1628 .flags = CLK_SET_RATE_PARENT, 1629 .ops = &clk_rcg2_shared_no_init_park_ops, 1630 }, 1631 }; 1632 1633 static struct clk_rcg2 gcc_pcie_5_aux_clk_src = { 1634 .cmd_rcgr = 0xc30a0, 1635 .mnd_width = 16, 1636 .hid_width = 5, 1637 .parent_map = gcc_parent_map_2, 1638 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1639 .clkr.hw.init = &(const struct clk_init_data) { 1640 .name = "gcc_pcie_5_aux_clk_src", 1641 .parent_data = gcc_parent_data_2, 1642 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1643 .flags = CLK_SET_RATE_PARENT, 1644 .ops = &clk_rcg2_shared_no_init_park_ops, 1645 }, 1646 }; 1647 1648 static struct clk_rcg2 gcc_pcie_5_phy_rchng_clk_src = { 1649 .cmd_rcgr = 0xc3084, 1650 .mnd_width = 0, 1651 .hid_width = 5, 1652 .parent_map = gcc_parent_map_0, 1653 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1654 .clkr.hw.init = &(const struct clk_init_data) { 1655 .name = "gcc_pcie_5_phy_rchng_clk_src", 1656 .parent_data = gcc_parent_data_0, 1657 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1658 .flags = CLK_SET_RATE_PARENT, 1659 .ops = &clk_rcg2_shared_no_init_park_ops, 1660 }, 1661 }; 1662 1663 static struct clk_rcg2 gcc_pcie_6_aux_clk_src = { 1664 .cmd_rcgr = 0x8a1a8, 1665 .mnd_width = 16, 1666 .hid_width = 5, 1667 .parent_map = gcc_parent_map_2, 1668 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1669 .clkr.hw.init = &(const struct clk_init_data) { 1670 .name = "gcc_pcie_6_aux_clk_src", 1671 .parent_data = gcc_parent_data_2, 1672 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1673 .flags = CLK_SET_RATE_PARENT, 1674 .ops = &clk_rcg2_shared_no_init_park_ops, 1675 }, 1676 }; 1677 1678 static struct clk_rcg2 gcc_pcie_6_phy_rchng_clk_src = { 1679 .cmd_rcgr = 0x8a078, 1680 .mnd_width = 0, 1681 .hid_width = 5, 1682 .parent_map = gcc_parent_map_0, 1683 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 1684 .clkr.hw.init = &(const struct clk_init_data) { 1685 .name = "gcc_pcie_6_phy_rchng_clk_src", 1686 .parent_data = gcc_parent_data_0, 1687 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1688 .flags = CLK_SET_RATE_PARENT, 1689 .ops = &clk_rcg2_shared_no_init_park_ops, 1690 }, 1691 }; 1692 1693 static struct clk_rcg2 gcc_pcie_phy_3a_aux_clk_src = { 1694 .cmd_rcgr = 0x6c01c, 1695 .mnd_width = 16, 1696 .hid_width = 5, 1697 .parent_map = gcc_parent_map_2, 1698 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1699 .clkr.hw.init = &(const struct clk_init_data) { 1700 .name = "gcc_pcie_phy_3a_aux_clk_src", 1701 .parent_data = gcc_parent_data_2, 1702 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1703 .flags = CLK_SET_RATE_PARENT, 1704 .ops = &clk_rcg2_shared_no_init_park_ops, 1705 }, 1706 }; 1707 1708 static struct clk_rcg2 gcc_pcie_phy_3b_aux_clk_src = { 1709 .cmd_rcgr = 0x7501c, 1710 .mnd_width = 16, 1711 .hid_width = 5, 1712 .parent_map = gcc_parent_map_2, 1713 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1714 .clkr.hw.init = &(const struct clk_init_data) { 1715 .name = "gcc_pcie_phy_3b_aux_clk_src", 1716 .parent_data = gcc_parent_data_2, 1717 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1718 .flags = CLK_SET_RATE_PARENT, 1719 .ops = &clk_rcg2_shared_no_init_park_ops, 1720 }, 1721 }; 1722 1723 static struct clk_rcg2 gcc_pcie_phy_4_aux_clk_src = { 1724 .cmd_rcgr = 0xd3018, 1725 .mnd_width = 16, 1726 .hid_width = 5, 1727 .parent_map = gcc_parent_map_2, 1728 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1729 .clkr.hw.init = &(const struct clk_init_data) { 1730 .name = "gcc_pcie_phy_4_aux_clk_src", 1731 .parent_data = gcc_parent_data_2, 1732 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1733 .flags = CLK_SET_RATE_PARENT, 1734 .ops = &clk_rcg2_shared_no_init_park_ops, 1735 }, 1736 }; 1737 1738 static struct clk_rcg2 gcc_pcie_phy_5_aux_clk_src = { 1739 .cmd_rcgr = 0xd2018, 1740 .mnd_width = 16, 1741 .hid_width = 5, 1742 .parent_map = gcc_parent_map_2, 1743 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1744 .clkr.hw.init = &(const struct clk_init_data) { 1745 .name = "gcc_pcie_phy_5_aux_clk_src", 1746 .parent_data = gcc_parent_data_2, 1747 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1748 .flags = CLK_SET_RATE_PARENT, 1749 .ops = &clk_rcg2_shared_no_init_park_ops, 1750 }, 1751 }; 1752 1753 static struct clk_rcg2 gcc_pcie_phy_6_aux_clk_src = { 1754 .cmd_rcgr = 0xd4018, 1755 .mnd_width = 16, 1756 .hid_width = 5, 1757 .parent_map = gcc_parent_map_2, 1758 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1759 .clkr.hw.init = &(const struct clk_init_data) { 1760 .name = "gcc_pcie_phy_6_aux_clk_src", 1761 .parent_data = gcc_parent_data_2, 1762 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 1763 .flags = CLK_SET_RATE_PARENT, 1764 .ops = &clk_rcg2_shared_no_init_park_ops, 1765 }, 1766 }; 1767 1768 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 1769 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 1770 { } 1771 }; 1772 1773 static struct clk_rcg2 gcc_pdm2_clk_src = { 1774 .cmd_rcgr = 0x33010, 1775 .mnd_width = 0, 1776 .hid_width = 5, 1777 .parent_map = gcc_parent_map_0, 1778 .freq_tbl = ftbl_gcc_pdm2_clk_src, 1779 .clkr.hw.init = &(const struct clk_init_data) { 1780 .name = "gcc_pdm2_clk_src", 1781 .parent_data = gcc_parent_data_0, 1782 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1783 .flags = CLK_SET_RATE_PARENT, 1784 .ops = &clk_rcg2_shared_no_init_park_ops, 1785 }, 1786 }; 1787 1788 static const struct freq_tbl ftbl_gcc_qupv3_oob_qspi_s0_clk_src[] = { 1789 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 1790 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 1791 F(19200000, P_BI_TCXO, 1, 0, 0), 1792 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 1793 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 1794 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 1795 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 1796 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1797 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 1798 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 1799 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 1800 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 1801 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 1802 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1803 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 1804 { } 1805 }; 1806 1807 static struct clk_init_data gcc_qupv3_oob_qspi_s0_clk_src_init = { 1808 .name = "gcc_qupv3_oob_qspi_s0_clk_src", 1809 .parent_data = gcc_parent_data_3, 1810 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1811 .flags = CLK_SET_RATE_PARENT, 1812 .ops = &clk_rcg2_shared_no_init_park_ops, 1813 }; 1814 1815 static struct clk_rcg2 gcc_qupv3_oob_qspi_s0_clk_src = { 1816 .cmd_rcgr = 0xe7044, 1817 .mnd_width = 16, 1818 .hid_width = 5, 1819 .parent_map = gcc_parent_map_3, 1820 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s0_clk_src, 1821 .clkr.hw.init = &gcc_qupv3_oob_qspi_s0_clk_src_init, 1822 }; 1823 1824 static const struct freq_tbl ftbl_gcc_qupv3_oob_qspi_s1_clk_src[] = { 1825 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 1826 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 1827 F(19200000, P_BI_TCXO, 1, 0, 0), 1828 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 1829 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 1830 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 1831 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 1832 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1833 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 1834 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 1835 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 1836 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 1837 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 1838 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1839 { } 1840 }; 1841 1842 static struct clk_init_data gcc_qupv3_oob_qspi_s1_clk_src_init = { 1843 .name = "gcc_qupv3_oob_qspi_s1_clk_src", 1844 .parent_data = gcc_parent_data_1, 1845 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1846 .flags = CLK_SET_RATE_PARENT, 1847 .ops = &clk_rcg2_shared_no_init_park_ops, 1848 }; 1849 1850 static struct clk_rcg2 gcc_qupv3_oob_qspi_s1_clk_src = { 1851 .cmd_rcgr = 0xe7170, 1852 .mnd_width = 16, 1853 .hid_width = 5, 1854 .parent_map = gcc_parent_map_1, 1855 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src, 1856 .clkr.hw.init = &gcc_qupv3_oob_qspi_s1_clk_src_init, 1857 }; 1858 1859 static struct clk_init_data gcc_qupv3_wrap0_qspi_s2_clk_src_init = { 1860 .name = "gcc_qupv3_wrap0_qspi_s2_clk_src", 1861 .parent_data = gcc_parent_data_1, 1862 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1863 .flags = CLK_SET_RATE_PARENT, 1864 .ops = &clk_rcg2_shared_no_init_park_ops, 1865 }; 1866 1867 static struct clk_rcg2 gcc_qupv3_wrap0_qspi_s2_clk_src = { 1868 .cmd_rcgr = 0x287a0, 1869 .mnd_width = 16, 1870 .hid_width = 5, 1871 .parent_map = gcc_parent_map_1, 1872 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src, 1873 .clkr.hw.init = &gcc_qupv3_wrap0_qspi_s2_clk_src_init, 1874 }; 1875 1876 static struct clk_init_data gcc_qupv3_wrap0_qspi_s3_clk_src_init = { 1877 .name = "gcc_qupv3_wrap0_qspi_s3_clk_src", 1878 .parent_data = gcc_parent_data_1, 1879 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1880 .flags = CLK_SET_RATE_PARENT, 1881 .ops = &clk_rcg2_shared_no_init_park_ops, 1882 }; 1883 1884 static struct clk_rcg2 gcc_qupv3_wrap0_qspi_s3_clk_src = { 1885 .cmd_rcgr = 0x288d0, 1886 .mnd_width = 16, 1887 .hid_width = 5, 1888 .parent_map = gcc_parent_map_1, 1889 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src, 1890 .clkr.hw.init = &gcc_qupv3_wrap0_qspi_s3_clk_src_init, 1891 }; 1892 1893 static struct clk_init_data gcc_qupv3_wrap0_qspi_s6_clk_src_init = { 1894 .name = "gcc_qupv3_wrap0_qspi_s6_clk_src", 1895 .parent_data = gcc_parent_data_1, 1896 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1897 .flags = CLK_SET_RATE_PARENT, 1898 .ops = &clk_rcg2_shared_no_init_park_ops, 1899 }; 1900 1901 static struct clk_rcg2 gcc_qupv3_wrap0_qspi_s6_clk_src = { 1902 .cmd_rcgr = 0x2866c, 1903 .mnd_width = 16, 1904 .hid_width = 5, 1905 .parent_map = gcc_parent_map_1, 1906 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src, 1907 .clkr.hw.init = &gcc_qupv3_wrap0_qspi_s6_clk_src_init, 1908 }; 1909 1910 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 1911 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 1912 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 1913 F(19200000, P_BI_TCXO, 1, 0, 0), 1914 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 1915 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 1916 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 1917 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 1918 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1919 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 1920 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 1921 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 1922 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 1923 { } 1924 }; 1925 1926 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 1927 .name = "gcc_qupv3_wrap0_s0_clk_src", 1928 .parent_data = gcc_parent_data_1, 1929 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1930 .flags = CLK_SET_RATE_PARENT, 1931 .ops = &clk_rcg2_shared_no_init_park_ops, 1932 }; 1933 1934 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 1935 .cmd_rcgr = 0x28014, 1936 .mnd_width = 16, 1937 .hid_width = 5, 1938 .parent_map = gcc_parent_map_1, 1939 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1940 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 1941 }; 1942 1943 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 1944 .name = "gcc_qupv3_wrap0_s1_clk_src", 1945 .parent_data = gcc_parent_data_1, 1946 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1947 .flags = CLK_SET_RATE_PARENT, 1948 .ops = &clk_rcg2_shared_no_init_park_ops, 1949 }; 1950 1951 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 1952 .cmd_rcgr = 0x28150, 1953 .mnd_width = 16, 1954 .hid_width = 5, 1955 .parent_map = gcc_parent_map_1, 1956 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 1957 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 1958 }; 1959 1960 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s4_clk_src[] = { 1961 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 1962 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 1963 F(19200000, P_BI_TCXO, 1, 0, 0), 1964 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 1965 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 1966 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 1967 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 1968 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1969 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 1970 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 1971 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 1972 { } 1973 }; 1974 1975 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 1976 .name = "gcc_qupv3_wrap0_s4_clk_src", 1977 .parent_data = gcc_parent_data_1, 1978 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1979 .flags = CLK_SET_RATE_PARENT, 1980 .ops = &clk_rcg2_shared_no_init_park_ops, 1981 }; 1982 1983 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 1984 .cmd_rcgr = 0x282b4, 1985 .mnd_width = 16, 1986 .hid_width = 5, 1987 .parent_map = gcc_parent_map_1, 1988 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 1989 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 1990 }; 1991 1992 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 1993 .name = "gcc_qupv3_wrap0_s5_clk_src", 1994 .parent_data = gcc_parent_data_1, 1995 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1996 .flags = CLK_SET_RATE_PARENT, 1997 .ops = &clk_rcg2_shared_no_init_park_ops, 1998 }; 1999 2000 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 2001 .cmd_rcgr = 0x283f0, 2002 .mnd_width = 16, 2003 .hid_width = 5, 2004 .parent_map = gcc_parent_map_1, 2005 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 2006 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 2007 }; 2008 2009 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 2010 .name = "gcc_qupv3_wrap0_s7_clk_src", 2011 .parent_data = gcc_parent_data_1, 2012 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2013 .flags = CLK_SET_RATE_PARENT, 2014 .ops = &clk_rcg2_shared_no_init_park_ops, 2015 }; 2016 2017 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 2018 .cmd_rcgr = 0x28540, 2019 .mnd_width = 16, 2020 .hid_width = 5, 2021 .parent_map = gcc_parent_map_1, 2022 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 2023 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 2024 }; 2025 2026 static struct clk_init_data gcc_qupv3_wrap1_qspi_s2_clk_src_init = { 2027 .name = "gcc_qupv3_wrap1_qspi_s2_clk_src", 2028 .parent_data = gcc_parent_data_1, 2029 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2030 .flags = CLK_SET_RATE_PARENT, 2031 .ops = &clk_rcg2_shared_no_init_park_ops, 2032 }; 2033 2034 static struct clk_rcg2 gcc_qupv3_wrap1_qspi_s2_clk_src = { 2035 .cmd_rcgr = 0xb37a0, 2036 .mnd_width = 16, 2037 .hid_width = 5, 2038 .parent_map = gcc_parent_map_1, 2039 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src, 2040 .clkr.hw.init = &gcc_qupv3_wrap1_qspi_s2_clk_src_init, 2041 }; 2042 2043 static struct clk_init_data gcc_qupv3_wrap1_qspi_s3_clk_src_init = { 2044 .name = "gcc_qupv3_wrap1_qspi_s3_clk_src", 2045 .parent_data = gcc_parent_data_1, 2046 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2047 .flags = CLK_SET_RATE_PARENT, 2048 .ops = &clk_rcg2_shared_no_init_park_ops, 2049 }; 2050 2051 static struct clk_rcg2 gcc_qupv3_wrap1_qspi_s3_clk_src = { 2052 .cmd_rcgr = 0xb38d0, 2053 .mnd_width = 16, 2054 .hid_width = 5, 2055 .parent_map = gcc_parent_map_1, 2056 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src, 2057 .clkr.hw.init = &gcc_qupv3_wrap1_qspi_s3_clk_src_init, 2058 }; 2059 2060 static struct clk_init_data gcc_qupv3_wrap1_qspi_s6_clk_src_init = { 2061 .name = "gcc_qupv3_wrap1_qspi_s6_clk_src", 2062 .parent_data = gcc_parent_data_1, 2063 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2064 .flags = CLK_SET_RATE_PARENT, 2065 .ops = &clk_rcg2_shared_no_init_park_ops, 2066 }; 2067 2068 static struct clk_rcg2 gcc_qupv3_wrap1_qspi_s6_clk_src = { 2069 .cmd_rcgr = 0xb366c, 2070 .mnd_width = 16, 2071 .hid_width = 5, 2072 .parent_map = gcc_parent_map_1, 2073 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src, 2074 .clkr.hw.init = &gcc_qupv3_wrap1_qspi_s6_clk_src_init, 2075 }; 2076 2077 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 2078 .name = "gcc_qupv3_wrap1_s0_clk_src", 2079 .parent_data = gcc_parent_data_1, 2080 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2081 .flags = CLK_SET_RATE_PARENT, 2082 .ops = &clk_rcg2_shared_no_init_park_ops, 2083 }; 2084 2085 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 2086 .cmd_rcgr = 0xb3014, 2087 .mnd_width = 16, 2088 .hid_width = 5, 2089 .parent_map = gcc_parent_map_1, 2090 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 2091 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 2092 }; 2093 2094 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 2095 .name = "gcc_qupv3_wrap1_s1_clk_src", 2096 .parent_data = gcc_parent_data_1, 2097 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2098 .flags = CLK_SET_RATE_PARENT, 2099 .ops = &clk_rcg2_shared_no_init_park_ops, 2100 }; 2101 2102 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 2103 .cmd_rcgr = 0xb3150, 2104 .mnd_width = 16, 2105 .hid_width = 5, 2106 .parent_map = gcc_parent_map_1, 2107 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 2108 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 2109 }; 2110 2111 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 2112 .name = "gcc_qupv3_wrap1_s4_clk_src", 2113 .parent_data = gcc_parent_data_1, 2114 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2115 .flags = CLK_SET_RATE_PARENT, 2116 .ops = &clk_rcg2_shared_no_init_park_ops, 2117 }; 2118 2119 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 2120 .cmd_rcgr = 0xb32b4, 2121 .mnd_width = 16, 2122 .hid_width = 5, 2123 .parent_map = gcc_parent_map_1, 2124 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 2125 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 2126 }; 2127 2128 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 2129 .name = "gcc_qupv3_wrap1_s5_clk_src", 2130 .parent_data = gcc_parent_data_1, 2131 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2132 .flags = CLK_SET_RATE_PARENT, 2133 .ops = &clk_rcg2_shared_no_init_park_ops, 2134 }; 2135 2136 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 2137 .cmd_rcgr = 0xb33f0, 2138 .mnd_width = 16, 2139 .hid_width = 5, 2140 .parent_map = gcc_parent_map_1, 2141 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 2142 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 2143 }; 2144 2145 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 2146 .name = "gcc_qupv3_wrap1_s7_clk_src", 2147 .parent_data = gcc_parent_data_1, 2148 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2149 .flags = CLK_SET_RATE_PARENT, 2150 .ops = &clk_rcg2_shared_no_init_park_ops, 2151 }; 2152 2153 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 2154 .cmd_rcgr = 0xb3540, 2155 .mnd_width = 16, 2156 .hid_width = 5, 2157 .parent_map = gcc_parent_map_1, 2158 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 2159 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 2160 }; 2161 2162 static struct clk_init_data gcc_qupv3_wrap2_qspi_s2_clk_src_init = { 2163 .name = "gcc_qupv3_wrap2_qspi_s2_clk_src", 2164 .parent_data = gcc_parent_data_1, 2165 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2166 .flags = CLK_SET_RATE_PARENT, 2167 .ops = &clk_rcg2_shared_no_init_park_ops, 2168 }; 2169 2170 static struct clk_rcg2 gcc_qupv3_wrap2_qspi_s2_clk_src = { 2171 .cmd_rcgr = 0xb47a0, 2172 .mnd_width = 16, 2173 .hid_width = 5, 2174 .parent_map = gcc_parent_map_1, 2175 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src, 2176 .clkr.hw.init = &gcc_qupv3_wrap2_qspi_s2_clk_src_init, 2177 }; 2178 2179 static struct clk_init_data gcc_qupv3_wrap2_qspi_s3_clk_src_init = { 2180 .name = "gcc_qupv3_wrap2_qspi_s3_clk_src", 2181 .parent_data = gcc_parent_data_1, 2182 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2183 .flags = CLK_SET_RATE_PARENT, 2184 .ops = &clk_rcg2_shared_no_init_park_ops, 2185 }; 2186 2187 static struct clk_rcg2 gcc_qupv3_wrap2_qspi_s3_clk_src = { 2188 .cmd_rcgr = 0xb48d0, 2189 .mnd_width = 16, 2190 .hid_width = 5, 2191 .parent_map = gcc_parent_map_1, 2192 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src, 2193 .clkr.hw.init = &gcc_qupv3_wrap2_qspi_s3_clk_src_init, 2194 }; 2195 2196 static struct clk_init_data gcc_qupv3_wrap2_qspi_s6_clk_src_init = { 2197 .name = "gcc_qupv3_wrap2_qspi_s6_clk_src", 2198 .parent_data = gcc_parent_data_1, 2199 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2200 .flags = CLK_SET_RATE_PARENT, 2201 .ops = &clk_rcg2_shared_no_init_park_ops, 2202 }; 2203 2204 static struct clk_rcg2 gcc_qupv3_wrap2_qspi_s6_clk_src = { 2205 .cmd_rcgr = 0xb466c, 2206 .mnd_width = 16, 2207 .hid_width = 5, 2208 .parent_map = gcc_parent_map_1, 2209 .freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src, 2210 .clkr.hw.init = &gcc_qupv3_wrap2_qspi_s6_clk_src_init, 2211 }; 2212 2213 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 2214 .name = "gcc_qupv3_wrap2_s0_clk_src", 2215 .parent_data = gcc_parent_data_1, 2216 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2217 .flags = CLK_SET_RATE_PARENT, 2218 .ops = &clk_rcg2_shared_no_init_park_ops, 2219 }; 2220 2221 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 2222 .cmd_rcgr = 0xb4014, 2223 .mnd_width = 16, 2224 .hid_width = 5, 2225 .parent_map = gcc_parent_map_1, 2226 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 2227 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 2228 }; 2229 2230 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 2231 .name = "gcc_qupv3_wrap2_s1_clk_src", 2232 .parent_data = gcc_parent_data_1, 2233 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2234 .flags = CLK_SET_RATE_PARENT, 2235 .ops = &clk_rcg2_shared_no_init_park_ops, 2236 }; 2237 2238 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 2239 .cmd_rcgr = 0xb4150, 2240 .mnd_width = 16, 2241 .hid_width = 5, 2242 .parent_map = gcc_parent_map_1, 2243 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 2244 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 2245 }; 2246 2247 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 2248 .name = "gcc_qupv3_wrap2_s4_clk_src", 2249 .parent_data = gcc_parent_data_1, 2250 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2251 .flags = CLK_SET_RATE_PARENT, 2252 .ops = &clk_rcg2_shared_no_init_park_ops, 2253 }; 2254 2255 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 2256 .cmd_rcgr = 0xb42b4, 2257 .mnd_width = 16, 2258 .hid_width = 5, 2259 .parent_map = gcc_parent_map_1, 2260 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 2261 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 2262 }; 2263 2264 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { 2265 .name = "gcc_qupv3_wrap2_s5_clk_src", 2266 .parent_data = gcc_parent_data_1, 2267 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2268 .flags = CLK_SET_RATE_PARENT, 2269 .ops = &clk_rcg2_shared_no_init_park_ops, 2270 }; 2271 2272 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { 2273 .cmd_rcgr = 0xb43f0, 2274 .mnd_width = 16, 2275 .hid_width = 5, 2276 .parent_map = gcc_parent_map_1, 2277 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 2278 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, 2279 }; 2280 2281 static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = { 2282 .name = "gcc_qupv3_wrap2_s7_clk_src", 2283 .parent_data = gcc_parent_data_1, 2284 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2285 .flags = CLK_SET_RATE_PARENT, 2286 .ops = &clk_rcg2_shared_no_init_park_ops, 2287 }; 2288 2289 static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = { 2290 .cmd_rcgr = 0xb4540, 2291 .mnd_width = 16, 2292 .hid_width = 5, 2293 .parent_map = gcc_parent_map_1, 2294 .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, 2295 .clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init, 2296 }; 2297 2298 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 2299 F(400000, P_BI_TCXO, 12, 1, 4), 2300 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 2301 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 2302 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 2303 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), 2304 { } 2305 }; 2306 2307 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 2308 .cmd_rcgr = 0xb001c, 2309 .mnd_width = 8, 2310 .hid_width = 5, 2311 .parent_map = gcc_parent_map_17, 2312 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 2313 .clkr.hw.init = &(const struct clk_init_data) { 2314 .name = "gcc_sdcc2_apps_clk_src", 2315 .parent_data = gcc_parent_data_17, 2316 .num_parents = ARRAY_SIZE(gcc_parent_data_17), 2317 .flags = CLK_SET_RATE_PARENT, 2318 .ops = &clk_rcg2_shared_floor_ops, 2319 }, 2320 }; 2321 2322 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 2323 F(400000, P_BI_TCXO, 12, 1, 4), 2324 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 2325 F(75000000, P_GCC_GPLL0_OUT_MAIN, 8, 0, 0), 2326 { } 2327 }; 2328 2329 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 2330 .cmd_rcgr = 0xdf01c, 2331 .mnd_width = 8, 2332 .hid_width = 5, 2333 .parent_map = gcc_parent_map_3, 2334 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 2335 .clkr.hw.init = &(const struct clk_init_data) { 2336 .name = "gcc_sdcc4_apps_clk_src", 2337 .parent_data = gcc_parent_data_3, 2338 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 2339 .flags = CLK_SET_RATE_PARENT, 2340 .ops = &clk_rcg2_shared_floor_ops, 2341 }, 2342 }; 2343 2344 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 2345 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 2346 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 2347 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), 2348 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 2349 { } 2350 }; 2351 2352 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 2353 .cmd_rcgr = 0x77038, 2354 .mnd_width = 8, 2355 .hid_width = 5, 2356 .parent_map = gcc_parent_map_6, 2357 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 2358 .clkr.hw.init = &(const struct clk_init_data) { 2359 .name = "gcc_ufs_phy_axi_clk_src", 2360 .parent_data = gcc_parent_data_6, 2361 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 2362 .flags = CLK_SET_RATE_PARENT, 2363 .ops = &clk_rcg2_shared_no_init_park_ops, 2364 }, 2365 }; 2366 2367 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 2368 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 2369 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), 2370 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 2371 { } 2372 }; 2373 2374 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 2375 .cmd_rcgr = 0x77090, 2376 .mnd_width = 0, 2377 .hid_width = 5, 2378 .parent_map = gcc_parent_map_6, 2379 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 2380 .clkr.hw.init = &(const struct clk_init_data) { 2381 .name = "gcc_ufs_phy_ice_core_clk_src", 2382 .parent_data = gcc_parent_data_6, 2383 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 2384 .flags = CLK_SET_RATE_PARENT, 2385 .ops = &clk_rcg2_shared_no_init_park_ops, 2386 }, 2387 }; 2388 2389 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 2390 .cmd_rcgr = 0x770c4, 2391 .mnd_width = 0, 2392 .hid_width = 5, 2393 .parent_map = gcc_parent_map_5, 2394 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2395 .clkr.hw.init = &(const struct clk_init_data) { 2396 .name = "gcc_ufs_phy_phy_aux_clk_src", 2397 .parent_data = gcc_parent_data_5, 2398 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 2399 .flags = CLK_SET_RATE_PARENT, 2400 .ops = &clk_rcg2_shared_no_init_park_ops, 2401 }, 2402 }; 2403 2404 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 2405 .cmd_rcgr = 0x770a8, 2406 .mnd_width = 0, 2407 .hid_width = 5, 2408 .parent_map = gcc_parent_map_6, 2409 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 2410 .clkr.hw.init = &(const struct clk_init_data) { 2411 .name = "gcc_ufs_phy_unipro_core_clk_src", 2412 .parent_data = gcc_parent_data_6, 2413 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 2414 .flags = CLK_SET_RATE_PARENT, 2415 .ops = &clk_rcg2_shared_no_init_park_ops, 2416 }, 2417 }; 2418 2419 static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = { 2420 F(60000000, P_GCC_GPLL14_OUT_MAIN, 10, 0, 0), 2421 F(120000000, P_GCC_GPLL14_OUT_MAIN, 5, 0, 0), 2422 { } 2423 }; 2424 2425 static struct clk_rcg2 gcc_usb20_master_clk_src = { 2426 .cmd_rcgr = 0xbc030, 2427 .mnd_width = 8, 2428 .hid_width = 5, 2429 .parent_map = gcc_parent_map_7, 2430 .freq_tbl = ftbl_gcc_usb20_master_clk_src, 2431 .clkr.hw.init = &(const struct clk_init_data) { 2432 .name = "gcc_usb20_master_clk_src", 2433 .parent_data = gcc_parent_data_7, 2434 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 2435 .flags = CLK_SET_RATE_PARENT, 2436 .ops = &clk_rcg2_shared_no_init_park_ops, 2437 }, 2438 }; 2439 2440 static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = { 2441 .cmd_rcgr = 0xbc048, 2442 .mnd_width = 0, 2443 .hid_width = 5, 2444 .parent_map = gcc_parent_map_7, 2445 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2446 .clkr.hw.init = &(const struct clk_init_data) { 2447 .name = "gcc_usb20_mock_utmi_clk_src", 2448 .parent_data = gcc_parent_data_7, 2449 .num_parents = ARRAY_SIZE(gcc_parent_data_7), 2450 .flags = CLK_SET_RATE_PARENT, 2451 .ops = &clk_rcg2_shared_no_init_park_ops, 2452 }, 2453 }; 2454 2455 static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = { 2456 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), 2457 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 2458 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 2459 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 2460 { } 2461 }; 2462 2463 static struct clk_rcg2 gcc_usb30_mp_master_clk_src = { 2464 .cmd_rcgr = 0x9a03c, 2465 .mnd_width = 8, 2466 .hid_width = 5, 2467 .parent_map = gcc_parent_map_0, 2468 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 2469 .clkr.hw.init = &(const struct clk_init_data) { 2470 .name = "gcc_usb30_mp_master_clk_src", 2471 .parent_data = gcc_parent_data_0, 2472 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2473 .flags = CLK_SET_RATE_PARENT, 2474 .ops = &clk_rcg2_shared_no_init_park_ops, 2475 }, 2476 }; 2477 2478 static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = { 2479 .cmd_rcgr = 0x9a054, 2480 .mnd_width = 0, 2481 .hid_width = 5, 2482 .parent_map = gcc_parent_map_0, 2483 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2484 .clkr.hw.init = &(const struct clk_init_data) { 2485 .name = "gcc_usb30_mp_mock_utmi_clk_src", 2486 .parent_data = gcc_parent_data_0, 2487 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2488 .flags = CLK_SET_RATE_PARENT, 2489 .ops = &clk_rcg2_shared_no_init_park_ops, 2490 }, 2491 }; 2492 2493 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 2494 .cmd_rcgr = 0x3f04c, 2495 .mnd_width = 8, 2496 .hid_width = 5, 2497 .parent_map = gcc_parent_map_0, 2498 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 2499 .clkr.hw.init = &(const struct clk_init_data) { 2500 .name = "gcc_usb30_prim_master_clk_src", 2501 .parent_data = gcc_parent_data_0, 2502 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2503 .flags = CLK_SET_RATE_PARENT, 2504 .ops = &clk_rcg2_shared_no_init_park_ops, 2505 }, 2506 }; 2507 2508 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 2509 .cmd_rcgr = 0x3f064, 2510 .mnd_width = 0, 2511 .hid_width = 5, 2512 .parent_map = gcc_parent_map_0, 2513 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2514 .clkr.hw.init = &(const struct clk_init_data) { 2515 .name = "gcc_usb30_prim_mock_utmi_clk_src", 2516 .parent_data = gcc_parent_data_0, 2517 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2518 .flags = CLK_SET_RATE_PARENT, 2519 .ops = &clk_rcg2_shared_no_init_park_ops, 2520 }, 2521 }; 2522 2523 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { 2524 .cmd_rcgr = 0xe203c, 2525 .mnd_width = 8, 2526 .hid_width = 5, 2527 .parent_map = gcc_parent_map_0, 2528 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 2529 .clkr.hw.init = &(const struct clk_init_data) { 2530 .name = "gcc_usb30_sec_master_clk_src", 2531 .parent_data = gcc_parent_data_0, 2532 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2533 .flags = CLK_SET_RATE_PARENT, 2534 .ops = &clk_rcg2_shared_no_init_park_ops, 2535 }, 2536 }; 2537 2538 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { 2539 .cmd_rcgr = 0xe2054, 2540 .mnd_width = 0, 2541 .hid_width = 5, 2542 .parent_map = gcc_parent_map_0, 2543 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2544 .clkr.hw.init = &(const struct clk_init_data) { 2545 .name = "gcc_usb30_sec_mock_utmi_clk_src", 2546 .parent_data = gcc_parent_data_0, 2547 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2548 .flags = CLK_SET_RATE_PARENT, 2549 .ops = &clk_rcg2_shared_no_init_park_ops, 2550 }, 2551 }; 2552 2553 static struct clk_rcg2 gcc_usb30_tert_master_clk_src = { 2554 .cmd_rcgr = 0xe103c, 2555 .mnd_width = 8, 2556 .hid_width = 5, 2557 .parent_map = gcc_parent_map_0, 2558 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, 2559 .clkr.hw.init = &(const struct clk_init_data) { 2560 .name = "gcc_usb30_tert_master_clk_src", 2561 .parent_data = gcc_parent_data_0, 2562 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2563 .flags = CLK_SET_RATE_PARENT, 2564 .ops = &clk_rcg2_shared_no_init_park_ops, 2565 }, 2566 }; 2567 2568 static struct clk_rcg2 gcc_usb30_tert_mock_utmi_clk_src = { 2569 .cmd_rcgr = 0xe1054, 2570 .mnd_width = 0, 2571 .hid_width = 5, 2572 .parent_map = gcc_parent_map_0, 2573 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2574 .clkr.hw.init = &(const struct clk_init_data) { 2575 .name = "gcc_usb30_tert_mock_utmi_clk_src", 2576 .parent_data = gcc_parent_data_0, 2577 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 2578 .flags = CLK_SET_RATE_PARENT, 2579 .ops = &clk_rcg2_shared_no_init_park_ops, 2580 }, 2581 }; 2582 2583 static struct clk_rcg2 gcc_usb3_mp_phy_aux_clk_src = { 2584 .cmd_rcgr = 0x9a088, 2585 .mnd_width = 0, 2586 .hid_width = 5, 2587 .parent_map = gcc_parent_map_8, 2588 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2589 .clkr.hw.init = &(const struct clk_init_data) { 2590 .name = "gcc_usb3_mp_phy_aux_clk_src", 2591 .parent_data = gcc_parent_data_8, 2592 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 2593 .flags = CLK_SET_RATE_PARENT, 2594 .ops = &clk_rcg2_shared_no_init_park_ops, 2595 }, 2596 }; 2597 2598 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 2599 .cmd_rcgr = 0x3f090, 2600 .mnd_width = 0, 2601 .hid_width = 5, 2602 .parent_map = gcc_parent_map_8, 2603 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2604 .clkr.hw.init = &(const struct clk_init_data) { 2605 .name = "gcc_usb3_prim_phy_aux_clk_src", 2606 .parent_data = gcc_parent_data_8, 2607 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 2608 .flags = CLK_SET_RATE_PARENT, 2609 .ops = &clk_rcg2_shared_no_init_park_ops, 2610 }, 2611 }; 2612 2613 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { 2614 .cmd_rcgr = 0xe2080, 2615 .mnd_width = 0, 2616 .hid_width = 5, 2617 .parent_map = gcc_parent_map_8, 2618 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2619 .clkr.hw.init = &(const struct clk_init_data) { 2620 .name = "gcc_usb3_sec_phy_aux_clk_src", 2621 .parent_data = gcc_parent_data_8, 2622 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 2623 .flags = CLK_SET_RATE_PARENT, 2624 .ops = &clk_rcg2_shared_no_init_park_ops, 2625 }, 2626 }; 2627 2628 static struct clk_rcg2 gcc_usb3_tert_phy_aux_clk_src = { 2629 .cmd_rcgr = 0xe1080, 2630 .mnd_width = 0, 2631 .hid_width = 5, 2632 .parent_map = gcc_parent_map_8, 2633 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2634 .clkr.hw.init = &(const struct clk_init_data) { 2635 .name = "gcc_usb3_tert_phy_aux_clk_src", 2636 .parent_data = gcc_parent_data_8, 2637 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 2638 .flags = CLK_SET_RATE_PARENT, 2639 .ops = &clk_rcg2_shared_no_init_park_ops, 2640 }, 2641 }; 2642 2643 static const struct freq_tbl ftbl_gcc_usb4_0_master_clk_src[] = { 2644 F(177666750, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0), 2645 F(355333500, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0), 2646 { } 2647 }; 2648 2649 static struct clk_rcg2 gcc_usb4_0_master_clk_src = { 2650 .cmd_rcgr = 0x2b02c, 2651 .mnd_width = 8, 2652 .hid_width = 5, 2653 .parent_map = gcc_parent_map_9, 2654 .freq_tbl = ftbl_gcc_usb4_0_master_clk_src, 2655 .clkr.hw.init = &(const struct clk_init_data) { 2656 .name = "gcc_usb4_0_master_clk_src", 2657 .parent_data = gcc_parent_data_9, 2658 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 2659 .flags = CLK_SET_RATE_PARENT, 2660 .ops = &clk_rcg2_shared_no_init_park_ops, 2661 }, 2662 }; 2663 2664 static const struct freq_tbl ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src[] = { 2665 F(19200000, P_BI_TCXO, 1, 0, 0), 2666 F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0), 2667 F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0), 2668 { } 2669 }; 2670 2671 static struct clk_rcg2 gcc_usb4_0_phy_pcie_pipe_clk_src = { 2672 .cmd_rcgr = 0x2b104, 2673 .mnd_width = 0, 2674 .hid_width = 5, 2675 .parent_map = gcc_parent_map_32, 2676 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src, 2677 .clkr.hw.init = &(const struct clk_init_data) { 2678 .name = "gcc_usb4_0_phy_pcie_pipe_clk_src", 2679 .parent_data = gcc_parent_data_32, 2680 .num_parents = ARRAY_SIZE(gcc_parent_data_32), 2681 .flags = CLK_SET_RATE_PARENT, 2682 .ops = &clk_rcg2_shared_no_init_park_ops, 2683 }, 2684 }; 2685 2686 static struct clk_rcg2 gcc_usb4_0_sb_if_clk_src = { 2687 .cmd_rcgr = 0x2b0a0, 2688 .mnd_width = 0, 2689 .hid_width = 5, 2690 .parent_map = gcc_parent_map_5, 2691 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2692 .clkr.hw.init = &(const struct clk_init_data) { 2693 .name = "gcc_usb4_0_sb_if_clk_src", 2694 .parent_data = gcc_parent_data_5, 2695 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 2696 .flags = CLK_SET_RATE_PARENT, 2697 .ops = &clk_rcg2_shared_no_init_park_ops, 2698 }, 2699 }; 2700 2701 static struct clk_rcg2 gcc_usb4_0_tmu_clk_src = { 2702 .cmd_rcgr = 0x2b084, 2703 .mnd_width = 0, 2704 .hid_width = 5, 2705 .parent_map = gcc_parent_map_10, 2706 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src, 2707 .clkr.hw.init = &(const struct clk_init_data) { 2708 .name = "gcc_usb4_0_tmu_clk_src", 2709 .parent_data = gcc_parent_data_10, 2710 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 2711 .flags = CLK_SET_RATE_PARENT, 2712 .ops = &clk_rcg2_shared_no_init_park_ops, 2713 }, 2714 }; 2715 2716 static struct clk_rcg2 gcc_usb4_1_master_clk_src = { 2717 .cmd_rcgr = 0x2d02c, 2718 .mnd_width = 8, 2719 .hid_width = 5, 2720 .parent_map = gcc_parent_map_9, 2721 .freq_tbl = ftbl_gcc_usb4_0_master_clk_src, 2722 .clkr.hw.init = &(const struct clk_init_data) { 2723 .name = "gcc_usb4_1_master_clk_src", 2724 .parent_data = gcc_parent_data_9, 2725 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 2726 .flags = CLK_SET_RATE_PARENT, 2727 .ops = &clk_rcg2_shared_no_init_park_ops, 2728 }, 2729 }; 2730 2731 static const struct freq_tbl ftbl_gcc_usb4_1_phy_pcie_pipe_clk_src[] = { 2732 F(19200000, P_BI_TCXO, 1, 0, 0), 2733 F(177666750, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0), 2734 F(355333500, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0), 2735 { } 2736 }; 2737 2738 static struct clk_rcg2 gcc_usb4_1_phy_pcie_pipe_clk_src = { 2739 .cmd_rcgr = 0x2d128, 2740 .mnd_width = 0, 2741 .hid_width = 5, 2742 .parent_map = gcc_parent_map_11, 2743 .freq_tbl = ftbl_gcc_usb4_1_phy_pcie_pipe_clk_src, 2744 .clkr.hw.init = &(const struct clk_init_data) { 2745 .name = "gcc_usb4_1_phy_pcie_pipe_clk_src", 2746 .parent_data = gcc_parent_data_11, 2747 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 2748 .flags = CLK_SET_RATE_PARENT, 2749 .ops = &clk_rcg2_shared_no_init_park_ops, 2750 }, 2751 }; 2752 2753 static const struct freq_tbl ftbl_gcc_usb4_1_phy_pll_pipe_clk_src[] = { 2754 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 2755 F(311000000, P_GCC_GPLL5_OUT_MAIN, 3, 0, 0), 2756 { } 2757 }; 2758 2759 static struct clk_rcg2 gcc_usb4_1_phy_pll_pipe_clk_src = { 2760 .cmd_rcgr = 0x2d0c8, 2761 .mnd_width = 0, 2762 .hid_width = 5, 2763 .parent_map = gcc_parent_map_41, 2764 .freq_tbl = ftbl_gcc_usb4_1_phy_pll_pipe_clk_src, 2765 .clkr.hw.init = &(const struct clk_init_data) { 2766 .name = "gcc_usb4_1_phy_pll_pipe_clk_src", 2767 .parent_data = gcc_parent_data_41, 2768 .num_parents = ARRAY_SIZE(gcc_parent_data_41), 2769 .flags = CLK_SET_RATE_PARENT, 2770 .ops = &clk_rcg2_shared_no_init_park_ops, 2771 }, 2772 }; 2773 2774 static struct clk_rcg2 gcc_usb4_1_sb_if_clk_src = { 2775 .cmd_rcgr = 0x2d0ac, 2776 .mnd_width = 0, 2777 .hid_width = 5, 2778 .parent_map = gcc_parent_map_5, 2779 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2780 .clkr.hw.init = &(const struct clk_init_data) { 2781 .name = "gcc_usb4_1_sb_if_clk_src", 2782 .parent_data = gcc_parent_data_5, 2783 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 2784 .flags = CLK_SET_RATE_PARENT, 2785 .ops = &clk_rcg2_shared_no_init_park_ops, 2786 }, 2787 }; 2788 2789 static struct clk_rcg2 gcc_usb4_1_tmu_clk_src = { 2790 .cmd_rcgr = 0x2d090, 2791 .mnd_width = 0, 2792 .hid_width = 5, 2793 .parent_map = gcc_parent_map_10, 2794 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src, 2795 .clkr.hw.init = &(const struct clk_init_data) { 2796 .name = "gcc_usb4_1_tmu_clk_src", 2797 .parent_data = gcc_parent_data_10, 2798 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 2799 .flags = CLK_SET_RATE_PARENT, 2800 .ops = &clk_rcg2_shared_no_init_park_ops, 2801 }, 2802 }; 2803 2804 static struct clk_rcg2 gcc_usb4_2_master_clk_src = { 2805 .cmd_rcgr = 0xe002c, 2806 .mnd_width = 8, 2807 .hid_width = 5, 2808 .parent_map = gcc_parent_map_9, 2809 .freq_tbl = ftbl_gcc_usb4_0_master_clk_src, 2810 .clkr.hw.init = &(const struct clk_init_data) { 2811 .name = "gcc_usb4_2_master_clk_src", 2812 .parent_data = gcc_parent_data_9, 2813 .num_parents = ARRAY_SIZE(gcc_parent_data_9), 2814 .flags = CLK_SET_RATE_PARENT, 2815 .ops = &clk_rcg2_shared_no_init_park_ops, 2816 }, 2817 }; 2818 2819 static struct clk_rcg2 gcc_usb4_2_phy_pcie_pipe_clk_src = { 2820 .cmd_rcgr = 0xe0108, 2821 .mnd_width = 0, 2822 .hid_width = 5, 2823 .parent_map = gcc_parent_map_11, 2824 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src, 2825 .clkr.hw.init = &(const struct clk_init_data) { 2826 .name = "gcc_usb4_2_phy_pcie_pipe_clk_src", 2827 .parent_data = gcc_parent_data_11, 2828 .num_parents = ARRAY_SIZE(gcc_parent_data_11), 2829 .flags = CLK_SET_RATE_PARENT, 2830 .ops = &clk_rcg2_shared_no_init_park_ops, 2831 }, 2832 }; 2833 2834 static struct clk_rcg2 gcc_usb4_2_sb_if_clk_src = { 2835 .cmd_rcgr = 0xe00a4, 2836 .mnd_width = 0, 2837 .hid_width = 5, 2838 .parent_map = gcc_parent_map_5, 2839 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 2840 .clkr.hw.init = &(const struct clk_init_data) { 2841 .name = "gcc_usb4_2_sb_if_clk_src", 2842 .parent_data = gcc_parent_data_5, 2843 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 2844 .flags = CLK_SET_RATE_PARENT, 2845 .ops = &clk_rcg2_shared_no_init_park_ops, 2846 }, 2847 }; 2848 2849 static struct clk_rcg2 gcc_usb4_2_tmu_clk_src = { 2850 .cmd_rcgr = 0xe0088, 2851 .mnd_width = 0, 2852 .hid_width = 5, 2853 .parent_map = gcc_parent_map_10, 2854 .freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src, 2855 .clkr.hw.init = &(const struct clk_init_data) { 2856 .name = "gcc_usb4_2_tmu_clk_src", 2857 .parent_data = gcc_parent_data_10, 2858 .num_parents = ARRAY_SIZE(gcc_parent_data_10), 2859 .flags = CLK_SET_RATE_PARENT, 2860 .ops = &clk_rcg2_shared_no_init_park_ops, 2861 }, 2862 }; 2863 2864 static struct clk_regmap_div gcc_pcie_3b_pipe_div_clk_src = { 2865 .reg = 0x94070, 2866 .shift = 0, 2867 .width = 4, 2868 .clkr.hw.init = &(const struct clk_init_data) { 2869 .name = "gcc_pcie_3b_pipe_div_clk_src", 2870 .parent_hws = (const struct clk_hw*[]) { 2871 &gcc_pcie_3b_pipe_clk_src.clkr.hw, 2872 }, 2873 .num_parents = 1, 2874 .flags = CLK_SET_RATE_PARENT, 2875 .ops = &clk_regmap_div_ro_ops, 2876 }, 2877 }; 2878 2879 static struct clk_regmap_div gcc_pcie_4_pipe_div_clk_src = { 2880 .reg = 0x88060, 2881 .shift = 0, 2882 .width = 4, 2883 .clkr.hw.init = &(const struct clk_init_data) { 2884 .name = "gcc_pcie_4_pipe_div_clk_src", 2885 .parent_hws = (const struct clk_hw*[]) { 2886 &gcc_pcie_4_pipe_clk_src.clkr.hw, 2887 }, 2888 .num_parents = 1, 2889 .flags = CLK_SET_RATE_PARENT, 2890 .ops = &clk_regmap_div_ro_ops, 2891 }, 2892 }; 2893 2894 static struct clk_regmap_div gcc_pcie_5_pipe_div_clk_src = { 2895 .reg = 0xc306c, 2896 .shift = 0, 2897 .width = 4, 2898 .clkr.hw.init = &(const struct clk_init_data) { 2899 .name = "gcc_pcie_5_pipe_div_clk_src", 2900 .parent_hws = (const struct clk_hw*[]) { 2901 &gcc_pcie_5_pipe_clk_src.clkr.hw, 2902 }, 2903 .num_parents = 1, 2904 .flags = CLK_SET_RATE_PARENT, 2905 .ops = &clk_regmap_div_ro_ops, 2906 }, 2907 }; 2908 2909 static struct clk_regmap_div gcc_pcie_6_pipe_div_clk_src = { 2910 .reg = 0x8a060, 2911 .shift = 0, 2912 .width = 4, 2913 .clkr.hw.init = &(const struct clk_init_data) { 2914 .name = "gcc_pcie_6_pipe_div_clk_src", 2915 .parent_hws = (const struct clk_hw*[]) { 2916 &gcc_pcie_6_pipe_clk_src.clkr.hw, 2917 }, 2918 .num_parents = 1, 2919 .flags = CLK_SET_RATE_PARENT, 2920 .ops = &clk_regmap_div_ro_ops, 2921 }, 2922 }; 2923 2924 static struct clk_regmap_div gcc_qupv3_oob_s0_clk_src = { 2925 .reg = 0xe7024, 2926 .shift = 0, 2927 .width = 4, 2928 .clkr.hw.init = &(const struct clk_init_data) { 2929 .name = "gcc_qupv3_oob_s0_clk_src", 2930 .parent_hws = (const struct clk_hw*[]) { 2931 &gcc_qupv3_oob_qspi_s0_clk_src.clkr.hw, 2932 }, 2933 .num_parents = 1, 2934 .flags = CLK_SET_RATE_PARENT, 2935 .ops = &clk_regmap_div_ro_ops, 2936 }, 2937 }; 2938 2939 static struct clk_regmap_div gcc_qupv3_oob_s1_clk_src = { 2940 .reg = 0xe7038, 2941 .shift = 0, 2942 .width = 4, 2943 .clkr.hw.init = &(const struct clk_init_data) { 2944 .name = "gcc_qupv3_oob_s1_clk_src", 2945 .parent_hws = (const struct clk_hw*[]) { 2946 &gcc_qupv3_oob_qspi_s1_clk_src.clkr.hw, 2947 }, 2948 .num_parents = 1, 2949 .flags = CLK_SET_RATE_PARENT, 2950 .ops = &clk_regmap_div_ro_ops, 2951 }, 2952 }; 2953 2954 static struct clk_regmap_div gcc_qupv3_wrap0_s2_clk_src = { 2955 .reg = 0x2828c, 2956 .shift = 0, 2957 .width = 4, 2958 .clkr.hw.init = &(const struct clk_init_data) { 2959 .name = "gcc_qupv3_wrap0_s2_clk_src", 2960 .parent_hws = (const struct clk_hw*[]) { 2961 &gcc_qupv3_wrap0_qspi_s2_clk_src.clkr.hw, 2962 }, 2963 .num_parents = 1, 2964 .flags = CLK_SET_RATE_PARENT, 2965 .ops = &clk_regmap_div_ro_ops, 2966 }, 2967 }; 2968 2969 static struct clk_regmap_div gcc_qupv3_wrap0_s3_clk_src = { 2970 .reg = 0x282a0, 2971 .shift = 0, 2972 .width = 4, 2973 .clkr.hw.init = &(const struct clk_init_data) { 2974 .name = "gcc_qupv3_wrap0_s3_clk_src", 2975 .parent_hws = (const struct clk_hw*[]) { 2976 &gcc_qupv3_wrap0_qspi_s3_clk_src.clkr.hw, 2977 }, 2978 .num_parents = 1, 2979 .flags = CLK_SET_RATE_PARENT, 2980 .ops = &clk_regmap_div_ro_ops, 2981 }, 2982 }; 2983 2984 static struct clk_regmap_div gcc_qupv3_wrap0_s6_clk_src = { 2985 .reg = 0x2852c, 2986 .shift = 0, 2987 .width = 4, 2988 .clkr.hw.init = &(const struct clk_init_data) { 2989 .name = "gcc_qupv3_wrap0_s6_clk_src", 2990 .parent_hws = (const struct clk_hw*[]) { 2991 &gcc_qupv3_wrap0_qspi_s6_clk_src.clkr.hw, 2992 }, 2993 .num_parents = 1, 2994 .flags = CLK_SET_RATE_PARENT, 2995 .ops = &clk_regmap_div_ro_ops, 2996 }, 2997 }; 2998 2999 static struct clk_regmap_div gcc_qupv3_wrap1_s2_clk_src = { 3000 .reg = 0xb328c, 3001 .shift = 0, 3002 .width = 4, 3003 .clkr.hw.init = &(const struct clk_init_data) { 3004 .name = "gcc_qupv3_wrap1_s2_clk_src", 3005 .parent_hws = (const struct clk_hw*[]) { 3006 &gcc_qupv3_wrap1_qspi_s2_clk_src.clkr.hw, 3007 }, 3008 .num_parents = 1, 3009 .flags = CLK_SET_RATE_PARENT, 3010 .ops = &clk_regmap_div_ro_ops, 3011 }, 3012 }; 3013 3014 static struct clk_regmap_div gcc_qupv3_wrap1_s3_clk_src = { 3015 .reg = 0xb32a0, 3016 .shift = 0, 3017 .width = 4, 3018 .clkr.hw.init = &(const struct clk_init_data) { 3019 .name = "gcc_qupv3_wrap1_s3_clk_src", 3020 .parent_hws = (const struct clk_hw*[]) { 3021 &gcc_qupv3_wrap1_qspi_s3_clk_src.clkr.hw, 3022 }, 3023 .num_parents = 1, 3024 .flags = CLK_SET_RATE_PARENT, 3025 .ops = &clk_regmap_div_ro_ops, 3026 }, 3027 }; 3028 3029 static struct clk_regmap_div gcc_qupv3_wrap1_s6_clk_src = { 3030 .reg = 0xb352c, 3031 .shift = 0, 3032 .width = 4, 3033 .clkr.hw.init = &(const struct clk_init_data) { 3034 .name = "gcc_qupv3_wrap1_s6_clk_src", 3035 .parent_hws = (const struct clk_hw*[]) { 3036 &gcc_qupv3_wrap1_qspi_s6_clk_src.clkr.hw, 3037 }, 3038 .num_parents = 1, 3039 .flags = CLK_SET_RATE_PARENT, 3040 .ops = &clk_regmap_div_ro_ops, 3041 }, 3042 }; 3043 3044 static struct clk_regmap_div gcc_qupv3_wrap2_s2_clk_src = { 3045 .reg = 0xb428c, 3046 .shift = 0, 3047 .width = 4, 3048 .clkr.hw.init = &(const struct clk_init_data) { 3049 .name = "gcc_qupv3_wrap2_s2_clk_src", 3050 .parent_hws = (const struct clk_hw*[]) { 3051 &gcc_qupv3_wrap2_qspi_s2_clk_src.clkr.hw, 3052 }, 3053 .num_parents = 1, 3054 .flags = CLK_SET_RATE_PARENT, 3055 .ops = &clk_regmap_div_ro_ops, 3056 }, 3057 }; 3058 3059 static struct clk_regmap_div gcc_qupv3_wrap2_s3_clk_src = { 3060 .reg = 0xb42a0, 3061 .shift = 0, 3062 .width = 4, 3063 .clkr.hw.init = &(const struct clk_init_data) { 3064 .name = "gcc_qupv3_wrap2_s3_clk_src", 3065 .parent_hws = (const struct clk_hw*[]) { 3066 &gcc_qupv3_wrap2_qspi_s3_clk_src.clkr.hw, 3067 }, 3068 .num_parents = 1, 3069 .flags = CLK_SET_RATE_PARENT, 3070 .ops = &clk_regmap_div_ro_ops, 3071 }, 3072 }; 3073 3074 static struct clk_regmap_div gcc_qupv3_wrap2_s6_clk_src = { 3075 .reg = 0xb452c, 3076 .shift = 0, 3077 .width = 4, 3078 .clkr.hw.init = &(const struct clk_init_data) { 3079 .name = "gcc_qupv3_wrap2_s6_clk_src", 3080 .parent_hws = (const struct clk_hw*[]) { 3081 &gcc_qupv3_wrap2_qspi_s6_clk_src.clkr.hw, 3082 }, 3083 .num_parents = 1, 3084 .flags = CLK_SET_RATE_PARENT, 3085 .ops = &clk_regmap_div_ro_ops, 3086 }, 3087 }; 3088 3089 static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src = { 3090 .reg = 0xbc174, 3091 .shift = 0, 3092 .width = 4, 3093 .clkr.hw.init = &(const struct clk_init_data) { 3094 .name = "gcc_usb20_mock_utmi_postdiv_clk_src", 3095 .parent_hws = (const struct clk_hw*[]) { 3096 &gcc_usb20_mock_utmi_clk_src.clkr.hw, 3097 }, 3098 .num_parents = 1, 3099 .flags = CLK_SET_RATE_PARENT, 3100 .ops = &clk_regmap_div_ro_ops, 3101 }, 3102 }; 3103 3104 static struct clk_regmap_div gcc_usb30_mp_mock_utmi_postdiv_clk_src = { 3105 .reg = 0x9a06c, 3106 .shift = 0, 3107 .width = 4, 3108 .clkr.hw.init = &(const struct clk_init_data) { 3109 .name = "gcc_usb30_mp_mock_utmi_postdiv_clk_src", 3110 .parent_hws = (const struct clk_hw*[]) { 3111 &gcc_usb30_mp_mock_utmi_clk_src.clkr.hw, 3112 }, 3113 .num_parents = 1, 3114 .flags = CLK_SET_RATE_PARENT, 3115 .ops = &clk_regmap_div_ro_ops, 3116 }, 3117 }; 3118 3119 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 3120 .reg = 0x3f07c, 3121 .shift = 0, 3122 .width = 4, 3123 .clkr.hw.init = &(const struct clk_init_data) { 3124 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 3125 .parent_hws = (const struct clk_hw*[]) { 3126 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 3127 }, 3128 .num_parents = 1, 3129 .flags = CLK_SET_RATE_PARENT, 3130 .ops = &clk_regmap_div_ro_ops, 3131 }, 3132 }; 3133 3134 static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = { 3135 .reg = 0xe206c, 3136 .shift = 0, 3137 .width = 4, 3138 .clkr.hw.init = &(const struct clk_init_data) { 3139 .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src", 3140 .parent_hws = (const struct clk_hw*[]) { 3141 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, 3142 }, 3143 .num_parents = 1, 3144 .flags = CLK_SET_RATE_PARENT, 3145 .ops = &clk_regmap_div_ro_ops, 3146 }, 3147 }; 3148 3149 static struct clk_regmap_div gcc_usb30_tert_mock_utmi_postdiv_clk_src = { 3150 .reg = 0xe106c, 3151 .shift = 0, 3152 .width = 4, 3153 .clkr.hw.init = &(const struct clk_init_data) { 3154 .name = "gcc_usb30_tert_mock_utmi_postdiv_clk_src", 3155 .parent_hws = (const struct clk_hw*[]) { 3156 &gcc_usb30_tert_mock_utmi_clk_src.clkr.hw, 3157 }, 3158 .num_parents = 1, 3159 .flags = CLK_SET_RATE_PARENT, 3160 .ops = &clk_regmap_div_ro_ops, 3161 }, 3162 }; 3163 3164 static struct clk_branch gcc_aggre_noc_pcie_3a_west_sf_axi_clk = { 3165 .halt_reg = 0xdc0bc, 3166 .halt_check = BRANCH_HALT_VOTED, 3167 .clkr = { 3168 .enable_reg = 0x62008, 3169 .enable_mask = BIT(27), 3170 .hw.init = &(const struct clk_init_data) { 3171 .name = "gcc_aggre_noc_pcie_3a_west_sf_axi_clk", 3172 .ops = &clk_branch2_ops, 3173 }, 3174 }, 3175 }; 3176 3177 static struct clk_branch gcc_aggre_noc_pcie_3b_west_sf_axi_clk = { 3178 .halt_reg = 0x941ec, 3179 .halt_check = BRANCH_HALT_VOTED, 3180 .clkr = { 3181 .enable_reg = 0x62008, 3182 .enable_mask = BIT(28), 3183 .hw.init = &(const struct clk_init_data) { 3184 .name = "gcc_aggre_noc_pcie_3b_west_sf_axi_clk", 3185 .ops = &clk_branch2_ops, 3186 }, 3187 }, 3188 }; 3189 3190 static struct clk_branch gcc_aggre_noc_pcie_4_west_sf_axi_clk = { 3191 .halt_reg = 0x881d0, 3192 .halt_check = BRANCH_HALT_VOTED, 3193 .clkr = { 3194 .enable_reg = 0x62008, 3195 .enable_mask = BIT(29), 3196 .hw.init = &(const struct clk_init_data) { 3197 .name = "gcc_aggre_noc_pcie_4_west_sf_axi_clk", 3198 .ops = &clk_branch2_ops, 3199 }, 3200 }, 3201 }; 3202 3203 static struct clk_branch gcc_aggre_noc_pcie_5_east_sf_axi_clk = { 3204 .halt_reg = 0xc30d0, 3205 .halt_check = BRANCH_HALT_VOTED, 3206 .clkr = { 3207 .enable_reg = 0x62008, 3208 .enable_mask = BIT(30), 3209 .hw.init = &(const struct clk_init_data) { 3210 .name = "gcc_aggre_noc_pcie_5_east_sf_axi_clk", 3211 .ops = &clk_branch2_ops, 3212 }, 3213 }, 3214 }; 3215 3216 static struct clk_branch gcc_aggre_noc_pcie_6_west_sf_axi_clk = { 3217 .halt_reg = 0x8a1d0, 3218 .halt_check = BRANCH_HALT_VOTED, 3219 .clkr = { 3220 .enable_reg = 0x62008, 3221 .enable_mask = BIT(31), 3222 .hw.init = &(const struct clk_init_data) { 3223 .name = "gcc_aggre_noc_pcie_6_west_sf_axi_clk", 3224 .ops = &clk_branch2_ops, 3225 }, 3226 }, 3227 }; 3228 3229 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 3230 .halt_reg = 0x77000, 3231 .halt_check = BRANCH_HALT_VOTED, 3232 .hwcg_reg = 0x77000, 3233 .hwcg_bit = 1, 3234 .clkr = { 3235 .enable_reg = 0x77000, 3236 .enable_mask = BIT(0), 3237 .hw.init = &(const struct clk_init_data) { 3238 .name = "gcc_aggre_ufs_phy_axi_clk", 3239 .parent_hws = (const struct clk_hw*[]) { 3240 &gcc_ufs_phy_axi_clk_src.clkr.hw, 3241 }, 3242 .num_parents = 1, 3243 .flags = CLK_SET_RATE_PARENT, 3244 .ops = &clk_branch2_ops, 3245 }, 3246 }, 3247 }; 3248 3249 static struct clk_branch gcc_aggre_usb2_prim_axi_clk = { 3250 .halt_reg = 0xbc17c, 3251 .halt_check = BRANCH_HALT_VOTED, 3252 .hwcg_reg = 0xbc17c, 3253 .hwcg_bit = 1, 3254 .clkr = { 3255 .enable_reg = 0xbc17c, 3256 .enable_mask = BIT(0), 3257 .hw.init = &(const struct clk_init_data) { 3258 .name = "gcc_aggre_usb2_prim_axi_clk", 3259 .parent_hws = (const struct clk_hw*[]) { 3260 &gcc_usb20_master_clk_src.clkr.hw, 3261 }, 3262 .num_parents = 1, 3263 .flags = CLK_SET_RATE_PARENT, 3264 .ops = &clk_branch2_ops, 3265 }, 3266 }, 3267 }; 3268 3269 static struct clk_branch gcc_aggre_usb3_mp_axi_clk = { 3270 .halt_reg = 0x9a004, 3271 .halt_check = BRANCH_HALT_VOTED, 3272 .hwcg_reg = 0x9a004, 3273 .hwcg_bit = 1, 3274 .clkr = { 3275 .enable_reg = 0x9a004, 3276 .enable_mask = BIT(0), 3277 .hw.init = &(const struct clk_init_data) { 3278 .name = "gcc_aggre_usb3_mp_axi_clk", 3279 .parent_hws = (const struct clk_hw*[]) { 3280 &gcc_usb30_mp_master_clk_src.clkr.hw, 3281 }, 3282 .num_parents = 1, 3283 .flags = CLK_SET_RATE_PARENT, 3284 .ops = &clk_branch2_ops, 3285 }, 3286 }, 3287 }; 3288 3289 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 3290 .halt_reg = 0x3f00c, 3291 .halt_check = BRANCH_HALT_VOTED, 3292 .hwcg_reg = 0x3f00c, 3293 .hwcg_bit = 1, 3294 .clkr = { 3295 .enable_reg = 0x3f00c, 3296 .enable_mask = BIT(0), 3297 .hw.init = &(const struct clk_init_data) { 3298 .name = "gcc_aggre_usb3_prim_axi_clk", 3299 .parent_hws = (const struct clk_hw*[]) { 3300 &gcc_usb30_prim_master_clk_src.clkr.hw, 3301 }, 3302 .num_parents = 1, 3303 .flags = CLK_SET_RATE_PARENT, 3304 .ops = &clk_branch2_ops, 3305 }, 3306 }, 3307 }; 3308 3309 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { 3310 .halt_reg = 0xe2004, 3311 .halt_check = BRANCH_HALT_VOTED, 3312 .hwcg_reg = 0xe2004, 3313 .hwcg_bit = 1, 3314 .clkr = { 3315 .enable_reg = 0xe2004, 3316 .enable_mask = BIT(0), 3317 .hw.init = &(const struct clk_init_data) { 3318 .name = "gcc_aggre_usb3_sec_axi_clk", 3319 .parent_hws = (const struct clk_hw*[]) { 3320 &gcc_usb30_sec_master_clk_src.clkr.hw, 3321 }, 3322 .num_parents = 1, 3323 .flags = CLK_SET_RATE_PARENT, 3324 .ops = &clk_branch2_ops, 3325 }, 3326 }, 3327 }; 3328 3329 static struct clk_branch gcc_aggre_usb3_tert_axi_clk = { 3330 .halt_reg = 0xe1004, 3331 .halt_check = BRANCH_HALT_VOTED, 3332 .hwcg_reg = 0xe1004, 3333 .hwcg_bit = 1, 3334 .clkr = { 3335 .enable_reg = 0xe1004, 3336 .enable_mask = BIT(0), 3337 .hw.init = &(const struct clk_init_data) { 3338 .name = "gcc_aggre_usb3_tert_axi_clk", 3339 .parent_hws = (const struct clk_hw*[]) { 3340 &gcc_usb30_tert_master_clk_src.clkr.hw, 3341 }, 3342 .num_parents = 1, 3343 .flags = CLK_SET_RATE_PARENT, 3344 .ops = &clk_branch2_ops, 3345 }, 3346 }, 3347 }; 3348 3349 static struct clk_branch gcc_aggre_usb4_0_axi_clk = { 3350 .halt_reg = 0x2b000, 3351 .halt_check = BRANCH_HALT_VOTED, 3352 .hwcg_reg = 0x2b000, 3353 .hwcg_bit = 1, 3354 .clkr = { 3355 .enable_reg = 0x2b000, 3356 .enable_mask = BIT(0), 3357 .hw.init = &(const struct clk_init_data) { 3358 .name = "gcc_aggre_usb4_0_axi_clk", 3359 .parent_hws = (const struct clk_hw*[]) { 3360 &gcc_usb4_0_master_clk_src.clkr.hw, 3361 }, 3362 .num_parents = 1, 3363 .flags = CLK_SET_RATE_PARENT, 3364 .ops = &clk_branch2_ops, 3365 }, 3366 }, 3367 }; 3368 3369 static struct clk_branch gcc_aggre_usb4_1_axi_clk = { 3370 .halt_reg = 0x2d000, 3371 .halt_check = BRANCH_HALT_VOTED, 3372 .hwcg_reg = 0x2d000, 3373 .hwcg_bit = 1, 3374 .clkr = { 3375 .enable_reg = 0x2d000, 3376 .enable_mask = BIT(0), 3377 .hw.init = &(const struct clk_init_data) { 3378 .name = "gcc_aggre_usb4_1_axi_clk", 3379 .parent_hws = (const struct clk_hw*[]) { 3380 &gcc_usb4_1_master_clk_src.clkr.hw, 3381 }, 3382 .num_parents = 1, 3383 .flags = CLK_SET_RATE_PARENT, 3384 .ops = &clk_branch2_ops, 3385 }, 3386 }, 3387 }; 3388 3389 static struct clk_branch gcc_aggre_usb4_2_axi_clk = { 3390 .halt_reg = 0xe0000, 3391 .halt_check = BRANCH_HALT_VOTED, 3392 .hwcg_reg = 0xe0000, 3393 .hwcg_bit = 1, 3394 .clkr = { 3395 .enable_reg = 0xe0000, 3396 .enable_mask = BIT(0), 3397 .hw.init = &(const struct clk_init_data) { 3398 .name = "gcc_aggre_usb4_2_axi_clk", 3399 .parent_hws = (const struct clk_hw*[]) { 3400 &gcc_usb4_2_master_clk_src.clkr.hw, 3401 }, 3402 .num_parents = 1, 3403 .flags = CLK_SET_RATE_PARENT, 3404 .ops = &clk_branch2_ops, 3405 }, 3406 }, 3407 }; 3408 3409 static struct clk_branch gcc_av1e_ahb_clk = { 3410 .halt_reg = 0x9b02c, 3411 .halt_check = BRANCH_HALT_VOTED, 3412 .hwcg_reg = 0x9b02c, 3413 .hwcg_bit = 1, 3414 .clkr = { 3415 .enable_reg = 0x9b02c, 3416 .enable_mask = BIT(0), 3417 .hw.init = &(const struct clk_init_data) { 3418 .name = "gcc_av1e_ahb_clk", 3419 .ops = &clk_branch2_ops, 3420 }, 3421 }, 3422 }; 3423 3424 static struct clk_branch gcc_av1e_axi_clk = { 3425 .halt_reg = 0x9b030, 3426 .halt_check = BRANCH_HALT_SKIP, 3427 .hwcg_reg = 0x9b030, 3428 .hwcg_bit = 1, 3429 .clkr = { 3430 .enable_reg = 0x9b030, 3431 .enable_mask = BIT(0), 3432 .hw.init = &(const struct clk_init_data) { 3433 .name = "gcc_av1e_axi_clk", 3434 .ops = &clk_branch2_ops, 3435 }, 3436 }, 3437 }; 3438 3439 static struct clk_branch gcc_av1e_xo_clk = { 3440 .halt_reg = 0x9b044, 3441 .halt_check = BRANCH_HALT, 3442 .clkr = { 3443 .enable_reg = 0x9b044, 3444 .enable_mask = BIT(0), 3445 .hw.init = &(const struct clk_init_data) { 3446 .name = "gcc_av1e_xo_clk", 3447 .ops = &clk_branch2_ops, 3448 }, 3449 }, 3450 }; 3451 3452 static struct clk_branch gcc_boot_rom_ahb_clk = { 3453 .halt_reg = 0x34038, 3454 .halt_check = BRANCH_HALT_VOTED, 3455 .hwcg_reg = 0x34038, 3456 .hwcg_bit = 1, 3457 .clkr = { 3458 .enable_reg = 0x62020, 3459 .enable_mask = BIT(27), 3460 .hw.init = &(const struct clk_init_data) { 3461 .name = "gcc_boot_rom_ahb_clk", 3462 .ops = &clk_branch2_ops, 3463 }, 3464 }, 3465 }; 3466 3467 static struct clk_branch gcc_camera_hf_axi_clk = { 3468 .halt_reg = 0x26014, 3469 .halt_check = BRANCH_HALT_SKIP, 3470 .hwcg_reg = 0x26014, 3471 .hwcg_bit = 1, 3472 .clkr = { 3473 .enable_reg = 0x26014, 3474 .enable_mask = BIT(0), 3475 .hw.init = &(const struct clk_init_data) { 3476 .name = "gcc_camera_hf_axi_clk", 3477 .ops = &clk_branch2_ops, 3478 }, 3479 }, 3480 }; 3481 3482 static struct clk_branch gcc_camera_sf_axi_clk = { 3483 .halt_reg = 0x26028, 3484 .halt_check = BRANCH_HALT_SKIP, 3485 .hwcg_reg = 0x26028, 3486 .hwcg_bit = 1, 3487 .clkr = { 3488 .enable_reg = 0x26028, 3489 .enable_mask = BIT(0), 3490 .hw.init = &(const struct clk_init_data) { 3491 .name = "gcc_camera_sf_axi_clk", 3492 .ops = &clk_branch2_ops, 3493 }, 3494 }, 3495 }; 3496 3497 static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = { 3498 .halt_reg = 0x82004, 3499 .halt_check = BRANCH_HALT_VOTED, 3500 .hwcg_reg = 0x82004, 3501 .hwcg_bit = 1, 3502 .clkr = { 3503 .enable_reg = 0x62008, 3504 .enable_mask = BIT(19), 3505 .hw.init = &(const struct clk_init_data) { 3506 .name = "gcc_cfg_noc_pcie_anoc_ahb_clk", 3507 .ops = &clk_branch2_ops, 3508 }, 3509 }, 3510 }; 3511 3512 static struct clk_branch gcc_cfg_noc_pcie_anoc_south_ahb_clk = { 3513 .halt_reg = 0xba2ec, 3514 .halt_check = BRANCH_HALT_VOTED, 3515 .hwcg_reg = 0xba2ec, 3516 .hwcg_bit = 1, 3517 .clkr = { 3518 .enable_reg = 0x62008, 3519 .enable_mask = BIT(16), 3520 .hw.init = &(const struct clk_init_data) { 3521 .name = "gcc_cfg_noc_pcie_anoc_south_ahb_clk", 3522 .ops = &clk_branch2_ops, 3523 }, 3524 }, 3525 }; 3526 3527 static struct clk_branch gcc_cfg_noc_usb2_prim_axi_clk = { 3528 .halt_reg = 0xbc178, 3529 .halt_check = BRANCH_HALT_VOTED, 3530 .hwcg_reg = 0xbc178, 3531 .hwcg_bit = 1, 3532 .clkr = { 3533 .enable_reg = 0xbc178, 3534 .enable_mask = BIT(0), 3535 .hw.init = &(const struct clk_init_data) { 3536 .name = "gcc_cfg_noc_usb2_prim_axi_clk", 3537 .parent_hws = (const struct clk_hw*[]) { 3538 &gcc_usb20_master_clk_src.clkr.hw, 3539 }, 3540 .num_parents = 1, 3541 .flags = CLK_SET_RATE_PARENT, 3542 .ops = &clk_branch2_ops, 3543 }, 3544 }, 3545 }; 3546 3547 static struct clk_branch gcc_cfg_noc_usb3_mp_axi_clk = { 3548 .halt_reg = 0x9a000, 3549 .halt_check = BRANCH_HALT_VOTED, 3550 .hwcg_reg = 0x9a000, 3551 .hwcg_bit = 1, 3552 .clkr = { 3553 .enable_reg = 0x9a000, 3554 .enable_mask = BIT(0), 3555 .hw.init = &(const struct clk_init_data) { 3556 .name = "gcc_cfg_noc_usb3_mp_axi_clk", 3557 .parent_hws = (const struct clk_hw*[]) { 3558 &gcc_usb30_mp_master_clk_src.clkr.hw, 3559 }, 3560 .num_parents = 1, 3561 .flags = CLK_SET_RATE_PARENT, 3562 .ops = &clk_branch2_ops, 3563 }, 3564 }, 3565 }; 3566 3567 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 3568 .halt_reg = 0x3f000, 3569 .halt_check = BRANCH_HALT_VOTED, 3570 .hwcg_reg = 0x3f000, 3571 .hwcg_bit = 1, 3572 .clkr = { 3573 .enable_reg = 0x3f000, 3574 .enable_mask = BIT(0), 3575 .hw.init = &(const struct clk_init_data) { 3576 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 3577 .parent_hws = (const struct clk_hw*[]) { 3578 &gcc_usb30_prim_master_clk_src.clkr.hw, 3579 }, 3580 .num_parents = 1, 3581 .flags = CLK_SET_RATE_PARENT, 3582 .ops = &clk_branch2_ops, 3583 }, 3584 }, 3585 }; 3586 3587 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { 3588 .halt_reg = 0xe2000, 3589 .halt_check = BRANCH_HALT_VOTED, 3590 .hwcg_reg = 0xe2000, 3591 .hwcg_bit = 1, 3592 .clkr = { 3593 .enable_reg = 0xe2000, 3594 .enable_mask = BIT(0), 3595 .hw.init = &(const struct clk_init_data) { 3596 .name = "gcc_cfg_noc_usb3_sec_axi_clk", 3597 .parent_hws = (const struct clk_hw*[]) { 3598 &gcc_usb30_sec_master_clk_src.clkr.hw, 3599 }, 3600 .num_parents = 1, 3601 .flags = CLK_SET_RATE_PARENT, 3602 .ops = &clk_branch2_ops, 3603 }, 3604 }, 3605 }; 3606 3607 static struct clk_branch gcc_cfg_noc_usb3_tert_axi_clk = { 3608 .halt_reg = 0xe1000, 3609 .halt_check = BRANCH_HALT_VOTED, 3610 .hwcg_reg = 0xe1000, 3611 .hwcg_bit = 1, 3612 .clkr = { 3613 .enable_reg = 0xe1000, 3614 .enable_mask = BIT(0), 3615 .hw.init = &(const struct clk_init_data) { 3616 .name = "gcc_cfg_noc_usb3_tert_axi_clk", 3617 .parent_hws = (const struct clk_hw*[]) { 3618 &gcc_usb30_tert_master_clk_src.clkr.hw, 3619 }, 3620 .num_parents = 1, 3621 .flags = CLK_SET_RATE_PARENT, 3622 .ops = &clk_branch2_ops, 3623 }, 3624 }, 3625 }; 3626 3627 static struct clk_branch gcc_cfg_noc_usb_anoc_ahb_clk = { 3628 .halt_reg = 0x3f004, 3629 .halt_check = BRANCH_HALT_VOTED, 3630 .hwcg_reg = 0x3f004, 3631 .hwcg_bit = 1, 3632 .clkr = { 3633 .enable_reg = 0x62008, 3634 .enable_mask = BIT(17), 3635 .hw.init = &(const struct clk_init_data) { 3636 .name = "gcc_cfg_noc_usb_anoc_ahb_clk", 3637 .ops = &clk_branch2_ops, 3638 }, 3639 }, 3640 }; 3641 3642 static struct clk_branch gcc_cfg_noc_usb_anoc_south_ahb_clk = { 3643 .halt_reg = 0x3f008, 3644 .halt_check = BRANCH_HALT_VOTED, 3645 .hwcg_reg = 0x3f008, 3646 .hwcg_bit = 1, 3647 .clkr = { 3648 .enable_reg = 0x62008, 3649 .enable_mask = BIT(18), 3650 .hw.init = &(const struct clk_init_data) { 3651 .name = "gcc_cfg_noc_usb_anoc_south_ahb_clk", 3652 .ops = &clk_branch2_ops, 3653 }, 3654 }, 3655 }; 3656 3657 static struct clk_branch gcc_disp_hf_axi_clk = { 3658 .halt_reg = 0x27008, 3659 .halt_check = BRANCH_HALT_SKIP, 3660 .clkr = { 3661 .enable_reg = 0x27008, 3662 .enable_mask = BIT(0), 3663 .hw.init = &(const struct clk_init_data) { 3664 .name = "gcc_disp_hf_axi_clk", 3665 .ops = &clk_branch2_ops, 3666 .flags = CLK_IS_CRITICAL, 3667 }, 3668 }, 3669 }; 3670 3671 static struct clk_branch gcc_eva_axi0_clk = { 3672 .halt_reg = 0x9b008, 3673 .halt_check = BRANCH_HALT_SKIP, 3674 .hwcg_reg = 0x9b008, 3675 .hwcg_bit = 1, 3676 .clkr = { 3677 .enable_reg = 0x9b008, 3678 .enable_mask = BIT(0), 3679 .hw.init = &(const struct clk_init_data) { 3680 .name = "gcc_eva_axi0_clk", 3681 .ops = &clk_branch2_ops, 3682 }, 3683 }, 3684 }; 3685 3686 static struct clk_branch gcc_eva_axi0c_clk = { 3687 .halt_reg = 0x9b01c, 3688 .halt_check = BRANCH_HALT_VOTED, 3689 .hwcg_reg = 0x9b01c, 3690 .hwcg_bit = 1, 3691 .clkr = { 3692 .enable_reg = 0x9b01c, 3693 .enable_mask = BIT(0), 3694 .hw.init = &(const struct clk_init_data) { 3695 .name = "gcc_eva_axi0c_clk", 3696 .ops = &clk_branch2_ops, 3697 }, 3698 }, 3699 }; 3700 3701 static struct clk_branch gcc_gp1_clk = { 3702 .halt_reg = 0x64000, 3703 .halt_check = BRANCH_HALT, 3704 .clkr = { 3705 .enable_reg = 0x64000, 3706 .enable_mask = BIT(0), 3707 .hw.init = &(const struct clk_init_data) { 3708 .name = "gcc_gp1_clk", 3709 .parent_hws = (const struct clk_hw*[]) { 3710 &gcc_gp1_clk_src.clkr.hw, 3711 }, 3712 .num_parents = 1, 3713 .flags = CLK_SET_RATE_PARENT, 3714 .ops = &clk_branch2_ops, 3715 }, 3716 }, 3717 }; 3718 3719 static struct clk_branch gcc_gp2_clk = { 3720 .halt_reg = 0x92000, 3721 .halt_check = BRANCH_HALT, 3722 .clkr = { 3723 .enable_reg = 0x92000, 3724 .enable_mask = BIT(0), 3725 .hw.init = &(const struct clk_init_data) { 3726 .name = "gcc_gp2_clk", 3727 .parent_hws = (const struct clk_hw*[]) { 3728 &gcc_gp2_clk_src.clkr.hw, 3729 }, 3730 .num_parents = 1, 3731 .flags = CLK_SET_RATE_PARENT, 3732 .ops = &clk_branch2_ops, 3733 }, 3734 }, 3735 }; 3736 3737 static struct clk_branch gcc_gp3_clk = { 3738 .halt_reg = 0x93000, 3739 .halt_check = BRANCH_HALT, 3740 .clkr = { 3741 .enable_reg = 0x93000, 3742 .enable_mask = BIT(0), 3743 .hw.init = &(const struct clk_init_data) { 3744 .name = "gcc_gp3_clk", 3745 .parent_hws = (const struct clk_hw*[]) { 3746 &gcc_gp3_clk_src.clkr.hw, 3747 }, 3748 .num_parents = 1, 3749 .flags = CLK_SET_RATE_PARENT, 3750 .ops = &clk_branch2_ops, 3751 }, 3752 }, 3753 }; 3754 3755 static struct clk_branch gcc_gpu_gemnoc_gfx_clk = { 3756 .halt_reg = 0x71010, 3757 .halt_check = BRANCH_HALT_VOTED, 3758 .hwcg_reg = 0x71010, 3759 .hwcg_bit = 1, 3760 .clkr = { 3761 .enable_reg = 0x71010, 3762 .enable_mask = BIT(0), 3763 .hw.init = &(const struct clk_init_data) { 3764 .name = "gcc_gpu_gemnoc_gfx_clk", 3765 .ops = &clk_branch2_ops, 3766 }, 3767 }, 3768 }; 3769 3770 static struct clk_branch gcc_gpu_gpll0_clk_src = { 3771 .halt_reg = 0x71024, 3772 .halt_check = BRANCH_HALT_VOTED, 3773 .hwcg_reg = 0x71024, 3774 .hwcg_bit = 1, 3775 .clkr = { 3776 .enable_reg = 0x62038, 3777 .enable_mask = BIT(0), 3778 .hw.init = &(const struct clk_init_data) { 3779 .name = "gcc_gpu_gpll0_clk_src", 3780 .parent_hws = (const struct clk_hw*[]) { 3781 &gcc_gpll0.clkr.hw, 3782 }, 3783 .num_parents = 1, 3784 .flags = CLK_SET_RATE_PARENT, 3785 .ops = &clk_branch2_ops, 3786 }, 3787 }, 3788 }; 3789 3790 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 3791 .halt_reg = 0x7102c, 3792 .halt_check = BRANCH_HALT_VOTED, 3793 .hwcg_reg = 0x7102c, 3794 .hwcg_bit = 1, 3795 .clkr = { 3796 .enable_reg = 0x62038, 3797 .enable_mask = BIT(1), 3798 .hw.init = &(const struct clk_init_data) { 3799 .name = "gcc_gpu_gpll0_div_clk_src", 3800 .parent_hws = (const struct clk_hw*[]) { 3801 &gcc_gpll0_out_even.clkr.hw, 3802 }, 3803 .num_parents = 1, 3804 .flags = CLK_SET_RATE_PARENT, 3805 .ops = &clk_branch2_ops, 3806 }, 3807 }, 3808 }; 3809 3810 static struct clk_branch gcc_pcie_0_aux_clk = { 3811 .halt_reg = 0xc8018, 3812 .halt_check = BRANCH_HALT_VOTED, 3813 .clkr = { 3814 .enable_reg = 0x62010, 3815 .enable_mask = BIT(25), 3816 .hw.init = &(const struct clk_init_data) { 3817 .name = "gcc_pcie_0_aux_clk", 3818 .parent_hws = (const struct clk_hw*[]) { 3819 &gcc_pcie_0_aux_clk_src.clkr.hw, 3820 }, 3821 .num_parents = 1, 3822 .flags = CLK_SET_RATE_PARENT, 3823 .ops = &clk_branch2_ops, 3824 }, 3825 }, 3826 }; 3827 3828 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 3829 .halt_reg = 0xba4a8, 3830 .halt_check = BRANCH_HALT_VOTED, 3831 .hwcg_reg = 0xba4a8, 3832 .hwcg_bit = 1, 3833 .clkr = { 3834 .enable_reg = 0x62010, 3835 .enable_mask = BIT(24), 3836 .hw.init = &(const struct clk_init_data) { 3837 .name = "gcc_pcie_0_cfg_ahb_clk", 3838 .ops = &clk_branch2_ops, 3839 }, 3840 }, 3841 }; 3842 3843 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 3844 .halt_reg = 0xba498, 3845 .halt_check = BRANCH_HALT_SKIP, 3846 .hwcg_reg = 0xba498, 3847 .hwcg_bit = 1, 3848 .clkr = { 3849 .enable_reg = 0x62010, 3850 .enable_mask = BIT(23), 3851 .hw.init = &(const struct clk_init_data) { 3852 .name = "gcc_pcie_0_mstr_axi_clk", 3853 .ops = &clk_branch2_ops, 3854 }, 3855 }, 3856 }; 3857 3858 static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 3859 .halt_reg = 0xc8038, 3860 .halt_check = BRANCH_HALT_VOTED, 3861 .clkr = { 3862 .enable_reg = 0x62010, 3863 .enable_mask = BIT(27), 3864 .hw.init = &(const struct clk_init_data) { 3865 .name = "gcc_pcie_0_phy_rchng_clk", 3866 .parent_hws = (const struct clk_hw*[]) { 3867 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 3868 }, 3869 .num_parents = 1, 3870 .flags = CLK_SET_RATE_PARENT, 3871 .ops = &clk_branch2_ops, 3872 }, 3873 }, 3874 }; 3875 3876 static struct clk_branch gcc_pcie_0_pipe_clk = { 3877 .halt_reg = 0xc8028, 3878 .halt_check = BRANCH_HALT_SKIP, 3879 .clkr = { 3880 .enable_reg = 0x62010, 3881 .enable_mask = BIT(26), 3882 .hw.init = &(const struct clk_init_data) { 3883 .name = "gcc_pcie_0_pipe_clk", 3884 .parent_hws = (const struct clk_hw*[]) { 3885 &gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr.hw, 3886 }, 3887 .num_parents = 1, 3888 .flags = CLK_SET_RATE_PARENT, 3889 .ops = &clk_branch2_ops, 3890 }, 3891 }, 3892 }; 3893 3894 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 3895 .halt_reg = 0xba488, 3896 .halt_check = BRANCH_HALT_VOTED, 3897 .hwcg_reg = 0xba488, 3898 .hwcg_bit = 1, 3899 .clkr = { 3900 .enable_reg = 0x62010, 3901 .enable_mask = BIT(22), 3902 .hw.init = &(const struct clk_init_data) { 3903 .name = "gcc_pcie_0_slv_axi_clk", 3904 .ops = &clk_branch2_ops, 3905 }, 3906 }, 3907 }; 3908 3909 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 3910 .halt_reg = 0xba484, 3911 .halt_check = BRANCH_HALT_VOTED, 3912 .clkr = { 3913 .enable_reg = 0x62010, 3914 .enable_mask = BIT(21), 3915 .hw.init = &(const struct clk_init_data) { 3916 .name = "gcc_pcie_0_slv_q2a_axi_clk", 3917 .ops = &clk_branch2_ops, 3918 }, 3919 }, 3920 }; 3921 3922 static struct clk_branch gcc_pcie_1_aux_clk = { 3923 .halt_reg = 0x2e018, 3924 .halt_check = BRANCH_HALT_VOTED, 3925 .clkr = { 3926 .enable_reg = 0x62010, 3927 .enable_mask = BIT(18), 3928 .hw.init = &(const struct clk_init_data) { 3929 .name = "gcc_pcie_1_aux_clk", 3930 .parent_hws = (const struct clk_hw*[]) { 3931 &gcc_pcie_1_aux_clk_src.clkr.hw, 3932 }, 3933 .num_parents = 1, 3934 .flags = CLK_SET_RATE_PARENT, 3935 .ops = &clk_branch2_ops, 3936 }, 3937 }, 3938 }; 3939 3940 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 3941 .halt_reg = 0xba480, 3942 .halt_check = BRANCH_HALT_VOTED, 3943 .hwcg_reg = 0xba480, 3944 .hwcg_bit = 1, 3945 .clkr = { 3946 .enable_reg = 0x62010, 3947 .enable_mask = BIT(17), 3948 .hw.init = &(const struct clk_init_data) { 3949 .name = "gcc_pcie_1_cfg_ahb_clk", 3950 .ops = &clk_branch2_ops, 3951 }, 3952 }, 3953 }; 3954 3955 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 3956 .halt_reg = 0xba470, 3957 .halt_check = BRANCH_HALT_SKIP, 3958 .hwcg_reg = 0xba470, 3959 .hwcg_bit = 1, 3960 .clkr = { 3961 .enable_reg = 0x62010, 3962 .enable_mask = BIT(16), 3963 .hw.init = &(const struct clk_init_data) { 3964 .name = "gcc_pcie_1_mstr_axi_clk", 3965 .ops = &clk_branch2_ops, 3966 }, 3967 }, 3968 }; 3969 3970 static struct clk_branch gcc_pcie_1_phy_rchng_clk = { 3971 .halt_reg = 0x2e038, 3972 .halt_check = BRANCH_HALT_VOTED, 3973 .clkr = { 3974 .enable_reg = 0x62010, 3975 .enable_mask = BIT(20), 3976 .hw.init = &(const struct clk_init_data) { 3977 .name = "gcc_pcie_1_phy_rchng_clk", 3978 .parent_hws = (const struct clk_hw*[]) { 3979 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, 3980 }, 3981 .num_parents = 1, 3982 .flags = CLK_SET_RATE_PARENT, 3983 .ops = &clk_branch2_ops, 3984 }, 3985 }, 3986 }; 3987 3988 static struct clk_branch gcc_pcie_1_pipe_clk = { 3989 .halt_reg = 0x2e028, 3990 .halt_check = BRANCH_HALT_SKIP, 3991 .clkr = { 3992 .enable_reg = 0x62010, 3993 .enable_mask = BIT(19), 3994 .hw.init = &(const struct clk_init_data) { 3995 .name = "gcc_pcie_1_pipe_clk", 3996 .parent_hws = (const struct clk_hw*[]) { 3997 &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw, 3998 }, 3999 .num_parents = 1, 4000 .flags = CLK_SET_RATE_PARENT, 4001 .ops = &clk_branch2_ops, 4002 }, 4003 }, 4004 }; 4005 4006 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 4007 .halt_reg = 0xba460, 4008 .halt_check = BRANCH_HALT_VOTED, 4009 .hwcg_reg = 0xba460, 4010 .hwcg_bit = 1, 4011 .clkr = { 4012 .enable_reg = 0x62010, 4013 .enable_mask = BIT(15), 4014 .hw.init = &(const struct clk_init_data) { 4015 .name = "gcc_pcie_1_slv_axi_clk", 4016 .ops = &clk_branch2_ops, 4017 }, 4018 }, 4019 }; 4020 4021 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 4022 .halt_reg = 0xba45c, 4023 .halt_check = BRANCH_HALT_VOTED, 4024 .clkr = { 4025 .enable_reg = 0x62010, 4026 .enable_mask = BIT(14), 4027 .hw.init = &(const struct clk_init_data) { 4028 .name = "gcc_pcie_1_slv_q2a_axi_clk", 4029 .ops = &clk_branch2_ops, 4030 }, 4031 }, 4032 }; 4033 4034 static struct clk_branch gcc_pcie_2_aux_clk = { 4035 .halt_reg = 0xc0018, 4036 .halt_check = BRANCH_HALT_VOTED, 4037 .clkr = { 4038 .enable_reg = 0x62018, 4039 .enable_mask = BIT(0), 4040 .hw.init = &(const struct clk_init_data) { 4041 .name = "gcc_pcie_2_aux_clk", 4042 .parent_hws = (const struct clk_hw*[]) { 4043 &gcc_pcie_2_aux_clk_src.clkr.hw, 4044 }, 4045 .num_parents = 1, 4046 .flags = CLK_SET_RATE_PARENT, 4047 .ops = &clk_branch2_ops, 4048 }, 4049 }, 4050 }; 4051 4052 static struct clk_branch gcc_pcie_2_cfg_ahb_clk = { 4053 .halt_reg = 0xba4d0, 4054 .halt_check = BRANCH_HALT_VOTED, 4055 .hwcg_reg = 0xba4d0, 4056 .hwcg_bit = 1, 4057 .clkr = { 4058 .enable_reg = 0x62010, 4059 .enable_mask = BIT(31), 4060 .hw.init = &(const struct clk_init_data) { 4061 .name = "gcc_pcie_2_cfg_ahb_clk", 4062 .ops = &clk_branch2_ops, 4063 }, 4064 }, 4065 }; 4066 4067 static struct clk_branch gcc_pcie_2_mstr_axi_clk = { 4068 .halt_reg = 0xba4c0, 4069 .halt_check = BRANCH_HALT_SKIP, 4070 .hwcg_reg = 0xba4c0, 4071 .hwcg_bit = 1, 4072 .clkr = { 4073 .enable_reg = 0x62010, 4074 .enable_mask = BIT(30), 4075 .hw.init = &(const struct clk_init_data) { 4076 .name = "gcc_pcie_2_mstr_axi_clk", 4077 .ops = &clk_branch2_ops, 4078 }, 4079 }, 4080 }; 4081 4082 static struct clk_branch gcc_pcie_2_phy_rchng_clk = { 4083 .halt_reg = 0xc0038, 4084 .halt_check = BRANCH_HALT_VOTED, 4085 .clkr = { 4086 .enable_reg = 0x62018, 4087 .enable_mask = BIT(2), 4088 .hw.init = &(const struct clk_init_data) { 4089 .name = "gcc_pcie_2_phy_rchng_clk", 4090 .parent_hws = (const struct clk_hw*[]) { 4091 &gcc_pcie_2_phy_rchng_clk_src.clkr.hw, 4092 }, 4093 .num_parents = 1, 4094 .flags = CLK_SET_RATE_PARENT, 4095 .ops = &clk_branch2_ops, 4096 }, 4097 }, 4098 }; 4099 4100 static struct clk_branch gcc_pcie_2_pipe_clk = { 4101 .halt_reg = 0xc0028, 4102 .halt_check = BRANCH_HALT_SKIP, 4103 .clkr = { 4104 .enable_reg = 0x62018, 4105 .enable_mask = BIT(1), 4106 .hw.init = &(const struct clk_init_data) { 4107 .name = "gcc_pcie_2_pipe_clk", 4108 .parent_hws = (const struct clk_hw*[]) { 4109 &gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr.hw, 4110 }, 4111 .num_parents = 1, 4112 .flags = CLK_SET_RATE_PARENT, 4113 .ops = &clk_branch2_ops, 4114 }, 4115 }, 4116 }; 4117 4118 static struct clk_branch gcc_pcie_2_slv_axi_clk = { 4119 .halt_reg = 0xba4b0, 4120 .halt_check = BRANCH_HALT_VOTED, 4121 .hwcg_reg = 0xba4b0, 4122 .hwcg_bit = 1, 4123 .clkr = { 4124 .enable_reg = 0x62010, 4125 .enable_mask = BIT(29), 4126 .hw.init = &(const struct clk_init_data) { 4127 .name = "gcc_pcie_2_slv_axi_clk", 4128 .ops = &clk_branch2_ops, 4129 }, 4130 }, 4131 }; 4132 4133 static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = { 4134 .halt_reg = 0xba4ac, 4135 .halt_check = BRANCH_HALT_VOTED, 4136 .clkr = { 4137 .enable_reg = 0x62010, 4138 .enable_mask = BIT(28), 4139 .hw.init = &(const struct clk_init_data) { 4140 .name = "gcc_pcie_2_slv_q2a_axi_clk", 4141 .ops = &clk_branch2_ops, 4142 }, 4143 }, 4144 }; 4145 4146 static struct clk_branch gcc_pcie_3a_aux_clk = { 4147 .halt_reg = 0xdc04c, 4148 .halt_check = BRANCH_HALT_VOTED, 4149 .hwcg_reg = 0xdc04c, 4150 .hwcg_bit = 1, 4151 .clkr = { 4152 .enable_reg = 0x62028, 4153 .enable_mask = BIT(16), 4154 .hw.init = &(const struct clk_init_data) { 4155 .name = "gcc_pcie_3a_aux_clk", 4156 .parent_hws = (const struct clk_hw*[]) { 4157 &gcc_pcie_3a_aux_clk_src.clkr.hw, 4158 }, 4159 .num_parents = 1, 4160 .flags = CLK_SET_RATE_PARENT, 4161 .ops = &clk_branch2_ops, 4162 }, 4163 }, 4164 }; 4165 4166 static struct clk_branch gcc_pcie_3a_cfg_ahb_clk = { 4167 .halt_reg = 0xba4f0, 4168 .halt_check = BRANCH_HALT_VOTED, 4169 .hwcg_reg = 0xba4f0, 4170 .hwcg_bit = 1, 4171 .clkr = { 4172 .enable_reg = 0x62028, 4173 .enable_mask = BIT(15), 4174 .hw.init = &(const struct clk_init_data) { 4175 .name = "gcc_pcie_3a_cfg_ahb_clk", 4176 .ops = &clk_branch2_ops, 4177 }, 4178 }, 4179 }; 4180 4181 static struct clk_branch gcc_pcie_3a_mstr_axi_clk = { 4182 .halt_reg = 0xdc038, 4183 .halt_check = BRANCH_HALT_SKIP, 4184 .hwcg_reg = 0xdc038, 4185 .hwcg_bit = 1, 4186 .clkr = { 4187 .enable_reg = 0x62028, 4188 .enable_mask = BIT(14), 4189 .hw.init = &(const struct clk_init_data) { 4190 .name = "gcc_pcie_3a_mstr_axi_clk", 4191 .ops = &clk_branch2_ops, 4192 }, 4193 }, 4194 }; 4195 4196 static struct clk_branch gcc_pcie_3a_phy_rchng_clk = { 4197 .halt_reg = 0xdc06c, 4198 .halt_check = BRANCH_HALT_VOTED, 4199 .hwcg_reg = 0xdc06c, 4200 .hwcg_bit = 1, 4201 .clkr = { 4202 .enable_reg = 0x62028, 4203 .enable_mask = BIT(18), 4204 .hw.init = &(const struct clk_init_data) { 4205 .name = "gcc_pcie_3a_phy_rchng_clk", 4206 .parent_hws = (const struct clk_hw*[]) { 4207 &gcc_pcie_3a_phy_rchng_clk_src.clkr.hw, 4208 }, 4209 .num_parents = 1, 4210 .flags = CLK_SET_RATE_PARENT, 4211 .ops = &clk_branch2_ops, 4212 }, 4213 }, 4214 }; 4215 4216 static struct clk_branch gcc_pcie_3a_pipe_clk = { 4217 .halt_reg = 0xdc05c, 4218 .halt_check = BRANCH_HALT_SKIP, 4219 .hwcg_reg = 0xdc05c, 4220 .hwcg_bit = 1, 4221 .clkr = { 4222 .enable_reg = 0x62028, 4223 .enable_mask = BIT(17), 4224 .hw.init = &(const struct clk_init_data) { 4225 .name = "gcc_pcie_3a_pipe_clk", 4226 .parent_hws = (const struct clk_hw*[]) { 4227 &gcc_pcie_3a_pipe_clk_src.clkr.hw, 4228 }, 4229 .num_parents = 1, 4230 .flags = CLK_SET_RATE_PARENT, 4231 .ops = &clk_branch2_ops, 4232 }, 4233 }, 4234 }; 4235 4236 static struct clk_branch gcc_pcie_3a_slv_axi_clk = { 4237 .halt_reg = 0xdc024, 4238 .halt_check = BRANCH_HALT_VOTED, 4239 .hwcg_reg = 0xdc024, 4240 .hwcg_bit = 1, 4241 .clkr = { 4242 .enable_reg = 0x62028, 4243 .enable_mask = BIT(13), 4244 .hw.init = &(const struct clk_init_data) { 4245 .name = "gcc_pcie_3a_slv_axi_clk", 4246 .ops = &clk_branch2_ops, 4247 }, 4248 }, 4249 }; 4250 4251 static struct clk_branch gcc_pcie_3a_slv_q2a_axi_clk = { 4252 .halt_reg = 0xdc01c, 4253 .halt_check = BRANCH_HALT_VOTED, 4254 .hwcg_reg = 0xdc01c, 4255 .hwcg_bit = 1, 4256 .clkr = { 4257 .enable_reg = 0x62028, 4258 .enable_mask = BIT(12), 4259 .hw.init = &(const struct clk_init_data) { 4260 .name = "gcc_pcie_3a_slv_q2a_axi_clk", 4261 .ops = &clk_branch2_ops, 4262 }, 4263 }, 4264 }; 4265 4266 static struct clk_branch gcc_pcie_3b_aux_clk = { 4267 .halt_reg = 0x94050, 4268 .halt_check = BRANCH_HALT_VOTED, 4269 .clkr = { 4270 .enable_reg = 0x62028, 4271 .enable_mask = BIT(25), 4272 .hw.init = &(const struct clk_init_data) { 4273 .name = "gcc_pcie_3b_aux_clk", 4274 .parent_hws = (const struct clk_hw*[]) { 4275 &gcc_pcie_3b_aux_clk_src.clkr.hw, 4276 }, 4277 .num_parents = 1, 4278 .flags = CLK_SET_RATE_PARENT, 4279 .ops = &clk_branch2_ops, 4280 }, 4281 }, 4282 }; 4283 4284 static struct clk_branch gcc_pcie_3b_cfg_ahb_clk = { 4285 .halt_reg = 0xba4f4, 4286 .halt_check = BRANCH_HALT_VOTED, 4287 .hwcg_reg = 0xba4f4, 4288 .hwcg_bit = 1, 4289 .clkr = { 4290 .enable_reg = 0x62028, 4291 .enable_mask = BIT(24), 4292 .hw.init = &(const struct clk_init_data) { 4293 .name = "gcc_pcie_3b_cfg_ahb_clk", 4294 .ops = &clk_branch2_ops, 4295 }, 4296 }, 4297 }; 4298 4299 static struct clk_branch gcc_pcie_3b_mstr_axi_clk = { 4300 .halt_reg = 0x94038, 4301 .halt_check = BRANCH_HALT_SKIP, 4302 .hwcg_reg = 0x94038, 4303 .hwcg_bit = 1, 4304 .clkr = { 4305 .enable_reg = 0x62028, 4306 .enable_mask = BIT(23), 4307 .hw.init = &(const struct clk_init_data) { 4308 .name = "gcc_pcie_3b_mstr_axi_clk", 4309 .ops = &clk_branch2_ops, 4310 }, 4311 }, 4312 }; 4313 4314 static struct clk_branch gcc_pcie_3b_phy_rchng_clk = { 4315 .halt_reg = 0x94084, 4316 .halt_check = BRANCH_HALT_VOTED, 4317 .clkr = { 4318 .enable_reg = 0x62028, 4319 .enable_mask = BIT(28), 4320 .hw.init = &(const struct clk_init_data) { 4321 .name = "gcc_pcie_3b_phy_rchng_clk", 4322 .parent_hws = (const struct clk_hw*[]) { 4323 &gcc_pcie_3b_phy_rchng_clk_src.clkr.hw, 4324 }, 4325 .num_parents = 1, 4326 .flags = CLK_SET_RATE_PARENT, 4327 .ops = &clk_branch2_ops, 4328 }, 4329 }, 4330 }; 4331 4332 static struct clk_branch gcc_pcie_3b_pipe_clk = { 4333 .halt_reg = 0x94060, 4334 .halt_check = BRANCH_HALT_SKIP, 4335 .clkr = { 4336 .enable_reg = 0x62028, 4337 .enable_mask = BIT(26), 4338 .hw.init = &(const struct clk_init_data) { 4339 .name = "gcc_pcie_3b_pipe_clk", 4340 .parent_hws = (const struct clk_hw*[]) { 4341 &gcc_pcie_3b_pipe_clk_src.clkr.hw, 4342 }, 4343 .num_parents = 1, 4344 .flags = CLK_SET_RATE_PARENT, 4345 .ops = &clk_branch2_ops, 4346 }, 4347 }, 4348 }; 4349 4350 static struct clk_branch gcc_pcie_3b_pipe_div2_clk = { 4351 .halt_reg = 0x94074, 4352 .halt_check = BRANCH_HALT_SKIP, 4353 .clkr = { 4354 .enable_reg = 0x62028, 4355 .enable_mask = BIT(27), 4356 .hw.init = &(const struct clk_init_data) { 4357 .name = "gcc_pcie_3b_pipe_div2_clk", 4358 .parent_hws = (const struct clk_hw*[]) { 4359 &gcc_pcie_3b_pipe_div_clk_src.clkr.hw, 4360 }, 4361 .num_parents = 1, 4362 .flags = CLK_SET_RATE_PARENT, 4363 .ops = &clk_branch2_ops, 4364 }, 4365 }, 4366 }; 4367 4368 static struct clk_branch gcc_pcie_3b_slv_axi_clk = { 4369 .halt_reg = 0x94024, 4370 .halt_check = BRANCH_HALT_VOTED, 4371 .hwcg_reg = 0x94024, 4372 .hwcg_bit = 1, 4373 .clkr = { 4374 .enable_reg = 0x62028, 4375 .enable_mask = BIT(22), 4376 .hw.init = &(const struct clk_init_data) { 4377 .name = "gcc_pcie_3b_slv_axi_clk", 4378 .ops = &clk_branch2_ops, 4379 }, 4380 }, 4381 }; 4382 4383 static struct clk_branch gcc_pcie_3b_slv_q2a_axi_clk = { 4384 .halt_reg = 0x9401c, 4385 .halt_check = BRANCH_HALT_VOTED, 4386 .clkr = { 4387 .enable_reg = 0x62028, 4388 .enable_mask = BIT(21), 4389 .hw.init = &(const struct clk_init_data) { 4390 .name = "gcc_pcie_3b_slv_q2a_axi_clk", 4391 .ops = &clk_branch2_ops, 4392 }, 4393 }, 4394 }; 4395 4396 static struct clk_branch gcc_pcie_4_aux_clk = { 4397 .halt_reg = 0x88040, 4398 .halt_check = BRANCH_HALT_VOTED, 4399 .clkr = { 4400 .enable_reg = 0x62030, 4401 .enable_mask = BIT(17), 4402 .hw.init = &(const struct clk_init_data) { 4403 .name = "gcc_pcie_4_aux_clk", 4404 .parent_hws = (const struct clk_hw*[]) { 4405 &gcc_pcie_4_aux_clk_src.clkr.hw, 4406 }, 4407 .num_parents = 1, 4408 .flags = CLK_SET_RATE_PARENT, 4409 .ops = &clk_branch2_ops, 4410 }, 4411 }, 4412 }; 4413 4414 static struct clk_branch gcc_pcie_4_cfg_ahb_clk = { 4415 .halt_reg = 0xba4fc, 4416 .halt_check = BRANCH_HALT_VOTED, 4417 .hwcg_reg = 0xba4fc, 4418 .hwcg_bit = 1, 4419 .clkr = { 4420 .enable_reg = 0x62030, 4421 .enable_mask = BIT(16), 4422 .hw.init = &(const struct clk_init_data) { 4423 .name = "gcc_pcie_4_cfg_ahb_clk", 4424 .ops = &clk_branch2_ops, 4425 }, 4426 }, 4427 }; 4428 4429 static struct clk_branch gcc_pcie_4_mstr_axi_clk = { 4430 .halt_reg = 0x88030, 4431 .halt_check = BRANCH_HALT_SKIP, 4432 .hwcg_reg = 0x88030, 4433 .hwcg_bit = 1, 4434 .clkr = { 4435 .enable_reg = 0x62030, 4436 .enable_mask = BIT(15), 4437 .hw.init = &(const struct clk_init_data) { 4438 .name = "gcc_pcie_4_mstr_axi_clk", 4439 .ops = &clk_branch2_ops, 4440 }, 4441 }, 4442 }; 4443 4444 static struct clk_branch gcc_pcie_4_phy_rchng_clk = { 4445 .halt_reg = 0x88074, 4446 .halt_check = BRANCH_HALT_VOTED, 4447 .clkr = { 4448 .enable_reg = 0x62030, 4449 .enable_mask = BIT(20), 4450 .hw.init = &(const struct clk_init_data) { 4451 .name = "gcc_pcie_4_phy_rchng_clk", 4452 .parent_hws = (const struct clk_hw*[]) { 4453 &gcc_pcie_4_phy_rchng_clk_src.clkr.hw, 4454 }, 4455 .num_parents = 1, 4456 .flags = CLK_SET_RATE_PARENT, 4457 .ops = &clk_branch2_ops, 4458 }, 4459 }, 4460 }; 4461 4462 static struct clk_branch gcc_pcie_4_pipe_clk = { 4463 .halt_reg = 0x88050, 4464 .halt_check = BRANCH_HALT_SKIP, 4465 .clkr = { 4466 .enable_reg = 0x62030, 4467 .enable_mask = BIT(18), 4468 .hw.init = &(const struct clk_init_data) { 4469 .name = "gcc_pcie_4_pipe_clk", 4470 .parent_hws = (const struct clk_hw*[]) { 4471 &gcc_pcie_4_pipe_clk_src.clkr.hw, 4472 }, 4473 .num_parents = 1, 4474 .flags = CLK_SET_RATE_PARENT, 4475 .ops = &clk_branch2_ops, 4476 }, 4477 }, 4478 }; 4479 4480 static struct clk_branch gcc_pcie_4_pipe_div2_clk = { 4481 .halt_reg = 0x88064, 4482 .halt_check = BRANCH_HALT_SKIP, 4483 .clkr = { 4484 .enable_reg = 0x62030, 4485 .enable_mask = BIT(19), 4486 .hw.init = &(const struct clk_init_data) { 4487 .name = "gcc_pcie_4_pipe_div2_clk", 4488 .parent_hws = (const struct clk_hw*[]) { 4489 &gcc_pcie_4_pipe_div_clk_src.clkr.hw, 4490 }, 4491 .num_parents = 1, 4492 .flags = CLK_SET_RATE_PARENT, 4493 .ops = &clk_branch2_ops, 4494 }, 4495 }, 4496 }; 4497 4498 static struct clk_branch gcc_pcie_4_slv_axi_clk = { 4499 .halt_reg = 0x88020, 4500 .halt_check = BRANCH_HALT_VOTED, 4501 .hwcg_reg = 0x88020, 4502 .hwcg_bit = 1, 4503 .clkr = { 4504 .enable_reg = 0x62030, 4505 .enable_mask = BIT(14), 4506 .hw.init = &(const struct clk_init_data) { 4507 .name = "gcc_pcie_4_slv_axi_clk", 4508 .ops = &clk_branch2_ops, 4509 }, 4510 }, 4511 }; 4512 4513 static struct clk_branch gcc_pcie_4_slv_q2a_axi_clk = { 4514 .halt_reg = 0x8801c, 4515 .halt_check = BRANCH_HALT_VOTED, 4516 .clkr = { 4517 .enable_reg = 0x62030, 4518 .enable_mask = BIT(13), 4519 .hw.init = &(const struct clk_init_data) { 4520 .name = "gcc_pcie_4_slv_q2a_axi_clk", 4521 .ops = &clk_branch2_ops, 4522 }, 4523 }, 4524 }; 4525 4526 static struct clk_branch gcc_pcie_5_aux_clk = { 4527 .halt_reg = 0xc304c, 4528 .halt_check = BRANCH_HALT_VOTED, 4529 .clkr = { 4530 .enable_reg = 0x62030, 4531 .enable_mask = BIT(5), 4532 .hw.init = &(const struct clk_init_data) { 4533 .name = "gcc_pcie_5_aux_clk", 4534 .parent_hws = (const struct clk_hw*[]) { 4535 &gcc_pcie_5_aux_clk_src.clkr.hw, 4536 }, 4537 .num_parents = 1, 4538 .flags = CLK_SET_RATE_PARENT, 4539 .ops = &clk_branch2_ops, 4540 }, 4541 }, 4542 }; 4543 4544 static struct clk_branch gcc_pcie_5_cfg_ahb_clk = { 4545 .halt_reg = 0xba4f8, 4546 .halt_check = BRANCH_HALT_VOTED, 4547 .hwcg_reg = 0xba4f8, 4548 .hwcg_bit = 1, 4549 .clkr = { 4550 .enable_reg = 0x62030, 4551 .enable_mask = BIT(4), 4552 .hw.init = &(const struct clk_init_data) { 4553 .name = "gcc_pcie_5_cfg_ahb_clk", 4554 .ops = &clk_branch2_ops, 4555 }, 4556 }, 4557 }; 4558 4559 static struct clk_branch gcc_pcie_5_mstr_axi_clk = { 4560 .halt_reg = 0xc3038, 4561 .halt_check = BRANCH_HALT_SKIP, 4562 .hwcg_reg = 0xc3038, 4563 .hwcg_bit = 1, 4564 .clkr = { 4565 .enable_reg = 0x62030, 4566 .enable_mask = BIT(3), 4567 .hw.init = &(const struct clk_init_data) { 4568 .name = "gcc_pcie_5_mstr_axi_clk", 4569 .ops = &clk_branch2_ops, 4570 }, 4571 }, 4572 }; 4573 4574 static struct clk_branch gcc_pcie_5_phy_rchng_clk = { 4575 .halt_reg = 0xc3080, 4576 .halt_check = BRANCH_HALT_VOTED, 4577 .clkr = { 4578 .enable_reg = 0x62030, 4579 .enable_mask = BIT(8), 4580 .hw.init = &(const struct clk_init_data) { 4581 .name = "gcc_pcie_5_phy_rchng_clk", 4582 .parent_hws = (const struct clk_hw*[]) { 4583 &gcc_pcie_5_phy_rchng_clk_src.clkr.hw, 4584 }, 4585 .num_parents = 1, 4586 .flags = CLK_SET_RATE_PARENT, 4587 .ops = &clk_branch2_ops, 4588 }, 4589 }, 4590 }; 4591 4592 static struct clk_branch gcc_pcie_5_pipe_clk = { 4593 .halt_reg = 0xc305c, 4594 .halt_check = BRANCH_HALT_SKIP, 4595 .clkr = { 4596 .enable_reg = 0x62030, 4597 .enable_mask = BIT(6), 4598 .hw.init = &(const struct clk_init_data) { 4599 .name = "gcc_pcie_5_pipe_clk", 4600 .parent_hws = (const struct clk_hw*[]) { 4601 &gcc_pcie_5_pipe_clk_src.clkr.hw, 4602 }, 4603 .num_parents = 1, 4604 .flags = CLK_SET_RATE_PARENT, 4605 .ops = &clk_branch2_ops, 4606 }, 4607 }, 4608 }; 4609 4610 static struct clk_branch gcc_pcie_5_pipe_div2_clk = { 4611 .halt_reg = 0xc3070, 4612 .halt_check = BRANCH_HALT_SKIP, 4613 .clkr = { 4614 .enable_reg = 0x62030, 4615 .enable_mask = BIT(7), 4616 .hw.init = &(const struct clk_init_data) { 4617 .name = "gcc_pcie_5_pipe_div2_clk", 4618 .parent_hws = (const struct clk_hw*[]) { 4619 &gcc_pcie_5_pipe_div_clk_src.clkr.hw, 4620 }, 4621 .num_parents = 1, 4622 .flags = CLK_SET_RATE_PARENT, 4623 .ops = &clk_branch2_ops, 4624 }, 4625 }, 4626 }; 4627 4628 static struct clk_branch gcc_pcie_5_slv_axi_clk = { 4629 .halt_reg = 0xc3024, 4630 .halt_check = BRANCH_HALT_VOTED, 4631 .hwcg_reg = 0xc3024, 4632 .hwcg_bit = 1, 4633 .clkr = { 4634 .enable_reg = 0x62030, 4635 .enable_mask = BIT(2), 4636 .hw.init = &(const struct clk_init_data) { 4637 .name = "gcc_pcie_5_slv_axi_clk", 4638 .ops = &clk_branch2_ops, 4639 }, 4640 }, 4641 }; 4642 4643 static struct clk_branch gcc_pcie_5_slv_q2a_axi_clk = { 4644 .halt_reg = 0xc301c, 4645 .halt_check = BRANCH_HALT_VOTED, 4646 .clkr = { 4647 .enable_reg = 0x62030, 4648 .enable_mask = BIT(1), 4649 .hw.init = &(const struct clk_init_data) { 4650 .name = "gcc_pcie_5_slv_q2a_axi_clk", 4651 .ops = &clk_branch2_ops, 4652 }, 4653 }, 4654 }; 4655 4656 static struct clk_branch gcc_pcie_6_aux_clk = { 4657 .halt_reg = 0x8a040, 4658 .halt_check = BRANCH_HALT_VOTED, 4659 .clkr = { 4660 .enable_reg = 0x62030, 4661 .enable_mask = BIT(27), 4662 .hw.init = &(const struct clk_init_data) { 4663 .name = "gcc_pcie_6_aux_clk", 4664 .parent_hws = (const struct clk_hw*[]) { 4665 &gcc_pcie_6_aux_clk_src.clkr.hw, 4666 }, 4667 .num_parents = 1, 4668 .flags = CLK_SET_RATE_PARENT, 4669 .ops = &clk_branch2_ops, 4670 }, 4671 }, 4672 }; 4673 4674 static struct clk_branch gcc_pcie_6_cfg_ahb_clk = { 4675 .halt_reg = 0xba500, 4676 .halt_check = BRANCH_HALT_VOTED, 4677 .hwcg_reg = 0xba500, 4678 .hwcg_bit = 1, 4679 .clkr = { 4680 .enable_reg = 0x62030, 4681 .enable_mask = BIT(26), 4682 .hw.init = &(const struct clk_init_data) { 4683 .name = "gcc_pcie_6_cfg_ahb_clk", 4684 .ops = &clk_branch2_ops, 4685 }, 4686 }, 4687 }; 4688 4689 static struct clk_branch gcc_pcie_6_mstr_axi_clk = { 4690 .halt_reg = 0x8a030, 4691 .halt_check = BRANCH_HALT_SKIP, 4692 .hwcg_reg = 0x8a030, 4693 .hwcg_bit = 1, 4694 .clkr = { 4695 .enable_reg = 0x62030, 4696 .enable_mask = BIT(25), 4697 .hw.init = &(const struct clk_init_data) { 4698 .name = "gcc_pcie_6_mstr_axi_clk", 4699 .ops = &clk_branch2_ops, 4700 }, 4701 }, 4702 }; 4703 4704 static struct clk_branch gcc_pcie_6_phy_rchng_clk = { 4705 .halt_reg = 0x8a074, 4706 .halt_check = BRANCH_HALT_VOTED, 4707 .clkr = { 4708 .enable_reg = 0x62030, 4709 .enable_mask = BIT(30), 4710 .hw.init = &(const struct clk_init_data) { 4711 .name = "gcc_pcie_6_phy_rchng_clk", 4712 .parent_hws = (const struct clk_hw*[]) { 4713 &gcc_pcie_6_phy_rchng_clk_src.clkr.hw, 4714 }, 4715 .num_parents = 1, 4716 .flags = CLK_SET_RATE_PARENT, 4717 .ops = &clk_branch2_ops, 4718 }, 4719 }, 4720 }; 4721 4722 static struct clk_branch gcc_pcie_6_pipe_clk = { 4723 .halt_reg = 0x8a050, 4724 .halt_check = BRANCH_HALT_SKIP, 4725 .clkr = { 4726 .enable_reg = 0x62030, 4727 .enable_mask = BIT(28), 4728 .hw.init = &(const struct clk_init_data) { 4729 .name = "gcc_pcie_6_pipe_clk", 4730 .parent_hws = (const struct clk_hw*[]) { 4731 &gcc_pcie_6_pipe_clk_src.clkr.hw, 4732 }, 4733 .num_parents = 1, 4734 .flags = CLK_SET_RATE_PARENT, 4735 .ops = &clk_branch2_ops, 4736 }, 4737 }, 4738 }; 4739 4740 static struct clk_branch gcc_pcie_6_pipe_div2_clk = { 4741 .halt_reg = 0x8a064, 4742 .halt_check = BRANCH_HALT_SKIP, 4743 .clkr = { 4744 .enable_reg = 0x62030, 4745 .enable_mask = BIT(29), 4746 .hw.init = &(const struct clk_init_data) { 4747 .name = "gcc_pcie_6_pipe_div2_clk", 4748 .parent_hws = (const struct clk_hw*[]) { 4749 &gcc_pcie_6_pipe_div_clk_src.clkr.hw, 4750 }, 4751 .num_parents = 1, 4752 .flags = CLK_SET_RATE_PARENT, 4753 .ops = &clk_branch2_ops, 4754 }, 4755 }, 4756 }; 4757 4758 static struct clk_branch gcc_pcie_6_slv_axi_clk = { 4759 .halt_reg = 0x8a020, 4760 .halt_check = BRANCH_HALT_VOTED, 4761 .hwcg_reg = 0x8a020, 4762 .hwcg_bit = 1, 4763 .clkr = { 4764 .enable_reg = 0x62030, 4765 .enable_mask = BIT(24), 4766 .hw.init = &(const struct clk_init_data) { 4767 .name = "gcc_pcie_6_slv_axi_clk", 4768 .ops = &clk_branch2_ops, 4769 }, 4770 }, 4771 }; 4772 4773 static struct clk_branch gcc_pcie_6_slv_q2a_axi_clk = { 4774 .halt_reg = 0x8a01c, 4775 .halt_check = BRANCH_HALT_VOTED, 4776 .clkr = { 4777 .enable_reg = 0x62030, 4778 .enable_mask = BIT(23), 4779 .hw.init = &(const struct clk_init_data) { 4780 .name = "gcc_pcie_6_slv_q2a_axi_clk", 4781 .ops = &clk_branch2_ops, 4782 }, 4783 }, 4784 }; 4785 4786 static struct clk_branch gcc_pcie_noc_pwrctl_clk = { 4787 .halt_reg = 0xba2ac, 4788 .halt_check = BRANCH_HALT_VOTED, 4789 .clkr = { 4790 .enable_reg = 0x62008, 4791 .enable_mask = BIT(7), 4792 .hw.init = &(const struct clk_init_data) { 4793 .name = "gcc_pcie_noc_pwrctl_clk", 4794 .ops = &clk_branch2_ops, 4795 }, 4796 }, 4797 }; 4798 4799 static struct clk_branch gcc_pcie_noc_qosgen_extref_clk = { 4800 .halt_reg = 0xba2a8, 4801 .halt_check = BRANCH_HALT_VOTED, 4802 .clkr = { 4803 .enable_reg = 0x62008, 4804 .enable_mask = BIT(6), 4805 .hw.init = &(const struct clk_init_data) { 4806 .name = "gcc_pcie_noc_qosgen_extref_clk", 4807 .ops = &clk_branch2_ops, 4808 }, 4809 }, 4810 }; 4811 4812 static struct clk_branch gcc_pcie_noc_sf_center_clk = { 4813 .halt_reg = 0xba2b0, 4814 .halt_check = BRANCH_HALT_VOTED, 4815 .hwcg_reg = 0xba2b0, 4816 .hwcg_bit = 1, 4817 .clkr = { 4818 .enable_reg = 0x62008, 4819 .enable_mask = BIT(8), 4820 .hw.init = &(const struct clk_init_data) { 4821 .name = "gcc_pcie_noc_sf_center_clk", 4822 .ops = &clk_branch2_ops, 4823 }, 4824 }, 4825 }; 4826 4827 static struct clk_branch gcc_pcie_noc_slave_sf_east_clk = { 4828 .halt_reg = 0xba2b8, 4829 .halt_check = BRANCH_HALT_VOTED, 4830 .hwcg_reg = 0xba2b8, 4831 .hwcg_bit = 1, 4832 .clkr = { 4833 .enable_reg = 0x62008, 4834 .enable_mask = BIT(9), 4835 .hw.init = &(const struct clk_init_data) { 4836 .name = "gcc_pcie_noc_slave_sf_east_clk", 4837 .ops = &clk_branch2_ops, 4838 }, 4839 }, 4840 }; 4841 4842 static struct clk_branch gcc_pcie_noc_slave_sf_west_clk = { 4843 .halt_reg = 0xba2c0, 4844 .halt_check = BRANCH_HALT_VOTED, 4845 .hwcg_reg = 0xba2c0, 4846 .hwcg_bit = 1, 4847 .clkr = { 4848 .enable_reg = 0x62008, 4849 .enable_mask = BIT(10), 4850 .hw.init = &(const struct clk_init_data) { 4851 .name = "gcc_pcie_noc_slave_sf_west_clk", 4852 .ops = &clk_branch2_ops, 4853 }, 4854 }, 4855 }; 4856 4857 static struct clk_branch gcc_pcie_noc_tsctr_clk = { 4858 .halt_reg = 0xba2a4, 4859 .halt_check = BRANCH_HALT_VOTED, 4860 .hwcg_reg = 0xba2a4, 4861 .hwcg_bit = 1, 4862 .clkr = { 4863 .enable_reg = 0x62008, 4864 .enable_mask = BIT(5), 4865 .hw.init = &(const struct clk_init_data) { 4866 .name = "gcc_pcie_noc_tsctr_clk", 4867 .ops = &clk_branch2_ops, 4868 }, 4869 }, 4870 }; 4871 4872 static struct clk_branch gcc_pcie_phy_3a_aux_clk = { 4873 .halt_reg = 0x6c038, 4874 .halt_check = BRANCH_HALT_VOTED, 4875 .hwcg_reg = 0x6c038, 4876 .hwcg_bit = 1, 4877 .clkr = { 4878 .enable_reg = 0x62028, 4879 .enable_mask = BIT(19), 4880 .hw.init = &(const struct clk_init_data) { 4881 .name = "gcc_pcie_phy_3a_aux_clk", 4882 .parent_hws = (const struct clk_hw*[]) { 4883 &gcc_pcie_phy_3a_aux_clk_src.clkr.hw, 4884 }, 4885 .num_parents = 1, 4886 .flags = CLK_SET_RATE_PARENT, 4887 .ops = &clk_branch2_ops, 4888 }, 4889 }, 4890 }; 4891 4892 static struct clk_branch gcc_pcie_phy_3b_aux_clk = { 4893 .halt_reg = 0x75034, 4894 .halt_check = BRANCH_HALT_VOTED, 4895 .clkr = { 4896 .enable_reg = 0x62028, 4897 .enable_mask = BIT(31), 4898 .hw.init = &(const struct clk_init_data) { 4899 .name = "gcc_pcie_phy_3b_aux_clk", 4900 .parent_hws = (const struct clk_hw*[]) { 4901 &gcc_pcie_phy_3b_aux_clk_src.clkr.hw, 4902 }, 4903 .num_parents = 1, 4904 .flags = CLK_SET_RATE_PARENT, 4905 .ops = &clk_branch2_ops, 4906 }, 4907 }, 4908 }; 4909 4910 static struct clk_branch gcc_pcie_phy_4_aux_clk = { 4911 .halt_reg = 0xd3030, 4912 .halt_check = BRANCH_HALT_VOTED, 4913 .clkr = { 4914 .enable_reg = 0x62030, 4915 .enable_mask = BIT(21), 4916 .hw.init = &(const struct clk_init_data) { 4917 .name = "gcc_pcie_phy_4_aux_clk", 4918 .parent_hws = (const struct clk_hw*[]) { 4919 &gcc_pcie_phy_4_aux_clk_src.clkr.hw, 4920 }, 4921 .num_parents = 1, 4922 .flags = CLK_SET_RATE_PARENT, 4923 .ops = &clk_branch2_ops, 4924 }, 4925 }, 4926 }; 4927 4928 static struct clk_branch gcc_pcie_phy_5_aux_clk = { 4929 .halt_reg = 0xd2030, 4930 .halt_check = BRANCH_HALT_VOTED, 4931 .clkr = { 4932 .enable_reg = 0x62030, 4933 .enable_mask = BIT(11), 4934 .hw.init = &(const struct clk_init_data) { 4935 .name = "gcc_pcie_phy_5_aux_clk", 4936 .parent_hws = (const struct clk_hw*[]) { 4937 &gcc_pcie_phy_5_aux_clk_src.clkr.hw, 4938 }, 4939 .num_parents = 1, 4940 .flags = CLK_SET_RATE_PARENT, 4941 .ops = &clk_branch2_ops, 4942 }, 4943 }, 4944 }; 4945 4946 static struct clk_branch gcc_pcie_phy_6_aux_clk = { 4947 .halt_reg = 0xd4030, 4948 .halt_check = BRANCH_HALT_VOTED, 4949 .clkr = { 4950 .enable_reg = 0x62030, 4951 .enable_mask = BIT(31), 4952 .hw.init = &(const struct clk_init_data) { 4953 .name = "gcc_pcie_phy_6_aux_clk", 4954 .parent_hws = (const struct clk_hw*[]) { 4955 &gcc_pcie_phy_6_aux_clk_src.clkr.hw, 4956 }, 4957 .num_parents = 1, 4958 .flags = CLK_SET_RATE_PARENT, 4959 .ops = &clk_branch2_ops, 4960 }, 4961 }, 4962 }; 4963 4964 static struct clk_branch gcc_pcie_rscc_cfg_ahb_clk = { 4965 .halt_reg = 0xb8004, 4966 .halt_check = BRANCH_HALT_VOTED, 4967 .hwcg_reg = 0xb8004, 4968 .hwcg_bit = 1, 4969 .clkr = { 4970 .enable_reg = 0x62038, 4971 .enable_mask = BIT(2), 4972 .hw.init = &(const struct clk_init_data) { 4973 .name = "gcc_pcie_rscc_cfg_ahb_clk", 4974 .ops = &clk_branch2_ops, 4975 }, 4976 }, 4977 }; 4978 4979 static struct clk_branch gcc_pcie_rscc_xo_clk = { 4980 .halt_reg = 0xb8008, 4981 .halt_check = BRANCH_HALT_VOTED, 4982 .clkr = { 4983 .enable_reg = 0x62038, 4984 .enable_mask = BIT(3), 4985 .hw.init = &(const struct clk_init_data) { 4986 .name = "gcc_pcie_rscc_xo_clk", 4987 .ops = &clk_branch2_ops, 4988 }, 4989 }, 4990 }; 4991 4992 static struct clk_branch gcc_pdm2_clk = { 4993 .halt_reg = 0x3300c, 4994 .halt_check = BRANCH_HALT, 4995 .clkr = { 4996 .enable_reg = 0x3300c, 4997 .enable_mask = BIT(0), 4998 .hw.init = &(const struct clk_init_data) { 4999 .name = "gcc_pdm2_clk", 5000 .parent_hws = (const struct clk_hw*[]) { 5001 &gcc_pdm2_clk_src.clkr.hw, 5002 }, 5003 .num_parents = 1, 5004 .flags = CLK_SET_RATE_PARENT, 5005 .ops = &clk_branch2_ops, 5006 }, 5007 }, 5008 }; 5009 5010 static struct clk_branch gcc_pdm_ahb_clk = { 5011 .halt_reg = 0x33004, 5012 .halt_check = BRANCH_HALT_VOTED, 5013 .hwcg_reg = 0x33004, 5014 .hwcg_bit = 1, 5015 .clkr = { 5016 .enable_reg = 0x33004, 5017 .enable_mask = BIT(0), 5018 .hw.init = &(const struct clk_init_data) { 5019 .name = "gcc_pdm_ahb_clk", 5020 .ops = &clk_branch2_ops, 5021 }, 5022 }, 5023 }; 5024 5025 static struct clk_branch gcc_pdm_xo4_clk = { 5026 .halt_reg = 0x33008, 5027 .halt_check = BRANCH_HALT, 5028 .clkr = { 5029 .enable_reg = 0x33008, 5030 .enable_mask = BIT(0), 5031 .hw.init = &(const struct clk_init_data) { 5032 .name = "gcc_pdm_xo4_clk", 5033 .ops = &clk_branch2_ops, 5034 }, 5035 }, 5036 }; 5037 5038 static struct clk_branch gcc_qmip_av1e_ahb_clk = { 5039 .halt_reg = 0x9b048, 5040 .halt_check = BRANCH_HALT_VOTED, 5041 .hwcg_reg = 0x9b048, 5042 .hwcg_bit = 1, 5043 .clkr = { 5044 .enable_reg = 0x9b048, 5045 .enable_mask = BIT(0), 5046 .hw.init = &(const struct clk_init_data) { 5047 .name = "gcc_qmip_av1e_ahb_clk", 5048 .ops = &clk_branch2_ops, 5049 }, 5050 }, 5051 }; 5052 5053 static struct clk_branch gcc_qmip_camera_cmd_ahb_clk = { 5054 .halt_reg = 0x26010, 5055 .halt_check = BRANCH_HALT_VOTED, 5056 .hwcg_reg = 0x26010, 5057 .hwcg_bit = 1, 5058 .clkr = { 5059 .enable_reg = 0x26010, 5060 .enable_mask = BIT(0), 5061 .hw.init = &(const struct clk_init_data) { 5062 .name = "gcc_qmip_camera_cmd_ahb_clk", 5063 .ops = &clk_branch2_ops, 5064 }, 5065 }, 5066 }; 5067 5068 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 5069 .halt_reg = 0x26008, 5070 .halt_check = BRANCH_HALT_VOTED, 5071 .hwcg_reg = 0x26008, 5072 .hwcg_bit = 1, 5073 .clkr = { 5074 .enable_reg = 0x26008, 5075 .enable_mask = BIT(0), 5076 .hw.init = &(const struct clk_init_data) { 5077 .name = "gcc_qmip_camera_nrt_ahb_clk", 5078 .ops = &clk_branch2_ops, 5079 }, 5080 }, 5081 }; 5082 5083 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 5084 .halt_reg = 0x2600c, 5085 .halt_check = BRANCH_HALT_VOTED, 5086 .hwcg_reg = 0x2600c, 5087 .hwcg_bit = 1, 5088 .clkr = { 5089 .enable_reg = 0x2600c, 5090 .enable_mask = BIT(0), 5091 .hw.init = &(const struct clk_init_data) { 5092 .name = "gcc_qmip_camera_rt_ahb_clk", 5093 .ops = &clk_branch2_ops, 5094 }, 5095 }, 5096 }; 5097 5098 static struct clk_branch gcc_qmip_gpu_ahb_clk = { 5099 .halt_reg = 0x71008, 5100 .halt_check = BRANCH_HALT_VOTED, 5101 .hwcg_reg = 0x71008, 5102 .hwcg_bit = 1, 5103 .clkr = { 5104 .enable_reg = 0x71008, 5105 .enable_mask = BIT(0), 5106 .hw.init = &(const struct clk_init_data) { 5107 .name = "gcc_qmip_gpu_ahb_clk", 5108 .ops = &clk_branch2_ops, 5109 }, 5110 }, 5111 }; 5112 5113 static struct clk_branch gcc_qmip_pcie_3a_ahb_clk = { 5114 .halt_reg = 0xdc018, 5115 .halt_check = BRANCH_HALT_VOTED, 5116 .hwcg_reg = 0xdc018, 5117 .hwcg_bit = 1, 5118 .clkr = { 5119 .enable_reg = 0x62028, 5120 .enable_mask = BIT(11), 5121 .hw.init = &(const struct clk_init_data) { 5122 .name = "gcc_qmip_pcie_3a_ahb_clk", 5123 .ops = &clk_branch2_ops, 5124 }, 5125 }, 5126 }; 5127 5128 static struct clk_branch gcc_qmip_pcie_3b_ahb_clk = { 5129 .halt_reg = 0x94018, 5130 .halt_check = BRANCH_HALT_VOTED, 5131 .hwcg_reg = 0x94018, 5132 .hwcg_bit = 1, 5133 .clkr = { 5134 .enable_reg = 0x62028, 5135 .enable_mask = BIT(20), 5136 .hw.init = &(const struct clk_init_data) { 5137 .name = "gcc_qmip_pcie_3b_ahb_clk", 5138 .ops = &clk_branch2_ops, 5139 }, 5140 }, 5141 }; 5142 5143 static struct clk_branch gcc_qmip_pcie_4_ahb_clk = { 5144 .halt_reg = 0x88018, 5145 .halt_check = BRANCH_HALT_VOTED, 5146 .hwcg_reg = 0x88018, 5147 .hwcg_bit = 1, 5148 .clkr = { 5149 .enable_reg = 0x62030, 5150 .enable_mask = BIT(12), 5151 .hw.init = &(const struct clk_init_data) { 5152 .name = "gcc_qmip_pcie_4_ahb_clk", 5153 .ops = &clk_branch2_ops, 5154 }, 5155 }, 5156 }; 5157 5158 static struct clk_branch gcc_qmip_pcie_5_ahb_clk = { 5159 .halt_reg = 0xc3018, 5160 .halt_check = BRANCH_HALT_VOTED, 5161 .hwcg_reg = 0xc3018, 5162 .hwcg_bit = 1, 5163 .clkr = { 5164 .enable_reg = 0x62030, 5165 .enable_mask = BIT(0), 5166 .hw.init = &(const struct clk_init_data) { 5167 .name = "gcc_qmip_pcie_5_ahb_clk", 5168 .ops = &clk_branch2_ops, 5169 }, 5170 }, 5171 }; 5172 5173 static struct clk_branch gcc_qmip_pcie_6_ahb_clk = { 5174 .halt_reg = 0x8a018, 5175 .halt_check = BRANCH_HALT_VOTED, 5176 .hwcg_reg = 0x8a018, 5177 .hwcg_bit = 1, 5178 .clkr = { 5179 .enable_reg = 0x62030, 5180 .enable_mask = BIT(22), 5181 .hw.init = &(const struct clk_init_data) { 5182 .name = "gcc_qmip_pcie_6_ahb_clk", 5183 .ops = &clk_branch2_ops, 5184 }, 5185 }, 5186 }; 5187 5188 static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = { 5189 .halt_reg = 0x32018, 5190 .halt_check = BRANCH_HALT_VOTED, 5191 .hwcg_reg = 0x32018, 5192 .hwcg_bit = 1, 5193 .clkr = { 5194 .enable_reg = 0x32018, 5195 .enable_mask = BIT(0), 5196 .hw.init = &(const struct clk_init_data) { 5197 .name = "gcc_qmip_video_cv_cpu_ahb_clk", 5198 .ops = &clk_branch2_ops, 5199 }, 5200 }, 5201 }; 5202 5203 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 5204 .halt_reg = 0x32008, 5205 .halt_check = BRANCH_HALT_VOTED, 5206 .hwcg_reg = 0x32008, 5207 .hwcg_bit = 1, 5208 .clkr = { 5209 .enable_reg = 0x32008, 5210 .enable_mask = BIT(0), 5211 .hw.init = &(const struct clk_init_data) { 5212 .name = "gcc_qmip_video_cvp_ahb_clk", 5213 .ops = &clk_branch2_ops, 5214 }, 5215 }, 5216 }; 5217 5218 static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = { 5219 .halt_reg = 0x32014, 5220 .halt_check = BRANCH_HALT_VOTED, 5221 .hwcg_reg = 0x32014, 5222 .hwcg_bit = 1, 5223 .clkr = { 5224 .enable_reg = 0x32014, 5225 .enable_mask = BIT(0), 5226 .hw.init = &(const struct clk_init_data) { 5227 .name = "gcc_qmip_video_v_cpu_ahb_clk", 5228 .ops = &clk_branch2_ops, 5229 }, 5230 }, 5231 }; 5232 5233 static struct clk_branch gcc_qmip_video_vcodec1_ahb_clk = { 5234 .halt_reg = 0x32010, 5235 .halt_check = BRANCH_HALT_VOTED, 5236 .hwcg_reg = 0x32010, 5237 .hwcg_bit = 1, 5238 .clkr = { 5239 .enable_reg = 0x32010, 5240 .enable_mask = BIT(0), 5241 .hw.init = &(const struct clk_init_data) { 5242 .name = "gcc_qmip_video_vcodec1_ahb_clk", 5243 .ops = &clk_branch2_ops, 5244 }, 5245 }, 5246 }; 5247 5248 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 5249 .halt_reg = 0x3200c, 5250 .halt_check = BRANCH_HALT_VOTED, 5251 .hwcg_reg = 0x3200c, 5252 .hwcg_bit = 1, 5253 .clkr = { 5254 .enable_reg = 0x3200c, 5255 .enable_mask = BIT(0), 5256 .hw.init = &(const struct clk_init_data) { 5257 .name = "gcc_qmip_video_vcodec_ahb_clk", 5258 .ops = &clk_branch2_ops, 5259 }, 5260 }, 5261 }; 5262 5263 static struct clk_branch gcc_qupv3_oob_core_2x_clk = { 5264 .halt_reg = 0xc5040, 5265 .halt_check = BRANCH_HALT_VOTED, 5266 .clkr = { 5267 .enable_reg = 0x62018, 5268 .enable_mask = BIT(5), 5269 .hw.init = &(const struct clk_init_data) { 5270 .name = "gcc_qupv3_oob_core_2x_clk", 5271 .ops = &clk_branch2_ops, 5272 }, 5273 }, 5274 }; 5275 5276 static struct clk_branch gcc_qupv3_oob_core_clk = { 5277 .halt_reg = 0xc502c, 5278 .halt_check = BRANCH_HALT_VOTED, 5279 .clkr = { 5280 .enable_reg = 0x62018, 5281 .enable_mask = BIT(4), 5282 .hw.init = &(const struct clk_init_data) { 5283 .name = "gcc_qupv3_oob_core_clk", 5284 .ops = &clk_branch2_ops, 5285 }, 5286 }, 5287 }; 5288 5289 static struct clk_branch gcc_qupv3_oob_m_ahb_clk = { 5290 .halt_reg = 0xe7004, 5291 .halt_check = BRANCH_HALT_VOTED, 5292 .hwcg_reg = 0xe7004, 5293 .hwcg_bit = 1, 5294 .clkr = { 5295 .enable_reg = 0xe7004, 5296 .enable_mask = BIT(0), 5297 .hw.init = &(const struct clk_init_data) { 5298 .name = "gcc_qupv3_oob_m_ahb_clk", 5299 .ops = &clk_branch2_ops, 5300 }, 5301 }, 5302 }; 5303 5304 static struct clk_branch gcc_qupv3_oob_qspi_s0_clk = { 5305 .halt_reg = 0xe7040, 5306 .halt_check = BRANCH_HALT_VOTED, 5307 .clkr = { 5308 .enable_reg = 0x62018, 5309 .enable_mask = BIT(9), 5310 .hw.init = &(const struct clk_init_data) { 5311 .name = "gcc_qupv3_oob_qspi_s0_clk", 5312 .parent_hws = (const struct clk_hw*[]) { 5313 &gcc_qupv3_oob_qspi_s0_clk_src.clkr.hw, 5314 }, 5315 .num_parents = 1, 5316 .flags = CLK_SET_RATE_PARENT, 5317 .ops = &clk_branch2_ops, 5318 }, 5319 }, 5320 }; 5321 5322 static struct clk_branch gcc_qupv3_oob_qspi_s1_clk = { 5323 .halt_reg = 0xe729c, 5324 .halt_check = BRANCH_HALT_VOTED, 5325 .clkr = { 5326 .enable_reg = 0x62018, 5327 .enable_mask = BIT(10), 5328 .hw.init = &(const struct clk_init_data) { 5329 .name = "gcc_qupv3_oob_qspi_s1_clk", 5330 .parent_hws = (const struct clk_hw*[]) { 5331 &gcc_qupv3_oob_qspi_s1_clk_src.clkr.hw, 5332 }, 5333 .num_parents = 1, 5334 .flags = CLK_SET_RATE_PARENT, 5335 .ops = &clk_branch2_ops, 5336 }, 5337 }, 5338 }; 5339 5340 static struct clk_branch gcc_qupv3_oob_s0_clk = { 5341 .halt_reg = 0xe7014, 5342 .halt_check = BRANCH_HALT_VOTED, 5343 .clkr = { 5344 .enable_reg = 0x62018, 5345 .enable_mask = BIT(6), 5346 .hw.init = &(const struct clk_init_data) { 5347 .name = "gcc_qupv3_oob_s0_clk", 5348 .parent_hws = (const struct clk_hw*[]) { 5349 &gcc_qupv3_oob_s0_clk_src.clkr.hw, 5350 }, 5351 .num_parents = 1, 5352 .flags = CLK_SET_RATE_PARENT, 5353 .ops = &clk_branch2_ops, 5354 }, 5355 }, 5356 }; 5357 5358 static struct clk_branch gcc_qupv3_oob_s1_clk = { 5359 .halt_reg = 0xe7028, 5360 .halt_check = BRANCH_HALT_VOTED, 5361 .clkr = { 5362 .enable_reg = 0x62018, 5363 .enable_mask = BIT(7), 5364 .hw.init = &(const struct clk_init_data) { 5365 .name = "gcc_qupv3_oob_s1_clk", 5366 .parent_hws = (const struct clk_hw*[]) { 5367 &gcc_qupv3_oob_s1_clk_src.clkr.hw, 5368 }, 5369 .num_parents = 1, 5370 .flags = CLK_SET_RATE_PARENT, 5371 .ops = &clk_branch2_ops, 5372 }, 5373 }, 5374 }; 5375 5376 static struct clk_branch gcc_qupv3_oob_s_ahb_clk = { 5377 .halt_reg = 0xc5028, 5378 .halt_check = BRANCH_HALT_VOTED, 5379 .hwcg_reg = 0xc5028, 5380 .hwcg_bit = 1, 5381 .clkr = { 5382 .enable_reg = 0x62018, 5383 .enable_mask = BIT(3), 5384 .hw.init = &(const struct clk_init_data) { 5385 .name = "gcc_qupv3_oob_s_ahb_clk", 5386 .ops = &clk_branch2_ops, 5387 }, 5388 }, 5389 }; 5390 5391 static struct clk_branch gcc_qupv3_oob_tcxo_clk = { 5392 .halt_reg = 0xe703c, 5393 .halt_check = BRANCH_HALT_VOTED, 5394 .clkr = { 5395 .enable_reg = 0x62018, 5396 .enable_mask = BIT(8), 5397 .hw.init = &(const struct clk_init_data) { 5398 .name = "gcc_qupv3_oob_tcxo_clk", 5399 .ops = &clk_branch2_ops, 5400 }, 5401 }, 5402 }; 5403 5404 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { 5405 .halt_reg = 0xc5448, 5406 .halt_check = BRANCH_HALT_VOTED, 5407 .clkr = { 5408 .enable_reg = 0x62020, 5409 .enable_mask = BIT(12), 5410 .hw.init = &(const struct clk_init_data) { 5411 .name = "gcc_qupv3_wrap0_core_2x_clk", 5412 .ops = &clk_branch2_ops, 5413 }, 5414 }, 5415 }; 5416 5417 static struct clk_branch gcc_qupv3_wrap0_core_clk = { 5418 .halt_reg = 0xc5434, 5419 .halt_check = BRANCH_HALT_VOTED, 5420 .clkr = { 5421 .enable_reg = 0x62020, 5422 .enable_mask = BIT(11), 5423 .hw.init = &(const struct clk_init_data) { 5424 .name = "gcc_qupv3_wrap0_core_clk", 5425 .ops = &clk_branch2_ops, 5426 }, 5427 }, 5428 }; 5429 5430 static struct clk_branch gcc_qupv3_wrap0_qspi_s2_clk = { 5431 .halt_reg = 0x2879c, 5432 .halt_check = BRANCH_HALT_VOTED, 5433 .clkr = { 5434 .enable_reg = 0x62020, 5435 .enable_mask = BIT(22), 5436 .hw.init = &(const struct clk_init_data) { 5437 .name = "gcc_qupv3_wrap0_qspi_s2_clk", 5438 .parent_hws = (const struct clk_hw*[]) { 5439 &gcc_qupv3_wrap0_qspi_s2_clk_src.clkr.hw, 5440 }, 5441 .num_parents = 1, 5442 .flags = CLK_SET_RATE_PARENT, 5443 .ops = &clk_branch2_ops, 5444 }, 5445 }, 5446 }; 5447 5448 static struct clk_branch gcc_qupv3_wrap0_qspi_s3_clk = { 5449 .halt_reg = 0x288cc, 5450 .halt_check = BRANCH_HALT_VOTED, 5451 .clkr = { 5452 .enable_reg = 0x62020, 5453 .enable_mask = BIT(23), 5454 .hw.init = &(const struct clk_init_data) { 5455 .name = "gcc_qupv3_wrap0_qspi_s3_clk", 5456 .parent_hws = (const struct clk_hw*[]) { 5457 &gcc_qupv3_wrap0_qspi_s3_clk_src.clkr.hw, 5458 }, 5459 .num_parents = 1, 5460 .flags = CLK_SET_RATE_PARENT, 5461 .ops = &clk_branch2_ops, 5462 }, 5463 }, 5464 }; 5465 5466 static struct clk_branch gcc_qupv3_wrap0_qspi_s6_clk = { 5467 .halt_reg = 0x28798, 5468 .halt_check = BRANCH_HALT_VOTED, 5469 .clkr = { 5470 .enable_reg = 0x62020, 5471 .enable_mask = BIT(21), 5472 .hw.init = &(const struct clk_init_data) { 5473 .name = "gcc_qupv3_wrap0_qspi_s6_clk", 5474 .parent_hws = (const struct clk_hw*[]) { 5475 &gcc_qupv3_wrap0_qspi_s6_clk_src.clkr.hw, 5476 }, 5477 .num_parents = 1, 5478 .flags = CLK_SET_RATE_PARENT, 5479 .ops = &clk_branch2_ops, 5480 }, 5481 }, 5482 }; 5483 5484 static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 5485 .halt_reg = 0x28004, 5486 .halt_check = BRANCH_HALT_VOTED, 5487 .clkr = { 5488 .enable_reg = 0x62020, 5489 .enable_mask = BIT(13), 5490 .hw.init = &(const struct clk_init_data) { 5491 .name = "gcc_qupv3_wrap0_s0_clk", 5492 .parent_hws = (const struct clk_hw*[]) { 5493 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, 5494 }, 5495 .num_parents = 1, 5496 .flags = CLK_SET_RATE_PARENT, 5497 .ops = &clk_branch2_ops, 5498 }, 5499 }, 5500 }; 5501 5502 static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 5503 .halt_reg = 0x28140, 5504 .halt_check = BRANCH_HALT_VOTED, 5505 .clkr = { 5506 .enable_reg = 0x62020, 5507 .enable_mask = BIT(14), 5508 .hw.init = &(const struct clk_init_data) { 5509 .name = "gcc_qupv3_wrap0_s1_clk", 5510 .parent_hws = (const struct clk_hw*[]) { 5511 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, 5512 }, 5513 .num_parents = 1, 5514 .flags = CLK_SET_RATE_PARENT, 5515 .ops = &clk_branch2_ops, 5516 }, 5517 }, 5518 }; 5519 5520 static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 5521 .halt_reg = 0x2827c, 5522 .halt_check = BRANCH_HALT_VOTED, 5523 .clkr = { 5524 .enable_reg = 0x62020, 5525 .enable_mask = BIT(15), 5526 .hw.init = &(const struct clk_init_data) { 5527 .name = "gcc_qupv3_wrap0_s2_clk", 5528 .parent_hws = (const struct clk_hw*[]) { 5529 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, 5530 }, 5531 .num_parents = 1, 5532 .flags = CLK_SET_RATE_PARENT, 5533 .ops = &clk_branch2_ops, 5534 }, 5535 }, 5536 }; 5537 5538 static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 5539 .halt_reg = 0x28290, 5540 .halt_check = BRANCH_HALT_VOTED, 5541 .clkr = { 5542 .enable_reg = 0x62020, 5543 .enable_mask = BIT(16), 5544 .hw.init = &(const struct clk_init_data) { 5545 .name = "gcc_qupv3_wrap0_s3_clk", 5546 .parent_hws = (const struct clk_hw*[]) { 5547 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, 5548 }, 5549 .num_parents = 1, 5550 .flags = CLK_SET_RATE_PARENT, 5551 .ops = &clk_branch2_ops, 5552 }, 5553 }, 5554 }; 5555 5556 static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 5557 .halt_reg = 0x282a4, 5558 .halt_check = BRANCH_HALT_VOTED, 5559 .clkr = { 5560 .enable_reg = 0x62020, 5561 .enable_mask = BIT(17), 5562 .hw.init = &(const struct clk_init_data) { 5563 .name = "gcc_qupv3_wrap0_s4_clk", 5564 .parent_hws = (const struct clk_hw*[]) { 5565 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, 5566 }, 5567 .num_parents = 1, 5568 .flags = CLK_SET_RATE_PARENT, 5569 .ops = &clk_branch2_ops, 5570 }, 5571 }, 5572 }; 5573 5574 static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 5575 .halt_reg = 0x283e0, 5576 .halt_check = BRANCH_HALT_VOTED, 5577 .clkr = { 5578 .enable_reg = 0x62020, 5579 .enable_mask = BIT(18), 5580 .hw.init = &(const struct clk_init_data) { 5581 .name = "gcc_qupv3_wrap0_s5_clk", 5582 .parent_hws = (const struct clk_hw*[]) { 5583 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, 5584 }, 5585 .num_parents = 1, 5586 .flags = CLK_SET_RATE_PARENT, 5587 .ops = &clk_branch2_ops, 5588 }, 5589 }, 5590 }; 5591 5592 static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 5593 .halt_reg = 0x2851c, 5594 .halt_check = BRANCH_HALT_VOTED, 5595 .clkr = { 5596 .enable_reg = 0x62020, 5597 .enable_mask = BIT(19), 5598 .hw.init = &(const struct clk_init_data) { 5599 .name = "gcc_qupv3_wrap0_s6_clk", 5600 .parent_hws = (const struct clk_hw*[]) { 5601 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, 5602 }, 5603 .num_parents = 1, 5604 .flags = CLK_SET_RATE_PARENT, 5605 .ops = &clk_branch2_ops, 5606 }, 5607 }, 5608 }; 5609 5610 static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 5611 .halt_reg = 0x28530, 5612 .halt_check = BRANCH_HALT_VOTED, 5613 .clkr = { 5614 .enable_reg = 0x62020, 5615 .enable_mask = BIT(20), 5616 .hw.init = &(const struct clk_init_data) { 5617 .name = "gcc_qupv3_wrap0_s7_clk", 5618 .parent_hws = (const struct clk_hw*[]) { 5619 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, 5620 }, 5621 .num_parents = 1, 5622 .flags = CLK_SET_RATE_PARENT, 5623 .ops = &clk_branch2_ops, 5624 }, 5625 }, 5626 }; 5627 5628 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 5629 .halt_reg = 0xc5198, 5630 .halt_check = BRANCH_HALT_VOTED, 5631 .clkr = { 5632 .enable_reg = 0x62018, 5633 .enable_mask = BIT(14), 5634 .hw.init = &(const struct clk_init_data) { 5635 .name = "gcc_qupv3_wrap1_core_2x_clk", 5636 .ops = &clk_branch2_ops, 5637 }, 5638 }, 5639 }; 5640 5641 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 5642 .halt_reg = 0xc5184, 5643 .halt_check = BRANCH_HALT_VOTED, 5644 .clkr = { 5645 .enable_reg = 0x62018, 5646 .enable_mask = BIT(13), 5647 .hw.init = &(const struct clk_init_data) { 5648 .name = "gcc_qupv3_wrap1_core_clk", 5649 .ops = &clk_branch2_ops, 5650 }, 5651 }, 5652 }; 5653 5654 static struct clk_branch gcc_qupv3_wrap1_qspi_s2_clk = { 5655 .halt_reg = 0xb379c, 5656 .halt_check = BRANCH_HALT_VOTED, 5657 .clkr = { 5658 .enable_reg = 0x62018, 5659 .enable_mask = BIT(24), 5660 .hw.init = &(const struct clk_init_data) { 5661 .name = "gcc_qupv3_wrap1_qspi_s2_clk", 5662 .parent_hws = (const struct clk_hw*[]) { 5663 &gcc_qupv3_wrap1_qspi_s2_clk_src.clkr.hw, 5664 }, 5665 .num_parents = 1, 5666 .flags = CLK_SET_RATE_PARENT, 5667 .ops = &clk_branch2_ops, 5668 }, 5669 }, 5670 }; 5671 5672 static struct clk_branch gcc_qupv3_wrap1_qspi_s3_clk = { 5673 .halt_reg = 0xb38cc, 5674 .halt_check = BRANCH_HALT_VOTED, 5675 .clkr = { 5676 .enable_reg = 0x62018, 5677 .enable_mask = BIT(25), 5678 .hw.init = &(const struct clk_init_data) { 5679 .name = "gcc_qupv3_wrap1_qspi_s3_clk", 5680 .parent_hws = (const struct clk_hw*[]) { 5681 &gcc_qupv3_wrap1_qspi_s3_clk_src.clkr.hw, 5682 }, 5683 .num_parents = 1, 5684 .flags = CLK_SET_RATE_PARENT, 5685 .ops = &clk_branch2_ops, 5686 }, 5687 }, 5688 }; 5689 5690 static struct clk_branch gcc_qupv3_wrap1_qspi_s6_clk = { 5691 .halt_reg = 0xb3798, 5692 .halt_check = BRANCH_HALT_VOTED, 5693 .clkr = { 5694 .enable_reg = 0x62018, 5695 .enable_mask = BIT(23), 5696 .hw.init = &(const struct clk_init_data) { 5697 .name = "gcc_qupv3_wrap1_qspi_s6_clk", 5698 .parent_hws = (const struct clk_hw*[]) { 5699 &gcc_qupv3_wrap1_qspi_s6_clk_src.clkr.hw, 5700 }, 5701 .num_parents = 1, 5702 .flags = CLK_SET_RATE_PARENT, 5703 .ops = &clk_branch2_ops, 5704 }, 5705 }, 5706 }; 5707 5708 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 5709 .halt_reg = 0xb3004, 5710 .halt_check = BRANCH_HALT_VOTED, 5711 .clkr = { 5712 .enable_reg = 0x62018, 5713 .enable_mask = BIT(15), 5714 .hw.init = &(const struct clk_init_data) { 5715 .name = "gcc_qupv3_wrap1_s0_clk", 5716 .parent_hws = (const struct clk_hw*[]) { 5717 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 5718 }, 5719 .num_parents = 1, 5720 .flags = CLK_SET_RATE_PARENT, 5721 .ops = &clk_branch2_ops, 5722 }, 5723 }, 5724 }; 5725 5726 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 5727 .halt_reg = 0xb3140, 5728 .halt_check = BRANCH_HALT_VOTED, 5729 .clkr = { 5730 .enable_reg = 0x62018, 5731 .enable_mask = BIT(16), 5732 .hw.init = &(const struct clk_init_data) { 5733 .name = "gcc_qupv3_wrap1_s1_clk", 5734 .parent_hws = (const struct clk_hw*[]) { 5735 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 5736 }, 5737 .num_parents = 1, 5738 .flags = CLK_SET_RATE_PARENT, 5739 .ops = &clk_branch2_ops, 5740 }, 5741 }, 5742 }; 5743 5744 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 5745 .halt_reg = 0xb327c, 5746 .halt_check = BRANCH_HALT_VOTED, 5747 .clkr = { 5748 .enable_reg = 0x62018, 5749 .enable_mask = BIT(17), 5750 .hw.init = &(const struct clk_init_data) { 5751 .name = "gcc_qupv3_wrap1_s2_clk", 5752 .parent_hws = (const struct clk_hw*[]) { 5753 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 5754 }, 5755 .num_parents = 1, 5756 .flags = CLK_SET_RATE_PARENT, 5757 .ops = &clk_branch2_ops, 5758 }, 5759 }, 5760 }; 5761 5762 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 5763 .halt_reg = 0xb3290, 5764 .halt_check = BRANCH_HALT_VOTED, 5765 .clkr = { 5766 .enable_reg = 0x62018, 5767 .enable_mask = BIT(18), 5768 .hw.init = &(const struct clk_init_data) { 5769 .name = "gcc_qupv3_wrap1_s3_clk", 5770 .parent_hws = (const struct clk_hw*[]) { 5771 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 5772 }, 5773 .num_parents = 1, 5774 .flags = CLK_SET_RATE_PARENT, 5775 .ops = &clk_branch2_ops, 5776 }, 5777 }, 5778 }; 5779 5780 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 5781 .halt_reg = 0xb32a4, 5782 .halt_check = BRANCH_HALT_VOTED, 5783 .clkr = { 5784 .enable_reg = 0x62018, 5785 .enable_mask = BIT(19), 5786 .hw.init = &(const struct clk_init_data) { 5787 .name = "gcc_qupv3_wrap1_s4_clk", 5788 .parent_hws = (const struct clk_hw*[]) { 5789 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 5790 }, 5791 .num_parents = 1, 5792 .flags = CLK_SET_RATE_PARENT, 5793 .ops = &clk_branch2_ops, 5794 }, 5795 }, 5796 }; 5797 5798 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 5799 .halt_reg = 0xb33e0, 5800 .halt_check = BRANCH_HALT_VOTED, 5801 .clkr = { 5802 .enable_reg = 0x62018, 5803 .enable_mask = BIT(20), 5804 .hw.init = &(const struct clk_init_data) { 5805 .name = "gcc_qupv3_wrap1_s5_clk", 5806 .parent_hws = (const struct clk_hw*[]) { 5807 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 5808 }, 5809 .num_parents = 1, 5810 .flags = CLK_SET_RATE_PARENT, 5811 .ops = &clk_branch2_ops, 5812 }, 5813 }, 5814 }; 5815 5816 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 5817 .halt_reg = 0xb351c, 5818 .halt_check = BRANCH_HALT_VOTED, 5819 .clkr = { 5820 .enable_reg = 0x62018, 5821 .enable_mask = BIT(21), 5822 .hw.init = &(const struct clk_init_data) { 5823 .name = "gcc_qupv3_wrap1_s6_clk", 5824 .parent_hws = (const struct clk_hw*[]) { 5825 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 5826 }, 5827 .num_parents = 1, 5828 .flags = CLK_SET_RATE_PARENT, 5829 .ops = &clk_branch2_ops, 5830 }, 5831 }, 5832 }; 5833 5834 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 5835 .halt_reg = 0xb3530, 5836 .halt_check = BRANCH_HALT_VOTED, 5837 .clkr = { 5838 .enable_reg = 0x62018, 5839 .enable_mask = BIT(22), 5840 .hw.init = &(const struct clk_init_data) { 5841 .name = "gcc_qupv3_wrap1_s7_clk", 5842 .parent_hws = (const struct clk_hw*[]) { 5843 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 5844 }, 5845 .num_parents = 1, 5846 .flags = CLK_SET_RATE_PARENT, 5847 .ops = &clk_branch2_ops, 5848 }, 5849 }, 5850 }; 5851 5852 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { 5853 .halt_reg = 0xc52f0, 5854 .halt_check = BRANCH_HALT_VOTED, 5855 .clkr = { 5856 .enable_reg = 0x62018, 5857 .enable_mask = BIT(29), 5858 .hw.init = &(const struct clk_init_data) { 5859 .name = "gcc_qupv3_wrap2_core_2x_clk", 5860 .ops = &clk_branch2_ops, 5861 }, 5862 }, 5863 }; 5864 5865 static struct clk_branch gcc_qupv3_wrap2_core_clk = { 5866 .halt_reg = 0xc52dc, 5867 .halt_check = BRANCH_HALT_VOTED, 5868 .clkr = { 5869 .enable_reg = 0x62018, 5870 .enable_mask = BIT(28), 5871 .hw.init = &(const struct clk_init_data) { 5872 .name = "gcc_qupv3_wrap2_core_clk", 5873 .ops = &clk_branch2_ops, 5874 }, 5875 }, 5876 }; 5877 5878 static struct clk_branch gcc_qupv3_wrap2_qspi_s2_clk = { 5879 .halt_reg = 0xb479c, 5880 .halt_check = BRANCH_HALT_VOTED, 5881 .clkr = { 5882 .enable_reg = 0x62020, 5883 .enable_mask = BIT(7), 5884 .hw.init = &(const struct clk_init_data) { 5885 .name = "gcc_qupv3_wrap2_qspi_s2_clk", 5886 .parent_hws = (const struct clk_hw*[]) { 5887 &gcc_qupv3_wrap2_qspi_s2_clk_src.clkr.hw, 5888 }, 5889 .num_parents = 1, 5890 .flags = CLK_SET_RATE_PARENT, 5891 .ops = &clk_branch2_ops, 5892 }, 5893 }, 5894 }; 5895 5896 static struct clk_branch gcc_qupv3_wrap2_qspi_s3_clk = { 5897 .halt_reg = 0xb48cc, 5898 .halt_check = BRANCH_HALT_VOTED, 5899 .clkr = { 5900 .enable_reg = 0x62020, 5901 .enable_mask = BIT(8), 5902 .hw.init = &(const struct clk_init_data) { 5903 .name = "gcc_qupv3_wrap2_qspi_s3_clk", 5904 .parent_hws = (const struct clk_hw*[]) { 5905 &gcc_qupv3_wrap2_qspi_s3_clk_src.clkr.hw, 5906 }, 5907 .num_parents = 1, 5908 .flags = CLK_SET_RATE_PARENT, 5909 .ops = &clk_branch2_ops, 5910 }, 5911 }, 5912 }; 5913 5914 static struct clk_branch gcc_qupv3_wrap2_qspi_s6_clk = { 5915 .halt_reg = 0xb4798, 5916 .halt_check = BRANCH_HALT_VOTED, 5917 .clkr = { 5918 .enable_reg = 0x62020, 5919 .enable_mask = BIT(6), 5920 .hw.init = &(const struct clk_init_data) { 5921 .name = "gcc_qupv3_wrap2_qspi_s6_clk", 5922 .parent_hws = (const struct clk_hw*[]) { 5923 &gcc_qupv3_wrap2_qspi_s6_clk_src.clkr.hw, 5924 }, 5925 .num_parents = 1, 5926 .flags = CLK_SET_RATE_PARENT, 5927 .ops = &clk_branch2_ops, 5928 }, 5929 }, 5930 }; 5931 5932 static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 5933 .halt_reg = 0xb4004, 5934 .halt_check = BRANCH_HALT_VOTED, 5935 .clkr = { 5936 .enable_reg = 0x62018, 5937 .enable_mask = BIT(30), 5938 .hw.init = &(const struct clk_init_data) { 5939 .name = "gcc_qupv3_wrap2_s0_clk", 5940 .parent_hws = (const struct clk_hw*[]) { 5941 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 5942 }, 5943 .num_parents = 1, 5944 .flags = CLK_SET_RATE_PARENT, 5945 .ops = &clk_branch2_ops, 5946 }, 5947 }, 5948 }; 5949 5950 static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 5951 .halt_reg = 0xb4140, 5952 .halt_check = BRANCH_HALT_VOTED, 5953 .clkr = { 5954 .enable_reg = 0x62018, 5955 .enable_mask = BIT(31), 5956 .hw.init = &(const struct clk_init_data) { 5957 .name = "gcc_qupv3_wrap2_s1_clk", 5958 .parent_hws = (const struct clk_hw*[]) { 5959 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 5960 }, 5961 .num_parents = 1, 5962 .flags = CLK_SET_RATE_PARENT, 5963 .ops = &clk_branch2_ops, 5964 }, 5965 }, 5966 }; 5967 5968 static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 5969 .halt_reg = 0xb427c, 5970 .halt_check = BRANCH_HALT_VOTED, 5971 .clkr = { 5972 .enable_reg = 0x62020, 5973 .enable_mask = BIT(0), 5974 .hw.init = &(const struct clk_init_data) { 5975 .name = "gcc_qupv3_wrap2_s2_clk", 5976 .parent_hws = (const struct clk_hw*[]) { 5977 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 5978 }, 5979 .num_parents = 1, 5980 .flags = CLK_SET_RATE_PARENT, 5981 .ops = &clk_branch2_ops, 5982 }, 5983 }, 5984 }; 5985 5986 static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 5987 .halt_reg = 0xb4290, 5988 .halt_check = BRANCH_HALT_VOTED, 5989 .clkr = { 5990 .enable_reg = 0x62020, 5991 .enable_mask = BIT(1), 5992 .hw.init = &(const struct clk_init_data) { 5993 .name = "gcc_qupv3_wrap2_s3_clk", 5994 .parent_hws = (const struct clk_hw*[]) { 5995 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 5996 }, 5997 .num_parents = 1, 5998 .flags = CLK_SET_RATE_PARENT, 5999 .ops = &clk_branch2_ops, 6000 }, 6001 }, 6002 }; 6003 6004 static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 6005 .halt_reg = 0xb42a4, 6006 .halt_check = BRANCH_HALT_VOTED, 6007 .clkr = { 6008 .enable_reg = 0x62020, 6009 .enable_mask = BIT(2), 6010 .hw.init = &(const struct clk_init_data) { 6011 .name = "gcc_qupv3_wrap2_s4_clk", 6012 .parent_hws = (const struct clk_hw*[]) { 6013 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 6014 }, 6015 .num_parents = 1, 6016 .flags = CLK_SET_RATE_PARENT, 6017 .ops = &clk_branch2_ops, 6018 }, 6019 }, 6020 }; 6021 6022 static struct clk_branch gcc_qupv3_wrap2_s5_clk = { 6023 .halt_reg = 0xb43e0, 6024 .halt_check = BRANCH_HALT_VOTED, 6025 .clkr = { 6026 .enable_reg = 0x62020, 6027 .enable_mask = BIT(3), 6028 .hw.init = &(const struct clk_init_data) { 6029 .name = "gcc_qupv3_wrap2_s5_clk", 6030 .parent_hws = (const struct clk_hw*[]) { 6031 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, 6032 }, 6033 .num_parents = 1, 6034 .flags = CLK_SET_RATE_PARENT, 6035 .ops = &clk_branch2_ops, 6036 }, 6037 }, 6038 }; 6039 6040 static struct clk_branch gcc_qupv3_wrap2_s6_clk = { 6041 .halt_reg = 0xb451c, 6042 .halt_check = BRANCH_HALT_VOTED, 6043 .clkr = { 6044 .enable_reg = 0x62020, 6045 .enable_mask = BIT(4), 6046 .hw.init = &(const struct clk_init_data) { 6047 .name = "gcc_qupv3_wrap2_s6_clk", 6048 .parent_hws = (const struct clk_hw*[]) { 6049 &gcc_qupv3_wrap2_s6_clk_src.clkr.hw, 6050 }, 6051 .num_parents = 1, 6052 .flags = CLK_SET_RATE_PARENT, 6053 .ops = &clk_branch2_ops, 6054 }, 6055 }, 6056 }; 6057 6058 static struct clk_branch gcc_qupv3_wrap2_s7_clk = { 6059 .halt_reg = 0xb4530, 6060 .halt_check = BRANCH_HALT_VOTED, 6061 .clkr = { 6062 .enable_reg = 0x62020, 6063 .enable_mask = BIT(5), 6064 .hw.init = &(const struct clk_init_data) { 6065 .name = "gcc_qupv3_wrap2_s7_clk", 6066 .parent_hws = (const struct clk_hw*[]) { 6067 &gcc_qupv3_wrap2_s7_clk_src.clkr.hw, 6068 }, 6069 .num_parents = 1, 6070 .flags = CLK_SET_RATE_PARENT, 6071 .ops = &clk_branch2_ops, 6072 }, 6073 }, 6074 }; 6075 6076 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 6077 .halt_reg = 0xc542c, 6078 .halt_check = BRANCH_HALT_VOTED, 6079 .hwcg_reg = 0xc542c, 6080 .hwcg_bit = 1, 6081 .clkr = { 6082 .enable_reg = 0x62020, 6083 .enable_mask = BIT(9), 6084 .hw.init = &(const struct clk_init_data) { 6085 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 6086 .ops = &clk_branch2_ops, 6087 }, 6088 }, 6089 }; 6090 6091 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 6092 .halt_reg = 0xc5430, 6093 .halt_check = BRANCH_HALT_VOTED, 6094 .hwcg_reg = 0xc5430, 6095 .hwcg_bit = 1, 6096 .clkr = { 6097 .enable_reg = 0x62020, 6098 .enable_mask = BIT(10), 6099 .hw.init = &(const struct clk_init_data) { 6100 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 6101 .ops = &clk_branch2_ops, 6102 }, 6103 }, 6104 }; 6105 6106 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 6107 .halt_reg = 0xc517c, 6108 .halt_check = BRANCH_HALT_VOTED, 6109 .hwcg_reg = 0xc517c, 6110 .hwcg_bit = 1, 6111 .clkr = { 6112 .enable_reg = 0x62018, 6113 .enable_mask = BIT(11), 6114 .hw.init = &(const struct clk_init_data) { 6115 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 6116 .ops = &clk_branch2_ops, 6117 }, 6118 }, 6119 }; 6120 6121 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 6122 .halt_reg = 0xc5180, 6123 .halt_check = BRANCH_HALT_VOTED, 6124 .hwcg_reg = 0xc5180, 6125 .hwcg_bit = 1, 6126 .clkr = { 6127 .enable_reg = 0x62018, 6128 .enable_mask = BIT(12), 6129 .hw.init = &(const struct clk_init_data) { 6130 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 6131 .ops = &clk_branch2_ops, 6132 }, 6133 }, 6134 }; 6135 6136 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 6137 .halt_reg = 0xc52d4, 6138 .halt_check = BRANCH_HALT_VOTED, 6139 .hwcg_reg = 0xc52d4, 6140 .hwcg_bit = 1, 6141 .clkr = { 6142 .enable_reg = 0x62018, 6143 .enable_mask = BIT(26), 6144 .hw.init = &(const struct clk_init_data) { 6145 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 6146 .ops = &clk_branch2_ops, 6147 }, 6148 }, 6149 }; 6150 6151 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 6152 .halt_reg = 0xc52d8, 6153 .halt_check = BRANCH_HALT_VOTED, 6154 .hwcg_reg = 0xc52d8, 6155 .hwcg_bit = 1, 6156 .clkr = { 6157 .enable_reg = 0x62018, 6158 .enable_mask = BIT(27), 6159 .hw.init = &(const struct clk_init_data) { 6160 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 6161 .ops = &clk_branch2_ops, 6162 }, 6163 }, 6164 }; 6165 6166 static struct clk_branch gcc_sdcc2_ahb_clk = { 6167 .halt_reg = 0xb0014, 6168 .halt_check = BRANCH_HALT, 6169 .clkr = { 6170 .enable_reg = 0xb0014, 6171 .enable_mask = BIT(0), 6172 .hw.init = &(const struct clk_init_data) { 6173 .name = "gcc_sdcc2_ahb_clk", 6174 .ops = &clk_branch2_ops, 6175 }, 6176 }, 6177 }; 6178 6179 static struct clk_branch gcc_sdcc2_apps_clk = { 6180 .halt_reg = 0xb0004, 6181 .halt_check = BRANCH_HALT, 6182 .clkr = { 6183 .enable_reg = 0xb0004, 6184 .enable_mask = BIT(0), 6185 .hw.init = &(const struct clk_init_data) { 6186 .name = "gcc_sdcc2_apps_clk", 6187 .parent_hws = (const struct clk_hw*[]) { 6188 &gcc_sdcc2_apps_clk_src.clkr.hw, 6189 }, 6190 .num_parents = 1, 6191 .flags = CLK_SET_RATE_PARENT, 6192 .ops = &clk_branch2_ops, 6193 }, 6194 }, 6195 }; 6196 6197 static struct clk_branch gcc_sdcc4_ahb_clk = { 6198 .halt_reg = 0xdf014, 6199 .halt_check = BRANCH_HALT, 6200 .clkr = { 6201 .enable_reg = 0xdf014, 6202 .enable_mask = BIT(0), 6203 .hw.init = &(const struct clk_init_data) { 6204 .name = "gcc_sdcc4_ahb_clk", 6205 .ops = &clk_branch2_ops, 6206 }, 6207 }, 6208 }; 6209 6210 static struct clk_branch gcc_sdcc4_apps_clk = { 6211 .halt_reg = 0xdf004, 6212 .halt_check = BRANCH_HALT, 6213 .clkr = { 6214 .enable_reg = 0xdf004, 6215 .enable_mask = BIT(0), 6216 .hw.init = &(const struct clk_init_data) { 6217 .name = "gcc_sdcc4_apps_clk", 6218 .parent_hws = (const struct clk_hw*[]) { 6219 &gcc_sdcc4_apps_clk_src.clkr.hw, 6220 }, 6221 .num_parents = 1, 6222 .flags = CLK_SET_RATE_PARENT, 6223 .ops = &clk_branch2_ops, 6224 }, 6225 }, 6226 }; 6227 6228 static struct clk_branch gcc_ufs_phy_ahb_clk = { 6229 .halt_reg = 0xba504, 6230 .halt_check = BRANCH_HALT_VOTED, 6231 .hwcg_reg = 0xba504, 6232 .hwcg_bit = 1, 6233 .clkr = { 6234 .enable_reg = 0xba504, 6235 .enable_mask = BIT(0), 6236 .hw.init = &(const struct clk_init_data) { 6237 .name = "gcc_ufs_phy_ahb_clk", 6238 .ops = &clk_branch2_ops, 6239 }, 6240 }, 6241 }; 6242 6243 static struct clk_branch gcc_ufs_phy_axi_clk = { 6244 .halt_reg = 0x7701c, 6245 .halt_check = BRANCH_HALT_VOTED, 6246 .hwcg_reg = 0x7701c, 6247 .hwcg_bit = 1, 6248 .clkr = { 6249 .enable_reg = 0x7701c, 6250 .enable_mask = BIT(0), 6251 .hw.init = &(const struct clk_init_data) { 6252 .name = "gcc_ufs_phy_axi_clk", 6253 .parent_hws = (const struct clk_hw*[]) { 6254 &gcc_ufs_phy_axi_clk_src.clkr.hw, 6255 }, 6256 .num_parents = 1, 6257 .flags = CLK_SET_RATE_PARENT, 6258 .ops = &clk_branch2_ops, 6259 }, 6260 }, 6261 }; 6262 6263 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 6264 .halt_reg = 0x77080, 6265 .halt_check = BRANCH_HALT_VOTED, 6266 .hwcg_reg = 0x77080, 6267 .hwcg_bit = 1, 6268 .clkr = { 6269 .enable_reg = 0x77080, 6270 .enable_mask = BIT(0), 6271 .hw.init = &(const struct clk_init_data) { 6272 .name = "gcc_ufs_phy_ice_core_clk", 6273 .parent_hws = (const struct clk_hw*[]) { 6274 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 6275 }, 6276 .num_parents = 1, 6277 .flags = CLK_SET_RATE_PARENT, 6278 .ops = &clk_branch2_ops, 6279 }, 6280 }, 6281 }; 6282 6283 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 6284 .halt_reg = 0x770c0, 6285 .halt_check = BRANCH_HALT_VOTED, 6286 .hwcg_reg = 0x770c0, 6287 .hwcg_bit = 1, 6288 .clkr = { 6289 .enable_reg = 0x770c0, 6290 .enable_mask = BIT(0), 6291 .hw.init = &(const struct clk_init_data) { 6292 .name = "gcc_ufs_phy_phy_aux_clk", 6293 .parent_hws = (const struct clk_hw*[]) { 6294 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 6295 }, 6296 .num_parents = 1, 6297 .flags = CLK_SET_RATE_PARENT, 6298 .ops = &clk_branch2_ops, 6299 }, 6300 }, 6301 }; 6302 6303 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 6304 .halt_reg = 0x77034, 6305 .halt_check = BRANCH_HALT_DELAY, 6306 .clkr = { 6307 .enable_reg = 0x77034, 6308 .enable_mask = BIT(0), 6309 .hw.init = &(const struct clk_init_data) { 6310 .name = "gcc_ufs_phy_rx_symbol_0_clk", 6311 .parent_hws = (const struct clk_hw*[]) { 6312 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, 6313 }, 6314 .num_parents = 1, 6315 .flags = CLK_SET_RATE_PARENT, 6316 .ops = &clk_branch2_ops, 6317 }, 6318 }, 6319 }; 6320 6321 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 6322 .halt_reg = 0x770dc, 6323 .halt_check = BRANCH_HALT_DELAY, 6324 .clkr = { 6325 .enable_reg = 0x770dc, 6326 .enable_mask = BIT(0), 6327 .hw.init = &(const struct clk_init_data) { 6328 .name = "gcc_ufs_phy_rx_symbol_1_clk", 6329 .parent_hws = (const struct clk_hw*[]) { 6330 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, 6331 }, 6332 .num_parents = 1, 6333 .flags = CLK_SET_RATE_PARENT, 6334 .ops = &clk_branch2_ops, 6335 }, 6336 }, 6337 }; 6338 6339 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 6340 .halt_reg = 0x77030, 6341 .halt_check = BRANCH_HALT_DELAY, 6342 .clkr = { 6343 .enable_reg = 0x77030, 6344 .enable_mask = BIT(0), 6345 .hw.init = &(const struct clk_init_data) { 6346 .name = "gcc_ufs_phy_tx_symbol_0_clk", 6347 .parent_hws = (const struct clk_hw*[]) { 6348 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, 6349 }, 6350 .num_parents = 1, 6351 .flags = CLK_SET_RATE_PARENT, 6352 .ops = &clk_branch2_ops, 6353 }, 6354 }, 6355 }; 6356 6357 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 6358 .halt_reg = 0x77070, 6359 .halt_check = BRANCH_HALT_VOTED, 6360 .hwcg_reg = 0x77070, 6361 .hwcg_bit = 1, 6362 .clkr = { 6363 .enable_reg = 0x77070, 6364 .enable_mask = BIT(0), 6365 .hw.init = &(const struct clk_init_data) { 6366 .name = "gcc_ufs_phy_unipro_core_clk", 6367 .parent_hws = (const struct clk_hw*[]) { 6368 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 6369 }, 6370 .num_parents = 1, 6371 .flags = CLK_SET_RATE_PARENT, 6372 .ops = &clk_branch2_ops, 6373 }, 6374 }, 6375 }; 6376 6377 static struct clk_branch gcc_usb20_master_clk = { 6378 .halt_reg = 0xbc018, 6379 .halt_check = BRANCH_HALT, 6380 .clkr = { 6381 .enable_reg = 0xbc018, 6382 .enable_mask = BIT(0), 6383 .hw.init = &(const struct clk_init_data) { 6384 .name = "gcc_usb20_master_clk", 6385 .parent_hws = (const struct clk_hw*[]) { 6386 &gcc_usb20_master_clk_src.clkr.hw, 6387 }, 6388 .num_parents = 1, 6389 .flags = CLK_SET_RATE_PARENT, 6390 .ops = &clk_branch2_ops, 6391 }, 6392 }, 6393 }; 6394 6395 static struct clk_branch gcc_usb20_mock_utmi_clk = { 6396 .halt_reg = 0xbc02c, 6397 .halt_check = BRANCH_HALT, 6398 .clkr = { 6399 .enable_reg = 0xbc02c, 6400 .enable_mask = BIT(0), 6401 .hw.init = &(const struct clk_init_data) { 6402 .name = "gcc_usb20_mock_utmi_clk", 6403 .parent_hws = (const struct clk_hw*[]) { 6404 &gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw, 6405 }, 6406 .num_parents = 1, 6407 .flags = CLK_SET_RATE_PARENT, 6408 .ops = &clk_branch2_ops, 6409 }, 6410 }, 6411 }; 6412 6413 static struct clk_branch gcc_usb20_sleep_clk = { 6414 .halt_reg = 0xbc028, 6415 .halt_check = BRANCH_HALT, 6416 .clkr = { 6417 .enable_reg = 0xbc028, 6418 .enable_mask = BIT(0), 6419 .hw.init = &(const struct clk_init_data) { 6420 .name = "gcc_usb20_sleep_clk", 6421 .ops = &clk_branch2_ops, 6422 }, 6423 }, 6424 }; 6425 6426 static struct clk_branch gcc_usb30_mp_master_clk = { 6427 .halt_reg = 0x9a024, 6428 .halt_check = BRANCH_HALT, 6429 .clkr = { 6430 .enable_reg = 0x9a024, 6431 .enable_mask = BIT(0), 6432 .hw.init = &(const struct clk_init_data) { 6433 .name = "gcc_usb30_mp_master_clk", 6434 .parent_hws = (const struct clk_hw*[]) { 6435 &gcc_usb30_mp_master_clk_src.clkr.hw, 6436 }, 6437 .num_parents = 1, 6438 .flags = CLK_SET_RATE_PARENT, 6439 .ops = &clk_branch2_ops, 6440 }, 6441 }, 6442 }; 6443 6444 static struct clk_branch gcc_usb30_mp_mock_utmi_clk = { 6445 .halt_reg = 0x9a038, 6446 .halt_check = BRANCH_HALT, 6447 .clkr = { 6448 .enable_reg = 0x9a038, 6449 .enable_mask = BIT(0), 6450 .hw.init = &(const struct clk_init_data) { 6451 .name = "gcc_usb30_mp_mock_utmi_clk", 6452 .parent_hws = (const struct clk_hw*[]) { 6453 &gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr.hw, 6454 }, 6455 .num_parents = 1, 6456 .flags = CLK_SET_RATE_PARENT, 6457 .ops = &clk_branch2_ops, 6458 }, 6459 }, 6460 }; 6461 6462 static struct clk_branch gcc_usb30_mp_sleep_clk = { 6463 .halt_reg = 0x9a034, 6464 .halt_check = BRANCH_HALT, 6465 .clkr = { 6466 .enable_reg = 0x9a034, 6467 .enable_mask = BIT(0), 6468 .hw.init = &(const struct clk_init_data) { 6469 .name = "gcc_usb30_mp_sleep_clk", 6470 .ops = &clk_branch2_ops, 6471 }, 6472 }, 6473 }; 6474 6475 static struct clk_branch gcc_usb30_prim_master_clk = { 6476 .halt_reg = 0x3f030, 6477 .halt_check = BRANCH_HALT, 6478 .clkr = { 6479 .enable_reg = 0x3f030, 6480 .enable_mask = BIT(0), 6481 .hw.init = &(const struct clk_init_data) { 6482 .name = "gcc_usb30_prim_master_clk", 6483 .parent_hws = (const struct clk_hw*[]) { 6484 &gcc_usb30_prim_master_clk_src.clkr.hw, 6485 }, 6486 .num_parents = 1, 6487 .flags = CLK_SET_RATE_PARENT, 6488 .ops = &clk_branch2_ops, 6489 }, 6490 }, 6491 }; 6492 6493 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 6494 .halt_reg = 0x3f048, 6495 .halt_check = BRANCH_HALT, 6496 .clkr = { 6497 .enable_reg = 0x3f048, 6498 .enable_mask = BIT(0), 6499 .hw.init = &(const struct clk_init_data) { 6500 .name = "gcc_usb30_prim_mock_utmi_clk", 6501 .parent_hws = (const struct clk_hw*[]) { 6502 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 6503 }, 6504 .num_parents = 1, 6505 .flags = CLK_SET_RATE_PARENT, 6506 .ops = &clk_branch2_ops, 6507 }, 6508 }, 6509 }; 6510 6511 static struct clk_branch gcc_usb30_prim_sleep_clk = { 6512 .halt_reg = 0x3f044, 6513 .halt_check = BRANCH_HALT, 6514 .clkr = { 6515 .enable_reg = 0x3f044, 6516 .enable_mask = BIT(0), 6517 .hw.init = &(const struct clk_init_data) { 6518 .name = "gcc_usb30_prim_sleep_clk", 6519 .ops = &clk_branch2_ops, 6520 }, 6521 }, 6522 }; 6523 6524 static struct clk_branch gcc_usb30_sec_master_clk = { 6525 .halt_reg = 0xe2024, 6526 .halt_check = BRANCH_HALT, 6527 .clkr = { 6528 .enable_reg = 0xe2024, 6529 .enable_mask = BIT(0), 6530 .hw.init = &(const struct clk_init_data) { 6531 .name = "gcc_usb30_sec_master_clk", 6532 .parent_hws = (const struct clk_hw*[]) { 6533 &gcc_usb30_sec_master_clk_src.clkr.hw, 6534 }, 6535 .num_parents = 1, 6536 .flags = CLK_SET_RATE_PARENT, 6537 .ops = &clk_branch2_ops, 6538 }, 6539 }, 6540 }; 6541 6542 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { 6543 .halt_reg = 0xe2038, 6544 .halt_check = BRANCH_HALT, 6545 .clkr = { 6546 .enable_reg = 0xe2038, 6547 .enable_mask = BIT(0), 6548 .hw.init = &(const struct clk_init_data) { 6549 .name = "gcc_usb30_sec_mock_utmi_clk", 6550 .parent_hws = (const struct clk_hw*[]) { 6551 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw, 6552 }, 6553 .num_parents = 1, 6554 .flags = CLK_SET_RATE_PARENT, 6555 .ops = &clk_branch2_ops, 6556 }, 6557 }, 6558 }; 6559 6560 static struct clk_branch gcc_usb30_sec_sleep_clk = { 6561 .halt_reg = 0xe2034, 6562 .halt_check = BRANCH_HALT, 6563 .clkr = { 6564 .enable_reg = 0xe2034, 6565 .enable_mask = BIT(0), 6566 .hw.init = &(const struct clk_init_data) { 6567 .name = "gcc_usb30_sec_sleep_clk", 6568 .ops = &clk_branch2_ops, 6569 }, 6570 }, 6571 }; 6572 6573 static struct clk_branch gcc_usb30_tert_master_clk = { 6574 .halt_reg = 0xe1024, 6575 .halt_check = BRANCH_HALT, 6576 .clkr = { 6577 .enable_reg = 0xe1024, 6578 .enable_mask = BIT(0), 6579 .hw.init = &(const struct clk_init_data) { 6580 .name = "gcc_usb30_tert_master_clk", 6581 .parent_hws = (const struct clk_hw*[]) { 6582 &gcc_usb30_tert_master_clk_src.clkr.hw, 6583 }, 6584 .num_parents = 1, 6585 .flags = CLK_SET_RATE_PARENT, 6586 .ops = &clk_branch2_ops, 6587 }, 6588 }, 6589 }; 6590 6591 static struct clk_branch gcc_usb30_tert_mock_utmi_clk = { 6592 .halt_reg = 0xe1038, 6593 .halt_check = BRANCH_HALT, 6594 .clkr = { 6595 .enable_reg = 0xe1038, 6596 .enable_mask = BIT(0), 6597 .hw.init = &(const struct clk_init_data) { 6598 .name = "gcc_usb30_tert_mock_utmi_clk", 6599 .parent_hws = (const struct clk_hw*[]) { 6600 &gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr.hw, 6601 }, 6602 .num_parents = 1, 6603 .flags = CLK_SET_RATE_PARENT, 6604 .ops = &clk_branch2_ops, 6605 }, 6606 }, 6607 }; 6608 6609 static struct clk_branch gcc_usb30_tert_sleep_clk = { 6610 .halt_reg = 0xe1034, 6611 .halt_check = BRANCH_HALT, 6612 .clkr = { 6613 .enable_reg = 0xe1034, 6614 .enable_mask = BIT(0), 6615 .hw.init = &(const struct clk_init_data) { 6616 .name = "gcc_usb30_tert_sleep_clk", 6617 .ops = &clk_branch2_ops, 6618 }, 6619 }, 6620 }; 6621 6622 static struct clk_branch gcc_usb3_mp_phy_aux_clk = { 6623 .halt_reg = 0x9a070, 6624 .halt_check = BRANCH_HALT, 6625 .clkr = { 6626 .enable_reg = 0x9a070, 6627 .enable_mask = BIT(0), 6628 .hw.init = &(const struct clk_init_data) { 6629 .name = "gcc_usb3_mp_phy_aux_clk", 6630 .parent_hws = (const struct clk_hw*[]) { 6631 &gcc_usb3_mp_phy_aux_clk_src.clkr.hw, 6632 }, 6633 .num_parents = 1, 6634 .flags = CLK_SET_RATE_PARENT, 6635 .ops = &clk_branch2_ops, 6636 }, 6637 }, 6638 }; 6639 6640 static struct clk_branch gcc_usb3_mp_phy_com_aux_clk = { 6641 .halt_reg = 0x9a074, 6642 .halt_check = BRANCH_HALT, 6643 .clkr = { 6644 .enable_reg = 0x9a074, 6645 .enable_mask = BIT(0), 6646 .hw.init = &(const struct clk_init_data) { 6647 .name = "gcc_usb3_mp_phy_com_aux_clk", 6648 .parent_hws = (const struct clk_hw*[]) { 6649 &gcc_usb3_mp_phy_aux_clk_src.clkr.hw, 6650 }, 6651 .num_parents = 1, 6652 .flags = CLK_SET_RATE_PARENT, 6653 .ops = &clk_branch2_ops, 6654 }, 6655 }, 6656 }; 6657 6658 static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = { 6659 .halt_reg = 0x9a078, 6660 .halt_check = BRANCH_HALT_SKIP, 6661 .clkr = { 6662 .enable_reg = 0x9a078, 6663 .enable_mask = BIT(0), 6664 .hw.init = &(const struct clk_init_data) { 6665 .name = "gcc_usb3_mp_phy_pipe_0_clk", 6666 .parent_hws = (const struct clk_hw*[]) { 6667 &gcc_usb3_mp_phy_pipe_0_clk_src.clkr.hw, 6668 }, 6669 .num_parents = 1, 6670 .flags = CLK_SET_RATE_PARENT, 6671 .ops = &clk_branch2_ops, 6672 }, 6673 }, 6674 }; 6675 6676 static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = { 6677 .halt_reg = 0x9a080, 6678 .halt_check = BRANCH_HALT_SKIP, 6679 .clkr = { 6680 .enable_reg = 0x9a080, 6681 .enable_mask = BIT(0), 6682 .hw.init = &(const struct clk_init_data) { 6683 .name = "gcc_usb3_mp_phy_pipe_1_clk", 6684 .parent_hws = (const struct clk_hw*[]) { 6685 &gcc_usb3_mp_phy_pipe_1_clk_src.clkr.hw, 6686 }, 6687 .num_parents = 1, 6688 .flags = CLK_SET_RATE_PARENT, 6689 .ops = &clk_branch2_ops, 6690 }, 6691 }, 6692 }; 6693 6694 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 6695 .halt_reg = 0x3f080, 6696 .halt_check = BRANCH_HALT, 6697 .clkr = { 6698 .enable_reg = 0x3f080, 6699 .enable_mask = BIT(0), 6700 .hw.init = &(const struct clk_init_data) { 6701 .name = "gcc_usb3_prim_phy_aux_clk", 6702 .parent_hws = (const struct clk_hw*[]) { 6703 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 6704 }, 6705 .num_parents = 1, 6706 .flags = CLK_SET_RATE_PARENT, 6707 .ops = &clk_branch2_ops, 6708 }, 6709 }, 6710 }; 6711 6712 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 6713 .halt_reg = 0x3f084, 6714 .halt_check = BRANCH_HALT, 6715 .clkr = { 6716 .enable_reg = 0x3f084, 6717 .enable_mask = BIT(0), 6718 .hw.init = &(const struct clk_init_data) { 6719 .name = "gcc_usb3_prim_phy_com_aux_clk", 6720 .parent_hws = (const struct clk_hw*[]) { 6721 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 6722 }, 6723 .num_parents = 1, 6724 .flags = CLK_SET_RATE_PARENT, 6725 .ops = &clk_branch2_ops, 6726 }, 6727 }, 6728 }; 6729 6730 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 6731 .halt_reg = 0x3f088, 6732 .halt_check = BRANCH_HALT_SKIP, 6733 .hwcg_reg = 0x3f088, 6734 .hwcg_bit = 1, 6735 .clkr = { 6736 .enable_reg = 0x3f088, 6737 .enable_mask = BIT(0), 6738 .hw.init = &(const struct clk_init_data) { 6739 .name = "gcc_usb3_prim_phy_pipe_clk", 6740 .parent_hws = (const struct clk_hw*[]) { 6741 &gcc_usb34_prim_phy_pipe_clk_src.clkr.hw, 6742 }, 6743 .num_parents = 1, 6744 .flags = CLK_SET_RATE_PARENT, 6745 .ops = &clk_branch2_ops, 6746 }, 6747 }, 6748 }; 6749 6750 static struct clk_branch gcc_usb3_sec_phy_aux_clk = { 6751 .halt_reg = 0xe2070, 6752 .halt_check = BRANCH_HALT, 6753 .clkr = { 6754 .enable_reg = 0xe2070, 6755 .enable_mask = BIT(0), 6756 .hw.init = &(const struct clk_init_data) { 6757 .name = "gcc_usb3_sec_phy_aux_clk", 6758 .parent_hws = (const struct clk_hw*[]) { 6759 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 6760 }, 6761 .num_parents = 1, 6762 .flags = CLK_SET_RATE_PARENT, 6763 .ops = &clk_branch2_ops, 6764 }, 6765 }, 6766 }; 6767 6768 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { 6769 .halt_reg = 0xe2074, 6770 .halt_check = BRANCH_HALT, 6771 .clkr = { 6772 .enable_reg = 0xe2074, 6773 .enable_mask = BIT(0), 6774 .hw.init = &(const struct clk_init_data) { 6775 .name = "gcc_usb3_sec_phy_com_aux_clk", 6776 .parent_hws = (const struct clk_hw*[]) { 6777 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, 6778 }, 6779 .num_parents = 1, 6780 .flags = CLK_SET_RATE_PARENT, 6781 .ops = &clk_branch2_ops, 6782 }, 6783 }, 6784 }; 6785 6786 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { 6787 .halt_reg = 0xe2078, 6788 .halt_check = BRANCH_HALT_SKIP, 6789 .hwcg_reg = 0xe2078, 6790 .hwcg_bit = 1, 6791 .clkr = { 6792 .enable_reg = 0xe2078, 6793 .enable_mask = BIT(0), 6794 .hw.init = &(const struct clk_init_data) { 6795 .name = "gcc_usb3_sec_phy_pipe_clk", 6796 .parent_hws = (const struct clk_hw*[]) { 6797 &gcc_usb34_sec_phy_pipe_clk_src.clkr.hw, 6798 }, 6799 .num_parents = 1, 6800 .flags = CLK_SET_RATE_PARENT, 6801 .ops = &clk_branch2_ops, 6802 }, 6803 }, 6804 }; 6805 6806 static struct clk_branch gcc_usb3_tert_phy_aux_clk = { 6807 .halt_reg = 0xe1070, 6808 .halt_check = BRANCH_HALT, 6809 .clkr = { 6810 .enable_reg = 0xe1070, 6811 .enable_mask = BIT(0), 6812 .hw.init = &(const struct clk_init_data) { 6813 .name = "gcc_usb3_tert_phy_aux_clk", 6814 .parent_hws = (const struct clk_hw*[]) { 6815 &gcc_usb3_tert_phy_aux_clk_src.clkr.hw, 6816 }, 6817 .num_parents = 1, 6818 .flags = CLK_SET_RATE_PARENT, 6819 .ops = &clk_branch2_ops, 6820 }, 6821 }, 6822 }; 6823 6824 static struct clk_branch gcc_usb3_tert_phy_com_aux_clk = { 6825 .halt_reg = 0xe1074, 6826 .halt_check = BRANCH_HALT, 6827 .clkr = { 6828 .enable_reg = 0xe1074, 6829 .enable_mask = BIT(0), 6830 .hw.init = &(const struct clk_init_data) { 6831 .name = "gcc_usb3_tert_phy_com_aux_clk", 6832 .parent_hws = (const struct clk_hw*[]) { 6833 &gcc_usb3_tert_phy_aux_clk_src.clkr.hw, 6834 }, 6835 .num_parents = 1, 6836 .flags = CLK_SET_RATE_PARENT, 6837 .ops = &clk_branch2_ops, 6838 }, 6839 }, 6840 }; 6841 6842 static struct clk_branch gcc_usb3_tert_phy_pipe_clk = { 6843 .halt_reg = 0xe1078, 6844 .halt_check = BRANCH_HALT_SKIP, 6845 .hwcg_reg = 0xe1078, 6846 .hwcg_bit = 1, 6847 .clkr = { 6848 .enable_reg = 0xe1078, 6849 .enable_mask = BIT(0), 6850 .hw.init = &(const struct clk_init_data) { 6851 .name = "gcc_usb3_tert_phy_pipe_clk", 6852 .parent_hws = (const struct clk_hw*[]) { 6853 &gcc_usb34_tert_phy_pipe_clk_src.clkr.hw, 6854 }, 6855 .num_parents = 1, 6856 .flags = CLK_SET_RATE_PARENT, 6857 .ops = &clk_branch2_ops, 6858 }, 6859 }, 6860 }; 6861 6862 static struct clk_branch gcc_usb4_0_cfg_ahb_clk = { 6863 .halt_reg = 0xba450, 6864 .halt_check = BRANCH_HALT_VOTED, 6865 .hwcg_reg = 0xba450, 6866 .hwcg_bit = 1, 6867 .clkr = { 6868 .enable_reg = 0xba450, 6869 .enable_mask = BIT(0), 6870 .hw.init = &(const struct clk_init_data) { 6871 .name = "gcc_usb4_0_cfg_ahb_clk", 6872 .ops = &clk_branch2_ops, 6873 }, 6874 }, 6875 }; 6876 6877 static struct clk_branch gcc_usb4_0_dp0_clk = { 6878 .halt_reg = 0x2b070, 6879 .halt_check = BRANCH_HALT, 6880 .clkr = { 6881 .enable_reg = 0x2b070, 6882 .enable_mask = BIT(0), 6883 .hw.init = &(const struct clk_init_data) { 6884 .name = "gcc_usb4_0_dp0_clk", 6885 .parent_hws = (const struct clk_hw*[]) { 6886 &gcc_usb4_0_phy_dp0_clk_src.clkr.hw, 6887 }, 6888 .num_parents = 1, 6889 .flags = CLK_SET_RATE_PARENT, 6890 .ops = &clk_branch2_ops, 6891 }, 6892 }, 6893 }; 6894 6895 static struct clk_branch gcc_usb4_0_dp1_clk = { 6896 .halt_reg = 0x2b124, 6897 .halt_check = BRANCH_HALT, 6898 .clkr = { 6899 .enable_reg = 0x2b124, 6900 .enable_mask = BIT(0), 6901 .hw.init = &(const struct clk_init_data) { 6902 .name = "gcc_usb4_0_dp1_clk", 6903 .parent_hws = (const struct clk_hw*[]) { 6904 &gcc_usb4_0_phy_dp1_clk_src.clkr.hw, 6905 }, 6906 .num_parents = 1, 6907 .flags = CLK_SET_RATE_PARENT, 6908 .ops = &clk_branch2_ops, 6909 }, 6910 }, 6911 }; 6912 6913 static struct clk_branch gcc_usb4_0_master_clk = { 6914 .halt_reg = 0x2b01c, 6915 .halt_check = BRANCH_HALT, 6916 .clkr = { 6917 .enable_reg = 0x2b01c, 6918 .enable_mask = BIT(0), 6919 .hw.init = &(const struct clk_init_data) { 6920 .name = "gcc_usb4_0_master_clk", 6921 .parent_hws = (const struct clk_hw*[]) { 6922 &gcc_usb4_0_master_clk_src.clkr.hw, 6923 }, 6924 .num_parents = 1, 6925 .flags = CLK_SET_RATE_PARENT, 6926 .ops = &clk_branch2_ops, 6927 }, 6928 }, 6929 }; 6930 6931 static struct clk_branch gcc_usb4_0_phy_p2rr2p_pipe_clk = { 6932 .halt_reg = 0x2b0f4, 6933 .halt_check = BRANCH_HALT_SKIP, 6934 .clkr = { 6935 .enable_reg = 0x2b0f4, 6936 .enable_mask = BIT(0), 6937 .hw.init = &(const struct clk_init_data) { 6938 .name = "gcc_usb4_0_phy_p2rr2p_pipe_clk", 6939 .parent_hws = (const struct clk_hw*[]) { 6940 &gcc_usb4_0_phy_p2rr2p_pipe_clk_src.clkr.hw, 6941 }, 6942 .num_parents = 1, 6943 .flags = CLK_SET_RATE_PARENT, 6944 .ops = &clk_branch2_ops, 6945 }, 6946 }, 6947 }; 6948 6949 static struct clk_branch gcc_usb4_0_phy_pcie_pipe_clk = { 6950 .halt_reg = 0x2b04c, 6951 .halt_check = BRANCH_HALT_SKIP, 6952 .clkr = { 6953 .enable_reg = 0x62010, 6954 .enable_mask = BIT(11), 6955 .hw.init = &(const struct clk_init_data) { 6956 .name = "gcc_usb4_0_phy_pcie_pipe_clk", 6957 .parent_hws = (const struct clk_hw*[]) { 6958 &gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr.hw, 6959 }, 6960 .num_parents = 1, 6961 .flags = CLK_SET_RATE_PARENT, 6962 .ops = &clk_branch2_ops, 6963 }, 6964 }, 6965 }; 6966 6967 static struct clk_branch gcc_usb4_0_phy_rx0_clk = { 6968 .halt_reg = 0x2b0c4, 6969 .halt_check = BRANCH_HALT, 6970 .clkr = { 6971 .enable_reg = 0x2b0c4, 6972 .enable_mask = BIT(0), 6973 .hw.init = &(const struct clk_init_data) { 6974 .name = "gcc_usb4_0_phy_rx0_clk", 6975 .parent_hws = (const struct clk_hw*[]) { 6976 &gcc_usb4_0_phy_rx0_clk_src.clkr.hw, 6977 }, 6978 .num_parents = 1, 6979 .flags = CLK_SET_RATE_PARENT, 6980 .ops = &clk_branch2_ops, 6981 }, 6982 }, 6983 }; 6984 6985 static struct clk_branch gcc_usb4_0_phy_rx1_clk = { 6986 .halt_reg = 0x2b0d8, 6987 .halt_check = BRANCH_HALT, 6988 .clkr = { 6989 .enable_reg = 0x2b0d8, 6990 .enable_mask = BIT(0), 6991 .hw.init = &(const struct clk_init_data) { 6992 .name = "gcc_usb4_0_phy_rx1_clk", 6993 .parent_hws = (const struct clk_hw*[]) { 6994 &gcc_usb4_0_phy_rx1_clk_src.clkr.hw, 6995 }, 6996 .num_parents = 1, 6997 .flags = CLK_SET_RATE_PARENT, 6998 .ops = &clk_branch2_ops, 6999 }, 7000 }, 7001 }; 7002 7003 static struct clk_branch gcc_usb4_0_phy_usb_pipe_clk = { 7004 .halt_reg = 0x2b0bc, 7005 .halt_check = BRANCH_HALT_SKIP, 7006 .hwcg_reg = 0x2b0bc, 7007 .hwcg_bit = 1, 7008 .clkr = { 7009 .enable_reg = 0x2b0bc, 7010 .enable_mask = BIT(0), 7011 .hw.init = &(const struct clk_init_data) { 7012 .name = "gcc_usb4_0_phy_usb_pipe_clk", 7013 .parent_hws = (const struct clk_hw*[]) { 7014 &gcc_usb34_prim_phy_pipe_clk_src.clkr.hw, 7015 }, 7016 .num_parents = 1, 7017 .flags = CLK_SET_RATE_PARENT, 7018 .ops = &clk_branch2_ops, 7019 }, 7020 }, 7021 }; 7022 7023 static struct clk_branch gcc_usb4_0_sb_if_clk = { 7024 .halt_reg = 0x2b048, 7025 .halt_check = BRANCH_HALT, 7026 .clkr = { 7027 .enable_reg = 0x2b048, 7028 .enable_mask = BIT(0), 7029 .hw.init = &(const struct clk_init_data) { 7030 .name = "gcc_usb4_0_sb_if_clk", 7031 .parent_hws = (const struct clk_hw*[]) { 7032 &gcc_usb4_0_sb_if_clk_src.clkr.hw, 7033 }, 7034 .num_parents = 1, 7035 .flags = CLK_SET_RATE_PARENT, 7036 .ops = &clk_branch2_ops, 7037 }, 7038 }, 7039 }; 7040 7041 static struct clk_branch gcc_usb4_0_sys_clk = { 7042 .halt_reg = 0x2b05c, 7043 .halt_check = BRANCH_HALT, 7044 .clkr = { 7045 .enable_reg = 0x2b05c, 7046 .enable_mask = BIT(0), 7047 .hw.init = &(const struct clk_init_data) { 7048 .name = "gcc_usb4_0_sys_clk", 7049 .parent_hws = (const struct clk_hw*[]) { 7050 &gcc_usb4_0_phy_sys_clk_src.clkr.hw, 7051 }, 7052 .num_parents = 1, 7053 .flags = CLK_SET_RATE_PARENT, 7054 .ops = &clk_branch2_ops, 7055 }, 7056 }, 7057 }; 7058 7059 static struct clk_branch gcc_usb4_0_tmu_clk = { 7060 .halt_reg = 0x2b09c, 7061 .halt_check = BRANCH_HALT_VOTED, 7062 .hwcg_reg = 0x2b09c, 7063 .hwcg_bit = 1, 7064 .clkr = { 7065 .enable_reg = 0x2b09c, 7066 .enable_mask = BIT(0), 7067 .hw.init = &(const struct clk_init_data) { 7068 .name = "gcc_usb4_0_tmu_clk", 7069 .parent_hws = (const struct clk_hw*[]) { 7070 &gcc_usb4_0_tmu_clk_src.clkr.hw, 7071 }, 7072 .num_parents = 1, 7073 .flags = CLK_SET_RATE_PARENT, 7074 .ops = &clk_branch2_ops, 7075 }, 7076 }, 7077 }; 7078 7079 static struct clk_branch gcc_usb4_0_uc_hrr_clk = { 7080 .halt_reg = 0x2b06c, 7081 .halt_check = BRANCH_HALT, 7082 .clkr = { 7083 .enable_reg = 0x2b06c, 7084 .enable_mask = BIT(0), 7085 .hw.init = &(const struct clk_init_data) { 7086 .name = "gcc_usb4_0_uc_hrr_clk", 7087 .parent_hws = (const struct clk_hw*[]) { 7088 &gcc_usb4_0_phy_sys_clk_src.clkr.hw, 7089 }, 7090 .num_parents = 1, 7091 .flags = CLK_SET_RATE_PARENT, 7092 .ops = &clk_branch2_ops, 7093 }, 7094 }, 7095 }; 7096 7097 static struct clk_branch gcc_usb4_1_cfg_ahb_clk = { 7098 .halt_reg = 0xba454, 7099 .halt_check = BRANCH_HALT_VOTED, 7100 .hwcg_reg = 0xba454, 7101 .hwcg_bit = 1, 7102 .clkr = { 7103 .enable_reg = 0xba454, 7104 .enable_mask = BIT(0), 7105 .hw.init = &(const struct clk_init_data) { 7106 .name = "gcc_usb4_1_cfg_ahb_clk", 7107 .ops = &clk_branch2_ops, 7108 }, 7109 }, 7110 }; 7111 7112 static struct clk_branch gcc_usb4_1_dp0_clk = { 7113 .halt_reg = 0x2d07c, 7114 .halt_check = BRANCH_HALT, 7115 .clkr = { 7116 .enable_reg = 0x2d07c, 7117 .enable_mask = BIT(0), 7118 .hw.init = &(const struct clk_init_data) { 7119 .name = "gcc_usb4_1_dp0_clk", 7120 .parent_hws = (const struct clk_hw*[]) { 7121 &gcc_usb4_1_phy_dp0_clk_src.clkr.hw, 7122 }, 7123 .num_parents = 1, 7124 .flags = CLK_SET_RATE_PARENT, 7125 .ops = &clk_branch2_ops, 7126 }, 7127 }, 7128 }; 7129 7130 static struct clk_branch gcc_usb4_1_dp1_clk = { 7131 .halt_reg = 0x2d144, 7132 .halt_check = BRANCH_HALT, 7133 .clkr = { 7134 .enable_reg = 0x2d144, 7135 .enable_mask = BIT(0), 7136 .hw.init = &(const struct clk_init_data) { 7137 .name = "gcc_usb4_1_dp1_clk", 7138 .parent_hws = (const struct clk_hw*[]) { 7139 &gcc_usb4_1_phy_dp1_clk_src.clkr.hw, 7140 }, 7141 .num_parents = 1, 7142 .flags = CLK_SET_RATE_PARENT, 7143 .ops = &clk_branch2_ops, 7144 }, 7145 }, 7146 }; 7147 7148 static struct clk_branch gcc_usb4_1_master_clk = { 7149 .halt_reg = 0x2d01c, 7150 .halt_check = BRANCH_HALT, 7151 .clkr = { 7152 .enable_reg = 0x2d01c, 7153 .enable_mask = BIT(0), 7154 .hw.init = &(const struct clk_init_data) { 7155 .name = "gcc_usb4_1_master_clk", 7156 .parent_hws = (const struct clk_hw*[]) { 7157 &gcc_usb4_1_master_clk_src.clkr.hw, 7158 }, 7159 .num_parents = 1, 7160 .flags = CLK_SET_RATE_PARENT, 7161 .ops = &clk_branch2_ops, 7162 }, 7163 }, 7164 }; 7165 7166 static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = { 7167 .halt_reg = 0x2d118, 7168 .halt_check = BRANCH_HALT_SKIP, 7169 .clkr = { 7170 .enable_reg = 0x2d118, 7171 .enable_mask = BIT(0), 7172 .hw.init = &(const struct clk_init_data) { 7173 .name = "gcc_usb4_1_phy_p2rr2p_pipe_clk", 7174 .parent_hws = (const struct clk_hw*[]) { 7175 &gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr.hw, 7176 }, 7177 .num_parents = 1, 7178 .flags = CLK_SET_RATE_PARENT, 7179 .ops = &clk_branch2_ops, 7180 }, 7181 }, 7182 }; 7183 7184 static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk = { 7185 .halt_reg = 0x2d04c, 7186 .halt_check = BRANCH_HALT_SKIP, 7187 .clkr = { 7188 .enable_reg = 0x62010, 7189 .enable_mask = BIT(12), 7190 .hw.init = &(const struct clk_init_data) { 7191 .name = "gcc_usb4_1_phy_pcie_pipe_clk", 7192 .parent_hws = (const struct clk_hw*[]) { 7193 &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw, 7194 }, 7195 .num_parents = 1, 7196 .flags = CLK_SET_RATE_PARENT, 7197 .ops = &clk_branch2_ops, 7198 }, 7199 }, 7200 }; 7201 7202 static struct clk_branch gcc_usb4_1_phy_rx0_clk = { 7203 .halt_reg = 0x2d0e8, 7204 .halt_check = BRANCH_HALT, 7205 .clkr = { 7206 .enable_reg = 0x2d0e8, 7207 .enable_mask = BIT(0), 7208 .hw.init = &(const struct clk_init_data) { 7209 .name = "gcc_usb4_1_phy_rx0_clk", 7210 .parent_hws = (const struct clk_hw*[]) { 7211 &gcc_usb4_1_phy_rx0_clk_src.clkr.hw, 7212 }, 7213 .num_parents = 1, 7214 .flags = CLK_SET_RATE_PARENT, 7215 .ops = &clk_branch2_ops, 7216 }, 7217 }, 7218 }; 7219 7220 static struct clk_branch gcc_usb4_1_phy_rx1_clk = { 7221 .halt_reg = 0x2d0fc, 7222 .halt_check = BRANCH_HALT, 7223 .clkr = { 7224 .enable_reg = 0x2d0fc, 7225 .enable_mask = BIT(0), 7226 .hw.init = &(const struct clk_init_data) { 7227 .name = "gcc_usb4_1_phy_rx1_clk", 7228 .parent_hws = (const struct clk_hw*[]) { 7229 &gcc_usb4_1_phy_rx1_clk_src.clkr.hw, 7230 }, 7231 .num_parents = 1, 7232 .flags = CLK_SET_RATE_PARENT, 7233 .ops = &clk_branch2_ops, 7234 }, 7235 }, 7236 }; 7237 7238 static struct clk_branch gcc_usb4_1_phy_usb_pipe_clk = { 7239 .halt_reg = 0x2d0e0, 7240 .halt_check = BRANCH_HALT_SKIP, 7241 .hwcg_reg = 0x2d0e0, 7242 .hwcg_bit = 1, 7243 .clkr = { 7244 .enable_reg = 0x2d0e0, 7245 .enable_mask = BIT(0), 7246 .hw.init = &(const struct clk_init_data) { 7247 .name = "gcc_usb4_1_phy_usb_pipe_clk", 7248 .parent_hws = (const struct clk_hw*[]) { 7249 &gcc_usb34_sec_phy_pipe_clk_src.clkr.hw, 7250 }, 7251 .num_parents = 1, 7252 .flags = CLK_SET_RATE_PARENT, 7253 .ops = &clk_branch2_ops, 7254 }, 7255 }, 7256 }; 7257 7258 static struct clk_branch gcc_usb4_1_sb_if_clk = { 7259 .halt_reg = 0x2d048, 7260 .halt_check = BRANCH_HALT, 7261 .clkr = { 7262 .enable_reg = 0x2d048, 7263 .enable_mask = BIT(0), 7264 .hw.init = &(const struct clk_init_data) { 7265 .name = "gcc_usb4_1_sb_if_clk", 7266 .parent_hws = (const struct clk_hw*[]) { 7267 &gcc_usb4_1_sb_if_clk_src.clkr.hw, 7268 }, 7269 .num_parents = 1, 7270 .flags = CLK_SET_RATE_PARENT, 7271 .ops = &clk_branch2_ops, 7272 }, 7273 }, 7274 }; 7275 7276 static struct clk_branch gcc_usb4_1_sys_clk = { 7277 .halt_reg = 0x2d05c, 7278 .halt_check = BRANCH_HALT, 7279 .clkr = { 7280 .enable_reg = 0x2d05c, 7281 .enable_mask = BIT(0), 7282 .hw.init = &(const struct clk_init_data) { 7283 .name = "gcc_usb4_1_sys_clk", 7284 .parent_hws = (const struct clk_hw*[]) { 7285 &gcc_usb4_1_phy_sys_clk_src.clkr.hw, 7286 }, 7287 .num_parents = 1, 7288 .flags = CLK_SET_RATE_PARENT, 7289 .ops = &clk_branch2_ops, 7290 }, 7291 }, 7292 }; 7293 7294 static struct clk_branch gcc_usb4_1_tmu_clk = { 7295 .halt_reg = 0x2d0a8, 7296 .halt_check = BRANCH_HALT_VOTED, 7297 .hwcg_reg = 0x2d0a8, 7298 .hwcg_bit = 1, 7299 .clkr = { 7300 .enable_reg = 0x2d0a8, 7301 .enable_mask = BIT(0), 7302 .hw.init = &(const struct clk_init_data) { 7303 .name = "gcc_usb4_1_tmu_clk", 7304 .parent_hws = (const struct clk_hw*[]) { 7305 &gcc_usb4_1_tmu_clk_src.clkr.hw, 7306 }, 7307 .num_parents = 1, 7308 .flags = CLK_SET_RATE_PARENT, 7309 .ops = &clk_branch2_ops, 7310 }, 7311 }, 7312 }; 7313 7314 static struct clk_branch gcc_usb4_1_uc_hrr_clk = { 7315 .halt_reg = 0x2d06c, 7316 .halt_check = BRANCH_HALT, 7317 .clkr = { 7318 .enable_reg = 0x2d06c, 7319 .enable_mask = BIT(0), 7320 .hw.init = &(const struct clk_init_data) { 7321 .name = "gcc_usb4_1_uc_hrr_clk", 7322 .parent_hws = (const struct clk_hw*[]) { 7323 &gcc_usb4_1_phy_sys_clk_src.clkr.hw, 7324 }, 7325 .num_parents = 1, 7326 .flags = CLK_SET_RATE_PARENT, 7327 .ops = &clk_branch2_ops, 7328 }, 7329 }, 7330 }; 7331 7332 static struct clk_branch gcc_usb4_2_cfg_ahb_clk = { 7333 .halt_reg = 0xba458, 7334 .halt_check = BRANCH_HALT_VOTED, 7335 .hwcg_reg = 0xba458, 7336 .hwcg_bit = 1, 7337 .clkr = { 7338 .enable_reg = 0xba458, 7339 .enable_mask = BIT(0), 7340 .hw.init = &(const struct clk_init_data) { 7341 .name = "gcc_usb4_2_cfg_ahb_clk", 7342 .ops = &clk_branch2_ops, 7343 }, 7344 }, 7345 }; 7346 7347 static struct clk_branch gcc_usb4_2_dp0_clk = { 7348 .halt_reg = 0xe0070, 7349 .halt_check = BRANCH_HALT, 7350 .clkr = { 7351 .enable_reg = 0xe0070, 7352 .enable_mask = BIT(0), 7353 .hw.init = &(const struct clk_init_data) { 7354 .name = "gcc_usb4_2_dp0_clk", 7355 .parent_hws = (const struct clk_hw*[]) { 7356 &gcc_usb4_2_phy_dp0_clk_src.clkr.hw, 7357 }, 7358 .num_parents = 1, 7359 .flags = CLK_SET_RATE_PARENT, 7360 .ops = &clk_branch2_ops, 7361 }, 7362 }, 7363 }; 7364 7365 static struct clk_branch gcc_usb4_2_dp1_clk = { 7366 .halt_reg = 0xe0128, 7367 .halt_check = BRANCH_HALT, 7368 .clkr = { 7369 .enable_reg = 0xe0128, 7370 .enable_mask = BIT(0), 7371 .hw.init = &(const struct clk_init_data) { 7372 .name = "gcc_usb4_2_dp1_clk", 7373 .parent_hws = (const struct clk_hw*[]) { 7374 &gcc_usb4_2_phy_dp1_clk_src.clkr.hw, 7375 }, 7376 .num_parents = 1, 7377 .flags = CLK_SET_RATE_PARENT, 7378 .ops = &clk_branch2_ops, 7379 }, 7380 }, 7381 }; 7382 7383 static struct clk_branch gcc_usb4_2_master_clk = { 7384 .halt_reg = 0xe001c, 7385 .halt_check = BRANCH_HALT, 7386 .clkr = { 7387 .enable_reg = 0xe001c, 7388 .enable_mask = BIT(0), 7389 .hw.init = &(const struct clk_init_data) { 7390 .name = "gcc_usb4_2_master_clk", 7391 .parent_hws = (const struct clk_hw*[]) { 7392 &gcc_usb4_2_master_clk_src.clkr.hw, 7393 }, 7394 .num_parents = 1, 7395 .flags = CLK_SET_RATE_PARENT, 7396 .ops = &clk_branch2_ops, 7397 }, 7398 }, 7399 }; 7400 7401 static struct clk_branch gcc_usb4_2_phy_p2rr2p_pipe_clk = { 7402 .halt_reg = 0xe00f8, 7403 .halt_check = BRANCH_HALT_SKIP, 7404 .clkr = { 7405 .enable_reg = 0xe00f8, 7406 .enable_mask = BIT(0), 7407 .hw.init = &(const struct clk_init_data) { 7408 .name = "gcc_usb4_2_phy_p2rr2p_pipe_clk", 7409 .parent_hws = (const struct clk_hw*[]) { 7410 &gcc_usb4_2_phy_p2rr2p_pipe_clk_src.clkr.hw, 7411 }, 7412 .num_parents = 1, 7413 .flags = CLK_SET_RATE_PARENT, 7414 .ops = &clk_branch2_ops, 7415 }, 7416 }, 7417 }; 7418 7419 static struct clk_branch gcc_usb4_2_phy_pcie_pipe_clk = { 7420 .halt_reg = 0xe004c, 7421 .halt_check = BRANCH_HALT_SKIP, 7422 .clkr = { 7423 .enable_reg = 0x62010, 7424 .enable_mask = BIT(13), 7425 .hw.init = &(const struct clk_init_data) { 7426 .name = "gcc_usb4_2_phy_pcie_pipe_clk", 7427 .parent_hws = (const struct clk_hw*[]) { 7428 &gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr.hw, 7429 }, 7430 .num_parents = 1, 7431 .flags = CLK_SET_RATE_PARENT, 7432 .ops = &clk_branch2_ops, 7433 }, 7434 }, 7435 }; 7436 7437 static struct clk_branch gcc_usb4_2_phy_rx0_clk = { 7438 .halt_reg = 0xe00c8, 7439 .halt_check = BRANCH_HALT, 7440 .clkr = { 7441 .enable_reg = 0xe00c8, 7442 .enable_mask = BIT(0), 7443 .hw.init = &(const struct clk_init_data) { 7444 .name = "gcc_usb4_2_phy_rx0_clk", 7445 .parent_hws = (const struct clk_hw*[]) { 7446 &gcc_usb4_2_phy_rx0_clk_src.clkr.hw, 7447 }, 7448 .num_parents = 1, 7449 .flags = CLK_SET_RATE_PARENT, 7450 .ops = &clk_branch2_ops, 7451 }, 7452 }, 7453 }; 7454 7455 static struct clk_branch gcc_usb4_2_phy_rx1_clk = { 7456 .halt_reg = 0xe00dc, 7457 .halt_check = BRANCH_HALT, 7458 .clkr = { 7459 .enable_reg = 0xe00dc, 7460 .enable_mask = BIT(0), 7461 .hw.init = &(const struct clk_init_data) { 7462 .name = "gcc_usb4_2_phy_rx1_clk", 7463 .parent_hws = (const struct clk_hw*[]) { 7464 &gcc_usb4_2_phy_rx1_clk_src.clkr.hw, 7465 }, 7466 .num_parents = 1, 7467 .flags = CLK_SET_RATE_PARENT, 7468 .ops = &clk_branch2_ops, 7469 }, 7470 }, 7471 }; 7472 7473 static struct clk_branch gcc_usb4_2_phy_usb_pipe_clk = { 7474 .halt_reg = 0xe00c0, 7475 .halt_check = BRANCH_HALT_SKIP, 7476 .hwcg_reg = 0xe00c0, 7477 .hwcg_bit = 1, 7478 .clkr = { 7479 .enable_reg = 0xe00c0, 7480 .enable_mask = BIT(0), 7481 .hw.init = &(const struct clk_init_data) { 7482 .name = "gcc_usb4_2_phy_usb_pipe_clk", 7483 .parent_hws = (const struct clk_hw*[]) { 7484 &gcc_usb34_tert_phy_pipe_clk_src.clkr.hw, 7485 }, 7486 .num_parents = 1, 7487 .flags = CLK_SET_RATE_PARENT, 7488 .ops = &clk_branch2_ops, 7489 }, 7490 }, 7491 }; 7492 7493 static struct clk_branch gcc_usb4_2_sb_if_clk = { 7494 .halt_reg = 0xe0048, 7495 .halt_check = BRANCH_HALT, 7496 .clkr = { 7497 .enable_reg = 0xe0048, 7498 .enable_mask = BIT(0), 7499 .hw.init = &(const struct clk_init_data) { 7500 .name = "gcc_usb4_2_sb_if_clk", 7501 .parent_hws = (const struct clk_hw*[]) { 7502 &gcc_usb4_2_sb_if_clk_src.clkr.hw, 7503 }, 7504 .num_parents = 1, 7505 .flags = CLK_SET_RATE_PARENT, 7506 .ops = &clk_branch2_ops, 7507 }, 7508 }, 7509 }; 7510 7511 static struct clk_branch gcc_usb4_2_sys_clk = { 7512 .halt_reg = 0xe005c, 7513 .halt_check = BRANCH_HALT, 7514 .clkr = { 7515 .enable_reg = 0xe005c, 7516 .enable_mask = BIT(0), 7517 .hw.init = &(const struct clk_init_data) { 7518 .name = "gcc_usb4_2_sys_clk", 7519 .parent_hws = (const struct clk_hw*[]) { 7520 &gcc_usb4_2_phy_sys_clk_src.clkr.hw, 7521 }, 7522 .num_parents = 1, 7523 .flags = CLK_SET_RATE_PARENT, 7524 .ops = &clk_branch2_ops, 7525 }, 7526 }, 7527 }; 7528 7529 static struct clk_branch gcc_usb4_2_tmu_clk = { 7530 .halt_reg = 0xe00a0, 7531 .halt_check = BRANCH_HALT_VOTED, 7532 .hwcg_reg = 0xe00a0, 7533 .hwcg_bit = 1, 7534 .clkr = { 7535 .enable_reg = 0xe00a0, 7536 .enable_mask = BIT(0), 7537 .hw.init = &(const struct clk_init_data) { 7538 .name = "gcc_usb4_2_tmu_clk", 7539 .parent_hws = (const struct clk_hw*[]) { 7540 &gcc_usb4_2_tmu_clk_src.clkr.hw, 7541 }, 7542 .num_parents = 1, 7543 .flags = CLK_SET_RATE_PARENT, 7544 .ops = &clk_branch2_ops, 7545 }, 7546 }, 7547 }; 7548 7549 static struct clk_branch gcc_usb4_2_uc_hrr_clk = { 7550 .halt_reg = 0xe006c, 7551 .halt_check = BRANCH_HALT, 7552 .clkr = { 7553 .enable_reg = 0xe006c, 7554 .enable_mask = BIT(0), 7555 .hw.init = &(const struct clk_init_data) { 7556 .name = "gcc_usb4_2_uc_hrr_clk", 7557 .parent_hws = (const struct clk_hw*[]) { 7558 &gcc_usb4_2_phy_sys_clk_src.clkr.hw, 7559 }, 7560 .num_parents = 1, 7561 .flags = CLK_SET_RATE_PARENT, 7562 .ops = &clk_branch2_ops, 7563 }, 7564 }, 7565 }; 7566 7567 static struct clk_branch gcc_video_axi0_clk = { 7568 .halt_reg = 0x3201c, 7569 .halt_check = BRANCH_HALT_SKIP, 7570 .hwcg_reg = 0x3201c, 7571 .hwcg_bit = 1, 7572 .clkr = { 7573 .enable_reg = 0x3201c, 7574 .enable_mask = BIT(0), 7575 .hw.init = &(const struct clk_init_data) { 7576 .name = "gcc_video_axi0_clk", 7577 .ops = &clk_branch2_ops, 7578 }, 7579 }, 7580 }; 7581 7582 static struct clk_branch gcc_video_axi0c_clk = { 7583 .halt_reg = 0x32030, 7584 .halt_check = BRANCH_HALT_SKIP, 7585 .hwcg_reg = 0x32030, 7586 .hwcg_bit = 1, 7587 .clkr = { 7588 .enable_reg = 0x32030, 7589 .enable_mask = BIT(0), 7590 .hw.init = &(const struct clk_init_data) { 7591 .name = "gcc_video_axi0c_clk", 7592 .ops = &clk_branch2_ops, 7593 }, 7594 }, 7595 }; 7596 7597 static struct clk_branch gcc_video_axi1_clk = { 7598 .halt_reg = 0x32044, 7599 .halt_check = BRANCH_HALT_SKIP, 7600 .hwcg_reg = 0x32044, 7601 .hwcg_bit = 1, 7602 .clkr = { 7603 .enable_reg = 0x32044, 7604 .enable_mask = BIT(0), 7605 .hw.init = &(const struct clk_init_data) { 7606 .name = "gcc_video_axi1_clk", 7607 .ops = &clk_branch2_ops, 7608 }, 7609 }, 7610 }; 7611 7612 static struct gdsc gcc_pcie_0_tunnel_gdsc = { 7613 .gdscr = 0xc8004, 7614 .en_rest_wait_val = 0x2, 7615 .en_few_wait_val = 0x2, 7616 .clk_dis_wait_val = 0xf, 7617 .pd = { 7618 .name = "gcc_pcie_0_tunnel_gdsc", 7619 }, 7620 .pwrsts = PWRSTS_OFF_ON, 7621 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7622 }; 7623 7624 static struct gdsc gcc_pcie_1_tunnel_gdsc = { 7625 .gdscr = 0x2e004, 7626 .en_rest_wait_val = 0x2, 7627 .en_few_wait_val = 0x2, 7628 .clk_dis_wait_val = 0xf, 7629 .pd = { 7630 .name = "gcc_pcie_1_tunnel_gdsc", 7631 }, 7632 .pwrsts = PWRSTS_OFF_ON, 7633 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7634 }; 7635 7636 static struct gdsc gcc_pcie_2_tunnel_gdsc = { 7637 .gdscr = 0xc0004, 7638 .en_rest_wait_val = 0x2, 7639 .en_few_wait_val = 0x2, 7640 .clk_dis_wait_val = 0xf, 7641 .pd = { 7642 .name = "gcc_pcie_2_tunnel_gdsc", 7643 }, 7644 .pwrsts = PWRSTS_OFF_ON, 7645 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7646 }; 7647 7648 static struct gdsc gcc_pcie_3a_gdsc = { 7649 .gdscr = 0xdc004, 7650 .en_rest_wait_val = 0x2, 7651 .en_few_wait_val = 0x2, 7652 .clk_dis_wait_val = 0xf, 7653 .pd = { 7654 .name = "gcc_pcie_3a_gdsc", 7655 }, 7656 .pwrsts = PWRSTS_OFF_ON, 7657 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7658 }; 7659 7660 static struct gdsc gcc_pcie_3a_phy_gdsc = { 7661 .gdscr = 0x6c004, 7662 .en_rest_wait_val = 0x2, 7663 .en_few_wait_val = 0x2, 7664 .clk_dis_wait_val = 0x2, 7665 .pd = { 7666 .name = "gcc_pcie_3a_phy_gdsc", 7667 }, 7668 .pwrsts = PWRSTS_OFF_ON, 7669 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7670 }; 7671 7672 static struct gdsc gcc_pcie_3b_gdsc = { 7673 .gdscr = 0x94004, 7674 .en_rest_wait_val = 0x2, 7675 .en_few_wait_val = 0x2, 7676 .clk_dis_wait_val = 0xf, 7677 .pd = { 7678 .name = "gcc_pcie_3b_gdsc", 7679 }, 7680 .pwrsts = PWRSTS_OFF_ON, 7681 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7682 }; 7683 7684 static struct gdsc gcc_pcie_3b_phy_gdsc = { 7685 .gdscr = 0x75004, 7686 .en_rest_wait_val = 0x2, 7687 .en_few_wait_val = 0x2, 7688 .clk_dis_wait_val = 0x2, 7689 .pd = { 7690 .name = "gcc_pcie_3b_phy_gdsc", 7691 }, 7692 .pwrsts = PWRSTS_OFF_ON, 7693 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7694 }; 7695 7696 static struct gdsc gcc_pcie_4_gdsc = { 7697 .gdscr = 0x88004, 7698 .en_rest_wait_val = 0x2, 7699 .en_few_wait_val = 0x2, 7700 .clk_dis_wait_val = 0xf, 7701 .pd = { 7702 .name = "gcc_pcie_4_gdsc", 7703 }, 7704 .pwrsts = PWRSTS_OFF_ON, 7705 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7706 }; 7707 7708 static struct gdsc gcc_pcie_4_phy_gdsc = { 7709 .gdscr = 0xd3004, 7710 .en_rest_wait_val = 0x2, 7711 .en_few_wait_val = 0x2, 7712 .clk_dis_wait_val = 0x2, 7713 .pd = { 7714 .name = "gcc_pcie_4_phy_gdsc", 7715 }, 7716 .pwrsts = PWRSTS_OFF_ON, 7717 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7718 }; 7719 7720 static struct gdsc gcc_pcie_5_gdsc = { 7721 .gdscr = 0xc3004, 7722 .en_rest_wait_val = 0x2, 7723 .en_few_wait_val = 0x2, 7724 .clk_dis_wait_val = 0xf, 7725 .pd = { 7726 .name = "gcc_pcie_5_gdsc", 7727 }, 7728 .pwrsts = PWRSTS_OFF_ON, 7729 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7730 }; 7731 7732 static struct gdsc gcc_pcie_5_phy_gdsc = { 7733 .gdscr = 0xd2004, 7734 .en_rest_wait_val = 0x2, 7735 .en_few_wait_val = 0x2, 7736 .clk_dis_wait_val = 0x2, 7737 .pd = { 7738 .name = "gcc_pcie_5_phy_gdsc", 7739 }, 7740 .pwrsts = PWRSTS_OFF_ON, 7741 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7742 }; 7743 7744 static struct gdsc gcc_pcie_6_gdsc = { 7745 .gdscr = 0x8a004, 7746 .en_rest_wait_val = 0x2, 7747 .en_few_wait_val = 0x2, 7748 .clk_dis_wait_val = 0xf, 7749 .pd = { 7750 .name = "gcc_pcie_6_gdsc", 7751 }, 7752 .pwrsts = PWRSTS_OFF_ON, 7753 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7754 }; 7755 7756 static struct gdsc gcc_pcie_6_phy_gdsc = { 7757 .gdscr = 0xd4004, 7758 .en_rest_wait_val = 0x2, 7759 .en_few_wait_val = 0x2, 7760 .clk_dis_wait_val = 0x2, 7761 .pd = { 7762 .name = "gcc_pcie_6_phy_gdsc", 7763 }, 7764 .pwrsts = PWRSTS_OFF_ON, 7765 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 7766 }; 7767 7768 static struct gdsc gcc_ufs_phy_gdsc = { 7769 .gdscr = 0x77008, 7770 .en_rest_wait_val = 0x2, 7771 .en_few_wait_val = 0x2, 7772 .clk_dis_wait_val = 0xf, 7773 .pd = { 7774 .name = "gcc_ufs_phy_gdsc", 7775 }, 7776 .pwrsts = PWRSTS_OFF_ON, 7777 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7778 }; 7779 7780 static struct gdsc gcc_usb20_prim_gdsc = { 7781 .gdscr = 0xbc004, 7782 .en_rest_wait_val = 0x2, 7783 .en_few_wait_val = 0x2, 7784 .clk_dis_wait_val = 0xf, 7785 .pd = { 7786 .name = "gcc_usb20_prim_gdsc", 7787 }, 7788 .pwrsts = PWRSTS_OFF_ON, 7789 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7790 }; 7791 7792 static struct gdsc gcc_usb30_mp_gdsc = { 7793 .gdscr = 0x9a010, 7794 .en_rest_wait_val = 0x2, 7795 .en_few_wait_val = 0x2, 7796 .clk_dis_wait_val = 0xf, 7797 .pd = { 7798 .name = "gcc_usb30_mp_gdsc", 7799 }, 7800 .pwrsts = PWRSTS_OFF_ON, 7801 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7802 }; 7803 7804 static struct gdsc gcc_usb30_prim_gdsc = { 7805 .gdscr = 0x3f01c, 7806 .en_rest_wait_val = 0x2, 7807 .en_few_wait_val = 0x2, 7808 .clk_dis_wait_val = 0xf, 7809 .pd = { 7810 .name = "gcc_usb30_prim_gdsc", 7811 }, 7812 .pwrsts = PWRSTS_OFF_ON, 7813 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7814 }; 7815 7816 static struct gdsc gcc_usb30_sec_gdsc = { 7817 .gdscr = 0xe2010, 7818 .en_rest_wait_val = 0x2, 7819 .en_few_wait_val = 0x2, 7820 .clk_dis_wait_val = 0xf, 7821 .pd = { 7822 .name = "gcc_usb30_sec_gdsc", 7823 }, 7824 .pwrsts = PWRSTS_OFF_ON, 7825 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7826 }; 7827 7828 static struct gdsc gcc_usb30_tert_gdsc = { 7829 .gdscr = 0xe1010, 7830 .en_rest_wait_val = 0x2, 7831 .en_few_wait_val = 0x2, 7832 .clk_dis_wait_val = 0xf, 7833 .pd = { 7834 .name = "gcc_usb30_tert_gdsc", 7835 }, 7836 .pwrsts = PWRSTS_OFF_ON, 7837 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7838 }; 7839 7840 static struct gdsc gcc_usb3_mp_ss0_phy_gdsc = { 7841 .gdscr = 0x5400c, 7842 .en_rest_wait_val = 0x2, 7843 .en_few_wait_val = 0x2, 7844 .clk_dis_wait_val = 0x2, 7845 .pd = { 7846 .name = "gcc_usb3_mp_ss0_phy_gdsc", 7847 }, 7848 .pwrsts = PWRSTS_OFF_ON, 7849 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7850 }; 7851 7852 static struct gdsc gcc_usb3_mp_ss1_phy_gdsc = { 7853 .gdscr = 0x5402c, 7854 .en_rest_wait_val = 0x2, 7855 .en_few_wait_val = 0x2, 7856 .clk_dis_wait_val = 0x2, 7857 .pd = { 7858 .name = "gcc_usb3_mp_ss1_phy_gdsc", 7859 }, 7860 .pwrsts = PWRSTS_OFF_ON, 7861 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7862 }; 7863 7864 static struct gdsc gcc_usb4_0_gdsc = { 7865 .gdscr = 0x2b008, 7866 .en_rest_wait_val = 0x2, 7867 .en_few_wait_val = 0x2, 7868 .clk_dis_wait_val = 0xf, 7869 .pd = { 7870 .name = "gcc_usb4_0_gdsc", 7871 }, 7872 .pwrsts = PWRSTS_OFF_ON, 7873 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7874 }; 7875 7876 static struct gdsc gcc_usb4_1_gdsc = { 7877 .gdscr = 0x2d008, 7878 .en_rest_wait_val = 0x2, 7879 .en_few_wait_val = 0x2, 7880 .clk_dis_wait_val = 0xf, 7881 .pd = { 7882 .name = "gcc_usb4_1_gdsc", 7883 }, 7884 .pwrsts = PWRSTS_OFF_ON, 7885 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7886 }; 7887 7888 static struct gdsc gcc_usb4_2_gdsc = { 7889 .gdscr = 0xe0008, 7890 .en_rest_wait_val = 0x2, 7891 .en_few_wait_val = 0x2, 7892 .clk_dis_wait_val = 0xf, 7893 .pd = { 7894 .name = "gcc_usb4_2_gdsc", 7895 }, 7896 .pwrsts = PWRSTS_OFF_ON, 7897 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7898 }; 7899 7900 static struct gdsc gcc_usb_0_phy_gdsc = { 7901 .gdscr = 0xdb024, 7902 .en_rest_wait_val = 0x2, 7903 .en_few_wait_val = 0x2, 7904 .clk_dis_wait_val = 0x2, 7905 .pd = { 7906 .name = "gcc_usb_0_phy_gdsc", 7907 }, 7908 .pwrsts = PWRSTS_OFF_ON, 7909 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7910 }; 7911 7912 static struct gdsc gcc_usb_1_phy_gdsc = { 7913 .gdscr = 0x2c024, 7914 .en_rest_wait_val = 0x2, 7915 .en_few_wait_val = 0x2, 7916 .clk_dis_wait_val = 0x2, 7917 .pd = { 7918 .name = "gcc_usb_1_phy_gdsc", 7919 }, 7920 .pwrsts = PWRSTS_OFF_ON, 7921 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7922 }; 7923 7924 static struct gdsc gcc_usb_2_phy_gdsc = { 7925 .gdscr = 0xbe024, 7926 .en_rest_wait_val = 0x2, 7927 .en_few_wait_val = 0x2, 7928 .clk_dis_wait_val = 0x2, 7929 .pd = { 7930 .name = "gcc_usb_2_phy_gdsc", 7931 }, 7932 .pwrsts = PWRSTS_OFF_ON, 7933 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 7934 }; 7935 7936 static struct clk_regmap *gcc_glymur_clocks[] = { 7937 [GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK] = &gcc_aggre_noc_pcie_3a_west_sf_axi_clk.clkr, 7938 [GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK] = &gcc_aggre_noc_pcie_3b_west_sf_axi_clk.clkr, 7939 [GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK] = &gcc_aggre_noc_pcie_4_west_sf_axi_clk.clkr, 7940 [GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK] = &gcc_aggre_noc_pcie_5_east_sf_axi_clk.clkr, 7941 [GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK] = &gcc_aggre_noc_pcie_6_west_sf_axi_clk.clkr, 7942 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 7943 [GCC_AGGRE_USB2_PRIM_AXI_CLK] = &gcc_aggre_usb2_prim_axi_clk.clkr, 7944 [GCC_AGGRE_USB3_MP_AXI_CLK] = &gcc_aggre_usb3_mp_axi_clk.clkr, 7945 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 7946 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, 7947 [GCC_AGGRE_USB3_TERT_AXI_CLK] = &gcc_aggre_usb3_tert_axi_clk.clkr, 7948 [GCC_AGGRE_USB4_0_AXI_CLK] = &gcc_aggre_usb4_0_axi_clk.clkr, 7949 [GCC_AGGRE_USB4_1_AXI_CLK] = &gcc_aggre_usb4_1_axi_clk.clkr, 7950 [GCC_AGGRE_USB4_2_AXI_CLK] = &gcc_aggre_usb4_2_axi_clk.clkr, 7951 [GCC_AV1E_AHB_CLK] = &gcc_av1e_ahb_clk.clkr, 7952 [GCC_AV1E_AXI_CLK] = &gcc_av1e_axi_clk.clkr, 7953 [GCC_AV1E_XO_CLK] = &gcc_av1e_xo_clk.clkr, 7954 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 7955 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 7956 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 7957 [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr, 7958 [GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_south_ahb_clk.clkr, 7959 [GCC_CFG_NOC_USB2_PRIM_AXI_CLK] = &gcc_cfg_noc_usb2_prim_axi_clk.clkr, 7960 [GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr, 7961 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 7962 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, 7963 [GCC_CFG_NOC_USB3_TERT_AXI_CLK] = &gcc_cfg_noc_usb3_tert_axi_clk.clkr, 7964 [GCC_CFG_NOC_USB_ANOC_AHB_CLK] = &gcc_cfg_noc_usb_anoc_ahb_clk.clkr, 7965 [GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK] = &gcc_cfg_noc_usb_anoc_south_ahb_clk.clkr, 7966 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 7967 [GCC_EVA_AXI0_CLK] = &gcc_eva_axi0_clk.clkr, 7968 [GCC_EVA_AXI0C_CLK] = &gcc_eva_axi0c_clk.clkr, 7969 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 7970 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 7971 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 7972 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 7973 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 7974 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 7975 [GCC_GPLL0] = &gcc_gpll0.clkr, 7976 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 7977 [GCC_GPLL1] = &gcc_gpll1.clkr, 7978 [GCC_GPLL14] = &gcc_gpll14.clkr, 7979 [GCC_GPLL14_OUT_EVEN] = &gcc_gpll14_out_even.clkr, 7980 [GCC_GPLL4] = &gcc_gpll4.clkr, 7981 [GCC_GPLL5] = &gcc_gpll5.clkr, 7982 [GCC_GPLL7] = &gcc_gpll7.clkr, 7983 [GCC_GPLL8] = &gcc_gpll8.clkr, 7984 [GCC_GPLL9] = &gcc_gpll9.clkr, 7985 [GCC_GPU_GEMNOC_GFX_CLK] = &gcc_gpu_gemnoc_gfx_clk.clkr, 7986 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 7987 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 7988 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 7989 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 7990 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 7991 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 7992 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 7993 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 7994 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 7995 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 7996 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 7997 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 7998 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 7999 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 8000 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 8001 [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr, 8002 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, 8003 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 8004 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 8005 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 8006 [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr, 8007 [GCC_PCIE_2_AUX_CLK_SRC] = &gcc_pcie_2_aux_clk_src.clkr, 8008 [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr, 8009 [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr, 8010 [GCC_PCIE_2_PHY_RCHNG_CLK] = &gcc_pcie_2_phy_rchng_clk.clkr, 8011 [GCC_PCIE_2_PHY_RCHNG_CLK_SRC] = &gcc_pcie_2_phy_rchng_clk_src.clkr, 8012 [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr, 8013 [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr, 8014 [GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr, 8015 [GCC_PCIE_3A_AUX_CLK] = &gcc_pcie_3a_aux_clk.clkr, 8016 [GCC_PCIE_3A_AUX_CLK_SRC] = &gcc_pcie_3a_aux_clk_src.clkr, 8017 [GCC_PCIE_3A_CFG_AHB_CLK] = &gcc_pcie_3a_cfg_ahb_clk.clkr, 8018 [GCC_PCIE_3A_MSTR_AXI_CLK] = &gcc_pcie_3a_mstr_axi_clk.clkr, 8019 [GCC_PCIE_3A_PHY_RCHNG_CLK] = &gcc_pcie_3a_phy_rchng_clk.clkr, 8020 [GCC_PCIE_3A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_3a_phy_rchng_clk_src.clkr, 8021 [GCC_PCIE_3A_PIPE_CLK] = &gcc_pcie_3a_pipe_clk.clkr, 8022 [GCC_PCIE_3A_PIPE_CLK_SRC] = &gcc_pcie_3a_pipe_clk_src.clkr, 8023 [GCC_PCIE_3A_SLV_AXI_CLK] = &gcc_pcie_3a_slv_axi_clk.clkr, 8024 [GCC_PCIE_3A_SLV_Q2A_AXI_CLK] = &gcc_pcie_3a_slv_q2a_axi_clk.clkr, 8025 [GCC_PCIE_3B_AUX_CLK] = &gcc_pcie_3b_aux_clk.clkr, 8026 [GCC_PCIE_3B_AUX_CLK_SRC] = &gcc_pcie_3b_aux_clk_src.clkr, 8027 [GCC_PCIE_3B_CFG_AHB_CLK] = &gcc_pcie_3b_cfg_ahb_clk.clkr, 8028 [GCC_PCIE_3B_MSTR_AXI_CLK] = &gcc_pcie_3b_mstr_axi_clk.clkr, 8029 [GCC_PCIE_3B_PHY_RCHNG_CLK] = &gcc_pcie_3b_phy_rchng_clk.clkr, 8030 [GCC_PCIE_3B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_3b_phy_rchng_clk_src.clkr, 8031 [GCC_PCIE_3B_PIPE_CLK] = &gcc_pcie_3b_pipe_clk.clkr, 8032 [GCC_PCIE_3B_PIPE_CLK_SRC] = &gcc_pcie_3b_pipe_clk_src.clkr, 8033 [GCC_PCIE_3B_PIPE_DIV2_CLK] = &gcc_pcie_3b_pipe_div2_clk.clkr, 8034 [GCC_PCIE_3B_PIPE_DIV_CLK_SRC] = &gcc_pcie_3b_pipe_div_clk_src.clkr, 8035 [GCC_PCIE_3B_SLV_AXI_CLK] = &gcc_pcie_3b_slv_axi_clk.clkr, 8036 [GCC_PCIE_3B_SLV_Q2A_AXI_CLK] = &gcc_pcie_3b_slv_q2a_axi_clk.clkr, 8037 [GCC_PCIE_4_AUX_CLK] = &gcc_pcie_4_aux_clk.clkr, 8038 [GCC_PCIE_4_AUX_CLK_SRC] = &gcc_pcie_4_aux_clk_src.clkr, 8039 [GCC_PCIE_4_CFG_AHB_CLK] = &gcc_pcie_4_cfg_ahb_clk.clkr, 8040 [GCC_PCIE_4_MSTR_AXI_CLK] = &gcc_pcie_4_mstr_axi_clk.clkr, 8041 [GCC_PCIE_4_PHY_RCHNG_CLK] = &gcc_pcie_4_phy_rchng_clk.clkr, 8042 [GCC_PCIE_4_PHY_RCHNG_CLK_SRC] = &gcc_pcie_4_phy_rchng_clk_src.clkr, 8043 [GCC_PCIE_4_PIPE_CLK] = &gcc_pcie_4_pipe_clk.clkr, 8044 [GCC_PCIE_4_PIPE_CLK_SRC] = &gcc_pcie_4_pipe_clk_src.clkr, 8045 [GCC_PCIE_4_PIPE_DIV2_CLK] = &gcc_pcie_4_pipe_div2_clk.clkr, 8046 [GCC_PCIE_4_PIPE_DIV_CLK_SRC] = &gcc_pcie_4_pipe_div_clk_src.clkr, 8047 [GCC_PCIE_4_SLV_AXI_CLK] = &gcc_pcie_4_slv_axi_clk.clkr, 8048 [GCC_PCIE_4_SLV_Q2A_AXI_CLK] = &gcc_pcie_4_slv_q2a_axi_clk.clkr, 8049 [GCC_PCIE_5_AUX_CLK] = &gcc_pcie_5_aux_clk.clkr, 8050 [GCC_PCIE_5_AUX_CLK_SRC] = &gcc_pcie_5_aux_clk_src.clkr, 8051 [GCC_PCIE_5_CFG_AHB_CLK] = &gcc_pcie_5_cfg_ahb_clk.clkr, 8052 [GCC_PCIE_5_MSTR_AXI_CLK] = &gcc_pcie_5_mstr_axi_clk.clkr, 8053 [GCC_PCIE_5_PHY_RCHNG_CLK] = &gcc_pcie_5_phy_rchng_clk.clkr, 8054 [GCC_PCIE_5_PHY_RCHNG_CLK_SRC] = &gcc_pcie_5_phy_rchng_clk_src.clkr, 8055 [GCC_PCIE_5_PIPE_CLK] = &gcc_pcie_5_pipe_clk.clkr, 8056 [GCC_PCIE_5_PIPE_CLK_SRC] = &gcc_pcie_5_pipe_clk_src.clkr, 8057 [GCC_PCIE_5_PIPE_DIV2_CLK] = &gcc_pcie_5_pipe_div2_clk.clkr, 8058 [GCC_PCIE_5_PIPE_DIV_CLK_SRC] = &gcc_pcie_5_pipe_div_clk_src.clkr, 8059 [GCC_PCIE_5_SLV_AXI_CLK] = &gcc_pcie_5_slv_axi_clk.clkr, 8060 [GCC_PCIE_5_SLV_Q2A_AXI_CLK] = &gcc_pcie_5_slv_q2a_axi_clk.clkr, 8061 [GCC_PCIE_6_AUX_CLK] = &gcc_pcie_6_aux_clk.clkr, 8062 [GCC_PCIE_6_AUX_CLK_SRC] = &gcc_pcie_6_aux_clk_src.clkr, 8063 [GCC_PCIE_6_CFG_AHB_CLK] = &gcc_pcie_6_cfg_ahb_clk.clkr, 8064 [GCC_PCIE_6_MSTR_AXI_CLK] = &gcc_pcie_6_mstr_axi_clk.clkr, 8065 [GCC_PCIE_6_PHY_RCHNG_CLK] = &gcc_pcie_6_phy_rchng_clk.clkr, 8066 [GCC_PCIE_6_PHY_RCHNG_CLK_SRC] = &gcc_pcie_6_phy_rchng_clk_src.clkr, 8067 [GCC_PCIE_6_PIPE_CLK] = &gcc_pcie_6_pipe_clk.clkr, 8068 [GCC_PCIE_6_PIPE_CLK_SRC] = &gcc_pcie_6_pipe_clk_src.clkr, 8069 [GCC_PCIE_6_PIPE_DIV2_CLK] = &gcc_pcie_6_pipe_div2_clk.clkr, 8070 [GCC_PCIE_6_PIPE_DIV_CLK_SRC] = &gcc_pcie_6_pipe_div_clk_src.clkr, 8071 [GCC_PCIE_6_SLV_AXI_CLK] = &gcc_pcie_6_slv_axi_clk.clkr, 8072 [GCC_PCIE_6_SLV_Q2A_AXI_CLK] = &gcc_pcie_6_slv_q2a_axi_clk.clkr, 8073 [GCC_PCIE_NOC_PWRCTL_CLK] = &gcc_pcie_noc_pwrctl_clk.clkr, 8074 [GCC_PCIE_NOC_QOSGEN_EXTREF_CLK] = &gcc_pcie_noc_qosgen_extref_clk.clkr, 8075 [GCC_PCIE_NOC_SF_CENTER_CLK] = &gcc_pcie_noc_sf_center_clk.clkr, 8076 [GCC_PCIE_NOC_SLAVE_SF_EAST_CLK] = &gcc_pcie_noc_slave_sf_east_clk.clkr, 8077 [GCC_PCIE_NOC_SLAVE_SF_WEST_CLK] = &gcc_pcie_noc_slave_sf_west_clk.clkr, 8078 [GCC_PCIE_NOC_TSCTR_CLK] = &gcc_pcie_noc_tsctr_clk.clkr, 8079 [GCC_PCIE_PHY_3A_AUX_CLK] = &gcc_pcie_phy_3a_aux_clk.clkr, 8080 [GCC_PCIE_PHY_3A_AUX_CLK_SRC] = &gcc_pcie_phy_3a_aux_clk_src.clkr, 8081 [GCC_PCIE_PHY_3B_AUX_CLK] = &gcc_pcie_phy_3b_aux_clk.clkr, 8082 [GCC_PCIE_PHY_3B_AUX_CLK_SRC] = &gcc_pcie_phy_3b_aux_clk_src.clkr, 8083 [GCC_PCIE_PHY_4_AUX_CLK] = &gcc_pcie_phy_4_aux_clk.clkr, 8084 [GCC_PCIE_PHY_4_AUX_CLK_SRC] = &gcc_pcie_phy_4_aux_clk_src.clkr, 8085 [GCC_PCIE_PHY_5_AUX_CLK] = &gcc_pcie_phy_5_aux_clk.clkr, 8086 [GCC_PCIE_PHY_5_AUX_CLK_SRC] = &gcc_pcie_phy_5_aux_clk_src.clkr, 8087 [GCC_PCIE_PHY_6_AUX_CLK] = &gcc_pcie_phy_6_aux_clk.clkr, 8088 [GCC_PCIE_PHY_6_AUX_CLK_SRC] = &gcc_pcie_phy_6_aux_clk_src.clkr, 8089 [GCC_PCIE_RSCC_CFG_AHB_CLK] = &gcc_pcie_rscc_cfg_ahb_clk.clkr, 8090 [GCC_PCIE_RSCC_XO_CLK] = &gcc_pcie_rscc_xo_clk.clkr, 8091 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 8092 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 8093 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 8094 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 8095 [GCC_QMIP_AV1E_AHB_CLK] = &gcc_qmip_av1e_ahb_clk.clkr, 8096 [GCC_QMIP_CAMERA_CMD_AHB_CLK] = &gcc_qmip_camera_cmd_ahb_clk.clkr, 8097 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 8098 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 8099 [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr, 8100 [GCC_QMIP_PCIE_3A_AHB_CLK] = &gcc_qmip_pcie_3a_ahb_clk.clkr, 8101 [GCC_QMIP_PCIE_3B_AHB_CLK] = &gcc_qmip_pcie_3b_ahb_clk.clkr, 8102 [GCC_QMIP_PCIE_4_AHB_CLK] = &gcc_qmip_pcie_4_ahb_clk.clkr, 8103 [GCC_QMIP_PCIE_5_AHB_CLK] = &gcc_qmip_pcie_5_ahb_clk.clkr, 8104 [GCC_QMIP_PCIE_6_AHB_CLK] = &gcc_qmip_pcie_6_ahb_clk.clkr, 8105 [GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr, 8106 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 8107 [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr, 8108 [GCC_QMIP_VIDEO_VCODEC1_AHB_CLK] = &gcc_qmip_video_vcodec1_ahb_clk.clkr, 8109 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 8110 [GCC_QUPV3_OOB_CORE_2X_CLK] = &gcc_qupv3_oob_core_2x_clk.clkr, 8111 [GCC_QUPV3_OOB_CORE_CLK] = &gcc_qupv3_oob_core_clk.clkr, 8112 [GCC_QUPV3_OOB_M_AHB_CLK] = &gcc_qupv3_oob_m_ahb_clk.clkr, 8113 [GCC_QUPV3_OOB_QSPI_S0_CLK] = &gcc_qupv3_oob_qspi_s0_clk.clkr, 8114 [GCC_QUPV3_OOB_QSPI_S0_CLK_SRC] = &gcc_qupv3_oob_qspi_s0_clk_src.clkr, 8115 [GCC_QUPV3_OOB_QSPI_S1_CLK] = &gcc_qupv3_oob_qspi_s1_clk.clkr, 8116 [GCC_QUPV3_OOB_QSPI_S1_CLK_SRC] = &gcc_qupv3_oob_qspi_s1_clk_src.clkr, 8117 [GCC_QUPV3_OOB_S0_CLK] = &gcc_qupv3_oob_s0_clk.clkr, 8118 [GCC_QUPV3_OOB_S0_CLK_SRC] = &gcc_qupv3_oob_s0_clk_src.clkr, 8119 [GCC_QUPV3_OOB_S1_CLK] = &gcc_qupv3_oob_s1_clk.clkr, 8120 [GCC_QUPV3_OOB_S1_CLK_SRC] = &gcc_qupv3_oob_s1_clk_src.clkr, 8121 [GCC_QUPV3_OOB_S_AHB_CLK] = &gcc_qupv3_oob_s_ahb_clk.clkr, 8122 [GCC_QUPV3_OOB_TCXO_CLK] = &gcc_qupv3_oob_tcxo_clk.clkr, 8123 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, 8124 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, 8125 [GCC_QUPV3_WRAP0_QSPI_S2_CLK] = &gcc_qupv3_wrap0_qspi_s2_clk.clkr, 8126 [GCC_QUPV3_WRAP0_QSPI_S2_CLK_SRC] = &gcc_qupv3_wrap0_qspi_s2_clk_src.clkr, 8127 [GCC_QUPV3_WRAP0_QSPI_S3_CLK] = &gcc_qupv3_wrap0_qspi_s3_clk.clkr, 8128 [GCC_QUPV3_WRAP0_QSPI_S3_CLK_SRC] = &gcc_qupv3_wrap0_qspi_s3_clk_src.clkr, 8129 [GCC_QUPV3_WRAP0_QSPI_S6_CLK] = &gcc_qupv3_wrap0_qspi_s6_clk.clkr, 8130 [GCC_QUPV3_WRAP0_QSPI_S6_CLK_SRC] = &gcc_qupv3_wrap0_qspi_s6_clk_src.clkr, 8131 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 8132 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 8133 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 8134 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 8135 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 8136 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 8137 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 8138 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 8139 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 8140 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 8141 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 8142 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 8143 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 8144 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 8145 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 8146 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 8147 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 8148 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 8149 [GCC_QUPV3_WRAP1_QSPI_S2_CLK] = &gcc_qupv3_wrap1_qspi_s2_clk.clkr, 8150 [GCC_QUPV3_WRAP1_QSPI_S2_CLK_SRC] = &gcc_qupv3_wrap1_qspi_s2_clk_src.clkr, 8151 [GCC_QUPV3_WRAP1_QSPI_S3_CLK] = &gcc_qupv3_wrap1_qspi_s3_clk.clkr, 8152 [GCC_QUPV3_WRAP1_QSPI_S3_CLK_SRC] = &gcc_qupv3_wrap1_qspi_s3_clk_src.clkr, 8153 [GCC_QUPV3_WRAP1_QSPI_S6_CLK] = &gcc_qupv3_wrap1_qspi_s6_clk.clkr, 8154 [GCC_QUPV3_WRAP1_QSPI_S6_CLK_SRC] = &gcc_qupv3_wrap1_qspi_s6_clk_src.clkr, 8155 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 8156 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 8157 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 8158 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 8159 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 8160 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 8161 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 8162 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 8163 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 8164 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 8165 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 8166 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 8167 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 8168 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 8169 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 8170 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 8171 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, 8172 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, 8173 [GCC_QUPV3_WRAP2_QSPI_S2_CLK] = &gcc_qupv3_wrap2_qspi_s2_clk.clkr, 8174 [GCC_QUPV3_WRAP2_QSPI_S2_CLK_SRC] = &gcc_qupv3_wrap2_qspi_s2_clk_src.clkr, 8175 [GCC_QUPV3_WRAP2_QSPI_S3_CLK] = &gcc_qupv3_wrap2_qspi_s3_clk.clkr, 8176 [GCC_QUPV3_WRAP2_QSPI_S3_CLK_SRC] = &gcc_qupv3_wrap2_qspi_s3_clk_src.clkr, 8177 [GCC_QUPV3_WRAP2_QSPI_S6_CLK] = &gcc_qupv3_wrap2_qspi_s6_clk.clkr, 8178 [GCC_QUPV3_WRAP2_QSPI_S6_CLK_SRC] = &gcc_qupv3_wrap2_qspi_s6_clk_src.clkr, 8179 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 8180 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 8181 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 8182 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 8183 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 8184 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 8185 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 8186 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 8187 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 8188 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 8189 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, 8190 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, 8191 [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr, 8192 [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr, 8193 [GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr, 8194 [GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr, 8195 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 8196 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 8197 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 8198 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 8199 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 8200 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 8201 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 8202 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 8203 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 8204 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 8205 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 8206 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 8207 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 8208 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 8209 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 8210 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 8211 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 8212 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 8213 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 8214 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 8215 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr, 8216 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 8217 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr, 8218 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 8219 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr, 8220 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 8221 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 8222 [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr, 8223 [GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr, 8224 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr, 8225 [GCC_USB20_MOCK_UTMI_CLK_SRC] = &gcc_usb20_mock_utmi_clk_src.clkr, 8226 [GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb20_mock_utmi_postdiv_clk_src.clkr, 8227 [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr, 8228 [GCC_USB30_MP_MASTER_CLK] = &gcc_usb30_mp_master_clk.clkr, 8229 [GCC_USB30_MP_MASTER_CLK_SRC] = &gcc_usb30_mp_master_clk_src.clkr, 8230 [GCC_USB30_MP_MOCK_UTMI_CLK] = &gcc_usb30_mp_mock_utmi_clk.clkr, 8231 [GCC_USB30_MP_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mp_mock_utmi_clk_src.clkr, 8232 [GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr, 8233 [GCC_USB30_MP_SLEEP_CLK] = &gcc_usb30_mp_sleep_clk.clkr, 8234 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 8235 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 8236 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 8237 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 8238 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 8239 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 8240 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, 8241 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, 8242 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, 8243 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr, 8244 [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr, 8245 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, 8246 [GCC_USB30_TERT_MASTER_CLK] = &gcc_usb30_tert_master_clk.clkr, 8247 [GCC_USB30_TERT_MASTER_CLK_SRC] = &gcc_usb30_tert_master_clk_src.clkr, 8248 [GCC_USB30_TERT_MOCK_UTMI_CLK] = &gcc_usb30_tert_mock_utmi_clk.clkr, 8249 [GCC_USB30_TERT_MOCK_UTMI_CLK_SRC] = &gcc_usb30_tert_mock_utmi_clk_src.clkr, 8250 [GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr, 8251 [GCC_USB30_TERT_SLEEP_CLK] = &gcc_usb30_tert_sleep_clk.clkr, 8252 [GCC_USB34_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb34_prim_phy_pipe_clk_src.clkr, 8253 [GCC_USB34_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb34_sec_phy_pipe_clk_src.clkr, 8254 [GCC_USB34_TERT_PHY_PIPE_CLK_SRC] = &gcc_usb34_tert_phy_pipe_clk_src.clkr, 8255 [GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr, 8256 [GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr, 8257 [GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr, 8258 [GCC_USB3_MP_PHY_PIPE_0_CLK] = &gcc_usb3_mp_phy_pipe_0_clk.clkr, 8259 [GCC_USB3_MP_PHY_PIPE_0_CLK_SRC] = &gcc_usb3_mp_phy_pipe_0_clk_src.clkr, 8260 [GCC_USB3_MP_PHY_PIPE_1_CLK] = &gcc_usb3_mp_phy_pipe_1_clk.clkr, 8261 [GCC_USB3_MP_PHY_PIPE_1_CLK_SRC] = &gcc_usb3_mp_phy_pipe_1_clk_src.clkr, 8262 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 8263 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 8264 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 8265 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 8266 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 8267 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, 8268 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, 8269 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, 8270 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, 8271 [GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr, 8272 [GCC_USB3_TERT_PHY_AUX_CLK] = &gcc_usb3_tert_phy_aux_clk.clkr, 8273 [GCC_USB3_TERT_PHY_AUX_CLK_SRC] = &gcc_usb3_tert_phy_aux_clk_src.clkr, 8274 [GCC_USB3_TERT_PHY_COM_AUX_CLK] = &gcc_usb3_tert_phy_com_aux_clk.clkr, 8275 [GCC_USB3_TERT_PHY_PIPE_CLK] = &gcc_usb3_tert_phy_pipe_clk.clkr, 8276 [GCC_USB3_TERT_PHY_PIPE_CLK_SRC] = &gcc_usb3_tert_phy_pipe_clk_src.clkr, 8277 [GCC_USB4_0_CFG_AHB_CLK] = &gcc_usb4_0_cfg_ahb_clk.clkr, 8278 [GCC_USB4_0_DP0_CLK] = &gcc_usb4_0_dp0_clk.clkr, 8279 [GCC_USB4_0_DP1_CLK] = &gcc_usb4_0_dp1_clk.clkr, 8280 [GCC_USB4_0_MASTER_CLK] = &gcc_usb4_0_master_clk.clkr, 8281 [GCC_USB4_0_MASTER_CLK_SRC] = &gcc_usb4_0_master_clk_src.clkr, 8282 [GCC_USB4_0_PHY_DP0_CLK_SRC] = &gcc_usb4_0_phy_dp0_clk_src.clkr, 8283 [GCC_USB4_0_PHY_DP1_CLK_SRC] = &gcc_usb4_0_phy_dp1_clk_src.clkr, 8284 [GCC_USB4_0_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_0_phy_p2rr2p_pipe_clk.clkr, 8285 [GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_0_phy_p2rr2p_pipe_clk_src.clkr, 8286 [GCC_USB4_0_PHY_PCIE_PIPE_CLK] = &gcc_usb4_0_phy_pcie_pipe_clk.clkr, 8287 [GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_clk_src.clkr, 8288 [GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr, 8289 [GCC_USB4_0_PHY_RX0_CLK] = &gcc_usb4_0_phy_rx0_clk.clkr, 8290 [GCC_USB4_0_PHY_RX0_CLK_SRC] = &gcc_usb4_0_phy_rx0_clk_src.clkr, 8291 [GCC_USB4_0_PHY_RX1_CLK] = &gcc_usb4_0_phy_rx1_clk.clkr, 8292 [GCC_USB4_0_PHY_RX1_CLK_SRC] = &gcc_usb4_0_phy_rx1_clk_src.clkr, 8293 [GCC_USB4_0_PHY_SYS_CLK_SRC] = &gcc_usb4_0_phy_sys_clk_src.clkr, 8294 [GCC_USB4_0_PHY_USB_PIPE_CLK] = &gcc_usb4_0_phy_usb_pipe_clk.clkr, 8295 [GCC_USB4_0_SB_IF_CLK] = &gcc_usb4_0_sb_if_clk.clkr, 8296 [GCC_USB4_0_SB_IF_CLK_SRC] = &gcc_usb4_0_sb_if_clk_src.clkr, 8297 [GCC_USB4_0_SYS_CLK] = &gcc_usb4_0_sys_clk.clkr, 8298 [GCC_USB4_0_TMU_CLK] = &gcc_usb4_0_tmu_clk.clkr, 8299 [GCC_USB4_0_TMU_CLK_SRC] = &gcc_usb4_0_tmu_clk_src.clkr, 8300 [GCC_USB4_0_UC_HRR_CLK] = &gcc_usb4_0_uc_hrr_clk.clkr, 8301 [GCC_USB4_1_CFG_AHB_CLK] = &gcc_usb4_1_cfg_ahb_clk.clkr, 8302 [GCC_USB4_1_DP0_CLK] = &gcc_usb4_1_dp0_clk.clkr, 8303 [GCC_USB4_1_DP1_CLK] = &gcc_usb4_1_dp1_clk.clkr, 8304 [GCC_USB4_1_MASTER_CLK] = &gcc_usb4_1_master_clk.clkr, 8305 [GCC_USB4_1_MASTER_CLK_SRC] = &gcc_usb4_1_master_clk_src.clkr, 8306 [GCC_USB4_1_PHY_DP0_CLK_SRC] = &gcc_usb4_1_phy_dp0_clk_src.clkr, 8307 [GCC_USB4_1_PHY_DP1_CLK_SRC] = &gcc_usb4_1_phy_dp1_clk_src.clkr, 8308 [GCC_USB4_1_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_1_phy_p2rr2p_pipe_clk.clkr, 8309 [GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr, 8310 [GCC_USB4_1_PHY_PCIE_PIPE_CLK] = &gcc_usb4_1_phy_pcie_pipe_clk.clkr, 8311 [GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_clk_src.clkr, 8312 [GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr, 8313 [GCC_USB4_1_PHY_PLL_PIPE_CLK_SRC] = &gcc_usb4_1_phy_pll_pipe_clk_src.clkr, 8314 [GCC_USB4_1_PHY_RX0_CLK] = &gcc_usb4_1_phy_rx0_clk.clkr, 8315 [GCC_USB4_1_PHY_RX0_CLK_SRC] = &gcc_usb4_1_phy_rx0_clk_src.clkr, 8316 [GCC_USB4_1_PHY_RX1_CLK] = &gcc_usb4_1_phy_rx1_clk.clkr, 8317 [GCC_USB4_1_PHY_RX1_CLK_SRC] = &gcc_usb4_1_phy_rx1_clk_src.clkr, 8318 [GCC_USB4_1_PHY_SYS_CLK_SRC] = &gcc_usb4_1_phy_sys_clk_src.clkr, 8319 [GCC_USB4_1_PHY_USB_PIPE_CLK] = &gcc_usb4_1_phy_usb_pipe_clk.clkr, 8320 [GCC_USB4_1_SB_IF_CLK] = &gcc_usb4_1_sb_if_clk.clkr, 8321 [GCC_USB4_1_SB_IF_CLK_SRC] = &gcc_usb4_1_sb_if_clk_src.clkr, 8322 [GCC_USB4_1_SYS_CLK] = &gcc_usb4_1_sys_clk.clkr, 8323 [GCC_USB4_1_TMU_CLK] = &gcc_usb4_1_tmu_clk.clkr, 8324 [GCC_USB4_1_TMU_CLK_SRC] = &gcc_usb4_1_tmu_clk_src.clkr, 8325 [GCC_USB4_1_UC_HRR_CLK] = &gcc_usb4_1_uc_hrr_clk.clkr, 8326 [GCC_USB4_2_CFG_AHB_CLK] = &gcc_usb4_2_cfg_ahb_clk.clkr, 8327 [GCC_USB4_2_DP0_CLK] = &gcc_usb4_2_dp0_clk.clkr, 8328 [GCC_USB4_2_DP1_CLK] = &gcc_usb4_2_dp1_clk.clkr, 8329 [GCC_USB4_2_MASTER_CLK] = &gcc_usb4_2_master_clk.clkr, 8330 [GCC_USB4_2_MASTER_CLK_SRC] = &gcc_usb4_2_master_clk_src.clkr, 8331 [GCC_USB4_2_PHY_DP0_CLK_SRC] = &gcc_usb4_2_phy_dp0_clk_src.clkr, 8332 [GCC_USB4_2_PHY_DP1_CLK_SRC] = &gcc_usb4_2_phy_dp1_clk_src.clkr, 8333 [GCC_USB4_2_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_2_phy_p2rr2p_pipe_clk.clkr, 8334 [GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_2_phy_p2rr2p_pipe_clk_src.clkr, 8335 [GCC_USB4_2_PHY_PCIE_PIPE_CLK] = &gcc_usb4_2_phy_pcie_pipe_clk.clkr, 8336 [GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_clk_src.clkr, 8337 [GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr, 8338 [GCC_USB4_2_PHY_RX0_CLK] = &gcc_usb4_2_phy_rx0_clk.clkr, 8339 [GCC_USB4_2_PHY_RX0_CLK_SRC] = &gcc_usb4_2_phy_rx0_clk_src.clkr, 8340 [GCC_USB4_2_PHY_RX1_CLK] = &gcc_usb4_2_phy_rx1_clk.clkr, 8341 [GCC_USB4_2_PHY_RX1_CLK_SRC] = &gcc_usb4_2_phy_rx1_clk_src.clkr, 8342 [GCC_USB4_2_PHY_SYS_CLK_SRC] = &gcc_usb4_2_phy_sys_clk_src.clkr, 8343 [GCC_USB4_2_PHY_USB_PIPE_CLK] = &gcc_usb4_2_phy_usb_pipe_clk.clkr, 8344 [GCC_USB4_2_SB_IF_CLK] = &gcc_usb4_2_sb_if_clk.clkr, 8345 [GCC_USB4_2_SB_IF_CLK_SRC] = &gcc_usb4_2_sb_if_clk_src.clkr, 8346 [GCC_USB4_2_SYS_CLK] = &gcc_usb4_2_sys_clk.clkr, 8347 [GCC_USB4_2_TMU_CLK] = &gcc_usb4_2_tmu_clk.clkr, 8348 [GCC_USB4_2_TMU_CLK_SRC] = &gcc_usb4_2_tmu_clk_src.clkr, 8349 [GCC_USB4_2_UC_HRR_CLK] = &gcc_usb4_2_uc_hrr_clk.clkr, 8350 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 8351 [GCC_VIDEO_AXI0C_CLK] = &gcc_video_axi0c_clk.clkr, 8352 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 8353 }; 8354 8355 static struct gdsc *gcc_glymur_gdscs[] = { 8356 [GCC_PCIE_0_TUNNEL_GDSC] = &gcc_pcie_0_tunnel_gdsc, 8357 [GCC_PCIE_1_TUNNEL_GDSC] = &gcc_pcie_1_tunnel_gdsc, 8358 [GCC_PCIE_2_TUNNEL_GDSC] = &gcc_pcie_2_tunnel_gdsc, 8359 [GCC_PCIE_3A_GDSC] = &gcc_pcie_3a_gdsc, 8360 [GCC_PCIE_3A_PHY_GDSC] = &gcc_pcie_3a_phy_gdsc, 8361 [GCC_PCIE_3B_GDSC] = &gcc_pcie_3b_gdsc, 8362 [GCC_PCIE_3B_PHY_GDSC] = &gcc_pcie_3b_phy_gdsc, 8363 [GCC_PCIE_4_GDSC] = &gcc_pcie_4_gdsc, 8364 [GCC_PCIE_4_PHY_GDSC] = &gcc_pcie_4_phy_gdsc, 8365 [GCC_PCIE_5_GDSC] = &gcc_pcie_5_gdsc, 8366 [GCC_PCIE_5_PHY_GDSC] = &gcc_pcie_5_phy_gdsc, 8367 [GCC_PCIE_6_GDSC] = &gcc_pcie_6_gdsc, 8368 [GCC_PCIE_6_PHY_GDSC] = &gcc_pcie_6_phy_gdsc, 8369 [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc, 8370 [GCC_USB20_PRIM_GDSC] = &gcc_usb20_prim_gdsc, 8371 [GCC_USB30_MP_GDSC] = &gcc_usb30_mp_gdsc, 8372 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, 8373 [GCC_USB30_SEC_GDSC] = &gcc_usb30_sec_gdsc, 8374 [GCC_USB30_TERT_GDSC] = &gcc_usb30_tert_gdsc, 8375 [GCC_USB3_MP_SS0_PHY_GDSC] = &gcc_usb3_mp_ss0_phy_gdsc, 8376 [GCC_USB3_MP_SS1_PHY_GDSC] = &gcc_usb3_mp_ss1_phy_gdsc, 8377 [GCC_USB4_0_GDSC] = &gcc_usb4_0_gdsc, 8378 [GCC_USB4_1_GDSC] = &gcc_usb4_1_gdsc, 8379 [GCC_USB4_2_GDSC] = &gcc_usb4_2_gdsc, 8380 [GCC_USB_0_PHY_GDSC] = &gcc_usb_0_phy_gdsc, 8381 [GCC_USB_1_PHY_GDSC] = &gcc_usb_1_phy_gdsc, 8382 [GCC_USB_2_PHY_GDSC] = &gcc_usb_2_phy_gdsc, 8383 }; 8384 8385 static const struct qcom_reset_map gcc_glymur_resets[] = { 8386 [GCC_AV1E_BCR] = { 0x9b028 }, 8387 [GCC_CAMERA_BCR] = { 0x26000 }, 8388 [GCC_DISPLAY_BCR] = { 0x27000 }, 8389 [GCC_EVA_BCR] = { 0x9b000 }, 8390 [GCC_GPU_BCR] = { 0x71000 }, 8391 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0xbc2d0 }, 8392 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0xbc2dc }, 8393 [GCC_PCIE_0_PHY_BCR] = { 0xbc2d8 }, 8394 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0xbc2e0 }, 8395 [GCC_PCIE_0_TUNNEL_BCR] = { 0xc8000 }, 8396 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x7f018 }, 8397 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x7f024 }, 8398 [GCC_PCIE_1_PHY_BCR] = { 0x7f020 }, 8399 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x7f028 }, 8400 [GCC_PCIE_1_TUNNEL_BCR] = { 0x2e000 }, 8401 [GCC_PCIE_2_LINK_DOWN_BCR] = { 0x281d0 }, 8402 [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0x281dc }, 8403 [GCC_PCIE_2_PHY_BCR] = { 0x281d8 }, 8404 [GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0x281e0 }, 8405 [GCC_PCIE_2_TUNNEL_BCR] = { 0xc0000 }, 8406 [GCC_PCIE_3A_BCR] = { 0xdc000 }, 8407 [GCC_PCIE_3A_LINK_DOWN_BCR] = { 0x7b0a0 }, 8408 [GCC_PCIE_3A_NOCSR_COM_PHY_BCR] = { 0x7b0ac }, 8409 [GCC_PCIE_3A_PHY_BCR] = { 0x6c000 }, 8410 [GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR] = { 0x7b0b0 }, 8411 [GCC_PCIE_3B_BCR] = { 0x94000 }, 8412 [GCC_PCIE_3B_LINK_DOWN_BCR] = { 0x7a0c0 }, 8413 [GCC_PCIE_3B_NOCSR_COM_PHY_BCR] = { 0x7a0cc }, 8414 [GCC_PCIE_3B_PHY_BCR] = { 0x75000 }, 8415 [GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR] = { 0x7a0c8 }, 8416 [GCC_PCIE_4_BCR] = { 0x88000 }, 8417 [GCC_PCIE_4_LINK_DOWN_BCR] = { 0x980c0 }, 8418 [GCC_PCIE_4_NOCSR_COM_PHY_BCR] = { 0x980cc }, 8419 [GCC_PCIE_4_PHY_BCR] = { 0xd3000 }, 8420 [GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] = { 0x980d0 }, 8421 [GCC_PCIE_5_BCR] = { 0xc3000 }, 8422 [GCC_PCIE_5_LINK_DOWN_BCR] = { 0x850c0 }, 8423 [GCC_PCIE_5_NOCSR_COM_PHY_BCR] = { 0x850cc }, 8424 [GCC_PCIE_5_PHY_BCR] = { 0xd2000 }, 8425 [GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR] = { 0x850d0 }, 8426 [GCC_PCIE_6_BCR] = { 0x8a000 }, 8427 [GCC_PCIE_6_LINK_DOWN_BCR] = { 0x3a0b0 }, 8428 [GCC_PCIE_6_NOCSR_COM_PHY_BCR] = { 0x3a0bc }, 8429 [GCC_PCIE_6_PHY_BCR] = { 0xd4000 }, 8430 [GCC_PCIE_6_PHY_NOCSR_COM_PHY_BCR] = { 0x3a0c0 }, 8431 [GCC_PCIE_NOC_BCR] = { 0xba294 }, 8432 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 8433 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c }, 8434 [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 }, 8435 [GCC_PCIE_RSCC_BCR] = { 0xb8000 }, 8436 [GCC_PDM_BCR] = { 0x33000 }, 8437 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x28000 }, 8438 [GCC_QUPV3_WRAPPER_1_BCR] = { 0xb3000 }, 8439 [GCC_QUPV3_WRAPPER_2_BCR] = { 0xb4000 }, 8440 [GCC_QUPV3_WRAPPER_OOB_BCR] = { 0xe7000 }, 8441 [GCC_QUSB2PHY_HS0_MP_BCR] = { 0xca000 }, 8442 [GCC_QUSB2PHY_HS1_MP_BCR] = { 0xe6000 }, 8443 [GCC_QUSB2PHY_PRIM_BCR] = { 0xad024 }, 8444 [GCC_QUSB2PHY_SEC_BCR] = { 0xae000 }, 8445 [GCC_QUSB2PHY_TERT_BCR] = { 0xc9000 }, 8446 [GCC_QUSB2PHY_USB20_HS_BCR] = { 0xe9000 }, 8447 [GCC_SDCC2_BCR] = { 0xb0000 }, 8448 [GCC_SDCC4_BCR] = { 0xdf000 }, 8449 [GCC_TCSR_PCIE_BCR] = { 0x281e4 }, 8450 [GCC_UFS_PHY_BCR] = { 0x77004 }, 8451 [GCC_USB20_PRIM_BCR] = { 0xbc000 }, 8452 [GCC_USB30_MP_BCR] = { 0x9a00c }, 8453 [GCC_USB30_PRIM_BCR] = { 0x3f018 }, 8454 [GCC_USB30_SEC_BCR] = { 0xe200c }, 8455 [GCC_USB30_TERT_BCR] = { 0xe100c }, 8456 [GCC_USB3_MP_SS0_PHY_BCR] = { 0x54008 }, 8457 [GCC_USB3_MP_SS1_PHY_BCR] = { 0x54028 }, 8458 [GCC_USB3_PHY_PRIM_BCR] = { 0xdb000 }, 8459 [GCC_USB3_PHY_SEC_BCR] = { 0x2c000 }, 8460 [GCC_USB3_PHY_TERT_BCR] = { 0xbe000 }, 8461 [GCC_USB3_UNIPHY_MP0_BCR] = { 0x54000 }, 8462 [GCC_USB3_UNIPHY_MP1_BCR] = { 0x54020 }, 8463 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0xdb004 }, 8464 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x2c004 }, 8465 [GCC_USB3PHY_PHY_TERT_BCR] = { 0xbe004 }, 8466 [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x54004 }, 8467 [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x54024 }, 8468 [GCC_USB4_0_BCR] = { 0x2b004 }, 8469 [GCC_USB4_0_DP0_PHY_PRIM_BCR] = { 0xdb010 }, 8470 [GCC_USB4_1_BCR] = { 0x2d004 }, 8471 [GCC_USB4_2_BCR] = { 0xe0004 }, 8472 [GCC_USB_0_PHY_BCR] = { 0xdb020 }, 8473 [GCC_USB_1_PHY_BCR] = { 0x2c020 }, 8474 [GCC_USB_2_PHY_BCR] = { 0xbe020 }, 8475 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x3201c, 2 }, 8476 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x32044, 2 }, 8477 [GCC_VIDEO_BCR] = { 0x32000 }, 8478 [GCC_VIDEO_AXI0C_CLK_ARES] = { 0x32030, 2 }, 8479 }; 8480 8481 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 8482 DEFINE_RCG_DFS(gcc_qupv3_oob_qspi_s0_clk_src), 8483 DEFINE_RCG_DFS(gcc_qupv3_oob_qspi_s1_clk_src), 8484 DEFINE_RCG_DFS(gcc_qupv3_wrap0_qspi_s2_clk_src), 8485 DEFINE_RCG_DFS(gcc_qupv3_wrap0_qspi_s3_clk_src), 8486 DEFINE_RCG_DFS(gcc_qupv3_wrap0_qspi_s6_clk_src), 8487 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 8488 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 8489 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 8490 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 8491 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 8492 DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_s2_clk_src), 8493 DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_s3_clk_src), 8494 DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_s6_clk_src), 8495 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 8496 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 8497 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 8498 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 8499 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 8500 DEFINE_RCG_DFS(gcc_qupv3_wrap2_qspi_s2_clk_src), 8501 DEFINE_RCG_DFS(gcc_qupv3_wrap2_qspi_s3_clk_src), 8502 DEFINE_RCG_DFS(gcc_qupv3_wrap2_qspi_s6_clk_src), 8503 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 8504 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 8505 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 8506 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), 8507 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src), 8508 }; 8509 8510 static const u32 gcc_glymur_critical_cbcrs[] = { 8511 0x26004, /* GCC_CAMERA_AHB_CLK */ 8512 0x26040, /* GCC_CAMERA_XO_CLK */ 8513 0x27004, /* GCC_DISP_AHB_CLK */ 8514 0x71004, /* GCC_GPU_CFG_AHB_CLK */ 8515 0x32004, /* GCC_VIDEO_AHB_CLK */ 8516 0x32058, /* GCC_VIDEO_XO_CLK */ 8517 0x9b004, /* GCC_EVA_AHB_CLK */ 8518 0x9b024, /* GCC_EVA_XO_CLK */ 8519 }; 8520 8521 static const struct regmap_config gcc_glymur_regmap_config = { 8522 .reg_bits = 32, 8523 .reg_stride = 4, 8524 .val_bits = 32, 8525 .max_register = 0x1f8ff0, 8526 .fast_io = true, 8527 }; 8528 8529 static void clk_glymur_regs_configure(struct device *dev, struct regmap *regmap) 8530 { 8531 /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ 8532 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); 8533 } 8534 8535 static const struct qcom_cc_driver_data gcc_glymur_driver_data = { 8536 .clk_cbcrs = gcc_glymur_critical_cbcrs, 8537 .num_clk_cbcrs = ARRAY_SIZE(gcc_glymur_critical_cbcrs), 8538 .dfs_rcgs = gcc_dfs_clocks, 8539 .num_dfs_rcgs = ARRAY_SIZE(gcc_dfs_clocks), 8540 .clk_regs_configure = clk_glymur_regs_configure, 8541 }; 8542 8543 static const struct qcom_cc_desc gcc_glymur_desc = { 8544 .config = &gcc_glymur_regmap_config, 8545 .clks = gcc_glymur_clocks, 8546 .num_clks = ARRAY_SIZE(gcc_glymur_clocks), 8547 .resets = gcc_glymur_resets, 8548 .num_resets = ARRAY_SIZE(gcc_glymur_resets), 8549 .gdscs = gcc_glymur_gdscs, 8550 .num_gdscs = ARRAY_SIZE(gcc_glymur_gdscs), 8551 .use_rpm = true, 8552 .driver_data = &gcc_glymur_driver_data, 8553 }; 8554 8555 static const struct of_device_id gcc_glymur_match_table[] = { 8556 { .compatible = "qcom,glymur-gcc" }, 8557 { } 8558 }; 8559 MODULE_DEVICE_TABLE(of, gcc_glymur_match_table); 8560 8561 static int gcc_glymur_probe(struct platform_device *pdev) 8562 { 8563 return qcom_cc_probe(pdev, &gcc_glymur_desc); 8564 } 8565 8566 static struct platform_driver gcc_glymur_driver = { 8567 .probe = gcc_glymur_probe, 8568 .driver = { 8569 .name = "gcc-glymur", 8570 .of_match_table = gcc_glymur_match_table, 8571 }, 8572 }; 8573 8574 static int __init gcc_glymur_init(void) 8575 { 8576 return platform_driver_register(&gcc_glymur_driver); 8577 } 8578 subsys_initcall(gcc_glymur_init); 8579 8580 static void __exit gcc_glymur_exit(void) 8581 { 8582 platform_driver_unregister(&gcc_glymur_driver); 8583 } 8584 module_exit(gcc_glymur_exit); 8585 8586 MODULE_DESCRIPTION("QTI GCC Glymur Driver"); 8587 MODULE_LICENSE("GPL"); 8588