1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/mod_devicetable.h> 9 #include <linux/platform_device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/regmap.h> 12 13 #include <dt-bindings/clock/qcom,sa8775p-dispcc.h> 14 15 #include "clk-alpha-pll.h" 16 #include "clk-branch.h" 17 #include "clk-pll.h" 18 #include "clk-rcg.h" 19 #include "clk-regmap.h" 20 #include "clk-regmap-divider.h" 21 #include "clk-regmap-mux.h" 22 #include "common.h" 23 #include "gdsc.h" 24 #include "reset.h" 25 26 enum { 27 DT_IFACE, 28 DT_BI_TCXO, 29 DT_BI_TCXO_AO, 30 DT_SLEEP_CLK, 31 DT_DP0_PHY_PLL_LINK_CLK, 32 DT_DP0_PHY_PLL_VCO_DIV_CLK, 33 DT_DP1_PHY_PLL_LINK_CLK, 34 DT_DP1_PHY_PLL_VCO_DIV_CLK, 35 DT_DSI0_PHY_PLL_OUT_BYTECLK, 36 DT_DSI0_PHY_PLL_OUT_DSICLK, 37 DT_DSI1_PHY_PLL_OUT_BYTECLK, 38 DT_DSI1_PHY_PLL_OUT_DSICLK, 39 }; 40 41 enum { 42 P_BI_TCXO, 43 P_DP0_PHY_PLL_LINK_CLK, 44 P_DP0_PHY_PLL_VCO_DIV_CLK, 45 P_DP1_PHY_PLL_LINK_CLK, 46 P_DP1_PHY_PLL_VCO_DIV_CLK, 47 P_DSI0_PHY_PLL_OUT_BYTECLK, 48 P_DSI0_PHY_PLL_OUT_DSICLK, 49 P_DSI1_PHY_PLL_OUT_BYTECLK, 50 P_DSI1_PHY_PLL_OUT_DSICLK, 51 P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 52 P_MDSS_1_DISP_CC_PLL1_OUT_EVEN, 53 P_MDSS_1_DISP_CC_PLL1_OUT_MAIN, 54 P_SLEEP_CLK, 55 }; 56 57 static const struct pll_vco lucid_evo_vco[] = { 58 { 249600000, 2020000000, 0 }, 59 }; 60 61 static const struct alpha_pll_config mdss_1_disp_cc_pll0_config = { 62 .l = 0x3a, 63 .alpha = 0x9800, 64 .config_ctl_val = 0x20485699, 65 .config_ctl_hi_val = 0x00182261, 66 .config_ctl_hi1_val = 0x32aa299c, 67 .user_ctl_val = 0x00000000, 68 .user_ctl_hi_val = 0x00400805, 69 }; 70 71 static struct clk_alpha_pll mdss_1_disp_cc_pll0 = { 72 .offset = 0x0, 73 .vco_table = lucid_evo_vco, 74 .num_vco = ARRAY_SIZE(lucid_evo_vco), 75 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 76 .clkr = { 77 .hw.init = &(const struct clk_init_data) { 78 .name = "mdss_1_disp_cc_pll0", 79 .parent_data = &(const struct clk_parent_data) { 80 .index = DT_BI_TCXO, 81 }, 82 .num_parents = 1, 83 .ops = &clk_alpha_pll_lucid_evo_ops, 84 }, 85 }, 86 }; 87 88 static const struct alpha_pll_config mdss_1_disp_cc_pll1_config = { 89 .l = 0x1f, 90 .alpha = 0x4000, 91 .config_ctl_val = 0x20485699, 92 .config_ctl_hi_val = 0x00182261, 93 .config_ctl_hi1_val = 0x32aa299c, 94 .user_ctl_val = 0x00000000, 95 .user_ctl_hi_val = 0x00400805, 96 }; 97 98 static struct clk_alpha_pll mdss_1_disp_cc_pll1 = { 99 .offset = 0x1000, 100 .vco_table = lucid_evo_vco, 101 .num_vco = ARRAY_SIZE(lucid_evo_vco), 102 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 103 .clkr = { 104 .hw.init = &(const struct clk_init_data) { 105 .name = "mdss_1_disp_cc_pll1", 106 .parent_data = &(const struct clk_parent_data) { 107 .index = DT_BI_TCXO, 108 }, 109 .num_parents = 1, 110 .ops = &clk_alpha_pll_lucid_evo_ops, 111 }, 112 }, 113 }; 114 115 static const struct parent_map disp_cc_1_parent_map_0[] = { 116 { P_BI_TCXO, 0 }, 117 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 118 { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 }, 119 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, 120 }; 121 122 static const struct clk_parent_data disp_cc_1_parent_data_0[] = { 123 { .index = DT_BI_TCXO }, 124 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 125 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK }, 126 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 127 }; 128 129 static const struct parent_map disp_cc_1_parent_map_1[] = { 130 { P_BI_TCXO, 0 }, 131 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 132 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 133 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, 134 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 135 }; 136 137 static const struct clk_parent_data disp_cc_1_parent_data_1[] = { 138 { .index = DT_BI_TCXO }, 139 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, 140 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 141 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, 142 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 143 }; 144 145 static const struct parent_map disp_cc_1_parent_map_2[] = { 146 { P_BI_TCXO, 0 }, 147 }; 148 149 static const struct clk_parent_data disp_cc_1_parent_data_2[] = { 150 { .index = DT_BI_TCXO }, 151 }; 152 153 static const struct clk_parent_data disp_cc_1_parent_data_2_ao[] = { 154 { .index = DT_BI_TCXO_AO }, 155 }; 156 157 static const struct parent_map disp_cc_1_parent_map_3[] = { 158 { P_BI_TCXO, 0 }, 159 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 160 { P_DP1_PHY_PLL_LINK_CLK, 2 }, 161 }; 162 163 static const struct clk_parent_data disp_cc_1_parent_data_3[] = { 164 { .index = DT_BI_TCXO }, 165 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 166 { .index = DT_DP1_PHY_PLL_LINK_CLK }, 167 }; 168 169 static const struct parent_map disp_cc_1_parent_map_4[] = { 170 { P_BI_TCXO, 0 }, 171 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 172 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 173 }; 174 175 static const struct clk_parent_data disp_cc_1_parent_data_4[] = { 176 { .index = DT_BI_TCXO }, 177 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 178 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 179 }; 180 181 static const struct parent_map disp_cc_1_parent_map_5[] = { 182 { P_BI_TCXO, 0 }, 183 { P_MDSS_1_DISP_CC_PLL1_OUT_MAIN, 4 }, 184 { P_MDSS_1_DISP_CC_PLL1_OUT_EVEN, 6 }, 185 }; 186 187 static const struct clk_parent_data disp_cc_1_parent_data_5[] = { 188 { .index = DT_BI_TCXO }, 189 { .hw = &mdss_1_disp_cc_pll1.clkr.hw }, 190 { .hw = &mdss_1_disp_cc_pll1.clkr.hw }, 191 }; 192 193 static const struct parent_map disp_cc_1_parent_map_6[] = { 194 { P_BI_TCXO, 0 }, 195 { P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 1 }, 196 { P_MDSS_1_DISP_CC_PLL1_OUT_MAIN, 4 }, 197 { P_MDSS_1_DISP_CC_PLL1_OUT_EVEN, 6 }, 198 }; 199 200 static const struct clk_parent_data disp_cc_1_parent_data_6[] = { 201 { .index = DT_BI_TCXO }, 202 { .hw = &mdss_1_disp_cc_pll0.clkr.hw }, 203 { .hw = &mdss_1_disp_cc_pll1.clkr.hw }, 204 { .hw = &mdss_1_disp_cc_pll1.clkr.hw }, 205 }; 206 207 static const struct parent_map disp_cc_1_parent_map_7[] = { 208 { P_SLEEP_CLK, 0 }, 209 }; 210 211 static const struct clk_parent_data disp_cc_1_parent_data_7_ao[] = { 212 { .index = DT_SLEEP_CLK }, 213 }; 214 215 static const struct freq_tbl ftbl_mdss_1_disp_cc_mdss_ahb_clk_src[] = { 216 F(37500000, P_MDSS_1_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), 217 F(75000000, P_MDSS_1_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), 218 { } 219 }; 220 221 static struct clk_rcg2 mdss_1_disp_cc_mdss_ahb_clk_src = { 222 .cmd_rcgr = 0x824c, 223 .mnd_width = 0, 224 .hid_width = 5, 225 .parent_map = disp_cc_1_parent_map_5, 226 .freq_tbl = ftbl_mdss_1_disp_cc_mdss_ahb_clk_src, 227 .clkr.hw.init = &(const struct clk_init_data) { 228 .name = "mdss_1_disp_cc_mdss_ahb_clk_src", 229 .parent_data = disp_cc_1_parent_data_5, 230 .num_parents = ARRAY_SIZE(disp_cc_1_parent_data_5), 231 .flags = CLK_SET_RATE_PARENT, 232 .ops = &clk_rcg2_shared_ops, 233 }, 234 }; 235 236 static const struct freq_tbl ftbl_mdss_1_disp_cc_mdss_byte0_clk_src[] = { 237 F(19200000, P_BI_TCXO, 1, 0, 0), 238 { } 239 }; 240 241 static struct clk_rcg2 mdss_1_disp_cc_mdss_byte0_clk_src = { 242 .cmd_rcgr = 0x80ec, 243 .mnd_width = 0, 244 .hid_width = 5, 245 .parent_map = disp_cc_1_parent_map_1, 246 .freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, 247 .clkr.hw.init = &(const struct clk_init_data) { 248 .name = "mdss_1_disp_cc_mdss_byte0_clk_src", 249 .parent_data = disp_cc_1_parent_data_1, 250 .num_parents = ARRAY_SIZE(disp_cc_1_parent_data_1), 251 .flags = CLK_SET_RATE_PARENT, 252 .ops = &clk_byte2_ops, 253 }, 254 }; 255 256 static struct clk_rcg2 mdss_1_disp_cc_mdss_byte1_clk_src = { 257 .cmd_rcgr = 0x8108, 258 .mnd_width = 0, 259 .hid_width = 5, 260 .parent_map = disp_cc_1_parent_map_1, 261 .freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, 262 .clkr.hw.init = &(const struct clk_init_data) { 263 .name = "mdss_1_disp_cc_mdss_byte1_clk_src", 264 .parent_data = disp_cc_1_parent_data_1, 265 .num_parents = ARRAY_SIZE(disp_cc_1_parent_data_1), 266 .flags = CLK_SET_RATE_PARENT, 267 .ops = &clk_byte2_ops, 268 }, 269 }; 270 271 static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_aux_clk_src = { 272 .cmd_rcgr = 0x81b8, 273 .mnd_width = 0, 274 .hid_width = 5, 275 .parent_map = disp_cc_1_parent_map_2, 276 .freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, 277 .clkr.hw.init = &(const struct clk_init_data) { 278 .name = "mdss_1_disp_cc_mdss_dptx0_aux_clk_src", 279 .parent_data = disp_cc_1_parent_data_2, 280 .num_parents = ARRAY_SIZE(disp_cc_1_parent_data_2), 281 .flags = CLK_SET_RATE_PARENT, 282 .ops = &clk_rcg2_shared_ops, 283 }, 284 }; 285 286 static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_crypto_clk_src = { 287 .cmd_rcgr = 0x8170, 288 .mnd_width = 0, 289 .hid_width = 5, 290 .parent_map = disp_cc_1_parent_map_3, 291 .freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, 292 .clkr.hw.init = &(const struct clk_init_data) { 293 .name = "mdss_1_disp_cc_mdss_dptx0_crypto_clk_src", 294 .parent_data = disp_cc_1_parent_data_3, 295 .num_parents = ARRAY_SIZE(disp_cc_1_parent_data_3), 296 .flags = CLK_SET_RATE_PARENT, 297 .ops = &clk_byte2_ops, 298 }, 299 }; 300 301 static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_link_clk_src = { 302 .cmd_rcgr = 0x8154, 303 .mnd_width = 0, 304 .hid_width = 5, 305 .parent_map = disp_cc_1_parent_map_3, 306 .freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, 307 .clkr.hw.init = &(const struct clk_init_data) { 308 .name = "mdss_1_disp_cc_mdss_dptx0_link_clk_src", 309 .parent_data = disp_cc_1_parent_data_3, 310 .num_parents = ARRAY_SIZE(disp_cc_1_parent_data_3), 311 .flags = CLK_SET_RATE_PARENT, 312 .ops = &clk_byte2_ops, 313 }, 314 }; 315 316 static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_pixel0_clk_src = { 317 .cmd_rcgr = 0x8188, 318 .mnd_width = 16, 319 .hid_width = 5, 320 .parent_map = disp_cc_1_parent_map_0, 321 .freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, 322 .clkr.hw.init = &(const struct clk_init_data) { 323 .name = "mdss_1_disp_cc_mdss_dptx0_pixel0_clk_src", 324 .parent_data = disp_cc_1_parent_data_0, 325 .num_parents = ARRAY_SIZE(disp_cc_1_parent_data_0), 326 .flags = CLK_SET_RATE_PARENT, 327 .ops = &clk_dp_ops, 328 }, 329 }; 330 331 static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_pixel1_clk_src = { 332 .cmd_rcgr = 0x81a0, 333 .mnd_width = 16, 334 .hid_width = 5, 335 .parent_map = disp_cc_1_parent_map_0, 336 .freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, 337 .clkr.hw.init = &(const struct clk_init_data) { 338 .name = "mdss_1_disp_cc_mdss_dptx0_pixel1_clk_src", 339 .parent_data = disp_cc_1_parent_data_0, 340 .num_parents = ARRAY_SIZE(disp_cc_1_parent_data_0), 341 .flags = CLK_SET_RATE_PARENT, 342 .ops = &clk_dp_ops, 343 }, 344 }; 345 346 static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_pixel2_clk_src = { 347 .cmd_rcgr = 0x826c, 348 .mnd_width = 16, 349 .hid_width = 5, 350 .parent_map = disp_cc_1_parent_map_0, 351 .freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, 352 .clkr.hw.init = &(const struct clk_init_data) { 353 .name = "mdss_1_disp_cc_mdss_dptx0_pixel2_clk_src", 354 .parent_data = disp_cc_1_parent_data_0, 355 .num_parents = ARRAY_SIZE(disp_cc_1_parent_data_0), 356 .flags = CLK_SET_RATE_PARENT, 357 .ops = &clk_dp_ops, 358 }, 359 }; 360 361 static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_pixel3_clk_src = { 362 .cmd_rcgr = 0x8284, 363 .mnd_width = 16, 364 .hid_width = 5, 365 .parent_map = disp_cc_1_parent_map_0, 366 .freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, 367 .clkr.hw.init = &(const struct clk_init_data) { 368 .name = "mdss_1_disp_cc_mdss_dptx0_pixel3_clk_src", 369 .parent_data = disp_cc_1_parent_data_0, 370 .num_parents = ARRAY_SIZE(disp_cc_1_parent_data_0), 371 .flags = CLK_SET_RATE_PARENT, 372 .ops = &clk_dp_ops, 373 }, 374 }; 375 376 static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx1_aux_clk_src = { 377 .cmd_rcgr = 0x8234, 378 .mnd_width = 0, 379 .hid_width = 5, 380 .parent_map = disp_cc_1_parent_map_2, 381 .freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, 382 .clkr.hw.init = &(const struct clk_init_data) { 383 .name = "mdss_1_disp_cc_mdss_dptx1_aux_clk_src", 384 .parent_data = disp_cc_1_parent_data_2, 385 .num_parents = ARRAY_SIZE(disp_cc_1_parent_data_2), 386 .flags = CLK_SET_RATE_PARENT, 387 .ops = &clk_rcg2_shared_ops, 388 }, 389 }; 390 391 static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx1_crypto_clk_src = { 392 .cmd_rcgr = 0x821c, 393 .mnd_width = 0, 394 .hid_width = 5, 395 .parent_map = disp_cc_1_parent_map_3, 396 .freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, 397 .clkr.hw.init = &(const struct clk_init_data) { 398 .name = "mdss_1_disp_cc_mdss_dptx1_crypto_clk_src", 399 .parent_data = disp_cc_1_parent_data_3, 400 .num_parents = ARRAY_SIZE(disp_cc_1_parent_data_3), 401 .flags = CLK_SET_RATE_PARENT, 402 .ops = &clk_byte2_ops, 403 }, 404 }; 405 406 static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx1_link_clk_src = { 407 .cmd_rcgr = 0x8200, 408 .mnd_width = 0, 409 .hid_width = 5, 410 .parent_map = disp_cc_1_parent_map_3, 411 .freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, 412 .clkr.hw.init = &(const struct clk_init_data) { 413 .name = "mdss_1_disp_cc_mdss_dptx1_link_clk_src", 414 .parent_data = disp_cc_1_parent_data_3, 415 .num_parents = ARRAY_SIZE(disp_cc_1_parent_data_3), 416 .flags = CLK_SET_RATE_PARENT, 417 .ops = &clk_byte2_ops, 418 }, 419 }; 420 421 static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx1_pixel0_clk_src = { 422 .cmd_rcgr = 0x81d0, 423 .mnd_width = 16, 424 .hid_width = 5, 425 .parent_map = disp_cc_1_parent_map_0, 426 .freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, 427 .clkr.hw.init = &(const struct clk_init_data) { 428 .name = "mdss_1_disp_cc_mdss_dptx1_pixel0_clk_src", 429 .parent_data = disp_cc_1_parent_data_0, 430 .num_parents = ARRAY_SIZE(disp_cc_1_parent_data_0), 431 .flags = CLK_SET_RATE_PARENT, 432 .ops = &clk_dp_ops, 433 }, 434 }; 435 436 static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx1_pixel1_clk_src = { 437 .cmd_rcgr = 0x81e8, 438 .mnd_width = 16, 439 .hid_width = 5, 440 .parent_map = disp_cc_1_parent_map_0, 441 .freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, 442 .clkr.hw.init = &(const struct clk_init_data) { 443 .name = "mdss_1_disp_cc_mdss_dptx1_pixel1_clk_src", 444 .parent_data = disp_cc_1_parent_data_0, 445 .num_parents = ARRAY_SIZE(disp_cc_1_parent_data_0), 446 .flags = CLK_SET_RATE_PARENT, 447 .ops = &clk_dp_ops, 448 }, 449 }; 450 451 static struct clk_rcg2 mdss_1_disp_cc_mdss_esc0_clk_src = { 452 .cmd_rcgr = 0x8124, 453 .mnd_width = 0, 454 .hid_width = 5, 455 .parent_map = disp_cc_1_parent_map_4, 456 .freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, 457 .clkr.hw.init = &(const struct clk_init_data) { 458 .name = "mdss_1_disp_cc_mdss_esc0_clk_src", 459 .parent_data = disp_cc_1_parent_data_4, 460 .num_parents = ARRAY_SIZE(disp_cc_1_parent_data_4), 461 .flags = CLK_SET_RATE_PARENT, 462 .ops = &clk_rcg2_shared_ops, 463 }, 464 }; 465 466 static struct clk_rcg2 mdss_1_disp_cc_mdss_esc1_clk_src = { 467 .cmd_rcgr = 0x813c, 468 .mnd_width = 0, 469 .hid_width = 5, 470 .parent_map = disp_cc_1_parent_map_4, 471 .freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, 472 .clkr.hw.init = &(const struct clk_init_data) { 473 .name = "mdss_1_disp_cc_mdss_esc1_clk_src", 474 .parent_data = disp_cc_1_parent_data_4, 475 .num_parents = ARRAY_SIZE(disp_cc_1_parent_data_4), 476 .flags = CLK_SET_RATE_PARENT, 477 .ops = &clk_rcg2_shared_ops, 478 }, 479 }; 480 481 static const struct freq_tbl ftbl_mdss_1_disp_cc_mdss_mdp_clk_src[] = { 482 F(375000000, P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 483 F(500000000, P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 484 F(575000000, P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 485 F(650000000, P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 486 { } 487 }; 488 489 static struct clk_rcg2 mdss_1_disp_cc_mdss_mdp_clk_src = { 490 .cmd_rcgr = 0x80bc, 491 .mnd_width = 0, 492 .hid_width = 5, 493 .parent_map = disp_cc_1_parent_map_6, 494 .freq_tbl = ftbl_mdss_1_disp_cc_mdss_mdp_clk_src, 495 .clkr.hw.init = &(const struct clk_init_data) { 496 .name = "mdss_1_disp_cc_mdss_mdp_clk_src", 497 .parent_data = disp_cc_1_parent_data_6, 498 .num_parents = ARRAY_SIZE(disp_cc_1_parent_data_6), 499 .flags = CLK_SET_RATE_PARENT, 500 .ops = &clk_rcg2_shared_ops, 501 }, 502 }; 503 504 static struct clk_rcg2 mdss_1_disp_cc_mdss_pclk0_clk_src = { 505 .cmd_rcgr = 0x808c, 506 .mnd_width = 8, 507 .hid_width = 5, 508 .parent_map = disp_cc_1_parent_map_1, 509 .freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, 510 .clkr.hw.init = &(const struct clk_init_data) { 511 .name = "mdss_1_disp_cc_mdss_pclk0_clk_src", 512 .parent_data = disp_cc_1_parent_data_1, 513 .num_parents = ARRAY_SIZE(disp_cc_1_parent_data_1), 514 .flags = CLK_SET_RATE_PARENT, 515 .ops = &clk_pixel_ops, 516 }, 517 }; 518 519 static struct clk_rcg2 mdss_1_disp_cc_mdss_pclk1_clk_src = { 520 .cmd_rcgr = 0x80a4, 521 .mnd_width = 8, 522 .hid_width = 5, 523 .parent_map = disp_cc_1_parent_map_1, 524 .freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, 525 .clkr.hw.init = &(const struct clk_init_data) { 526 .name = "mdss_1_disp_cc_mdss_pclk1_clk_src", 527 .parent_data = disp_cc_1_parent_data_1, 528 .num_parents = ARRAY_SIZE(disp_cc_1_parent_data_1), 529 .flags = CLK_SET_RATE_PARENT, 530 .ops = &clk_pixel_ops, 531 }, 532 }; 533 534 static struct clk_rcg2 mdss_1_disp_cc_mdss_vsync_clk_src = { 535 .cmd_rcgr = 0x80d4, 536 .mnd_width = 0, 537 .hid_width = 5, 538 .parent_map = disp_cc_1_parent_map_2, 539 .freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, 540 .clkr.hw.init = &(const struct clk_init_data) { 541 .name = "mdss_1_disp_cc_mdss_vsync_clk_src", 542 .parent_data = disp_cc_1_parent_data_2, 543 .num_parents = ARRAY_SIZE(disp_cc_1_parent_data_2), 544 .flags = CLK_SET_RATE_PARENT, 545 .ops = &clk_rcg2_shared_ops, 546 }, 547 }; 548 549 static const struct freq_tbl ftbl_mdss_1_disp_cc_sleep_clk_src[] = { 550 F(32000, P_SLEEP_CLK, 1, 0, 0), 551 { } 552 }; 553 554 static struct clk_rcg2 mdss_1_disp_cc_sleep_clk_src = { 555 .cmd_rcgr = 0xc058, 556 .mnd_width = 0, 557 .hid_width = 5, 558 .parent_map = disp_cc_1_parent_map_7, 559 .freq_tbl = ftbl_mdss_1_disp_cc_sleep_clk_src, 560 .clkr.hw.init = &(const struct clk_init_data) { 561 .name = "mdss_1_disp_cc_sleep_clk_src", 562 .parent_data = disp_cc_1_parent_data_7_ao, 563 .num_parents = ARRAY_SIZE(disp_cc_1_parent_data_7_ao), 564 .flags = CLK_SET_RATE_PARENT, 565 .ops = &clk_rcg2_shared_ops, 566 }, 567 }; 568 569 static struct clk_rcg2 mdss_1_disp_cc_xo_clk_src = { 570 .cmd_rcgr = 0xc03c, 571 .mnd_width = 0, 572 .hid_width = 5, 573 .parent_map = disp_cc_1_parent_map_2, 574 .freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, 575 .clkr.hw.init = &(const struct clk_init_data) { 576 .name = "mdss_1_disp_cc_xo_clk_src", 577 .parent_data = disp_cc_1_parent_data_2_ao, 578 .num_parents = ARRAY_SIZE(disp_cc_1_parent_data_2_ao), 579 .flags = CLK_SET_RATE_PARENT, 580 .ops = &clk_rcg2_shared_ops, 581 }, 582 }; 583 584 static struct clk_regmap_div mdss_1_disp_cc_mdss_byte0_div_clk_src = { 585 .reg = 0x8104, 586 .shift = 0, 587 .width = 4, 588 .clkr.hw.init = &(const struct clk_init_data) { 589 .name = "mdss_1_disp_cc_mdss_byte0_div_clk_src", 590 .parent_hws = (const struct clk_hw*[]) { 591 &mdss_1_disp_cc_mdss_byte0_clk_src.clkr.hw, 592 }, 593 .num_parents = 1, 594 .ops = &clk_regmap_div_ops, 595 }, 596 }; 597 598 static struct clk_regmap_div mdss_1_disp_cc_mdss_byte1_div_clk_src = { 599 .reg = 0x8120, 600 .shift = 0, 601 .width = 4, 602 .clkr.hw.init = &(const struct clk_init_data) { 603 .name = "mdss_1_disp_cc_mdss_byte1_div_clk_src", 604 .parent_hws = (const struct clk_hw*[]) { 605 &mdss_1_disp_cc_mdss_byte1_clk_src.clkr.hw, 606 }, 607 .num_parents = 1, 608 .ops = &clk_regmap_div_ops, 609 }, 610 }; 611 612 static struct clk_regmap_div mdss_1_disp_cc_mdss_dptx0_link_div_clk_src = { 613 .reg = 0x816c, 614 .shift = 0, 615 .width = 4, 616 .clkr.hw.init = &(const struct clk_init_data) { 617 .name = "mdss_1_disp_cc_mdss_dptx0_link_div_clk_src", 618 .parent_hws = (const struct clk_hw*[]) { 619 &mdss_1_disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 620 }, 621 .num_parents = 1, 622 .flags = CLK_SET_RATE_PARENT, 623 .ops = &clk_regmap_div_ro_ops, 624 }, 625 }; 626 627 static struct clk_regmap_div mdss_1_disp_cc_mdss_dptx1_link_div_clk_src = { 628 .reg = 0x8218, 629 .shift = 0, 630 .width = 4, 631 .clkr.hw.init = &(const struct clk_init_data) { 632 .name = "mdss_1_disp_cc_mdss_dptx1_link_div_clk_src", 633 .parent_hws = (const struct clk_hw*[]) { 634 &mdss_1_disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 635 }, 636 .num_parents = 1, 637 .flags = CLK_SET_RATE_PARENT, 638 .ops = &clk_regmap_div_ro_ops, 639 }, 640 }; 641 642 static struct clk_branch mdss_1_disp_cc_mdss_ahb1_clk = { 643 .halt_reg = 0x8088, 644 .halt_check = BRANCH_HALT, 645 .clkr = { 646 .enable_reg = 0x8088, 647 .enable_mask = BIT(0), 648 .hw.init = &(const struct clk_init_data) { 649 .name = "mdss_1_disp_cc_mdss_ahb1_clk", 650 .parent_hws = (const struct clk_hw*[]) { 651 &mdss_1_disp_cc_mdss_ahb_clk_src.clkr.hw, 652 }, 653 .num_parents = 1, 654 .flags = CLK_SET_RATE_PARENT, 655 .ops = &clk_branch2_ops, 656 }, 657 }, 658 }; 659 660 static struct clk_branch mdss_1_disp_cc_mdss_ahb_clk = { 661 .halt_reg = 0x8084, 662 .halt_check = BRANCH_HALT, 663 .clkr = { 664 .enable_reg = 0x8084, 665 .enable_mask = BIT(0), 666 .hw.init = &(const struct clk_init_data) { 667 .name = "mdss_1_disp_cc_mdss_ahb_clk", 668 .parent_hws = (const struct clk_hw*[]) { 669 &mdss_1_disp_cc_mdss_ahb_clk_src.clkr.hw, 670 }, 671 .num_parents = 1, 672 .flags = CLK_SET_RATE_PARENT, 673 .ops = &clk_branch2_ops, 674 }, 675 }, 676 }; 677 678 static struct clk_branch mdss_1_disp_cc_mdss_byte0_clk = { 679 .halt_reg = 0x8034, 680 .halt_check = BRANCH_HALT, 681 .clkr = { 682 .enable_reg = 0x8034, 683 .enable_mask = BIT(0), 684 .hw.init = &(const struct clk_init_data) { 685 .name = "mdss_1_disp_cc_mdss_byte0_clk", 686 .parent_hws = (const struct clk_hw*[]) { 687 &mdss_1_disp_cc_mdss_byte0_clk_src.clkr.hw, 688 }, 689 .num_parents = 1, 690 .flags = CLK_SET_RATE_PARENT, 691 .ops = &clk_branch2_ops, 692 }, 693 }, 694 }; 695 696 static struct clk_branch mdss_1_disp_cc_mdss_byte0_intf_clk = { 697 .halt_reg = 0x8038, 698 .halt_check = BRANCH_HALT, 699 .clkr = { 700 .enable_reg = 0x8038, 701 .enable_mask = BIT(0), 702 .hw.init = &(const struct clk_init_data) { 703 .name = "mdss_1_disp_cc_mdss_byte0_intf_clk", 704 .parent_hws = (const struct clk_hw*[]) { 705 &mdss_1_disp_cc_mdss_byte0_div_clk_src.clkr.hw, 706 }, 707 .num_parents = 1, 708 .flags = CLK_SET_RATE_PARENT, 709 .ops = &clk_branch2_ops, 710 }, 711 }, 712 }; 713 714 static struct clk_branch mdss_1_disp_cc_mdss_byte1_clk = { 715 .halt_reg = 0x803c, 716 .halt_check = BRANCH_HALT, 717 .clkr = { 718 .enable_reg = 0x803c, 719 .enable_mask = BIT(0), 720 .hw.init = &(const struct clk_init_data) { 721 .name = "mdss_1_disp_cc_mdss_byte1_clk", 722 .parent_hws = (const struct clk_hw*[]) { 723 &mdss_1_disp_cc_mdss_byte1_clk_src.clkr.hw, 724 }, 725 .num_parents = 1, 726 .flags = CLK_SET_RATE_PARENT, 727 .ops = &clk_branch2_ops, 728 }, 729 }, 730 }; 731 732 static struct clk_branch mdss_1_disp_cc_mdss_byte1_intf_clk = { 733 .halt_reg = 0x8040, 734 .halt_check = BRANCH_HALT, 735 .clkr = { 736 .enable_reg = 0x8040, 737 .enable_mask = BIT(0), 738 .hw.init = &(const struct clk_init_data) { 739 .name = "mdss_1_disp_cc_mdss_byte1_intf_clk", 740 .parent_hws = (const struct clk_hw*[]) { 741 &mdss_1_disp_cc_mdss_byte1_div_clk_src.clkr.hw, 742 }, 743 .num_parents = 1, 744 .flags = CLK_SET_RATE_PARENT, 745 .ops = &clk_branch2_ops, 746 }, 747 }, 748 }; 749 750 static struct clk_branch mdss_1_disp_cc_mdss_dptx0_aux_clk = { 751 .halt_reg = 0x805c, 752 .halt_check = BRANCH_HALT, 753 .clkr = { 754 .enable_reg = 0x805c, 755 .enable_mask = BIT(0), 756 .hw.init = &(const struct clk_init_data) { 757 .name = "mdss_1_disp_cc_mdss_dptx0_aux_clk", 758 .parent_hws = (const struct clk_hw*[]) { 759 &mdss_1_disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, 760 }, 761 .num_parents = 1, 762 .flags = CLK_SET_RATE_PARENT, 763 .ops = &clk_branch2_ops, 764 }, 765 }, 766 }; 767 768 static struct clk_branch mdss_1_disp_cc_mdss_dptx0_crypto_clk = { 769 .halt_reg = 0x8058, 770 .halt_check = BRANCH_HALT, 771 .clkr = { 772 .enable_reg = 0x8058, 773 .enable_mask = BIT(0), 774 .hw.init = &(const struct clk_init_data) { 775 .name = "mdss_1_disp_cc_mdss_dptx0_crypto_clk", 776 .parent_hws = (const struct clk_hw*[]) { 777 &mdss_1_disp_cc_mdss_dptx0_crypto_clk_src.clkr.hw, 778 }, 779 .num_parents = 1, 780 .flags = CLK_SET_RATE_PARENT, 781 .ops = &clk_branch2_ops, 782 }, 783 }, 784 }; 785 786 static struct clk_branch mdss_1_disp_cc_mdss_dptx0_link_clk = { 787 .halt_reg = 0x804c, 788 .halt_check = BRANCH_HALT, 789 .clkr = { 790 .enable_reg = 0x804c, 791 .enable_mask = BIT(0), 792 .hw.init = &(const struct clk_init_data) { 793 .name = "mdss_1_disp_cc_mdss_dptx0_link_clk", 794 .parent_hws = (const struct clk_hw*[]) { 795 &mdss_1_disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 796 }, 797 .num_parents = 1, 798 .flags = CLK_SET_RATE_PARENT, 799 .ops = &clk_branch2_ops, 800 }, 801 }, 802 }; 803 804 static struct clk_branch mdss_1_disp_cc_mdss_dptx0_link_intf_clk = { 805 .halt_reg = 0x8050, 806 .halt_check = BRANCH_HALT, 807 .clkr = { 808 .enable_reg = 0x8050, 809 .enable_mask = BIT(0), 810 .hw.init = &(const struct clk_init_data) { 811 .name = "mdss_1_disp_cc_mdss_dptx0_link_intf_clk", 812 .parent_hws = (const struct clk_hw*[]) { 813 &mdss_1_disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 814 }, 815 .num_parents = 1, 816 .flags = CLK_SET_RATE_PARENT, 817 .ops = &clk_branch2_ops, 818 }, 819 }, 820 }; 821 822 static struct clk_branch mdss_1_disp_cc_mdss_dptx0_pixel0_clk = { 823 .halt_reg = 0x8060, 824 .halt_check = BRANCH_HALT, 825 .clkr = { 826 .enable_reg = 0x8060, 827 .enable_mask = BIT(0), 828 .hw.init = &(const struct clk_init_data) { 829 .name = "mdss_1_disp_cc_mdss_dptx0_pixel0_clk", 830 .parent_hws = (const struct clk_hw*[]) { 831 &mdss_1_disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, 832 }, 833 .num_parents = 1, 834 .flags = CLK_SET_RATE_PARENT, 835 .ops = &clk_branch2_ops, 836 }, 837 }, 838 }; 839 840 static struct clk_branch mdss_1_disp_cc_mdss_dptx0_pixel1_clk = { 841 .halt_reg = 0x8064, 842 .halt_check = BRANCH_HALT, 843 .clkr = { 844 .enable_reg = 0x8064, 845 .enable_mask = BIT(0), 846 .hw.init = &(const struct clk_init_data) { 847 .name = "mdss_1_disp_cc_mdss_dptx0_pixel1_clk", 848 .parent_hws = (const struct clk_hw*[]) { 849 &mdss_1_disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, 850 }, 851 .num_parents = 1, 852 .flags = CLK_SET_RATE_PARENT, 853 .ops = &clk_branch2_ops, 854 }, 855 }, 856 }; 857 858 static struct clk_branch mdss_1_disp_cc_mdss_dptx0_pixel2_clk = { 859 .halt_reg = 0x8264, 860 .halt_check = BRANCH_HALT, 861 .clkr = { 862 .enable_reg = 0x8264, 863 .enable_mask = BIT(0), 864 .hw.init = &(const struct clk_init_data) { 865 .name = "mdss_1_disp_cc_mdss_dptx0_pixel2_clk", 866 .parent_hws = (const struct clk_hw*[]) { 867 &mdss_1_disp_cc_mdss_dptx0_pixel2_clk_src.clkr.hw, 868 }, 869 .num_parents = 1, 870 .flags = CLK_SET_RATE_PARENT, 871 .ops = &clk_branch2_ops, 872 }, 873 }, 874 }; 875 876 static struct clk_branch mdss_1_disp_cc_mdss_dptx0_pixel3_clk = { 877 .halt_reg = 0x8268, 878 .halt_check = BRANCH_HALT, 879 .clkr = { 880 .enable_reg = 0x8268, 881 .enable_mask = BIT(0), 882 .hw.init = &(const struct clk_init_data) { 883 .name = "mdss_1_disp_cc_mdss_dptx0_pixel3_clk", 884 .parent_hws = (const struct clk_hw*[]) { 885 &mdss_1_disp_cc_mdss_dptx0_pixel3_clk_src.clkr.hw, 886 }, 887 .num_parents = 1, 888 .flags = CLK_SET_RATE_PARENT, 889 .ops = &clk_branch2_ops, 890 }, 891 }, 892 }; 893 894 static struct clk_branch mdss_1_disp_cc_mdss_dptx0_usb_router_link_intf_clk = { 895 .halt_reg = 0x8054, 896 .halt_check = BRANCH_HALT, 897 .clkr = { 898 .enable_reg = 0x8054, 899 .enable_mask = BIT(0), 900 .hw.init = &(const struct clk_init_data) { 901 .name = "mdss_1_disp_cc_mdss_dptx0_usb_router_link_intf_clk", 902 .parent_hws = (const struct clk_hw*[]) { 903 &mdss_1_disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 904 }, 905 .num_parents = 1, 906 .flags = CLK_SET_RATE_PARENT, 907 .ops = &clk_branch2_ops, 908 }, 909 }, 910 }; 911 912 static struct clk_branch mdss_1_disp_cc_mdss_dptx1_aux_clk = { 913 .halt_reg = 0x8080, 914 .halt_check = BRANCH_HALT, 915 .clkr = { 916 .enable_reg = 0x8080, 917 .enable_mask = BIT(0), 918 .hw.init = &(const struct clk_init_data) { 919 .name = "mdss_1_disp_cc_mdss_dptx1_aux_clk", 920 .parent_hws = (const struct clk_hw*[]) { 921 &mdss_1_disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, 922 }, 923 .num_parents = 1, 924 .flags = CLK_SET_RATE_PARENT, 925 .ops = &clk_branch2_ops, 926 }, 927 }, 928 }; 929 930 static struct clk_branch mdss_1_disp_cc_mdss_dptx1_crypto_clk = { 931 .halt_reg = 0x807c, 932 .halt_check = BRANCH_HALT, 933 .clkr = { 934 .enable_reg = 0x807c, 935 .enable_mask = BIT(0), 936 .hw.init = &(const struct clk_init_data) { 937 .name = "mdss_1_disp_cc_mdss_dptx1_crypto_clk", 938 .parent_hws = (const struct clk_hw*[]) { 939 &mdss_1_disp_cc_mdss_dptx1_crypto_clk_src.clkr.hw, 940 }, 941 .num_parents = 1, 942 .flags = CLK_SET_RATE_PARENT, 943 .ops = &clk_branch2_ops, 944 }, 945 }, 946 }; 947 948 static struct clk_branch mdss_1_disp_cc_mdss_dptx1_link_clk = { 949 .halt_reg = 0x8070, 950 .halt_check = BRANCH_HALT, 951 .clkr = { 952 .enable_reg = 0x8070, 953 .enable_mask = BIT(0), 954 .hw.init = &(const struct clk_init_data) { 955 .name = "mdss_1_disp_cc_mdss_dptx1_link_clk", 956 .parent_hws = (const struct clk_hw*[]) { 957 &mdss_1_disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 958 }, 959 .num_parents = 1, 960 .flags = CLK_SET_RATE_PARENT, 961 .ops = &clk_branch2_ops, 962 }, 963 }, 964 }; 965 966 static struct clk_branch mdss_1_disp_cc_mdss_dptx1_link_intf_clk = { 967 .halt_reg = 0x8074, 968 .halt_check = BRANCH_HALT, 969 .clkr = { 970 .enable_reg = 0x8074, 971 .enable_mask = BIT(0), 972 .hw.init = &(const struct clk_init_data) { 973 .name = "mdss_1_disp_cc_mdss_dptx1_link_intf_clk", 974 .parent_hws = (const struct clk_hw*[]) { 975 &mdss_1_disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 976 }, 977 .num_parents = 1, 978 .flags = CLK_SET_RATE_PARENT, 979 .ops = &clk_branch2_ops, 980 }, 981 }, 982 }; 983 984 static struct clk_branch mdss_1_disp_cc_mdss_dptx1_pixel0_clk = { 985 .halt_reg = 0x8068, 986 .halt_check = BRANCH_HALT, 987 .clkr = { 988 .enable_reg = 0x8068, 989 .enable_mask = BIT(0), 990 .hw.init = &(const struct clk_init_data) { 991 .name = "mdss_1_disp_cc_mdss_dptx1_pixel0_clk", 992 .parent_hws = (const struct clk_hw*[]) { 993 &mdss_1_disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, 994 }, 995 .num_parents = 1, 996 .flags = CLK_SET_RATE_PARENT, 997 .ops = &clk_branch2_ops, 998 }, 999 }, 1000 }; 1001 1002 static struct clk_branch mdss_1_disp_cc_mdss_dptx1_pixel1_clk = { 1003 .halt_reg = 0x806c, 1004 .halt_check = BRANCH_HALT, 1005 .clkr = { 1006 .enable_reg = 0x806c, 1007 .enable_mask = BIT(0), 1008 .hw.init = &(const struct clk_init_data) { 1009 .name = "mdss_1_disp_cc_mdss_dptx1_pixel1_clk", 1010 .parent_hws = (const struct clk_hw*[]) { 1011 &mdss_1_disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, 1012 }, 1013 .num_parents = 1, 1014 .flags = CLK_SET_RATE_PARENT, 1015 .ops = &clk_branch2_ops, 1016 }, 1017 }, 1018 }; 1019 1020 static struct clk_branch mdss_1_disp_cc_mdss_dptx1_usb_router_link_intf_clk = { 1021 .halt_reg = 0x8078, 1022 .halt_check = BRANCH_HALT, 1023 .clkr = { 1024 .enable_reg = 0x8078, 1025 .enable_mask = BIT(0), 1026 .hw.init = &(const struct clk_init_data) { 1027 .name = "mdss_1_disp_cc_mdss_dptx1_usb_router_link_intf_clk", 1028 .parent_hws = (const struct clk_hw*[]) { 1029 &mdss_1_disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1030 }, 1031 .num_parents = 1, 1032 .flags = CLK_SET_RATE_PARENT, 1033 .ops = &clk_branch2_ops, 1034 }, 1035 }, 1036 }; 1037 1038 static struct clk_branch mdss_1_disp_cc_mdss_esc0_clk = { 1039 .halt_reg = 0x8044, 1040 .halt_check = BRANCH_HALT, 1041 .clkr = { 1042 .enable_reg = 0x8044, 1043 .enable_mask = BIT(0), 1044 .hw.init = &(const struct clk_init_data) { 1045 .name = "mdss_1_disp_cc_mdss_esc0_clk", 1046 .parent_hws = (const struct clk_hw*[]) { 1047 &mdss_1_disp_cc_mdss_esc0_clk_src.clkr.hw, 1048 }, 1049 .num_parents = 1, 1050 .flags = CLK_SET_RATE_PARENT, 1051 .ops = &clk_branch2_ops, 1052 }, 1053 }, 1054 }; 1055 1056 static struct clk_branch mdss_1_disp_cc_mdss_esc1_clk = { 1057 .halt_reg = 0x8048, 1058 .halt_check = BRANCH_HALT, 1059 .clkr = { 1060 .enable_reg = 0x8048, 1061 .enable_mask = BIT(0), 1062 .hw.init = &(const struct clk_init_data) { 1063 .name = "mdss_1_disp_cc_mdss_esc1_clk", 1064 .parent_hws = (const struct clk_hw*[]) { 1065 &mdss_1_disp_cc_mdss_esc1_clk_src.clkr.hw, 1066 }, 1067 .num_parents = 1, 1068 .flags = CLK_SET_RATE_PARENT, 1069 .ops = &clk_branch2_ops, 1070 }, 1071 }, 1072 }; 1073 1074 static struct clk_branch mdss_1_disp_cc_mdss_mdp1_clk = { 1075 .halt_reg = 0x8014, 1076 .halt_check = BRANCH_HALT, 1077 .clkr = { 1078 .enable_reg = 0x8014, 1079 .enable_mask = BIT(0), 1080 .hw.init = &(const struct clk_init_data) { 1081 .name = "mdss_1_disp_cc_mdss_mdp1_clk", 1082 .parent_hws = (const struct clk_hw*[]) { 1083 &mdss_1_disp_cc_mdss_mdp_clk_src.clkr.hw, 1084 }, 1085 .num_parents = 1, 1086 .flags = CLK_SET_RATE_PARENT, 1087 .ops = &clk_branch2_ops, 1088 }, 1089 }, 1090 }; 1091 1092 static struct clk_branch mdss_1_disp_cc_mdss_mdp_clk = { 1093 .halt_reg = 0x800c, 1094 .halt_check = BRANCH_HALT, 1095 .clkr = { 1096 .enable_reg = 0x800c, 1097 .enable_mask = BIT(0), 1098 .hw.init = &(const struct clk_init_data) { 1099 .name = "mdss_1_disp_cc_mdss_mdp_clk", 1100 .parent_hws = (const struct clk_hw*[]) { 1101 &mdss_1_disp_cc_mdss_mdp_clk_src.clkr.hw, 1102 }, 1103 .num_parents = 1, 1104 .flags = CLK_SET_RATE_PARENT, 1105 .ops = &clk_branch2_ops, 1106 }, 1107 }, 1108 }; 1109 1110 static struct clk_branch mdss_1_disp_cc_mdss_mdp_lut1_clk = { 1111 .halt_reg = 0x8024, 1112 .halt_check = BRANCH_HALT_VOTED, 1113 .clkr = { 1114 .enable_reg = 0x8024, 1115 .enable_mask = BIT(0), 1116 .hw.init = &(const struct clk_init_data) { 1117 .name = "mdss_1_disp_cc_mdss_mdp_lut1_clk", 1118 .parent_hws = (const struct clk_hw*[]) { 1119 &mdss_1_disp_cc_mdss_mdp_clk_src.clkr.hw, 1120 }, 1121 .num_parents = 1, 1122 .flags = CLK_SET_RATE_PARENT, 1123 .ops = &clk_branch2_ops, 1124 }, 1125 }, 1126 }; 1127 1128 static struct clk_branch mdss_1_disp_cc_mdss_mdp_lut_clk = { 1129 .halt_reg = 0x801c, 1130 .halt_check = BRANCH_HALT_VOTED, 1131 .clkr = { 1132 .enable_reg = 0x801c, 1133 .enable_mask = BIT(0), 1134 .hw.init = &(const struct clk_init_data) { 1135 .name = "mdss_1_disp_cc_mdss_mdp_lut_clk", 1136 .parent_hws = (const struct clk_hw*[]) { 1137 &mdss_1_disp_cc_mdss_mdp_clk_src.clkr.hw, 1138 }, 1139 .num_parents = 1, 1140 .flags = CLK_SET_RATE_PARENT, 1141 .ops = &clk_branch2_ops, 1142 }, 1143 }, 1144 }; 1145 1146 static struct clk_branch mdss_1_disp_cc_mdss_non_gdsc_ahb_clk = { 1147 .halt_reg = 0xa004, 1148 .halt_check = BRANCH_HALT_VOTED, 1149 .clkr = { 1150 .enable_reg = 0xa004, 1151 .enable_mask = BIT(0), 1152 .hw.init = &(const struct clk_init_data) { 1153 .name = "mdss_1_disp_cc_mdss_non_gdsc_ahb_clk", 1154 .parent_hws = (const struct clk_hw*[]) { 1155 &mdss_1_disp_cc_mdss_ahb_clk_src.clkr.hw, 1156 }, 1157 .num_parents = 1, 1158 .flags = CLK_SET_RATE_PARENT, 1159 .ops = &clk_branch2_ops, 1160 }, 1161 }, 1162 }; 1163 1164 static struct clk_branch mdss_1_disp_cc_mdss_pclk0_clk = { 1165 .halt_reg = 0x8004, 1166 .halt_check = BRANCH_HALT, 1167 .clkr = { 1168 .enable_reg = 0x8004, 1169 .enable_mask = BIT(0), 1170 .hw.init = &(const struct clk_init_data) { 1171 .name = "mdss_1_disp_cc_mdss_pclk0_clk", 1172 .parent_hws = (const struct clk_hw*[]) { 1173 &mdss_1_disp_cc_mdss_pclk0_clk_src.clkr.hw, 1174 }, 1175 .num_parents = 1, 1176 .flags = CLK_SET_RATE_PARENT, 1177 .ops = &clk_branch2_ops, 1178 }, 1179 }, 1180 }; 1181 1182 static struct clk_branch mdss_1_disp_cc_mdss_pclk1_clk = { 1183 .halt_reg = 0x8008, 1184 .halt_check = BRANCH_HALT, 1185 .clkr = { 1186 .enable_reg = 0x8008, 1187 .enable_mask = BIT(0), 1188 .hw.init = &(const struct clk_init_data) { 1189 .name = "mdss_1_disp_cc_mdss_pclk1_clk", 1190 .parent_hws = (const struct clk_hw*[]) { 1191 &mdss_1_disp_cc_mdss_pclk1_clk_src.clkr.hw, 1192 }, 1193 .num_parents = 1, 1194 .flags = CLK_SET_RATE_PARENT, 1195 .ops = &clk_branch2_ops, 1196 }, 1197 }, 1198 }; 1199 1200 static struct clk_branch mdss_1_disp_cc_mdss_pll_lock_monitor_clk = { 1201 .halt_reg = 0xe000, 1202 .halt_check = BRANCH_HALT, 1203 .clkr = { 1204 .enable_reg = 0xe000, 1205 .enable_mask = BIT(0), 1206 .hw.init = &(const struct clk_init_data) { 1207 .name = "mdss_1_disp_cc_mdss_pll_lock_monitor_clk", 1208 .parent_hws = (const struct clk_hw*[]) { 1209 &mdss_1_disp_cc_xo_clk_src.clkr.hw, 1210 }, 1211 .num_parents = 1, 1212 .flags = CLK_SET_RATE_PARENT, 1213 .ops = &clk_branch2_ops, 1214 }, 1215 }, 1216 }; 1217 1218 static struct clk_branch mdss_1_disp_cc_mdss_rscc_ahb_clk = { 1219 .halt_reg = 0xa00c, 1220 .halt_check = BRANCH_HALT, 1221 .clkr = { 1222 .enable_reg = 0xa00c, 1223 .enable_mask = BIT(0), 1224 .hw.init = &(const struct clk_init_data) { 1225 .name = "mdss_1_disp_cc_mdss_rscc_ahb_clk", 1226 .parent_hws = (const struct clk_hw*[]) { 1227 &mdss_1_disp_cc_mdss_ahb_clk_src.clkr.hw, 1228 }, 1229 .num_parents = 1, 1230 .flags = CLK_SET_RATE_PARENT, 1231 .ops = &clk_branch2_ops, 1232 }, 1233 }, 1234 }; 1235 1236 static struct clk_branch mdss_1_disp_cc_mdss_rscc_vsync_clk = { 1237 .halt_reg = 0xa008, 1238 .halt_check = BRANCH_HALT, 1239 .clkr = { 1240 .enable_reg = 0xa008, 1241 .enable_mask = BIT(0), 1242 .hw.init = &(const struct clk_init_data) { 1243 .name = "mdss_1_disp_cc_mdss_rscc_vsync_clk", 1244 .parent_hws = (const struct clk_hw*[]) { 1245 &mdss_1_disp_cc_mdss_vsync_clk_src.clkr.hw, 1246 }, 1247 .num_parents = 1, 1248 .flags = CLK_SET_RATE_PARENT, 1249 .ops = &clk_branch2_ops, 1250 }, 1251 }, 1252 }; 1253 1254 static struct clk_branch mdss_1_disp_cc_mdss_vsync1_clk = { 1255 .halt_reg = 0x8030, 1256 .halt_check = BRANCH_HALT, 1257 .clkr = { 1258 .enable_reg = 0x8030, 1259 .enable_mask = BIT(0), 1260 .hw.init = &(const struct clk_init_data) { 1261 .name = "mdss_1_disp_cc_mdss_vsync1_clk", 1262 .parent_hws = (const struct clk_hw*[]) { 1263 &mdss_1_disp_cc_mdss_vsync_clk_src.clkr.hw, 1264 }, 1265 .num_parents = 1, 1266 .flags = CLK_SET_RATE_PARENT, 1267 .ops = &clk_branch2_ops, 1268 }, 1269 }, 1270 }; 1271 1272 static struct clk_branch mdss_1_disp_cc_mdss_vsync_clk = { 1273 .halt_reg = 0x802c, 1274 .halt_check = BRANCH_HALT, 1275 .clkr = { 1276 .enable_reg = 0x802c, 1277 .enable_mask = BIT(0), 1278 .hw.init = &(const struct clk_init_data) { 1279 .name = "mdss_1_disp_cc_mdss_vsync_clk", 1280 .parent_hws = (const struct clk_hw*[]) { 1281 &mdss_1_disp_cc_mdss_vsync_clk_src.clkr.hw, 1282 }, 1283 .num_parents = 1, 1284 .flags = CLK_SET_RATE_PARENT, 1285 .ops = &clk_branch2_ops, 1286 }, 1287 }, 1288 }; 1289 1290 static struct clk_branch mdss_1_disp_cc_sm_obs_clk = { 1291 .halt_reg = 0x11014, 1292 .halt_check = BRANCH_HALT_SKIP, 1293 .clkr = { 1294 .enable_reg = 0x11014, 1295 .enable_mask = BIT(0), 1296 .hw.init = &(const struct clk_init_data) { 1297 .name = "mdss_1_disp_cc_sm_obs_clk", 1298 .ops = &clk_branch2_ops, 1299 }, 1300 }, 1301 }; 1302 1303 static struct gdsc mdss_1_disp_cc_mdss_core_gdsc = { 1304 .gdscr = 0x9000, 1305 .en_rest_wait_val = 0x2, 1306 .en_few_wait_val = 0x2, 1307 .clk_dis_wait_val = 0xf, 1308 .pd = { 1309 .name = "mdss_1_disp_cc_mdss_core_gdsc", 1310 }, 1311 .pwrsts = PWRSTS_OFF_ON, 1312 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL, 1313 }; 1314 1315 static struct gdsc mdss_1_disp_cc_mdss_core_int2_gdsc = { 1316 .gdscr = 0xd000, 1317 .en_rest_wait_val = 0x2, 1318 .en_few_wait_val = 0x2, 1319 .clk_dis_wait_val = 0xf, 1320 .pd = { 1321 .name = "mdss_1_disp_cc_mdss_core_int2_gdsc", 1322 }, 1323 .pwrsts = PWRSTS_OFF_ON, 1324 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL, 1325 }; 1326 1327 static struct clk_regmap *disp_cc_1_sa8775p_clocks[] = { 1328 [MDSS_DISP_CC_MDSS_AHB1_CLK] = &mdss_1_disp_cc_mdss_ahb1_clk.clkr, 1329 [MDSS_DISP_CC_MDSS_AHB_CLK] = &mdss_1_disp_cc_mdss_ahb_clk.clkr, 1330 [MDSS_DISP_CC_MDSS_AHB_CLK_SRC] = &mdss_1_disp_cc_mdss_ahb_clk_src.clkr, 1331 [MDSS_DISP_CC_MDSS_BYTE0_CLK] = &mdss_1_disp_cc_mdss_byte0_clk.clkr, 1332 [MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC] = &mdss_1_disp_cc_mdss_byte0_clk_src.clkr, 1333 [MDSS_DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &mdss_1_disp_cc_mdss_byte0_div_clk_src.clkr, 1334 [MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK] = &mdss_1_disp_cc_mdss_byte0_intf_clk.clkr, 1335 [MDSS_DISP_CC_MDSS_BYTE1_CLK] = &mdss_1_disp_cc_mdss_byte1_clk.clkr, 1336 [MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC] = &mdss_1_disp_cc_mdss_byte1_clk_src.clkr, 1337 [MDSS_DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &mdss_1_disp_cc_mdss_byte1_div_clk_src.clkr, 1338 [MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK] = &mdss_1_disp_cc_mdss_byte1_intf_clk.clkr, 1339 [MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK] = &mdss_1_disp_cc_mdss_dptx0_aux_clk.clkr, 1340 [MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &mdss_1_disp_cc_mdss_dptx0_aux_clk_src.clkr, 1341 [MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &mdss_1_disp_cc_mdss_dptx0_crypto_clk.clkr, 1342 [MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK_SRC] = &mdss_1_disp_cc_mdss_dptx0_crypto_clk_src.clkr, 1343 [MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK] = &mdss_1_disp_cc_mdss_dptx0_link_clk.clkr, 1344 [MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &mdss_1_disp_cc_mdss_dptx0_link_clk_src.clkr, 1345 [MDSS_DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = 1346 &mdss_1_disp_cc_mdss_dptx0_link_div_clk_src.clkr, 1347 [MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &mdss_1_disp_cc_mdss_dptx0_link_intf_clk.clkr, 1348 [MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &mdss_1_disp_cc_mdss_dptx0_pixel0_clk.clkr, 1349 [MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &mdss_1_disp_cc_mdss_dptx0_pixel0_clk_src.clkr, 1350 [MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &mdss_1_disp_cc_mdss_dptx0_pixel1_clk.clkr, 1351 [MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &mdss_1_disp_cc_mdss_dptx0_pixel1_clk_src.clkr, 1352 [MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK] = &mdss_1_disp_cc_mdss_dptx0_pixel2_clk.clkr, 1353 [MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC] = &mdss_1_disp_cc_mdss_dptx0_pixel2_clk_src.clkr, 1354 [MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK] = &mdss_1_disp_cc_mdss_dptx0_pixel3_clk.clkr, 1355 [MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC] = &mdss_1_disp_cc_mdss_dptx0_pixel3_clk_src.clkr, 1356 [MDSS_DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = 1357 &mdss_1_disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, 1358 [MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK] = &mdss_1_disp_cc_mdss_dptx1_aux_clk.clkr, 1359 [MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &mdss_1_disp_cc_mdss_dptx1_aux_clk_src.clkr, 1360 [MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &mdss_1_disp_cc_mdss_dptx1_crypto_clk.clkr, 1361 [MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK_SRC] = &mdss_1_disp_cc_mdss_dptx1_crypto_clk_src.clkr, 1362 [MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK] = &mdss_1_disp_cc_mdss_dptx1_link_clk.clkr, 1363 [MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &mdss_1_disp_cc_mdss_dptx1_link_clk_src.clkr, 1364 [MDSS_DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = 1365 &mdss_1_disp_cc_mdss_dptx1_link_div_clk_src.clkr, 1366 [MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &mdss_1_disp_cc_mdss_dptx1_link_intf_clk.clkr, 1367 [MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &mdss_1_disp_cc_mdss_dptx1_pixel0_clk.clkr, 1368 [MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &mdss_1_disp_cc_mdss_dptx1_pixel0_clk_src.clkr, 1369 [MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &mdss_1_disp_cc_mdss_dptx1_pixel1_clk.clkr, 1370 [MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &mdss_1_disp_cc_mdss_dptx1_pixel1_clk_src.clkr, 1371 [MDSS_DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] = 1372 &mdss_1_disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, 1373 [MDSS_DISP_CC_MDSS_ESC0_CLK] = &mdss_1_disp_cc_mdss_esc0_clk.clkr, 1374 [MDSS_DISP_CC_MDSS_ESC0_CLK_SRC] = &mdss_1_disp_cc_mdss_esc0_clk_src.clkr, 1375 [MDSS_DISP_CC_MDSS_ESC1_CLK] = &mdss_1_disp_cc_mdss_esc1_clk.clkr, 1376 [MDSS_DISP_CC_MDSS_ESC1_CLK_SRC] = &mdss_1_disp_cc_mdss_esc1_clk_src.clkr, 1377 [MDSS_DISP_CC_MDSS_MDP1_CLK] = &mdss_1_disp_cc_mdss_mdp1_clk.clkr, 1378 [MDSS_DISP_CC_MDSS_MDP_CLK] = &mdss_1_disp_cc_mdss_mdp_clk.clkr, 1379 [MDSS_DISP_CC_MDSS_MDP_CLK_SRC] = &mdss_1_disp_cc_mdss_mdp_clk_src.clkr, 1380 [MDSS_DISP_CC_MDSS_MDP_LUT1_CLK] = &mdss_1_disp_cc_mdss_mdp_lut1_clk.clkr, 1381 [MDSS_DISP_CC_MDSS_MDP_LUT_CLK] = &mdss_1_disp_cc_mdss_mdp_lut_clk.clkr, 1382 [MDSS_DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &mdss_1_disp_cc_mdss_non_gdsc_ahb_clk.clkr, 1383 [MDSS_DISP_CC_MDSS_PCLK0_CLK] = &mdss_1_disp_cc_mdss_pclk0_clk.clkr, 1384 [MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC] = &mdss_1_disp_cc_mdss_pclk0_clk_src.clkr, 1385 [MDSS_DISP_CC_MDSS_PCLK1_CLK] = &mdss_1_disp_cc_mdss_pclk1_clk.clkr, 1386 [MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC] = &mdss_1_disp_cc_mdss_pclk1_clk_src.clkr, 1387 [MDSS_DISP_CC_MDSS_PLL_LOCK_MONITOR_CLK] = &mdss_1_disp_cc_mdss_pll_lock_monitor_clk.clkr, 1388 [MDSS_DISP_CC_MDSS_RSCC_AHB_CLK] = &mdss_1_disp_cc_mdss_rscc_ahb_clk.clkr, 1389 [MDSS_DISP_CC_MDSS_RSCC_VSYNC_CLK] = &mdss_1_disp_cc_mdss_rscc_vsync_clk.clkr, 1390 [MDSS_DISP_CC_MDSS_VSYNC1_CLK] = &mdss_1_disp_cc_mdss_vsync1_clk.clkr, 1391 [MDSS_DISP_CC_MDSS_VSYNC_CLK] = &mdss_1_disp_cc_mdss_vsync_clk.clkr, 1392 [MDSS_DISP_CC_MDSS_VSYNC_CLK_SRC] = &mdss_1_disp_cc_mdss_vsync_clk_src.clkr, 1393 [MDSS_DISP_CC_PLL0] = &mdss_1_disp_cc_pll0.clkr, 1394 [MDSS_DISP_CC_PLL1] = &mdss_1_disp_cc_pll1.clkr, 1395 [MDSS_DISP_CC_SLEEP_CLK_SRC] = &mdss_1_disp_cc_sleep_clk_src.clkr, 1396 [MDSS_DISP_CC_SM_OBS_CLK] = &mdss_1_disp_cc_sm_obs_clk.clkr, 1397 [MDSS_DISP_CC_XO_CLK_SRC] = &mdss_1_disp_cc_xo_clk_src.clkr, 1398 }; 1399 1400 static struct gdsc *disp_cc_1_sa8775p_gdscs[] = { 1401 [MDSS_DISP_CC_MDSS_CORE_GDSC] = &mdss_1_disp_cc_mdss_core_gdsc, 1402 [MDSS_DISP_CC_MDSS_CORE_INT2_GDSC] = &mdss_1_disp_cc_mdss_core_int2_gdsc, 1403 }; 1404 1405 static const struct qcom_reset_map disp_cc_1_sa8775p_resets[] = { 1406 [MDSS_DISP_CC_MDSS_CORE_BCR] = { 0x8000 }, 1407 [MDSS_DISP_CC_MDSS_RSCC_BCR] = { 0xa000 }, 1408 }; 1409 1410 static const struct regmap_config disp_cc_1_sa8775p_regmap_config = { 1411 .reg_bits = 32, 1412 .reg_stride = 4, 1413 .val_bits = 32, 1414 .max_register = 0x12414, 1415 .fast_io = true, 1416 }; 1417 1418 static const struct qcom_cc_desc disp_cc_1_sa8775p_desc = { 1419 .config = &disp_cc_1_sa8775p_regmap_config, 1420 .clks = disp_cc_1_sa8775p_clocks, 1421 .num_clks = ARRAY_SIZE(disp_cc_1_sa8775p_clocks), 1422 .resets = disp_cc_1_sa8775p_resets, 1423 .num_resets = ARRAY_SIZE(disp_cc_1_sa8775p_resets), 1424 .gdscs = disp_cc_1_sa8775p_gdscs, 1425 .num_gdscs = ARRAY_SIZE(disp_cc_1_sa8775p_gdscs), 1426 }; 1427 1428 static const struct of_device_id disp_cc_1_sa8775p_match_table[] = { 1429 { .compatible = "qcom,sa8775p-dispcc1" }, 1430 { } 1431 }; 1432 MODULE_DEVICE_TABLE(of, disp_cc_1_sa8775p_match_table); 1433 1434 static int disp_cc_1_sa8775p_probe(struct platform_device *pdev) 1435 { 1436 struct regmap *regmap; 1437 int ret; 1438 1439 ret = devm_pm_runtime_enable(&pdev->dev); 1440 if (ret) 1441 return ret; 1442 1443 ret = pm_runtime_resume_and_get(&pdev->dev); 1444 if (ret) 1445 return ret; 1446 1447 regmap = qcom_cc_map(pdev, &disp_cc_1_sa8775p_desc); 1448 if (IS_ERR(regmap)) { 1449 pm_runtime_put(&pdev->dev); 1450 return PTR_ERR(regmap); 1451 } 1452 1453 clk_lucid_evo_pll_configure(&mdss_1_disp_cc_pll0, regmap, &mdss_1_disp_cc_pll0_config); 1454 clk_lucid_evo_pll_configure(&mdss_1_disp_cc_pll1, regmap, &mdss_1_disp_cc_pll1_config); 1455 1456 /* Keep some clocks always enabled */ 1457 qcom_branch_set_clk_en(regmap, 0xc070); /* MDSS_1_DISP_CC_SLEEP_CLK */ 1458 qcom_branch_set_clk_en(regmap, 0xc054); /* MDSS_1_DISP_CC_XO_CLK */ 1459 1460 ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_1_sa8775p_desc, regmap); 1461 1462 pm_runtime_put(&pdev->dev); 1463 1464 return ret; 1465 } 1466 1467 static struct platform_driver disp_cc_1_sa8775p_driver = { 1468 .probe = disp_cc_1_sa8775p_probe, 1469 .driver = { 1470 .name = "dispcc1-sa8775p", 1471 .of_match_table = disp_cc_1_sa8775p_match_table, 1472 }, 1473 }; 1474 1475 module_platform_driver(disp_cc_1_sa8775p_driver); 1476 1477 MODULE_DESCRIPTION("QTI DISPCC1 SA8775P Driver"); 1478 MODULE_LICENSE("GPL"); 1479