1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved 4 * Copyright (c) 2023, Linaro Ltd. 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/err.h> 9 #include <linux/kernel.h> 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regmap.h> 15 16 #include <dt-bindings/clock/qcom,sm8650-dispcc.h> 17 18 #include "common.h" 19 #include "clk-alpha-pll.h" 20 #include "clk-branch.h" 21 #include "clk-pll.h" 22 #include "clk-rcg.h" 23 #include "clk-regmap.h" 24 #include "clk-regmap-divider.h" 25 #include "reset.h" 26 #include "gdsc.h" 27 28 /* Need to match the order of clocks in DT binding */ 29 enum { 30 DT_BI_TCXO, 31 DT_BI_TCXO_AO, 32 DT_AHB_CLK, 33 DT_SLEEP_CLK, 34 35 DT_DSI0_PHY_PLL_OUT_BYTECLK, 36 DT_DSI0_PHY_PLL_OUT_DSICLK, 37 DT_DSI1_PHY_PLL_OUT_BYTECLK, 38 DT_DSI1_PHY_PLL_OUT_DSICLK, 39 40 DT_DP0_PHY_PLL_LINK_CLK, 41 DT_DP0_PHY_PLL_VCO_DIV_CLK, 42 DT_DP1_PHY_PLL_LINK_CLK, 43 DT_DP1_PHY_PLL_VCO_DIV_CLK, 44 DT_DP2_PHY_PLL_LINK_CLK, 45 DT_DP2_PHY_PLL_VCO_DIV_CLK, 46 DT_DP3_PHY_PLL_LINK_CLK, 47 DT_DP3_PHY_PLL_VCO_DIV_CLK, 48 }; 49 50 #define DISP_CC_MISC_CMD 0xF000 51 52 enum { 53 P_BI_TCXO, 54 P_DISP_CC_PLL0_OUT_MAIN, 55 P_DISP_CC_PLL1_OUT_EVEN, 56 P_DISP_CC_PLL1_OUT_MAIN, 57 P_DP0_PHY_PLL_LINK_CLK, 58 P_DP0_PHY_PLL_VCO_DIV_CLK, 59 P_DP1_PHY_PLL_LINK_CLK, 60 P_DP1_PHY_PLL_VCO_DIV_CLK, 61 P_DP2_PHY_PLL_LINK_CLK, 62 P_DP2_PHY_PLL_VCO_DIV_CLK, 63 P_DP3_PHY_PLL_LINK_CLK, 64 P_DP3_PHY_PLL_VCO_DIV_CLK, 65 P_DSI0_PHY_PLL_OUT_BYTECLK, 66 P_DSI0_PHY_PLL_OUT_DSICLK, 67 P_DSI1_PHY_PLL_OUT_BYTECLK, 68 P_DSI1_PHY_PLL_OUT_DSICLK, 69 P_SLEEP_CLK, 70 }; 71 72 static const struct pll_vco lucid_ole_vco[] = { 73 { 249600000, 2100000000, 0 }, 74 }; 75 76 static const struct alpha_pll_config disp_cc_pll0_config = { 77 .l = 0xd, 78 .alpha = 0x6492, 79 .config_ctl_val = 0x20485699, 80 .config_ctl_hi_val = 0x00182261, 81 .config_ctl_hi1_val = 0x82aa299c, 82 .test_ctl_val = 0x00000000, 83 .test_ctl_hi_val = 0x00000003, 84 .test_ctl_hi1_val = 0x00009000, 85 .test_ctl_hi2_val = 0x00000034, 86 .user_ctl_val = 0x00000000, 87 .user_ctl_hi_val = 0x00000005, 88 }; 89 90 static struct clk_alpha_pll disp_cc_pll0 = { 91 .offset = 0x0, 92 .vco_table = lucid_ole_vco, 93 .num_vco = ARRAY_SIZE(lucid_ole_vco), 94 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 95 .clkr = { 96 .hw.init = &(const struct clk_init_data) { 97 .name = "disp_cc_pll0", 98 .parent_data = &(const struct clk_parent_data) { 99 .index = DT_BI_TCXO, 100 }, 101 .num_parents = 1, 102 .ops = &clk_alpha_pll_reset_lucid_ole_ops, 103 }, 104 }, 105 }; 106 107 static const struct alpha_pll_config disp_cc_pll1_config = { 108 .l = 0x1f, 109 .alpha = 0x4000, 110 .config_ctl_val = 0x20485699, 111 .config_ctl_hi_val = 0x00182261, 112 .config_ctl_hi1_val = 0x82aa299c, 113 .test_ctl_val = 0x00000000, 114 .test_ctl_hi_val = 0x00000003, 115 .test_ctl_hi1_val = 0x00009000, 116 .test_ctl_hi2_val = 0x00000034, 117 .user_ctl_val = 0x00000000, 118 .user_ctl_hi_val = 0x00000005, 119 }; 120 121 static struct clk_alpha_pll disp_cc_pll1 = { 122 .offset = 0x1000, 123 .vco_table = lucid_ole_vco, 124 .num_vco = ARRAY_SIZE(lucid_ole_vco), 125 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 126 .clkr = { 127 .hw.init = &(const struct clk_init_data) { 128 .name = "disp_cc_pll1", 129 .parent_data = &(const struct clk_parent_data) { 130 .index = DT_BI_TCXO, 131 }, 132 .num_parents = 1, 133 .ops = &clk_alpha_pll_reset_lucid_ole_ops, 134 }, 135 }, 136 }; 137 138 static const struct parent_map disp_cc_parent_map_0[] = { 139 { P_BI_TCXO, 0 }, 140 }; 141 142 static const struct clk_parent_data disp_cc_parent_data_0[] = { 143 { .index = DT_BI_TCXO }, 144 }; 145 146 static const struct clk_parent_data disp_cc_parent_data_0_ao[] = { 147 { .index = DT_BI_TCXO_AO }, 148 }; 149 150 static const struct parent_map disp_cc_parent_map_1[] = { 151 { P_BI_TCXO, 0 }, 152 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, 153 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, 154 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, 155 }; 156 157 static const struct clk_parent_data disp_cc_parent_data_1[] = { 158 { .index = DT_BI_TCXO }, 159 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 160 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 161 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 162 }; 163 164 static const struct parent_map disp_cc_parent_map_2[] = { 165 { P_BI_TCXO, 0 }, 166 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 167 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 168 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, 169 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 170 }; 171 172 static const struct clk_parent_data disp_cc_parent_data_2[] = { 173 { .index = DT_BI_TCXO }, 174 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, 175 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 176 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, 177 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 178 }; 179 180 static const struct parent_map disp_cc_parent_map_3[] = { 181 { P_BI_TCXO, 0 }, 182 { P_DP1_PHY_PLL_LINK_CLK, 2 }, 183 { P_DP2_PHY_PLL_LINK_CLK, 3 }, 184 { P_DP3_PHY_PLL_LINK_CLK, 4 }, 185 }; 186 187 static const struct clk_parent_data disp_cc_parent_data_3[] = { 188 { .index = DT_BI_TCXO }, 189 { .index = DT_DP1_PHY_PLL_LINK_CLK }, 190 { .index = DT_DP2_PHY_PLL_LINK_CLK }, 191 { .index = DT_DP3_PHY_PLL_LINK_CLK }, 192 }; 193 194 static const struct parent_map disp_cc_parent_map_4[] = { 195 { P_BI_TCXO, 0 }, 196 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 197 { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 }, 198 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, 199 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, 200 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, 201 }; 202 203 static const struct clk_parent_data disp_cc_parent_data_4[] = { 204 { .index = DT_BI_TCXO }, 205 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 206 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK }, 207 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 208 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 209 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 210 }; 211 212 static const struct parent_map disp_cc_parent_map_5[] = { 213 { P_BI_TCXO, 0 }, 214 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 215 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 216 }; 217 218 static const struct clk_parent_data disp_cc_parent_data_5[] = { 219 { .index = DT_BI_TCXO }, 220 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 221 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 222 }; 223 224 static const struct parent_map disp_cc_parent_map_6[] = { 225 { P_BI_TCXO, 0 }, 226 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 227 { P_DISP_CC_PLL1_OUT_EVEN, 6 }, 228 }; 229 230 static const struct clk_parent_data disp_cc_parent_data_6[] = { 231 { .index = DT_BI_TCXO }, 232 { .hw = &disp_cc_pll1.clkr.hw }, 233 { .hw = &disp_cc_pll1.clkr.hw }, 234 }; 235 236 static const struct parent_map disp_cc_parent_map_7[] = { 237 { P_BI_TCXO, 0 }, 238 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 239 { P_DP1_PHY_PLL_LINK_CLK, 2 }, 240 { P_DP2_PHY_PLL_LINK_CLK, 3 }, 241 { P_DP3_PHY_PLL_LINK_CLK, 4 }, 242 }; 243 244 static const struct clk_parent_data disp_cc_parent_data_7[] = { 245 { .index = DT_BI_TCXO }, 246 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 247 { .index = DT_DP1_PHY_PLL_LINK_CLK }, 248 { .index = DT_DP2_PHY_PLL_LINK_CLK }, 249 { .index = DT_DP3_PHY_PLL_LINK_CLK }, 250 }; 251 252 static const struct parent_map disp_cc_parent_map_8[] = { 253 { P_BI_TCXO, 0 }, 254 { P_DISP_CC_PLL0_OUT_MAIN, 1 }, 255 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 256 { P_DISP_CC_PLL1_OUT_EVEN, 6 }, 257 }; 258 259 static const struct clk_parent_data disp_cc_parent_data_8[] = { 260 { .index = DT_BI_TCXO }, 261 { .hw = &disp_cc_pll0.clkr.hw }, 262 { .hw = &disp_cc_pll1.clkr.hw }, 263 { .hw = &disp_cc_pll1.clkr.hw }, 264 }; 265 266 static const struct parent_map disp_cc_parent_map_9[] = { 267 { P_SLEEP_CLK, 0 }, 268 }; 269 270 static const struct clk_parent_data disp_cc_parent_data_9[] = { 271 { .index = DT_SLEEP_CLK }, 272 }; 273 274 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { 275 F(19200000, P_BI_TCXO, 1, 0, 0), 276 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), 277 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), 278 { } 279 }; 280 281 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { 282 .cmd_rcgr = 0x82e8, 283 .mnd_width = 0, 284 .hid_width = 5, 285 .parent_map = disp_cc_parent_map_6, 286 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 287 .clkr.hw.init = &(const struct clk_init_data) { 288 .name = "disp_cc_mdss_ahb_clk_src", 289 .parent_data = disp_cc_parent_data_6, 290 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 291 .flags = CLK_SET_RATE_PARENT, 292 .ops = &clk_rcg2_shared_ops, 293 }, 294 }; 295 296 static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = { 297 F(19200000, P_BI_TCXO, 1, 0, 0), 298 { } 299 }; 300 301 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { 302 .cmd_rcgr = 0x8108, 303 .mnd_width = 0, 304 .hid_width = 5, 305 .parent_map = disp_cc_parent_map_2, 306 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 307 .clkr.hw.init = &(const struct clk_init_data) { 308 .name = "disp_cc_mdss_byte0_clk_src", 309 .parent_data = disp_cc_parent_data_2, 310 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 311 .flags = CLK_SET_RATE_PARENT, 312 .ops = &clk_byte2_ops, 313 }, 314 }; 315 316 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { 317 .cmd_rcgr = 0x8124, 318 .mnd_width = 0, 319 .hid_width = 5, 320 .parent_map = disp_cc_parent_map_2, 321 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 322 .clkr.hw.init = &(const struct clk_init_data) { 323 .name = "disp_cc_mdss_byte1_clk_src", 324 .parent_data = disp_cc_parent_data_2, 325 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 326 .flags = CLK_SET_RATE_PARENT, 327 .ops = &clk_byte2_ops, 328 }, 329 }; 330 331 static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { 332 .cmd_rcgr = 0x81bc, 333 .mnd_width = 0, 334 .hid_width = 5, 335 .parent_map = disp_cc_parent_map_0, 336 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 337 .clkr.hw.init = &(const struct clk_init_data) { 338 .name = "disp_cc_mdss_dptx0_aux_clk_src", 339 .parent_data = disp_cc_parent_data_0, 340 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 341 .flags = CLK_SET_RATE_PARENT, 342 .ops = &clk_rcg2_ops, 343 }, 344 }; 345 346 static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { 347 .cmd_rcgr = 0x8170, 348 .mnd_width = 0, 349 .hid_width = 5, 350 .parent_map = disp_cc_parent_map_7, 351 .clkr.hw.init = &(const struct clk_init_data) { 352 .name = "disp_cc_mdss_dptx0_link_clk_src", 353 .parent_data = disp_cc_parent_data_7, 354 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), 355 .flags = CLK_SET_RATE_PARENT, 356 .ops = &clk_byte2_ops, 357 }, 358 }; 359 360 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = { 361 .cmd_rcgr = 0x818c, 362 .mnd_width = 16, 363 .hid_width = 5, 364 .parent_map = disp_cc_parent_map_4, 365 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 366 .clkr.hw.init = &(const struct clk_init_data) { 367 .name = "disp_cc_mdss_dptx0_pixel0_clk_src", 368 .parent_data = disp_cc_parent_data_4, 369 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 370 .flags = CLK_SET_RATE_PARENT, 371 .ops = &clk_dp_ops, 372 }, 373 }; 374 375 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = { 376 .cmd_rcgr = 0x81a4, 377 .mnd_width = 16, 378 .hid_width = 5, 379 .parent_map = disp_cc_parent_map_4, 380 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 381 .clkr.hw.init = &(const struct clk_init_data) { 382 .name = "disp_cc_mdss_dptx0_pixel1_clk_src", 383 .parent_data = disp_cc_parent_data_4, 384 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 385 .flags = CLK_SET_RATE_PARENT, 386 .ops = &clk_dp_ops, 387 }, 388 }; 389 390 static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { 391 .cmd_rcgr = 0x8220, 392 .mnd_width = 0, 393 .hid_width = 5, 394 .parent_map = disp_cc_parent_map_0, 395 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 396 .clkr.hw.init = &(const struct clk_init_data) { 397 .name = "disp_cc_mdss_dptx1_aux_clk_src", 398 .parent_data = disp_cc_parent_data_0, 399 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 400 .flags = CLK_SET_RATE_PARENT, 401 .ops = &clk_dp_ops, 402 }, 403 }; 404 405 static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { 406 .cmd_rcgr = 0x8204, 407 .mnd_width = 0, 408 .hid_width = 5, 409 .parent_map = disp_cc_parent_map_3, 410 .clkr.hw.init = &(const struct clk_init_data) { 411 .name = "disp_cc_mdss_dptx1_link_clk_src", 412 .parent_data = disp_cc_parent_data_3, 413 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 414 .flags = CLK_SET_RATE_PARENT, 415 .ops = &clk_byte2_ops, 416 }, 417 }; 418 419 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = { 420 .cmd_rcgr = 0x81d4, 421 .mnd_width = 16, 422 .hid_width = 5, 423 .parent_map = disp_cc_parent_map_1, 424 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 425 .clkr.hw.init = &(const struct clk_init_data) { 426 .name = "disp_cc_mdss_dptx1_pixel0_clk_src", 427 .parent_data = disp_cc_parent_data_1, 428 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 429 .flags = CLK_SET_RATE_PARENT, 430 .ops = &clk_dp_ops, 431 }, 432 }; 433 434 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = { 435 .cmd_rcgr = 0x81ec, 436 .mnd_width = 16, 437 .hid_width = 5, 438 .parent_map = disp_cc_parent_map_1, 439 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 440 .clkr.hw.init = &(const struct clk_init_data) { 441 .name = "disp_cc_mdss_dptx1_pixel1_clk_src", 442 .parent_data = disp_cc_parent_data_1, 443 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 444 .flags = CLK_SET_RATE_PARENT, 445 .ops = &clk_dp_ops, 446 }, 447 }; 448 449 static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = { 450 .cmd_rcgr = 0x8284, 451 .mnd_width = 0, 452 .hid_width = 5, 453 .parent_map = disp_cc_parent_map_0, 454 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 455 .clkr.hw.init = &(const struct clk_init_data) { 456 .name = "disp_cc_mdss_dptx2_aux_clk_src", 457 .parent_data = disp_cc_parent_data_0, 458 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 459 .flags = CLK_SET_RATE_PARENT, 460 .ops = &clk_rcg2_ops, 461 }, 462 }; 463 464 static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { 465 .cmd_rcgr = 0x8238, 466 .mnd_width = 0, 467 .hid_width = 5, 468 .parent_map = disp_cc_parent_map_3, 469 .clkr.hw.init = &(const struct clk_init_data) { 470 .name = "disp_cc_mdss_dptx2_link_clk_src", 471 .parent_data = disp_cc_parent_data_3, 472 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 473 .flags = CLK_SET_RATE_PARENT, 474 .ops = &clk_byte2_ops, 475 }, 476 }; 477 478 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = { 479 .cmd_rcgr = 0x8254, 480 .mnd_width = 16, 481 .hid_width = 5, 482 .parent_map = disp_cc_parent_map_1, 483 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 484 .clkr.hw.init = &(const struct clk_init_data) { 485 .name = "disp_cc_mdss_dptx2_pixel0_clk_src", 486 .parent_data = disp_cc_parent_data_1, 487 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 488 .flags = CLK_SET_RATE_PARENT, 489 .ops = &clk_dp_ops, 490 }, 491 }; 492 493 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = { 494 .cmd_rcgr = 0x826c, 495 .mnd_width = 16, 496 .hid_width = 5, 497 .parent_map = disp_cc_parent_map_1, 498 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 499 .clkr.hw.init = &(const struct clk_init_data) { 500 .name = "disp_cc_mdss_dptx2_pixel1_clk_src", 501 .parent_data = disp_cc_parent_data_1, 502 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 503 .flags = CLK_SET_RATE_PARENT, 504 .ops = &clk_dp_ops, 505 }, 506 }; 507 508 static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = { 509 .cmd_rcgr = 0x82d0, 510 .mnd_width = 0, 511 .hid_width = 5, 512 .parent_map = disp_cc_parent_map_0, 513 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 514 .clkr.hw.init = &(const struct clk_init_data) { 515 .name = "disp_cc_mdss_dptx3_aux_clk_src", 516 .parent_data = disp_cc_parent_data_0, 517 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 518 .flags = CLK_SET_RATE_PARENT, 519 .ops = &clk_rcg2_ops, 520 }, 521 }; 522 523 static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { 524 .cmd_rcgr = 0x82b4, 525 .mnd_width = 0, 526 .hid_width = 5, 527 .parent_map = disp_cc_parent_map_3, 528 .clkr.hw.init = &(const struct clk_init_data) { 529 .name = "disp_cc_mdss_dptx3_link_clk_src", 530 .parent_data = disp_cc_parent_data_3, 531 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 532 .flags = CLK_SET_RATE_PARENT, 533 .ops = &clk_byte2_ops, 534 }, 535 }; 536 537 static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = { 538 .cmd_rcgr = 0x829c, 539 .mnd_width = 16, 540 .hid_width = 5, 541 .parent_map = disp_cc_parent_map_1, 542 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 543 .clkr.hw.init = &(const struct clk_init_data) { 544 .name = "disp_cc_mdss_dptx3_pixel0_clk_src", 545 .parent_data = disp_cc_parent_data_1, 546 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 547 .flags = CLK_SET_RATE_PARENT, 548 .ops = &clk_dp_ops, 549 }, 550 }; 551 552 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { 553 .cmd_rcgr = 0x8140, 554 .mnd_width = 0, 555 .hid_width = 5, 556 .parent_map = disp_cc_parent_map_5, 557 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 558 .clkr.hw.init = &(const struct clk_init_data) { 559 .name = "disp_cc_mdss_esc0_clk_src", 560 .parent_data = disp_cc_parent_data_5, 561 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 562 .flags = CLK_SET_RATE_PARENT, 563 .ops = &clk_rcg2_ops, 564 }, 565 }; 566 567 static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { 568 .cmd_rcgr = 0x8158, 569 .mnd_width = 0, 570 .hid_width = 5, 571 .parent_map = disp_cc_parent_map_5, 572 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 573 .clkr.hw.init = &(const struct clk_init_data) { 574 .name = "disp_cc_mdss_esc1_clk_src", 575 .parent_data = disp_cc_parent_data_5, 576 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 577 .flags = CLK_SET_RATE_PARENT, 578 .ops = &clk_rcg2_ops, 579 }, 580 }; 581 582 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { 583 F(19200000, P_BI_TCXO, 1, 0, 0), 584 F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 585 F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 586 F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 587 F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 588 F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 589 F(402000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 590 F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 591 { } 592 }; 593 594 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { 595 .cmd_rcgr = 0x80d8, 596 .mnd_width = 0, 597 .hid_width = 5, 598 .parent_map = disp_cc_parent_map_8, 599 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 600 .clkr.hw.init = &(const struct clk_init_data) { 601 .name = "disp_cc_mdss_mdp_clk_src", 602 .parent_data = disp_cc_parent_data_8, 603 .num_parents = ARRAY_SIZE(disp_cc_parent_data_8), 604 .flags = CLK_SET_RATE_PARENT, 605 .ops = &clk_rcg2_shared_ops, 606 }, 607 }; 608 609 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { 610 .cmd_rcgr = 0x80a8, 611 .mnd_width = 8, 612 .hid_width = 5, 613 .parent_map = disp_cc_parent_map_2, 614 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 615 .clkr.hw.init = &(const struct clk_init_data) { 616 .name = "disp_cc_mdss_pclk0_clk_src", 617 .parent_data = disp_cc_parent_data_2, 618 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 619 .flags = CLK_SET_RATE_PARENT, 620 .ops = &clk_pixel_ops, 621 }, 622 }; 623 624 static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { 625 .cmd_rcgr = 0x80c0, 626 .mnd_width = 8, 627 .hid_width = 5, 628 .parent_map = disp_cc_parent_map_2, 629 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 630 .clkr.hw.init = &(const struct clk_init_data) { 631 .name = "disp_cc_mdss_pclk1_clk_src", 632 .parent_data = disp_cc_parent_data_2, 633 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 634 .flags = CLK_SET_RATE_PARENT, 635 .ops = &clk_pixel_ops, 636 }, 637 }; 638 639 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { 640 .cmd_rcgr = 0x80f0, 641 .mnd_width = 0, 642 .hid_width = 5, 643 .parent_map = disp_cc_parent_map_0, 644 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 645 .clkr.hw.init = &(const struct clk_init_data) { 646 .name = "disp_cc_mdss_vsync_clk_src", 647 .parent_data = disp_cc_parent_data_0, 648 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 649 .flags = CLK_SET_RATE_PARENT, 650 .ops = &clk_rcg2_ops, 651 }, 652 }; 653 654 static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = { 655 F(32000, P_SLEEP_CLK, 1, 0, 0), 656 { } 657 }; 658 659 static struct clk_rcg2 disp_cc_sleep_clk_src = { 660 .cmd_rcgr = 0xe05c, 661 .mnd_width = 0, 662 .hid_width = 5, 663 .parent_map = disp_cc_parent_map_9, 664 .freq_tbl = ftbl_disp_cc_sleep_clk_src, 665 .clkr.hw.init = &(const struct clk_init_data) { 666 .name = "disp_cc_sleep_clk_src", 667 .parent_data = disp_cc_parent_data_9, 668 .num_parents = ARRAY_SIZE(disp_cc_parent_data_9), 669 .flags = CLK_SET_RATE_PARENT, 670 .ops = &clk_rcg2_ops, 671 }, 672 }; 673 674 static struct clk_rcg2 disp_cc_xo_clk_src = { 675 .cmd_rcgr = 0xe03c, 676 .mnd_width = 0, 677 .hid_width = 5, 678 .parent_map = disp_cc_parent_map_0, 679 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 680 .clkr.hw.init = &(const struct clk_init_data) { 681 .name = "disp_cc_xo_clk_src", 682 .parent_data = disp_cc_parent_data_0_ao, 683 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0_ao), 684 .flags = CLK_SET_RATE_PARENT, 685 .ops = &clk_rcg2_ops, 686 }, 687 }; 688 689 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { 690 .reg = 0x8120, 691 .shift = 0, 692 .width = 4, 693 .clkr.hw.init = &(const struct clk_init_data) { 694 .name = "disp_cc_mdss_byte0_div_clk_src", 695 .parent_hws = (const struct clk_hw*[]) { 696 &disp_cc_mdss_byte0_clk_src.clkr.hw, 697 }, 698 .num_parents = 1, 699 .ops = &clk_regmap_div_ops, 700 }, 701 }; 702 703 static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { 704 .reg = 0x813c, 705 .shift = 0, 706 .width = 4, 707 .clkr.hw.init = &(const struct clk_init_data) { 708 .name = "disp_cc_mdss_byte1_div_clk_src", 709 .parent_hws = (const struct clk_hw*[]) { 710 &disp_cc_mdss_byte1_clk_src.clkr.hw, 711 }, 712 .num_parents = 1, 713 .ops = &clk_regmap_div_ops, 714 }, 715 }; 716 717 static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = { 718 .reg = 0x8188, 719 .shift = 0, 720 .width = 4, 721 .clkr.hw.init = &(const struct clk_init_data) { 722 .name = "disp_cc_mdss_dptx0_link_div_clk_src", 723 .parent_hws = (const struct clk_hw*[]) { 724 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 725 }, 726 .num_parents = 1, 727 .flags = CLK_SET_RATE_PARENT, 728 .ops = &clk_regmap_div_ro_ops, 729 }, 730 }; 731 732 static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = { 733 .reg = 0x821c, 734 .shift = 0, 735 .width = 4, 736 .clkr.hw.init = &(const struct clk_init_data) { 737 .name = "disp_cc_mdss_dptx1_link_div_clk_src", 738 .parent_hws = (const struct clk_hw*[]) { 739 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 740 }, 741 .num_parents = 1, 742 .flags = CLK_SET_RATE_PARENT, 743 .ops = &clk_regmap_div_ro_ops, 744 }, 745 }; 746 747 static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = { 748 .reg = 0x8250, 749 .shift = 0, 750 .width = 4, 751 .clkr.hw.init = &(const struct clk_init_data) { 752 .name = "disp_cc_mdss_dptx2_link_div_clk_src", 753 .parent_hws = (const struct clk_hw*[]) { 754 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 755 }, 756 .num_parents = 1, 757 .flags = CLK_SET_RATE_PARENT, 758 .ops = &clk_regmap_div_ro_ops, 759 }, 760 }; 761 762 static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = { 763 .reg = 0x82cc, 764 .shift = 0, 765 .width = 4, 766 .clkr.hw.init = &(const struct clk_init_data) { 767 .name = "disp_cc_mdss_dptx3_link_div_clk_src", 768 .parent_hws = (const struct clk_hw*[]) { 769 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 770 }, 771 .num_parents = 1, 772 .flags = CLK_SET_RATE_PARENT, 773 .ops = &clk_regmap_div_ro_ops, 774 }, 775 }; 776 777 static struct clk_branch disp_cc_mdss_accu_clk = { 778 .halt_reg = 0xe058, 779 .halt_check = BRANCH_HALT_VOTED, 780 .clkr = { 781 .enable_reg = 0xe058, 782 .enable_mask = BIT(0), 783 .hw.init = &(const struct clk_init_data) { 784 .name = "disp_cc_mdss_accu_clk", 785 .parent_hws = (const struct clk_hw*[]) { 786 &disp_cc_xo_clk_src.clkr.hw, 787 }, 788 .num_parents = 1, 789 .flags = CLK_SET_RATE_PARENT, 790 .ops = &clk_branch2_ops, 791 }, 792 }, 793 }; 794 795 static struct clk_branch disp_cc_mdss_ahb1_clk = { 796 .halt_reg = 0xa020, 797 .halt_check = BRANCH_HALT, 798 .clkr = { 799 .enable_reg = 0xa020, 800 .enable_mask = BIT(0), 801 .hw.init = &(const struct clk_init_data) { 802 .name = "disp_cc_mdss_ahb1_clk", 803 .parent_hws = (const struct clk_hw*[]) { 804 &disp_cc_mdss_ahb_clk_src.clkr.hw, 805 }, 806 .num_parents = 1, 807 .flags = CLK_SET_RATE_PARENT, 808 .ops = &clk_branch2_ops, 809 }, 810 }, 811 }; 812 813 static struct clk_branch disp_cc_mdss_ahb_clk = { 814 .halt_reg = 0x80a4, 815 .halt_check = BRANCH_HALT, 816 .clkr = { 817 .enable_reg = 0x80a4, 818 .enable_mask = BIT(0), 819 .hw.init = &(const struct clk_init_data) { 820 .name = "disp_cc_mdss_ahb_clk", 821 .parent_hws = (const struct clk_hw*[]) { 822 &disp_cc_mdss_ahb_clk_src.clkr.hw, 823 }, 824 .num_parents = 1, 825 .flags = CLK_SET_RATE_PARENT, 826 .ops = &clk_branch2_ops, 827 }, 828 }, 829 }; 830 831 static struct clk_branch disp_cc_mdss_byte0_clk = { 832 .halt_reg = 0x8028, 833 .halt_check = BRANCH_HALT, 834 .clkr = { 835 .enable_reg = 0x8028, 836 .enable_mask = BIT(0), 837 .hw.init = &(const struct clk_init_data) { 838 .name = "disp_cc_mdss_byte0_clk", 839 .parent_hws = (const struct clk_hw*[]) { 840 &disp_cc_mdss_byte0_clk_src.clkr.hw, 841 }, 842 .num_parents = 1, 843 .flags = CLK_SET_RATE_PARENT, 844 .ops = &clk_branch2_ops, 845 }, 846 }, 847 }; 848 849 static struct clk_branch disp_cc_mdss_byte0_intf_clk = { 850 .halt_reg = 0x802c, 851 .halt_check = BRANCH_HALT, 852 .clkr = { 853 .enable_reg = 0x802c, 854 .enable_mask = BIT(0), 855 .hw.init = &(const struct clk_init_data) { 856 .name = "disp_cc_mdss_byte0_intf_clk", 857 .parent_hws = (const struct clk_hw*[]) { 858 &disp_cc_mdss_byte0_div_clk_src.clkr.hw, 859 }, 860 .num_parents = 1, 861 .flags = CLK_SET_RATE_PARENT, 862 .ops = &clk_branch2_ops, 863 }, 864 }, 865 }; 866 867 static struct clk_branch disp_cc_mdss_byte1_clk = { 868 .halt_reg = 0x8030, 869 .halt_check = BRANCH_HALT, 870 .clkr = { 871 .enable_reg = 0x8030, 872 .enable_mask = BIT(0), 873 .hw.init = &(const struct clk_init_data) { 874 .name = "disp_cc_mdss_byte1_clk", 875 .parent_hws = (const struct clk_hw*[]) { 876 &disp_cc_mdss_byte1_clk_src.clkr.hw, 877 }, 878 .num_parents = 1, 879 .flags = CLK_SET_RATE_PARENT, 880 .ops = &clk_branch2_ops, 881 }, 882 }, 883 }; 884 885 static struct clk_branch disp_cc_mdss_byte1_intf_clk = { 886 .halt_reg = 0x8034, 887 .halt_check = BRANCH_HALT, 888 .clkr = { 889 .enable_reg = 0x8034, 890 .enable_mask = BIT(0), 891 .hw.init = &(const struct clk_init_data) { 892 .name = "disp_cc_mdss_byte1_intf_clk", 893 .parent_hws = (const struct clk_hw*[]) { 894 &disp_cc_mdss_byte1_div_clk_src.clkr.hw, 895 }, 896 .num_parents = 1, 897 .flags = CLK_SET_RATE_PARENT, 898 .ops = &clk_branch2_ops, 899 }, 900 }, 901 }; 902 903 static struct clk_branch disp_cc_mdss_dptx0_aux_clk = { 904 .halt_reg = 0x8058, 905 .halt_check = BRANCH_HALT, 906 .clkr = { 907 .enable_reg = 0x8058, 908 .enable_mask = BIT(0), 909 .hw.init = &(const struct clk_init_data) { 910 .name = "disp_cc_mdss_dptx0_aux_clk", 911 .parent_hws = (const struct clk_hw*[]) { 912 &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, 913 }, 914 .num_parents = 1, 915 .flags = CLK_SET_RATE_PARENT, 916 .ops = &clk_branch2_ops, 917 }, 918 }, 919 }; 920 921 static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = { 922 .halt_reg = 0x804c, 923 .halt_check = BRANCH_HALT, 924 .clkr = { 925 .enable_reg = 0x804c, 926 .enable_mask = BIT(0), 927 .hw.init = &(const struct clk_init_data) { 928 .name = "disp_cc_mdss_dptx0_crypto_clk", 929 .parent_hws = (const struct clk_hw*[]) { 930 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 931 }, 932 .num_parents = 1, 933 .flags = CLK_SET_RATE_PARENT, 934 .ops = &clk_branch2_ops, 935 }, 936 }, 937 }; 938 939 static struct clk_branch disp_cc_mdss_dptx0_link_clk = { 940 .halt_reg = 0x8040, 941 .halt_check = BRANCH_HALT, 942 .clkr = { 943 .enable_reg = 0x8040, 944 .enable_mask = BIT(0), 945 .hw.init = &(const struct clk_init_data) { 946 .name = "disp_cc_mdss_dptx0_link_clk", 947 .parent_hws = (const struct clk_hw*[]) { 948 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 949 }, 950 .num_parents = 1, 951 .flags = CLK_SET_RATE_PARENT, 952 .ops = &clk_branch2_ops, 953 }, 954 }, 955 }; 956 957 static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = { 958 .halt_reg = 0x8048, 959 .halt_check = BRANCH_HALT, 960 .clkr = { 961 .enable_reg = 0x8048, 962 .enable_mask = BIT(0), 963 .hw.init = &(const struct clk_init_data) { 964 .name = "disp_cc_mdss_dptx0_link_intf_clk", 965 .parent_hws = (const struct clk_hw*[]) { 966 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 967 }, 968 .num_parents = 1, 969 .flags = CLK_SET_RATE_PARENT, 970 .ops = &clk_branch2_ops, 971 }, 972 }, 973 }; 974 975 static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = { 976 .halt_reg = 0x8050, 977 .halt_check = BRANCH_HALT, 978 .clkr = { 979 .enable_reg = 0x8050, 980 .enable_mask = BIT(0), 981 .hw.init = &(const struct clk_init_data) { 982 .name = "disp_cc_mdss_dptx0_pixel0_clk", 983 .parent_hws = (const struct clk_hw*[]) { 984 &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, 985 }, 986 .num_parents = 1, 987 .flags = CLK_SET_RATE_PARENT, 988 .ops = &clk_branch2_ops, 989 }, 990 }, 991 }; 992 993 static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = { 994 .halt_reg = 0x8054, 995 .halt_check = BRANCH_HALT, 996 .clkr = { 997 .enable_reg = 0x8054, 998 .enable_mask = BIT(0), 999 .hw.init = &(const struct clk_init_data) { 1000 .name = "disp_cc_mdss_dptx0_pixel1_clk", 1001 .parent_hws = (const struct clk_hw*[]) { 1002 &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, 1003 }, 1004 .num_parents = 1, 1005 .flags = CLK_SET_RATE_PARENT, 1006 .ops = &clk_branch2_ops, 1007 }, 1008 }, 1009 }; 1010 1011 static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = { 1012 .halt_reg = 0x8044, 1013 .halt_check = BRANCH_HALT, 1014 .clkr = { 1015 .enable_reg = 0x8044, 1016 .enable_mask = BIT(0), 1017 .hw.init = &(const struct clk_init_data) { 1018 .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk", 1019 .parent_hws = (const struct clk_hw*[]) { 1020 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1021 }, 1022 .num_parents = 1, 1023 .flags = CLK_SET_RATE_PARENT, 1024 .ops = &clk_branch2_ops, 1025 }, 1026 }, 1027 }; 1028 1029 static struct clk_branch disp_cc_mdss_dptx1_aux_clk = { 1030 .halt_reg = 0x8074, 1031 .halt_check = BRANCH_HALT, 1032 .clkr = { 1033 .enable_reg = 0x8074, 1034 .enable_mask = BIT(0), 1035 .hw.init = &(const struct clk_init_data) { 1036 .name = "disp_cc_mdss_dptx1_aux_clk", 1037 .parent_hws = (const struct clk_hw*[]) { 1038 &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, 1039 }, 1040 .num_parents = 1, 1041 .flags = CLK_SET_RATE_PARENT, 1042 .ops = &clk_branch2_ops, 1043 }, 1044 }, 1045 }; 1046 1047 static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = { 1048 .halt_reg = 0x8070, 1049 .halt_check = BRANCH_HALT, 1050 .clkr = { 1051 .enable_reg = 0x8070, 1052 .enable_mask = BIT(0), 1053 .hw.init = &(const struct clk_init_data) { 1054 .name = "disp_cc_mdss_dptx1_crypto_clk", 1055 .parent_hws = (const struct clk_hw*[]) { 1056 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 1057 }, 1058 .num_parents = 1, 1059 .flags = CLK_SET_RATE_PARENT, 1060 .ops = &clk_branch2_ops, 1061 }, 1062 }, 1063 }; 1064 1065 static struct clk_branch disp_cc_mdss_dptx1_link_clk = { 1066 .halt_reg = 0x8064, 1067 .halt_check = BRANCH_HALT, 1068 .clkr = { 1069 .enable_reg = 0x8064, 1070 .enable_mask = BIT(0), 1071 .hw.init = &(const struct clk_init_data) { 1072 .name = "disp_cc_mdss_dptx1_link_clk", 1073 .parent_hws = (const struct clk_hw*[]) { 1074 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 1075 }, 1076 .num_parents = 1, 1077 .flags = CLK_SET_RATE_PARENT, 1078 .ops = &clk_branch2_ops, 1079 }, 1080 }, 1081 }; 1082 1083 static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = { 1084 .halt_reg = 0x806c, 1085 .halt_check = BRANCH_HALT, 1086 .clkr = { 1087 .enable_reg = 0x806c, 1088 .enable_mask = BIT(0), 1089 .hw.init = &(const struct clk_init_data) { 1090 .name = "disp_cc_mdss_dptx1_link_intf_clk", 1091 .parent_hws = (const struct clk_hw*[]) { 1092 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1093 }, 1094 .num_parents = 1, 1095 .flags = CLK_SET_RATE_PARENT, 1096 .ops = &clk_branch2_ops, 1097 }, 1098 }, 1099 }; 1100 1101 static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = { 1102 .halt_reg = 0x805c, 1103 .halt_check = BRANCH_HALT, 1104 .clkr = { 1105 .enable_reg = 0x805c, 1106 .enable_mask = BIT(0), 1107 .hw.init = &(const struct clk_init_data) { 1108 .name = "disp_cc_mdss_dptx1_pixel0_clk", 1109 .parent_hws = (const struct clk_hw*[]) { 1110 &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, 1111 }, 1112 .num_parents = 1, 1113 .flags = CLK_SET_RATE_PARENT, 1114 .ops = &clk_branch2_ops, 1115 }, 1116 }, 1117 }; 1118 1119 static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = { 1120 .halt_reg = 0x8060, 1121 .halt_check = BRANCH_HALT, 1122 .clkr = { 1123 .enable_reg = 0x8060, 1124 .enable_mask = BIT(0), 1125 .hw.init = &(const struct clk_init_data) { 1126 .name = "disp_cc_mdss_dptx1_pixel1_clk", 1127 .parent_hws = (const struct clk_hw*[]) { 1128 &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, 1129 }, 1130 .num_parents = 1, 1131 .flags = CLK_SET_RATE_PARENT, 1132 .ops = &clk_branch2_ops, 1133 }, 1134 }, 1135 }; 1136 1137 static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = { 1138 .halt_reg = 0x8068, 1139 .halt_check = BRANCH_HALT, 1140 .clkr = { 1141 .enable_reg = 0x8068, 1142 .enable_mask = BIT(0), 1143 .hw.init = &(const struct clk_init_data) { 1144 .name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk", 1145 .parent_hws = (const struct clk_hw*[]) { 1146 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1147 }, 1148 .num_parents = 1, 1149 .flags = CLK_SET_RATE_PARENT, 1150 .ops = &clk_branch2_ops, 1151 }, 1152 }, 1153 }; 1154 1155 static struct clk_branch disp_cc_mdss_dptx2_aux_clk = { 1156 .halt_reg = 0x808c, 1157 .halt_check = BRANCH_HALT, 1158 .clkr = { 1159 .enable_reg = 0x808c, 1160 .enable_mask = BIT(0), 1161 .hw.init = &(const struct clk_init_data) { 1162 .name = "disp_cc_mdss_dptx2_aux_clk", 1163 .parent_hws = (const struct clk_hw*[]) { 1164 &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw, 1165 }, 1166 .num_parents = 1, 1167 .flags = CLK_SET_RATE_PARENT, 1168 .ops = &clk_branch2_ops, 1169 }, 1170 }, 1171 }; 1172 1173 static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = { 1174 .halt_reg = 0x8088, 1175 .halt_check = BRANCH_HALT, 1176 .clkr = { 1177 .enable_reg = 0x8088, 1178 .enable_mask = BIT(0), 1179 .hw.init = &(const struct clk_init_data) { 1180 .name = "disp_cc_mdss_dptx2_crypto_clk", 1181 .parent_hws = (const struct clk_hw*[]) { 1182 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 1183 }, 1184 .num_parents = 1, 1185 .flags = CLK_SET_RATE_PARENT, 1186 .ops = &clk_branch2_ops, 1187 }, 1188 }, 1189 }; 1190 1191 static struct clk_branch disp_cc_mdss_dptx2_link_clk = { 1192 .halt_reg = 0x8080, 1193 .halt_check = BRANCH_HALT, 1194 .clkr = { 1195 .enable_reg = 0x8080, 1196 .enable_mask = BIT(0), 1197 .hw.init = &(const struct clk_init_data) { 1198 .name = "disp_cc_mdss_dptx2_link_clk", 1199 .parent_hws = (const struct clk_hw*[]) { 1200 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 1201 }, 1202 .num_parents = 1, 1203 .flags = CLK_SET_RATE_PARENT, 1204 .ops = &clk_branch2_ops, 1205 }, 1206 }, 1207 }; 1208 1209 static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = { 1210 .halt_reg = 0x8084, 1211 .halt_check = BRANCH_HALT, 1212 .clkr = { 1213 .enable_reg = 0x8084, 1214 .enable_mask = BIT(0), 1215 .hw.init = &(const struct clk_init_data) { 1216 .name = "disp_cc_mdss_dptx2_link_intf_clk", 1217 .parent_hws = (const struct clk_hw*[]) { 1218 &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, 1219 }, 1220 .num_parents = 1, 1221 .flags = CLK_SET_RATE_PARENT, 1222 .ops = &clk_branch2_ops, 1223 }, 1224 }, 1225 }; 1226 1227 static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = { 1228 .halt_reg = 0x8078, 1229 .halt_check = BRANCH_HALT, 1230 .clkr = { 1231 .enable_reg = 0x8078, 1232 .enable_mask = BIT(0), 1233 .hw.init = &(const struct clk_init_data) { 1234 .name = "disp_cc_mdss_dptx2_pixel0_clk", 1235 .parent_hws = (const struct clk_hw*[]) { 1236 &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, 1237 }, 1238 .num_parents = 1, 1239 .flags = CLK_SET_RATE_PARENT, 1240 .ops = &clk_branch2_ops, 1241 }, 1242 }, 1243 }; 1244 1245 static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = { 1246 .halt_reg = 0x807c, 1247 .halt_check = BRANCH_HALT, 1248 .clkr = { 1249 .enable_reg = 0x807c, 1250 .enable_mask = BIT(0), 1251 .hw.init = &(const struct clk_init_data) { 1252 .name = "disp_cc_mdss_dptx2_pixel1_clk", 1253 .parent_hws = (const struct clk_hw*[]) { 1254 &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, 1255 }, 1256 .num_parents = 1, 1257 .flags = CLK_SET_RATE_PARENT, 1258 .ops = &clk_branch2_ops, 1259 }, 1260 }, 1261 }; 1262 1263 static struct clk_branch disp_cc_mdss_dptx3_aux_clk = { 1264 .halt_reg = 0x809c, 1265 .halt_check = BRANCH_HALT, 1266 .clkr = { 1267 .enable_reg = 0x809c, 1268 .enable_mask = BIT(0), 1269 .hw.init = &(const struct clk_init_data) { 1270 .name = "disp_cc_mdss_dptx3_aux_clk", 1271 .parent_hws = (const struct clk_hw*[]) { 1272 &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw, 1273 }, 1274 .num_parents = 1, 1275 .flags = CLK_SET_RATE_PARENT, 1276 .ops = &clk_branch2_ops, 1277 }, 1278 }, 1279 }; 1280 1281 static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = { 1282 .halt_reg = 0x80a0, 1283 .halt_check = BRANCH_HALT, 1284 .clkr = { 1285 .enable_reg = 0x80a0, 1286 .enable_mask = BIT(0), 1287 .hw.init = &(const struct clk_init_data) { 1288 .name = "disp_cc_mdss_dptx3_crypto_clk", 1289 .parent_hws = (const struct clk_hw*[]) { 1290 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 1291 }, 1292 .num_parents = 1, 1293 .flags = CLK_SET_RATE_PARENT, 1294 .ops = &clk_branch2_ops, 1295 }, 1296 }, 1297 }; 1298 1299 static struct clk_branch disp_cc_mdss_dptx3_link_clk = { 1300 .halt_reg = 0x8094, 1301 .halt_check = BRANCH_HALT, 1302 .clkr = { 1303 .enable_reg = 0x8094, 1304 .enable_mask = BIT(0), 1305 .hw.init = &(const struct clk_init_data) { 1306 .name = "disp_cc_mdss_dptx3_link_clk", 1307 .parent_hws = (const struct clk_hw*[]) { 1308 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 1309 }, 1310 .num_parents = 1, 1311 .flags = CLK_SET_RATE_PARENT, 1312 .ops = &clk_branch2_ops, 1313 }, 1314 }, 1315 }; 1316 1317 static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = { 1318 .halt_reg = 0x8098, 1319 .halt_check = BRANCH_HALT, 1320 .clkr = { 1321 .enable_reg = 0x8098, 1322 .enable_mask = BIT(0), 1323 .hw.init = &(const struct clk_init_data) { 1324 .name = "disp_cc_mdss_dptx3_link_intf_clk", 1325 .parent_hws = (const struct clk_hw*[]) { 1326 &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw, 1327 }, 1328 .num_parents = 1, 1329 .flags = CLK_SET_RATE_PARENT, 1330 .ops = &clk_branch2_ops, 1331 }, 1332 }, 1333 }; 1334 1335 static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = { 1336 .halt_reg = 0x8090, 1337 .halt_check = BRANCH_HALT, 1338 .clkr = { 1339 .enable_reg = 0x8090, 1340 .enable_mask = BIT(0), 1341 .hw.init = &(const struct clk_init_data) { 1342 .name = "disp_cc_mdss_dptx3_pixel0_clk", 1343 .parent_hws = (const struct clk_hw*[]) { 1344 &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, 1345 }, 1346 .num_parents = 1, 1347 .flags = CLK_SET_RATE_PARENT, 1348 .ops = &clk_branch2_ops, 1349 }, 1350 }, 1351 }; 1352 1353 static struct clk_branch disp_cc_mdss_esc0_clk = { 1354 .halt_reg = 0x8038, 1355 .halt_check = BRANCH_HALT, 1356 .clkr = { 1357 .enable_reg = 0x8038, 1358 .enable_mask = BIT(0), 1359 .hw.init = &(const struct clk_init_data) { 1360 .name = "disp_cc_mdss_esc0_clk", 1361 .parent_hws = (const struct clk_hw*[]) { 1362 &disp_cc_mdss_esc0_clk_src.clkr.hw, 1363 }, 1364 .num_parents = 1, 1365 .flags = CLK_SET_RATE_PARENT, 1366 .ops = &clk_branch2_ops, 1367 }, 1368 }, 1369 }; 1370 1371 static struct clk_branch disp_cc_mdss_esc1_clk = { 1372 .halt_reg = 0x803c, 1373 .halt_check = BRANCH_HALT, 1374 .clkr = { 1375 .enable_reg = 0x803c, 1376 .enable_mask = BIT(0), 1377 .hw.init = &(const struct clk_init_data) { 1378 .name = "disp_cc_mdss_esc1_clk", 1379 .parent_hws = (const struct clk_hw*[]) { 1380 &disp_cc_mdss_esc1_clk_src.clkr.hw, 1381 }, 1382 .num_parents = 1, 1383 .flags = CLK_SET_RATE_PARENT, 1384 .ops = &clk_branch2_ops, 1385 }, 1386 }, 1387 }; 1388 1389 static struct clk_branch disp_cc_mdss_mdp1_clk = { 1390 .halt_reg = 0xa004, 1391 .halt_check = BRANCH_HALT, 1392 .clkr = { 1393 .enable_reg = 0xa004, 1394 .enable_mask = BIT(0), 1395 .hw.init = &(const struct clk_init_data) { 1396 .name = "disp_cc_mdss_mdp1_clk", 1397 .parent_hws = (const struct clk_hw*[]) { 1398 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1399 }, 1400 .num_parents = 1, 1401 .flags = CLK_SET_RATE_PARENT, 1402 .ops = &clk_branch2_ops, 1403 }, 1404 }, 1405 }; 1406 1407 static struct clk_branch disp_cc_mdss_mdp_clk = { 1408 .halt_reg = 0x800c, 1409 .halt_check = BRANCH_HALT, 1410 .clkr = { 1411 .enable_reg = 0x800c, 1412 .enable_mask = BIT(0), 1413 .hw.init = &(const struct clk_init_data) { 1414 .name = "disp_cc_mdss_mdp_clk", 1415 .parent_hws = (const struct clk_hw*[]) { 1416 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1417 }, 1418 .num_parents = 1, 1419 .flags = CLK_SET_RATE_PARENT, 1420 .ops = &clk_branch2_ops, 1421 }, 1422 }, 1423 }; 1424 1425 static struct clk_branch disp_cc_mdss_mdp_lut1_clk = { 1426 .halt_reg = 0xa010, 1427 .halt_check = BRANCH_HALT, 1428 .clkr = { 1429 .enable_reg = 0xa010, 1430 .enable_mask = BIT(0), 1431 .hw.init = &(const struct clk_init_data) { 1432 .name = "disp_cc_mdss_mdp_lut1_clk", 1433 .parent_hws = (const struct clk_hw*[]) { 1434 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1435 }, 1436 .num_parents = 1, 1437 .flags = CLK_SET_RATE_PARENT, 1438 .ops = &clk_branch2_ops, 1439 }, 1440 }, 1441 }; 1442 1443 static struct clk_branch disp_cc_mdss_mdp_lut_clk = { 1444 .halt_reg = 0x8018, 1445 .halt_check = BRANCH_HALT_VOTED, 1446 .clkr = { 1447 .enable_reg = 0x8018, 1448 .enable_mask = BIT(0), 1449 .hw.init = &(const struct clk_init_data) { 1450 .name = "disp_cc_mdss_mdp_lut_clk", 1451 .parent_hws = (const struct clk_hw*[]) { 1452 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1453 }, 1454 .num_parents = 1, 1455 .flags = CLK_SET_RATE_PARENT, 1456 .ops = &clk_branch2_ops, 1457 }, 1458 }, 1459 }; 1460 1461 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { 1462 .halt_reg = 0xc004, 1463 .halt_check = BRANCH_HALT_VOTED, 1464 .clkr = { 1465 .enable_reg = 0xc004, 1466 .enable_mask = BIT(0), 1467 .hw.init = &(const struct clk_init_data) { 1468 .name = "disp_cc_mdss_non_gdsc_ahb_clk", 1469 .parent_hws = (const struct clk_hw*[]) { 1470 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1471 }, 1472 .num_parents = 1, 1473 .flags = CLK_SET_RATE_PARENT, 1474 .ops = &clk_branch2_ops, 1475 }, 1476 }, 1477 }; 1478 1479 static struct clk_branch disp_cc_mdss_pclk0_clk = { 1480 .halt_reg = 0x8004, 1481 .halt_check = BRANCH_HALT, 1482 .clkr = { 1483 .enable_reg = 0x8004, 1484 .enable_mask = BIT(0), 1485 .hw.init = &(const struct clk_init_data) { 1486 .name = "disp_cc_mdss_pclk0_clk", 1487 .parent_hws = (const struct clk_hw*[]) { 1488 &disp_cc_mdss_pclk0_clk_src.clkr.hw, 1489 }, 1490 .num_parents = 1, 1491 .flags = CLK_SET_RATE_PARENT, 1492 .ops = &clk_branch2_ops, 1493 }, 1494 }, 1495 }; 1496 1497 static struct clk_branch disp_cc_mdss_pclk1_clk = { 1498 .halt_reg = 0x8008, 1499 .halt_check = BRANCH_HALT, 1500 .clkr = { 1501 .enable_reg = 0x8008, 1502 .enable_mask = BIT(0), 1503 .hw.init = &(const struct clk_init_data) { 1504 .name = "disp_cc_mdss_pclk1_clk", 1505 .parent_hws = (const struct clk_hw*[]) { 1506 &disp_cc_mdss_pclk1_clk_src.clkr.hw, 1507 }, 1508 .num_parents = 1, 1509 .flags = CLK_SET_RATE_PARENT, 1510 .ops = &clk_branch2_ops, 1511 }, 1512 }, 1513 }; 1514 1515 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { 1516 .halt_reg = 0xc00c, 1517 .halt_check = BRANCH_HALT, 1518 .clkr = { 1519 .enable_reg = 0xc00c, 1520 .enable_mask = BIT(0), 1521 .hw.init = &(const struct clk_init_data) { 1522 .name = "disp_cc_mdss_rscc_ahb_clk", 1523 .parent_hws = (const struct clk_hw*[]) { 1524 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1525 }, 1526 .num_parents = 1, 1527 .flags = CLK_SET_RATE_PARENT, 1528 .ops = &clk_branch2_ops, 1529 }, 1530 }, 1531 }; 1532 1533 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { 1534 .halt_reg = 0xc008, 1535 .halt_check = BRANCH_HALT, 1536 .clkr = { 1537 .enable_reg = 0xc008, 1538 .enable_mask = BIT(0), 1539 .hw.init = &(const struct clk_init_data) { 1540 .name = "disp_cc_mdss_rscc_vsync_clk", 1541 .parent_hws = (const struct clk_hw*[]) { 1542 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1543 }, 1544 .num_parents = 1, 1545 .flags = CLK_SET_RATE_PARENT, 1546 .ops = &clk_branch2_ops, 1547 }, 1548 }, 1549 }; 1550 1551 static struct clk_branch disp_cc_mdss_vsync1_clk = { 1552 .halt_reg = 0xa01c, 1553 .halt_check = BRANCH_HALT, 1554 .clkr = { 1555 .enable_reg = 0xa01c, 1556 .enable_mask = BIT(0), 1557 .hw.init = &(const struct clk_init_data) { 1558 .name = "disp_cc_mdss_vsync1_clk", 1559 .parent_hws = (const struct clk_hw*[]) { 1560 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1561 }, 1562 .num_parents = 1, 1563 .flags = CLK_SET_RATE_PARENT, 1564 .ops = &clk_branch2_ops, 1565 }, 1566 }, 1567 }; 1568 1569 static struct clk_branch disp_cc_mdss_vsync_clk = { 1570 .halt_reg = 0x8024, 1571 .halt_check = BRANCH_HALT, 1572 .clkr = { 1573 .enable_reg = 0x8024, 1574 .enable_mask = BIT(0), 1575 .hw.init = &(const struct clk_init_data) { 1576 .name = "disp_cc_mdss_vsync_clk", 1577 .parent_hws = (const struct clk_hw*[]) { 1578 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1579 }, 1580 .num_parents = 1, 1581 .flags = CLK_SET_RATE_PARENT, 1582 .ops = &clk_branch2_ops, 1583 }, 1584 }, 1585 }; 1586 1587 static struct clk_branch disp_cc_sleep_clk = { 1588 .halt_reg = 0xe074, 1589 .halt_check = BRANCH_HALT, 1590 .clkr = { 1591 .enable_reg = 0xe074, 1592 .enable_mask = BIT(0), 1593 .hw.init = &(const struct clk_init_data) { 1594 .name = "disp_cc_sleep_clk", 1595 .parent_hws = (const struct clk_hw*[]) { 1596 &disp_cc_sleep_clk_src.clkr.hw, 1597 }, 1598 .num_parents = 1, 1599 .flags = CLK_SET_RATE_PARENT, 1600 .ops = &clk_branch2_ops, 1601 }, 1602 }, 1603 }; 1604 1605 static struct gdsc mdss_gdsc = { 1606 .gdscr = 0x9000, 1607 .pd = { 1608 .name = "mdss_gdsc", 1609 }, 1610 .pwrsts = PWRSTS_OFF_ON, 1611 .flags = HW_CTRL | RETAIN_FF_ENABLE, 1612 }; 1613 1614 static struct gdsc mdss_int2_gdsc = { 1615 .gdscr = 0xb000, 1616 .pd = { 1617 .name = "mdss_int2_gdsc", 1618 }, 1619 .pwrsts = PWRSTS_OFF_ON, 1620 .flags = HW_CTRL | RETAIN_FF_ENABLE, 1621 }; 1622 1623 static struct clk_regmap *disp_cc_sm8650_clocks[] = { 1624 [DISP_CC_MDSS_ACCU_CLK] = &disp_cc_mdss_accu_clk.clkr, 1625 [DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr, 1626 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, 1627 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, 1628 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, 1629 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, 1630 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, 1631 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, 1632 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr, 1633 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr, 1634 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr, 1635 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, 1636 [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr, 1637 [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr, 1638 [DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr, 1639 [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr, 1640 [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr, 1641 [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr, 1642 [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr, 1643 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr, 1644 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr, 1645 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr, 1646 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr, 1647 [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = 1648 &disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, 1649 [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr, 1650 [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr, 1651 [DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &disp_cc_mdss_dptx1_crypto_clk.clkr, 1652 [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr, 1653 [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr, 1654 [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr, 1655 [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr, 1656 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr, 1657 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr, 1658 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr, 1659 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr, 1660 [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] = 1661 &disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, 1662 [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr, 1663 [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr, 1664 [DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &disp_cc_mdss_dptx2_crypto_clk.clkr, 1665 [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr, 1666 [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr, 1667 [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr, 1668 [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr, 1669 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr, 1670 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr, 1671 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr, 1672 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr, 1673 [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr, 1674 [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr, 1675 [DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &disp_cc_mdss_dptx3_crypto_clk.clkr, 1676 [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr, 1677 [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr, 1678 [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr, 1679 [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr, 1680 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr, 1681 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr, 1682 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, 1683 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, 1684 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, 1685 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr, 1686 [DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr, 1687 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, 1688 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, 1689 [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr, 1690 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, 1691 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, 1692 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, 1693 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, 1694 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr, 1695 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr, 1696 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, 1697 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, 1698 [DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr, 1699 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, 1700 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, 1701 [DISP_CC_PLL0] = &disp_cc_pll0.clkr, 1702 [DISP_CC_PLL1] = &disp_cc_pll1.clkr, 1703 [DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr, 1704 [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr, 1705 [DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr, 1706 }; 1707 1708 static const struct qcom_reset_map disp_cc_sm8650_resets[] = { 1709 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 }, 1710 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 }, 1711 [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 }, 1712 }; 1713 1714 static struct gdsc *disp_cc_sm8650_gdscs[] = { 1715 [MDSS_GDSC] = &mdss_gdsc, 1716 [MDSS_INT2_GDSC] = &mdss_int2_gdsc, 1717 }; 1718 1719 static const struct regmap_config disp_cc_sm8650_regmap_config = { 1720 .reg_bits = 32, 1721 .reg_stride = 4, 1722 .val_bits = 32, 1723 .max_register = 0x11008, 1724 .fast_io = true, 1725 }; 1726 1727 static struct qcom_cc_desc disp_cc_sm8650_desc = { 1728 .config = &disp_cc_sm8650_regmap_config, 1729 .clks = disp_cc_sm8650_clocks, 1730 .num_clks = ARRAY_SIZE(disp_cc_sm8650_clocks), 1731 .resets = disp_cc_sm8650_resets, 1732 .num_resets = ARRAY_SIZE(disp_cc_sm8650_resets), 1733 .gdscs = disp_cc_sm8650_gdscs, 1734 .num_gdscs = ARRAY_SIZE(disp_cc_sm8650_gdscs), 1735 }; 1736 1737 static const struct of_device_id disp_cc_sm8650_match_table[] = { 1738 { .compatible = "qcom,sm8650-dispcc" }, 1739 { } 1740 }; 1741 MODULE_DEVICE_TABLE(of, disp_cc_sm8650_match_table); 1742 1743 static int disp_cc_sm8650_probe(struct platform_device *pdev) 1744 { 1745 struct regmap *regmap; 1746 int ret; 1747 1748 ret = devm_pm_runtime_enable(&pdev->dev); 1749 if (ret) 1750 return ret; 1751 1752 ret = pm_runtime_resume_and_get(&pdev->dev); 1753 if (ret) 1754 return ret; 1755 1756 regmap = qcom_cc_map(pdev, &disp_cc_sm8650_desc); 1757 if (IS_ERR(regmap)) { 1758 ret = PTR_ERR(regmap); 1759 goto err_put_rpm; 1760 } 1761 1762 clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); 1763 clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); 1764 1765 /* Enable clock gating for MDP clocks */ 1766 regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); 1767 1768 /* Keep some clocks always-on */ 1769 qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */ 1770 1771 ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8650_desc, regmap); 1772 if (ret) 1773 goto err_put_rpm; 1774 1775 pm_runtime_put(&pdev->dev); 1776 1777 return 0; 1778 1779 err_put_rpm: 1780 pm_runtime_put_sync(&pdev->dev); 1781 1782 return ret; 1783 } 1784 1785 static struct platform_driver disp_cc_sm8650_driver = { 1786 .probe = disp_cc_sm8650_probe, 1787 .driver = { 1788 .name = "disp_cc-sm8650", 1789 .of_match_table = disp_cc_sm8650_match_table, 1790 }, 1791 }; 1792 1793 module_platform_driver(disp_cc_sm8650_driver); 1794 1795 MODULE_DESCRIPTION("QTI DISPCC SM8650 Driver"); 1796 MODULE_LICENSE("GPL"); 1797