1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Ltd. 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/err.h> 9 #include <linux/kernel.h> 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 #include <linux/pm_runtime.h> 15 16 #include <dt-bindings/clock/qcom,sm8450-dispcc.h> 17 18 #include "common.h" 19 #include "clk-alpha-pll.h" 20 #include "clk-branch.h" 21 #include "clk-pll.h" 22 #include "clk-rcg.h" 23 #include "clk-regmap.h" 24 #include "clk-regmap-divider.h" 25 #include "clk-regmap-mux.h" 26 #include "reset.h" 27 #include "gdsc.h" 28 29 /* Need to match the order of clocks in DT binding */ 30 enum { 31 DT_BI_TCXO, 32 DT_BI_TCXO_AO, 33 DT_AHB_CLK, 34 DT_SLEEP_CLK, 35 36 DT_DSI0_PHY_PLL_OUT_BYTECLK, 37 DT_DSI0_PHY_PLL_OUT_DSICLK, 38 DT_DSI1_PHY_PLL_OUT_BYTECLK, 39 DT_DSI1_PHY_PLL_OUT_DSICLK, 40 41 DT_DP0_PHY_PLL_LINK_CLK, 42 DT_DP0_PHY_PLL_VCO_DIV_CLK, 43 DT_DP1_PHY_PLL_LINK_CLK, 44 DT_DP1_PHY_PLL_VCO_DIV_CLK, 45 DT_DP2_PHY_PLL_LINK_CLK, 46 DT_DP2_PHY_PLL_VCO_DIV_CLK, 47 DT_DP3_PHY_PLL_LINK_CLK, 48 DT_DP3_PHY_PLL_VCO_DIV_CLK, 49 }; 50 51 #define DISP_CC_MISC_CMD 0xF000 52 53 enum { 54 P_BI_TCXO, 55 P_DISP_CC_PLL0_OUT_MAIN, 56 P_DISP_CC_PLL1_OUT_EVEN, 57 P_DISP_CC_PLL1_OUT_MAIN, 58 P_DP0_PHY_PLL_LINK_CLK, 59 P_DP0_PHY_PLL_VCO_DIV_CLK, 60 P_DP1_PHY_PLL_LINK_CLK, 61 P_DP1_PHY_PLL_VCO_DIV_CLK, 62 P_DP2_PHY_PLL_LINK_CLK, 63 P_DP2_PHY_PLL_VCO_DIV_CLK, 64 P_DP3_PHY_PLL_LINK_CLK, 65 P_DP3_PHY_PLL_VCO_DIV_CLK, 66 P_DSI0_PHY_PLL_OUT_BYTECLK, 67 P_DSI0_PHY_PLL_OUT_DSICLK, 68 P_DSI1_PHY_PLL_OUT_BYTECLK, 69 P_DSI1_PHY_PLL_OUT_DSICLK, 70 P_SLEEP_CLK, 71 }; 72 73 static const struct pll_vco lucid_evo_vco[] = { 74 { 249600000, 2000000000, 0 }, 75 }; 76 77 static const struct alpha_pll_config disp_cc_pll0_config = { 78 .l = 0xD, 79 .alpha = 0x6492, 80 .config_ctl_val = 0x20485699, 81 .config_ctl_hi_val = 0x00182261, 82 .config_ctl_hi1_val = 0x32AA299C, 83 .user_ctl_val = 0x00000000, 84 .user_ctl_hi_val = 0x00000805, 85 }; 86 87 static const struct alpha_pll_config sm8475_disp_cc_pll0_config = { 88 .l = 0xd, 89 .alpha = 0x6492, 90 .config_ctl_val = 0x20485699, 91 .config_ctl_hi_val = 0x00182261, 92 .config_ctl_hi1_val = 0x82aa299c, 93 .test_ctl_val = 0x00000000, 94 .test_ctl_hi_val = 0x00000003, 95 .test_ctl_hi1_val = 0x00009000, 96 .test_ctl_hi2_val = 0x00000034, 97 .user_ctl_val = 0x00000000, 98 .user_ctl_hi_val = 0x00000005, 99 }; 100 101 static struct clk_init_data sm8475_disp_cc_pll0_init = { 102 .name = "disp_cc_pll0", 103 .parent_data = &(const struct clk_parent_data) { 104 .index = DT_BI_TCXO, 105 }, 106 .num_parents = 1, 107 .ops = &clk_alpha_pll_reset_lucid_ole_ops, 108 }; 109 110 static struct clk_alpha_pll disp_cc_pll0 = { 111 .offset = 0x0, 112 .vco_table = lucid_evo_vco, 113 .num_vco = ARRAY_SIZE(lucid_evo_vco), 114 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 115 .clkr = { 116 .hw.init = &(struct clk_init_data) { 117 .name = "disp_cc_pll0", 118 .parent_data = &(const struct clk_parent_data) { 119 .index = DT_BI_TCXO, 120 }, 121 .num_parents = 1, 122 .ops = &clk_alpha_pll_reset_lucid_evo_ops, 123 }, 124 }, 125 }; 126 127 static const struct alpha_pll_config disp_cc_pll1_config = { 128 .l = 0x1F, 129 .alpha = 0x4000, 130 .config_ctl_val = 0x20485699, 131 .config_ctl_hi_val = 0x00182261, 132 .config_ctl_hi1_val = 0x32AA299C, 133 .user_ctl_val = 0x00000000, 134 .user_ctl_hi_val = 0x00000805, 135 }; 136 137 static const struct alpha_pll_config sm8475_disp_cc_pll1_config = { 138 .l = 0x1f, 139 .alpha = 0x4000, 140 .config_ctl_val = 0x20485699, 141 .config_ctl_hi_val = 0x00182261, 142 .config_ctl_hi1_val = 0x82aa299c, 143 .test_ctl_val = 0x00000000, 144 .test_ctl_hi_val = 0x00000003, 145 .test_ctl_hi1_val = 0x00009000, 146 .test_ctl_hi2_val = 0x00000034, 147 .user_ctl_val = 0x00000000, 148 .user_ctl_hi_val = 0x00000005, 149 }; 150 151 static struct clk_init_data sm8475_disp_cc_pll1_init = { 152 .name = "disp_cc_pll1", 153 .parent_data = &(const struct clk_parent_data) { 154 .index = DT_BI_TCXO, 155 }, 156 .num_parents = 1, 157 .ops = &clk_alpha_pll_reset_lucid_ole_ops, 158 }; 159 160 static struct clk_alpha_pll disp_cc_pll1 = { 161 .offset = 0x1000, 162 .vco_table = lucid_evo_vco, 163 .num_vco = ARRAY_SIZE(lucid_evo_vco), 164 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 165 .clkr = { 166 .hw.init = &(struct clk_init_data) { 167 .name = "disp_cc_pll1", 168 .parent_data = &(const struct clk_parent_data) { 169 .index = DT_BI_TCXO, 170 }, 171 .num_parents = 1, 172 .ops = &clk_alpha_pll_reset_lucid_evo_ops, 173 }, 174 }, 175 }; 176 177 static const struct parent_map disp_cc_parent_map_0[] = { 178 { P_BI_TCXO, 0 }, 179 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 180 { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 }, 181 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, 182 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, 183 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, 184 }; 185 186 static const struct clk_parent_data disp_cc_parent_data_0[] = { 187 { .index = DT_BI_TCXO }, 188 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 189 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK }, 190 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 191 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 192 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 193 }; 194 195 static const struct parent_map disp_cc_parent_map_1[] = { 196 { P_BI_TCXO, 0 }, 197 }; 198 199 static const struct clk_parent_data disp_cc_parent_data_1[] = { 200 { .index = DT_BI_TCXO }, 201 }; 202 203 static const struct clk_parent_data disp_cc_parent_data_1_ao[] = { 204 { .index = DT_BI_TCXO_AO }, 205 }; 206 207 static const struct parent_map disp_cc_parent_map_2[] = { 208 { P_BI_TCXO, 0 }, 209 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 210 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 211 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, 212 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 213 }; 214 215 static const struct clk_parent_data disp_cc_parent_data_2[] = { 216 { .index = DT_BI_TCXO }, 217 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, 218 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 219 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, 220 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 221 }; 222 223 static const struct parent_map disp_cc_parent_map_3[] = { 224 { P_BI_TCXO, 0 }, 225 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 226 { P_DP1_PHY_PLL_LINK_CLK, 2 }, 227 { P_DP2_PHY_PLL_LINK_CLK, 3 }, 228 { P_DP3_PHY_PLL_LINK_CLK, 4 }, 229 }; 230 231 static const struct clk_parent_data disp_cc_parent_data_3[] = { 232 { .index = DT_BI_TCXO }, 233 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 234 { .index = DT_DP1_PHY_PLL_LINK_CLK }, 235 { .index = DT_DP2_PHY_PLL_LINK_CLK }, 236 { .index = DT_DP3_PHY_PLL_LINK_CLK }, 237 }; 238 239 static const struct parent_map disp_cc_parent_map_4[] = { 240 { P_BI_TCXO, 0 }, 241 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 242 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 243 }; 244 245 static const struct clk_parent_data disp_cc_parent_data_4[] = { 246 { .index = DT_BI_TCXO }, 247 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 248 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 249 }; 250 251 static const struct parent_map disp_cc_parent_map_5[] = { 252 { P_BI_TCXO, 0 }, 253 { P_DISP_CC_PLL0_OUT_MAIN, 1 }, 254 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 255 { P_DISP_CC_PLL1_OUT_EVEN, 6 }, 256 }; 257 258 static const struct clk_parent_data disp_cc_parent_data_5[] = { 259 { .index = DT_BI_TCXO }, 260 { .hw = &disp_cc_pll0.clkr.hw }, 261 { .hw = &disp_cc_pll1.clkr.hw }, 262 { .hw = &disp_cc_pll1.clkr.hw }, 263 }; 264 265 static const struct parent_map disp_cc_parent_map_6[] = { 266 { P_BI_TCXO, 0 }, 267 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 268 { P_DISP_CC_PLL1_OUT_EVEN, 6 }, 269 }; 270 271 static const struct clk_parent_data disp_cc_parent_data_6[] = { 272 { .index = DT_BI_TCXO }, 273 { .hw = &disp_cc_pll1.clkr.hw }, 274 { .hw = &disp_cc_pll1.clkr.hw }, 275 }; 276 277 static const struct parent_map disp_cc_parent_map_7[] = { 278 { P_SLEEP_CLK, 0 }, 279 }; 280 281 static const struct clk_parent_data disp_cc_parent_data_7[] = { 282 { .index = DT_SLEEP_CLK }, 283 }; 284 285 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { 286 F(19200000, P_BI_TCXO, 1, 0, 0), 287 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), 288 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), 289 { } 290 }; 291 292 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { 293 .cmd_rcgr = 0x8324, 294 .mnd_width = 0, 295 .hid_width = 5, 296 .parent_map = disp_cc_parent_map_6, 297 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 298 .clkr.hw.init = &(struct clk_init_data) { 299 .name = "disp_cc_mdss_ahb_clk_src", 300 .parent_data = disp_cc_parent_data_6, 301 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 302 .flags = CLK_SET_RATE_PARENT, 303 .ops = &clk_rcg2_shared_ops, 304 }, 305 }; 306 307 static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = { 308 F(19200000, P_BI_TCXO, 1, 0, 0), 309 { } 310 }; 311 312 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { 313 .cmd_rcgr = 0x8134, 314 .mnd_width = 0, 315 .hid_width = 5, 316 .parent_map = disp_cc_parent_map_2, 317 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 318 .clkr.hw.init = &(struct clk_init_data) { 319 .name = "disp_cc_mdss_byte0_clk_src", 320 .parent_data = disp_cc_parent_data_2, 321 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 322 .flags = CLK_SET_RATE_PARENT, 323 .ops = &clk_byte2_ops, 324 }, 325 }; 326 327 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { 328 .cmd_rcgr = 0x8150, 329 .mnd_width = 0, 330 .hid_width = 5, 331 .parent_map = disp_cc_parent_map_2, 332 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 333 .clkr.hw.init = &(struct clk_init_data) { 334 .name = "disp_cc_mdss_byte1_clk_src", 335 .parent_data = disp_cc_parent_data_2, 336 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 337 .flags = CLK_SET_RATE_PARENT, 338 .ops = &clk_byte2_ops, 339 }, 340 }; 341 342 static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { 343 .cmd_rcgr = 0x81ec, 344 .mnd_width = 0, 345 .hid_width = 5, 346 .parent_map = disp_cc_parent_map_1, 347 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 348 .clkr.hw.init = &(struct clk_init_data) { 349 .name = "disp_cc_mdss_dptx0_aux_clk_src", 350 .parent_data = disp_cc_parent_data_1, 351 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 352 .flags = CLK_SET_RATE_PARENT, 353 .ops = &clk_rcg2_ops, 354 }, 355 }; 356 357 static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { 358 .cmd_rcgr = 0x819c, 359 .mnd_width = 0, 360 .hid_width = 5, 361 .parent_map = disp_cc_parent_map_3, 362 .clkr.hw.init = &(struct clk_init_data) { 363 .name = "disp_cc_mdss_dptx0_link_clk_src", 364 .parent_data = disp_cc_parent_data_3, 365 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 366 .flags = CLK_SET_RATE_PARENT, 367 .ops = &clk_byte2_ops, 368 }, 369 }; 370 371 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = { 372 .cmd_rcgr = 0x81bc, 373 .mnd_width = 16, 374 .hid_width = 5, 375 .parent_map = disp_cc_parent_map_0, 376 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 377 .clkr.hw.init = &(struct clk_init_data) { 378 .name = "disp_cc_mdss_dptx0_pixel0_clk_src", 379 .parent_data = disp_cc_parent_data_0, 380 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 381 .flags = CLK_SET_RATE_PARENT, 382 .ops = &clk_dp_ops, 383 }, 384 }; 385 386 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = { 387 .cmd_rcgr = 0x81d4, 388 .mnd_width = 16, 389 .hid_width = 5, 390 .parent_map = disp_cc_parent_map_0, 391 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 392 .clkr.hw.init = &(struct clk_init_data) { 393 .name = "disp_cc_mdss_dptx0_pixel1_clk_src", 394 .parent_data = disp_cc_parent_data_0, 395 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 396 .flags = CLK_SET_RATE_PARENT, 397 .ops = &clk_dp_ops, 398 }, 399 }; 400 401 static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { 402 .cmd_rcgr = 0x8254, 403 .mnd_width = 0, 404 .hid_width = 5, 405 .parent_map = disp_cc_parent_map_1, 406 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 407 .clkr.hw.init = &(struct clk_init_data) { 408 .name = "disp_cc_mdss_dptx1_aux_clk_src", 409 .parent_data = disp_cc_parent_data_1, 410 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 411 .flags = CLK_SET_RATE_PARENT, 412 .ops = &clk_dp_ops, 413 }, 414 }; 415 416 static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { 417 .cmd_rcgr = 0x8234, 418 .mnd_width = 0, 419 .hid_width = 5, 420 .parent_map = disp_cc_parent_map_3, 421 .clkr.hw.init = &(struct clk_init_data) { 422 .name = "disp_cc_mdss_dptx1_link_clk_src", 423 .parent_data = disp_cc_parent_data_3, 424 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 425 .flags = CLK_SET_RATE_PARENT, 426 .ops = &clk_byte2_ops, 427 }, 428 }; 429 430 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = { 431 .cmd_rcgr = 0x8204, 432 .mnd_width = 16, 433 .hid_width = 5, 434 .parent_map = disp_cc_parent_map_0, 435 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 436 .clkr.hw.init = &(struct clk_init_data) { 437 .name = "disp_cc_mdss_dptx1_pixel0_clk_src", 438 .parent_data = disp_cc_parent_data_0, 439 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 440 .flags = CLK_SET_RATE_PARENT, 441 .ops = &clk_dp_ops, 442 }, 443 }; 444 445 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = { 446 .cmd_rcgr = 0x821c, 447 .mnd_width = 16, 448 .hid_width = 5, 449 .parent_map = disp_cc_parent_map_0, 450 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 451 .clkr.hw.init = &(struct clk_init_data) { 452 .name = "disp_cc_mdss_dptx1_pixel1_clk_src", 453 .parent_data = disp_cc_parent_data_0, 454 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 455 .flags = CLK_SET_RATE_PARENT, 456 .ops = &clk_dp_ops, 457 }, 458 }; 459 460 static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = { 461 .cmd_rcgr = 0x82bc, 462 .mnd_width = 0, 463 .hid_width = 5, 464 .parent_map = disp_cc_parent_map_1, 465 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 466 .clkr.hw.init = &(struct clk_init_data) { 467 .name = "disp_cc_mdss_dptx2_aux_clk_src", 468 .parent_data = disp_cc_parent_data_1, 469 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 470 .flags = CLK_SET_RATE_PARENT, 471 .ops = &clk_rcg2_ops, 472 }, 473 }; 474 475 static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { 476 .cmd_rcgr = 0x826c, 477 .mnd_width = 0, 478 .hid_width = 5, 479 .parent_map = disp_cc_parent_map_3, 480 .clkr.hw.init = &(struct clk_init_data) { 481 .name = "disp_cc_mdss_dptx2_link_clk_src", 482 .parent_data = disp_cc_parent_data_3, 483 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 484 .flags = CLK_SET_RATE_PARENT, 485 .ops = &clk_byte2_ops, 486 }, 487 }; 488 489 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = { 490 .cmd_rcgr = 0x828c, 491 .mnd_width = 16, 492 .hid_width = 5, 493 .parent_map = disp_cc_parent_map_0, 494 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 495 .clkr.hw.init = &(struct clk_init_data) { 496 .name = "disp_cc_mdss_dptx2_pixel0_clk_src", 497 .parent_data = disp_cc_parent_data_0, 498 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 499 .flags = CLK_SET_RATE_PARENT, 500 .ops = &clk_dp_ops, 501 }, 502 }; 503 504 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = { 505 .cmd_rcgr = 0x82a4, 506 .mnd_width = 16, 507 .hid_width = 5, 508 .parent_map = disp_cc_parent_map_0, 509 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 510 .clkr.hw.init = &(struct clk_init_data) { 511 .name = "disp_cc_mdss_dptx2_pixel1_clk_src", 512 .parent_data = disp_cc_parent_data_0, 513 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 514 .flags = CLK_SET_RATE_PARENT, 515 .ops = &clk_dp_ops, 516 }, 517 }; 518 519 static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = { 520 .cmd_rcgr = 0x8308, 521 .mnd_width = 0, 522 .hid_width = 5, 523 .parent_map = disp_cc_parent_map_1, 524 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 525 .clkr.hw.init = &(struct clk_init_data) { 526 .name = "disp_cc_mdss_dptx3_aux_clk_src", 527 .parent_data = disp_cc_parent_data_1, 528 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 529 .flags = CLK_SET_RATE_PARENT, 530 .ops = &clk_rcg2_ops, 531 }, 532 }; 533 534 static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { 535 .cmd_rcgr = 0x82ec, 536 .mnd_width = 0, 537 .hid_width = 5, 538 .parent_map = disp_cc_parent_map_3, 539 .clkr.hw.init = &(struct clk_init_data) { 540 .name = "disp_cc_mdss_dptx3_link_clk_src", 541 .parent_data = disp_cc_parent_data_3, 542 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 543 .flags = CLK_SET_RATE_PARENT, 544 .ops = &clk_byte2_ops, 545 }, 546 }; 547 548 static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = { 549 .cmd_rcgr = 0x82d4, 550 .mnd_width = 16, 551 .hid_width = 5, 552 .parent_map = disp_cc_parent_map_0, 553 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 554 .clkr.hw.init = &(struct clk_init_data) { 555 .name = "disp_cc_mdss_dptx3_pixel0_clk_src", 556 .parent_data = disp_cc_parent_data_0, 557 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 558 .flags = CLK_SET_RATE_PARENT, 559 .ops = &clk_dp_ops, 560 }, 561 }; 562 563 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { 564 .cmd_rcgr = 0x816c, 565 .mnd_width = 0, 566 .hid_width = 5, 567 .parent_map = disp_cc_parent_map_4, 568 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 569 .clkr.hw.init = &(struct clk_init_data) { 570 .name = "disp_cc_mdss_esc0_clk_src", 571 .parent_data = disp_cc_parent_data_4, 572 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 573 .flags = CLK_SET_RATE_PARENT, 574 .ops = &clk_rcg2_ops, 575 }, 576 }; 577 578 static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { 579 .cmd_rcgr = 0x8184, 580 .mnd_width = 0, 581 .hid_width = 5, 582 .parent_map = disp_cc_parent_map_4, 583 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 584 .clkr.hw.init = &(struct clk_init_data) { 585 .name = "disp_cc_mdss_esc1_clk_src", 586 .parent_data = disp_cc_parent_data_4, 587 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 588 .flags = CLK_SET_RATE_PARENT, 589 .ops = &clk_rcg2_ops, 590 }, 591 }; 592 593 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { 594 F(19200000, P_BI_TCXO, 1, 0, 0), 595 F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 596 F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 597 F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 598 F(172000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 599 F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 600 F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 601 F(375000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 602 F(500000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 603 { } 604 }; 605 606 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { 607 .cmd_rcgr = 0x80ec, 608 .mnd_width = 0, 609 .hid_width = 5, 610 .parent_map = disp_cc_parent_map_5, 611 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 612 .clkr.hw.init = &(struct clk_init_data) { 613 .name = "disp_cc_mdss_mdp_clk_src", 614 .parent_data = disp_cc_parent_data_5, 615 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 616 .flags = CLK_SET_RATE_PARENT, 617 .ops = &clk_rcg2_shared_ops, 618 }, 619 }; 620 621 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { 622 .cmd_rcgr = 0x80bc, 623 .mnd_width = 8, 624 .hid_width = 5, 625 .parent_map = disp_cc_parent_map_2, 626 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 627 .clkr.hw.init = &(struct clk_init_data) { 628 .name = "disp_cc_mdss_pclk0_clk_src", 629 .parent_data = disp_cc_parent_data_2, 630 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 631 .flags = CLK_SET_RATE_PARENT, 632 .ops = &clk_pixel_ops, 633 }, 634 }; 635 636 static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { 637 .cmd_rcgr = 0x80d4, 638 .mnd_width = 8, 639 .hid_width = 5, 640 .parent_map = disp_cc_parent_map_2, 641 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 642 .clkr.hw.init = &(struct clk_init_data) { 643 .name = "disp_cc_mdss_pclk1_clk_src", 644 .parent_data = disp_cc_parent_data_2, 645 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 646 .flags = CLK_SET_RATE_PARENT, 647 .ops = &clk_pixel_ops, 648 }, 649 }; 650 651 static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = { 652 F(19200000, P_BI_TCXO, 1, 0, 0), 653 F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0), 654 F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0), 655 F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0), 656 { } 657 }; 658 659 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { 660 .cmd_rcgr = 0x8104, 661 .mnd_width = 0, 662 .hid_width = 5, 663 .parent_map = disp_cc_parent_map_5, 664 .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, 665 .clkr.hw.init = &(struct clk_init_data) { 666 .name = "disp_cc_mdss_rot_clk_src", 667 .parent_data = disp_cc_parent_data_5, 668 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 669 .flags = CLK_SET_RATE_PARENT, 670 .ops = &clk_rcg2_shared_ops, 671 }, 672 }; 673 674 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { 675 .cmd_rcgr = 0x811c, 676 .mnd_width = 0, 677 .hid_width = 5, 678 .parent_map = disp_cc_parent_map_1, 679 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 680 .clkr.hw.init = &(struct clk_init_data) { 681 .name = "disp_cc_mdss_vsync_clk_src", 682 .parent_data = disp_cc_parent_data_1, 683 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 684 .flags = CLK_SET_RATE_PARENT, 685 .ops = &clk_rcg2_ops, 686 }, 687 }; 688 689 static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = { 690 F(32000, P_SLEEP_CLK, 1, 0, 0), 691 { } 692 }; 693 694 static struct clk_rcg2 disp_cc_sleep_clk_src = { 695 .cmd_rcgr = 0xe060, 696 .mnd_width = 0, 697 .hid_width = 5, 698 .parent_map = disp_cc_parent_map_7, 699 .freq_tbl = ftbl_disp_cc_sleep_clk_src, 700 .clkr.hw.init = &(struct clk_init_data) { 701 .name = "disp_cc_sleep_clk_src", 702 .parent_data = disp_cc_parent_data_7, 703 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), 704 .flags = CLK_SET_RATE_PARENT, 705 .ops = &clk_rcg2_ops, 706 }, 707 }; 708 709 static struct clk_rcg2 disp_cc_xo_clk_src = { 710 .cmd_rcgr = 0xe044, 711 .mnd_width = 0, 712 .hid_width = 5, 713 .parent_map = disp_cc_parent_map_1, 714 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 715 .clkr.hw.init = &(struct clk_init_data) { 716 .name = "disp_cc_xo_clk_src", 717 .parent_data = disp_cc_parent_data_1_ao, 718 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1_ao), 719 .flags = CLK_SET_RATE_PARENT, 720 .ops = &clk_rcg2_ops, 721 }, 722 }; 723 724 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { 725 .reg = 0x814c, 726 .shift = 0, 727 .width = 4, 728 .clkr.hw.init = &(struct clk_init_data) { 729 .name = "disp_cc_mdss_byte0_div_clk_src", 730 .parent_hws = (const struct clk_hw*[]) { 731 &disp_cc_mdss_byte0_clk_src.clkr.hw, 732 }, 733 .num_parents = 1, 734 .ops = &clk_regmap_div_ops, 735 }, 736 }; 737 738 static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { 739 .reg = 0x8168, 740 .shift = 0, 741 .width = 4, 742 .clkr.hw.init = &(struct clk_init_data) { 743 .name = "disp_cc_mdss_byte1_div_clk_src", 744 .parent_hws = (const struct clk_hw*[]) { 745 &disp_cc_mdss_byte1_clk_src.clkr.hw, 746 }, 747 .num_parents = 1, 748 .ops = &clk_regmap_div_ops, 749 }, 750 }; 751 752 static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = { 753 .reg = 0x81b4, 754 .shift = 0, 755 .width = 4, 756 .clkr.hw.init = &(struct clk_init_data) { 757 .name = "disp_cc_mdss_dptx0_link_div_clk_src", 758 .parent_hws = (const struct clk_hw*[]) { 759 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 760 }, 761 .num_parents = 1, 762 .flags = CLK_SET_RATE_PARENT, 763 .ops = &clk_regmap_div_ro_ops, 764 }, 765 }; 766 767 static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = { 768 .reg = 0x824c, 769 .shift = 0, 770 .width = 4, 771 .clkr.hw.init = &(struct clk_init_data) { 772 .name = "disp_cc_mdss_dptx1_link_div_clk_src", 773 .parent_hws = (const struct clk_hw*[]) { 774 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 775 }, 776 .num_parents = 1, 777 .flags = CLK_SET_RATE_PARENT, 778 .ops = &clk_regmap_div_ro_ops, 779 }, 780 }; 781 782 static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = { 783 .reg = 0x8284, 784 .shift = 0, 785 .width = 4, 786 .clkr.hw.init = &(struct clk_init_data) { 787 .name = "disp_cc_mdss_dptx2_link_div_clk_src", 788 .parent_hws = (const struct clk_hw*[]) { 789 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 790 }, 791 .num_parents = 1, 792 .flags = CLK_SET_RATE_PARENT, 793 .ops = &clk_regmap_div_ro_ops, 794 }, 795 }; 796 797 static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = { 798 .reg = 0x8304, 799 .shift = 0, 800 .width = 4, 801 .clkr.hw.init = &(struct clk_init_data) { 802 .name = "disp_cc_mdss_dptx3_link_div_clk_src", 803 .parent_hws = (const struct clk_hw*[]) { 804 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 805 }, 806 .num_parents = 1, 807 .flags = CLK_SET_RATE_PARENT, 808 .ops = &clk_regmap_div_ro_ops, 809 }, 810 }; 811 812 static struct clk_branch disp_cc_mdss_ahb1_clk = { 813 .halt_reg = 0xa020, 814 .halt_check = BRANCH_HALT, 815 .clkr = { 816 .enable_reg = 0xa020, 817 .enable_mask = BIT(0), 818 .hw.init = &(struct clk_init_data) { 819 .name = "disp_cc_mdss_ahb1_clk", 820 .parent_hws = (const struct clk_hw*[]) { 821 &disp_cc_mdss_ahb_clk_src.clkr.hw, 822 }, 823 .num_parents = 1, 824 .flags = CLK_SET_RATE_PARENT, 825 .ops = &clk_branch2_ops, 826 }, 827 }, 828 }; 829 830 static struct clk_branch disp_cc_mdss_ahb_clk = { 831 .halt_reg = 0x80a4, 832 .halt_check = BRANCH_HALT, 833 .clkr = { 834 .enable_reg = 0x80a4, 835 .enable_mask = BIT(0), 836 .hw.init = &(struct clk_init_data) { 837 .name = "disp_cc_mdss_ahb_clk", 838 .parent_hws = (const struct clk_hw*[]) { 839 &disp_cc_mdss_ahb_clk_src.clkr.hw, 840 }, 841 .num_parents = 1, 842 .flags = CLK_SET_RATE_PARENT, 843 .ops = &clk_branch2_ops, 844 }, 845 }, 846 }; 847 848 static struct clk_branch disp_cc_mdss_byte0_clk = { 849 .halt_reg = 0x8028, 850 .halt_check = BRANCH_HALT, 851 .clkr = { 852 .enable_reg = 0x8028, 853 .enable_mask = BIT(0), 854 .hw.init = &(struct clk_init_data) { 855 .name = "disp_cc_mdss_byte0_clk", 856 .parent_hws = (const struct clk_hw*[]) { 857 &disp_cc_mdss_byte0_clk_src.clkr.hw, 858 }, 859 .num_parents = 1, 860 .flags = CLK_SET_RATE_PARENT, 861 .ops = &clk_branch2_ops, 862 }, 863 }, 864 }; 865 866 static struct clk_branch disp_cc_mdss_byte0_intf_clk = { 867 .halt_reg = 0x802c, 868 .halt_check = BRANCH_HALT, 869 .clkr = { 870 .enable_reg = 0x802c, 871 .enable_mask = BIT(0), 872 .hw.init = &(struct clk_init_data) { 873 .name = "disp_cc_mdss_byte0_intf_clk", 874 .parent_hws = (const struct clk_hw*[]) { 875 &disp_cc_mdss_byte0_div_clk_src.clkr.hw, 876 }, 877 .num_parents = 1, 878 .flags = CLK_SET_RATE_PARENT, 879 .ops = &clk_branch2_ops, 880 }, 881 }, 882 }; 883 884 static struct clk_branch disp_cc_mdss_byte1_clk = { 885 .halt_reg = 0x8030, 886 .halt_check = BRANCH_HALT, 887 .clkr = { 888 .enable_reg = 0x8030, 889 .enable_mask = BIT(0), 890 .hw.init = &(struct clk_init_data) { 891 .name = "disp_cc_mdss_byte1_clk", 892 .parent_hws = (const struct clk_hw*[]) { 893 &disp_cc_mdss_byte1_clk_src.clkr.hw, 894 }, 895 .num_parents = 1, 896 .flags = CLK_SET_RATE_PARENT, 897 .ops = &clk_branch2_ops, 898 }, 899 }, 900 }; 901 902 static struct clk_branch disp_cc_mdss_byte1_intf_clk = { 903 .halt_reg = 0x8034, 904 .halt_check = BRANCH_HALT, 905 .clkr = { 906 .enable_reg = 0x8034, 907 .enable_mask = BIT(0), 908 .hw.init = &(struct clk_init_data) { 909 .name = "disp_cc_mdss_byte1_intf_clk", 910 .parent_hws = (const struct clk_hw*[]) { 911 &disp_cc_mdss_byte1_div_clk_src.clkr.hw, 912 }, 913 .num_parents = 1, 914 .flags = CLK_SET_RATE_PARENT, 915 .ops = &clk_branch2_ops, 916 }, 917 }, 918 }; 919 920 static struct clk_branch disp_cc_mdss_dptx0_aux_clk = { 921 .halt_reg = 0x8058, 922 .halt_check = BRANCH_HALT, 923 .clkr = { 924 .enable_reg = 0x8058, 925 .enable_mask = BIT(0), 926 .hw.init = &(struct clk_init_data) { 927 .name = "disp_cc_mdss_dptx0_aux_clk", 928 .parent_hws = (const struct clk_hw*[]) { 929 &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, 930 }, 931 .num_parents = 1, 932 .flags = CLK_SET_RATE_PARENT, 933 .ops = &clk_branch2_ops, 934 }, 935 }, 936 }; 937 938 static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = { 939 .halt_reg = 0x804c, 940 .halt_check = BRANCH_HALT, 941 .clkr = { 942 .enable_reg = 0x804c, 943 .enable_mask = BIT(0), 944 .hw.init = &(struct clk_init_data) { 945 .name = "disp_cc_mdss_dptx0_crypto_clk", 946 .parent_hws = (const struct clk_hw*[]) { 947 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 948 }, 949 .num_parents = 1, 950 .flags = CLK_SET_RATE_PARENT, 951 .ops = &clk_branch2_ops, 952 }, 953 }, 954 }; 955 956 static struct clk_branch disp_cc_mdss_dptx0_link_clk = { 957 .halt_reg = 0x8040, 958 .halt_check = BRANCH_HALT, 959 .clkr = { 960 .enable_reg = 0x8040, 961 .enable_mask = BIT(0), 962 .hw.init = &(struct clk_init_data) { 963 .name = "disp_cc_mdss_dptx0_link_clk", 964 .parent_hws = (const struct clk_hw*[]) { 965 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 966 }, 967 .num_parents = 1, 968 .flags = CLK_SET_RATE_PARENT, 969 .ops = &clk_branch2_ops, 970 }, 971 }, 972 }; 973 974 static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = { 975 .halt_reg = 0x8048, 976 .halt_check = BRANCH_HALT, 977 .clkr = { 978 .enable_reg = 0x8048, 979 .enable_mask = BIT(0), 980 .hw.init = &(struct clk_init_data) { 981 .name = "disp_cc_mdss_dptx0_link_intf_clk", 982 .parent_hws = (const struct clk_hw*[]) { 983 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 984 }, 985 .num_parents = 1, 986 .flags = CLK_SET_RATE_PARENT, 987 .ops = &clk_branch2_ops, 988 }, 989 }, 990 }; 991 992 static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = { 993 .halt_reg = 0x8050, 994 .halt_check = BRANCH_HALT, 995 .clkr = { 996 .enable_reg = 0x8050, 997 .enable_mask = BIT(0), 998 .hw.init = &(struct clk_init_data) { 999 .name = "disp_cc_mdss_dptx0_pixel0_clk", 1000 .parent_hws = (const struct clk_hw*[]) { 1001 &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, 1002 }, 1003 .num_parents = 1, 1004 .flags = CLK_SET_RATE_PARENT, 1005 .ops = &clk_branch2_ops, 1006 }, 1007 }, 1008 }; 1009 1010 static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = { 1011 .halt_reg = 0x8054, 1012 .halt_check = BRANCH_HALT, 1013 .clkr = { 1014 .enable_reg = 0x8054, 1015 .enable_mask = BIT(0), 1016 .hw.init = &(struct clk_init_data) { 1017 .name = "disp_cc_mdss_dptx0_pixel1_clk", 1018 .parent_hws = (const struct clk_hw*[]) { 1019 &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, 1020 }, 1021 .num_parents = 1, 1022 .flags = CLK_SET_RATE_PARENT, 1023 .ops = &clk_branch2_ops, 1024 }, 1025 }, 1026 }; 1027 1028 static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = { 1029 .halt_reg = 0x8044, 1030 .halt_check = BRANCH_HALT, 1031 .clkr = { 1032 .enable_reg = 0x8044, 1033 .enable_mask = BIT(0), 1034 .hw.init = &(struct clk_init_data) { 1035 .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk", 1036 .parent_hws = (const struct clk_hw*[]) { 1037 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1038 }, 1039 .num_parents = 1, 1040 .flags = CLK_SET_RATE_PARENT, 1041 .ops = &clk_branch2_ops, 1042 }, 1043 }, 1044 }; 1045 1046 static struct clk_branch disp_cc_mdss_dptx1_aux_clk = { 1047 .halt_reg = 0x8074, 1048 .halt_check = BRANCH_HALT, 1049 .clkr = { 1050 .enable_reg = 0x8074, 1051 .enable_mask = BIT(0), 1052 .hw.init = &(struct clk_init_data) { 1053 .name = "disp_cc_mdss_dptx1_aux_clk", 1054 .parent_hws = (const struct clk_hw*[]) { 1055 &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, 1056 }, 1057 .num_parents = 1, 1058 .flags = CLK_SET_RATE_PARENT, 1059 .ops = &clk_branch2_ops, 1060 }, 1061 }, 1062 }; 1063 1064 static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = { 1065 .halt_reg = 0x8070, 1066 .halt_check = BRANCH_HALT, 1067 .clkr = { 1068 .enable_reg = 0x8070, 1069 .enable_mask = BIT(0), 1070 .hw.init = &(struct clk_init_data) { 1071 .name = "disp_cc_mdss_dptx1_crypto_clk", 1072 .parent_hws = (const struct clk_hw*[]) { 1073 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 1074 }, 1075 .num_parents = 1, 1076 .flags = CLK_SET_RATE_PARENT, 1077 .ops = &clk_branch2_ops, 1078 }, 1079 }, 1080 }; 1081 1082 static struct clk_branch disp_cc_mdss_dptx1_link_clk = { 1083 .halt_reg = 0x8064, 1084 .halt_check = BRANCH_HALT, 1085 .clkr = { 1086 .enable_reg = 0x8064, 1087 .enable_mask = BIT(0), 1088 .hw.init = &(struct clk_init_data) { 1089 .name = "disp_cc_mdss_dptx1_link_clk", 1090 .parent_hws = (const struct clk_hw*[]) { 1091 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 1092 }, 1093 .num_parents = 1, 1094 .flags = CLK_SET_RATE_PARENT, 1095 .ops = &clk_branch2_ops, 1096 }, 1097 }, 1098 }; 1099 1100 static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = { 1101 .halt_reg = 0x806c, 1102 .halt_check = BRANCH_HALT, 1103 .clkr = { 1104 .enable_reg = 0x806c, 1105 .enable_mask = BIT(0), 1106 .hw.init = &(struct clk_init_data) { 1107 .name = "disp_cc_mdss_dptx1_link_intf_clk", 1108 .parent_hws = (const struct clk_hw*[]) { 1109 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1110 }, 1111 .num_parents = 1, 1112 .flags = CLK_SET_RATE_PARENT, 1113 .ops = &clk_branch2_ops, 1114 }, 1115 }, 1116 }; 1117 1118 static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = { 1119 .halt_reg = 0x805c, 1120 .halt_check = BRANCH_HALT, 1121 .clkr = { 1122 .enable_reg = 0x805c, 1123 .enable_mask = BIT(0), 1124 .hw.init = &(struct clk_init_data) { 1125 .name = "disp_cc_mdss_dptx1_pixel0_clk", 1126 .parent_hws = (const struct clk_hw*[]) { 1127 &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, 1128 }, 1129 .num_parents = 1, 1130 .flags = CLK_SET_RATE_PARENT, 1131 .ops = &clk_branch2_ops, 1132 }, 1133 }, 1134 }; 1135 1136 static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = { 1137 .halt_reg = 0x8060, 1138 .halt_check = BRANCH_HALT, 1139 .clkr = { 1140 .enable_reg = 0x8060, 1141 .enable_mask = BIT(0), 1142 .hw.init = &(struct clk_init_data) { 1143 .name = "disp_cc_mdss_dptx1_pixel1_clk", 1144 .parent_hws = (const struct clk_hw*[]) { 1145 &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, 1146 }, 1147 .num_parents = 1, 1148 .flags = CLK_SET_RATE_PARENT, 1149 .ops = &clk_branch2_ops, 1150 }, 1151 }, 1152 }; 1153 1154 static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = { 1155 .halt_reg = 0x8068, 1156 .halt_check = BRANCH_HALT, 1157 .clkr = { 1158 .enable_reg = 0x8068, 1159 .enable_mask = BIT(0), 1160 .hw.init = &(struct clk_init_data) { 1161 .name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk", 1162 .parent_hws = (const struct clk_hw*[]) { 1163 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1164 }, 1165 .num_parents = 1, 1166 .flags = CLK_SET_RATE_PARENT, 1167 .ops = &clk_branch2_ops, 1168 }, 1169 }, 1170 }; 1171 1172 static struct clk_branch disp_cc_mdss_dptx2_aux_clk = { 1173 .halt_reg = 0x808c, 1174 .halt_check = BRANCH_HALT, 1175 .clkr = { 1176 .enable_reg = 0x808c, 1177 .enable_mask = BIT(0), 1178 .hw.init = &(struct clk_init_data) { 1179 .name = "disp_cc_mdss_dptx2_aux_clk", 1180 .parent_hws = (const struct clk_hw*[]) { 1181 &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw, 1182 }, 1183 .num_parents = 1, 1184 .flags = CLK_SET_RATE_PARENT, 1185 .ops = &clk_branch2_ops, 1186 }, 1187 }, 1188 }; 1189 1190 static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = { 1191 .halt_reg = 0x8088, 1192 .halt_check = BRANCH_HALT, 1193 .clkr = { 1194 .enable_reg = 0x8088, 1195 .enable_mask = BIT(0), 1196 .hw.init = &(struct clk_init_data) { 1197 .name = "disp_cc_mdss_dptx2_crypto_clk", 1198 .parent_hws = (const struct clk_hw*[]) { 1199 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 1200 }, 1201 .num_parents = 1, 1202 .flags = CLK_SET_RATE_PARENT, 1203 .ops = &clk_branch2_ops, 1204 }, 1205 }, 1206 }; 1207 1208 static struct clk_branch disp_cc_mdss_dptx2_link_clk = { 1209 .halt_reg = 0x8080, 1210 .halt_check = BRANCH_HALT, 1211 .clkr = { 1212 .enable_reg = 0x8080, 1213 .enable_mask = BIT(0), 1214 .hw.init = &(struct clk_init_data) { 1215 .name = "disp_cc_mdss_dptx2_link_clk", 1216 .parent_hws = (const struct clk_hw*[]) { 1217 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 1218 }, 1219 .num_parents = 1, 1220 .flags = CLK_SET_RATE_PARENT, 1221 .ops = &clk_branch2_ops, 1222 }, 1223 }, 1224 }; 1225 1226 static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = { 1227 .halt_reg = 0x8084, 1228 .halt_check = BRANCH_HALT, 1229 .clkr = { 1230 .enable_reg = 0x8084, 1231 .enable_mask = BIT(0), 1232 .hw.init = &(struct clk_init_data) { 1233 .name = "disp_cc_mdss_dptx2_link_intf_clk", 1234 .parent_hws = (const struct clk_hw*[]) { 1235 &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, 1236 }, 1237 .num_parents = 1, 1238 .flags = CLK_SET_RATE_PARENT, 1239 .ops = &clk_branch2_ops, 1240 }, 1241 }, 1242 }; 1243 1244 static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = { 1245 .halt_reg = 0x8078, 1246 .halt_check = BRANCH_HALT, 1247 .clkr = { 1248 .enable_reg = 0x8078, 1249 .enable_mask = BIT(0), 1250 .hw.init = &(struct clk_init_data) { 1251 .name = "disp_cc_mdss_dptx2_pixel0_clk", 1252 .parent_hws = (const struct clk_hw*[]) { 1253 &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, 1254 }, 1255 .num_parents = 1, 1256 .flags = CLK_SET_RATE_PARENT, 1257 .ops = &clk_branch2_ops, 1258 }, 1259 }, 1260 }; 1261 1262 static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = { 1263 .halt_reg = 0x807c, 1264 .halt_check = BRANCH_HALT, 1265 .clkr = { 1266 .enable_reg = 0x807c, 1267 .enable_mask = BIT(0), 1268 .hw.init = &(struct clk_init_data) { 1269 .name = "disp_cc_mdss_dptx2_pixel1_clk", 1270 .parent_hws = (const struct clk_hw*[]) { 1271 &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, 1272 }, 1273 .num_parents = 1, 1274 .flags = CLK_SET_RATE_PARENT, 1275 .ops = &clk_branch2_ops, 1276 }, 1277 }, 1278 }; 1279 1280 static struct clk_branch disp_cc_mdss_dptx3_aux_clk = { 1281 .halt_reg = 0x809c, 1282 .halt_check = BRANCH_HALT, 1283 .clkr = { 1284 .enable_reg = 0x809c, 1285 .enable_mask = BIT(0), 1286 .hw.init = &(struct clk_init_data) { 1287 .name = "disp_cc_mdss_dptx3_aux_clk", 1288 .parent_hws = (const struct clk_hw*[]) { 1289 &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw, 1290 }, 1291 .num_parents = 1, 1292 .flags = CLK_SET_RATE_PARENT, 1293 .ops = &clk_branch2_ops, 1294 }, 1295 }, 1296 }; 1297 1298 static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = { 1299 .halt_reg = 0x80a0, 1300 .halt_check = BRANCH_HALT, 1301 .clkr = { 1302 .enable_reg = 0x80a0, 1303 .enable_mask = BIT(0), 1304 .hw.init = &(struct clk_init_data) { 1305 .name = "disp_cc_mdss_dptx3_crypto_clk", 1306 .parent_hws = (const struct clk_hw*[]) { 1307 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 1308 }, 1309 .num_parents = 1, 1310 .flags = CLK_SET_RATE_PARENT, 1311 .ops = &clk_branch2_ops, 1312 }, 1313 }, 1314 }; 1315 1316 static struct clk_branch disp_cc_mdss_dptx3_link_clk = { 1317 .halt_reg = 0x8094, 1318 .halt_check = BRANCH_HALT, 1319 .clkr = { 1320 .enable_reg = 0x8094, 1321 .enable_mask = BIT(0), 1322 .hw.init = &(struct clk_init_data) { 1323 .name = "disp_cc_mdss_dptx3_link_clk", 1324 .parent_hws = (const struct clk_hw*[]) { 1325 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 1326 }, 1327 .num_parents = 1, 1328 .flags = CLK_SET_RATE_PARENT, 1329 .ops = &clk_branch2_ops, 1330 }, 1331 }, 1332 }; 1333 1334 static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = { 1335 .halt_reg = 0x8098, 1336 .halt_check = BRANCH_HALT, 1337 .clkr = { 1338 .enable_reg = 0x8098, 1339 .enable_mask = BIT(0), 1340 .hw.init = &(struct clk_init_data) { 1341 .name = "disp_cc_mdss_dptx3_link_intf_clk", 1342 .parent_hws = (const struct clk_hw*[]) { 1343 &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw, 1344 }, 1345 .num_parents = 1, 1346 .flags = CLK_SET_RATE_PARENT, 1347 .ops = &clk_branch2_ops, 1348 }, 1349 }, 1350 }; 1351 1352 static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = { 1353 .halt_reg = 0x8090, 1354 .halt_check = BRANCH_HALT, 1355 .clkr = { 1356 .enable_reg = 0x8090, 1357 .enable_mask = BIT(0), 1358 .hw.init = &(struct clk_init_data) { 1359 .name = "disp_cc_mdss_dptx3_pixel0_clk", 1360 .parent_hws = (const struct clk_hw*[]) { 1361 &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, 1362 }, 1363 .num_parents = 1, 1364 .flags = CLK_SET_RATE_PARENT, 1365 .ops = &clk_branch2_ops, 1366 }, 1367 }, 1368 }; 1369 1370 static struct clk_branch disp_cc_mdss_esc0_clk = { 1371 .halt_reg = 0x8038, 1372 .halt_check = BRANCH_HALT, 1373 .clkr = { 1374 .enable_reg = 0x8038, 1375 .enable_mask = BIT(0), 1376 .hw.init = &(struct clk_init_data) { 1377 .name = "disp_cc_mdss_esc0_clk", 1378 .parent_hws = (const struct clk_hw*[]) { 1379 &disp_cc_mdss_esc0_clk_src.clkr.hw, 1380 }, 1381 .num_parents = 1, 1382 .flags = CLK_SET_RATE_PARENT, 1383 .ops = &clk_branch2_ops, 1384 }, 1385 }, 1386 }; 1387 1388 static struct clk_branch disp_cc_mdss_esc1_clk = { 1389 .halt_reg = 0x803c, 1390 .halt_check = BRANCH_HALT, 1391 .clkr = { 1392 .enable_reg = 0x803c, 1393 .enable_mask = BIT(0), 1394 .hw.init = &(struct clk_init_data) { 1395 .name = "disp_cc_mdss_esc1_clk", 1396 .parent_hws = (const struct clk_hw*[]) { 1397 &disp_cc_mdss_esc1_clk_src.clkr.hw, 1398 }, 1399 .num_parents = 1, 1400 .flags = CLK_SET_RATE_PARENT, 1401 .ops = &clk_branch2_ops, 1402 }, 1403 }, 1404 }; 1405 1406 static struct clk_branch disp_cc_mdss_mdp1_clk = { 1407 .halt_reg = 0xa004, 1408 .halt_check = BRANCH_HALT, 1409 .clkr = { 1410 .enable_reg = 0xa004, 1411 .enable_mask = BIT(0), 1412 .hw.init = &(struct clk_init_data) { 1413 .name = "disp_cc_mdss_mdp1_clk", 1414 .parent_hws = (const struct clk_hw*[]) { 1415 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1416 }, 1417 .num_parents = 1, 1418 .flags = CLK_SET_RATE_PARENT, 1419 .ops = &clk_branch2_ops, 1420 }, 1421 }, 1422 }; 1423 1424 static struct clk_branch disp_cc_mdss_mdp_clk = { 1425 .halt_reg = 0x800c, 1426 .halt_check = BRANCH_HALT, 1427 .clkr = { 1428 .enable_reg = 0x800c, 1429 .enable_mask = BIT(0), 1430 .hw.init = &(struct clk_init_data) { 1431 .name = "disp_cc_mdss_mdp_clk", 1432 .parent_hws = (const struct clk_hw*[]) { 1433 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1434 }, 1435 .num_parents = 1, 1436 .flags = CLK_SET_RATE_PARENT, 1437 .ops = &clk_branch2_ops, 1438 }, 1439 }, 1440 }; 1441 1442 static struct clk_branch disp_cc_mdss_mdp_lut1_clk = { 1443 .halt_reg = 0xa014, 1444 .halt_check = BRANCH_HALT, 1445 .clkr = { 1446 .enable_reg = 0xa014, 1447 .enable_mask = BIT(0), 1448 .hw.init = &(struct clk_init_data) { 1449 .name = "disp_cc_mdss_mdp_lut1_clk", 1450 .parent_hws = (const struct clk_hw*[]) { 1451 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1452 }, 1453 .num_parents = 1, 1454 .flags = CLK_SET_RATE_PARENT, 1455 .ops = &clk_branch2_ops, 1456 }, 1457 }, 1458 }; 1459 1460 static struct clk_branch disp_cc_mdss_mdp_lut_clk = { 1461 .halt_reg = 0x801c, 1462 .halt_check = BRANCH_HALT_VOTED, 1463 .clkr = { 1464 .enable_reg = 0x801c, 1465 .enable_mask = BIT(0), 1466 .hw.init = &(struct clk_init_data) { 1467 .name = "disp_cc_mdss_mdp_lut_clk", 1468 .parent_hws = (const struct clk_hw*[]) { 1469 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1470 }, 1471 .num_parents = 1, 1472 .flags = CLK_SET_RATE_PARENT, 1473 .ops = &clk_branch2_ops, 1474 }, 1475 }, 1476 }; 1477 1478 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { 1479 .halt_reg = 0xc004, 1480 .halt_check = BRANCH_HALT_VOTED, 1481 .clkr = { 1482 .enable_reg = 0xc004, 1483 .enable_mask = BIT(0), 1484 .hw.init = &(struct clk_init_data) { 1485 .name = "disp_cc_mdss_non_gdsc_ahb_clk", 1486 .parent_hws = (const struct clk_hw*[]) { 1487 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1488 }, 1489 .num_parents = 1, 1490 .flags = CLK_SET_RATE_PARENT, 1491 .ops = &clk_branch2_ops, 1492 }, 1493 }, 1494 }; 1495 1496 static struct clk_branch disp_cc_mdss_pclk0_clk = { 1497 .halt_reg = 0x8004, 1498 .halt_check = BRANCH_HALT, 1499 .clkr = { 1500 .enable_reg = 0x8004, 1501 .enable_mask = BIT(0), 1502 .hw.init = &(struct clk_init_data) { 1503 .name = "disp_cc_mdss_pclk0_clk", 1504 .parent_hws = (const struct clk_hw*[]) { 1505 &disp_cc_mdss_pclk0_clk_src.clkr.hw, 1506 }, 1507 .num_parents = 1, 1508 .flags = CLK_SET_RATE_PARENT, 1509 .ops = &clk_branch2_ops, 1510 }, 1511 }, 1512 }; 1513 1514 static struct clk_branch disp_cc_mdss_pclk1_clk = { 1515 .halt_reg = 0x8008, 1516 .halt_check = BRANCH_HALT, 1517 .clkr = { 1518 .enable_reg = 0x8008, 1519 .enable_mask = BIT(0), 1520 .hw.init = &(struct clk_init_data) { 1521 .name = "disp_cc_mdss_pclk1_clk", 1522 .parent_hws = (const struct clk_hw*[]) { 1523 &disp_cc_mdss_pclk1_clk_src.clkr.hw, 1524 }, 1525 .num_parents = 1, 1526 .flags = CLK_SET_RATE_PARENT, 1527 .ops = &clk_branch2_ops, 1528 }, 1529 }, 1530 }; 1531 1532 static struct clk_branch disp_cc_mdss_rot1_clk = { 1533 .halt_reg = 0xa00c, 1534 .halt_check = BRANCH_HALT, 1535 .clkr = { 1536 .enable_reg = 0xa00c, 1537 .enable_mask = BIT(0), 1538 .hw.init = &(struct clk_init_data) { 1539 .name = "disp_cc_mdss_rot1_clk", 1540 .parent_hws = (const struct clk_hw*[]) { 1541 &disp_cc_mdss_rot_clk_src.clkr.hw, 1542 }, 1543 .num_parents = 1, 1544 .flags = CLK_SET_RATE_PARENT, 1545 .ops = &clk_branch2_ops, 1546 }, 1547 }, 1548 }; 1549 1550 static struct clk_branch disp_cc_mdss_rot_clk = { 1551 .halt_reg = 0x8014, 1552 .halt_check = BRANCH_HALT, 1553 .clkr = { 1554 .enable_reg = 0x8014, 1555 .enable_mask = BIT(0), 1556 .hw.init = &(struct clk_init_data) { 1557 .name = "disp_cc_mdss_rot_clk", 1558 .parent_hws = (const struct clk_hw*[]) { 1559 &disp_cc_mdss_rot_clk_src.clkr.hw, 1560 }, 1561 .num_parents = 1, 1562 .flags = CLK_SET_RATE_PARENT, 1563 .ops = &clk_branch2_ops, 1564 }, 1565 }, 1566 }; 1567 1568 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { 1569 .halt_reg = 0xc00c, 1570 .halt_check = BRANCH_HALT, 1571 .clkr = { 1572 .enable_reg = 0xc00c, 1573 .enable_mask = BIT(0), 1574 .hw.init = &(struct clk_init_data) { 1575 .name = "disp_cc_mdss_rscc_ahb_clk", 1576 .parent_hws = (const struct clk_hw*[]) { 1577 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1578 }, 1579 .num_parents = 1, 1580 .flags = CLK_SET_RATE_PARENT, 1581 .ops = &clk_branch2_ops, 1582 }, 1583 }, 1584 }; 1585 1586 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { 1587 .halt_reg = 0xc008, 1588 .halt_check = BRANCH_HALT, 1589 .clkr = { 1590 .enable_reg = 0xc008, 1591 .enable_mask = BIT(0), 1592 .hw.init = &(struct clk_init_data) { 1593 .name = "disp_cc_mdss_rscc_vsync_clk", 1594 .parent_hws = (const struct clk_hw*[]) { 1595 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1596 }, 1597 .num_parents = 1, 1598 .flags = CLK_SET_RATE_PARENT, 1599 .ops = &clk_branch2_ops, 1600 }, 1601 }, 1602 }; 1603 1604 static struct clk_branch disp_cc_mdss_vsync1_clk = { 1605 .halt_reg = 0xa01c, 1606 .halt_check = BRANCH_HALT, 1607 .clkr = { 1608 .enable_reg = 0xa01c, 1609 .enable_mask = BIT(0), 1610 .hw.init = &(struct clk_init_data) { 1611 .name = "disp_cc_mdss_vsync1_clk", 1612 .parent_hws = (const struct clk_hw*[]) { 1613 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1614 }, 1615 .num_parents = 1, 1616 .flags = CLK_SET_RATE_PARENT, 1617 .ops = &clk_branch2_ops, 1618 }, 1619 }, 1620 }; 1621 1622 static struct clk_branch disp_cc_mdss_vsync_clk = { 1623 .halt_reg = 0x8024, 1624 .halt_check = BRANCH_HALT, 1625 .clkr = { 1626 .enable_reg = 0x8024, 1627 .enable_mask = BIT(0), 1628 .hw.init = &(struct clk_init_data) { 1629 .name = "disp_cc_mdss_vsync_clk", 1630 .parent_hws = (const struct clk_hw*[]) { 1631 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1632 }, 1633 .num_parents = 1, 1634 .flags = CLK_SET_RATE_PARENT, 1635 .ops = &clk_branch2_ops, 1636 }, 1637 }, 1638 }; 1639 1640 static struct clk_branch disp_cc_sleep_clk = { 1641 .halt_reg = 0xe078, 1642 .halt_check = BRANCH_HALT, 1643 .clkr = { 1644 .enable_reg = 0xe078, 1645 .enable_mask = BIT(0), 1646 .hw.init = &(struct clk_init_data) { 1647 .name = "disp_cc_sleep_clk", 1648 .parent_hws = (const struct clk_hw*[]) { 1649 &disp_cc_sleep_clk_src.clkr.hw, 1650 }, 1651 .num_parents = 1, 1652 .flags = CLK_SET_RATE_PARENT, 1653 .ops = &clk_branch2_ops, 1654 }, 1655 }, 1656 }; 1657 1658 static struct gdsc mdss_gdsc = { 1659 .gdscr = 0x9000, 1660 .pd = { 1661 .name = "mdss_gdsc", 1662 }, 1663 .pwrsts = PWRSTS_OFF_ON, 1664 .flags = HW_CTRL | RETAIN_FF_ENABLE, 1665 }; 1666 1667 static struct gdsc mdss_int2_gdsc = { 1668 .gdscr = 0xb000, 1669 .pd = { 1670 .name = "mdss_int2_gdsc", 1671 }, 1672 .pwrsts = PWRSTS_OFF_ON, 1673 .flags = HW_CTRL | RETAIN_FF_ENABLE, 1674 }; 1675 1676 static struct clk_regmap *disp_cc_sm8450_clocks[] = { 1677 [DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr, 1678 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, 1679 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, 1680 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, 1681 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, 1682 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, 1683 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, 1684 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr, 1685 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr, 1686 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr, 1687 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, 1688 [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr, 1689 [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr, 1690 [DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr, 1691 [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr, 1692 [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr, 1693 [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr, 1694 [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr, 1695 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr, 1696 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr, 1697 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr, 1698 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr, 1699 [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = 1700 &disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, 1701 [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr, 1702 [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr, 1703 [DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &disp_cc_mdss_dptx1_crypto_clk.clkr, 1704 [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr, 1705 [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr, 1706 [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr, 1707 [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr, 1708 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr, 1709 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr, 1710 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr, 1711 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr, 1712 [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] = 1713 &disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, 1714 [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr, 1715 [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr, 1716 [DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &disp_cc_mdss_dptx2_crypto_clk.clkr, 1717 [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr, 1718 [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr, 1719 [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr, 1720 [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr, 1721 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr, 1722 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr, 1723 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr, 1724 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr, 1725 [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr, 1726 [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr, 1727 [DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &disp_cc_mdss_dptx3_crypto_clk.clkr, 1728 [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr, 1729 [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr, 1730 [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr, 1731 [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr, 1732 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr, 1733 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr, 1734 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, 1735 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, 1736 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, 1737 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr, 1738 [DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr, 1739 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, 1740 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, 1741 [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr, 1742 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, 1743 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, 1744 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, 1745 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, 1746 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr, 1747 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr, 1748 [DISP_CC_MDSS_ROT1_CLK] = &disp_cc_mdss_rot1_clk.clkr, 1749 [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr, 1750 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr, 1751 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, 1752 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, 1753 [DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr, 1754 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, 1755 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, 1756 [DISP_CC_PLL0] = &disp_cc_pll0.clkr, 1757 [DISP_CC_PLL1] = &disp_cc_pll1.clkr, 1758 [DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr, 1759 [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr, 1760 [DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr, 1761 }; 1762 1763 static const struct qcom_reset_map disp_cc_sm8450_resets[] = { 1764 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 }, 1765 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 }, 1766 [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 }, 1767 }; 1768 1769 static struct gdsc *disp_cc_sm8450_gdscs[] = { 1770 [MDSS_GDSC] = &mdss_gdsc, 1771 [MDSS_INT2_GDSC] = &mdss_int2_gdsc, 1772 }; 1773 1774 static const struct regmap_config disp_cc_sm8450_regmap_config = { 1775 .reg_bits = 32, 1776 .reg_stride = 4, 1777 .val_bits = 32, 1778 .max_register = 0x11008, 1779 .fast_io = true, 1780 }; 1781 1782 static const struct qcom_cc_desc disp_cc_sm8450_desc = { 1783 .config = &disp_cc_sm8450_regmap_config, 1784 .clks = disp_cc_sm8450_clocks, 1785 .num_clks = ARRAY_SIZE(disp_cc_sm8450_clocks), 1786 .resets = disp_cc_sm8450_resets, 1787 .num_resets = ARRAY_SIZE(disp_cc_sm8450_resets), 1788 .gdscs = disp_cc_sm8450_gdscs, 1789 .num_gdscs = ARRAY_SIZE(disp_cc_sm8450_gdscs), 1790 }; 1791 1792 static const struct of_device_id disp_cc_sm8450_match_table[] = { 1793 { .compatible = "qcom,sm8450-dispcc" }, 1794 { .compatible = "qcom,sm8475-dispcc" }, 1795 { } 1796 }; 1797 MODULE_DEVICE_TABLE(of, disp_cc_sm8450_match_table); 1798 1799 static int disp_cc_sm8450_probe(struct platform_device *pdev) 1800 { 1801 struct regmap *regmap; 1802 int ret; 1803 1804 ret = devm_pm_runtime_enable(&pdev->dev); 1805 if (ret) 1806 return ret; 1807 1808 ret = pm_runtime_resume_and_get(&pdev->dev); 1809 if (ret) 1810 return ret; 1811 1812 regmap = qcom_cc_map(pdev, &disp_cc_sm8450_desc); 1813 if (IS_ERR(regmap)) { 1814 ret = PTR_ERR(regmap); 1815 goto err_put_rpm; 1816 } 1817 1818 if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-dispcc")) { 1819 /* Update DISPCC PLL0 */ 1820 disp_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; 1821 disp_cc_pll0.clkr.hw.init = &sm8475_disp_cc_pll0_init; 1822 1823 /* Update DISPCC PLL1 */ 1824 disp_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; 1825 disp_cc_pll1.clkr.hw.init = &sm8475_disp_cc_pll1_init; 1826 1827 clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &sm8475_disp_cc_pll0_config); 1828 clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &sm8475_disp_cc_pll1_config); 1829 } else { 1830 clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); 1831 clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); 1832 } 1833 1834 /* Enable clock gating for MDP clocks */ 1835 regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); 1836 1837 /* Keep some clocks always-on */ 1838 qcom_branch_set_clk_en(regmap, 0xe05c); /* DISP_CC_XO_CLK */ 1839 1840 ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8450_desc, regmap); 1841 if (ret) 1842 goto err_put_rpm; 1843 1844 pm_runtime_put(&pdev->dev); 1845 1846 return 0; 1847 1848 err_put_rpm: 1849 pm_runtime_put_sync(&pdev->dev); 1850 1851 return ret; 1852 } 1853 1854 static struct platform_driver disp_cc_sm8450_driver = { 1855 .probe = disp_cc_sm8450_probe, 1856 .driver = { 1857 .name = "disp_cc-sm8450", 1858 .of_match_table = disp_cc_sm8450_match_table, 1859 }, 1860 }; 1861 1862 module_platform_driver(disp_cc_sm8450_driver); 1863 1864 MODULE_DESCRIPTION("QTI DISPCC SM8450 / SM8475 Driver"); 1865 MODULE_LICENSE("GPL"); 1866