1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Ltd. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/err.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/platform_device.h> 14 #include <linux/regmap.h> 15 #include <linux/pm_runtime.h> 16 17 #include <dt-bindings/clock/qcom,sm8450-dispcc.h> 18 19 #include "common.h" 20 #include "clk-alpha-pll.h" 21 #include "clk-branch.h" 22 #include "clk-pll.h" 23 #include "clk-rcg.h" 24 #include "clk-regmap.h" 25 #include "clk-regmap-divider.h" 26 #include "clk-regmap-mux.h" 27 #include "reset.h" 28 #include "gdsc.h" 29 30 /* Need to match the order of clocks in DT binding */ 31 enum { 32 DT_BI_TCXO, 33 DT_BI_TCXO_AO, 34 DT_AHB_CLK, 35 DT_SLEEP_CLK, 36 37 DT_DSI0_PHY_PLL_OUT_BYTECLK, 38 DT_DSI0_PHY_PLL_OUT_DSICLK, 39 DT_DSI1_PHY_PLL_OUT_BYTECLK, 40 DT_DSI1_PHY_PLL_OUT_DSICLK, 41 42 DT_DP0_PHY_PLL_LINK_CLK, 43 DT_DP0_PHY_PLL_VCO_DIV_CLK, 44 DT_DP1_PHY_PLL_LINK_CLK, 45 DT_DP1_PHY_PLL_VCO_DIV_CLK, 46 DT_DP2_PHY_PLL_LINK_CLK, 47 DT_DP2_PHY_PLL_VCO_DIV_CLK, 48 DT_DP3_PHY_PLL_LINK_CLK, 49 DT_DP3_PHY_PLL_VCO_DIV_CLK, 50 }; 51 52 #define DISP_CC_MISC_CMD 0xF000 53 54 enum { 55 P_BI_TCXO, 56 P_DISP_CC_PLL0_OUT_MAIN, 57 P_DISP_CC_PLL1_OUT_EVEN, 58 P_DISP_CC_PLL1_OUT_MAIN, 59 P_DP0_PHY_PLL_LINK_CLK, 60 P_DP0_PHY_PLL_VCO_DIV_CLK, 61 P_DP1_PHY_PLL_LINK_CLK, 62 P_DP1_PHY_PLL_VCO_DIV_CLK, 63 P_DP2_PHY_PLL_LINK_CLK, 64 P_DP2_PHY_PLL_VCO_DIV_CLK, 65 P_DP3_PHY_PLL_LINK_CLK, 66 P_DP3_PHY_PLL_VCO_DIV_CLK, 67 P_DSI0_PHY_PLL_OUT_BYTECLK, 68 P_DSI0_PHY_PLL_OUT_DSICLK, 69 P_DSI1_PHY_PLL_OUT_BYTECLK, 70 P_DSI1_PHY_PLL_OUT_DSICLK, 71 P_SLEEP_CLK, 72 }; 73 74 static const struct pll_vco lucid_evo_vco[] = { 75 { 249600000, 2000000000, 0 }, 76 }; 77 78 static const struct alpha_pll_config disp_cc_pll0_config = { 79 .l = 0xD, 80 .alpha = 0x6492, 81 .config_ctl_val = 0x20485699, 82 .config_ctl_hi_val = 0x00182261, 83 .config_ctl_hi1_val = 0x32AA299C, 84 .user_ctl_val = 0x00000000, 85 .user_ctl_hi_val = 0x00000805, 86 }; 87 88 static const struct alpha_pll_config sm8475_disp_cc_pll0_config = { 89 .l = 0xd, 90 .alpha = 0x6492, 91 .config_ctl_val = 0x20485699, 92 .config_ctl_hi_val = 0x00182261, 93 .config_ctl_hi1_val = 0x82aa299c, 94 .test_ctl_val = 0x00000000, 95 .test_ctl_hi_val = 0x00000003, 96 .test_ctl_hi1_val = 0x00009000, 97 .test_ctl_hi2_val = 0x00000034, 98 .user_ctl_val = 0x00000000, 99 .user_ctl_hi_val = 0x00000005, 100 }; 101 102 static struct clk_init_data sm8475_disp_cc_pll0_init = { 103 .name = "disp_cc_pll0", 104 .parent_data = &(const struct clk_parent_data) { 105 .index = DT_BI_TCXO, 106 }, 107 .num_parents = 1, 108 .ops = &clk_alpha_pll_reset_lucid_ole_ops, 109 }; 110 111 static struct clk_alpha_pll disp_cc_pll0 = { 112 .offset = 0x0, 113 .vco_table = lucid_evo_vco, 114 .num_vco = ARRAY_SIZE(lucid_evo_vco), 115 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 116 .clkr = { 117 .hw.init = &(struct clk_init_data) { 118 .name = "disp_cc_pll0", 119 .parent_data = &(const struct clk_parent_data) { 120 .index = DT_BI_TCXO, 121 }, 122 .num_parents = 1, 123 .ops = &clk_alpha_pll_reset_lucid_evo_ops, 124 }, 125 }, 126 }; 127 128 static const struct alpha_pll_config disp_cc_pll1_config = { 129 .l = 0x1F, 130 .alpha = 0x4000, 131 .config_ctl_val = 0x20485699, 132 .config_ctl_hi_val = 0x00182261, 133 .config_ctl_hi1_val = 0x32AA299C, 134 .user_ctl_val = 0x00000000, 135 .user_ctl_hi_val = 0x00000805, 136 }; 137 138 static const struct alpha_pll_config sm8475_disp_cc_pll1_config = { 139 .l = 0x1f, 140 .alpha = 0x4000, 141 .config_ctl_val = 0x20485699, 142 .config_ctl_hi_val = 0x00182261, 143 .config_ctl_hi1_val = 0x82aa299c, 144 .test_ctl_val = 0x00000000, 145 .test_ctl_hi_val = 0x00000003, 146 .test_ctl_hi1_val = 0x00009000, 147 .test_ctl_hi2_val = 0x00000034, 148 .user_ctl_val = 0x00000000, 149 .user_ctl_hi_val = 0x00000005, 150 }; 151 152 static struct clk_init_data sm8475_disp_cc_pll1_init = { 153 .name = "disp_cc_pll1", 154 .parent_data = &(const struct clk_parent_data) { 155 .index = DT_BI_TCXO, 156 }, 157 .num_parents = 1, 158 .ops = &clk_alpha_pll_reset_lucid_ole_ops, 159 }; 160 161 static struct clk_alpha_pll disp_cc_pll1 = { 162 .offset = 0x1000, 163 .vco_table = lucid_evo_vco, 164 .num_vco = ARRAY_SIZE(lucid_evo_vco), 165 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 166 .clkr = { 167 .hw.init = &(struct clk_init_data) { 168 .name = "disp_cc_pll1", 169 .parent_data = &(const struct clk_parent_data) { 170 .index = DT_BI_TCXO, 171 }, 172 .num_parents = 1, 173 .ops = &clk_alpha_pll_reset_lucid_evo_ops, 174 }, 175 }, 176 }; 177 178 static const struct parent_map disp_cc_parent_map_0[] = { 179 { P_BI_TCXO, 0 }, 180 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 181 { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 }, 182 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, 183 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, 184 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, 185 }; 186 187 static const struct clk_parent_data disp_cc_parent_data_0[] = { 188 { .index = DT_BI_TCXO }, 189 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 190 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK }, 191 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 192 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 193 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 194 }; 195 196 static const struct parent_map disp_cc_parent_map_1[] = { 197 { P_BI_TCXO, 0 }, 198 }; 199 200 static const struct clk_parent_data disp_cc_parent_data_1[] = { 201 { .index = DT_BI_TCXO }, 202 }; 203 204 static const struct clk_parent_data disp_cc_parent_data_1_ao[] = { 205 { .index = DT_BI_TCXO_AO }, 206 }; 207 208 static const struct parent_map disp_cc_parent_map_2[] = { 209 { P_BI_TCXO, 0 }, 210 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 211 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 212 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, 213 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 214 }; 215 216 static const struct clk_parent_data disp_cc_parent_data_2[] = { 217 { .index = DT_BI_TCXO }, 218 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, 219 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 220 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, 221 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 222 }; 223 224 static const struct parent_map disp_cc_parent_map_3[] = { 225 { P_BI_TCXO, 0 }, 226 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 227 { P_DP1_PHY_PLL_LINK_CLK, 2 }, 228 { P_DP2_PHY_PLL_LINK_CLK, 3 }, 229 { P_DP3_PHY_PLL_LINK_CLK, 4 }, 230 }; 231 232 static const struct clk_parent_data disp_cc_parent_data_3[] = { 233 { .index = DT_BI_TCXO }, 234 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 235 { .index = DT_DP1_PHY_PLL_LINK_CLK }, 236 { .index = DT_DP2_PHY_PLL_LINK_CLK }, 237 { .index = DT_DP3_PHY_PLL_LINK_CLK }, 238 }; 239 240 static const struct parent_map disp_cc_parent_map_4[] = { 241 { P_BI_TCXO, 0 }, 242 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 243 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 244 }; 245 246 static const struct clk_parent_data disp_cc_parent_data_4[] = { 247 { .index = DT_BI_TCXO }, 248 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 249 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 250 }; 251 252 static const struct parent_map disp_cc_parent_map_5[] = { 253 { P_BI_TCXO, 0 }, 254 { P_DISP_CC_PLL0_OUT_MAIN, 1 }, 255 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 256 { P_DISP_CC_PLL1_OUT_EVEN, 6 }, 257 }; 258 259 static const struct clk_parent_data disp_cc_parent_data_5[] = { 260 { .index = DT_BI_TCXO }, 261 { .hw = &disp_cc_pll0.clkr.hw }, 262 { .hw = &disp_cc_pll1.clkr.hw }, 263 { .hw = &disp_cc_pll1.clkr.hw }, 264 }; 265 266 static const struct parent_map disp_cc_parent_map_6[] = { 267 { P_BI_TCXO, 0 }, 268 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 269 { P_DISP_CC_PLL1_OUT_EVEN, 6 }, 270 }; 271 272 static const struct clk_parent_data disp_cc_parent_data_6[] = { 273 { .index = DT_BI_TCXO }, 274 { .hw = &disp_cc_pll1.clkr.hw }, 275 { .hw = &disp_cc_pll1.clkr.hw }, 276 }; 277 278 static const struct parent_map disp_cc_parent_map_7[] = { 279 { P_SLEEP_CLK, 0 }, 280 }; 281 282 static const struct clk_parent_data disp_cc_parent_data_7[] = { 283 { .index = DT_SLEEP_CLK }, 284 }; 285 286 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { 287 F(19200000, P_BI_TCXO, 1, 0, 0), 288 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), 289 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), 290 { } 291 }; 292 293 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { 294 .cmd_rcgr = 0x8324, 295 .mnd_width = 0, 296 .hid_width = 5, 297 .parent_map = disp_cc_parent_map_6, 298 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 299 .clkr.hw.init = &(struct clk_init_data) { 300 .name = "disp_cc_mdss_ahb_clk_src", 301 .parent_data = disp_cc_parent_data_6, 302 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 303 .flags = CLK_SET_RATE_PARENT, 304 .ops = &clk_rcg2_shared_ops, 305 }, 306 }; 307 308 static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = { 309 F(19200000, P_BI_TCXO, 1, 0, 0), 310 { } 311 }; 312 313 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { 314 .cmd_rcgr = 0x8134, 315 .mnd_width = 0, 316 .hid_width = 5, 317 .parent_map = disp_cc_parent_map_2, 318 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 319 .clkr.hw.init = &(struct clk_init_data) { 320 .name = "disp_cc_mdss_byte0_clk_src", 321 .parent_data = disp_cc_parent_data_2, 322 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 323 .flags = CLK_SET_RATE_PARENT, 324 .ops = &clk_byte2_ops, 325 }, 326 }; 327 328 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { 329 .cmd_rcgr = 0x8150, 330 .mnd_width = 0, 331 .hid_width = 5, 332 .parent_map = disp_cc_parent_map_2, 333 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 334 .clkr.hw.init = &(struct clk_init_data) { 335 .name = "disp_cc_mdss_byte1_clk_src", 336 .parent_data = disp_cc_parent_data_2, 337 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 338 .flags = CLK_SET_RATE_PARENT, 339 .ops = &clk_byte2_ops, 340 }, 341 }; 342 343 static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { 344 .cmd_rcgr = 0x81ec, 345 .mnd_width = 0, 346 .hid_width = 5, 347 .parent_map = disp_cc_parent_map_1, 348 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 349 .clkr.hw.init = &(struct clk_init_data) { 350 .name = "disp_cc_mdss_dptx0_aux_clk_src", 351 .parent_data = disp_cc_parent_data_1, 352 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 353 .flags = CLK_SET_RATE_PARENT, 354 .ops = &clk_rcg2_ops, 355 }, 356 }; 357 358 static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { 359 .cmd_rcgr = 0x819c, 360 .mnd_width = 0, 361 .hid_width = 5, 362 .parent_map = disp_cc_parent_map_3, 363 .clkr.hw.init = &(struct clk_init_data) { 364 .name = "disp_cc_mdss_dptx0_link_clk_src", 365 .parent_data = disp_cc_parent_data_3, 366 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 367 .flags = CLK_SET_RATE_PARENT, 368 .ops = &clk_byte2_ops, 369 }, 370 }; 371 372 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = { 373 .cmd_rcgr = 0x81bc, 374 .mnd_width = 16, 375 .hid_width = 5, 376 .parent_map = disp_cc_parent_map_0, 377 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 378 .clkr.hw.init = &(struct clk_init_data) { 379 .name = "disp_cc_mdss_dptx0_pixel0_clk_src", 380 .parent_data = disp_cc_parent_data_0, 381 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 382 .flags = CLK_SET_RATE_PARENT, 383 .ops = &clk_dp_ops, 384 }, 385 }; 386 387 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = { 388 .cmd_rcgr = 0x81d4, 389 .mnd_width = 16, 390 .hid_width = 5, 391 .parent_map = disp_cc_parent_map_0, 392 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 393 .clkr.hw.init = &(struct clk_init_data) { 394 .name = "disp_cc_mdss_dptx0_pixel1_clk_src", 395 .parent_data = disp_cc_parent_data_0, 396 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 397 .flags = CLK_SET_RATE_PARENT, 398 .ops = &clk_dp_ops, 399 }, 400 }; 401 402 static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { 403 .cmd_rcgr = 0x8254, 404 .mnd_width = 0, 405 .hid_width = 5, 406 .parent_map = disp_cc_parent_map_1, 407 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 408 .clkr.hw.init = &(struct clk_init_data) { 409 .name = "disp_cc_mdss_dptx1_aux_clk_src", 410 .parent_data = disp_cc_parent_data_1, 411 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 412 .flags = CLK_SET_RATE_PARENT, 413 .ops = &clk_dp_ops, 414 }, 415 }; 416 417 static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { 418 .cmd_rcgr = 0x8234, 419 .mnd_width = 0, 420 .hid_width = 5, 421 .parent_map = disp_cc_parent_map_3, 422 .clkr.hw.init = &(struct clk_init_data) { 423 .name = "disp_cc_mdss_dptx1_link_clk_src", 424 .parent_data = disp_cc_parent_data_3, 425 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 426 .flags = CLK_SET_RATE_PARENT, 427 .ops = &clk_byte2_ops, 428 }, 429 }; 430 431 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = { 432 .cmd_rcgr = 0x8204, 433 .mnd_width = 16, 434 .hid_width = 5, 435 .parent_map = disp_cc_parent_map_0, 436 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 437 .clkr.hw.init = &(struct clk_init_data) { 438 .name = "disp_cc_mdss_dptx1_pixel0_clk_src", 439 .parent_data = disp_cc_parent_data_0, 440 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 441 .flags = CLK_SET_RATE_PARENT, 442 .ops = &clk_dp_ops, 443 }, 444 }; 445 446 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = { 447 .cmd_rcgr = 0x821c, 448 .mnd_width = 16, 449 .hid_width = 5, 450 .parent_map = disp_cc_parent_map_0, 451 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 452 .clkr.hw.init = &(struct clk_init_data) { 453 .name = "disp_cc_mdss_dptx1_pixel1_clk_src", 454 .parent_data = disp_cc_parent_data_0, 455 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 456 .flags = CLK_SET_RATE_PARENT, 457 .ops = &clk_dp_ops, 458 }, 459 }; 460 461 static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = { 462 .cmd_rcgr = 0x82bc, 463 .mnd_width = 0, 464 .hid_width = 5, 465 .parent_map = disp_cc_parent_map_1, 466 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 467 .clkr.hw.init = &(struct clk_init_data) { 468 .name = "disp_cc_mdss_dptx2_aux_clk_src", 469 .parent_data = disp_cc_parent_data_1, 470 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 471 .flags = CLK_SET_RATE_PARENT, 472 .ops = &clk_rcg2_ops, 473 }, 474 }; 475 476 static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { 477 .cmd_rcgr = 0x826c, 478 .mnd_width = 0, 479 .hid_width = 5, 480 .parent_map = disp_cc_parent_map_3, 481 .clkr.hw.init = &(struct clk_init_data) { 482 .name = "disp_cc_mdss_dptx2_link_clk_src", 483 .parent_data = disp_cc_parent_data_3, 484 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 485 .flags = CLK_SET_RATE_PARENT, 486 .ops = &clk_byte2_ops, 487 }, 488 }; 489 490 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = { 491 .cmd_rcgr = 0x828c, 492 .mnd_width = 16, 493 .hid_width = 5, 494 .parent_map = disp_cc_parent_map_0, 495 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 496 .clkr.hw.init = &(struct clk_init_data) { 497 .name = "disp_cc_mdss_dptx2_pixel0_clk_src", 498 .parent_data = disp_cc_parent_data_0, 499 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 500 .flags = CLK_SET_RATE_PARENT, 501 .ops = &clk_dp_ops, 502 }, 503 }; 504 505 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = { 506 .cmd_rcgr = 0x82a4, 507 .mnd_width = 16, 508 .hid_width = 5, 509 .parent_map = disp_cc_parent_map_0, 510 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 511 .clkr.hw.init = &(struct clk_init_data) { 512 .name = "disp_cc_mdss_dptx2_pixel1_clk_src", 513 .parent_data = disp_cc_parent_data_0, 514 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 515 .flags = CLK_SET_RATE_PARENT, 516 .ops = &clk_dp_ops, 517 }, 518 }; 519 520 static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = { 521 .cmd_rcgr = 0x8308, 522 .mnd_width = 0, 523 .hid_width = 5, 524 .parent_map = disp_cc_parent_map_1, 525 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 526 .clkr.hw.init = &(struct clk_init_data) { 527 .name = "disp_cc_mdss_dptx3_aux_clk_src", 528 .parent_data = disp_cc_parent_data_1, 529 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 530 .flags = CLK_SET_RATE_PARENT, 531 .ops = &clk_rcg2_ops, 532 }, 533 }; 534 535 static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { 536 .cmd_rcgr = 0x82ec, 537 .mnd_width = 0, 538 .hid_width = 5, 539 .parent_map = disp_cc_parent_map_3, 540 .clkr.hw.init = &(struct clk_init_data) { 541 .name = "disp_cc_mdss_dptx3_link_clk_src", 542 .parent_data = disp_cc_parent_data_3, 543 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 544 .flags = CLK_SET_RATE_PARENT, 545 .ops = &clk_byte2_ops, 546 }, 547 }; 548 549 static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = { 550 .cmd_rcgr = 0x82d4, 551 .mnd_width = 16, 552 .hid_width = 5, 553 .parent_map = disp_cc_parent_map_0, 554 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 555 .clkr.hw.init = &(struct clk_init_data) { 556 .name = "disp_cc_mdss_dptx3_pixel0_clk_src", 557 .parent_data = disp_cc_parent_data_0, 558 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 559 .flags = CLK_SET_RATE_PARENT, 560 .ops = &clk_dp_ops, 561 }, 562 }; 563 564 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { 565 .cmd_rcgr = 0x816c, 566 .mnd_width = 0, 567 .hid_width = 5, 568 .parent_map = disp_cc_parent_map_4, 569 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 570 .clkr.hw.init = &(struct clk_init_data) { 571 .name = "disp_cc_mdss_esc0_clk_src", 572 .parent_data = disp_cc_parent_data_4, 573 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 574 .flags = CLK_SET_RATE_PARENT, 575 .ops = &clk_rcg2_ops, 576 }, 577 }; 578 579 static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { 580 .cmd_rcgr = 0x8184, 581 .mnd_width = 0, 582 .hid_width = 5, 583 .parent_map = disp_cc_parent_map_4, 584 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 585 .clkr.hw.init = &(struct clk_init_data) { 586 .name = "disp_cc_mdss_esc1_clk_src", 587 .parent_data = disp_cc_parent_data_4, 588 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 589 .flags = CLK_SET_RATE_PARENT, 590 .ops = &clk_rcg2_ops, 591 }, 592 }; 593 594 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { 595 F(19200000, P_BI_TCXO, 1, 0, 0), 596 F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 597 F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 598 F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 599 F(172000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 600 F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 601 F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 602 F(375000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 603 F(500000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 604 { } 605 }; 606 607 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { 608 .cmd_rcgr = 0x80ec, 609 .mnd_width = 0, 610 .hid_width = 5, 611 .parent_map = disp_cc_parent_map_5, 612 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 613 .clkr.hw.init = &(struct clk_init_data) { 614 .name = "disp_cc_mdss_mdp_clk_src", 615 .parent_data = disp_cc_parent_data_5, 616 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 617 .flags = CLK_SET_RATE_PARENT, 618 .ops = &clk_rcg2_shared_ops, 619 }, 620 }; 621 622 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { 623 .cmd_rcgr = 0x80bc, 624 .mnd_width = 8, 625 .hid_width = 5, 626 .parent_map = disp_cc_parent_map_2, 627 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 628 .clkr.hw.init = &(struct clk_init_data) { 629 .name = "disp_cc_mdss_pclk0_clk_src", 630 .parent_data = disp_cc_parent_data_2, 631 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 632 .flags = CLK_SET_RATE_PARENT, 633 .ops = &clk_pixel_ops, 634 }, 635 }; 636 637 static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { 638 .cmd_rcgr = 0x80d4, 639 .mnd_width = 8, 640 .hid_width = 5, 641 .parent_map = disp_cc_parent_map_2, 642 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 643 .clkr.hw.init = &(struct clk_init_data) { 644 .name = "disp_cc_mdss_pclk1_clk_src", 645 .parent_data = disp_cc_parent_data_2, 646 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 647 .flags = CLK_SET_RATE_PARENT, 648 .ops = &clk_pixel_ops, 649 }, 650 }; 651 652 static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = { 653 F(19200000, P_BI_TCXO, 1, 0, 0), 654 F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0), 655 F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0), 656 F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0), 657 { } 658 }; 659 660 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { 661 .cmd_rcgr = 0x8104, 662 .mnd_width = 0, 663 .hid_width = 5, 664 .parent_map = disp_cc_parent_map_5, 665 .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, 666 .clkr.hw.init = &(struct clk_init_data) { 667 .name = "disp_cc_mdss_rot_clk_src", 668 .parent_data = disp_cc_parent_data_5, 669 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 670 .flags = CLK_SET_RATE_PARENT, 671 .ops = &clk_rcg2_shared_ops, 672 }, 673 }; 674 675 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { 676 .cmd_rcgr = 0x811c, 677 .mnd_width = 0, 678 .hid_width = 5, 679 .parent_map = disp_cc_parent_map_1, 680 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 681 .clkr.hw.init = &(struct clk_init_data) { 682 .name = "disp_cc_mdss_vsync_clk_src", 683 .parent_data = disp_cc_parent_data_1, 684 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 685 .flags = CLK_SET_RATE_PARENT, 686 .ops = &clk_rcg2_ops, 687 }, 688 }; 689 690 static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = { 691 F(32000, P_SLEEP_CLK, 1, 0, 0), 692 { } 693 }; 694 695 static struct clk_rcg2 disp_cc_sleep_clk_src = { 696 .cmd_rcgr = 0xe060, 697 .mnd_width = 0, 698 .hid_width = 5, 699 .parent_map = disp_cc_parent_map_7, 700 .freq_tbl = ftbl_disp_cc_sleep_clk_src, 701 .clkr.hw.init = &(struct clk_init_data) { 702 .name = "disp_cc_sleep_clk_src", 703 .parent_data = disp_cc_parent_data_7, 704 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), 705 .flags = CLK_SET_RATE_PARENT, 706 .ops = &clk_rcg2_ops, 707 }, 708 }; 709 710 static struct clk_rcg2 disp_cc_xo_clk_src = { 711 .cmd_rcgr = 0xe044, 712 .mnd_width = 0, 713 .hid_width = 5, 714 .parent_map = disp_cc_parent_map_1, 715 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 716 .clkr.hw.init = &(struct clk_init_data) { 717 .name = "disp_cc_xo_clk_src", 718 .parent_data = disp_cc_parent_data_1_ao, 719 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1_ao), 720 .flags = CLK_SET_RATE_PARENT, 721 .ops = &clk_rcg2_ops, 722 }, 723 }; 724 725 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { 726 .reg = 0x814c, 727 .shift = 0, 728 .width = 4, 729 .clkr.hw.init = &(struct clk_init_data) { 730 .name = "disp_cc_mdss_byte0_div_clk_src", 731 .parent_hws = (const struct clk_hw*[]) { 732 &disp_cc_mdss_byte0_clk_src.clkr.hw, 733 }, 734 .num_parents = 1, 735 .ops = &clk_regmap_div_ops, 736 }, 737 }; 738 739 static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { 740 .reg = 0x8168, 741 .shift = 0, 742 .width = 4, 743 .clkr.hw.init = &(struct clk_init_data) { 744 .name = "disp_cc_mdss_byte1_div_clk_src", 745 .parent_hws = (const struct clk_hw*[]) { 746 &disp_cc_mdss_byte1_clk_src.clkr.hw, 747 }, 748 .num_parents = 1, 749 .ops = &clk_regmap_div_ops, 750 }, 751 }; 752 753 static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = { 754 .reg = 0x81b4, 755 .shift = 0, 756 .width = 4, 757 .clkr.hw.init = &(struct clk_init_data) { 758 .name = "disp_cc_mdss_dptx0_link_div_clk_src", 759 .parent_hws = (const struct clk_hw*[]) { 760 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 761 }, 762 .num_parents = 1, 763 .flags = CLK_SET_RATE_PARENT, 764 .ops = &clk_regmap_div_ro_ops, 765 }, 766 }; 767 768 static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = { 769 .reg = 0x824c, 770 .shift = 0, 771 .width = 4, 772 .clkr.hw.init = &(struct clk_init_data) { 773 .name = "disp_cc_mdss_dptx1_link_div_clk_src", 774 .parent_hws = (const struct clk_hw*[]) { 775 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 776 }, 777 .num_parents = 1, 778 .flags = CLK_SET_RATE_PARENT, 779 .ops = &clk_regmap_div_ro_ops, 780 }, 781 }; 782 783 static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = { 784 .reg = 0x8284, 785 .shift = 0, 786 .width = 4, 787 .clkr.hw.init = &(struct clk_init_data) { 788 .name = "disp_cc_mdss_dptx2_link_div_clk_src", 789 .parent_hws = (const struct clk_hw*[]) { 790 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 791 }, 792 .num_parents = 1, 793 .flags = CLK_SET_RATE_PARENT, 794 .ops = &clk_regmap_div_ro_ops, 795 }, 796 }; 797 798 static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = { 799 .reg = 0x8304, 800 .shift = 0, 801 .width = 4, 802 .clkr.hw.init = &(struct clk_init_data) { 803 .name = "disp_cc_mdss_dptx3_link_div_clk_src", 804 .parent_hws = (const struct clk_hw*[]) { 805 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 806 }, 807 .num_parents = 1, 808 .flags = CLK_SET_RATE_PARENT, 809 .ops = &clk_regmap_div_ro_ops, 810 }, 811 }; 812 813 static struct clk_branch disp_cc_mdss_ahb1_clk = { 814 .halt_reg = 0xa020, 815 .halt_check = BRANCH_HALT, 816 .clkr = { 817 .enable_reg = 0xa020, 818 .enable_mask = BIT(0), 819 .hw.init = &(struct clk_init_data) { 820 .name = "disp_cc_mdss_ahb1_clk", 821 .parent_hws = (const struct clk_hw*[]) { 822 &disp_cc_mdss_ahb_clk_src.clkr.hw, 823 }, 824 .num_parents = 1, 825 .flags = CLK_SET_RATE_PARENT, 826 .ops = &clk_branch2_ops, 827 }, 828 }, 829 }; 830 831 static struct clk_branch disp_cc_mdss_ahb_clk = { 832 .halt_reg = 0x80a4, 833 .halt_check = BRANCH_HALT, 834 .clkr = { 835 .enable_reg = 0x80a4, 836 .enable_mask = BIT(0), 837 .hw.init = &(struct clk_init_data) { 838 .name = "disp_cc_mdss_ahb_clk", 839 .parent_hws = (const struct clk_hw*[]) { 840 &disp_cc_mdss_ahb_clk_src.clkr.hw, 841 }, 842 .num_parents = 1, 843 .flags = CLK_SET_RATE_PARENT, 844 .ops = &clk_branch2_ops, 845 }, 846 }, 847 }; 848 849 static struct clk_branch disp_cc_mdss_byte0_clk = { 850 .halt_reg = 0x8028, 851 .halt_check = BRANCH_HALT, 852 .clkr = { 853 .enable_reg = 0x8028, 854 .enable_mask = BIT(0), 855 .hw.init = &(struct clk_init_data) { 856 .name = "disp_cc_mdss_byte0_clk", 857 .parent_hws = (const struct clk_hw*[]) { 858 &disp_cc_mdss_byte0_clk_src.clkr.hw, 859 }, 860 .num_parents = 1, 861 .flags = CLK_SET_RATE_PARENT, 862 .ops = &clk_branch2_ops, 863 }, 864 }, 865 }; 866 867 static struct clk_branch disp_cc_mdss_byte0_intf_clk = { 868 .halt_reg = 0x802c, 869 .halt_check = BRANCH_HALT, 870 .clkr = { 871 .enable_reg = 0x802c, 872 .enable_mask = BIT(0), 873 .hw.init = &(struct clk_init_data) { 874 .name = "disp_cc_mdss_byte0_intf_clk", 875 .parent_hws = (const struct clk_hw*[]) { 876 &disp_cc_mdss_byte0_div_clk_src.clkr.hw, 877 }, 878 .num_parents = 1, 879 .flags = CLK_SET_RATE_PARENT, 880 .ops = &clk_branch2_ops, 881 }, 882 }, 883 }; 884 885 static struct clk_branch disp_cc_mdss_byte1_clk = { 886 .halt_reg = 0x8030, 887 .halt_check = BRANCH_HALT, 888 .clkr = { 889 .enable_reg = 0x8030, 890 .enable_mask = BIT(0), 891 .hw.init = &(struct clk_init_data) { 892 .name = "disp_cc_mdss_byte1_clk", 893 .parent_hws = (const struct clk_hw*[]) { 894 &disp_cc_mdss_byte1_clk_src.clkr.hw, 895 }, 896 .num_parents = 1, 897 .flags = CLK_SET_RATE_PARENT, 898 .ops = &clk_branch2_ops, 899 }, 900 }, 901 }; 902 903 static struct clk_branch disp_cc_mdss_byte1_intf_clk = { 904 .halt_reg = 0x8034, 905 .halt_check = BRANCH_HALT, 906 .clkr = { 907 .enable_reg = 0x8034, 908 .enable_mask = BIT(0), 909 .hw.init = &(struct clk_init_data) { 910 .name = "disp_cc_mdss_byte1_intf_clk", 911 .parent_hws = (const struct clk_hw*[]) { 912 &disp_cc_mdss_byte1_div_clk_src.clkr.hw, 913 }, 914 .num_parents = 1, 915 .flags = CLK_SET_RATE_PARENT, 916 .ops = &clk_branch2_ops, 917 }, 918 }, 919 }; 920 921 static struct clk_branch disp_cc_mdss_dptx0_aux_clk = { 922 .halt_reg = 0x8058, 923 .halt_check = BRANCH_HALT, 924 .clkr = { 925 .enable_reg = 0x8058, 926 .enable_mask = BIT(0), 927 .hw.init = &(struct clk_init_data) { 928 .name = "disp_cc_mdss_dptx0_aux_clk", 929 .parent_hws = (const struct clk_hw*[]) { 930 &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, 931 }, 932 .num_parents = 1, 933 .flags = CLK_SET_RATE_PARENT, 934 .ops = &clk_branch2_ops, 935 }, 936 }, 937 }; 938 939 static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = { 940 .halt_reg = 0x804c, 941 .halt_check = BRANCH_HALT, 942 .clkr = { 943 .enable_reg = 0x804c, 944 .enable_mask = BIT(0), 945 .hw.init = &(struct clk_init_data) { 946 .name = "disp_cc_mdss_dptx0_crypto_clk", 947 .parent_hws = (const struct clk_hw*[]) { 948 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 949 }, 950 .num_parents = 1, 951 .flags = CLK_SET_RATE_PARENT, 952 .ops = &clk_branch2_ops, 953 }, 954 }, 955 }; 956 957 static struct clk_branch disp_cc_mdss_dptx0_link_clk = { 958 .halt_reg = 0x8040, 959 .halt_check = BRANCH_HALT, 960 .clkr = { 961 .enable_reg = 0x8040, 962 .enable_mask = BIT(0), 963 .hw.init = &(struct clk_init_data) { 964 .name = "disp_cc_mdss_dptx0_link_clk", 965 .parent_hws = (const struct clk_hw*[]) { 966 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 967 }, 968 .num_parents = 1, 969 .flags = CLK_SET_RATE_PARENT, 970 .ops = &clk_branch2_ops, 971 }, 972 }, 973 }; 974 975 static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = { 976 .halt_reg = 0x8048, 977 .halt_check = BRANCH_HALT, 978 .clkr = { 979 .enable_reg = 0x8048, 980 .enable_mask = BIT(0), 981 .hw.init = &(struct clk_init_data) { 982 .name = "disp_cc_mdss_dptx0_link_intf_clk", 983 .parent_hws = (const struct clk_hw*[]) { 984 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 985 }, 986 .num_parents = 1, 987 .flags = CLK_SET_RATE_PARENT, 988 .ops = &clk_branch2_ops, 989 }, 990 }, 991 }; 992 993 static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = { 994 .halt_reg = 0x8050, 995 .halt_check = BRANCH_HALT, 996 .clkr = { 997 .enable_reg = 0x8050, 998 .enable_mask = BIT(0), 999 .hw.init = &(struct clk_init_data) { 1000 .name = "disp_cc_mdss_dptx0_pixel0_clk", 1001 .parent_hws = (const struct clk_hw*[]) { 1002 &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, 1003 }, 1004 .num_parents = 1, 1005 .flags = CLK_SET_RATE_PARENT, 1006 .ops = &clk_branch2_ops, 1007 }, 1008 }, 1009 }; 1010 1011 static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = { 1012 .halt_reg = 0x8054, 1013 .halt_check = BRANCH_HALT, 1014 .clkr = { 1015 .enable_reg = 0x8054, 1016 .enable_mask = BIT(0), 1017 .hw.init = &(struct clk_init_data) { 1018 .name = "disp_cc_mdss_dptx0_pixel1_clk", 1019 .parent_hws = (const struct clk_hw*[]) { 1020 &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, 1021 }, 1022 .num_parents = 1, 1023 .flags = CLK_SET_RATE_PARENT, 1024 .ops = &clk_branch2_ops, 1025 }, 1026 }, 1027 }; 1028 1029 static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = { 1030 .halt_reg = 0x8044, 1031 .halt_check = BRANCH_HALT, 1032 .clkr = { 1033 .enable_reg = 0x8044, 1034 .enable_mask = BIT(0), 1035 .hw.init = &(struct clk_init_data) { 1036 .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk", 1037 .parent_hws = (const struct clk_hw*[]) { 1038 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1039 }, 1040 .num_parents = 1, 1041 .flags = CLK_SET_RATE_PARENT, 1042 .ops = &clk_branch2_ops, 1043 }, 1044 }, 1045 }; 1046 1047 static struct clk_branch disp_cc_mdss_dptx1_aux_clk = { 1048 .halt_reg = 0x8074, 1049 .halt_check = BRANCH_HALT, 1050 .clkr = { 1051 .enable_reg = 0x8074, 1052 .enable_mask = BIT(0), 1053 .hw.init = &(struct clk_init_data) { 1054 .name = "disp_cc_mdss_dptx1_aux_clk", 1055 .parent_hws = (const struct clk_hw*[]) { 1056 &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, 1057 }, 1058 .num_parents = 1, 1059 .flags = CLK_SET_RATE_PARENT, 1060 .ops = &clk_branch2_ops, 1061 }, 1062 }, 1063 }; 1064 1065 static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = { 1066 .halt_reg = 0x8070, 1067 .halt_check = BRANCH_HALT, 1068 .clkr = { 1069 .enable_reg = 0x8070, 1070 .enable_mask = BIT(0), 1071 .hw.init = &(struct clk_init_data) { 1072 .name = "disp_cc_mdss_dptx1_crypto_clk", 1073 .parent_hws = (const struct clk_hw*[]) { 1074 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 1075 }, 1076 .num_parents = 1, 1077 .flags = CLK_SET_RATE_PARENT, 1078 .ops = &clk_branch2_ops, 1079 }, 1080 }, 1081 }; 1082 1083 static struct clk_branch disp_cc_mdss_dptx1_link_clk = { 1084 .halt_reg = 0x8064, 1085 .halt_check = BRANCH_HALT, 1086 .clkr = { 1087 .enable_reg = 0x8064, 1088 .enable_mask = BIT(0), 1089 .hw.init = &(struct clk_init_data) { 1090 .name = "disp_cc_mdss_dptx1_link_clk", 1091 .parent_hws = (const struct clk_hw*[]) { 1092 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 1093 }, 1094 .num_parents = 1, 1095 .flags = CLK_SET_RATE_PARENT, 1096 .ops = &clk_branch2_ops, 1097 }, 1098 }, 1099 }; 1100 1101 static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = { 1102 .halt_reg = 0x806c, 1103 .halt_check = BRANCH_HALT, 1104 .clkr = { 1105 .enable_reg = 0x806c, 1106 .enable_mask = BIT(0), 1107 .hw.init = &(struct clk_init_data) { 1108 .name = "disp_cc_mdss_dptx1_link_intf_clk", 1109 .parent_hws = (const struct clk_hw*[]) { 1110 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1111 }, 1112 .num_parents = 1, 1113 .flags = CLK_SET_RATE_PARENT, 1114 .ops = &clk_branch2_ops, 1115 }, 1116 }, 1117 }; 1118 1119 static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = { 1120 .halt_reg = 0x805c, 1121 .halt_check = BRANCH_HALT, 1122 .clkr = { 1123 .enable_reg = 0x805c, 1124 .enable_mask = BIT(0), 1125 .hw.init = &(struct clk_init_data) { 1126 .name = "disp_cc_mdss_dptx1_pixel0_clk", 1127 .parent_hws = (const struct clk_hw*[]) { 1128 &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, 1129 }, 1130 .num_parents = 1, 1131 .flags = CLK_SET_RATE_PARENT, 1132 .ops = &clk_branch2_ops, 1133 }, 1134 }, 1135 }; 1136 1137 static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = { 1138 .halt_reg = 0x8060, 1139 .halt_check = BRANCH_HALT, 1140 .clkr = { 1141 .enable_reg = 0x8060, 1142 .enable_mask = BIT(0), 1143 .hw.init = &(struct clk_init_data) { 1144 .name = "disp_cc_mdss_dptx1_pixel1_clk", 1145 .parent_hws = (const struct clk_hw*[]) { 1146 &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, 1147 }, 1148 .num_parents = 1, 1149 .flags = CLK_SET_RATE_PARENT, 1150 .ops = &clk_branch2_ops, 1151 }, 1152 }, 1153 }; 1154 1155 static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = { 1156 .halt_reg = 0x8068, 1157 .halt_check = BRANCH_HALT, 1158 .clkr = { 1159 .enable_reg = 0x8068, 1160 .enable_mask = BIT(0), 1161 .hw.init = &(struct clk_init_data) { 1162 .name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk", 1163 .parent_hws = (const struct clk_hw*[]) { 1164 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1165 }, 1166 .num_parents = 1, 1167 .flags = CLK_SET_RATE_PARENT, 1168 .ops = &clk_branch2_ops, 1169 }, 1170 }, 1171 }; 1172 1173 static struct clk_branch disp_cc_mdss_dptx2_aux_clk = { 1174 .halt_reg = 0x808c, 1175 .halt_check = BRANCH_HALT, 1176 .clkr = { 1177 .enable_reg = 0x808c, 1178 .enable_mask = BIT(0), 1179 .hw.init = &(struct clk_init_data) { 1180 .name = "disp_cc_mdss_dptx2_aux_clk", 1181 .parent_hws = (const struct clk_hw*[]) { 1182 &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw, 1183 }, 1184 .num_parents = 1, 1185 .flags = CLK_SET_RATE_PARENT, 1186 .ops = &clk_branch2_ops, 1187 }, 1188 }, 1189 }; 1190 1191 static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = { 1192 .halt_reg = 0x8088, 1193 .halt_check = BRANCH_HALT, 1194 .clkr = { 1195 .enable_reg = 0x8088, 1196 .enable_mask = BIT(0), 1197 .hw.init = &(struct clk_init_data) { 1198 .name = "disp_cc_mdss_dptx2_crypto_clk", 1199 .parent_hws = (const struct clk_hw*[]) { 1200 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 1201 }, 1202 .num_parents = 1, 1203 .flags = CLK_SET_RATE_PARENT, 1204 .ops = &clk_branch2_ops, 1205 }, 1206 }, 1207 }; 1208 1209 static struct clk_branch disp_cc_mdss_dptx2_link_clk = { 1210 .halt_reg = 0x8080, 1211 .halt_check = BRANCH_HALT, 1212 .clkr = { 1213 .enable_reg = 0x8080, 1214 .enable_mask = BIT(0), 1215 .hw.init = &(struct clk_init_data) { 1216 .name = "disp_cc_mdss_dptx2_link_clk", 1217 .parent_hws = (const struct clk_hw*[]) { 1218 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 1219 }, 1220 .num_parents = 1, 1221 .flags = CLK_SET_RATE_PARENT, 1222 .ops = &clk_branch2_ops, 1223 }, 1224 }, 1225 }; 1226 1227 static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = { 1228 .halt_reg = 0x8084, 1229 .halt_check = BRANCH_HALT, 1230 .clkr = { 1231 .enable_reg = 0x8084, 1232 .enable_mask = BIT(0), 1233 .hw.init = &(struct clk_init_data) { 1234 .name = "disp_cc_mdss_dptx2_link_intf_clk", 1235 .parent_hws = (const struct clk_hw*[]) { 1236 &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, 1237 }, 1238 .num_parents = 1, 1239 .flags = CLK_SET_RATE_PARENT, 1240 .ops = &clk_branch2_ops, 1241 }, 1242 }, 1243 }; 1244 1245 static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = { 1246 .halt_reg = 0x8078, 1247 .halt_check = BRANCH_HALT, 1248 .clkr = { 1249 .enable_reg = 0x8078, 1250 .enable_mask = BIT(0), 1251 .hw.init = &(struct clk_init_data) { 1252 .name = "disp_cc_mdss_dptx2_pixel0_clk", 1253 .parent_hws = (const struct clk_hw*[]) { 1254 &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, 1255 }, 1256 .num_parents = 1, 1257 .flags = CLK_SET_RATE_PARENT, 1258 .ops = &clk_branch2_ops, 1259 }, 1260 }, 1261 }; 1262 1263 static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = { 1264 .halt_reg = 0x807c, 1265 .halt_check = BRANCH_HALT, 1266 .clkr = { 1267 .enable_reg = 0x807c, 1268 .enable_mask = BIT(0), 1269 .hw.init = &(struct clk_init_data) { 1270 .name = "disp_cc_mdss_dptx2_pixel1_clk", 1271 .parent_hws = (const struct clk_hw*[]) { 1272 &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, 1273 }, 1274 .num_parents = 1, 1275 .flags = CLK_SET_RATE_PARENT, 1276 .ops = &clk_branch2_ops, 1277 }, 1278 }, 1279 }; 1280 1281 static struct clk_branch disp_cc_mdss_dptx3_aux_clk = { 1282 .halt_reg = 0x809c, 1283 .halt_check = BRANCH_HALT, 1284 .clkr = { 1285 .enable_reg = 0x809c, 1286 .enable_mask = BIT(0), 1287 .hw.init = &(struct clk_init_data) { 1288 .name = "disp_cc_mdss_dptx3_aux_clk", 1289 .parent_hws = (const struct clk_hw*[]) { 1290 &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw, 1291 }, 1292 .num_parents = 1, 1293 .flags = CLK_SET_RATE_PARENT, 1294 .ops = &clk_branch2_ops, 1295 }, 1296 }, 1297 }; 1298 1299 static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = { 1300 .halt_reg = 0x80a0, 1301 .halt_check = BRANCH_HALT, 1302 .clkr = { 1303 .enable_reg = 0x80a0, 1304 .enable_mask = BIT(0), 1305 .hw.init = &(struct clk_init_data) { 1306 .name = "disp_cc_mdss_dptx3_crypto_clk", 1307 .parent_hws = (const struct clk_hw*[]) { 1308 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 1309 }, 1310 .num_parents = 1, 1311 .flags = CLK_SET_RATE_PARENT, 1312 .ops = &clk_branch2_ops, 1313 }, 1314 }, 1315 }; 1316 1317 static struct clk_branch disp_cc_mdss_dptx3_link_clk = { 1318 .halt_reg = 0x8094, 1319 .halt_check = BRANCH_HALT, 1320 .clkr = { 1321 .enable_reg = 0x8094, 1322 .enable_mask = BIT(0), 1323 .hw.init = &(struct clk_init_data) { 1324 .name = "disp_cc_mdss_dptx3_link_clk", 1325 .parent_hws = (const struct clk_hw*[]) { 1326 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 1327 }, 1328 .num_parents = 1, 1329 .flags = CLK_SET_RATE_PARENT, 1330 .ops = &clk_branch2_ops, 1331 }, 1332 }, 1333 }; 1334 1335 static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = { 1336 .halt_reg = 0x8098, 1337 .halt_check = BRANCH_HALT, 1338 .clkr = { 1339 .enable_reg = 0x8098, 1340 .enable_mask = BIT(0), 1341 .hw.init = &(struct clk_init_data) { 1342 .name = "disp_cc_mdss_dptx3_link_intf_clk", 1343 .parent_hws = (const struct clk_hw*[]) { 1344 &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw, 1345 }, 1346 .num_parents = 1, 1347 .flags = CLK_SET_RATE_PARENT, 1348 .ops = &clk_branch2_ops, 1349 }, 1350 }, 1351 }; 1352 1353 static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = { 1354 .halt_reg = 0x8090, 1355 .halt_check = BRANCH_HALT, 1356 .clkr = { 1357 .enable_reg = 0x8090, 1358 .enable_mask = BIT(0), 1359 .hw.init = &(struct clk_init_data) { 1360 .name = "disp_cc_mdss_dptx3_pixel0_clk", 1361 .parent_hws = (const struct clk_hw*[]) { 1362 &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, 1363 }, 1364 .num_parents = 1, 1365 .flags = CLK_SET_RATE_PARENT, 1366 .ops = &clk_branch2_ops, 1367 }, 1368 }, 1369 }; 1370 1371 static struct clk_branch disp_cc_mdss_esc0_clk = { 1372 .halt_reg = 0x8038, 1373 .halt_check = BRANCH_HALT, 1374 .clkr = { 1375 .enable_reg = 0x8038, 1376 .enable_mask = BIT(0), 1377 .hw.init = &(struct clk_init_data) { 1378 .name = "disp_cc_mdss_esc0_clk", 1379 .parent_hws = (const struct clk_hw*[]) { 1380 &disp_cc_mdss_esc0_clk_src.clkr.hw, 1381 }, 1382 .num_parents = 1, 1383 .flags = CLK_SET_RATE_PARENT, 1384 .ops = &clk_branch2_ops, 1385 }, 1386 }, 1387 }; 1388 1389 static struct clk_branch disp_cc_mdss_esc1_clk = { 1390 .halt_reg = 0x803c, 1391 .halt_check = BRANCH_HALT, 1392 .clkr = { 1393 .enable_reg = 0x803c, 1394 .enable_mask = BIT(0), 1395 .hw.init = &(struct clk_init_data) { 1396 .name = "disp_cc_mdss_esc1_clk", 1397 .parent_hws = (const struct clk_hw*[]) { 1398 &disp_cc_mdss_esc1_clk_src.clkr.hw, 1399 }, 1400 .num_parents = 1, 1401 .flags = CLK_SET_RATE_PARENT, 1402 .ops = &clk_branch2_ops, 1403 }, 1404 }, 1405 }; 1406 1407 static struct clk_branch disp_cc_mdss_mdp1_clk = { 1408 .halt_reg = 0xa004, 1409 .halt_check = BRANCH_HALT, 1410 .clkr = { 1411 .enable_reg = 0xa004, 1412 .enable_mask = BIT(0), 1413 .hw.init = &(struct clk_init_data) { 1414 .name = "disp_cc_mdss_mdp1_clk", 1415 .parent_hws = (const struct clk_hw*[]) { 1416 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1417 }, 1418 .num_parents = 1, 1419 .flags = CLK_SET_RATE_PARENT, 1420 .ops = &clk_branch2_ops, 1421 }, 1422 }, 1423 }; 1424 1425 static struct clk_branch disp_cc_mdss_mdp_clk = { 1426 .halt_reg = 0x800c, 1427 .halt_check = BRANCH_HALT, 1428 .clkr = { 1429 .enable_reg = 0x800c, 1430 .enable_mask = BIT(0), 1431 .hw.init = &(struct clk_init_data) { 1432 .name = "disp_cc_mdss_mdp_clk", 1433 .parent_hws = (const struct clk_hw*[]) { 1434 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1435 }, 1436 .num_parents = 1, 1437 .flags = CLK_SET_RATE_PARENT, 1438 .ops = &clk_branch2_ops, 1439 }, 1440 }, 1441 }; 1442 1443 static struct clk_branch disp_cc_mdss_mdp_lut1_clk = { 1444 .halt_reg = 0xa014, 1445 .halt_check = BRANCH_HALT, 1446 .clkr = { 1447 .enable_reg = 0xa014, 1448 .enable_mask = BIT(0), 1449 .hw.init = &(struct clk_init_data) { 1450 .name = "disp_cc_mdss_mdp_lut1_clk", 1451 .parent_hws = (const struct clk_hw*[]) { 1452 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1453 }, 1454 .num_parents = 1, 1455 .flags = CLK_SET_RATE_PARENT, 1456 .ops = &clk_branch2_ops, 1457 }, 1458 }, 1459 }; 1460 1461 static struct clk_branch disp_cc_mdss_mdp_lut_clk = { 1462 .halt_reg = 0x801c, 1463 .halt_check = BRANCH_HALT_VOTED, 1464 .clkr = { 1465 .enable_reg = 0x801c, 1466 .enable_mask = BIT(0), 1467 .hw.init = &(struct clk_init_data) { 1468 .name = "disp_cc_mdss_mdp_lut_clk", 1469 .parent_hws = (const struct clk_hw*[]) { 1470 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1471 }, 1472 .num_parents = 1, 1473 .flags = CLK_SET_RATE_PARENT, 1474 .ops = &clk_branch2_ops, 1475 }, 1476 }, 1477 }; 1478 1479 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { 1480 .halt_reg = 0xc004, 1481 .halt_check = BRANCH_HALT_VOTED, 1482 .clkr = { 1483 .enable_reg = 0xc004, 1484 .enable_mask = BIT(0), 1485 .hw.init = &(struct clk_init_data) { 1486 .name = "disp_cc_mdss_non_gdsc_ahb_clk", 1487 .parent_hws = (const struct clk_hw*[]) { 1488 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1489 }, 1490 .num_parents = 1, 1491 .flags = CLK_SET_RATE_PARENT, 1492 .ops = &clk_branch2_ops, 1493 }, 1494 }, 1495 }; 1496 1497 static struct clk_branch disp_cc_mdss_pclk0_clk = { 1498 .halt_reg = 0x8004, 1499 .halt_check = BRANCH_HALT, 1500 .clkr = { 1501 .enable_reg = 0x8004, 1502 .enable_mask = BIT(0), 1503 .hw.init = &(struct clk_init_data) { 1504 .name = "disp_cc_mdss_pclk0_clk", 1505 .parent_hws = (const struct clk_hw*[]) { 1506 &disp_cc_mdss_pclk0_clk_src.clkr.hw, 1507 }, 1508 .num_parents = 1, 1509 .flags = CLK_SET_RATE_PARENT, 1510 .ops = &clk_branch2_ops, 1511 }, 1512 }, 1513 }; 1514 1515 static struct clk_branch disp_cc_mdss_pclk1_clk = { 1516 .halt_reg = 0x8008, 1517 .halt_check = BRANCH_HALT, 1518 .clkr = { 1519 .enable_reg = 0x8008, 1520 .enable_mask = BIT(0), 1521 .hw.init = &(struct clk_init_data) { 1522 .name = "disp_cc_mdss_pclk1_clk", 1523 .parent_hws = (const struct clk_hw*[]) { 1524 &disp_cc_mdss_pclk1_clk_src.clkr.hw, 1525 }, 1526 .num_parents = 1, 1527 .flags = CLK_SET_RATE_PARENT, 1528 .ops = &clk_branch2_ops, 1529 }, 1530 }, 1531 }; 1532 1533 static struct clk_branch disp_cc_mdss_rot1_clk = { 1534 .halt_reg = 0xa00c, 1535 .halt_check = BRANCH_HALT, 1536 .clkr = { 1537 .enable_reg = 0xa00c, 1538 .enable_mask = BIT(0), 1539 .hw.init = &(struct clk_init_data) { 1540 .name = "disp_cc_mdss_rot1_clk", 1541 .parent_hws = (const struct clk_hw*[]) { 1542 &disp_cc_mdss_rot_clk_src.clkr.hw, 1543 }, 1544 .num_parents = 1, 1545 .flags = CLK_SET_RATE_PARENT, 1546 .ops = &clk_branch2_ops, 1547 }, 1548 }, 1549 }; 1550 1551 static struct clk_branch disp_cc_mdss_rot_clk = { 1552 .halt_reg = 0x8014, 1553 .halt_check = BRANCH_HALT, 1554 .clkr = { 1555 .enable_reg = 0x8014, 1556 .enable_mask = BIT(0), 1557 .hw.init = &(struct clk_init_data) { 1558 .name = "disp_cc_mdss_rot_clk", 1559 .parent_hws = (const struct clk_hw*[]) { 1560 &disp_cc_mdss_rot_clk_src.clkr.hw, 1561 }, 1562 .num_parents = 1, 1563 .flags = CLK_SET_RATE_PARENT, 1564 .ops = &clk_branch2_ops, 1565 }, 1566 }, 1567 }; 1568 1569 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { 1570 .halt_reg = 0xc00c, 1571 .halt_check = BRANCH_HALT, 1572 .clkr = { 1573 .enable_reg = 0xc00c, 1574 .enable_mask = BIT(0), 1575 .hw.init = &(struct clk_init_data) { 1576 .name = "disp_cc_mdss_rscc_ahb_clk", 1577 .parent_hws = (const struct clk_hw*[]) { 1578 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1579 }, 1580 .num_parents = 1, 1581 .flags = CLK_SET_RATE_PARENT, 1582 .ops = &clk_branch2_ops, 1583 }, 1584 }, 1585 }; 1586 1587 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { 1588 .halt_reg = 0xc008, 1589 .halt_check = BRANCH_HALT, 1590 .clkr = { 1591 .enable_reg = 0xc008, 1592 .enable_mask = BIT(0), 1593 .hw.init = &(struct clk_init_data) { 1594 .name = "disp_cc_mdss_rscc_vsync_clk", 1595 .parent_hws = (const struct clk_hw*[]) { 1596 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1597 }, 1598 .num_parents = 1, 1599 .flags = CLK_SET_RATE_PARENT, 1600 .ops = &clk_branch2_ops, 1601 }, 1602 }, 1603 }; 1604 1605 static struct clk_branch disp_cc_mdss_vsync1_clk = { 1606 .halt_reg = 0xa01c, 1607 .halt_check = BRANCH_HALT, 1608 .clkr = { 1609 .enable_reg = 0xa01c, 1610 .enable_mask = BIT(0), 1611 .hw.init = &(struct clk_init_data) { 1612 .name = "disp_cc_mdss_vsync1_clk", 1613 .parent_hws = (const struct clk_hw*[]) { 1614 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1615 }, 1616 .num_parents = 1, 1617 .flags = CLK_SET_RATE_PARENT, 1618 .ops = &clk_branch2_ops, 1619 }, 1620 }, 1621 }; 1622 1623 static struct clk_branch disp_cc_mdss_vsync_clk = { 1624 .halt_reg = 0x8024, 1625 .halt_check = BRANCH_HALT, 1626 .clkr = { 1627 .enable_reg = 0x8024, 1628 .enable_mask = BIT(0), 1629 .hw.init = &(struct clk_init_data) { 1630 .name = "disp_cc_mdss_vsync_clk", 1631 .parent_hws = (const struct clk_hw*[]) { 1632 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1633 }, 1634 .num_parents = 1, 1635 .flags = CLK_SET_RATE_PARENT, 1636 .ops = &clk_branch2_ops, 1637 }, 1638 }, 1639 }; 1640 1641 static struct clk_branch disp_cc_sleep_clk = { 1642 .halt_reg = 0xe078, 1643 .halt_check = BRANCH_HALT, 1644 .clkr = { 1645 .enable_reg = 0xe078, 1646 .enable_mask = BIT(0), 1647 .hw.init = &(struct clk_init_data) { 1648 .name = "disp_cc_sleep_clk", 1649 .parent_hws = (const struct clk_hw*[]) { 1650 &disp_cc_sleep_clk_src.clkr.hw, 1651 }, 1652 .num_parents = 1, 1653 .flags = CLK_SET_RATE_PARENT, 1654 .ops = &clk_branch2_ops, 1655 }, 1656 }, 1657 }; 1658 1659 static struct gdsc mdss_gdsc = { 1660 .gdscr = 0x9000, 1661 .pd = { 1662 .name = "mdss_gdsc", 1663 }, 1664 .pwrsts = PWRSTS_OFF_ON, 1665 .flags = HW_CTRL | RETAIN_FF_ENABLE, 1666 }; 1667 1668 static struct gdsc mdss_int2_gdsc = { 1669 .gdscr = 0xb000, 1670 .pd = { 1671 .name = "mdss_int2_gdsc", 1672 }, 1673 .pwrsts = PWRSTS_OFF_ON, 1674 .flags = HW_CTRL | RETAIN_FF_ENABLE, 1675 }; 1676 1677 static struct clk_regmap *disp_cc_sm8450_clocks[] = { 1678 [DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr, 1679 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, 1680 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, 1681 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, 1682 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, 1683 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, 1684 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, 1685 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr, 1686 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr, 1687 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr, 1688 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, 1689 [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr, 1690 [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr, 1691 [DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr, 1692 [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr, 1693 [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr, 1694 [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr, 1695 [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr, 1696 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr, 1697 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr, 1698 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr, 1699 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr, 1700 [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = 1701 &disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, 1702 [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr, 1703 [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr, 1704 [DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &disp_cc_mdss_dptx1_crypto_clk.clkr, 1705 [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr, 1706 [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr, 1707 [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr, 1708 [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr, 1709 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr, 1710 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr, 1711 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr, 1712 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr, 1713 [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] = 1714 &disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, 1715 [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr, 1716 [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr, 1717 [DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &disp_cc_mdss_dptx2_crypto_clk.clkr, 1718 [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr, 1719 [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr, 1720 [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr, 1721 [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr, 1722 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr, 1723 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr, 1724 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr, 1725 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr, 1726 [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr, 1727 [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr, 1728 [DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &disp_cc_mdss_dptx3_crypto_clk.clkr, 1729 [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr, 1730 [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr, 1731 [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr, 1732 [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr, 1733 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr, 1734 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr, 1735 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, 1736 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, 1737 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, 1738 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr, 1739 [DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr, 1740 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, 1741 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, 1742 [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr, 1743 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, 1744 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, 1745 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, 1746 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, 1747 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr, 1748 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr, 1749 [DISP_CC_MDSS_ROT1_CLK] = &disp_cc_mdss_rot1_clk.clkr, 1750 [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr, 1751 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr, 1752 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, 1753 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, 1754 [DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr, 1755 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, 1756 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, 1757 [DISP_CC_PLL0] = &disp_cc_pll0.clkr, 1758 [DISP_CC_PLL1] = &disp_cc_pll1.clkr, 1759 [DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr, 1760 [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr, 1761 [DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr, 1762 }; 1763 1764 static const struct qcom_reset_map disp_cc_sm8450_resets[] = { 1765 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 }, 1766 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 }, 1767 [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 }, 1768 }; 1769 1770 static struct gdsc *disp_cc_sm8450_gdscs[] = { 1771 [MDSS_GDSC] = &mdss_gdsc, 1772 [MDSS_INT2_GDSC] = &mdss_int2_gdsc, 1773 }; 1774 1775 static const struct regmap_config disp_cc_sm8450_regmap_config = { 1776 .reg_bits = 32, 1777 .reg_stride = 4, 1778 .val_bits = 32, 1779 .max_register = 0x11008, 1780 .fast_io = true, 1781 }; 1782 1783 static struct qcom_cc_desc disp_cc_sm8450_desc = { 1784 .config = &disp_cc_sm8450_regmap_config, 1785 .clks = disp_cc_sm8450_clocks, 1786 .num_clks = ARRAY_SIZE(disp_cc_sm8450_clocks), 1787 .resets = disp_cc_sm8450_resets, 1788 .num_resets = ARRAY_SIZE(disp_cc_sm8450_resets), 1789 .gdscs = disp_cc_sm8450_gdscs, 1790 .num_gdscs = ARRAY_SIZE(disp_cc_sm8450_gdscs), 1791 }; 1792 1793 static const struct of_device_id disp_cc_sm8450_match_table[] = { 1794 { .compatible = "qcom,sm8450-dispcc" }, 1795 { .compatible = "qcom,sm8475-dispcc" }, 1796 { } 1797 }; 1798 MODULE_DEVICE_TABLE(of, disp_cc_sm8450_match_table); 1799 1800 static int disp_cc_sm8450_probe(struct platform_device *pdev) 1801 { 1802 struct regmap *regmap; 1803 int ret; 1804 1805 ret = devm_pm_runtime_enable(&pdev->dev); 1806 if (ret) 1807 return ret; 1808 1809 ret = pm_runtime_resume_and_get(&pdev->dev); 1810 if (ret) 1811 return ret; 1812 1813 regmap = qcom_cc_map(pdev, &disp_cc_sm8450_desc); 1814 if (IS_ERR(regmap)) { 1815 ret = PTR_ERR(regmap); 1816 goto err_put_rpm; 1817 } 1818 1819 if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-dispcc")) { 1820 /* Update DISPCC PLL0 */ 1821 disp_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; 1822 disp_cc_pll0.clkr.hw.init = &sm8475_disp_cc_pll0_init; 1823 1824 /* Update DISPCC PLL1 */ 1825 disp_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; 1826 disp_cc_pll1.clkr.hw.init = &sm8475_disp_cc_pll1_init; 1827 1828 clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &sm8475_disp_cc_pll0_config); 1829 clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &sm8475_disp_cc_pll1_config); 1830 } else { 1831 clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); 1832 clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); 1833 } 1834 1835 /* Enable clock gating for MDP clocks */ 1836 regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); 1837 1838 /* Keep some clocks always-on */ 1839 qcom_branch_set_clk_en(regmap, 0xe05c); /* DISP_CC_XO_CLK */ 1840 1841 ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8450_desc, regmap); 1842 if (ret) 1843 goto err_put_rpm; 1844 1845 pm_runtime_put(&pdev->dev); 1846 1847 return 0; 1848 1849 err_put_rpm: 1850 pm_runtime_put_sync(&pdev->dev); 1851 1852 return ret; 1853 } 1854 1855 static struct platform_driver disp_cc_sm8450_driver = { 1856 .probe = disp_cc_sm8450_probe, 1857 .driver = { 1858 .name = "disp_cc-sm8450", 1859 .of_match_table = disp_cc_sm8450_match_table, 1860 }, 1861 }; 1862 1863 module_platform_driver(disp_cc_sm8450_driver); 1864 1865 MODULE_DESCRIPTION("QTI DISPCC SM8450 / SM8475 Driver"); 1866 MODULE_LICENSE("GPL"); 1867