1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Ltd. 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/err.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/regmap.h> 13 #include <linux/pm_runtime.h> 14 15 #include <dt-bindings/clock/qcom,sm8450-dispcc.h> 16 17 #include "common.h" 18 #include "clk-alpha-pll.h" 19 #include "clk-branch.h" 20 #include "clk-pll.h" 21 #include "clk-rcg.h" 22 #include "clk-regmap.h" 23 #include "clk-regmap-divider.h" 24 #include "clk-regmap-mux.h" 25 #include "reset.h" 26 #include "gdsc.h" 27 28 /* Need to match the order of clocks in DT binding */ 29 enum { 30 DT_BI_TCXO, 31 DT_BI_TCXO_AO, 32 DT_AHB_CLK, 33 DT_SLEEP_CLK, 34 35 DT_DSI0_PHY_PLL_OUT_BYTECLK, 36 DT_DSI0_PHY_PLL_OUT_DSICLK, 37 DT_DSI1_PHY_PLL_OUT_BYTECLK, 38 DT_DSI1_PHY_PLL_OUT_DSICLK, 39 40 DT_DP0_PHY_PLL_LINK_CLK, 41 DT_DP0_PHY_PLL_VCO_DIV_CLK, 42 DT_DP1_PHY_PLL_LINK_CLK, 43 DT_DP1_PHY_PLL_VCO_DIV_CLK, 44 DT_DP2_PHY_PLL_LINK_CLK, 45 DT_DP2_PHY_PLL_VCO_DIV_CLK, 46 DT_DP3_PHY_PLL_LINK_CLK, 47 DT_DP3_PHY_PLL_VCO_DIV_CLK, 48 }; 49 50 #define DISP_CC_MISC_CMD 0xF000 51 52 enum { 53 P_BI_TCXO, 54 P_DISP_CC_PLL0_OUT_MAIN, 55 P_DISP_CC_PLL1_OUT_EVEN, 56 P_DISP_CC_PLL1_OUT_MAIN, 57 P_DP0_PHY_PLL_LINK_CLK, 58 P_DP0_PHY_PLL_VCO_DIV_CLK, 59 P_DP1_PHY_PLL_LINK_CLK, 60 P_DP1_PHY_PLL_VCO_DIV_CLK, 61 P_DP2_PHY_PLL_LINK_CLK, 62 P_DP2_PHY_PLL_VCO_DIV_CLK, 63 P_DP3_PHY_PLL_LINK_CLK, 64 P_DP3_PHY_PLL_VCO_DIV_CLK, 65 P_DSI0_PHY_PLL_OUT_BYTECLK, 66 P_DSI0_PHY_PLL_OUT_DSICLK, 67 P_DSI1_PHY_PLL_OUT_BYTECLK, 68 P_DSI1_PHY_PLL_OUT_DSICLK, 69 P_SLEEP_CLK, 70 }; 71 72 static const struct pll_vco lucid_evo_vco[] = { 73 { 249600000, 2000000000, 0 }, 74 }; 75 76 static const struct alpha_pll_config disp_cc_pll0_config = { 77 .l = 0xD, 78 .alpha = 0x6492, 79 .config_ctl_val = 0x20485699, 80 .config_ctl_hi_val = 0x00182261, 81 .config_ctl_hi1_val = 0x32AA299C, 82 .user_ctl_val = 0x00000000, 83 .user_ctl_hi_val = 0x00000805, 84 }; 85 86 static const struct alpha_pll_config sm8475_disp_cc_pll0_config = { 87 .l = 0xd, 88 .alpha = 0x6492, 89 .config_ctl_val = 0x20485699, 90 .config_ctl_hi_val = 0x00182261, 91 .config_ctl_hi1_val = 0x82aa299c, 92 .test_ctl_val = 0x00000000, 93 .test_ctl_hi_val = 0x00000003, 94 .test_ctl_hi1_val = 0x00009000, 95 .test_ctl_hi2_val = 0x00000034, 96 .user_ctl_val = 0x00000000, 97 .user_ctl_hi_val = 0x00000005, 98 }; 99 100 static struct clk_init_data sm8475_disp_cc_pll0_init = { 101 .name = "disp_cc_pll0", 102 .parent_data = &(const struct clk_parent_data) { 103 .index = DT_BI_TCXO, 104 }, 105 .num_parents = 1, 106 .ops = &clk_alpha_pll_reset_lucid_ole_ops, 107 }; 108 109 static struct clk_alpha_pll disp_cc_pll0 = { 110 .offset = 0x0, 111 .vco_table = lucid_evo_vco, 112 .num_vco = ARRAY_SIZE(lucid_evo_vco), 113 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 114 .clkr = { 115 .hw.init = &(struct clk_init_data) { 116 .name = "disp_cc_pll0", 117 .parent_data = &(const struct clk_parent_data) { 118 .index = DT_BI_TCXO, 119 }, 120 .num_parents = 1, 121 .ops = &clk_alpha_pll_reset_lucid_evo_ops, 122 }, 123 }, 124 }; 125 126 static const struct alpha_pll_config disp_cc_pll1_config = { 127 .l = 0x1F, 128 .alpha = 0x4000, 129 .config_ctl_val = 0x20485699, 130 .config_ctl_hi_val = 0x00182261, 131 .config_ctl_hi1_val = 0x32AA299C, 132 .user_ctl_val = 0x00000000, 133 .user_ctl_hi_val = 0x00000805, 134 }; 135 136 static const struct alpha_pll_config sm8475_disp_cc_pll1_config = { 137 .l = 0x1f, 138 .alpha = 0x4000, 139 .config_ctl_val = 0x20485699, 140 .config_ctl_hi_val = 0x00182261, 141 .config_ctl_hi1_val = 0x82aa299c, 142 .test_ctl_val = 0x00000000, 143 .test_ctl_hi_val = 0x00000003, 144 .test_ctl_hi1_val = 0x00009000, 145 .test_ctl_hi2_val = 0x00000034, 146 .user_ctl_val = 0x00000000, 147 .user_ctl_hi_val = 0x00000005, 148 }; 149 150 static struct clk_init_data sm8475_disp_cc_pll1_init = { 151 .name = "disp_cc_pll1", 152 .parent_data = &(const struct clk_parent_data) { 153 .index = DT_BI_TCXO, 154 }, 155 .num_parents = 1, 156 .ops = &clk_alpha_pll_reset_lucid_ole_ops, 157 }; 158 159 static struct clk_alpha_pll disp_cc_pll1 = { 160 .offset = 0x1000, 161 .vco_table = lucid_evo_vco, 162 .num_vco = ARRAY_SIZE(lucid_evo_vco), 163 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 164 .clkr = { 165 .hw.init = &(struct clk_init_data) { 166 .name = "disp_cc_pll1", 167 .parent_data = &(const struct clk_parent_data) { 168 .index = DT_BI_TCXO, 169 }, 170 .num_parents = 1, 171 .ops = &clk_alpha_pll_reset_lucid_evo_ops, 172 }, 173 }, 174 }; 175 176 static const struct parent_map disp_cc_parent_map_0[] = { 177 { P_BI_TCXO, 0 }, 178 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 179 { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 }, 180 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, 181 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, 182 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, 183 }; 184 185 static const struct clk_parent_data disp_cc_parent_data_0[] = { 186 { .index = DT_BI_TCXO }, 187 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 188 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK }, 189 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 190 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 191 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 192 }; 193 194 static const struct parent_map disp_cc_parent_map_1[] = { 195 { P_BI_TCXO, 0 }, 196 }; 197 198 static const struct clk_parent_data disp_cc_parent_data_1[] = { 199 { .index = DT_BI_TCXO }, 200 }; 201 202 static const struct clk_parent_data disp_cc_parent_data_1_ao[] = { 203 { .index = DT_BI_TCXO_AO }, 204 }; 205 206 static const struct parent_map disp_cc_parent_map_2[] = { 207 { P_BI_TCXO, 0 }, 208 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 209 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 210 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, 211 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 212 }; 213 214 static const struct clk_parent_data disp_cc_parent_data_2[] = { 215 { .index = DT_BI_TCXO }, 216 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, 217 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 218 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, 219 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 220 }; 221 222 static const struct parent_map disp_cc_parent_map_3[] = { 223 { P_BI_TCXO, 0 }, 224 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 225 { P_DP1_PHY_PLL_LINK_CLK, 2 }, 226 { P_DP2_PHY_PLL_LINK_CLK, 3 }, 227 { P_DP3_PHY_PLL_LINK_CLK, 4 }, 228 }; 229 230 static const struct clk_parent_data disp_cc_parent_data_3[] = { 231 { .index = DT_BI_TCXO }, 232 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 233 { .index = DT_DP1_PHY_PLL_LINK_CLK }, 234 { .index = DT_DP2_PHY_PLL_LINK_CLK }, 235 { .index = DT_DP3_PHY_PLL_LINK_CLK }, 236 }; 237 238 static const struct parent_map disp_cc_parent_map_4[] = { 239 { P_BI_TCXO, 0 }, 240 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 241 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 242 }; 243 244 static const struct clk_parent_data disp_cc_parent_data_4[] = { 245 { .index = DT_BI_TCXO }, 246 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 247 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 248 }; 249 250 static const struct parent_map disp_cc_parent_map_5[] = { 251 { P_BI_TCXO, 0 }, 252 { P_DISP_CC_PLL0_OUT_MAIN, 1 }, 253 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 254 { P_DISP_CC_PLL1_OUT_EVEN, 6 }, 255 }; 256 257 static const struct clk_parent_data disp_cc_parent_data_5[] = { 258 { .index = DT_BI_TCXO }, 259 { .hw = &disp_cc_pll0.clkr.hw }, 260 { .hw = &disp_cc_pll1.clkr.hw }, 261 { .hw = &disp_cc_pll1.clkr.hw }, 262 }; 263 264 static const struct parent_map disp_cc_parent_map_6[] = { 265 { P_BI_TCXO, 0 }, 266 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 267 { P_DISP_CC_PLL1_OUT_EVEN, 6 }, 268 }; 269 270 static const struct clk_parent_data disp_cc_parent_data_6[] = { 271 { .index = DT_BI_TCXO }, 272 { .hw = &disp_cc_pll1.clkr.hw }, 273 { .hw = &disp_cc_pll1.clkr.hw }, 274 }; 275 276 static const struct parent_map disp_cc_parent_map_7[] = { 277 { P_SLEEP_CLK, 0 }, 278 }; 279 280 static const struct clk_parent_data disp_cc_parent_data_7[] = { 281 { .index = DT_SLEEP_CLK }, 282 }; 283 284 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { 285 F(19200000, P_BI_TCXO, 1, 0, 0), 286 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), 287 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), 288 { } 289 }; 290 291 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { 292 .cmd_rcgr = 0x8324, 293 .mnd_width = 0, 294 .hid_width = 5, 295 .parent_map = disp_cc_parent_map_6, 296 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 297 .clkr.hw.init = &(struct clk_init_data) { 298 .name = "disp_cc_mdss_ahb_clk_src", 299 .parent_data = disp_cc_parent_data_6, 300 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 301 .flags = CLK_SET_RATE_PARENT, 302 .ops = &clk_rcg2_shared_ops, 303 }, 304 }; 305 306 static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = { 307 F(19200000, P_BI_TCXO, 1, 0, 0), 308 { } 309 }; 310 311 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { 312 .cmd_rcgr = 0x8134, 313 .mnd_width = 0, 314 .hid_width = 5, 315 .parent_map = disp_cc_parent_map_2, 316 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 317 .clkr.hw.init = &(struct clk_init_data) { 318 .name = "disp_cc_mdss_byte0_clk_src", 319 .parent_data = disp_cc_parent_data_2, 320 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 321 .flags = CLK_SET_RATE_PARENT, 322 .ops = &clk_byte2_ops, 323 }, 324 }; 325 326 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { 327 .cmd_rcgr = 0x8150, 328 .mnd_width = 0, 329 .hid_width = 5, 330 .parent_map = disp_cc_parent_map_2, 331 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 332 .clkr.hw.init = &(struct clk_init_data) { 333 .name = "disp_cc_mdss_byte1_clk_src", 334 .parent_data = disp_cc_parent_data_2, 335 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 336 .flags = CLK_SET_RATE_PARENT, 337 .ops = &clk_byte2_ops, 338 }, 339 }; 340 341 static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { 342 .cmd_rcgr = 0x81ec, 343 .mnd_width = 0, 344 .hid_width = 5, 345 .parent_map = disp_cc_parent_map_1, 346 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 347 .clkr.hw.init = &(struct clk_init_data) { 348 .name = "disp_cc_mdss_dptx0_aux_clk_src", 349 .parent_data = disp_cc_parent_data_1, 350 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 351 .flags = CLK_SET_RATE_PARENT, 352 .ops = &clk_rcg2_ops, 353 }, 354 }; 355 356 static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { 357 .cmd_rcgr = 0x819c, 358 .mnd_width = 0, 359 .hid_width = 5, 360 .parent_map = disp_cc_parent_map_3, 361 .clkr.hw.init = &(struct clk_init_data) { 362 .name = "disp_cc_mdss_dptx0_link_clk_src", 363 .parent_data = disp_cc_parent_data_3, 364 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 365 .flags = CLK_SET_RATE_PARENT, 366 .ops = &clk_byte2_ops, 367 }, 368 }; 369 370 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = { 371 .cmd_rcgr = 0x81bc, 372 .mnd_width = 16, 373 .hid_width = 5, 374 .parent_map = disp_cc_parent_map_0, 375 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 376 .clkr.hw.init = &(struct clk_init_data) { 377 .name = "disp_cc_mdss_dptx0_pixel0_clk_src", 378 .parent_data = disp_cc_parent_data_0, 379 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 380 .flags = CLK_SET_RATE_PARENT, 381 .ops = &clk_dp_ops, 382 }, 383 }; 384 385 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = { 386 .cmd_rcgr = 0x81d4, 387 .mnd_width = 16, 388 .hid_width = 5, 389 .parent_map = disp_cc_parent_map_0, 390 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 391 .clkr.hw.init = &(struct clk_init_data) { 392 .name = "disp_cc_mdss_dptx0_pixel1_clk_src", 393 .parent_data = disp_cc_parent_data_0, 394 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 395 .flags = CLK_SET_RATE_PARENT, 396 .ops = &clk_dp_ops, 397 }, 398 }; 399 400 static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { 401 .cmd_rcgr = 0x8254, 402 .mnd_width = 0, 403 .hid_width = 5, 404 .parent_map = disp_cc_parent_map_1, 405 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 406 .clkr.hw.init = &(struct clk_init_data) { 407 .name = "disp_cc_mdss_dptx1_aux_clk_src", 408 .parent_data = disp_cc_parent_data_1, 409 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 410 .flags = CLK_SET_RATE_PARENT, 411 .ops = &clk_rcg2_ops, 412 }, 413 }; 414 415 static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { 416 .cmd_rcgr = 0x8234, 417 .mnd_width = 0, 418 .hid_width = 5, 419 .parent_map = disp_cc_parent_map_3, 420 .clkr.hw.init = &(struct clk_init_data) { 421 .name = "disp_cc_mdss_dptx1_link_clk_src", 422 .parent_data = disp_cc_parent_data_3, 423 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 424 .flags = CLK_SET_RATE_PARENT, 425 .ops = &clk_byte2_ops, 426 }, 427 }; 428 429 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = { 430 .cmd_rcgr = 0x8204, 431 .mnd_width = 16, 432 .hid_width = 5, 433 .parent_map = disp_cc_parent_map_0, 434 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 435 .clkr.hw.init = &(struct clk_init_data) { 436 .name = "disp_cc_mdss_dptx1_pixel0_clk_src", 437 .parent_data = disp_cc_parent_data_0, 438 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 439 .flags = CLK_SET_RATE_PARENT, 440 .ops = &clk_dp_ops, 441 }, 442 }; 443 444 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = { 445 .cmd_rcgr = 0x821c, 446 .mnd_width = 16, 447 .hid_width = 5, 448 .parent_map = disp_cc_parent_map_0, 449 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 450 .clkr.hw.init = &(struct clk_init_data) { 451 .name = "disp_cc_mdss_dptx1_pixel1_clk_src", 452 .parent_data = disp_cc_parent_data_0, 453 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 454 .flags = CLK_SET_RATE_PARENT, 455 .ops = &clk_dp_ops, 456 }, 457 }; 458 459 static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = { 460 .cmd_rcgr = 0x82bc, 461 .mnd_width = 0, 462 .hid_width = 5, 463 .parent_map = disp_cc_parent_map_1, 464 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 465 .clkr.hw.init = &(struct clk_init_data) { 466 .name = "disp_cc_mdss_dptx2_aux_clk_src", 467 .parent_data = disp_cc_parent_data_1, 468 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 469 .flags = CLK_SET_RATE_PARENT, 470 .ops = &clk_rcg2_ops, 471 }, 472 }; 473 474 static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { 475 .cmd_rcgr = 0x826c, 476 .mnd_width = 0, 477 .hid_width = 5, 478 .parent_map = disp_cc_parent_map_3, 479 .clkr.hw.init = &(struct clk_init_data) { 480 .name = "disp_cc_mdss_dptx2_link_clk_src", 481 .parent_data = disp_cc_parent_data_3, 482 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 483 .flags = CLK_SET_RATE_PARENT, 484 .ops = &clk_byte2_ops, 485 }, 486 }; 487 488 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = { 489 .cmd_rcgr = 0x828c, 490 .mnd_width = 16, 491 .hid_width = 5, 492 .parent_map = disp_cc_parent_map_0, 493 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 494 .clkr.hw.init = &(struct clk_init_data) { 495 .name = "disp_cc_mdss_dptx2_pixel0_clk_src", 496 .parent_data = disp_cc_parent_data_0, 497 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 498 .flags = CLK_SET_RATE_PARENT, 499 .ops = &clk_dp_ops, 500 }, 501 }; 502 503 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = { 504 .cmd_rcgr = 0x82a4, 505 .mnd_width = 16, 506 .hid_width = 5, 507 .parent_map = disp_cc_parent_map_0, 508 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 509 .clkr.hw.init = &(struct clk_init_data) { 510 .name = "disp_cc_mdss_dptx2_pixel1_clk_src", 511 .parent_data = disp_cc_parent_data_0, 512 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 513 .flags = CLK_SET_RATE_PARENT, 514 .ops = &clk_dp_ops, 515 }, 516 }; 517 518 static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = { 519 .cmd_rcgr = 0x8308, 520 .mnd_width = 0, 521 .hid_width = 5, 522 .parent_map = disp_cc_parent_map_1, 523 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 524 .clkr.hw.init = &(struct clk_init_data) { 525 .name = "disp_cc_mdss_dptx3_aux_clk_src", 526 .parent_data = disp_cc_parent_data_1, 527 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 528 .flags = CLK_SET_RATE_PARENT, 529 .ops = &clk_rcg2_ops, 530 }, 531 }; 532 533 static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { 534 .cmd_rcgr = 0x82ec, 535 .mnd_width = 0, 536 .hid_width = 5, 537 .parent_map = disp_cc_parent_map_3, 538 .clkr.hw.init = &(struct clk_init_data) { 539 .name = "disp_cc_mdss_dptx3_link_clk_src", 540 .parent_data = disp_cc_parent_data_3, 541 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 542 .flags = CLK_SET_RATE_PARENT, 543 .ops = &clk_byte2_ops, 544 }, 545 }; 546 547 static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = { 548 .cmd_rcgr = 0x82d4, 549 .mnd_width = 16, 550 .hid_width = 5, 551 .parent_map = disp_cc_parent_map_0, 552 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 553 .clkr.hw.init = &(struct clk_init_data) { 554 .name = "disp_cc_mdss_dptx3_pixel0_clk_src", 555 .parent_data = disp_cc_parent_data_0, 556 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 557 .flags = CLK_SET_RATE_PARENT, 558 .ops = &clk_dp_ops, 559 }, 560 }; 561 562 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { 563 .cmd_rcgr = 0x816c, 564 .mnd_width = 0, 565 .hid_width = 5, 566 .parent_map = disp_cc_parent_map_4, 567 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 568 .clkr.hw.init = &(struct clk_init_data) { 569 .name = "disp_cc_mdss_esc0_clk_src", 570 .parent_data = disp_cc_parent_data_4, 571 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 572 .flags = CLK_SET_RATE_PARENT, 573 .ops = &clk_rcg2_ops, 574 }, 575 }; 576 577 static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { 578 .cmd_rcgr = 0x8184, 579 .mnd_width = 0, 580 .hid_width = 5, 581 .parent_map = disp_cc_parent_map_4, 582 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 583 .clkr.hw.init = &(struct clk_init_data) { 584 .name = "disp_cc_mdss_esc1_clk_src", 585 .parent_data = disp_cc_parent_data_4, 586 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 587 .flags = CLK_SET_RATE_PARENT, 588 .ops = &clk_rcg2_ops, 589 }, 590 }; 591 592 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { 593 F(19200000, P_BI_TCXO, 1, 0, 0), 594 F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 595 F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 596 F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 597 F(172000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 598 F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 599 F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 600 F(375000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 601 F(500000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 602 { } 603 }; 604 605 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { 606 .cmd_rcgr = 0x80ec, 607 .mnd_width = 0, 608 .hid_width = 5, 609 .parent_map = disp_cc_parent_map_5, 610 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 611 .clkr.hw.init = &(struct clk_init_data) { 612 .name = "disp_cc_mdss_mdp_clk_src", 613 .parent_data = disp_cc_parent_data_5, 614 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 615 .flags = CLK_SET_RATE_PARENT, 616 .ops = &clk_rcg2_shared_ops, 617 }, 618 }; 619 620 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { 621 .cmd_rcgr = 0x80bc, 622 .mnd_width = 8, 623 .hid_width = 5, 624 .parent_map = disp_cc_parent_map_2, 625 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 626 .clkr.hw.init = &(struct clk_init_data) { 627 .name = "disp_cc_mdss_pclk0_clk_src", 628 .parent_data = disp_cc_parent_data_2, 629 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 630 .flags = CLK_SET_RATE_PARENT, 631 .ops = &clk_pixel_ops, 632 }, 633 }; 634 635 static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { 636 .cmd_rcgr = 0x80d4, 637 .mnd_width = 8, 638 .hid_width = 5, 639 .parent_map = disp_cc_parent_map_2, 640 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 641 .clkr.hw.init = &(struct clk_init_data) { 642 .name = "disp_cc_mdss_pclk1_clk_src", 643 .parent_data = disp_cc_parent_data_2, 644 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 645 .flags = CLK_SET_RATE_PARENT, 646 .ops = &clk_pixel_ops, 647 }, 648 }; 649 650 static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = { 651 F(19200000, P_BI_TCXO, 1, 0, 0), 652 F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0), 653 F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0), 654 F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0), 655 { } 656 }; 657 658 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { 659 .cmd_rcgr = 0x8104, 660 .mnd_width = 0, 661 .hid_width = 5, 662 .parent_map = disp_cc_parent_map_5, 663 .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, 664 .clkr.hw.init = &(struct clk_init_data) { 665 .name = "disp_cc_mdss_rot_clk_src", 666 .parent_data = disp_cc_parent_data_5, 667 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 668 .flags = CLK_SET_RATE_PARENT, 669 .ops = &clk_rcg2_shared_ops, 670 }, 671 }; 672 673 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { 674 .cmd_rcgr = 0x811c, 675 .mnd_width = 0, 676 .hid_width = 5, 677 .parent_map = disp_cc_parent_map_1, 678 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 679 .clkr.hw.init = &(struct clk_init_data) { 680 .name = "disp_cc_mdss_vsync_clk_src", 681 .parent_data = disp_cc_parent_data_1, 682 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 683 .flags = CLK_SET_RATE_PARENT, 684 .ops = &clk_rcg2_ops, 685 }, 686 }; 687 688 static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = { 689 F(32000, P_SLEEP_CLK, 1, 0, 0), 690 { } 691 }; 692 693 static struct clk_rcg2 disp_cc_sleep_clk_src = { 694 .cmd_rcgr = 0xe060, 695 .mnd_width = 0, 696 .hid_width = 5, 697 .parent_map = disp_cc_parent_map_7, 698 .freq_tbl = ftbl_disp_cc_sleep_clk_src, 699 .clkr.hw.init = &(struct clk_init_data) { 700 .name = "disp_cc_sleep_clk_src", 701 .parent_data = disp_cc_parent_data_7, 702 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), 703 .flags = CLK_SET_RATE_PARENT, 704 .ops = &clk_rcg2_ops, 705 }, 706 }; 707 708 static struct clk_rcg2 disp_cc_xo_clk_src = { 709 .cmd_rcgr = 0xe044, 710 .mnd_width = 0, 711 .hid_width = 5, 712 .parent_map = disp_cc_parent_map_1, 713 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 714 .clkr.hw.init = &(struct clk_init_data) { 715 .name = "disp_cc_xo_clk_src", 716 .parent_data = disp_cc_parent_data_1_ao, 717 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1_ao), 718 .flags = CLK_SET_RATE_PARENT, 719 .ops = &clk_rcg2_ops, 720 }, 721 }; 722 723 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { 724 .reg = 0x814c, 725 .shift = 0, 726 .width = 4, 727 .clkr.hw.init = &(struct clk_init_data) { 728 .name = "disp_cc_mdss_byte0_div_clk_src", 729 .parent_hws = (const struct clk_hw*[]) { 730 &disp_cc_mdss_byte0_clk_src.clkr.hw, 731 }, 732 .num_parents = 1, 733 .ops = &clk_regmap_div_ops, 734 }, 735 }; 736 737 static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { 738 .reg = 0x8168, 739 .shift = 0, 740 .width = 4, 741 .clkr.hw.init = &(struct clk_init_data) { 742 .name = "disp_cc_mdss_byte1_div_clk_src", 743 .parent_hws = (const struct clk_hw*[]) { 744 &disp_cc_mdss_byte1_clk_src.clkr.hw, 745 }, 746 .num_parents = 1, 747 .ops = &clk_regmap_div_ops, 748 }, 749 }; 750 751 static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = { 752 .reg = 0x81b4, 753 .shift = 0, 754 .width = 4, 755 .clkr.hw.init = &(struct clk_init_data) { 756 .name = "disp_cc_mdss_dptx0_link_div_clk_src", 757 .parent_hws = (const struct clk_hw*[]) { 758 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 759 }, 760 .num_parents = 1, 761 .flags = CLK_SET_RATE_PARENT, 762 .ops = &clk_regmap_div_ro_ops, 763 }, 764 }; 765 766 static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = { 767 .reg = 0x824c, 768 .shift = 0, 769 .width = 4, 770 .clkr.hw.init = &(struct clk_init_data) { 771 .name = "disp_cc_mdss_dptx1_link_div_clk_src", 772 .parent_hws = (const struct clk_hw*[]) { 773 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 774 }, 775 .num_parents = 1, 776 .flags = CLK_SET_RATE_PARENT, 777 .ops = &clk_regmap_div_ro_ops, 778 }, 779 }; 780 781 static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = { 782 .reg = 0x8284, 783 .shift = 0, 784 .width = 4, 785 .clkr.hw.init = &(struct clk_init_data) { 786 .name = "disp_cc_mdss_dptx2_link_div_clk_src", 787 .parent_hws = (const struct clk_hw*[]) { 788 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 789 }, 790 .num_parents = 1, 791 .flags = CLK_SET_RATE_PARENT, 792 .ops = &clk_regmap_div_ro_ops, 793 }, 794 }; 795 796 static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = { 797 .reg = 0x8304, 798 .shift = 0, 799 .width = 4, 800 .clkr.hw.init = &(struct clk_init_data) { 801 .name = "disp_cc_mdss_dptx3_link_div_clk_src", 802 .parent_hws = (const struct clk_hw*[]) { 803 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 804 }, 805 .num_parents = 1, 806 .flags = CLK_SET_RATE_PARENT, 807 .ops = &clk_regmap_div_ro_ops, 808 }, 809 }; 810 811 static struct clk_branch disp_cc_mdss_ahb1_clk = { 812 .halt_reg = 0xa020, 813 .halt_check = BRANCH_HALT, 814 .clkr = { 815 .enable_reg = 0xa020, 816 .enable_mask = BIT(0), 817 .hw.init = &(struct clk_init_data) { 818 .name = "disp_cc_mdss_ahb1_clk", 819 .parent_hws = (const struct clk_hw*[]) { 820 &disp_cc_mdss_ahb_clk_src.clkr.hw, 821 }, 822 .num_parents = 1, 823 .flags = CLK_SET_RATE_PARENT, 824 .ops = &clk_branch2_ops, 825 }, 826 }, 827 }; 828 829 static struct clk_branch disp_cc_mdss_ahb_clk = { 830 .halt_reg = 0x80a4, 831 .halt_check = BRANCH_HALT, 832 .clkr = { 833 .enable_reg = 0x80a4, 834 .enable_mask = BIT(0), 835 .hw.init = &(struct clk_init_data) { 836 .name = "disp_cc_mdss_ahb_clk", 837 .parent_hws = (const struct clk_hw*[]) { 838 &disp_cc_mdss_ahb_clk_src.clkr.hw, 839 }, 840 .num_parents = 1, 841 .flags = CLK_SET_RATE_PARENT, 842 .ops = &clk_branch2_ops, 843 }, 844 }, 845 }; 846 847 static struct clk_branch disp_cc_mdss_byte0_clk = { 848 .halt_reg = 0x8028, 849 .halt_check = BRANCH_HALT, 850 .clkr = { 851 .enable_reg = 0x8028, 852 .enable_mask = BIT(0), 853 .hw.init = &(struct clk_init_data) { 854 .name = "disp_cc_mdss_byte0_clk", 855 .parent_hws = (const struct clk_hw*[]) { 856 &disp_cc_mdss_byte0_clk_src.clkr.hw, 857 }, 858 .num_parents = 1, 859 .flags = CLK_SET_RATE_PARENT, 860 .ops = &clk_branch2_ops, 861 }, 862 }, 863 }; 864 865 static struct clk_branch disp_cc_mdss_byte0_intf_clk = { 866 .halt_reg = 0x802c, 867 .halt_check = BRANCH_HALT, 868 .clkr = { 869 .enable_reg = 0x802c, 870 .enable_mask = BIT(0), 871 .hw.init = &(struct clk_init_data) { 872 .name = "disp_cc_mdss_byte0_intf_clk", 873 .parent_hws = (const struct clk_hw*[]) { 874 &disp_cc_mdss_byte0_div_clk_src.clkr.hw, 875 }, 876 .num_parents = 1, 877 .flags = CLK_SET_RATE_PARENT, 878 .ops = &clk_branch2_ops, 879 }, 880 }, 881 }; 882 883 static struct clk_branch disp_cc_mdss_byte1_clk = { 884 .halt_reg = 0x8030, 885 .halt_check = BRANCH_HALT, 886 .clkr = { 887 .enable_reg = 0x8030, 888 .enable_mask = BIT(0), 889 .hw.init = &(struct clk_init_data) { 890 .name = "disp_cc_mdss_byte1_clk", 891 .parent_hws = (const struct clk_hw*[]) { 892 &disp_cc_mdss_byte1_clk_src.clkr.hw, 893 }, 894 .num_parents = 1, 895 .flags = CLK_SET_RATE_PARENT, 896 .ops = &clk_branch2_ops, 897 }, 898 }, 899 }; 900 901 static struct clk_branch disp_cc_mdss_byte1_intf_clk = { 902 .halt_reg = 0x8034, 903 .halt_check = BRANCH_HALT, 904 .clkr = { 905 .enable_reg = 0x8034, 906 .enable_mask = BIT(0), 907 .hw.init = &(struct clk_init_data) { 908 .name = "disp_cc_mdss_byte1_intf_clk", 909 .parent_hws = (const struct clk_hw*[]) { 910 &disp_cc_mdss_byte1_div_clk_src.clkr.hw, 911 }, 912 .num_parents = 1, 913 .flags = CLK_SET_RATE_PARENT, 914 .ops = &clk_branch2_ops, 915 }, 916 }, 917 }; 918 919 static struct clk_branch disp_cc_mdss_dptx0_aux_clk = { 920 .halt_reg = 0x8058, 921 .halt_check = BRANCH_HALT, 922 .clkr = { 923 .enable_reg = 0x8058, 924 .enable_mask = BIT(0), 925 .hw.init = &(struct clk_init_data) { 926 .name = "disp_cc_mdss_dptx0_aux_clk", 927 .parent_hws = (const struct clk_hw*[]) { 928 &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, 929 }, 930 .num_parents = 1, 931 .flags = CLK_SET_RATE_PARENT, 932 .ops = &clk_branch2_ops, 933 }, 934 }, 935 }; 936 937 static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = { 938 .halt_reg = 0x804c, 939 .halt_check = BRANCH_HALT, 940 .clkr = { 941 .enable_reg = 0x804c, 942 .enable_mask = BIT(0), 943 .hw.init = &(struct clk_init_data) { 944 .name = "disp_cc_mdss_dptx0_crypto_clk", 945 .parent_hws = (const struct clk_hw*[]) { 946 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 947 }, 948 .num_parents = 1, 949 .flags = CLK_SET_RATE_PARENT, 950 .ops = &clk_branch2_ops, 951 }, 952 }, 953 }; 954 955 static struct clk_branch disp_cc_mdss_dptx0_link_clk = { 956 .halt_reg = 0x8040, 957 .halt_check = BRANCH_HALT, 958 .clkr = { 959 .enable_reg = 0x8040, 960 .enable_mask = BIT(0), 961 .hw.init = &(struct clk_init_data) { 962 .name = "disp_cc_mdss_dptx0_link_clk", 963 .parent_hws = (const struct clk_hw*[]) { 964 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 965 }, 966 .num_parents = 1, 967 .flags = CLK_SET_RATE_PARENT, 968 .ops = &clk_branch2_ops, 969 }, 970 }, 971 }; 972 973 static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = { 974 .halt_reg = 0x8048, 975 .halt_check = BRANCH_HALT, 976 .clkr = { 977 .enable_reg = 0x8048, 978 .enable_mask = BIT(0), 979 .hw.init = &(struct clk_init_data) { 980 .name = "disp_cc_mdss_dptx0_link_intf_clk", 981 .parent_hws = (const struct clk_hw*[]) { 982 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 983 }, 984 .num_parents = 1, 985 .flags = CLK_SET_RATE_PARENT, 986 .ops = &clk_branch2_ops, 987 }, 988 }, 989 }; 990 991 static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = { 992 .halt_reg = 0x8050, 993 .halt_check = BRANCH_HALT, 994 .clkr = { 995 .enable_reg = 0x8050, 996 .enable_mask = BIT(0), 997 .hw.init = &(struct clk_init_data) { 998 .name = "disp_cc_mdss_dptx0_pixel0_clk", 999 .parent_hws = (const struct clk_hw*[]) { 1000 &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, 1001 }, 1002 .num_parents = 1, 1003 .flags = CLK_SET_RATE_PARENT, 1004 .ops = &clk_branch2_ops, 1005 }, 1006 }, 1007 }; 1008 1009 static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = { 1010 .halt_reg = 0x8054, 1011 .halt_check = BRANCH_HALT, 1012 .clkr = { 1013 .enable_reg = 0x8054, 1014 .enable_mask = BIT(0), 1015 .hw.init = &(struct clk_init_data) { 1016 .name = "disp_cc_mdss_dptx0_pixel1_clk", 1017 .parent_hws = (const struct clk_hw*[]) { 1018 &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, 1019 }, 1020 .num_parents = 1, 1021 .flags = CLK_SET_RATE_PARENT, 1022 .ops = &clk_branch2_ops, 1023 }, 1024 }, 1025 }; 1026 1027 static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = { 1028 .halt_reg = 0x8044, 1029 .halt_check = BRANCH_HALT, 1030 .clkr = { 1031 .enable_reg = 0x8044, 1032 .enable_mask = BIT(0), 1033 .hw.init = &(struct clk_init_data) { 1034 .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk", 1035 .parent_hws = (const struct clk_hw*[]) { 1036 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1037 }, 1038 .num_parents = 1, 1039 .flags = CLK_SET_RATE_PARENT, 1040 .ops = &clk_branch2_ops, 1041 }, 1042 }, 1043 }; 1044 1045 static struct clk_branch disp_cc_mdss_dptx1_aux_clk = { 1046 .halt_reg = 0x8074, 1047 .halt_check = BRANCH_HALT, 1048 .clkr = { 1049 .enable_reg = 0x8074, 1050 .enable_mask = BIT(0), 1051 .hw.init = &(struct clk_init_data) { 1052 .name = "disp_cc_mdss_dptx1_aux_clk", 1053 .parent_hws = (const struct clk_hw*[]) { 1054 &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, 1055 }, 1056 .num_parents = 1, 1057 .flags = CLK_SET_RATE_PARENT, 1058 .ops = &clk_branch2_ops, 1059 }, 1060 }, 1061 }; 1062 1063 static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = { 1064 .halt_reg = 0x8070, 1065 .halt_check = BRANCH_HALT, 1066 .clkr = { 1067 .enable_reg = 0x8070, 1068 .enable_mask = BIT(0), 1069 .hw.init = &(struct clk_init_data) { 1070 .name = "disp_cc_mdss_dptx1_crypto_clk", 1071 .parent_hws = (const struct clk_hw*[]) { 1072 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 1073 }, 1074 .num_parents = 1, 1075 .flags = CLK_SET_RATE_PARENT, 1076 .ops = &clk_branch2_ops, 1077 }, 1078 }, 1079 }; 1080 1081 static struct clk_branch disp_cc_mdss_dptx1_link_clk = { 1082 .halt_reg = 0x8064, 1083 .halt_check = BRANCH_HALT, 1084 .clkr = { 1085 .enable_reg = 0x8064, 1086 .enable_mask = BIT(0), 1087 .hw.init = &(struct clk_init_data) { 1088 .name = "disp_cc_mdss_dptx1_link_clk", 1089 .parent_hws = (const struct clk_hw*[]) { 1090 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 1091 }, 1092 .num_parents = 1, 1093 .flags = CLK_SET_RATE_PARENT, 1094 .ops = &clk_branch2_ops, 1095 }, 1096 }, 1097 }; 1098 1099 static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = { 1100 .halt_reg = 0x806c, 1101 .halt_check = BRANCH_HALT, 1102 .clkr = { 1103 .enable_reg = 0x806c, 1104 .enable_mask = BIT(0), 1105 .hw.init = &(struct clk_init_data) { 1106 .name = "disp_cc_mdss_dptx1_link_intf_clk", 1107 .parent_hws = (const struct clk_hw*[]) { 1108 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1109 }, 1110 .num_parents = 1, 1111 .flags = CLK_SET_RATE_PARENT, 1112 .ops = &clk_branch2_ops, 1113 }, 1114 }, 1115 }; 1116 1117 static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = { 1118 .halt_reg = 0x805c, 1119 .halt_check = BRANCH_HALT, 1120 .clkr = { 1121 .enable_reg = 0x805c, 1122 .enable_mask = BIT(0), 1123 .hw.init = &(struct clk_init_data) { 1124 .name = "disp_cc_mdss_dptx1_pixel0_clk", 1125 .parent_hws = (const struct clk_hw*[]) { 1126 &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, 1127 }, 1128 .num_parents = 1, 1129 .flags = CLK_SET_RATE_PARENT, 1130 .ops = &clk_branch2_ops, 1131 }, 1132 }, 1133 }; 1134 1135 static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = { 1136 .halt_reg = 0x8060, 1137 .halt_check = BRANCH_HALT, 1138 .clkr = { 1139 .enable_reg = 0x8060, 1140 .enable_mask = BIT(0), 1141 .hw.init = &(struct clk_init_data) { 1142 .name = "disp_cc_mdss_dptx1_pixel1_clk", 1143 .parent_hws = (const struct clk_hw*[]) { 1144 &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, 1145 }, 1146 .num_parents = 1, 1147 .flags = CLK_SET_RATE_PARENT, 1148 .ops = &clk_branch2_ops, 1149 }, 1150 }, 1151 }; 1152 1153 static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = { 1154 .halt_reg = 0x8068, 1155 .halt_check = BRANCH_HALT, 1156 .clkr = { 1157 .enable_reg = 0x8068, 1158 .enable_mask = BIT(0), 1159 .hw.init = &(struct clk_init_data) { 1160 .name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk", 1161 .parent_hws = (const struct clk_hw*[]) { 1162 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1163 }, 1164 .num_parents = 1, 1165 .flags = CLK_SET_RATE_PARENT, 1166 .ops = &clk_branch2_ops, 1167 }, 1168 }, 1169 }; 1170 1171 static struct clk_branch disp_cc_mdss_dptx2_aux_clk = { 1172 .halt_reg = 0x808c, 1173 .halt_check = BRANCH_HALT, 1174 .clkr = { 1175 .enable_reg = 0x808c, 1176 .enable_mask = BIT(0), 1177 .hw.init = &(struct clk_init_data) { 1178 .name = "disp_cc_mdss_dptx2_aux_clk", 1179 .parent_hws = (const struct clk_hw*[]) { 1180 &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw, 1181 }, 1182 .num_parents = 1, 1183 .flags = CLK_SET_RATE_PARENT, 1184 .ops = &clk_branch2_ops, 1185 }, 1186 }, 1187 }; 1188 1189 static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = { 1190 .halt_reg = 0x8088, 1191 .halt_check = BRANCH_HALT, 1192 .clkr = { 1193 .enable_reg = 0x8088, 1194 .enable_mask = BIT(0), 1195 .hw.init = &(struct clk_init_data) { 1196 .name = "disp_cc_mdss_dptx2_crypto_clk", 1197 .parent_hws = (const struct clk_hw*[]) { 1198 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 1199 }, 1200 .num_parents = 1, 1201 .flags = CLK_SET_RATE_PARENT, 1202 .ops = &clk_branch2_ops, 1203 }, 1204 }, 1205 }; 1206 1207 static struct clk_branch disp_cc_mdss_dptx2_link_clk = { 1208 .halt_reg = 0x8080, 1209 .halt_check = BRANCH_HALT, 1210 .clkr = { 1211 .enable_reg = 0x8080, 1212 .enable_mask = BIT(0), 1213 .hw.init = &(struct clk_init_data) { 1214 .name = "disp_cc_mdss_dptx2_link_clk", 1215 .parent_hws = (const struct clk_hw*[]) { 1216 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 1217 }, 1218 .num_parents = 1, 1219 .flags = CLK_SET_RATE_PARENT, 1220 .ops = &clk_branch2_ops, 1221 }, 1222 }, 1223 }; 1224 1225 static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = { 1226 .halt_reg = 0x8084, 1227 .halt_check = BRANCH_HALT, 1228 .clkr = { 1229 .enable_reg = 0x8084, 1230 .enable_mask = BIT(0), 1231 .hw.init = &(struct clk_init_data) { 1232 .name = "disp_cc_mdss_dptx2_link_intf_clk", 1233 .parent_hws = (const struct clk_hw*[]) { 1234 &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, 1235 }, 1236 .num_parents = 1, 1237 .flags = CLK_SET_RATE_PARENT, 1238 .ops = &clk_branch2_ops, 1239 }, 1240 }, 1241 }; 1242 1243 static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = { 1244 .halt_reg = 0x8078, 1245 .halt_check = BRANCH_HALT, 1246 .clkr = { 1247 .enable_reg = 0x8078, 1248 .enable_mask = BIT(0), 1249 .hw.init = &(struct clk_init_data) { 1250 .name = "disp_cc_mdss_dptx2_pixel0_clk", 1251 .parent_hws = (const struct clk_hw*[]) { 1252 &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, 1253 }, 1254 .num_parents = 1, 1255 .flags = CLK_SET_RATE_PARENT, 1256 .ops = &clk_branch2_ops, 1257 }, 1258 }, 1259 }; 1260 1261 static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = { 1262 .halt_reg = 0x807c, 1263 .halt_check = BRANCH_HALT, 1264 .clkr = { 1265 .enable_reg = 0x807c, 1266 .enable_mask = BIT(0), 1267 .hw.init = &(struct clk_init_data) { 1268 .name = "disp_cc_mdss_dptx2_pixel1_clk", 1269 .parent_hws = (const struct clk_hw*[]) { 1270 &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, 1271 }, 1272 .num_parents = 1, 1273 .flags = CLK_SET_RATE_PARENT, 1274 .ops = &clk_branch2_ops, 1275 }, 1276 }, 1277 }; 1278 1279 static struct clk_branch disp_cc_mdss_dptx3_aux_clk = { 1280 .halt_reg = 0x809c, 1281 .halt_check = BRANCH_HALT, 1282 .clkr = { 1283 .enable_reg = 0x809c, 1284 .enable_mask = BIT(0), 1285 .hw.init = &(struct clk_init_data) { 1286 .name = "disp_cc_mdss_dptx3_aux_clk", 1287 .parent_hws = (const struct clk_hw*[]) { 1288 &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw, 1289 }, 1290 .num_parents = 1, 1291 .flags = CLK_SET_RATE_PARENT, 1292 .ops = &clk_branch2_ops, 1293 }, 1294 }, 1295 }; 1296 1297 static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = { 1298 .halt_reg = 0x80a0, 1299 .halt_check = BRANCH_HALT, 1300 .clkr = { 1301 .enable_reg = 0x80a0, 1302 .enable_mask = BIT(0), 1303 .hw.init = &(struct clk_init_data) { 1304 .name = "disp_cc_mdss_dptx3_crypto_clk", 1305 .parent_hws = (const struct clk_hw*[]) { 1306 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 1307 }, 1308 .num_parents = 1, 1309 .flags = CLK_SET_RATE_PARENT, 1310 .ops = &clk_branch2_ops, 1311 }, 1312 }, 1313 }; 1314 1315 static struct clk_branch disp_cc_mdss_dptx3_link_clk = { 1316 .halt_reg = 0x8094, 1317 .halt_check = BRANCH_HALT, 1318 .clkr = { 1319 .enable_reg = 0x8094, 1320 .enable_mask = BIT(0), 1321 .hw.init = &(struct clk_init_data) { 1322 .name = "disp_cc_mdss_dptx3_link_clk", 1323 .parent_hws = (const struct clk_hw*[]) { 1324 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 1325 }, 1326 .num_parents = 1, 1327 .flags = CLK_SET_RATE_PARENT, 1328 .ops = &clk_branch2_ops, 1329 }, 1330 }, 1331 }; 1332 1333 static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = { 1334 .halt_reg = 0x8098, 1335 .halt_check = BRANCH_HALT, 1336 .clkr = { 1337 .enable_reg = 0x8098, 1338 .enable_mask = BIT(0), 1339 .hw.init = &(struct clk_init_data) { 1340 .name = "disp_cc_mdss_dptx3_link_intf_clk", 1341 .parent_hws = (const struct clk_hw*[]) { 1342 &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw, 1343 }, 1344 .num_parents = 1, 1345 .flags = CLK_SET_RATE_PARENT, 1346 .ops = &clk_branch2_ops, 1347 }, 1348 }, 1349 }; 1350 1351 static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = { 1352 .halt_reg = 0x8090, 1353 .halt_check = BRANCH_HALT, 1354 .clkr = { 1355 .enable_reg = 0x8090, 1356 .enable_mask = BIT(0), 1357 .hw.init = &(struct clk_init_data) { 1358 .name = "disp_cc_mdss_dptx3_pixel0_clk", 1359 .parent_hws = (const struct clk_hw*[]) { 1360 &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, 1361 }, 1362 .num_parents = 1, 1363 .flags = CLK_SET_RATE_PARENT, 1364 .ops = &clk_branch2_ops, 1365 }, 1366 }, 1367 }; 1368 1369 static struct clk_branch disp_cc_mdss_esc0_clk = { 1370 .halt_reg = 0x8038, 1371 .halt_check = BRANCH_HALT, 1372 .clkr = { 1373 .enable_reg = 0x8038, 1374 .enable_mask = BIT(0), 1375 .hw.init = &(struct clk_init_data) { 1376 .name = "disp_cc_mdss_esc0_clk", 1377 .parent_hws = (const struct clk_hw*[]) { 1378 &disp_cc_mdss_esc0_clk_src.clkr.hw, 1379 }, 1380 .num_parents = 1, 1381 .flags = CLK_SET_RATE_PARENT, 1382 .ops = &clk_branch2_ops, 1383 }, 1384 }, 1385 }; 1386 1387 static struct clk_branch disp_cc_mdss_esc1_clk = { 1388 .halt_reg = 0x803c, 1389 .halt_check = BRANCH_HALT, 1390 .clkr = { 1391 .enable_reg = 0x803c, 1392 .enable_mask = BIT(0), 1393 .hw.init = &(struct clk_init_data) { 1394 .name = "disp_cc_mdss_esc1_clk", 1395 .parent_hws = (const struct clk_hw*[]) { 1396 &disp_cc_mdss_esc1_clk_src.clkr.hw, 1397 }, 1398 .num_parents = 1, 1399 .flags = CLK_SET_RATE_PARENT, 1400 .ops = &clk_branch2_ops, 1401 }, 1402 }, 1403 }; 1404 1405 static struct clk_branch disp_cc_mdss_mdp1_clk = { 1406 .halt_reg = 0xa004, 1407 .halt_check = BRANCH_HALT, 1408 .clkr = { 1409 .enable_reg = 0xa004, 1410 .enable_mask = BIT(0), 1411 .hw.init = &(struct clk_init_data) { 1412 .name = "disp_cc_mdss_mdp1_clk", 1413 .parent_hws = (const struct clk_hw*[]) { 1414 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1415 }, 1416 .num_parents = 1, 1417 .flags = CLK_SET_RATE_PARENT, 1418 .ops = &clk_branch2_ops, 1419 }, 1420 }, 1421 }; 1422 1423 static struct clk_branch disp_cc_mdss_mdp_clk = { 1424 .halt_reg = 0x800c, 1425 .halt_check = BRANCH_HALT, 1426 .clkr = { 1427 .enable_reg = 0x800c, 1428 .enable_mask = BIT(0), 1429 .hw.init = &(struct clk_init_data) { 1430 .name = "disp_cc_mdss_mdp_clk", 1431 .parent_hws = (const struct clk_hw*[]) { 1432 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1433 }, 1434 .num_parents = 1, 1435 .flags = CLK_SET_RATE_PARENT, 1436 .ops = &clk_branch2_ops, 1437 }, 1438 }, 1439 }; 1440 1441 static struct clk_branch disp_cc_mdss_mdp_lut1_clk = { 1442 .halt_reg = 0xa014, 1443 .halt_check = BRANCH_HALT, 1444 .clkr = { 1445 .enable_reg = 0xa014, 1446 .enable_mask = BIT(0), 1447 .hw.init = &(struct clk_init_data) { 1448 .name = "disp_cc_mdss_mdp_lut1_clk", 1449 .parent_hws = (const struct clk_hw*[]) { 1450 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1451 }, 1452 .num_parents = 1, 1453 .flags = CLK_SET_RATE_PARENT, 1454 .ops = &clk_branch2_ops, 1455 }, 1456 }, 1457 }; 1458 1459 static struct clk_branch disp_cc_mdss_mdp_lut_clk = { 1460 .halt_reg = 0x801c, 1461 .halt_check = BRANCH_HALT_VOTED, 1462 .clkr = { 1463 .enable_reg = 0x801c, 1464 .enable_mask = BIT(0), 1465 .hw.init = &(struct clk_init_data) { 1466 .name = "disp_cc_mdss_mdp_lut_clk", 1467 .parent_hws = (const struct clk_hw*[]) { 1468 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1469 }, 1470 .num_parents = 1, 1471 .flags = CLK_SET_RATE_PARENT, 1472 .ops = &clk_branch2_ops, 1473 }, 1474 }, 1475 }; 1476 1477 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { 1478 .halt_reg = 0xc004, 1479 .halt_check = BRANCH_HALT_VOTED, 1480 .clkr = { 1481 .enable_reg = 0xc004, 1482 .enable_mask = BIT(0), 1483 .hw.init = &(struct clk_init_data) { 1484 .name = "disp_cc_mdss_non_gdsc_ahb_clk", 1485 .parent_hws = (const struct clk_hw*[]) { 1486 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1487 }, 1488 .num_parents = 1, 1489 .flags = CLK_SET_RATE_PARENT, 1490 .ops = &clk_branch2_ops, 1491 }, 1492 }, 1493 }; 1494 1495 static struct clk_branch disp_cc_mdss_pclk0_clk = { 1496 .halt_reg = 0x8004, 1497 .halt_check = BRANCH_HALT, 1498 .clkr = { 1499 .enable_reg = 0x8004, 1500 .enable_mask = BIT(0), 1501 .hw.init = &(struct clk_init_data) { 1502 .name = "disp_cc_mdss_pclk0_clk", 1503 .parent_hws = (const struct clk_hw*[]) { 1504 &disp_cc_mdss_pclk0_clk_src.clkr.hw, 1505 }, 1506 .num_parents = 1, 1507 .flags = CLK_SET_RATE_PARENT, 1508 .ops = &clk_branch2_ops, 1509 }, 1510 }, 1511 }; 1512 1513 static struct clk_branch disp_cc_mdss_pclk1_clk = { 1514 .halt_reg = 0x8008, 1515 .halt_check = BRANCH_HALT, 1516 .clkr = { 1517 .enable_reg = 0x8008, 1518 .enable_mask = BIT(0), 1519 .hw.init = &(struct clk_init_data) { 1520 .name = "disp_cc_mdss_pclk1_clk", 1521 .parent_hws = (const struct clk_hw*[]) { 1522 &disp_cc_mdss_pclk1_clk_src.clkr.hw, 1523 }, 1524 .num_parents = 1, 1525 .flags = CLK_SET_RATE_PARENT, 1526 .ops = &clk_branch2_ops, 1527 }, 1528 }, 1529 }; 1530 1531 static struct clk_branch disp_cc_mdss_rot1_clk = { 1532 .halt_reg = 0xa00c, 1533 .halt_check = BRANCH_HALT, 1534 .clkr = { 1535 .enable_reg = 0xa00c, 1536 .enable_mask = BIT(0), 1537 .hw.init = &(struct clk_init_data) { 1538 .name = "disp_cc_mdss_rot1_clk", 1539 .parent_hws = (const struct clk_hw*[]) { 1540 &disp_cc_mdss_rot_clk_src.clkr.hw, 1541 }, 1542 .num_parents = 1, 1543 .flags = CLK_SET_RATE_PARENT, 1544 .ops = &clk_branch2_ops, 1545 }, 1546 }, 1547 }; 1548 1549 static struct clk_branch disp_cc_mdss_rot_clk = { 1550 .halt_reg = 0x8014, 1551 .halt_check = BRANCH_HALT, 1552 .clkr = { 1553 .enable_reg = 0x8014, 1554 .enable_mask = BIT(0), 1555 .hw.init = &(struct clk_init_data) { 1556 .name = "disp_cc_mdss_rot_clk", 1557 .parent_hws = (const struct clk_hw*[]) { 1558 &disp_cc_mdss_rot_clk_src.clkr.hw, 1559 }, 1560 .num_parents = 1, 1561 .flags = CLK_SET_RATE_PARENT, 1562 .ops = &clk_branch2_ops, 1563 }, 1564 }, 1565 }; 1566 1567 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { 1568 .halt_reg = 0xc00c, 1569 .halt_check = BRANCH_HALT, 1570 .clkr = { 1571 .enable_reg = 0xc00c, 1572 .enable_mask = BIT(0), 1573 .hw.init = &(struct clk_init_data) { 1574 .name = "disp_cc_mdss_rscc_ahb_clk", 1575 .parent_hws = (const struct clk_hw*[]) { 1576 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1577 }, 1578 .num_parents = 1, 1579 .flags = CLK_SET_RATE_PARENT, 1580 .ops = &clk_branch2_ops, 1581 }, 1582 }, 1583 }; 1584 1585 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { 1586 .halt_reg = 0xc008, 1587 .halt_check = BRANCH_HALT, 1588 .clkr = { 1589 .enable_reg = 0xc008, 1590 .enable_mask = BIT(0), 1591 .hw.init = &(struct clk_init_data) { 1592 .name = "disp_cc_mdss_rscc_vsync_clk", 1593 .parent_hws = (const struct clk_hw*[]) { 1594 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1595 }, 1596 .num_parents = 1, 1597 .flags = CLK_SET_RATE_PARENT, 1598 .ops = &clk_branch2_ops, 1599 }, 1600 }, 1601 }; 1602 1603 static struct clk_branch disp_cc_mdss_vsync1_clk = { 1604 .halt_reg = 0xa01c, 1605 .halt_check = BRANCH_HALT, 1606 .clkr = { 1607 .enable_reg = 0xa01c, 1608 .enable_mask = BIT(0), 1609 .hw.init = &(struct clk_init_data) { 1610 .name = "disp_cc_mdss_vsync1_clk", 1611 .parent_hws = (const struct clk_hw*[]) { 1612 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1613 }, 1614 .num_parents = 1, 1615 .flags = CLK_SET_RATE_PARENT, 1616 .ops = &clk_branch2_ops, 1617 }, 1618 }, 1619 }; 1620 1621 static struct clk_branch disp_cc_mdss_vsync_clk = { 1622 .halt_reg = 0x8024, 1623 .halt_check = BRANCH_HALT, 1624 .clkr = { 1625 .enable_reg = 0x8024, 1626 .enable_mask = BIT(0), 1627 .hw.init = &(struct clk_init_data) { 1628 .name = "disp_cc_mdss_vsync_clk", 1629 .parent_hws = (const struct clk_hw*[]) { 1630 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1631 }, 1632 .num_parents = 1, 1633 .flags = CLK_SET_RATE_PARENT, 1634 .ops = &clk_branch2_ops, 1635 }, 1636 }, 1637 }; 1638 1639 static struct clk_branch disp_cc_sleep_clk = { 1640 .halt_reg = 0xe078, 1641 .halt_check = BRANCH_HALT, 1642 .clkr = { 1643 .enable_reg = 0xe078, 1644 .enable_mask = BIT(0), 1645 .hw.init = &(struct clk_init_data) { 1646 .name = "disp_cc_sleep_clk", 1647 .parent_hws = (const struct clk_hw*[]) { 1648 &disp_cc_sleep_clk_src.clkr.hw, 1649 }, 1650 .num_parents = 1, 1651 .flags = CLK_SET_RATE_PARENT, 1652 .ops = &clk_branch2_ops, 1653 }, 1654 }, 1655 }; 1656 1657 static struct gdsc mdss_gdsc = { 1658 .gdscr = 0x9000, 1659 .pd = { 1660 .name = "mdss_gdsc", 1661 }, 1662 .pwrsts = PWRSTS_OFF_ON, 1663 .flags = HW_CTRL | RETAIN_FF_ENABLE, 1664 }; 1665 1666 static struct gdsc mdss_int2_gdsc = { 1667 .gdscr = 0xb000, 1668 .pd = { 1669 .name = "mdss_int2_gdsc", 1670 }, 1671 .pwrsts = PWRSTS_OFF_ON, 1672 .flags = HW_CTRL | RETAIN_FF_ENABLE, 1673 }; 1674 1675 static struct clk_regmap *disp_cc_sm8450_clocks[] = { 1676 [DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr, 1677 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, 1678 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, 1679 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, 1680 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, 1681 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, 1682 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, 1683 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr, 1684 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr, 1685 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr, 1686 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, 1687 [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr, 1688 [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr, 1689 [DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr, 1690 [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr, 1691 [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr, 1692 [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr, 1693 [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr, 1694 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr, 1695 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr, 1696 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr, 1697 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr, 1698 [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = 1699 &disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, 1700 [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr, 1701 [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr, 1702 [DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &disp_cc_mdss_dptx1_crypto_clk.clkr, 1703 [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr, 1704 [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr, 1705 [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr, 1706 [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr, 1707 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr, 1708 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr, 1709 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr, 1710 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr, 1711 [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] = 1712 &disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, 1713 [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr, 1714 [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr, 1715 [DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &disp_cc_mdss_dptx2_crypto_clk.clkr, 1716 [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr, 1717 [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr, 1718 [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr, 1719 [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr, 1720 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr, 1721 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr, 1722 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr, 1723 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr, 1724 [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr, 1725 [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr, 1726 [DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &disp_cc_mdss_dptx3_crypto_clk.clkr, 1727 [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr, 1728 [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr, 1729 [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr, 1730 [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr, 1731 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr, 1732 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr, 1733 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, 1734 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, 1735 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, 1736 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr, 1737 [DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr, 1738 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, 1739 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, 1740 [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr, 1741 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, 1742 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, 1743 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, 1744 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, 1745 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr, 1746 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr, 1747 [DISP_CC_MDSS_ROT1_CLK] = &disp_cc_mdss_rot1_clk.clkr, 1748 [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr, 1749 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr, 1750 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, 1751 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, 1752 [DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr, 1753 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, 1754 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, 1755 [DISP_CC_PLL0] = &disp_cc_pll0.clkr, 1756 [DISP_CC_PLL1] = &disp_cc_pll1.clkr, 1757 [DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr, 1758 [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr, 1759 [DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr, 1760 }; 1761 1762 static const struct qcom_reset_map disp_cc_sm8450_resets[] = { 1763 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 }, 1764 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 }, 1765 [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 }, 1766 }; 1767 1768 static struct gdsc *disp_cc_sm8450_gdscs[] = { 1769 [MDSS_GDSC] = &mdss_gdsc, 1770 [MDSS_INT2_GDSC] = &mdss_int2_gdsc, 1771 }; 1772 1773 static const struct regmap_config disp_cc_sm8450_regmap_config = { 1774 .reg_bits = 32, 1775 .reg_stride = 4, 1776 .val_bits = 32, 1777 .max_register = 0x11008, 1778 .fast_io = true, 1779 }; 1780 1781 static const struct qcom_cc_desc disp_cc_sm8450_desc = { 1782 .config = &disp_cc_sm8450_regmap_config, 1783 .clks = disp_cc_sm8450_clocks, 1784 .num_clks = ARRAY_SIZE(disp_cc_sm8450_clocks), 1785 .resets = disp_cc_sm8450_resets, 1786 .num_resets = ARRAY_SIZE(disp_cc_sm8450_resets), 1787 .gdscs = disp_cc_sm8450_gdscs, 1788 .num_gdscs = ARRAY_SIZE(disp_cc_sm8450_gdscs), 1789 }; 1790 1791 static const struct of_device_id disp_cc_sm8450_match_table[] = { 1792 { .compatible = "qcom,sm8450-dispcc" }, 1793 { .compatible = "qcom,sm8475-dispcc" }, 1794 { } 1795 }; 1796 MODULE_DEVICE_TABLE(of, disp_cc_sm8450_match_table); 1797 1798 static int disp_cc_sm8450_probe(struct platform_device *pdev) 1799 { 1800 struct regmap *regmap; 1801 int ret; 1802 1803 ret = devm_pm_runtime_enable(&pdev->dev); 1804 if (ret) 1805 return ret; 1806 1807 ret = pm_runtime_resume_and_get(&pdev->dev); 1808 if (ret) 1809 return ret; 1810 1811 regmap = qcom_cc_map(pdev, &disp_cc_sm8450_desc); 1812 if (IS_ERR(regmap)) { 1813 ret = PTR_ERR(regmap); 1814 goto err_put_rpm; 1815 } 1816 1817 if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-dispcc")) { 1818 /* Update DISPCC PLL0 */ 1819 disp_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; 1820 disp_cc_pll0.clkr.hw.init = &sm8475_disp_cc_pll0_init; 1821 1822 /* Update DISPCC PLL1 */ 1823 disp_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; 1824 disp_cc_pll1.clkr.hw.init = &sm8475_disp_cc_pll1_init; 1825 1826 clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &sm8475_disp_cc_pll0_config); 1827 clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &sm8475_disp_cc_pll1_config); 1828 } else { 1829 clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); 1830 clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); 1831 } 1832 1833 /* Enable clock gating for MDP clocks */ 1834 regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); 1835 1836 /* Keep some clocks always-on */ 1837 qcom_branch_set_clk_en(regmap, 0xe05c); /* DISP_CC_XO_CLK */ 1838 1839 ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8450_desc, regmap); 1840 if (ret) 1841 goto err_put_rpm; 1842 1843 pm_runtime_put(&pdev->dev); 1844 1845 return 0; 1846 1847 err_put_rpm: 1848 pm_runtime_put_sync(&pdev->dev); 1849 1850 return ret; 1851 } 1852 1853 static struct platform_driver disp_cc_sm8450_driver = { 1854 .probe = disp_cc_sm8450_probe, 1855 .driver = { 1856 .name = "disp_cc-sm8450", 1857 .of_match_table = disp_cc_sm8450_match_table, 1858 }, 1859 }; 1860 1861 module_platform_driver(disp_cc_sm8450_driver); 1862 1863 MODULE_DESCRIPTION("QTI DISPCC SM8450 / SM8475 Driver"); 1864 MODULE_LICENSE("GPL"); 1865