xref: /linux/drivers/clk/qcom/dispcc-sm8250.c (revision 3a39d672e7f48b8d6b91a09afa4b55352773b4b5)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2018-2020, 2022, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/regmap.h>
11 #include <linux/reset-controller.h>
12 
13 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
14 
15 #include "clk-alpha-pll.h"
16 #include "clk-branch.h"
17 #include "clk-rcg.h"
18 #include "clk-regmap-divider.h"
19 #include "common.h"
20 #include "gdsc.h"
21 #include "reset.h"
22 
23 enum {
24 	P_BI_TCXO,
25 	P_DISP_CC_PLL0_OUT_MAIN,
26 	P_DISP_CC_PLL1_OUT_EVEN,
27 	P_DISP_CC_PLL1_OUT_MAIN,
28 	P_DP_PHY_PLL_LINK_CLK,
29 	P_DP_PHY_PLL_VCO_DIV_CLK,
30 	P_DPTX1_PHY_PLL_LINK_CLK,
31 	P_DPTX1_PHY_PLL_VCO_DIV_CLK,
32 	P_DPTX2_PHY_PLL_LINK_CLK,
33 	P_DPTX2_PHY_PLL_VCO_DIV_CLK,
34 	P_EDP_PHY_PLL_LINK_CLK,
35 	P_EDP_PHY_PLL_VCO_DIV_CLK,
36 	P_DSI0_PHY_PLL_OUT_BYTECLK,
37 	P_DSI0_PHY_PLL_OUT_DSICLK,
38 	P_DSI1_PHY_PLL_OUT_BYTECLK,
39 	P_DSI1_PHY_PLL_OUT_DSICLK,
40 };
41 
42 static const struct pll_vco vco_table[] = {
43 	{ 249600000, 2000000000, 0 },
44 };
45 
46 static const struct pll_vco lucid_5lpe_vco[] = {
47 	{ 249600000, 1750000000, 0 },
48 };
49 
50 static struct alpha_pll_config disp_cc_pll0_config = {
51 	.l = 0x47,
52 	.alpha = 0xE000,
53 	.config_ctl_val = 0x20485699,
54 	.config_ctl_hi_val = 0x00002261,
55 	.config_ctl_hi1_val = 0x329A699C,
56 	.user_ctl_val = 0x00000000,
57 	.user_ctl_hi_val = 0x00000805,
58 	.user_ctl_hi1_val = 0x00000000,
59 };
60 
61 static struct clk_init_data disp_cc_pll0_init = {
62 	.name = "disp_cc_pll0",
63 	.parent_data = &(const struct clk_parent_data){
64 		.fw_name = "bi_tcxo",
65 	},
66 	.num_parents = 1,
67 	.ops = &clk_alpha_pll_lucid_ops,
68 };
69 
70 static struct clk_alpha_pll disp_cc_pll0 = {
71 	.offset = 0x0,
72 	.vco_table = vco_table,
73 	.num_vco = ARRAY_SIZE(vco_table),
74 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
75 	.clkr.hw.init = &disp_cc_pll0_init
76 };
77 
78 static struct alpha_pll_config disp_cc_pll1_config = {
79 	.l = 0x1F,
80 	.alpha = 0x4000,
81 	.config_ctl_val = 0x20485699,
82 	.config_ctl_hi_val = 0x00002261,
83 	.config_ctl_hi1_val = 0x329A699C,
84 	.user_ctl_val = 0x00000000,
85 	.user_ctl_hi_val = 0x00000805,
86 	.user_ctl_hi1_val = 0x00000000,
87 };
88 
89 static struct clk_init_data disp_cc_pll1_init = {
90 	.name = "disp_cc_pll1",
91 	.parent_data = &(const struct clk_parent_data){
92 		.fw_name = "bi_tcxo",
93 	},
94 	.num_parents = 1,
95 	.ops = &clk_alpha_pll_lucid_ops,
96 };
97 
98 static struct clk_alpha_pll disp_cc_pll1 = {
99 	.offset = 0x1000,
100 	.vco_table = vco_table,
101 	.num_vco = ARRAY_SIZE(vco_table),
102 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
103 	.clkr.hw.init = &disp_cc_pll1_init
104 };
105 
106 static const struct parent_map disp_cc_parent_map_0[] = {
107 	{ P_BI_TCXO, 0 },
108 	{ P_DP_PHY_PLL_LINK_CLK, 1 },
109 	{ P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
110 	{ P_DPTX1_PHY_PLL_LINK_CLK, 3 },
111 	{ P_DPTX1_PHY_PLL_VCO_DIV_CLK, 4 },
112 	{ P_DPTX2_PHY_PLL_LINK_CLK, 5 },
113 	{ P_DPTX2_PHY_PLL_VCO_DIV_CLK, 6 },
114 };
115 
116 static const struct clk_parent_data disp_cc_parent_data_0[] = {
117 	{ .fw_name = "bi_tcxo" },
118 	{ .fw_name = "dp_phy_pll_link_clk" },
119 	{ .fw_name = "dp_phy_pll_vco_div_clk" },
120 	{ .fw_name = "dptx1_phy_pll_link_clk" },
121 	{ .fw_name = "dptx1_phy_pll_vco_div_clk" },
122 	{ .fw_name = "dptx2_phy_pll_link_clk" },
123 	{ .fw_name = "dptx2_phy_pll_vco_div_clk" },
124 };
125 
126 static const struct parent_map disp_cc_parent_map_1[] = {
127 	{ P_BI_TCXO, 0 },
128 };
129 
130 static const struct clk_parent_data disp_cc_parent_data_1[] = {
131 	{ .fw_name = "bi_tcxo" },
132 };
133 
134 static const struct parent_map disp_cc_parent_map_2[] = {
135 	{ P_BI_TCXO, 0 },
136 	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
137 	{ P_DSI1_PHY_PLL_OUT_BYTECLK, 2 },
138 };
139 
140 static const struct clk_parent_data disp_cc_parent_data_2[] = {
141 	{ .fw_name = "bi_tcxo" },
142 	{ .fw_name = "dsi0_phy_pll_out_byteclk" },
143 	{ .fw_name = "dsi1_phy_pll_out_byteclk" },
144 };
145 
146 static const struct parent_map disp_cc_parent_map_3[] = {
147 	{ P_BI_TCXO, 0 },
148 	{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
149 };
150 
151 static const struct clk_parent_data disp_cc_parent_data_3[] = {
152 	{ .fw_name = "bi_tcxo" },
153 	{ .hw = &disp_cc_pll1.clkr.hw },
154 };
155 
156 static const struct parent_map disp_cc_parent_map_4[] = {
157 	{ P_BI_TCXO, 0 },
158 	{ P_EDP_PHY_PLL_LINK_CLK, 1 },
159 	{ P_EDP_PHY_PLL_VCO_DIV_CLK, 2},
160 };
161 
162 static const struct clk_parent_data disp_cc_parent_data_4[] = {
163 	{ .fw_name = "bi_tcxo" },
164 	{ .fw_name = "edp_phy_pll_link_clk" },
165 	{ .fw_name = "edp_phy_pll_vco_div_clk" },
166 };
167 
168 static const struct parent_map disp_cc_parent_map_5[] = {
169 	{ P_BI_TCXO, 0 },
170 	{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
171 	{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
172 };
173 
174 static const struct clk_parent_data disp_cc_parent_data_5[] = {
175 	{ .fw_name = "bi_tcxo" },
176 	{ .hw = &disp_cc_pll0.clkr.hw },
177 	{ .hw = &disp_cc_pll1.clkr.hw },
178 };
179 
180 static const struct parent_map disp_cc_parent_map_6[] = {
181 	{ P_BI_TCXO, 0 },
182 	{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
183 	{ P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
184 };
185 
186 static const struct clk_parent_data disp_cc_parent_data_6[] = {
187 	{ .fw_name = "bi_tcxo" },
188 	{ .fw_name = "dsi0_phy_pll_out_dsiclk" },
189 	{ .fw_name = "dsi1_phy_pll_out_dsiclk" },
190 };
191 
192 static const struct parent_map disp_cc_parent_map_7[] = {
193 	{ P_BI_TCXO, 0 },
194 	{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
195 	/* { P_DISP_CC_PLL1_OUT_EVEN, 5 }, */
196 };
197 
198 static const struct clk_parent_data disp_cc_parent_data_7[] = {
199 	{ .fw_name = "bi_tcxo" },
200 	{ .hw = &disp_cc_pll1.clkr.hw },
201 	/* { .hw = &disp_cc_pll1_out_even.clkr.hw }, */
202 };
203 
204 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
205 	F(19200000, P_BI_TCXO, 1, 0, 0),
206 	F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
207 	F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
208 	{ }
209 };
210 
211 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
212 	.cmd_rcgr = 0x22bc,
213 	.mnd_width = 0,
214 	.hid_width = 5,
215 	.parent_map = disp_cc_parent_map_3,
216 	.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
217 	.clkr.hw.init = &(const struct clk_init_data) {
218 		.name = "disp_cc_mdss_ahb_clk_src",
219 		.parent_data = disp_cc_parent_data_3,
220 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
221 		.flags = CLK_SET_RATE_PARENT,
222 		.ops = &clk_rcg2_shared_ops,
223 	},
224 };
225 
226 static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
227 	F(19200000, P_BI_TCXO, 1, 0, 0),
228 	{ }
229 };
230 
231 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
232 	.cmd_rcgr = 0x2110,
233 	.mnd_width = 0,
234 	.hid_width = 5,
235 	.parent_map = disp_cc_parent_map_2,
236 	.clkr.hw.init = &(const struct clk_init_data) {
237 		.name = "disp_cc_mdss_byte0_clk_src",
238 		.parent_data = disp_cc_parent_data_2,
239 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
240 		.flags = CLK_SET_RATE_PARENT,
241 		.ops = &clk_byte2_ops,
242 	},
243 };
244 
245 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
246 	.cmd_rcgr = 0x212c,
247 	.mnd_width = 0,
248 	.hid_width = 5,
249 	.parent_map = disp_cc_parent_map_2,
250 	.clkr.hw.init = &(const struct clk_init_data) {
251 		.name = "disp_cc_mdss_byte1_clk_src",
252 		.parent_data = disp_cc_parent_data_2,
253 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
254 		.flags = CLK_SET_RATE_PARENT,
255 		.ops = &clk_byte2_ops,
256 	},
257 };
258 
259 static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = {
260 	.cmd_rcgr = 0x2240,
261 	.mnd_width = 0,
262 	.hid_width = 5,
263 	.parent_map = disp_cc_parent_map_1,
264 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
265 	.clkr.hw.init = &(const struct clk_init_data) {
266 		.name = "disp_cc_mdss_dp_aux1_clk_src",
267 		.parent_data = disp_cc_parent_data_1,
268 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
269 		.flags = CLK_SET_RATE_PARENT,
270 		.ops = &clk_rcg2_ops,
271 	},
272 };
273 
274 static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
275 	.cmd_rcgr = 0x21dc,
276 	.mnd_width = 0,
277 	.hid_width = 5,
278 	.parent_map = disp_cc_parent_map_1,
279 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
280 	.clkr.hw.init = &(const struct clk_init_data) {
281 		.name = "disp_cc_mdss_dp_aux_clk_src",
282 		.parent_data = disp_cc_parent_data_1,
283 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
284 		.flags = CLK_SET_RATE_PARENT,
285 		.ops = &clk_rcg2_ops,
286 	},
287 };
288 
289 static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = {
290 	.cmd_rcgr = 0x220c,
291 	.mnd_width = 0,
292 	.hid_width = 5,
293 	.parent_map = disp_cc_parent_map_0,
294 	.clkr.hw.init = &(const struct clk_init_data) {
295 		.name = "disp_cc_mdss_dp_link1_clk_src",
296 		.parent_data = disp_cc_parent_data_0,
297 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
298 		.ops = &clk_byte2_ops,
299 	},
300 };
301 
302 static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
303 	.cmd_rcgr = 0x2178,
304 	.mnd_width = 0,
305 	.hid_width = 5,
306 	.parent_map = disp_cc_parent_map_0,
307 	.clkr.hw.init = &(const struct clk_init_data) {
308 		.name = "disp_cc_mdss_dp_link_clk_src",
309 		.parent_data = disp_cc_parent_data_0,
310 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
311 		.ops = &clk_byte2_ops,
312 	},
313 };
314 
315 static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {
316 	.cmd_rcgr = 0x21c4,
317 	.mnd_width = 16,
318 	.hid_width = 5,
319 	.parent_map = disp_cc_parent_map_0,
320 	.clkr.hw.init = &(const struct clk_init_data) {
321 		.name = "disp_cc_mdss_dp_pixel1_clk_src",
322 		.parent_data = disp_cc_parent_data_0,
323 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
324 		.ops = &clk_dp_ops,
325 	},
326 };
327 
328 static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = {
329 	.cmd_rcgr = 0x21f4,
330 	.mnd_width = 16,
331 	.hid_width = 5,
332 	.parent_map = disp_cc_parent_map_0,
333 	.clkr.hw.init = &(const struct clk_init_data) {
334 		.name = "disp_cc_mdss_dp_pixel2_clk_src",
335 		.parent_data = disp_cc_parent_data_0,
336 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
337 		.ops = &clk_dp_ops,
338 	},
339 };
340 
341 static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
342 	.cmd_rcgr = 0x21ac,
343 	.mnd_width = 16,
344 	.hid_width = 5,
345 	.parent_map = disp_cc_parent_map_0,
346 	.clkr.hw.init = &(const struct clk_init_data) {
347 		.name = "disp_cc_mdss_dp_pixel_clk_src",
348 		.parent_data = disp_cc_parent_data_0,
349 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
350 		.ops = &clk_dp_ops,
351 	},
352 };
353 
354 static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = {
355 	.cmd_rcgr = 0x228c,
356 	.mnd_width = 0,
357 	.hid_width = 5,
358 	.parent_map = disp_cc_parent_map_1,
359 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
360 	.clkr.hw.init = &(const struct clk_init_data) {
361 		.name = "disp_cc_mdss_edp_aux_clk_src",
362 		.parent_data = disp_cc_parent_data_1,
363 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
364 		.flags = CLK_SET_RATE_PARENT,
365 		.ops = &clk_rcg2_ops,
366 	},
367 };
368 
369 static struct clk_rcg2 disp_cc_mdss_edp_gtc_clk_src = {
370 	.cmd_rcgr = 0x22a4,
371 	.mnd_width = 0,
372 	.hid_width = 5,
373 	.parent_map = disp_cc_parent_map_7,
374 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
375 	.clkr.hw.init = &(const struct clk_init_data) {
376 		.name = "disp_cc_mdss_edp_gtc_clk_src",
377 		.parent_data = disp_cc_parent_data_7,
378 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
379 		.flags = CLK_SET_RATE_PARENT,
380 		.ops = &clk_rcg2_ops,
381 	},
382 };
383 
384 static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = {
385 	.cmd_rcgr = 0x2270,
386 	.mnd_width = 0,
387 	.hid_width = 5,
388 	.parent_map = disp_cc_parent_map_4,
389 	.clkr.hw.init = &(const struct clk_init_data) {
390 		.name = "disp_cc_mdss_edp_link_clk_src",
391 		.parent_data = disp_cc_parent_data_4,
392 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
393 		.flags = CLK_SET_RATE_PARENT,
394 		.ops = &clk_byte2_ops,
395 	},
396 };
397 
398 static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = {
399 	.cmd_rcgr = 0x2258,
400 	.mnd_width = 16,
401 	.hid_width = 5,
402 	.parent_map = disp_cc_parent_map_4,
403 	.clkr.hw.init = &(const struct clk_init_data) {
404 		.name = "disp_cc_mdss_edp_pixel_clk_src",
405 		.parent_data = disp_cc_parent_data_4,
406 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
407 		.ops = &clk_dp_ops,
408 	},
409 };
410 
411 static struct clk_branch disp_cc_mdss_edp_aux_clk = {
412 	.halt_reg = 0x2078,
413 	.halt_check = BRANCH_HALT,
414 	.clkr = {
415 		.enable_reg = 0x2078,
416 		.enable_mask = BIT(0),
417 		.hw.init = &(const struct clk_init_data) {
418 			.name = "disp_cc_mdss_edp_aux_clk",
419 			.parent_hws = (const struct clk_hw*[]){
420 				&disp_cc_mdss_edp_aux_clk_src.clkr.hw,
421 			},
422 			.num_parents = 1,
423 			.flags = CLK_SET_RATE_PARENT,
424 			.ops = &clk_branch2_ops,
425 		},
426 	},
427 };
428 
429 static struct clk_branch disp_cc_mdss_edp_gtc_clk = {
430 	.halt_reg = 0x207c,
431 	.halt_check = BRANCH_HALT,
432 	.clkr = {
433 		.enable_reg = 0x207c,
434 		.enable_mask = BIT(0),
435 		.hw.init = &(const struct clk_init_data) {
436 			.name = "disp_cc_mdss_edp_gtc_clk",
437 			.parent_hws = (const struct clk_hw*[]){
438 				&disp_cc_mdss_edp_gtc_clk_src.clkr.hw,
439 			},
440 			.num_parents = 1,
441 			.flags = CLK_SET_RATE_PARENT,
442 			.ops = &clk_branch2_ops,
443 		},
444 	},
445 };
446 
447 static struct clk_branch disp_cc_mdss_edp_link_clk = {
448 	.halt_reg = 0x2070,
449 	.halt_check = BRANCH_HALT,
450 	.clkr = {
451 		.enable_reg = 0x2070,
452 		.enable_mask = BIT(0),
453 		.hw.init = &(const struct clk_init_data) {
454 			.name = "disp_cc_mdss_edp_link_clk",
455 			.parent_hws = (const struct clk_hw*[]){
456 				&disp_cc_mdss_edp_link_clk_src.clkr.hw,
457 			},
458 			.num_parents = 1,
459 			.flags = CLK_SET_RATE_PARENT,
460 			.ops = &clk_branch2_ops,
461 		},
462 	},
463 };
464 
465 static struct clk_regmap_div disp_cc_mdss_edp_link_div_clk_src = {
466 	.reg = 0x2288,
467 	.shift = 0,
468 	.width = 2,
469 	.clkr.hw.init = &(const struct clk_init_data) {
470 		.name = "disp_cc_mdss_edp_link_div_clk_src",
471 		.parent_hws = (const struct clk_hw*[]){
472 			&disp_cc_mdss_edp_link_clk_src.clkr.hw,
473 		},
474 		.num_parents = 1,
475 		.ops = &clk_regmap_div_ro_ops,
476 	},
477 };
478 
479 static struct clk_branch disp_cc_mdss_edp_link_intf_clk = {
480 	.halt_reg = 0x2074,
481 	.halt_check = BRANCH_HALT,
482 	.clkr = {
483 		.enable_reg = 0x2074,
484 		.enable_mask = BIT(0),
485 		.hw.init = &(const struct clk_init_data) {
486 			.name = "disp_cc_mdss_edp_link_intf_clk",
487 			.parent_hws = (const struct clk_hw*[]){
488 				&disp_cc_mdss_edp_link_div_clk_src.clkr.hw,
489 			},
490 			.num_parents = 1,
491 			.flags = CLK_GET_RATE_NOCACHE,
492 			.ops = &clk_branch2_ops,
493 		},
494 	},
495 };
496 
497 static struct clk_branch disp_cc_mdss_edp_pixel_clk = {
498 	.halt_reg = 0x206c,
499 	.halt_check = BRANCH_HALT,
500 	.clkr = {
501 		.enable_reg = 0x206c,
502 		.enable_mask = BIT(0),
503 		.hw.init = &(const struct clk_init_data) {
504 			.name = "disp_cc_mdss_edp_pixel_clk",
505 			.parent_hws = (const struct clk_hw*[]){
506 				&disp_cc_mdss_edp_pixel_clk_src.clkr.hw,
507 			},
508 			.num_parents = 1,
509 			.flags = CLK_SET_RATE_PARENT,
510 			.ops = &clk_branch2_ops,
511 		},
512 	},
513 };
514 
515 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
516 	.cmd_rcgr = 0x2148,
517 	.mnd_width = 0,
518 	.hid_width = 5,
519 	.parent_map = disp_cc_parent_map_2,
520 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
521 	.clkr.hw.init = &(const struct clk_init_data) {
522 		.name = "disp_cc_mdss_esc0_clk_src",
523 		.parent_data = disp_cc_parent_data_2,
524 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
525 		.flags = CLK_SET_RATE_PARENT,
526 		.ops = &clk_rcg2_ops,
527 	},
528 };
529 
530 static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
531 	.cmd_rcgr = 0x2160,
532 	.mnd_width = 0,
533 	.hid_width = 5,
534 	.parent_map = disp_cc_parent_map_2,
535 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
536 	.clkr.hw.init = &(const struct clk_init_data) {
537 		.name = "disp_cc_mdss_esc1_clk_src",
538 		.parent_data = disp_cc_parent_data_2,
539 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
540 		.flags = CLK_SET_RATE_PARENT,
541 		.ops = &clk_rcg2_ops,
542 	},
543 };
544 
545 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
546 	F(19200000, P_BI_TCXO, 1, 0, 0),
547 	F(85714286, P_DISP_CC_PLL1_OUT_MAIN, 7, 0, 0),
548 	F(100000000, P_DISP_CC_PLL1_OUT_MAIN, 6, 0, 0),
549 	F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0),
550 	F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
551 	F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
552 	F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
553 	F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
554 	{ }
555 };
556 
557 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
558 	.cmd_rcgr = 0x20c8,
559 	.mnd_width = 0,
560 	.hid_width = 5,
561 	.parent_map = disp_cc_parent_map_5,
562 	.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
563 	.clkr.hw.init = &(const struct clk_init_data) {
564 		.name = "disp_cc_mdss_mdp_clk_src",
565 		.parent_data = disp_cc_parent_data_5,
566 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
567 		.flags = CLK_SET_RATE_PARENT,
568 		.ops = &clk_rcg2_shared_ops,
569 	},
570 };
571 
572 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
573 	.cmd_rcgr = 0x2098,
574 	.mnd_width = 8,
575 	.hid_width = 5,
576 	.parent_map = disp_cc_parent_map_6,
577 	.clkr.hw.init = &(const struct clk_init_data) {
578 		.name = "disp_cc_mdss_pclk0_clk_src",
579 		.parent_data = disp_cc_parent_data_6,
580 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
581 		.flags = CLK_SET_RATE_PARENT,
582 		.ops = &clk_pixel_ops,
583 	},
584 };
585 
586 static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
587 	.cmd_rcgr = 0x20b0,
588 	.mnd_width = 8,
589 	.hid_width = 5,
590 	.parent_map = disp_cc_parent_map_6,
591 	.clkr.hw.init = &(const struct clk_init_data) {
592 		.name = "disp_cc_mdss_pclk1_clk_src",
593 		.parent_data = disp_cc_parent_data_6,
594 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
595 		.flags = CLK_SET_RATE_PARENT,
596 		.ops = &clk_pixel_ops,
597 	},
598 };
599 
600 static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
601 	F(19200000, P_BI_TCXO, 1, 0, 0),
602 	F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
603 	F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
604 	F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
605 	F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
606 	{ }
607 };
608 
609 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
610 	.cmd_rcgr = 0x20e0,
611 	.mnd_width = 0,
612 	.hid_width = 5,
613 	.parent_map = disp_cc_parent_map_5,
614 	.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
615 	.clkr.hw.init = &(const struct clk_init_data) {
616 		.name = "disp_cc_mdss_rot_clk_src",
617 		.parent_data = disp_cc_parent_data_5,
618 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
619 		.flags = CLK_SET_RATE_PARENT,
620 		.ops = &clk_rcg2_shared_ops,
621 	},
622 };
623 
624 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
625 	.cmd_rcgr = 0x20f8,
626 	.mnd_width = 0,
627 	.hid_width = 5,
628 	.parent_map = disp_cc_parent_map_1,
629 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
630 	.clkr.hw.init = &(const struct clk_init_data) {
631 		.name = "disp_cc_mdss_vsync_clk_src",
632 		.parent_data = disp_cc_parent_data_1,
633 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
634 		.flags = CLK_SET_RATE_PARENT,
635 		.ops = &clk_rcg2_ops,
636 	},
637 };
638 
639 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
640 	.reg = 0x2128,
641 	.shift = 0,
642 	.width = 2,
643 	.clkr.hw.init = &(const struct clk_init_data) {
644 		.name = "disp_cc_mdss_byte0_div_clk_src",
645 		.parent_hws = (const struct clk_hw*[]){
646 			&disp_cc_mdss_byte0_clk_src.clkr.hw,
647 		},
648 		.num_parents = 1,
649 		.ops = &clk_regmap_div_ops,
650 	},
651 };
652 
653 
654 static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
655 	.reg = 0x2144,
656 	.shift = 0,
657 	.width = 2,
658 	.clkr.hw.init = &(const struct clk_init_data) {
659 		.name = "disp_cc_mdss_byte1_div_clk_src",
660 		.parent_hws = (const struct clk_hw*[]){
661 			&disp_cc_mdss_byte1_clk_src.clkr.hw,
662 		},
663 		.num_parents = 1,
664 		.ops = &clk_regmap_div_ops,
665 	},
666 };
667 
668 static struct clk_regmap_div disp_cc_mdss_dp_link1_div_clk_src = {
669 	.reg = 0x2224,
670 	.shift = 0,
671 	.width = 2,
672 	.clkr.hw.init = &(const struct clk_init_data) {
673 		.name = "disp_cc_mdss_dp_link1_div_clk_src",
674 		.parent_hws = (const struct clk_hw*[]){
675 			&disp_cc_mdss_dp_link1_clk_src.clkr.hw,
676 		},
677 		.num_parents = 1,
678 		.ops = &clk_regmap_div_ro_ops,
679 	},
680 };
681 
682 static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
683 	.reg = 0x2190,
684 	.shift = 0,
685 	.width = 2,
686 	.clkr.hw.init = &(const struct clk_init_data) {
687 		.name = "disp_cc_mdss_dp_link_div_clk_src",
688 		.parent_hws = (const struct clk_hw*[]){
689 			&disp_cc_mdss_dp_link_clk_src.clkr.hw,
690 		},
691 		.num_parents = 1,
692 		.ops = &clk_regmap_div_ro_ops,
693 	},
694 };
695 
696 static struct clk_branch disp_cc_mdss_ahb_clk = {
697 	.halt_reg = 0x2080,
698 	.halt_check = BRANCH_HALT,
699 	.clkr = {
700 		.enable_reg = 0x2080,
701 		.enable_mask = BIT(0),
702 		.hw.init = &(const struct clk_init_data) {
703 			.name = "disp_cc_mdss_ahb_clk",
704 			.parent_hws = (const struct clk_hw*[]){
705 				&disp_cc_mdss_ahb_clk_src.clkr.hw,
706 			},
707 			.num_parents = 1,
708 			.flags = CLK_SET_RATE_PARENT,
709 			.ops = &clk_branch2_ops,
710 		},
711 	},
712 };
713 
714 static struct clk_branch disp_cc_mdss_byte0_clk = {
715 	.halt_reg = 0x2028,
716 	.halt_check = BRANCH_HALT,
717 	.clkr = {
718 		.enable_reg = 0x2028,
719 		.enable_mask = BIT(0),
720 		.hw.init = &(const struct clk_init_data) {
721 			.name = "disp_cc_mdss_byte0_clk",
722 			.parent_hws = (const struct clk_hw*[]){
723 				&disp_cc_mdss_byte0_clk_src.clkr.hw,
724 			},
725 			.num_parents = 1,
726 			.flags = CLK_SET_RATE_PARENT,
727 			.ops = &clk_branch2_ops,
728 		},
729 	},
730 };
731 
732 static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
733 	.halt_reg = 0x202c,
734 	.halt_check = BRANCH_HALT,
735 	.clkr = {
736 		.enable_reg = 0x202c,
737 		.enable_mask = BIT(0),
738 		.hw.init = &(const struct clk_init_data) {
739 			.name = "disp_cc_mdss_byte0_intf_clk",
740 			.parent_hws = (const struct clk_hw*[]){
741 				&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
742 			},
743 			.num_parents = 1,
744 			.flags = CLK_SET_RATE_PARENT,
745 			.ops = &clk_branch2_ops,
746 		},
747 	},
748 };
749 
750 static struct clk_branch disp_cc_mdss_byte1_clk = {
751 	.halt_reg = 0x2030,
752 	.halt_check = BRANCH_HALT,
753 	.clkr = {
754 		.enable_reg = 0x2030,
755 		.enable_mask = BIT(0),
756 		.hw.init = &(const struct clk_init_data) {
757 			.name = "disp_cc_mdss_byte1_clk",
758 			.parent_hws = (const struct clk_hw*[]){
759 				&disp_cc_mdss_byte1_clk_src.clkr.hw,
760 			},
761 			.num_parents = 1,
762 			.flags = CLK_SET_RATE_PARENT,
763 			.ops = &clk_branch2_ops,
764 		},
765 	},
766 };
767 
768 static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
769 	.halt_reg = 0x2034,
770 	.halt_check = BRANCH_HALT,
771 	.clkr = {
772 		.enable_reg = 0x2034,
773 		.enable_mask = BIT(0),
774 		.hw.init = &(const struct clk_init_data) {
775 			.name = "disp_cc_mdss_byte1_intf_clk",
776 			.parent_hws = (const struct clk_hw*[]){
777 				&disp_cc_mdss_byte1_div_clk_src.clkr.hw,
778 			},
779 			.num_parents = 1,
780 			.flags = CLK_SET_RATE_PARENT,
781 			.ops = &clk_branch2_ops,
782 		},
783 	},
784 };
785 
786 static struct clk_branch disp_cc_mdss_dp_aux1_clk = {
787 	.halt_reg = 0x2068,
788 	.halt_check = BRANCH_HALT,
789 	.clkr = {
790 		.enable_reg = 0x2068,
791 		.enable_mask = BIT(0),
792 		.hw.init = &(const struct clk_init_data) {
793 			.name = "disp_cc_mdss_dp_aux1_clk",
794 			.parent_hws = (const struct clk_hw*[]){
795 				&disp_cc_mdss_dp_aux1_clk_src.clkr.hw,
796 			},
797 			.num_parents = 1,
798 			.flags = CLK_SET_RATE_PARENT,
799 			.ops = &clk_branch2_ops,
800 		},
801 	},
802 };
803 
804 static struct clk_branch disp_cc_mdss_dp_aux_clk = {
805 	.halt_reg = 0x2054,
806 	.halt_check = BRANCH_HALT,
807 	.clkr = {
808 		.enable_reg = 0x2054,
809 		.enable_mask = BIT(0),
810 		.hw.init = &(const struct clk_init_data) {
811 			.name = "disp_cc_mdss_dp_aux_clk",
812 			.parent_hws = (const struct clk_hw*[]){
813 				&disp_cc_mdss_dp_aux_clk_src.clkr.hw,
814 			},
815 			.num_parents = 1,
816 			.flags = CLK_SET_RATE_PARENT,
817 			.ops = &clk_branch2_ops,
818 		},
819 	},
820 };
821 
822 static struct clk_branch disp_cc_mdss_dp_link1_clk = {
823 	.halt_reg = 0x205c,
824 	.halt_check = BRANCH_HALT,
825 	.clkr = {
826 		.enable_reg = 0x205c,
827 		.enable_mask = BIT(0),
828 		.hw.init = &(const struct clk_init_data) {
829 			.name = "disp_cc_mdss_dp_link1_clk",
830 			.parent_hws = (const struct clk_hw*[]){
831 				&disp_cc_mdss_dp_link1_clk_src.clkr.hw,
832 			},
833 			.num_parents = 1,
834 			.flags = CLK_SET_RATE_PARENT,
835 			.ops = &clk_branch2_ops,
836 		},
837 	},
838 };
839 
840 static struct clk_branch disp_cc_mdss_dp_link1_intf_clk = {
841 	.halt_reg = 0x2060,
842 	.halt_check = BRANCH_HALT,
843 	.clkr = {
844 		.enable_reg = 0x2060,
845 		.enable_mask = BIT(0),
846 		.hw.init = &(const struct clk_init_data) {
847 			.name = "disp_cc_mdss_dp_link1_intf_clk",
848 			.parent_hws = (const struct clk_hw*[]){
849 				&disp_cc_mdss_dp_link1_div_clk_src.clkr.hw,
850 			},
851 			.num_parents = 1,
852 			.flags = CLK_SET_RATE_PARENT,
853 			.ops = &clk_branch2_ops,
854 		},
855 	},
856 };
857 
858 static struct clk_branch disp_cc_mdss_dp_link_clk = {
859 	.halt_reg = 0x2040,
860 	.halt_check = BRANCH_HALT,
861 	.clkr = {
862 		.enable_reg = 0x2040,
863 		.enable_mask = BIT(0),
864 		.hw.init = &(const struct clk_init_data) {
865 			.name = "disp_cc_mdss_dp_link_clk",
866 			.parent_hws = (const struct clk_hw*[]){
867 				&disp_cc_mdss_dp_link_clk_src.clkr.hw,
868 			},
869 			.num_parents = 1,
870 			.flags = CLK_SET_RATE_PARENT,
871 			.ops = &clk_branch2_ops,
872 		},
873 	},
874 };
875 
876 static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
877 	.halt_reg = 0x2044,
878 	.halt_check = BRANCH_HALT,
879 	.clkr = {
880 		.enable_reg = 0x2044,
881 		.enable_mask = BIT(0),
882 		.hw.init = &(const struct clk_init_data) {
883 			.name = "disp_cc_mdss_dp_link_intf_clk",
884 			.parent_hws = (const struct clk_hw*[]){
885 				&disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
886 			},
887 			.num_parents = 1,
888 			.flags = CLK_SET_RATE_PARENT,
889 			.ops = &clk_branch2_ops,
890 		},
891 	},
892 };
893 
894 static struct clk_branch disp_cc_mdss_dp_pixel1_clk = {
895 	.halt_reg = 0x2050,
896 	.halt_check = BRANCH_HALT,
897 	.clkr = {
898 		.enable_reg = 0x2050,
899 		.enable_mask = BIT(0),
900 		.hw.init = &(const struct clk_init_data) {
901 			.name = "disp_cc_mdss_dp_pixel1_clk",
902 			.parent_hws = (const struct clk_hw*[]){
903 				&disp_cc_mdss_dp_pixel1_clk_src.clkr.hw,
904 			},
905 			.num_parents = 1,
906 			.flags = CLK_SET_RATE_PARENT,
907 			.ops = &clk_branch2_ops,
908 		},
909 	},
910 };
911 
912 static struct clk_branch disp_cc_mdss_dp_pixel2_clk = {
913 	.halt_reg = 0x2058,
914 	.halt_check = BRANCH_HALT,
915 	.clkr = {
916 		.enable_reg = 0x2058,
917 		.enable_mask = BIT(0),
918 		.hw.init = &(const struct clk_init_data) {
919 			.name = "disp_cc_mdss_dp_pixel2_clk",
920 			.parent_hws = (const struct clk_hw*[]){
921 				&disp_cc_mdss_dp_pixel2_clk_src.clkr.hw,
922 			},
923 			.num_parents = 1,
924 			.flags = CLK_SET_RATE_PARENT,
925 			.ops = &clk_branch2_ops,
926 		},
927 	},
928 };
929 
930 static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
931 	.halt_reg = 0x204c,
932 	.halt_check = BRANCH_HALT,
933 	.clkr = {
934 		.enable_reg = 0x204c,
935 		.enable_mask = BIT(0),
936 		.hw.init = &(const struct clk_init_data) {
937 			.name = "disp_cc_mdss_dp_pixel_clk",
938 			.parent_hws = (const struct clk_hw*[]){
939 				&disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
940 			},
941 			.num_parents = 1,
942 			.flags = CLK_SET_RATE_PARENT,
943 			.ops = &clk_branch2_ops,
944 		},
945 	},
946 };
947 
948 static struct clk_branch disp_cc_mdss_esc0_clk = {
949 	.halt_reg = 0x2038,
950 	.halt_check = BRANCH_HALT,
951 	.clkr = {
952 		.enable_reg = 0x2038,
953 		.enable_mask = BIT(0),
954 		.hw.init = &(const struct clk_init_data) {
955 			.name = "disp_cc_mdss_esc0_clk",
956 			.parent_hws = (const struct clk_hw*[]){
957 				&disp_cc_mdss_esc0_clk_src.clkr.hw,
958 			},
959 			.num_parents = 1,
960 			.flags = CLK_SET_RATE_PARENT,
961 			.ops = &clk_branch2_ops,
962 		},
963 	},
964 };
965 
966 static struct clk_branch disp_cc_mdss_esc1_clk = {
967 	.halt_reg = 0x203c,
968 	.halt_check = BRANCH_HALT,
969 	.clkr = {
970 		.enable_reg = 0x203c,
971 		.enable_mask = BIT(0),
972 		.hw.init = &(const struct clk_init_data) {
973 			.name = "disp_cc_mdss_esc1_clk",
974 			.parent_hws = (const struct clk_hw*[]){
975 				&disp_cc_mdss_esc1_clk_src.clkr.hw,
976 			},
977 			.num_parents = 1,
978 			.flags = CLK_SET_RATE_PARENT,
979 			.ops = &clk_branch2_ops,
980 		},
981 	},
982 };
983 
984 static struct clk_branch disp_cc_mdss_mdp_clk = {
985 	.halt_reg = 0x200c,
986 	.halt_check = BRANCH_HALT,
987 	.clkr = {
988 		.enable_reg = 0x200c,
989 		.enable_mask = BIT(0),
990 		.hw.init = &(const struct clk_init_data) {
991 			.name = "disp_cc_mdss_mdp_clk",
992 			.parent_hws = (const struct clk_hw*[]){
993 				&disp_cc_mdss_mdp_clk_src.clkr.hw,
994 			},
995 			.num_parents = 1,
996 			.flags = CLK_SET_RATE_PARENT,
997 			.ops = &clk_branch2_ops,
998 		},
999 	},
1000 };
1001 
1002 static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
1003 	.halt_reg = 0x201c,
1004 	.halt_check = BRANCH_VOTED,
1005 	.clkr = {
1006 		.enable_reg = 0x201c,
1007 		.enable_mask = BIT(0),
1008 		.hw.init = &(const struct clk_init_data) {
1009 			.name = "disp_cc_mdss_mdp_lut_clk",
1010 			.parent_hws = (const struct clk_hw*[]){
1011 				&disp_cc_mdss_mdp_clk_src.clkr.hw,
1012 			},
1013 			.num_parents = 1,
1014 			.flags = CLK_SET_RATE_PARENT,
1015 			.ops = &clk_branch2_ops,
1016 		},
1017 	},
1018 };
1019 
1020 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
1021 	.halt_reg = 0x4004,
1022 	.halt_check = BRANCH_VOTED,
1023 	.clkr = {
1024 		.enable_reg = 0x4004,
1025 		.enable_mask = BIT(0),
1026 		.hw.init = &(const struct clk_init_data) {
1027 			.name = "disp_cc_mdss_non_gdsc_ahb_clk",
1028 			.parent_hws = (const struct clk_hw*[]){
1029 				&disp_cc_mdss_ahb_clk_src.clkr.hw,
1030 			},
1031 			.num_parents = 1,
1032 			.flags = CLK_SET_RATE_PARENT,
1033 			.ops = &clk_branch2_ops,
1034 		},
1035 	},
1036 };
1037 
1038 static struct clk_branch disp_cc_mdss_pclk0_clk = {
1039 	.halt_reg = 0x2004,
1040 	.halt_check = BRANCH_HALT,
1041 	.clkr = {
1042 		.enable_reg = 0x2004,
1043 		.enable_mask = BIT(0),
1044 		.hw.init = &(const struct clk_init_data) {
1045 			.name = "disp_cc_mdss_pclk0_clk",
1046 			.parent_hws = (const struct clk_hw*[]){
1047 				&disp_cc_mdss_pclk0_clk_src.clkr.hw,
1048 			},
1049 			.num_parents = 1,
1050 			.flags = CLK_SET_RATE_PARENT,
1051 			.ops = &clk_branch2_ops,
1052 		},
1053 	},
1054 };
1055 
1056 static struct clk_branch disp_cc_mdss_pclk1_clk = {
1057 	.halt_reg = 0x2008,
1058 	.halt_check = BRANCH_HALT,
1059 	.clkr = {
1060 		.enable_reg = 0x2008,
1061 		.enable_mask = BIT(0),
1062 		.hw.init = &(const struct clk_init_data) {
1063 			.name = "disp_cc_mdss_pclk1_clk",
1064 			.parent_hws = (const struct clk_hw*[]){
1065 				&disp_cc_mdss_pclk1_clk_src.clkr.hw,
1066 			},
1067 			.num_parents = 1,
1068 			.flags = CLK_SET_RATE_PARENT,
1069 			.ops = &clk_branch2_ops,
1070 		},
1071 	},
1072 };
1073 
1074 static struct clk_branch disp_cc_mdss_rot_clk = {
1075 	.halt_reg = 0x2014,
1076 	.halt_check = BRANCH_HALT,
1077 	.clkr = {
1078 		.enable_reg = 0x2014,
1079 		.enable_mask = BIT(0),
1080 		.hw.init = &(const struct clk_init_data) {
1081 			.name = "disp_cc_mdss_rot_clk",
1082 			.parent_hws = (const struct clk_hw*[]){
1083 				&disp_cc_mdss_rot_clk_src.clkr.hw,
1084 			},
1085 			.num_parents = 1,
1086 			.flags = CLK_SET_RATE_PARENT,
1087 			.ops = &clk_branch2_ops,
1088 		},
1089 	},
1090 };
1091 
1092 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
1093 	.halt_reg = 0x400c,
1094 	.halt_check = BRANCH_HALT,
1095 	.clkr = {
1096 		.enable_reg = 0x400c,
1097 		.enable_mask = BIT(0),
1098 		.hw.init = &(const struct clk_init_data) {
1099 			.name = "disp_cc_mdss_rscc_ahb_clk",
1100 			.parent_hws = (const struct clk_hw*[]){
1101 				&disp_cc_mdss_ahb_clk_src.clkr.hw,
1102 			},
1103 			.num_parents = 1,
1104 			.flags = CLK_SET_RATE_PARENT,
1105 			.ops = &clk_branch2_ops,
1106 		},
1107 	},
1108 };
1109 
1110 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
1111 	.halt_reg = 0x4008,
1112 	.halt_check = BRANCH_HALT,
1113 	.clkr = {
1114 		.enable_reg = 0x4008,
1115 		.enable_mask = BIT(0),
1116 		.hw.init = &(const struct clk_init_data) {
1117 			.name = "disp_cc_mdss_rscc_vsync_clk",
1118 			.parent_hws = (const struct clk_hw*[]){
1119 				&disp_cc_mdss_vsync_clk_src.clkr.hw,
1120 			},
1121 			.num_parents = 1,
1122 			.flags = CLK_SET_RATE_PARENT,
1123 			.ops = &clk_branch2_ops,
1124 		},
1125 	},
1126 };
1127 
1128 static struct clk_branch disp_cc_mdss_vsync_clk = {
1129 	.halt_reg = 0x2024,
1130 	.halt_check = BRANCH_HALT,
1131 	.clkr = {
1132 		.enable_reg = 0x2024,
1133 		.enable_mask = BIT(0),
1134 		.hw.init = &(const struct clk_init_data) {
1135 			.name = "disp_cc_mdss_vsync_clk",
1136 			.parent_hws = (const struct clk_hw*[]){
1137 				&disp_cc_mdss_vsync_clk_src.clkr.hw,
1138 			},
1139 			.num_parents = 1,
1140 			.flags = CLK_SET_RATE_PARENT,
1141 			.ops = &clk_branch2_ops,
1142 		},
1143 	},
1144 };
1145 
1146 static struct gdsc mdss_gdsc = {
1147 	.gdscr = 0x3000,
1148 	.en_rest_wait_val = 0x2,
1149 	.en_few_wait_val = 0x2,
1150 	.clk_dis_wait_val = 0xf,
1151 	.pd = {
1152 		.name = "mdss_gdsc",
1153 	},
1154 	.pwrsts = PWRSTS_OFF_ON,
1155 	.flags = HW_CTRL | RETAIN_FF_ENABLE,
1156 };
1157 
1158 static struct clk_regmap *disp_cc_sm8250_clocks[] = {
1159 	[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
1160 	[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
1161 	[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
1162 	[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
1163 	[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
1164 	[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
1165 	[DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
1166 	[DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
1167 	[DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr,
1168 	[DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
1169 	[DISP_CC_MDSS_DP_AUX1_CLK] = &disp_cc_mdss_dp_aux1_clk.clkr,
1170 	[DISP_CC_MDSS_DP_AUX1_CLK_SRC] = &disp_cc_mdss_dp_aux1_clk_src.clkr,
1171 	[DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
1172 	[DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
1173 	[DISP_CC_MDSS_DP_LINK1_CLK] = &disp_cc_mdss_dp_link1_clk.clkr,
1174 	[DISP_CC_MDSS_DP_LINK1_CLK_SRC] = &disp_cc_mdss_dp_link1_clk_src.clkr,
1175 	[DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = &disp_cc_mdss_dp_link1_div_clk_src.clkr,
1176 	[DISP_CC_MDSS_DP_LINK1_INTF_CLK] = &disp_cc_mdss_dp_link1_intf_clk.clkr,
1177 	[DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
1178 	[DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
1179 	[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dp_link_div_clk_src.clkr,
1180 	[DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
1181 	[DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr,
1182 	[DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] = &disp_cc_mdss_dp_pixel1_clk_src.clkr,
1183 	[DISP_CC_MDSS_DP_PIXEL2_CLK] = &disp_cc_mdss_dp_pixel2_clk.clkr,
1184 	[DISP_CC_MDSS_DP_PIXEL2_CLK_SRC] = &disp_cc_mdss_dp_pixel2_clk_src.clkr,
1185 	[DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
1186 	[DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
1187 	[DISP_CC_MDSS_EDP_AUX_CLK] = &disp_cc_mdss_edp_aux_clk.clkr,
1188 	[DISP_CC_MDSS_EDP_AUX_CLK_SRC] = &disp_cc_mdss_edp_aux_clk_src.clkr,
1189 	[DISP_CC_MDSS_EDP_GTC_CLK] = &disp_cc_mdss_edp_gtc_clk.clkr,
1190 	[DISP_CC_MDSS_EDP_GTC_CLK_SRC] = &disp_cc_mdss_edp_gtc_clk_src.clkr,
1191 	[DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr,
1192 	[DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr,
1193 	[DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_edp_link_div_clk_src.clkr,
1194 	[DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr,
1195 	[DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr,
1196 	[DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr,
1197 	[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
1198 	[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
1199 	[DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
1200 	[DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
1201 	[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
1202 	[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
1203 	[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
1204 	[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
1205 	[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
1206 	[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
1207 	[DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
1208 	[DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
1209 	[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
1210 	[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
1211 	[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
1212 	[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
1213 	[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
1214 	[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
1215 	[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
1216 	[DISP_CC_PLL1] = &disp_cc_pll1.clkr,
1217 };
1218 
1219 static const struct qcom_reset_map disp_cc_sm8250_resets[] = {
1220 	[DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
1221 	[DISP_CC_MDSS_RSCC_BCR] = { 0x4000 },
1222 };
1223 
1224 static struct gdsc *disp_cc_sm8250_gdscs[] = {
1225 	[MDSS_GDSC] = &mdss_gdsc,
1226 };
1227 
1228 static const struct regmap_config disp_cc_sm8250_regmap_config = {
1229 	.reg_bits	= 32,
1230 	.reg_stride	= 4,
1231 	.val_bits	= 32,
1232 	.max_register	= 0x10000,
1233 	.fast_io	= true,
1234 };
1235 
1236 static const struct qcom_cc_desc disp_cc_sm8250_desc = {
1237 	.config = &disp_cc_sm8250_regmap_config,
1238 	.clks = disp_cc_sm8250_clocks,
1239 	.num_clks = ARRAY_SIZE(disp_cc_sm8250_clocks),
1240 	.resets = disp_cc_sm8250_resets,
1241 	.num_resets = ARRAY_SIZE(disp_cc_sm8250_resets),
1242 	.gdscs = disp_cc_sm8250_gdscs,
1243 	.num_gdscs = ARRAY_SIZE(disp_cc_sm8250_gdscs),
1244 };
1245 
1246 static const struct of_device_id disp_cc_sm8250_match_table[] = {
1247 	{ .compatible = "qcom,sc8180x-dispcc" },
1248 	{ .compatible = "qcom,sm8150-dispcc" },
1249 	{ .compatible = "qcom,sm8250-dispcc" },
1250 	{ .compatible = "qcom,sm8350-dispcc" },
1251 	{ }
1252 };
1253 MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table);
1254 
disp_cc_sm8250_probe(struct platform_device * pdev)1255 static int disp_cc_sm8250_probe(struct platform_device *pdev)
1256 {
1257 	struct regmap *regmap;
1258 	int ret;
1259 
1260 	ret = devm_pm_runtime_enable(&pdev->dev);
1261 	if (ret)
1262 		return ret;
1263 
1264 	ret = pm_runtime_resume_and_get(&pdev->dev);
1265 	if (ret)
1266 		return ret;
1267 
1268 	regmap = qcom_cc_map(pdev, &disp_cc_sm8250_desc);
1269 	if (IS_ERR(regmap)) {
1270 		pm_runtime_put(&pdev->dev);
1271 		return PTR_ERR(regmap);
1272 	}
1273 
1274 	/* Apply differences for SM8150 and SM8350 */
1275 	BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID);
1276 	if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") ||
1277 	    of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) {
1278 		disp_cc_pll0_config.config_ctl_hi_val = 0x00002267;
1279 		disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024;
1280 		disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0;
1281 		disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops;
1282 		disp_cc_pll1_config.config_ctl_hi_val = 0x00002267;
1283 		disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024;
1284 		disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0;
1285 		disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops;
1286 
1287 		disp_cc_mdss_dp_link_intf_clk.clkr.hw.init->parent_hws[0] =
1288 			&disp_cc_mdss_dp_link_clk_src.clkr.hw;
1289 		disp_cc_mdss_dp_link1_intf_clk.clkr.hw.init->parent_hws[0] =
1290 			&disp_cc_mdss_dp_link1_clk_src.clkr.hw;
1291 		disp_cc_mdss_edp_link_intf_clk.clkr.hw.init->parent_hws[0] =
1292 			&disp_cc_mdss_edp_link_clk_src.clkr.hw;
1293 
1294 		disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = NULL;
1295 		disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = NULL;
1296 		disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] = NULL;
1297 	} else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) {
1298 		static struct clk_rcg2 * const rcgs[] = {
1299 			&disp_cc_mdss_byte0_clk_src,
1300 			&disp_cc_mdss_byte1_clk_src,
1301 			&disp_cc_mdss_dp_aux1_clk_src,
1302 			&disp_cc_mdss_dp_aux_clk_src,
1303 			&disp_cc_mdss_dp_link1_clk_src,
1304 			&disp_cc_mdss_dp_link_clk_src,
1305 			&disp_cc_mdss_dp_pixel1_clk_src,
1306 			&disp_cc_mdss_dp_pixel2_clk_src,
1307 			&disp_cc_mdss_dp_pixel_clk_src,
1308 			&disp_cc_mdss_edp_aux_clk_src,
1309 			&disp_cc_mdss_edp_link_clk_src,
1310 			&disp_cc_mdss_edp_pixel_clk_src,
1311 			&disp_cc_mdss_esc0_clk_src,
1312 			&disp_cc_mdss_esc1_clk_src,
1313 			&disp_cc_mdss_mdp_clk_src,
1314 			&disp_cc_mdss_pclk0_clk_src,
1315 			&disp_cc_mdss_pclk1_clk_src,
1316 			&disp_cc_mdss_rot_clk_src,
1317 			&disp_cc_mdss_vsync_clk_src,
1318 		};
1319 		static struct clk_regmap_div * const divs[] = {
1320 			&disp_cc_mdss_byte0_div_clk_src,
1321 			&disp_cc_mdss_byte1_div_clk_src,
1322 			&disp_cc_mdss_dp_link1_div_clk_src,
1323 			&disp_cc_mdss_dp_link_div_clk_src,
1324 			&disp_cc_mdss_edp_link_div_clk_src,
1325 		};
1326 		unsigned int i;
1327 		static bool offset_applied;
1328 
1329 		/*
1330 		 * note: trion == lucid, except for the prepare() op
1331 		 * only apply the offsets once (in case of deferred probe)
1332 		 */
1333 		if (!offset_applied) {
1334 			for (i = 0; i < ARRAY_SIZE(rcgs); i++)
1335 				rcgs[i]->cmd_rcgr -= 4;
1336 
1337 			for (i = 0; i < ARRAY_SIZE(divs); i++) {
1338 				divs[i]->reg -= 4;
1339 				divs[i]->width = 4;
1340 			}
1341 
1342 			disp_cc_mdss_ahb_clk.halt_reg -= 4;
1343 			disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4;
1344 
1345 			offset_applied = true;
1346 		}
1347 
1348 		disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0;
1349 
1350 		disp_cc_pll0_config.config_ctl_hi1_val = 0x2a9a699c;
1351 		disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000;
1352 		disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
1353 		disp_cc_pll0.vco_table = lucid_5lpe_vco;
1354 		disp_cc_pll1_config.config_ctl_hi1_val = 0x2a9a699c;
1355 		disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000;
1356 		disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
1357 		disp_cc_pll1.vco_table = lucid_5lpe_vco;
1358 
1359 		disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK] = NULL;
1360 		disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK_SRC] = NULL;
1361 	}
1362 
1363 	if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) {
1364 		clk_lucid_5lpe_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
1365 		clk_lucid_5lpe_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
1366 	} else {
1367 		clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
1368 		clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
1369 	}
1370 
1371 	/* Enable clock gating for MDP clocks */
1372 	regmap_update_bits(regmap, 0x8000, 0x10, 0x10);
1373 
1374 	/* Keep some clocks always-on */
1375 	qcom_branch_set_clk_en(regmap, 0x605c); /* DISP_CC_XO_CLK */
1376 
1377 	ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8250_desc, regmap);
1378 
1379 	pm_runtime_put(&pdev->dev);
1380 
1381 	return ret;
1382 }
1383 
1384 static struct platform_driver disp_cc_sm8250_driver = {
1385 	.probe = disp_cc_sm8250_probe,
1386 	.driver = {
1387 		.name = "disp_cc-sm8250",
1388 		.of_match_table = disp_cc_sm8250_match_table,
1389 	},
1390 };
1391 
1392 module_platform_driver(disp_cc_sm8250_driver);
1393 
1394 MODULE_DESCRIPTION("QTI DISPCC SM8250 Driver");
1395 MODULE_LICENSE("GPL v2");
1396