1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,dispcc-sm6125.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "common.h" 19 #include "gdsc.h" 20 #include "reset.h" 21 22 enum { 23 P_BI_TCXO, 24 P_DISP_CC_PLL0_OUT_MAIN, 25 P_DP_PHY_PLL_LINK_CLK, 26 P_DP_PHY_PLL_VCO_DIV_CLK, 27 P_DSI0_PHY_PLL_OUT_BYTECLK, 28 P_DSI0_PHY_PLL_OUT_DSICLK, 29 P_DSI1_PHY_PLL_OUT_DSICLK, 30 P_GPLL0_OUT_MAIN, 31 }; 32 33 static const struct pll_vco disp_cc_pll_vco[] = { 34 { 500000000, 1000000000, 2 }, 35 }; 36 37 static struct clk_alpha_pll disp_cc_pll0 = { 38 .offset = 0x0, 39 .vco_table = disp_cc_pll_vco, 40 .num_vco = ARRAY_SIZE(disp_cc_pll_vco), 41 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 42 .flags = SUPPORTS_DYNAMIC_UPDATE, 43 .clkr = { 44 .hw.init = &(struct clk_init_data){ 45 .name = "disp_cc_pll0", 46 .parent_data = &(const struct clk_parent_data){ 47 .fw_name = "bi_tcxo", 48 }, 49 .num_parents = 1, 50 .ops = &clk_alpha_pll_ops, 51 }, 52 }, 53 }; 54 55 /* 768MHz configuration */ 56 static const struct alpha_pll_config disp_cc_pll0_config = { 57 .l = 0x28, 58 .vco_val = 0x2 << 20, 59 .vco_mask = 0x3 << 20, 60 .main_output_mask = BIT(0), 61 .config_ctl_val = 0x4001055b, 62 }; 63 64 static const struct parent_map disp_cc_parent_map_0[] = { 65 { P_BI_TCXO, 0 }, 66 }; 67 68 static const struct clk_parent_data disp_cc_parent_data_0[] = { 69 { .fw_name = "bi_tcxo" }, 70 }; 71 72 static const struct parent_map disp_cc_parent_map_1[] = { 73 { P_BI_TCXO, 0 }, 74 { P_DP_PHY_PLL_LINK_CLK, 1 }, 75 { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, 76 }; 77 78 static const struct clk_parent_data disp_cc_parent_data_1[] = { 79 { .fw_name = "bi_tcxo" }, 80 { .fw_name = "dp_phy_pll_link_clk" }, 81 { .fw_name = "dp_phy_pll_vco_div_clk" }, 82 }; 83 84 static const struct parent_map disp_cc_parent_map_2[] = { 85 { P_BI_TCXO, 0 }, 86 { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, 87 }; 88 89 static const struct clk_parent_data disp_cc_parent_data_2[] = { 90 { .fw_name = "bi_tcxo" }, 91 { .fw_name = "dsi0_phy_pll_out_byteclk" }, 92 }; 93 94 static const struct parent_map disp_cc_parent_map_3[] = { 95 { P_BI_TCXO, 0 }, 96 { P_DISP_CC_PLL0_OUT_MAIN, 1 }, 97 { P_GPLL0_OUT_MAIN, 4 }, 98 }; 99 100 static const struct clk_parent_data disp_cc_parent_data_3[] = { 101 { .fw_name = "bi_tcxo" }, 102 { .hw = &disp_cc_pll0.clkr.hw }, 103 { .fw_name = "gcc_disp_gpll0_div_clk_src" }, 104 }; 105 106 static const struct parent_map disp_cc_parent_map_4[] = { 107 { P_BI_TCXO, 0 }, 108 { P_GPLL0_OUT_MAIN, 4 }, 109 }; 110 111 static const struct clk_parent_data disp_cc_parent_data_4[] = { 112 { .fw_name = "bi_tcxo" }, 113 { .fw_name = "gcc_disp_gpll0_div_clk_src" }, 114 }; 115 116 static const struct parent_map disp_cc_parent_map_5[] = { 117 { P_BI_TCXO, 0 }, 118 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 119 { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, 120 }; 121 122 static const struct clk_parent_data disp_cc_parent_data_5[] = { 123 { .fw_name = "bi_tcxo" }, 124 { .fw_name = "dsi0_phy_pll_out_dsiclk" }, 125 { .fw_name = "dsi1_phy_pll_out_dsiclk" }, 126 }; 127 128 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { 129 F(19200000, P_BI_TCXO, 1, 0, 0), 130 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0), 131 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 132 { } 133 }; 134 135 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { 136 .cmd_rcgr = 0x2154, 137 .mnd_width = 0, 138 .hid_width = 5, 139 .parent_map = disp_cc_parent_map_4, 140 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 141 .clkr.hw.init = &(struct clk_init_data){ 142 .name = "disp_cc_mdss_ahb_clk_src", 143 .parent_data = disp_cc_parent_data_4, 144 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 145 .ops = &clk_rcg2_shared_ops, 146 }, 147 }; 148 149 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { 150 .cmd_rcgr = 0x20bc, 151 .mnd_width = 0, 152 .hid_width = 5, 153 .parent_map = disp_cc_parent_map_2, 154 .clkr.hw.init = &(struct clk_init_data){ 155 .name = "disp_cc_mdss_byte0_clk_src", 156 .parent_data = disp_cc_parent_data_2, 157 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 158 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 159 .ops = &clk_byte2_ops, 160 }, 161 }; 162 163 static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux1_clk_src[] = { 164 F(19200000, P_BI_TCXO, 1, 0, 0), 165 { } 166 }; 167 168 static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { 169 .cmd_rcgr = 0x213c, 170 .mnd_width = 0, 171 .hid_width = 5, 172 .parent_map = disp_cc_parent_map_0, 173 .freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src, 174 .clkr.hw.init = &(struct clk_init_data){ 175 .name = "disp_cc_mdss_dp_aux_clk_src", 176 .parent_data = disp_cc_parent_data_0, 177 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 178 .ops = &clk_rcg2_ops, 179 }, 180 }; 181 182 static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = { 183 F( 180000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0), 184 F( 360000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0), 185 { } 186 }; 187 188 static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { 189 .cmd_rcgr = 0x210c, 190 .mnd_width = 0, 191 .hid_width = 5, 192 .parent_map = disp_cc_parent_map_1, 193 .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, 194 .clkr.hw.init = &(struct clk_init_data){ 195 .name = "disp_cc_mdss_dp_crypto_clk_src", 196 .parent_data = disp_cc_parent_data_1, 197 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 198 .flags = CLK_GET_RATE_NOCACHE, 199 .ops = &clk_rcg2_ops, 200 }, 201 }; 202 203 static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { 204 F( 162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), 205 F( 270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), 206 F( 540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), 207 { } 208 }; 209 210 static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { 211 .cmd_rcgr = 0x20f0, 212 .mnd_width = 0, 213 .hid_width = 5, 214 .parent_map = disp_cc_parent_map_1, 215 .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, 216 .clkr.hw.init = &(struct clk_init_data){ 217 .name = "disp_cc_mdss_dp_link_clk_src", 218 .parent_data = disp_cc_parent_data_1, 219 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 220 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 221 .ops = &clk_rcg2_ops, 222 }, 223 }; 224 225 static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { 226 .cmd_rcgr = 0x2124, 227 .mnd_width = 16, 228 .hid_width = 5, 229 .parent_map = disp_cc_parent_map_1, 230 .clkr.hw.init = &(struct clk_init_data){ 231 .name = "disp_cc_mdss_dp_pixel_clk_src", 232 .parent_data = disp_cc_parent_data_1, 233 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 234 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 235 .ops = &clk_dp_ops, 236 }, 237 }; 238 239 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { 240 .cmd_rcgr = 0x20d8, 241 .mnd_width = 0, 242 .hid_width = 5, 243 .parent_map = disp_cc_parent_map_2, 244 .freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src, 245 .clkr.hw.init = &(struct clk_init_data){ 246 .name = "disp_cc_mdss_esc0_clk_src", 247 .parent_data = disp_cc_parent_data_2, 248 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 249 .ops = &clk_rcg2_ops, 250 }, 251 }; 252 253 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { 254 F(19200000, P_BI_TCXO, 1, 0, 0), 255 F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), 256 F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 257 F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 258 F(384000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0), 259 F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0), 260 { } 261 }; 262 263 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { 264 .cmd_rcgr = 0x2074, 265 .mnd_width = 0, 266 .hid_width = 5, 267 .parent_map = disp_cc_parent_map_3, 268 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 269 .clkr.hw.init = &(struct clk_init_data){ 270 .name = "disp_cc_mdss_mdp_clk_src", 271 .parent_data = disp_cc_parent_data_3, 272 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 273 .ops = &clk_rcg2_shared_ops, 274 }, 275 }; 276 277 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { 278 .cmd_rcgr = 0x205c, 279 .mnd_width = 8, 280 .hid_width = 5, 281 .parent_map = disp_cc_parent_map_5, 282 .clkr.hw.init = &(struct clk_init_data){ 283 .name = "disp_cc_mdss_pclk0_clk_src", 284 .parent_data = disp_cc_parent_data_5, 285 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 286 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 287 .ops = &clk_pixel_ops, 288 }, 289 }; 290 291 static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = { 292 F(19200000, P_BI_TCXO, 1, 0, 0), 293 F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), 294 F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 295 F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 296 { } 297 }; 298 299 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { 300 .cmd_rcgr = 0x208c, 301 .mnd_width = 0, 302 .hid_width = 5, 303 .parent_map = disp_cc_parent_map_3, 304 .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, 305 .clkr.hw.init = &(struct clk_init_data){ 306 .name = "disp_cc_mdss_rot_clk_src", 307 .parent_data = disp_cc_parent_data_3, 308 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 309 .flags = CLK_SET_RATE_PARENT, 310 .ops = &clk_rcg2_shared_ops, 311 }, 312 }; 313 314 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { 315 .cmd_rcgr = 0x20a4, 316 .mnd_width = 0, 317 .hid_width = 5, 318 .parent_map = disp_cc_parent_map_0, 319 .freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src, 320 .clkr.hw.init = &(struct clk_init_data){ 321 .name = "disp_cc_mdss_vsync_clk_src", 322 .parent_data = disp_cc_parent_data_0, 323 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 324 .ops = &clk_rcg2_ops, 325 }, 326 }; 327 328 static struct clk_branch disp_cc_mdss_ahb_clk = { 329 .halt_reg = 0x2044, 330 .halt_check = BRANCH_HALT, 331 .clkr = { 332 .enable_reg = 0x2044, 333 .enable_mask = BIT(0), 334 .hw.init = &(struct clk_init_data){ 335 .name = "disp_cc_mdss_ahb_clk", 336 .parent_hws = (const struct clk_hw*[]){ 337 &disp_cc_mdss_ahb_clk_src.clkr.hw, 338 }, 339 .num_parents = 1, 340 .flags = CLK_SET_RATE_PARENT, 341 .ops = &clk_branch2_ops, 342 }, 343 }, 344 }; 345 346 static struct clk_branch disp_cc_mdss_byte0_clk = { 347 .halt_reg = 0x2024, 348 .halt_check = BRANCH_HALT, 349 .clkr = { 350 .enable_reg = 0x2024, 351 .enable_mask = BIT(0), 352 .hw.init = &(struct clk_init_data){ 353 .name = "disp_cc_mdss_byte0_clk", 354 .parent_hws = (const struct clk_hw*[]){ 355 &disp_cc_mdss_byte0_clk_src.clkr.hw, 356 }, 357 .num_parents = 1, 358 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 359 .ops = &clk_branch2_ops, 360 }, 361 }, 362 }; 363 364 static struct clk_branch disp_cc_mdss_byte0_intf_clk = { 365 .halt_reg = 0x2028, 366 .halt_check = BRANCH_HALT, 367 .clkr = { 368 .enable_reg = 0x2028, 369 .enable_mask = BIT(0), 370 .hw.init = &(struct clk_init_data){ 371 .name = "disp_cc_mdss_byte0_intf_clk", 372 .parent_hws = (const struct clk_hw*[]){ 373 &disp_cc_mdss_byte0_clk_src.clkr.hw, 374 }, 375 .num_parents = 1, 376 .flags = CLK_GET_RATE_NOCACHE, 377 .ops = &clk_branch2_ops, 378 }, 379 }, 380 }; 381 382 static struct clk_branch disp_cc_mdss_dp_aux_clk = { 383 .halt_reg = 0x2040, 384 .halt_check = BRANCH_HALT, 385 .clkr = { 386 .enable_reg = 0x2040, 387 .enable_mask = BIT(0), 388 .hw.init = &(struct clk_init_data){ 389 .name = "disp_cc_mdss_dp_aux_clk", 390 .parent_hws = (const struct clk_hw*[]){ 391 &disp_cc_mdss_dp_aux_clk_src.clkr.hw, 392 }, 393 .num_parents = 1, 394 .flags = CLK_SET_RATE_PARENT, 395 .ops = &clk_branch2_ops, 396 }, 397 }, 398 }; 399 400 static struct clk_branch disp_cc_mdss_dp_crypto_clk = { 401 .halt_reg = 0x2038, 402 .halt_check = BRANCH_HALT, 403 .clkr = { 404 .enable_reg = 0x2038, 405 .enable_mask = BIT(0), 406 .hw.init = &(struct clk_init_data){ 407 .name = "disp_cc_mdss_dp_crypto_clk", 408 .parent_hws = (const struct clk_hw*[]){ 409 &disp_cc_mdss_dp_crypto_clk_src.clkr.hw, 410 }, 411 .num_parents = 1, 412 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 413 .ops = &clk_branch2_ops, 414 }, 415 }, 416 }; 417 418 static struct clk_branch disp_cc_mdss_dp_link_clk = { 419 .halt_reg = 0x2030, 420 .halt_check = BRANCH_HALT, 421 .clkr = { 422 .enable_reg = 0x2030, 423 .enable_mask = BIT(0), 424 .hw.init = &(struct clk_init_data){ 425 .name = "disp_cc_mdss_dp_link_clk", 426 .parent_hws = (const struct clk_hw*[]){ 427 &disp_cc_mdss_dp_link_clk_src.clkr.hw, 428 }, 429 .num_parents = 1, 430 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 431 .ops = &clk_branch2_ops, 432 }, 433 }, 434 }; 435 436 static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { 437 .halt_reg = 0x2034, 438 .halt_check = BRANCH_HALT, 439 .clkr = { 440 .enable_reg = 0x2034, 441 .enable_mask = BIT(0), 442 .hw.init = &(struct clk_init_data){ 443 .name = "disp_cc_mdss_dp_link_intf_clk", 444 .parent_hws = (const struct clk_hw*[]){ 445 &disp_cc_mdss_dp_link_clk_src.clkr.hw, 446 }, 447 .num_parents = 1, 448 .flags = CLK_GET_RATE_NOCACHE, 449 .ops = &clk_branch2_ops, 450 }, 451 }, 452 }; 453 454 static struct clk_branch disp_cc_mdss_dp_pixel_clk = { 455 .halt_reg = 0x203c, 456 .halt_check = BRANCH_HALT, 457 .clkr = { 458 .enable_reg = 0x203c, 459 .enable_mask = BIT(0), 460 .hw.init = &(struct clk_init_data){ 461 .name = "disp_cc_mdss_dp_pixel_clk", 462 .parent_hws = (const struct clk_hw*[]){ 463 &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, 464 }, 465 .num_parents = 1, 466 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 467 .ops = &clk_branch2_ops, 468 }, 469 }, 470 }; 471 472 static struct clk_branch disp_cc_mdss_esc0_clk = { 473 .halt_reg = 0x202c, 474 .halt_check = BRANCH_HALT, 475 .clkr = { 476 .enable_reg = 0x202c, 477 .enable_mask = BIT(0), 478 .hw.init = &(struct clk_init_data){ 479 .name = "disp_cc_mdss_esc0_clk", 480 .parent_hws = (const struct clk_hw*[]){ 481 &disp_cc_mdss_esc0_clk_src.clkr.hw, 482 }, 483 .num_parents = 1, 484 .flags = CLK_SET_RATE_PARENT, 485 .ops = &clk_branch2_ops, 486 }, 487 }, 488 }; 489 490 static struct clk_branch disp_cc_mdss_mdp_clk = { 491 .halt_reg = 0x2008, 492 .halt_check = BRANCH_HALT, 493 .clkr = { 494 .enable_reg = 0x2008, 495 .enable_mask = BIT(0), 496 .hw.init = &(struct clk_init_data){ 497 .name = "disp_cc_mdss_mdp_clk", 498 .parent_hws = (const struct clk_hw*[]){ 499 &disp_cc_mdss_mdp_clk_src.clkr.hw, 500 }, 501 .num_parents = 1, 502 .flags = CLK_SET_RATE_PARENT, 503 .ops = &clk_branch2_ops, 504 }, 505 }, 506 }; 507 508 static struct clk_branch disp_cc_mdss_mdp_lut_clk = { 509 .halt_reg = 0x2018, 510 .halt_check = BRANCH_VOTED, 511 .clkr = { 512 .enable_reg = 0x2018, 513 .enable_mask = BIT(0), 514 .hw.init = &(struct clk_init_data){ 515 .name = "disp_cc_mdss_mdp_lut_clk", 516 .parent_hws = (const struct clk_hw*[]){ 517 &disp_cc_mdss_mdp_clk_src.clkr.hw, 518 }, 519 .num_parents = 1, 520 .ops = &clk_branch2_ops, 521 }, 522 }, 523 }; 524 525 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { 526 .halt_reg = 0x4004, 527 .halt_check = BRANCH_VOTED, 528 .clkr = { 529 .enable_reg = 0x4004, 530 .enable_mask = BIT(0), 531 .hw.init = &(struct clk_init_data){ 532 .name = "disp_cc_mdss_non_gdsc_ahb_clk", 533 .parent_hws = (const struct clk_hw*[]){ 534 &disp_cc_mdss_ahb_clk_src.clkr.hw, 535 }, 536 .num_parents = 1, 537 .flags = CLK_SET_RATE_PARENT, 538 .ops = &clk_branch2_ops, 539 }, 540 }, 541 }; 542 543 static struct clk_branch disp_cc_mdss_pclk0_clk = { 544 .halt_reg = 0x2004, 545 .halt_check = BRANCH_HALT, 546 .clkr = { 547 .enable_reg = 0x2004, 548 .enable_mask = BIT(0), 549 .hw.init = &(struct clk_init_data){ 550 .name = "disp_cc_mdss_pclk0_clk", 551 .parent_hws = (const struct clk_hw*[]){ 552 &disp_cc_mdss_pclk0_clk_src.clkr.hw, 553 }, 554 .num_parents = 1, 555 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 556 .ops = &clk_branch2_ops, 557 }, 558 }, 559 }; 560 561 static struct clk_branch disp_cc_mdss_rot_clk = { 562 .halt_reg = 0x2010, 563 .halt_check = BRANCH_HALT, 564 .clkr = { 565 .enable_reg = 0x2010, 566 .enable_mask = BIT(0), 567 .hw.init = &(struct clk_init_data){ 568 .name = "disp_cc_mdss_rot_clk", 569 .parent_hws = (const struct clk_hw*[]){ 570 &disp_cc_mdss_rot_clk_src.clkr.hw, 571 }, 572 .num_parents = 1, 573 .flags = CLK_SET_RATE_PARENT, 574 .ops = &clk_branch2_ops, 575 }, 576 }, 577 }; 578 579 static struct clk_branch disp_cc_mdss_vsync_clk = { 580 .halt_reg = 0x2020, 581 .halt_check = BRANCH_HALT, 582 .clkr = { 583 .enable_reg = 0x2020, 584 .enable_mask = BIT(0), 585 .hw.init = &(struct clk_init_data){ 586 .name = "disp_cc_mdss_vsync_clk", 587 .parent_hws = (const struct clk_hw*[]){ 588 &disp_cc_mdss_vsync_clk_src.clkr.hw, 589 }, 590 .num_parents = 1, 591 .flags = CLK_SET_RATE_PARENT, 592 .ops = &clk_branch2_ops, 593 }, 594 }, 595 }; 596 597 static struct clk_branch disp_cc_xo_clk = { 598 .halt_reg = 0x604c, 599 .halt_check = BRANCH_HALT, 600 .clkr = { 601 .enable_reg = 0x604c, 602 .enable_mask = BIT(0), 603 .hw.init = &(struct clk_init_data){ 604 .name = "disp_cc_xo_clk", 605 .flags = CLK_IS_CRITICAL, 606 .ops = &clk_branch2_ops, 607 }, 608 }, 609 }; 610 611 static const struct qcom_reset_map disp_cc_sm6125_resets[] = { 612 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 }, 613 }; 614 615 static struct gdsc mdss_gdsc = { 616 .gdscr = 0x3000, 617 .pd = { 618 .name = "mdss_gdsc", 619 }, 620 .pwrsts = PWRSTS_OFF_ON, 621 .flags = HW_CTRL, 622 }; 623 624 static struct clk_regmap *disp_cc_sm6125_clocks[] = { 625 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, 626 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, 627 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, 628 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, 629 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, 630 [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr, 631 [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr, 632 [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr, 633 [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr, 634 [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr, 635 [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr, 636 [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr, 637 [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr, 638 [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr, 639 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, 640 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, 641 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, 642 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, 643 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, 644 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, 645 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, 646 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, 647 [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr, 648 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr, 649 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, 650 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, 651 [DISP_CC_PLL0] = &disp_cc_pll0.clkr, 652 [DISP_CC_XO_CLK] = &disp_cc_xo_clk.clkr, 653 }; 654 655 static struct gdsc *disp_cc_sm6125_gdscs[] = { 656 [MDSS_GDSC] = &mdss_gdsc, 657 }; 658 659 static const struct regmap_config disp_cc_sm6125_regmap_config = { 660 .reg_bits = 32, 661 .reg_stride = 4, 662 .val_bits = 32, 663 .max_register = 0x10000, 664 .fast_io = true, 665 }; 666 667 static const struct qcom_cc_desc disp_cc_sm6125_desc = { 668 .config = &disp_cc_sm6125_regmap_config, 669 .clks = disp_cc_sm6125_clocks, 670 .num_clks = ARRAY_SIZE(disp_cc_sm6125_clocks), 671 .resets = disp_cc_sm6125_resets, 672 .num_resets = ARRAY_SIZE(disp_cc_sm6125_resets), 673 .gdscs = disp_cc_sm6125_gdscs, 674 .num_gdscs = ARRAY_SIZE(disp_cc_sm6125_gdscs), 675 }; 676 677 static const struct of_device_id disp_cc_sm6125_match_table[] = { 678 { .compatible = "qcom,sm6125-dispcc" }, 679 { } 680 }; 681 MODULE_DEVICE_TABLE(of, disp_cc_sm6125_match_table); 682 683 static int disp_cc_sm6125_probe(struct platform_device *pdev) 684 { 685 struct regmap *regmap; 686 687 regmap = qcom_cc_map(pdev, &disp_cc_sm6125_desc); 688 if (IS_ERR(regmap)) 689 return PTR_ERR(regmap); 690 691 clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); 692 693 return qcom_cc_really_probe(&pdev->dev, &disp_cc_sm6125_desc, regmap); 694 } 695 696 static struct platform_driver disp_cc_sm6125_driver = { 697 .probe = disp_cc_sm6125_probe, 698 .driver = { 699 .name = "disp_cc-sm6125", 700 .of_match_table = disp_cc_sm6125_match_table, 701 }, 702 }; 703 704 module_platform_driver(disp_cc_sm6125_driver); 705 706 MODULE_DESCRIPTION("QTI DISPCC SM6125 Driver"); 707 MODULE_LICENSE("GPL v2"); 708