1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Ltd. 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/mod_devicetable.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/pm_clock.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 15 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> 16 17 #include "clk-alpha-pll.h" 18 #include "clk-branch.h" 19 #include "clk-rcg.h" 20 #include "clk-regmap-divider.h" 21 #include "common.h" 22 #include "gdsc.h" 23 #include "reset.h" 24 25 /* Need to match the order of clocks in DT binding */ 26 enum { 27 DT_IFACE, 28 DT_BI_TCXO, 29 DT_SLEEP_CLK, 30 DT_DP0_PHY_PLL_LINK_CLK, 31 DT_DP0_PHY_PLL_VCO_DIV_CLK, 32 DT_DP1_PHY_PLL_LINK_CLK, 33 DT_DP1_PHY_PLL_VCO_DIV_CLK, 34 DT_DP2_PHY_PLL_LINK_CLK, 35 DT_DP2_PHY_PLL_VCO_DIV_CLK, 36 DT_DP3_PHY_PLL_LINK_CLK, 37 DT_DP3_PHY_PLL_VCO_DIV_CLK, 38 DT_DSI0_PHY_PLL_OUT_BYTECLK, 39 DT_DSI0_PHY_PLL_OUT_DSICLK, 40 DT_DSI1_PHY_PLL_OUT_BYTECLK, 41 DT_DSI1_PHY_PLL_OUT_DSICLK, 42 }; 43 44 enum { 45 P_BI_TCXO, 46 P_DP0_PHY_PLL_LINK_CLK, 47 P_DP0_PHY_PLL_VCO_DIV_CLK, 48 P_DP1_PHY_PLL_LINK_CLK, 49 P_DP1_PHY_PLL_VCO_DIV_CLK, 50 P_DP2_PHY_PLL_LINK_CLK, 51 P_DP2_PHY_PLL_VCO_DIV_CLK, 52 P_DP3_PHY_PLL_LINK_CLK, 53 P_DP3_PHY_PLL_VCO_DIV_CLK, 54 P_DSI0_PHY_PLL_OUT_BYTECLK, 55 P_DSI0_PHY_PLL_OUT_DSICLK, 56 P_DSI1_PHY_PLL_OUT_BYTECLK, 57 P_DSI1_PHY_PLL_OUT_DSICLK, 58 P_DISPn_CC_PLL0_OUT_MAIN, 59 P_DISPn_CC_PLL1_OUT_EVEN, 60 P_DISPn_CC_PLL1_OUT_MAIN, 61 P_DISPn_CC_PLL2_OUT_MAIN, 62 P_SLEEP_CLK, 63 }; 64 65 static const struct clk_parent_data parent_data_tcxo = { .index = DT_BI_TCXO }; 66 67 static const struct pll_vco lucid_5lpe_vco[] = { 68 { 249600000, 1800000000, 0 }, 69 }; 70 71 static const struct alpha_pll_config disp_cc_pll0_config = { 72 .l = 0x4e, 73 .alpha = 0x2000, 74 .config_ctl_val = 0x20485699, 75 .config_ctl_hi_val = 0x00002261, 76 .config_ctl_hi1_val = 0x2a9a699c, 77 .test_ctl_val = 0x00000000, 78 .test_ctl_hi_val = 0x00000000, 79 .test_ctl_hi1_val = 0x01800000, 80 .user_ctl_val = 0x00000000, 81 .user_ctl_hi_val = 0x00000805, 82 .user_ctl_hi1_val = 0x00000000, 83 }; 84 85 static struct clk_alpha_pll disp0_cc_pll0 = { 86 .offset = 0x0, 87 .vco_table = lucid_5lpe_vco, 88 .num_vco = ARRAY_SIZE(lucid_5lpe_vco), 89 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 90 .clkr = { 91 .hw.init = &(const struct clk_init_data) { 92 .name = "disp0_cc_pll0", 93 .parent_data = &parent_data_tcxo, 94 .num_parents = 1, 95 .ops = &clk_alpha_pll_lucid_5lpe_ops, 96 }, 97 }, 98 }; 99 100 static struct clk_alpha_pll disp1_cc_pll0 = { 101 .offset = 0x0, 102 .vco_table = lucid_5lpe_vco, 103 .num_vco = ARRAY_SIZE(lucid_5lpe_vco), 104 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 105 .clkr = { 106 .hw.init = &(const struct clk_init_data) { 107 .name = "disp1_cc_pll0", 108 .parent_data = &parent_data_tcxo, 109 .num_parents = 1, 110 .ops = &clk_alpha_pll_lucid_5lpe_ops, 111 }, 112 }, 113 }; 114 115 static const struct alpha_pll_config disp_cc_pll1_config = { 116 .l = 0x1f, 117 .alpha = 0x4000, 118 .config_ctl_val = 0x20485699, 119 .config_ctl_hi_val = 0x00002261, 120 .config_ctl_hi1_val = 0x2a9a699c, 121 .test_ctl_val = 0x00000000, 122 .test_ctl_hi_val = 0x00000000, 123 .test_ctl_hi1_val = 0x01800000, 124 .user_ctl_val = 0x00000100, 125 .user_ctl_hi_val = 0x00000805, 126 .user_ctl_hi1_val = 0x00000000, 127 }; 128 129 static struct clk_alpha_pll disp0_cc_pll1 = { 130 .offset = 0x1000, 131 .vco_table = lucid_5lpe_vco, 132 .num_vco = ARRAY_SIZE(lucid_5lpe_vco), 133 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 134 .clkr = { 135 .hw.init = &(const struct clk_init_data) { 136 .name = "disp0_cc_pll1", 137 .parent_data = &parent_data_tcxo, 138 .num_parents = 1, 139 .ops = &clk_alpha_pll_lucid_5lpe_ops, 140 }, 141 }, 142 }; 143 144 static struct clk_alpha_pll disp1_cc_pll1 = { 145 .offset = 0x1000, 146 .vco_table = lucid_5lpe_vco, 147 .num_vco = ARRAY_SIZE(lucid_5lpe_vco), 148 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 149 .clkr = { 150 .hw.init = &(const struct clk_init_data) { 151 .name = "disp1_cc_pll1", 152 .parent_data = &parent_data_tcxo, 153 .num_parents = 1, 154 .ops = &clk_alpha_pll_lucid_5lpe_ops, 155 }, 156 }, 157 }; 158 159 static const struct clk_div_table post_div_table_disp_cc_pll1_out_even[] = { 160 { 0x1, 2 }, 161 { } 162 }; 163 164 static struct clk_alpha_pll_postdiv disp0_cc_pll1_out_even = { 165 .offset = 0x1000, 166 .post_div_shift = 8, 167 .post_div_table = post_div_table_disp_cc_pll1_out_even, 168 .num_post_div = ARRAY_SIZE(post_div_table_disp_cc_pll1_out_even), 169 .width = 4, 170 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 171 .clkr.hw.init = &(const struct clk_init_data) { 172 .name = "disp0_cc_pll1_out_even", 173 .parent_hws = (const struct clk_hw*[]){ 174 &disp0_cc_pll1.clkr.hw, 175 }, 176 .num_parents = 1, 177 .ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops, 178 }, 179 }; 180 181 static struct clk_alpha_pll_postdiv disp1_cc_pll1_out_even = { 182 .offset = 0x1000, 183 .post_div_shift = 8, 184 .post_div_table = post_div_table_disp_cc_pll1_out_even, 185 .num_post_div = ARRAY_SIZE(post_div_table_disp_cc_pll1_out_even), 186 .width = 4, 187 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 188 .clkr.hw.init = &(const struct clk_init_data) { 189 .name = "disp1_cc_pll1_out_even", 190 .parent_hws = (const struct clk_hw*[]){ 191 &disp1_cc_pll1.clkr.hw, 192 }, 193 .num_parents = 1, 194 .ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops, 195 }, 196 }; 197 198 static const struct alpha_pll_config disp_cc_pll2_config = { 199 .l = 0x46, 200 .alpha = 0x5000, 201 .config_ctl_val = 0x20485699, 202 .config_ctl_hi_val = 0x00002261, 203 .config_ctl_hi1_val = 0x2a9a699c, 204 .test_ctl_val = 0x00000000, 205 .test_ctl_hi_val = 0x00000000, 206 .test_ctl_hi1_val = 0x01800000, 207 .user_ctl_val = 0x00000000, 208 .user_ctl_hi_val = 0x00000805, 209 .user_ctl_hi1_val = 0x00000000, 210 }; 211 212 static struct clk_alpha_pll disp0_cc_pll2 = { 213 .offset = 0x9000, 214 .vco_table = lucid_5lpe_vco, 215 .num_vco = ARRAY_SIZE(lucid_5lpe_vco), 216 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 217 .clkr = { 218 .hw.init = &(const struct clk_init_data) { 219 .name = "disp0_cc_pll2", 220 .parent_data = &parent_data_tcxo, 221 .num_parents = 1, 222 .ops = &clk_alpha_pll_lucid_5lpe_ops, 223 }, 224 }, 225 }; 226 227 static struct clk_alpha_pll disp1_cc_pll2 = { 228 .offset = 0x9000, 229 .vco_table = lucid_5lpe_vco, 230 .num_vco = ARRAY_SIZE(lucid_5lpe_vco), 231 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 232 .clkr = { 233 .hw.init = &(const struct clk_init_data) { 234 .name = "disp1_cc_pll2", 235 .parent_data = &parent_data_tcxo, 236 .num_parents = 1, 237 .ops = &clk_alpha_pll_lucid_5lpe_ops, 238 }, 239 }, 240 }; 241 242 static const struct parent_map disp_cc_parent_map_0[] = { 243 { P_BI_TCXO, 0 }, 244 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 245 { P_DP1_PHY_PLL_LINK_CLK, 2 }, 246 { P_DP2_PHY_PLL_LINK_CLK, 3 }, 247 { P_DP3_PHY_PLL_LINK_CLK, 4 }, 248 { P_DISPn_CC_PLL2_OUT_MAIN, 5 }, 249 }; 250 251 static const struct clk_parent_data disp0_cc_parent_data_0[] = { 252 { .index = DT_BI_TCXO }, 253 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 254 { .index = DT_DP1_PHY_PLL_LINK_CLK }, 255 { .index = DT_DP2_PHY_PLL_LINK_CLK }, 256 { .index = DT_DP3_PHY_PLL_LINK_CLK }, 257 { .hw = &disp0_cc_pll2.clkr.hw }, 258 }; 259 260 static const struct clk_parent_data disp1_cc_parent_data_0[] = { 261 { .index = DT_BI_TCXO }, 262 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 263 { .index = DT_DP1_PHY_PLL_LINK_CLK }, 264 { .index = DT_DP2_PHY_PLL_LINK_CLK }, 265 { .index = DT_DP3_PHY_PLL_LINK_CLK }, 266 { .hw = &disp1_cc_pll2.clkr.hw }, 267 }; 268 269 static const struct parent_map disp_cc_parent_map_1[] = { 270 { P_BI_TCXO, 0 }, 271 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 272 { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 }, 273 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, 274 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, 275 { P_DISPn_CC_PLL2_OUT_MAIN, 5 }, 276 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, 277 }; 278 279 static const struct clk_parent_data disp0_cc_parent_data_1[] = { 280 { .index = DT_BI_TCXO }, 281 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 282 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK }, 283 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 284 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 285 { .hw = &disp0_cc_pll2.clkr.hw }, 286 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 287 }; 288 289 static const struct clk_parent_data disp1_cc_parent_data_1[] = { 290 { .index = DT_BI_TCXO }, 291 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 292 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK }, 293 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 294 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 295 { .hw = &disp1_cc_pll2.clkr.hw }, 296 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 297 }; 298 299 static const struct parent_map disp_cc_parent_map_2[] = { 300 { P_BI_TCXO, 0 }, 301 }; 302 303 static const struct clk_parent_data disp_cc_parent_data_2[] = { 304 { .index = DT_BI_TCXO }, 305 }; 306 307 static const struct parent_map disp_cc_parent_map_3[] = { 308 { P_BI_TCXO, 0 }, 309 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 310 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 311 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, 312 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 313 }; 314 315 static const struct clk_parent_data disp_cc_parent_data_3[] = { 316 { .index = DT_BI_TCXO }, 317 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, 318 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 319 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, 320 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 321 }; 322 323 static const struct parent_map disp_cc_parent_map_4[] = { 324 { P_BI_TCXO, 0 }, 325 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 326 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 327 }; 328 329 static const struct clk_parent_data disp_cc_parent_data_4[] = { 330 { .index = DT_BI_TCXO }, 331 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 332 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 333 }; 334 335 static const struct parent_map disp_cc_parent_map_5[] = { 336 { P_BI_TCXO, 0 }, 337 { P_DISPn_CC_PLL0_OUT_MAIN, 1 }, 338 { P_DISPn_CC_PLL1_OUT_MAIN, 4 }, 339 { P_DISPn_CC_PLL2_OUT_MAIN, 5 }, 340 { P_DISPn_CC_PLL1_OUT_EVEN, 6 }, 341 }; 342 343 static const struct clk_parent_data disp0_cc_parent_data_5[] = { 344 { .index = DT_BI_TCXO }, 345 { .hw = &disp0_cc_pll0.clkr.hw }, 346 { .hw = &disp0_cc_pll1.clkr.hw }, 347 { .hw = &disp0_cc_pll2.clkr.hw }, 348 { .hw = &disp0_cc_pll1_out_even.clkr.hw }, 349 }; 350 351 static const struct clk_parent_data disp1_cc_parent_data_5[] = { 352 { .index = DT_BI_TCXO }, 353 { .hw = &disp1_cc_pll0.clkr.hw }, 354 { .hw = &disp1_cc_pll1.clkr.hw }, 355 { .hw = &disp1_cc_pll2.clkr.hw }, 356 { .hw = &disp1_cc_pll1_out_even.clkr.hw }, 357 }; 358 359 static const struct parent_map disp_cc_parent_map_6[] = { 360 { P_BI_TCXO, 0 }, 361 { P_DISPn_CC_PLL1_OUT_MAIN, 4 }, 362 { P_DISPn_CC_PLL1_OUT_EVEN, 6 }, 363 }; 364 365 static const struct clk_parent_data disp0_cc_parent_data_6[] = { 366 { .index = DT_BI_TCXO }, 367 { .hw = &disp0_cc_pll1.clkr.hw }, 368 { .hw = &disp0_cc_pll1_out_even.clkr.hw }, 369 }; 370 371 static const struct clk_parent_data disp1_cc_parent_data_6[] = { 372 { .index = DT_BI_TCXO }, 373 { .hw = &disp1_cc_pll1.clkr.hw }, 374 { .hw = &disp1_cc_pll1_out_even.clkr.hw }, 375 }; 376 377 static const struct parent_map disp_cc_parent_map_7[] = { 378 { P_SLEEP_CLK, 0 }, 379 }; 380 381 static const struct clk_parent_data disp_cc_parent_data_7[] = { 382 { .index = DT_SLEEP_CLK }, 383 }; 384 385 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { 386 F(19200000, P_BI_TCXO, 1, 0, 0), 387 F(37500000, P_DISPn_CC_PLL1_OUT_EVEN, 8, 0, 0), 388 F(75000000, P_DISPn_CC_PLL1_OUT_MAIN, 8, 0, 0), 389 { } 390 }; 391 392 static struct clk_rcg2 disp0_cc_mdss_ahb_clk_src = { 393 .cmd_rcgr = 0x2364, 394 .mnd_width = 0, 395 .hid_width = 5, 396 .parent_map = disp_cc_parent_map_6, 397 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 398 .clkr.hw.init = &(const struct clk_init_data) { 399 .name = "disp0_cc_mdss_ahb_clk_src", 400 .parent_data = disp0_cc_parent_data_6, 401 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_6), 402 .ops = &clk_rcg2_shared_ops, 403 }, 404 }; 405 406 static struct clk_rcg2 disp1_cc_mdss_ahb_clk_src = { 407 .cmd_rcgr = 0x2364, 408 .mnd_width = 0, 409 .hid_width = 5, 410 .parent_map = disp_cc_parent_map_6, 411 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 412 .clkr.hw.init = &(const struct clk_init_data) { 413 .name = "disp1_cc_mdss_ahb_clk_src", 414 .parent_data = disp1_cc_parent_data_6, 415 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_6), 416 .ops = &clk_rcg2_shared_ops, 417 }, 418 }; 419 420 static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = { 421 F(19200000, P_BI_TCXO, 1, 0, 0), 422 { } 423 }; 424 425 static struct clk_rcg2 disp0_cc_mdss_byte0_clk_src = { 426 .cmd_rcgr = 0x213c, 427 .mnd_width = 0, 428 .hid_width = 5, 429 .parent_map = disp_cc_parent_map_3, 430 .clkr.hw.init = &(const struct clk_init_data) { 431 .name = "disp0_cc_mdss_byte0_clk_src", 432 .parent_data = disp_cc_parent_data_3, 433 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 434 .flags = CLK_SET_RATE_PARENT, 435 .ops = &clk_byte2_ops, 436 }, 437 }; 438 439 static struct clk_rcg2 disp1_cc_mdss_byte0_clk_src = { 440 .cmd_rcgr = 0x213c, 441 .mnd_width = 0, 442 .hid_width = 5, 443 .parent_map = disp_cc_parent_map_3, 444 .clkr.hw.init = &(const struct clk_init_data) { 445 .name = "disp1_cc_mdss_byte0_clk_src", 446 .parent_data = disp_cc_parent_data_3, 447 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 448 .flags = CLK_SET_RATE_PARENT, 449 .ops = &clk_byte2_ops, 450 }, 451 }; 452 453 static struct clk_rcg2 disp0_cc_mdss_byte1_clk_src = { 454 .cmd_rcgr = 0x2158, 455 .mnd_width = 0, 456 .hid_width = 5, 457 .parent_map = disp_cc_parent_map_3, 458 .clkr.hw.init = &(const struct clk_init_data) { 459 .name = "disp0_cc_mdss_byte1_clk_src", 460 .parent_data = disp_cc_parent_data_3, 461 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 462 .flags = CLK_SET_RATE_PARENT, 463 .ops = &clk_byte2_ops, 464 }, 465 }; 466 467 static struct clk_rcg2 disp1_cc_mdss_byte1_clk_src = { 468 .cmd_rcgr = 0x2158, 469 .mnd_width = 0, 470 .hid_width = 5, 471 .parent_map = disp_cc_parent_map_3, 472 .clkr.hw.init = &(const struct clk_init_data) { 473 .name = "disp1_cc_mdss_byte1_clk_src", 474 .parent_data = disp_cc_parent_data_3, 475 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 476 .flags = CLK_SET_RATE_PARENT, 477 .ops = &clk_byte2_ops, 478 }, 479 }; 480 481 static struct clk_rcg2 disp0_cc_mdss_dptx0_aux_clk_src = { 482 .cmd_rcgr = 0x2238, 483 .mnd_width = 0, 484 .hid_width = 5, 485 .parent_map = disp_cc_parent_map_2, 486 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 487 .clkr.hw.init = &(const struct clk_init_data) { 488 .name = "disp0_cc_mdss_dptx0_aux_clk_src", 489 .parent_data = disp_cc_parent_data_2, 490 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 491 .ops = &clk_rcg2_ops, 492 }, 493 }; 494 495 static struct clk_rcg2 disp1_cc_mdss_dptx0_aux_clk_src = { 496 .cmd_rcgr = 0x2238, 497 .mnd_width = 0, 498 .hid_width = 5, 499 .parent_map = disp_cc_parent_map_2, 500 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 501 .clkr.hw.init = &(const struct clk_init_data) { 502 .name = "disp1_cc_mdss_dptx0_aux_clk_src", 503 .parent_data = disp_cc_parent_data_2, 504 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 505 .ops = &clk_rcg2_ops, 506 }, 507 }; 508 509 static struct clk_rcg2 disp0_cc_mdss_dptx0_link_clk_src = { 510 .cmd_rcgr = 0x21a4, 511 .mnd_width = 0, 512 .hid_width = 5, 513 .parent_map = disp_cc_parent_map_0, 514 .clkr.hw.init = &(const struct clk_init_data) { 515 .name = "disp0_cc_mdss_dptx0_link_clk_src", 516 .parent_data = disp0_cc_parent_data_0, 517 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_0), 518 .flags = CLK_SET_RATE_PARENT, 519 .ops = &clk_byte2_ops, 520 }, 521 }; 522 523 static struct clk_rcg2 disp1_cc_mdss_dptx0_link_clk_src = { 524 .cmd_rcgr = 0x21a4, 525 .mnd_width = 0, 526 .hid_width = 5, 527 .parent_map = disp_cc_parent_map_0, 528 .clkr.hw.init = &(const struct clk_init_data) { 529 .name = "disp1_cc_mdss_dptx0_link_clk_src", 530 .parent_data = disp1_cc_parent_data_0, 531 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_0), 532 .flags = CLK_SET_RATE_PARENT, 533 .ops = &clk_byte2_ops, 534 }, 535 }; 536 537 static struct clk_rcg2 disp0_cc_mdss_dptx0_pixel0_clk_src = { 538 .cmd_rcgr = 0x21d8, 539 .mnd_width = 16, 540 .hid_width = 5, 541 .parent_map = disp_cc_parent_map_1, 542 .clkr.hw.init = &(const struct clk_init_data) { 543 .name = "disp0_cc_mdss_dptx0_pixel0_clk_src", 544 .parent_data = disp0_cc_parent_data_1, 545 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_1), 546 .flags = CLK_SET_RATE_PARENT, 547 .ops = &clk_dp_ops, 548 }, 549 }; 550 551 static struct clk_rcg2 disp1_cc_mdss_dptx0_pixel0_clk_src = { 552 .cmd_rcgr = 0x21d8, 553 .mnd_width = 16, 554 .hid_width = 5, 555 .parent_map = disp_cc_parent_map_1, 556 .clkr.hw.init = &(const struct clk_init_data) { 557 .name = "disp1_cc_mdss_dptx0_pixel0_clk_src", 558 .parent_data = disp1_cc_parent_data_1, 559 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_1), 560 .flags = CLK_SET_RATE_PARENT, 561 .ops = &clk_dp_ops, 562 }, 563 }; 564 565 static struct clk_rcg2 disp0_cc_mdss_dptx0_pixel1_clk_src = { 566 .cmd_rcgr = 0x21f0, 567 .mnd_width = 16, 568 .hid_width = 5, 569 .parent_map = disp_cc_parent_map_1, 570 .clkr.hw.init = &(const struct clk_init_data) { 571 .name = "disp0_cc_mdss_dptx0_pixel1_clk_src", 572 .parent_data = disp0_cc_parent_data_1, 573 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_1), 574 .flags = CLK_SET_RATE_PARENT, 575 .ops = &clk_dp_ops, 576 }, 577 }; 578 579 static struct clk_rcg2 disp1_cc_mdss_dptx0_pixel1_clk_src = { 580 .cmd_rcgr = 0x21f0, 581 .mnd_width = 16, 582 .hid_width = 5, 583 .parent_map = disp_cc_parent_map_1, 584 .clkr.hw.init = &(const struct clk_init_data) { 585 .name = "disp1_cc_mdss_dptx0_pixel1_clk_src", 586 .parent_data = disp1_cc_parent_data_1, 587 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_1), 588 .flags = CLK_SET_RATE_PARENT, 589 .ops = &clk_dp_ops, 590 }, 591 }; 592 593 static struct clk_rcg2 disp0_cc_mdss_dptx1_aux_clk_src = { 594 .cmd_rcgr = 0x22d0, 595 .mnd_width = 0, 596 .hid_width = 5, 597 .parent_map = disp_cc_parent_map_2, 598 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 599 .clkr.hw.init = &(const struct clk_init_data) { 600 .name = "disp0_cc_mdss_dptx1_aux_clk_src", 601 .parent_data = disp_cc_parent_data_2, 602 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 603 .ops = &clk_rcg2_ops, 604 }, 605 }; 606 607 static struct clk_rcg2 disp1_cc_mdss_dptx1_aux_clk_src = { 608 .cmd_rcgr = 0x22d0, 609 .mnd_width = 0, 610 .hid_width = 5, 611 .parent_map = disp_cc_parent_map_2, 612 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 613 .clkr.hw.init = &(const struct clk_init_data) { 614 .name = "disp1_cc_mdss_dptx1_aux_clk_src", 615 .parent_data = disp_cc_parent_data_2, 616 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 617 .ops = &clk_rcg2_ops, 618 }, 619 }; 620 621 static struct clk_rcg2 disp0_cc_mdss_dptx1_link_clk_src = { 622 .cmd_rcgr = 0x2268, 623 .mnd_width = 0, 624 .hid_width = 5, 625 .parent_map = disp_cc_parent_map_0, 626 .clkr.hw.init = &(const struct clk_init_data) { 627 .name = "disp0_cc_mdss_dptx1_link_clk_src", 628 .parent_data = disp0_cc_parent_data_0, 629 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_0), 630 .flags = CLK_SET_RATE_PARENT, 631 .ops = &clk_byte2_ops, 632 }, 633 }; 634 635 static struct clk_rcg2 disp1_cc_mdss_dptx1_link_clk_src = { 636 .cmd_rcgr = 0x2268, 637 .mnd_width = 0, 638 .hid_width = 5, 639 .parent_map = disp_cc_parent_map_0, 640 .clkr.hw.init = &(const struct clk_init_data) { 641 .name = "disp1_cc_mdss_dptx1_link_clk_src", 642 .parent_data = disp1_cc_parent_data_0, 643 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_0), 644 .flags = CLK_SET_RATE_PARENT, 645 .ops = &clk_byte2_ops, 646 }, 647 }; 648 649 static struct clk_rcg2 disp0_cc_mdss_dptx1_pixel0_clk_src = { 650 .cmd_rcgr = 0x2250, 651 .mnd_width = 16, 652 .hid_width = 5, 653 .parent_map = disp_cc_parent_map_1, 654 .clkr.hw.init = &(const struct clk_init_data) { 655 .name = "disp0_cc_mdss_dptx1_pixel0_clk_src", 656 .parent_data = disp0_cc_parent_data_1, 657 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_1), 658 .flags = CLK_SET_RATE_PARENT, 659 .ops = &clk_dp_ops, 660 }, 661 }; 662 663 static struct clk_rcg2 disp1_cc_mdss_dptx1_pixel0_clk_src = { 664 .cmd_rcgr = 0x2250, 665 .mnd_width = 16, 666 .hid_width = 5, 667 .parent_map = disp_cc_parent_map_1, 668 .clkr.hw.init = &(const struct clk_init_data) { 669 .name = "disp1_cc_mdss_dptx1_pixel0_clk_src", 670 .parent_data = disp1_cc_parent_data_1, 671 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_1), 672 .flags = CLK_SET_RATE_PARENT, 673 .ops = &clk_dp_ops, 674 }, 675 }; 676 677 static struct clk_rcg2 disp0_cc_mdss_dptx1_pixel1_clk_src = { 678 .cmd_rcgr = 0x2370, 679 .mnd_width = 16, 680 .hid_width = 5, 681 .parent_map = disp_cc_parent_map_1, 682 .clkr.hw.init = &(const struct clk_init_data) { 683 .name = "disp0_cc_mdss_dptx1_pixel1_clk_src", 684 .parent_data = disp0_cc_parent_data_1, 685 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_1), 686 .flags = CLK_SET_RATE_PARENT, 687 .ops = &clk_dp_ops, 688 }, 689 }; 690 691 static struct clk_rcg2 disp1_cc_mdss_dptx1_pixel1_clk_src = { 692 .cmd_rcgr = 0x2370, 693 .mnd_width = 16, 694 .hid_width = 5, 695 .parent_map = disp_cc_parent_map_1, 696 .clkr.hw.init = &(const struct clk_init_data) { 697 .name = "disp1_cc_mdss_dptx1_pixel1_clk_src", 698 .parent_data = disp1_cc_parent_data_1, 699 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_1), 700 .flags = CLK_SET_RATE_PARENT, 701 .ops = &clk_dp_ops, 702 }, 703 }; 704 705 static struct clk_rcg2 disp0_cc_mdss_dptx2_aux_clk_src = { 706 .cmd_rcgr = 0x22e8, 707 .mnd_width = 0, 708 .hid_width = 5, 709 .parent_map = disp_cc_parent_map_2, 710 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 711 .clkr.hw.init = &(const struct clk_init_data) { 712 .name = "disp0_cc_mdss_dptx2_aux_clk_src", 713 .parent_data = disp_cc_parent_data_2, 714 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 715 .ops = &clk_rcg2_ops, 716 }, 717 }; 718 719 static struct clk_rcg2 disp1_cc_mdss_dptx2_aux_clk_src = { 720 .cmd_rcgr = 0x22e8, 721 .mnd_width = 0, 722 .hid_width = 5, 723 .parent_map = disp_cc_parent_map_2, 724 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 725 .clkr.hw.init = &(const struct clk_init_data) { 726 .name = "disp1_cc_mdss_dptx2_aux_clk_src", 727 .parent_data = disp_cc_parent_data_2, 728 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 729 .ops = &clk_rcg2_ops, 730 }, 731 }; 732 733 static struct clk_rcg2 disp0_cc_mdss_dptx2_link_clk_src = { 734 .cmd_rcgr = 0x2284, 735 .mnd_width = 0, 736 .hid_width = 5, 737 .parent_map = disp_cc_parent_map_0, 738 .clkr.hw.init = &(const struct clk_init_data) { 739 .name = "disp0_cc_mdss_dptx2_link_clk_src", 740 .parent_data = disp0_cc_parent_data_0, 741 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_0), 742 .flags = CLK_SET_RATE_PARENT, 743 .ops = &clk_byte2_ops, 744 }, 745 }; 746 747 static struct clk_rcg2 disp1_cc_mdss_dptx2_link_clk_src = { 748 .cmd_rcgr = 0x2284, 749 .mnd_width = 0, 750 .hid_width = 5, 751 .parent_map = disp_cc_parent_map_0, 752 .clkr.hw.init = &(const struct clk_init_data) { 753 .name = "disp1_cc_mdss_dptx2_link_clk_src", 754 .parent_data = disp1_cc_parent_data_0, 755 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_0), 756 .flags = CLK_SET_RATE_PARENT, 757 .ops = &clk_byte2_ops, 758 }, 759 }; 760 761 static struct clk_rcg2 disp0_cc_mdss_dptx2_pixel0_clk_src = { 762 .cmd_rcgr = 0x2208, 763 .mnd_width = 16, 764 .hid_width = 5, 765 .parent_map = disp_cc_parent_map_1, 766 .clkr.hw.init = &(const struct clk_init_data) { 767 .name = "disp0_cc_mdss_dptx2_pixel0_clk_src", 768 .parent_data = disp0_cc_parent_data_1, 769 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_1), 770 .flags = CLK_SET_RATE_PARENT, 771 .ops = &clk_dp_ops, 772 }, 773 }; 774 775 static struct clk_rcg2 disp1_cc_mdss_dptx2_pixel0_clk_src = { 776 .cmd_rcgr = 0x2208, 777 .mnd_width = 16, 778 .hid_width = 5, 779 .parent_map = disp_cc_parent_map_1, 780 .clkr.hw.init = &(const struct clk_init_data) { 781 .name = "disp1_cc_mdss_dptx2_pixel0_clk_src", 782 .parent_data = disp1_cc_parent_data_1, 783 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_1), 784 .flags = CLK_SET_RATE_PARENT, 785 .ops = &clk_dp_ops, 786 }, 787 }; 788 789 static struct clk_rcg2 disp0_cc_mdss_dptx2_pixel1_clk_src = { 790 .cmd_rcgr = 0x2220, 791 .mnd_width = 16, 792 .hid_width = 5, 793 .parent_map = disp_cc_parent_map_1, 794 .clkr.hw.init = &(const struct clk_init_data) { 795 .name = "disp0_cc_mdss_dptx2_pixel1_clk_src", 796 .parent_data = disp0_cc_parent_data_1, 797 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_1), 798 .flags = CLK_SET_RATE_PARENT, 799 .ops = &clk_dp_ops, 800 }, 801 }; 802 803 static struct clk_rcg2 disp1_cc_mdss_dptx2_pixel1_clk_src = { 804 .cmd_rcgr = 0x2220, 805 .mnd_width = 16, 806 .hid_width = 5, 807 .parent_map = disp_cc_parent_map_1, 808 .clkr.hw.init = &(const struct clk_init_data) { 809 .name = "disp1_cc_mdss_dptx2_pixel1_clk_src", 810 .parent_data = disp1_cc_parent_data_1, 811 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_1), 812 .flags = CLK_SET_RATE_PARENT, 813 .ops = &clk_dp_ops, 814 }, 815 }; 816 817 static struct clk_rcg2 disp0_cc_mdss_dptx3_aux_clk_src = { 818 .cmd_rcgr = 0x234c, 819 .mnd_width = 0, 820 .hid_width = 5, 821 .parent_map = disp_cc_parent_map_2, 822 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 823 .clkr.hw.init = &(const struct clk_init_data) { 824 .name = "disp0_cc_mdss_dptx3_aux_clk_src", 825 .parent_data = disp_cc_parent_data_2, 826 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 827 .ops = &clk_rcg2_ops, 828 }, 829 }; 830 831 static struct clk_rcg2 disp1_cc_mdss_dptx3_aux_clk_src = { 832 .cmd_rcgr = 0x234c, 833 .mnd_width = 0, 834 .hid_width = 5, 835 .parent_map = disp_cc_parent_map_2, 836 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 837 .clkr.hw.init = &(const struct clk_init_data) { 838 .name = "disp1_cc_mdss_dptx3_aux_clk_src", 839 .parent_data = disp_cc_parent_data_2, 840 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 841 .ops = &clk_rcg2_ops, 842 }, 843 }; 844 845 static struct clk_rcg2 disp0_cc_mdss_dptx3_link_clk_src = { 846 .cmd_rcgr = 0x2318, 847 .mnd_width = 0, 848 .hid_width = 5, 849 .parent_map = disp_cc_parent_map_0, 850 .clkr.hw.init = &(const struct clk_init_data) { 851 .name = "disp0_cc_mdss_dptx3_link_clk_src", 852 .parent_data = disp0_cc_parent_data_0, 853 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_0), 854 .flags = CLK_SET_RATE_PARENT, 855 .ops = &clk_byte2_ops, 856 }, 857 }; 858 859 static struct clk_rcg2 disp1_cc_mdss_dptx3_link_clk_src = { 860 .cmd_rcgr = 0x2318, 861 .mnd_width = 0, 862 .hid_width = 5, 863 .parent_map = disp_cc_parent_map_0, 864 .clkr.hw.init = &(const struct clk_init_data) { 865 .name = "disp1_cc_mdss_dptx3_link_clk_src", 866 .parent_data = disp1_cc_parent_data_0, 867 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_0), 868 .flags = CLK_SET_RATE_PARENT, 869 .ops = &clk_byte2_ops, 870 }, 871 }; 872 873 static struct clk_rcg2 disp0_cc_mdss_dptx3_pixel0_clk_src = { 874 .cmd_rcgr = 0x2300, 875 .mnd_width = 16, 876 .hid_width = 5, 877 .parent_map = disp_cc_parent_map_1, 878 .clkr.hw.init = &(const struct clk_init_data) { 879 .name = "disp0_cc_mdss_dptx3_pixel0_clk_src", 880 .parent_data = disp0_cc_parent_data_1, 881 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_1), 882 .flags = CLK_SET_RATE_PARENT, 883 .ops = &clk_dp_ops, 884 }, 885 }; 886 887 static struct clk_rcg2 disp1_cc_mdss_dptx3_pixel0_clk_src = { 888 .cmd_rcgr = 0x2300, 889 .mnd_width = 16, 890 .hid_width = 5, 891 .parent_map = disp_cc_parent_map_1, 892 .clkr.hw.init = &(const struct clk_init_data) { 893 .name = "disp1_cc_mdss_dptx3_pixel0_clk_src", 894 .parent_data = disp1_cc_parent_data_1, 895 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_1), 896 .flags = CLK_SET_RATE_PARENT, 897 .ops = &clk_dp_ops, 898 }, 899 }; 900 901 static struct clk_rcg2 disp0_cc_mdss_esc0_clk_src = { 902 .cmd_rcgr = 0x2174, 903 .mnd_width = 0, 904 .hid_width = 5, 905 .parent_map = disp_cc_parent_map_4, 906 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 907 .clkr.hw.init = &(const struct clk_init_data) { 908 .name = "disp0_cc_mdss_esc0_clk_src", 909 .parent_data = disp_cc_parent_data_4, 910 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 911 .ops = &clk_rcg2_ops, 912 }, 913 }; 914 915 static struct clk_rcg2 disp1_cc_mdss_esc0_clk_src = { 916 .cmd_rcgr = 0x2174, 917 .mnd_width = 0, 918 .hid_width = 5, 919 .parent_map = disp_cc_parent_map_4, 920 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 921 .clkr.hw.init = &(const struct clk_init_data) { 922 .name = "disp1_cc_mdss_esc0_clk_src", 923 .parent_data = disp_cc_parent_data_4, 924 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 925 .ops = &clk_rcg2_ops, 926 }, 927 }; 928 929 static struct clk_rcg2 disp0_cc_mdss_esc1_clk_src = { 930 .cmd_rcgr = 0x218c, 931 .mnd_width = 0, 932 .hid_width = 5, 933 .parent_map = disp_cc_parent_map_4, 934 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 935 .clkr.hw.init = &(const struct clk_init_data) { 936 .name = "disp0_cc_mdss_esc1_clk_src", 937 .parent_data = disp_cc_parent_data_4, 938 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 939 .ops = &clk_rcg2_ops, 940 }, 941 }; 942 943 static struct clk_rcg2 disp1_cc_mdss_esc1_clk_src = { 944 .cmd_rcgr = 0x218c, 945 .mnd_width = 0, 946 .hid_width = 5, 947 .parent_map = disp_cc_parent_map_4, 948 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 949 .clkr.hw.init = &(const struct clk_init_data) { 950 .name = "disp1_cc_mdss_esc1_clk_src", 951 .parent_data = disp_cc_parent_data_4, 952 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 953 .ops = &clk_rcg2_ops, 954 }, 955 }; 956 957 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { 958 F(19200000, P_BI_TCXO, 1, 0, 0), 959 F(85714286, P_DISPn_CC_PLL1_OUT_MAIN, 7, 0, 0), 960 F(100000000, P_DISPn_CC_PLL1_OUT_MAIN, 6, 0, 0), 961 F(150000000, P_DISPn_CC_PLL1_OUT_MAIN, 4, 0, 0), 962 F(200000000, P_DISPn_CC_PLL1_OUT_MAIN, 3, 0, 0), 963 F(300000000, P_DISPn_CC_PLL1_OUT_MAIN, 2, 0, 0), 964 F(375000000, P_DISPn_CC_PLL0_OUT_MAIN, 4, 0, 0), 965 F(500000000, P_DISPn_CC_PLL0_OUT_MAIN, 3, 0, 0), 966 F(600000000, P_DISPn_CC_PLL1_OUT_MAIN, 1, 0, 0), 967 { } 968 }; 969 970 static struct clk_rcg2 disp0_cc_mdss_mdp_clk_src = { 971 .cmd_rcgr = 0x20f4, 972 .mnd_width = 0, 973 .hid_width = 5, 974 .parent_map = disp_cc_parent_map_5, 975 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 976 .clkr.hw.init = &(const struct clk_init_data) { 977 .name = "disp0_cc_mdss_mdp_clk_src", 978 .parent_data = disp0_cc_parent_data_5, 979 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_5), 980 .ops = &clk_rcg2_shared_ops, 981 }, 982 }; 983 984 static struct clk_rcg2 disp1_cc_mdss_mdp_clk_src = { 985 .cmd_rcgr = 0x20f4, 986 .mnd_width = 0, 987 .hid_width = 5, 988 .parent_map = disp_cc_parent_map_5, 989 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 990 .clkr.hw.init = &(const struct clk_init_data) { 991 .name = "disp1_cc_mdss_mdp_clk_src", 992 .parent_data = disp1_cc_parent_data_5, 993 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_5), 994 .ops = &clk_rcg2_shared_ops, 995 }, 996 }; 997 998 static struct clk_rcg2 disp0_cc_mdss_pclk0_clk_src = { 999 .cmd_rcgr = 0x20c4, 1000 .mnd_width = 8, 1001 .hid_width = 5, 1002 .parent_map = disp_cc_parent_map_3, 1003 .clkr.hw.init = &(const struct clk_init_data) { 1004 .name = "disp0_cc_mdss_pclk0_clk_src", 1005 .parent_data = disp_cc_parent_data_3, 1006 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 1007 .flags = CLK_SET_RATE_PARENT, 1008 .ops = &clk_pixel_ops, 1009 }, 1010 }; 1011 1012 static struct clk_rcg2 disp1_cc_mdss_pclk0_clk_src = { 1013 .cmd_rcgr = 0x20c4, 1014 .mnd_width = 8, 1015 .hid_width = 5, 1016 .parent_map = disp_cc_parent_map_3, 1017 .clkr.hw.init = &(const struct clk_init_data) { 1018 .name = "disp1_cc_mdss_pclk0_clk_src", 1019 .parent_data = disp_cc_parent_data_3, 1020 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 1021 .flags = CLK_SET_RATE_PARENT, 1022 .ops = &clk_pixel_ops, 1023 }, 1024 }; 1025 1026 static struct clk_rcg2 disp0_cc_mdss_pclk1_clk_src = { 1027 .cmd_rcgr = 0x20dc, 1028 .mnd_width = 8, 1029 .hid_width = 5, 1030 .parent_map = disp_cc_parent_map_3, 1031 .clkr.hw.init = &(const struct clk_init_data) { 1032 .name = "disp0_cc_mdss_pclk1_clk_src", 1033 .parent_data = disp_cc_parent_data_3, 1034 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 1035 .flags = CLK_SET_RATE_PARENT, 1036 .ops = &clk_pixel_ops, 1037 }, 1038 }; 1039 1040 static struct clk_rcg2 disp1_cc_mdss_pclk1_clk_src = { 1041 .cmd_rcgr = 0x20dc, 1042 .mnd_width = 8, 1043 .hid_width = 5, 1044 .parent_map = disp_cc_parent_map_3, 1045 .clkr.hw.init = &(const struct clk_init_data) { 1046 .name = "disp1_cc_mdss_pclk1_clk_src", 1047 .parent_data = disp_cc_parent_data_3, 1048 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 1049 .flags = CLK_SET_RATE_PARENT, 1050 .ops = &clk_pixel_ops, 1051 }, 1052 }; 1053 1054 static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = { 1055 F(19200000, P_BI_TCXO, 1, 0, 0), 1056 F(200000000, P_DISPn_CC_PLL1_OUT_MAIN, 3, 0, 0), 1057 F(300000000, P_DISPn_CC_PLL1_OUT_MAIN, 2, 0, 0), 1058 F(375000000, P_DISPn_CC_PLL0_OUT_MAIN, 4, 0, 0), 1059 F(500000000, P_DISPn_CC_PLL0_OUT_MAIN, 3, 0, 0), 1060 F(600000000, P_DISPn_CC_PLL1_OUT_MAIN, 1, 0, 0), 1061 { } 1062 }; 1063 1064 static struct clk_rcg2 disp0_cc_mdss_rot_clk_src = { 1065 .cmd_rcgr = 0x210c, 1066 .mnd_width = 0, 1067 .hid_width = 5, 1068 .parent_map = disp_cc_parent_map_5, 1069 .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, 1070 .clkr.hw.init = &(const struct clk_init_data) { 1071 .name = "disp0_cc_mdss_rot_clk_src", 1072 .parent_data = disp0_cc_parent_data_5, 1073 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_5), 1074 .ops = &clk_rcg2_shared_ops, 1075 }, 1076 }; 1077 1078 static struct clk_rcg2 disp1_cc_mdss_rot_clk_src = { 1079 .cmd_rcgr = 0x210c, 1080 .mnd_width = 0, 1081 .hid_width = 5, 1082 .parent_map = disp_cc_parent_map_5, 1083 .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, 1084 .clkr.hw.init = &(const struct clk_init_data) { 1085 .name = "disp1_cc_mdss_rot_clk_src", 1086 .parent_data = disp1_cc_parent_data_5, 1087 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_5), 1088 .ops = &clk_rcg2_shared_ops, 1089 }, 1090 }; 1091 1092 static struct clk_rcg2 disp0_cc_mdss_vsync_clk_src = { 1093 .cmd_rcgr = 0x2124, 1094 .mnd_width = 0, 1095 .hid_width = 5, 1096 .parent_map = disp_cc_parent_map_2, 1097 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 1098 .clkr.hw.init = &(const struct clk_init_data) { 1099 .name = "disp0_cc_mdss_vsync_clk_src", 1100 .parent_data = disp_cc_parent_data_2, 1101 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 1102 .ops = &clk_rcg2_ops, 1103 }, 1104 }; 1105 1106 static struct clk_rcg2 disp1_cc_mdss_vsync_clk_src = { 1107 .cmd_rcgr = 0x2124, 1108 .mnd_width = 0, 1109 .hid_width = 5, 1110 .parent_map = disp_cc_parent_map_2, 1111 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 1112 .clkr.hw.init = &(const struct clk_init_data) { 1113 .name = "disp1_cc_mdss_vsync_clk_src", 1114 .parent_data = disp_cc_parent_data_2, 1115 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 1116 .ops = &clk_rcg2_ops, 1117 }, 1118 }; 1119 1120 static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = { 1121 F(32000, P_SLEEP_CLK, 1, 0, 0), 1122 { } 1123 }; 1124 1125 static struct clk_rcg2 disp0_cc_sleep_clk_src = { 1126 .cmd_rcgr = 0x6060, 1127 .mnd_width = 0, 1128 .hid_width = 5, 1129 .parent_map = disp_cc_parent_map_7, 1130 .freq_tbl = ftbl_disp_cc_sleep_clk_src, 1131 .clkr.hw.init = &(const struct clk_init_data) { 1132 .name = "disp0_cc_sleep_clk_src", 1133 .parent_data = disp_cc_parent_data_7, 1134 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), 1135 .ops = &clk_rcg2_ops, 1136 }, 1137 }; 1138 1139 static struct clk_rcg2 disp1_cc_sleep_clk_src = { 1140 .cmd_rcgr = 0x6060, 1141 .mnd_width = 0, 1142 .hid_width = 5, 1143 .parent_map = disp_cc_parent_map_7, 1144 .freq_tbl = ftbl_disp_cc_sleep_clk_src, 1145 .clkr.hw.init = &(const struct clk_init_data) { 1146 .name = "disp1_cc_sleep_clk_src", 1147 .parent_data = disp_cc_parent_data_7, 1148 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), 1149 .ops = &clk_rcg2_ops, 1150 }, 1151 }; 1152 1153 static struct clk_regmap_div disp0_cc_mdss_byte0_div_clk_src = { 1154 .reg = 0x2154, 1155 .shift = 0, 1156 .width = 4, 1157 .clkr.hw.init = &(const struct clk_init_data) { 1158 .name = "disp0_cc_mdss_byte0_div_clk_src", 1159 .parent_hws = (const struct clk_hw*[]){ 1160 &disp0_cc_mdss_byte0_clk_src.clkr.hw, 1161 }, 1162 .num_parents = 1, 1163 .ops = &clk_regmap_div_ops, 1164 }, 1165 }; 1166 1167 static struct clk_regmap_div disp1_cc_mdss_byte0_div_clk_src = { 1168 .reg = 0x2154, 1169 .shift = 0, 1170 .width = 4, 1171 .clkr.hw.init = &(const struct clk_init_data) { 1172 .name = "disp1_cc_mdss_byte0_div_clk_src", 1173 .parent_hws = (const struct clk_hw*[]){ 1174 &disp1_cc_mdss_byte0_clk_src.clkr.hw, 1175 }, 1176 .num_parents = 1, 1177 .ops = &clk_regmap_div_ops, 1178 }, 1179 }; 1180 1181 static struct clk_regmap_div disp0_cc_mdss_byte1_div_clk_src = { 1182 .reg = 0x2170, 1183 .shift = 0, 1184 .width = 4, 1185 .clkr.hw.init = &(const struct clk_init_data) { 1186 .name = "disp0_cc_mdss_byte1_div_clk_src", 1187 .parent_hws = (const struct clk_hw*[]){ 1188 &disp0_cc_mdss_byte1_clk_src.clkr.hw, 1189 }, 1190 .num_parents = 1, 1191 .ops = &clk_regmap_div_ops, 1192 }, 1193 }; 1194 1195 static struct clk_regmap_div disp1_cc_mdss_byte1_div_clk_src = { 1196 .reg = 0x2170, 1197 .shift = 0, 1198 .width = 4, 1199 .clkr.hw.init = &(const struct clk_init_data) { 1200 .name = "disp1_cc_mdss_byte1_div_clk_src", 1201 .parent_hws = (const struct clk_hw*[]){ 1202 &disp1_cc_mdss_byte1_clk_src.clkr.hw, 1203 }, 1204 .num_parents = 1, 1205 .ops = &clk_regmap_div_ops, 1206 }, 1207 }; 1208 1209 static struct clk_regmap_div disp0_cc_mdss_dptx0_link_div_clk_src = { 1210 .reg = 0x21bc, 1211 .shift = 0, 1212 .width = 4, 1213 .clkr.hw.init = &(const struct clk_init_data) { 1214 .name = "disp0_cc_mdss_dptx0_link_div_clk_src", 1215 .parent_hws = (const struct clk_hw*[]){ 1216 &disp0_cc_mdss_dptx0_link_clk_src.clkr.hw, 1217 }, 1218 .num_parents = 1, 1219 .flags = CLK_SET_RATE_PARENT, 1220 .ops = &clk_regmap_div_ro_ops, 1221 }, 1222 }; 1223 1224 static struct clk_regmap_div disp1_cc_mdss_dptx0_link_div_clk_src = { 1225 .reg = 0x21bc, 1226 .shift = 0, 1227 .width = 4, 1228 .clkr.hw.init = &(const struct clk_init_data) { 1229 .name = "disp1_cc_mdss_dptx0_link_div_clk_src", 1230 .parent_hws = (const struct clk_hw*[]){ 1231 &disp1_cc_mdss_dptx0_link_clk_src.clkr.hw, 1232 }, 1233 .num_parents = 1, 1234 .flags = CLK_SET_RATE_PARENT, 1235 .ops = &clk_regmap_div_ro_ops, 1236 }, 1237 }; 1238 1239 static struct clk_regmap_div disp0_cc_mdss_dptx1_link_div_clk_src = { 1240 .reg = 0x2280, 1241 .shift = 0, 1242 .width = 4, 1243 .clkr.hw.init = &(const struct clk_init_data) { 1244 .name = "disp0_cc_mdss_dptx1_link_div_clk_src", 1245 .parent_hws = (const struct clk_hw*[]){ 1246 &disp0_cc_mdss_dptx1_link_clk_src.clkr.hw, 1247 }, 1248 .num_parents = 1, 1249 .flags = CLK_SET_RATE_PARENT, 1250 .ops = &clk_regmap_div_ro_ops, 1251 }, 1252 }; 1253 1254 static struct clk_regmap_div disp1_cc_mdss_dptx1_link_div_clk_src = { 1255 .reg = 0x2280, 1256 .shift = 0, 1257 .width = 4, 1258 .clkr.hw.init = &(const struct clk_init_data) { 1259 .name = "disp1_cc_mdss_dptx1_link_div_clk_src", 1260 .parent_hws = (const struct clk_hw*[]){ 1261 &disp1_cc_mdss_dptx1_link_clk_src.clkr.hw, 1262 }, 1263 .num_parents = 1, 1264 .flags = CLK_SET_RATE_PARENT, 1265 .ops = &clk_regmap_div_ro_ops, 1266 }, 1267 }; 1268 1269 static struct clk_regmap_div disp0_cc_mdss_dptx2_link_div_clk_src = { 1270 .reg = 0x229c, 1271 .shift = 0, 1272 .width = 4, 1273 .clkr.hw.init = &(const struct clk_init_data) { 1274 .name = "disp0_cc_mdss_dptx2_link_div_clk_src", 1275 .parent_hws = (const struct clk_hw*[]){ 1276 &disp0_cc_mdss_dptx2_link_clk_src.clkr.hw, 1277 }, 1278 .num_parents = 1, 1279 .flags = CLK_SET_RATE_PARENT, 1280 .ops = &clk_regmap_div_ro_ops, 1281 }, 1282 }; 1283 1284 static struct clk_regmap_div disp1_cc_mdss_dptx2_link_div_clk_src = { 1285 .reg = 0x229c, 1286 .shift = 0, 1287 .width = 4, 1288 .clkr.hw.init = &(const struct clk_init_data) { 1289 .name = "disp1_cc_mdss_dptx2_link_div_clk_src", 1290 .parent_hws = (const struct clk_hw*[]){ 1291 &disp1_cc_mdss_dptx2_link_clk_src.clkr.hw, 1292 }, 1293 .num_parents = 1, 1294 .flags = CLK_SET_RATE_PARENT, 1295 .ops = &clk_regmap_div_ro_ops, 1296 }, 1297 }; 1298 1299 static struct clk_regmap_div disp0_cc_mdss_dptx3_link_div_clk_src = { 1300 .reg = 0x2330, 1301 .shift = 0, 1302 .width = 4, 1303 .clkr.hw.init = &(const struct clk_init_data) { 1304 .name = "disp0_cc_mdss_dptx3_link_div_clk_src", 1305 .parent_hws = (const struct clk_hw*[]){ 1306 &disp0_cc_mdss_dptx3_link_clk_src.clkr.hw, 1307 }, 1308 .num_parents = 1, 1309 .flags = CLK_SET_RATE_PARENT, 1310 .ops = &clk_regmap_div_ro_ops, 1311 }, 1312 }; 1313 1314 static struct clk_regmap_div disp1_cc_mdss_dptx3_link_div_clk_src = { 1315 .reg = 0x2330, 1316 .shift = 0, 1317 .width = 4, 1318 .clkr.hw.init = &(const struct clk_init_data) { 1319 .name = "disp1_cc_mdss_dptx3_link_div_clk_src", 1320 .parent_hws = (const struct clk_hw*[]){ 1321 &disp1_cc_mdss_dptx3_link_clk_src.clkr.hw, 1322 }, 1323 .num_parents = 1, 1324 .flags = CLK_SET_RATE_PARENT, 1325 .ops = &clk_regmap_div_ro_ops, 1326 }, 1327 }; 1328 1329 static struct clk_branch disp0_cc_mdss_ahb1_clk = { 1330 .halt_reg = 0x20c0, 1331 .halt_check = BRANCH_HALT, 1332 .clkr = { 1333 .enable_reg = 0x20c0, 1334 .enable_mask = BIT(0), 1335 .hw.init = &(const struct clk_init_data) { 1336 .name = "disp0_cc_mdss_ahb1_clk", 1337 .parent_hws = (const struct clk_hw*[]){ 1338 &disp0_cc_mdss_ahb_clk_src.clkr.hw, 1339 }, 1340 .num_parents = 1, 1341 .flags = CLK_SET_RATE_PARENT, 1342 .ops = &clk_branch2_ops, 1343 }, 1344 }, 1345 }; 1346 1347 static struct clk_branch disp1_cc_mdss_ahb1_clk = { 1348 .halt_reg = 0x20c0, 1349 .halt_check = BRANCH_HALT, 1350 .clkr = { 1351 .enable_reg = 0x20c0, 1352 .enable_mask = BIT(0), 1353 .hw.init = &(const struct clk_init_data) { 1354 .name = "disp1_cc_mdss_ahb1_clk", 1355 .parent_hws = (const struct clk_hw*[]){ 1356 &disp1_cc_mdss_ahb_clk_src.clkr.hw, 1357 }, 1358 .num_parents = 1, 1359 .flags = CLK_SET_RATE_PARENT, 1360 .ops = &clk_branch2_ops, 1361 }, 1362 }, 1363 }; 1364 1365 static struct clk_branch disp0_cc_mdss_ahb_clk = { 1366 .halt_reg = 0x20bc, 1367 .halt_check = BRANCH_HALT, 1368 .clkr = { 1369 .enable_reg = 0x20bc, 1370 .enable_mask = BIT(0), 1371 .hw.init = &(const struct clk_init_data) { 1372 .name = "disp0_cc_mdss_ahb_clk", 1373 .parent_hws = (const struct clk_hw*[]){ 1374 &disp0_cc_mdss_ahb_clk_src.clkr.hw, 1375 }, 1376 .num_parents = 1, 1377 .flags = CLK_SET_RATE_PARENT, 1378 .ops = &clk_branch2_ops, 1379 }, 1380 }, 1381 }; 1382 1383 static struct clk_branch disp1_cc_mdss_ahb_clk = { 1384 .halt_reg = 0x20bc, 1385 .halt_check = BRANCH_HALT, 1386 .clkr = { 1387 .enable_reg = 0x20bc, 1388 .enable_mask = BIT(0), 1389 .hw.init = &(const struct clk_init_data) { 1390 .name = "disp1_cc_mdss_ahb_clk", 1391 .parent_hws = (const struct clk_hw*[]){ 1392 &disp1_cc_mdss_ahb_clk_src.clkr.hw, 1393 }, 1394 .num_parents = 1, 1395 .flags = CLK_SET_RATE_PARENT, 1396 .ops = &clk_branch2_ops, 1397 }, 1398 }, 1399 }; 1400 1401 static struct clk_branch disp0_cc_mdss_byte0_clk = { 1402 .halt_reg = 0x2044, 1403 .halt_check = BRANCH_HALT, 1404 .clkr = { 1405 .enable_reg = 0x2044, 1406 .enable_mask = BIT(0), 1407 .hw.init = &(const struct clk_init_data) { 1408 .name = "disp0_cc_mdss_byte0_clk", 1409 .parent_hws = (const struct clk_hw*[]){ 1410 &disp0_cc_mdss_byte0_clk_src.clkr.hw, 1411 }, 1412 .num_parents = 1, 1413 .flags = CLK_SET_RATE_PARENT, 1414 .ops = &clk_branch2_ops, 1415 }, 1416 }, 1417 }; 1418 1419 static struct clk_branch disp1_cc_mdss_byte0_clk = { 1420 .halt_reg = 0x2044, 1421 .halt_check = BRANCH_HALT, 1422 .clkr = { 1423 .enable_reg = 0x2044, 1424 .enable_mask = BIT(0), 1425 .hw.init = &(const struct clk_init_data) { 1426 .name = "disp1_cc_mdss_byte0_clk", 1427 .parent_hws = (const struct clk_hw*[]){ 1428 &disp1_cc_mdss_byte0_clk_src.clkr.hw, 1429 }, 1430 .num_parents = 1, 1431 .flags = CLK_SET_RATE_PARENT, 1432 .ops = &clk_branch2_ops, 1433 }, 1434 }, 1435 }; 1436 1437 static struct clk_branch disp0_cc_mdss_byte0_intf_clk = { 1438 .halt_reg = 0x2048, 1439 .halt_check = BRANCH_HALT, 1440 .clkr = { 1441 .enable_reg = 0x2048, 1442 .enable_mask = BIT(0), 1443 .hw.init = &(const struct clk_init_data) { 1444 .name = "disp0_cc_mdss_byte0_intf_clk", 1445 .parent_hws = (const struct clk_hw*[]){ 1446 &disp0_cc_mdss_byte0_div_clk_src.clkr.hw, 1447 }, 1448 .num_parents = 1, 1449 .flags = CLK_SET_RATE_PARENT, 1450 .ops = &clk_branch2_ops, 1451 }, 1452 }, 1453 }; 1454 1455 static struct clk_branch disp1_cc_mdss_byte0_intf_clk = { 1456 .halt_reg = 0x2048, 1457 .halt_check = BRANCH_HALT, 1458 .clkr = { 1459 .enable_reg = 0x2048, 1460 .enable_mask = BIT(0), 1461 .hw.init = &(const struct clk_init_data) { 1462 .name = "disp1_cc_mdss_byte0_intf_clk", 1463 .parent_hws = (const struct clk_hw*[]){ 1464 &disp1_cc_mdss_byte0_div_clk_src.clkr.hw, 1465 }, 1466 .num_parents = 1, 1467 .flags = CLK_SET_RATE_PARENT, 1468 .ops = &clk_branch2_ops, 1469 }, 1470 }, 1471 }; 1472 1473 static struct clk_branch disp0_cc_mdss_byte1_clk = { 1474 .halt_reg = 0x204c, 1475 .halt_check = BRANCH_HALT, 1476 .clkr = { 1477 .enable_reg = 0x204c, 1478 .enable_mask = BIT(0), 1479 .hw.init = &(const struct clk_init_data) { 1480 .name = "disp0_cc_mdss_byte1_clk", 1481 .parent_hws = (const struct clk_hw*[]){ 1482 &disp0_cc_mdss_byte1_clk_src.clkr.hw, 1483 }, 1484 .num_parents = 1, 1485 .flags = CLK_SET_RATE_PARENT, 1486 .ops = &clk_branch2_ops, 1487 }, 1488 }, 1489 }; 1490 1491 static struct clk_branch disp1_cc_mdss_byte1_clk = { 1492 .halt_reg = 0x204c, 1493 .halt_check = BRANCH_HALT, 1494 .clkr = { 1495 .enable_reg = 0x204c, 1496 .enable_mask = BIT(0), 1497 .hw.init = &(const struct clk_init_data) { 1498 .name = "disp1_cc_mdss_byte1_clk", 1499 .parent_hws = (const struct clk_hw*[]){ 1500 &disp1_cc_mdss_byte1_clk_src.clkr.hw, 1501 }, 1502 .num_parents = 1, 1503 .flags = CLK_SET_RATE_PARENT, 1504 .ops = &clk_branch2_ops, 1505 }, 1506 }, 1507 }; 1508 1509 static struct clk_branch disp0_cc_mdss_byte1_intf_clk = { 1510 .halt_reg = 0x2050, 1511 .halt_check = BRANCH_HALT, 1512 .clkr = { 1513 .enable_reg = 0x2050, 1514 .enable_mask = BIT(0), 1515 .hw.init = &(const struct clk_init_data) { 1516 .name = "disp0_cc_mdss_byte1_intf_clk", 1517 .parent_hws = (const struct clk_hw*[]){ 1518 &disp0_cc_mdss_byte1_div_clk_src.clkr.hw, 1519 }, 1520 .num_parents = 1, 1521 .flags = CLK_SET_RATE_PARENT, 1522 .ops = &clk_branch2_ops, 1523 }, 1524 }, 1525 }; 1526 1527 static struct clk_branch disp1_cc_mdss_byte1_intf_clk = { 1528 .halt_reg = 0x2050, 1529 .halt_check = BRANCH_HALT, 1530 .clkr = { 1531 .enable_reg = 0x2050, 1532 .enable_mask = BIT(0), 1533 .hw.init = &(const struct clk_init_data) { 1534 .name = "disp1_cc_mdss_byte1_intf_clk", 1535 .parent_hws = (const struct clk_hw*[]){ 1536 &disp1_cc_mdss_byte1_div_clk_src.clkr.hw, 1537 }, 1538 .num_parents = 1, 1539 .flags = CLK_SET_RATE_PARENT, 1540 .ops = &clk_branch2_ops, 1541 }, 1542 }, 1543 }; 1544 1545 static struct clk_branch disp0_cc_mdss_dptx0_aux_clk = { 1546 .halt_reg = 0x206c, 1547 .halt_check = BRANCH_HALT, 1548 .clkr = { 1549 .enable_reg = 0x206c, 1550 .enable_mask = BIT(0), 1551 .hw.init = &(const struct clk_init_data) { 1552 .name = "disp0_cc_mdss_dptx0_aux_clk", 1553 .parent_hws = (const struct clk_hw*[]){ 1554 &disp0_cc_mdss_dptx0_aux_clk_src.clkr.hw, 1555 }, 1556 .num_parents = 1, 1557 .flags = CLK_SET_RATE_PARENT, 1558 .ops = &clk_branch2_ops, 1559 }, 1560 }, 1561 }; 1562 1563 static struct clk_branch disp1_cc_mdss_dptx0_aux_clk = { 1564 .halt_reg = 0x206c, 1565 .halt_check = BRANCH_HALT, 1566 .clkr = { 1567 .enable_reg = 0x206c, 1568 .enable_mask = BIT(0), 1569 .hw.init = &(const struct clk_init_data) { 1570 .name = "disp1_cc_mdss_dptx0_aux_clk", 1571 .parent_hws = (const struct clk_hw*[]){ 1572 &disp1_cc_mdss_dptx0_aux_clk_src.clkr.hw, 1573 }, 1574 .num_parents = 1, 1575 .flags = CLK_SET_RATE_PARENT, 1576 .ops = &clk_branch2_ops, 1577 }, 1578 }, 1579 }; 1580 1581 static struct clk_branch disp0_cc_mdss_dptx0_link_clk = { 1582 .halt_reg = 0x205c, 1583 .halt_check = BRANCH_HALT, 1584 .clkr = { 1585 .enable_reg = 0x205c, 1586 .enable_mask = BIT(0), 1587 .hw.init = &(const struct clk_init_data) { 1588 .name = "disp0_cc_mdss_dptx0_link_clk", 1589 .parent_hws = (const struct clk_hw*[]){ 1590 &disp0_cc_mdss_dptx0_link_clk_src.clkr.hw, 1591 }, 1592 .num_parents = 1, 1593 .flags = CLK_SET_RATE_PARENT, 1594 .ops = &clk_branch2_ops, 1595 }, 1596 }, 1597 }; 1598 1599 static struct clk_branch disp1_cc_mdss_dptx0_link_clk = { 1600 .halt_reg = 0x205c, 1601 .halt_check = BRANCH_HALT, 1602 .clkr = { 1603 .enable_reg = 0x205c, 1604 .enable_mask = BIT(0), 1605 .hw.init = &(const struct clk_init_data) { 1606 .name = "disp1_cc_mdss_dptx0_link_clk", 1607 .parent_hws = (const struct clk_hw*[]){ 1608 &disp1_cc_mdss_dptx0_link_clk_src.clkr.hw, 1609 }, 1610 .num_parents = 1, 1611 .flags = CLK_SET_RATE_PARENT, 1612 .ops = &clk_branch2_ops, 1613 }, 1614 }, 1615 }; 1616 1617 static struct clk_branch disp0_cc_mdss_dptx0_link_intf_clk = { 1618 .halt_reg = 0x2060, 1619 .halt_check = BRANCH_HALT, 1620 .clkr = { 1621 .enable_reg = 0x2060, 1622 .enable_mask = BIT(0), 1623 .hw.init = &(const struct clk_init_data) { 1624 .name = "disp0_cc_mdss_dptx0_link_intf_clk", 1625 .parent_hws = (const struct clk_hw*[]){ 1626 &disp0_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1627 }, 1628 .num_parents = 1, 1629 .flags = CLK_SET_RATE_PARENT, 1630 .ops = &clk_branch2_ops, 1631 }, 1632 }, 1633 }; 1634 1635 static struct clk_branch disp1_cc_mdss_dptx0_link_intf_clk = { 1636 .halt_reg = 0x2060, 1637 .halt_check = BRANCH_HALT, 1638 .clkr = { 1639 .enable_reg = 0x2060, 1640 .enable_mask = BIT(0), 1641 .hw.init = &(const struct clk_init_data) { 1642 .name = "disp1_cc_mdss_dptx0_link_intf_clk", 1643 .parent_hws = (const struct clk_hw*[]){ 1644 &disp1_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1645 }, 1646 .num_parents = 1, 1647 .flags = CLK_SET_RATE_PARENT, 1648 .ops = &clk_branch2_ops, 1649 }, 1650 }, 1651 }; 1652 1653 static struct clk_branch disp0_cc_mdss_dptx0_pixel0_clk = { 1654 .halt_reg = 0x2070, 1655 .halt_check = BRANCH_HALT, 1656 .clkr = { 1657 .enable_reg = 0x2070, 1658 .enable_mask = BIT(0), 1659 .hw.init = &(const struct clk_init_data) { 1660 .name = "disp0_cc_mdss_dptx0_pixel0_clk", 1661 .parent_hws = (const struct clk_hw*[]){ 1662 &disp0_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, 1663 }, 1664 .num_parents = 1, 1665 .flags = CLK_SET_RATE_PARENT, 1666 .ops = &clk_branch2_ops, 1667 }, 1668 }, 1669 }; 1670 1671 static struct clk_branch disp1_cc_mdss_dptx0_pixel0_clk = { 1672 .halt_reg = 0x2070, 1673 .halt_check = BRANCH_HALT, 1674 .clkr = { 1675 .enable_reg = 0x2070, 1676 .enable_mask = BIT(0), 1677 .hw.init = &(const struct clk_init_data) { 1678 .name = "disp1_cc_mdss_dptx0_pixel0_clk", 1679 .parent_hws = (const struct clk_hw*[]){ 1680 &disp1_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, 1681 }, 1682 .num_parents = 1, 1683 .flags = CLK_SET_RATE_PARENT, 1684 .ops = &clk_branch2_ops, 1685 }, 1686 }, 1687 }; 1688 1689 static struct clk_branch disp0_cc_mdss_dptx0_pixel1_clk = { 1690 .halt_reg = 0x2074, 1691 .halt_check = BRANCH_HALT, 1692 .clkr = { 1693 .enable_reg = 0x2074, 1694 .enable_mask = BIT(0), 1695 .hw.init = &(const struct clk_init_data) { 1696 .name = "disp0_cc_mdss_dptx0_pixel1_clk", 1697 .parent_hws = (const struct clk_hw*[]){ 1698 &disp0_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, 1699 }, 1700 .num_parents = 1, 1701 .flags = CLK_SET_RATE_PARENT, 1702 .ops = &clk_branch2_ops, 1703 }, 1704 }, 1705 }; 1706 1707 static struct clk_branch disp1_cc_mdss_dptx0_pixel1_clk = { 1708 .halt_reg = 0x2074, 1709 .halt_check = BRANCH_HALT, 1710 .clkr = { 1711 .enable_reg = 0x2074, 1712 .enable_mask = BIT(0), 1713 .hw.init = &(const struct clk_init_data) { 1714 .name = "disp1_cc_mdss_dptx0_pixel1_clk", 1715 .parent_hws = (const struct clk_hw*[]){ 1716 &disp1_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, 1717 }, 1718 .num_parents = 1, 1719 .flags = CLK_SET_RATE_PARENT, 1720 .ops = &clk_branch2_ops, 1721 }, 1722 }, 1723 }; 1724 1725 static struct clk_branch disp0_cc_mdss_dptx0_usb_router_link_intf_clk = { 1726 .halt_reg = 0x2064, 1727 .halt_check = BRANCH_HALT, 1728 .clkr = { 1729 .enable_reg = 0x2064, 1730 .enable_mask = BIT(0), 1731 .hw.init = &(const struct clk_init_data) { 1732 .name = "disp0_cc_mdss_dptx0_usb_router_link_intf_clk", 1733 .parent_hws = (const struct clk_hw*[]){ 1734 &disp0_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1735 }, 1736 .num_parents = 1, 1737 .flags = CLK_SET_RATE_PARENT, 1738 .ops = &clk_branch2_ops, 1739 }, 1740 }, 1741 }; 1742 1743 static struct clk_branch disp1_cc_mdss_dptx0_usb_router_link_intf_clk = { 1744 .halt_reg = 0x2064, 1745 .halt_check = BRANCH_HALT, 1746 .clkr = { 1747 .enable_reg = 0x2064, 1748 .enable_mask = BIT(0), 1749 .hw.init = &(const struct clk_init_data) { 1750 .name = "disp1_cc_mdss_dptx0_usb_router_link_intf_clk", 1751 .parent_hws = (const struct clk_hw*[]){ 1752 &disp1_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1753 }, 1754 .num_parents = 1, 1755 .flags = CLK_SET_RATE_PARENT, 1756 .ops = &clk_branch2_ops, 1757 }, 1758 }, 1759 }; 1760 1761 static struct clk_branch disp0_cc_mdss_dptx1_aux_clk = { 1762 .halt_reg = 0x20a0, 1763 .halt_check = BRANCH_HALT, 1764 .clkr = { 1765 .enable_reg = 0x20a0, 1766 .enable_mask = BIT(0), 1767 .hw.init = &(const struct clk_init_data) { 1768 .name = "disp0_cc_mdss_dptx1_aux_clk", 1769 .parent_hws = (const struct clk_hw*[]){ 1770 &disp0_cc_mdss_dptx1_aux_clk_src.clkr.hw, 1771 }, 1772 .num_parents = 1, 1773 .flags = CLK_SET_RATE_PARENT, 1774 .ops = &clk_branch2_ops, 1775 }, 1776 }, 1777 }; 1778 1779 static struct clk_branch disp1_cc_mdss_dptx1_aux_clk = { 1780 .halt_reg = 0x20a0, 1781 .halt_check = BRANCH_HALT, 1782 .clkr = { 1783 .enable_reg = 0x20a0, 1784 .enable_mask = BIT(0), 1785 .hw.init = &(const struct clk_init_data) { 1786 .name = "disp1_cc_mdss_dptx1_aux_clk", 1787 .parent_hws = (const struct clk_hw*[]){ 1788 &disp1_cc_mdss_dptx1_aux_clk_src.clkr.hw, 1789 }, 1790 .num_parents = 1, 1791 .flags = CLK_SET_RATE_PARENT, 1792 .ops = &clk_branch2_ops, 1793 }, 1794 }, 1795 }; 1796 1797 static struct clk_branch disp0_cc_mdss_dptx1_link_clk = { 1798 .halt_reg = 0x2084, 1799 .halt_check = BRANCH_HALT, 1800 .clkr = { 1801 .enable_reg = 0x2084, 1802 .enable_mask = BIT(0), 1803 .hw.init = &(const struct clk_init_data) { 1804 .name = "disp0_cc_mdss_dptx1_link_clk", 1805 .parent_hws = (const struct clk_hw*[]){ 1806 &disp0_cc_mdss_dptx1_link_clk_src.clkr.hw, 1807 }, 1808 .num_parents = 1, 1809 .flags = CLK_SET_RATE_PARENT, 1810 .ops = &clk_branch2_ops, 1811 }, 1812 }, 1813 }; 1814 1815 static struct clk_branch disp1_cc_mdss_dptx1_link_clk = { 1816 .halt_reg = 0x2084, 1817 .halt_check = BRANCH_HALT, 1818 .clkr = { 1819 .enable_reg = 0x2084, 1820 .enable_mask = BIT(0), 1821 .hw.init = &(const struct clk_init_data) { 1822 .name = "disp1_cc_mdss_dptx1_link_clk", 1823 .parent_hws = (const struct clk_hw*[]){ 1824 &disp1_cc_mdss_dptx1_link_clk_src.clkr.hw, 1825 }, 1826 .num_parents = 1, 1827 .flags = CLK_SET_RATE_PARENT, 1828 .ops = &clk_branch2_ops, 1829 }, 1830 }, 1831 }; 1832 1833 static struct clk_branch disp0_cc_mdss_dptx1_link_intf_clk = { 1834 .halt_reg = 0x2088, 1835 .halt_check = BRANCH_HALT, 1836 .clkr = { 1837 .enable_reg = 0x2088, 1838 .enable_mask = BIT(0), 1839 .hw.init = &(const struct clk_init_data) { 1840 .name = "disp0_cc_mdss_dptx1_link_intf_clk", 1841 .parent_hws = (const struct clk_hw*[]){ 1842 &disp0_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1843 }, 1844 .num_parents = 1, 1845 .flags = CLK_SET_RATE_PARENT, 1846 .ops = &clk_branch2_ops, 1847 }, 1848 }, 1849 }; 1850 1851 static struct clk_branch disp1_cc_mdss_dptx1_link_intf_clk = { 1852 .halt_reg = 0x2088, 1853 .halt_check = BRANCH_HALT, 1854 .clkr = { 1855 .enable_reg = 0x2088, 1856 .enable_mask = BIT(0), 1857 .hw.init = &(const struct clk_init_data) { 1858 .name = "disp1_cc_mdss_dptx1_link_intf_clk", 1859 .parent_hws = (const struct clk_hw*[]){ 1860 &disp1_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1861 }, 1862 .num_parents = 1, 1863 .flags = CLK_SET_RATE_PARENT, 1864 .ops = &clk_branch2_ops, 1865 }, 1866 }, 1867 }; 1868 1869 static struct clk_branch disp0_cc_mdss_dptx1_pixel0_clk = { 1870 .halt_reg = 0x2078, 1871 .halt_check = BRANCH_HALT, 1872 .clkr = { 1873 .enable_reg = 0x2078, 1874 .enable_mask = BIT(0), 1875 .hw.init = &(const struct clk_init_data) { 1876 .name = "disp0_cc_mdss_dptx1_pixel0_clk", 1877 .parent_hws = (const struct clk_hw*[]){ 1878 &disp0_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, 1879 }, 1880 .num_parents = 1, 1881 .flags = CLK_SET_RATE_PARENT, 1882 .ops = &clk_branch2_ops, 1883 }, 1884 }, 1885 }; 1886 1887 static struct clk_branch disp1_cc_mdss_dptx1_pixel0_clk = { 1888 .halt_reg = 0x2078, 1889 .halt_check = BRANCH_HALT, 1890 .clkr = { 1891 .enable_reg = 0x2078, 1892 .enable_mask = BIT(0), 1893 .hw.init = &(const struct clk_init_data) { 1894 .name = "disp1_cc_mdss_dptx1_pixel0_clk", 1895 .parent_hws = (const struct clk_hw*[]){ 1896 &disp1_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, 1897 }, 1898 .num_parents = 1, 1899 .flags = CLK_SET_RATE_PARENT, 1900 .ops = &clk_branch2_ops, 1901 }, 1902 }, 1903 }; 1904 1905 static struct clk_branch disp0_cc_mdss_dptx1_pixel1_clk = { 1906 .halt_reg = 0x236c, 1907 .halt_check = BRANCH_HALT, 1908 .clkr = { 1909 .enable_reg = 0x236c, 1910 .enable_mask = BIT(0), 1911 .hw.init = &(const struct clk_init_data) { 1912 .name = "disp0_cc_mdss_dptx1_pixel1_clk", 1913 .parent_hws = (const struct clk_hw*[]){ 1914 &disp0_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, 1915 }, 1916 .num_parents = 1, 1917 .flags = CLK_SET_RATE_PARENT, 1918 .ops = &clk_branch2_ops, 1919 }, 1920 }, 1921 }; 1922 1923 static struct clk_branch disp1_cc_mdss_dptx1_pixel1_clk = { 1924 .halt_reg = 0x236c, 1925 .halt_check = BRANCH_HALT, 1926 .clkr = { 1927 .enable_reg = 0x236c, 1928 .enable_mask = BIT(0), 1929 .hw.init = &(const struct clk_init_data) { 1930 .name = "disp1_cc_mdss_dptx1_pixel1_clk", 1931 .parent_hws = (const struct clk_hw*[]){ 1932 &disp1_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, 1933 }, 1934 .num_parents = 1, 1935 .flags = CLK_SET_RATE_PARENT, 1936 .ops = &clk_branch2_ops, 1937 }, 1938 }, 1939 }; 1940 1941 static struct clk_branch disp0_cc_mdss_dptx1_usb_router_link_intf_clk = { 1942 .halt_reg = 0x208c, 1943 .halt_check = BRANCH_HALT, 1944 .clkr = { 1945 .enable_reg = 0x208c, 1946 .enable_mask = BIT(0), 1947 .hw.init = &(const struct clk_init_data) { 1948 .name = "disp0_cc_mdss_dptx1_usb_router_link_intf_clk", 1949 .parent_hws = (const struct clk_hw*[]){ 1950 &disp0_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1951 }, 1952 .num_parents = 1, 1953 .flags = CLK_SET_RATE_PARENT, 1954 .ops = &clk_branch2_ops, 1955 }, 1956 }, 1957 }; 1958 1959 static struct clk_branch disp1_cc_mdss_dptx1_usb_router_link_intf_clk = { 1960 .halt_reg = 0x208c, 1961 .halt_check = BRANCH_HALT, 1962 .clkr = { 1963 .enable_reg = 0x208c, 1964 .enable_mask = BIT(0), 1965 .hw.init = &(const struct clk_init_data) { 1966 .name = "disp1_cc_mdss_dptx1_usb_router_link_intf_clk", 1967 .parent_hws = (const struct clk_hw*[]){ 1968 &disp1_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1969 }, 1970 .num_parents = 1, 1971 .flags = CLK_SET_RATE_PARENT, 1972 .ops = &clk_branch2_ops, 1973 }, 1974 }, 1975 }; 1976 1977 static struct clk_branch disp0_cc_mdss_dptx2_aux_clk = { 1978 .halt_reg = 0x20a4, 1979 .halt_check = BRANCH_HALT, 1980 .clkr = { 1981 .enable_reg = 0x20a4, 1982 .enable_mask = BIT(0), 1983 .hw.init = &(const struct clk_init_data) { 1984 .name = "disp0_cc_mdss_dptx2_aux_clk", 1985 .parent_hws = (const struct clk_hw*[]){ 1986 &disp0_cc_mdss_dptx2_aux_clk_src.clkr.hw, 1987 }, 1988 .num_parents = 1, 1989 .flags = CLK_SET_RATE_PARENT, 1990 .ops = &clk_branch2_ops, 1991 }, 1992 }, 1993 }; 1994 1995 static struct clk_branch disp1_cc_mdss_dptx2_aux_clk = { 1996 .halt_reg = 0x20a4, 1997 .halt_check = BRANCH_HALT, 1998 .clkr = { 1999 .enable_reg = 0x20a4, 2000 .enable_mask = BIT(0), 2001 .hw.init = &(const struct clk_init_data) { 2002 .name = "disp1_cc_mdss_dptx2_aux_clk", 2003 .parent_hws = (const struct clk_hw*[]){ 2004 &disp1_cc_mdss_dptx2_aux_clk_src.clkr.hw, 2005 }, 2006 .num_parents = 1, 2007 .flags = CLK_SET_RATE_PARENT, 2008 .ops = &clk_branch2_ops, 2009 }, 2010 }, 2011 }; 2012 2013 static struct clk_branch disp0_cc_mdss_dptx2_link_clk = { 2014 .halt_reg = 0x2090, 2015 .halt_check = BRANCH_HALT, 2016 .clkr = { 2017 .enable_reg = 0x2090, 2018 .enable_mask = BIT(0), 2019 .hw.init = &(const struct clk_init_data) { 2020 .name = "disp0_cc_mdss_dptx2_link_clk", 2021 .parent_hws = (const struct clk_hw*[]){ 2022 &disp0_cc_mdss_dptx2_link_clk_src.clkr.hw, 2023 }, 2024 .num_parents = 1, 2025 .flags = CLK_SET_RATE_PARENT, 2026 .ops = &clk_branch2_ops, 2027 }, 2028 }, 2029 }; 2030 2031 static struct clk_branch disp1_cc_mdss_dptx2_link_clk = { 2032 .halt_reg = 0x2090, 2033 .halt_check = BRANCH_HALT, 2034 .clkr = { 2035 .enable_reg = 0x2090, 2036 .enable_mask = BIT(0), 2037 .hw.init = &(const struct clk_init_data) { 2038 .name = "disp1_cc_mdss_dptx2_link_clk", 2039 .parent_hws = (const struct clk_hw*[]){ 2040 &disp1_cc_mdss_dptx2_link_clk_src.clkr.hw, 2041 }, 2042 .num_parents = 1, 2043 .flags = CLK_SET_RATE_PARENT, 2044 .ops = &clk_branch2_ops, 2045 }, 2046 }, 2047 }; 2048 2049 static struct clk_branch disp0_cc_mdss_dptx2_link_intf_clk = { 2050 .halt_reg = 0x2094, 2051 .halt_check = BRANCH_HALT, 2052 .clkr = { 2053 .enable_reg = 0x2094, 2054 .enable_mask = BIT(0), 2055 .hw.init = &(const struct clk_init_data) { 2056 .name = "disp0_cc_mdss_dptx2_link_intf_clk", 2057 .parent_hws = (const struct clk_hw*[]){ 2058 &disp0_cc_mdss_dptx2_link_div_clk_src.clkr.hw, 2059 }, 2060 .num_parents = 1, 2061 .flags = CLK_SET_RATE_PARENT, 2062 .ops = &clk_branch2_ops, 2063 }, 2064 }, 2065 }; 2066 2067 static struct clk_branch disp1_cc_mdss_dptx2_link_intf_clk = { 2068 .halt_reg = 0x2094, 2069 .halt_check = BRANCH_HALT, 2070 .clkr = { 2071 .enable_reg = 0x2094, 2072 .enable_mask = BIT(0), 2073 .hw.init = &(const struct clk_init_data) { 2074 .name = "disp1_cc_mdss_dptx2_link_intf_clk", 2075 .parent_hws = (const struct clk_hw*[]){ 2076 &disp1_cc_mdss_dptx2_link_div_clk_src.clkr.hw, 2077 }, 2078 .num_parents = 1, 2079 .flags = CLK_SET_RATE_PARENT, 2080 .ops = &clk_branch2_ops, 2081 }, 2082 }, 2083 }; 2084 2085 static struct clk_branch disp0_cc_mdss_dptx2_pixel0_clk = { 2086 .halt_reg = 0x207c, 2087 .halt_check = BRANCH_HALT, 2088 .clkr = { 2089 .enable_reg = 0x207c, 2090 .enable_mask = BIT(0), 2091 .hw.init = &(const struct clk_init_data) { 2092 .name = "disp0_cc_mdss_dptx2_pixel0_clk", 2093 .parent_hws = (const struct clk_hw*[]){ 2094 &disp0_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, 2095 }, 2096 .num_parents = 1, 2097 .flags = CLK_SET_RATE_PARENT, 2098 .ops = &clk_branch2_ops, 2099 }, 2100 }, 2101 }; 2102 2103 static struct clk_branch disp1_cc_mdss_dptx2_pixel0_clk = { 2104 .halt_reg = 0x207c, 2105 .halt_check = BRANCH_HALT, 2106 .clkr = { 2107 .enable_reg = 0x207c, 2108 .enable_mask = BIT(0), 2109 .hw.init = &(const struct clk_init_data) { 2110 .name = "disp1_cc_mdss_dptx2_pixel0_clk", 2111 .parent_hws = (const struct clk_hw*[]){ 2112 &disp1_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, 2113 }, 2114 .num_parents = 1, 2115 .flags = CLK_SET_RATE_PARENT, 2116 .ops = &clk_branch2_ops, 2117 }, 2118 }, 2119 }; 2120 2121 static struct clk_branch disp0_cc_mdss_dptx2_pixel1_clk = { 2122 .halt_reg = 0x2080, 2123 .halt_check = BRANCH_HALT, 2124 .clkr = { 2125 .enable_reg = 0x2080, 2126 .enable_mask = BIT(0), 2127 .hw.init = &(const struct clk_init_data) { 2128 .name = "disp0_cc_mdss_dptx2_pixel1_clk", 2129 .parent_hws = (const struct clk_hw*[]){ 2130 &disp0_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, 2131 }, 2132 .num_parents = 1, 2133 .flags = CLK_SET_RATE_PARENT, 2134 .ops = &clk_branch2_ops, 2135 }, 2136 }, 2137 }; 2138 2139 static struct clk_branch disp1_cc_mdss_dptx2_pixel1_clk = { 2140 .halt_reg = 0x2080, 2141 .halt_check = BRANCH_HALT, 2142 .clkr = { 2143 .enable_reg = 0x2080, 2144 .enable_mask = BIT(0), 2145 .hw.init = &(const struct clk_init_data) { 2146 .name = "disp1_cc_mdss_dptx2_pixel1_clk", 2147 .parent_hws = (const struct clk_hw*[]){ 2148 &disp1_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, 2149 }, 2150 .num_parents = 1, 2151 .flags = CLK_SET_RATE_PARENT, 2152 .ops = &clk_branch2_ops, 2153 }, 2154 }, 2155 }; 2156 2157 static struct clk_branch disp0_cc_mdss_dptx3_aux_clk = { 2158 .halt_reg = 0x20b8, 2159 .halt_check = BRANCH_HALT, 2160 .clkr = { 2161 .enable_reg = 0x20b8, 2162 .enable_mask = BIT(0), 2163 .hw.init = &(const struct clk_init_data) { 2164 .name = "disp0_cc_mdss_dptx3_aux_clk", 2165 .parent_hws = (const struct clk_hw*[]){ 2166 &disp0_cc_mdss_dptx3_aux_clk_src.clkr.hw, 2167 }, 2168 .num_parents = 1, 2169 .flags = CLK_SET_RATE_PARENT, 2170 .ops = &clk_branch2_ops, 2171 }, 2172 }, 2173 }; 2174 2175 static struct clk_branch disp1_cc_mdss_dptx3_aux_clk = { 2176 .halt_reg = 0x20b8, 2177 .halt_check = BRANCH_HALT, 2178 .clkr = { 2179 .enable_reg = 0x20b8, 2180 .enable_mask = BIT(0), 2181 .hw.init = &(const struct clk_init_data) { 2182 .name = "disp1_cc_mdss_dptx3_aux_clk", 2183 .parent_hws = (const struct clk_hw*[]){ 2184 &disp1_cc_mdss_dptx3_aux_clk_src.clkr.hw, 2185 }, 2186 .num_parents = 1, 2187 .flags = CLK_SET_RATE_PARENT, 2188 .ops = &clk_branch2_ops, 2189 }, 2190 }, 2191 }; 2192 2193 static struct clk_branch disp0_cc_mdss_dptx3_link_clk = { 2194 .halt_reg = 0x20ac, 2195 .halt_check = BRANCH_HALT, 2196 .clkr = { 2197 .enable_reg = 0x20ac, 2198 .enable_mask = BIT(0), 2199 .hw.init = &(const struct clk_init_data) { 2200 .name = "disp0_cc_mdss_dptx3_link_clk", 2201 .parent_hws = (const struct clk_hw*[]){ 2202 &disp0_cc_mdss_dptx3_link_clk_src.clkr.hw, 2203 }, 2204 .num_parents = 1, 2205 .flags = CLK_SET_RATE_PARENT, 2206 .ops = &clk_branch2_ops, 2207 }, 2208 }, 2209 }; 2210 2211 static struct clk_branch disp1_cc_mdss_dptx3_link_clk = { 2212 .halt_reg = 0x20ac, 2213 .halt_check = BRANCH_HALT, 2214 .clkr = { 2215 .enable_reg = 0x20ac, 2216 .enable_mask = BIT(0), 2217 .hw.init = &(const struct clk_init_data) { 2218 .name = "disp1_cc_mdss_dptx3_link_clk", 2219 .parent_hws = (const struct clk_hw*[]){ 2220 &disp1_cc_mdss_dptx3_link_clk_src.clkr.hw, 2221 }, 2222 .num_parents = 1, 2223 .flags = CLK_SET_RATE_PARENT, 2224 .ops = &clk_branch2_ops, 2225 }, 2226 }, 2227 }; 2228 2229 static struct clk_branch disp0_cc_mdss_dptx3_link_intf_clk = { 2230 .halt_reg = 0x20b0, 2231 .halt_check = BRANCH_HALT, 2232 .clkr = { 2233 .enable_reg = 0x20b0, 2234 .enable_mask = BIT(0), 2235 .hw.init = &(const struct clk_init_data) { 2236 .name = "disp0_cc_mdss_dptx3_link_intf_clk", 2237 .parent_hws = (const struct clk_hw*[]){ 2238 &disp0_cc_mdss_dptx3_link_div_clk_src.clkr.hw, 2239 }, 2240 .num_parents = 1, 2241 .flags = CLK_SET_RATE_PARENT, 2242 .ops = &clk_branch2_ops, 2243 }, 2244 }, 2245 }; 2246 2247 static struct clk_branch disp1_cc_mdss_dptx3_link_intf_clk = { 2248 .halt_reg = 0x20b0, 2249 .halt_check = BRANCH_HALT, 2250 .clkr = { 2251 .enable_reg = 0x20b0, 2252 .enable_mask = BIT(0), 2253 .hw.init = &(const struct clk_init_data) { 2254 .name = "disp1_cc_mdss_dptx3_link_intf_clk", 2255 .parent_hws = (const struct clk_hw*[]){ 2256 &disp1_cc_mdss_dptx3_link_div_clk_src.clkr.hw, 2257 }, 2258 .num_parents = 1, 2259 .flags = CLK_SET_RATE_PARENT, 2260 .ops = &clk_branch2_ops, 2261 }, 2262 }, 2263 }; 2264 2265 static struct clk_branch disp0_cc_mdss_dptx3_pixel0_clk = { 2266 .halt_reg = 0x20a8, 2267 .halt_check = BRANCH_HALT, 2268 .clkr = { 2269 .enable_reg = 0x20a8, 2270 .enable_mask = BIT(0), 2271 .hw.init = &(const struct clk_init_data) { 2272 .name = "disp0_cc_mdss_dptx3_pixel0_clk", 2273 .parent_hws = (const struct clk_hw*[]){ 2274 &disp0_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, 2275 }, 2276 .num_parents = 1, 2277 .flags = CLK_SET_RATE_PARENT, 2278 .ops = &clk_branch2_ops, 2279 }, 2280 }, 2281 }; 2282 2283 static struct clk_branch disp1_cc_mdss_dptx3_pixel0_clk = { 2284 .halt_reg = 0x20a8, 2285 .halt_check = BRANCH_HALT, 2286 .clkr = { 2287 .enable_reg = 0x20a8, 2288 .enable_mask = BIT(0), 2289 .hw.init = &(const struct clk_init_data) { 2290 .name = "disp1_cc_mdss_dptx3_pixel0_clk", 2291 .parent_hws = (const struct clk_hw*[]){ 2292 &disp1_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, 2293 }, 2294 .num_parents = 1, 2295 .flags = CLK_SET_RATE_PARENT, 2296 .ops = &clk_branch2_ops, 2297 }, 2298 }, 2299 }; 2300 2301 static struct clk_branch disp0_cc_mdss_esc0_clk = { 2302 .halt_reg = 0x2054, 2303 .halt_check = BRANCH_HALT, 2304 .clkr = { 2305 .enable_reg = 0x2054, 2306 .enable_mask = BIT(0), 2307 .hw.init = &(const struct clk_init_data) { 2308 .name = "disp0_cc_mdss_esc0_clk", 2309 .parent_hws = (const struct clk_hw*[]){ 2310 &disp0_cc_mdss_esc0_clk_src.clkr.hw, 2311 }, 2312 .num_parents = 1, 2313 .flags = CLK_SET_RATE_PARENT, 2314 .ops = &clk_branch2_ops, 2315 }, 2316 }, 2317 }; 2318 2319 static struct clk_branch disp1_cc_mdss_esc0_clk = { 2320 .halt_reg = 0x2054, 2321 .halt_check = BRANCH_HALT, 2322 .clkr = { 2323 .enable_reg = 0x2054, 2324 .enable_mask = BIT(0), 2325 .hw.init = &(const struct clk_init_data) { 2326 .name = "disp1_cc_mdss_esc0_clk", 2327 .parent_hws = (const struct clk_hw*[]){ 2328 &disp1_cc_mdss_esc0_clk_src.clkr.hw, 2329 }, 2330 .num_parents = 1, 2331 .flags = CLK_SET_RATE_PARENT, 2332 .ops = &clk_branch2_ops, 2333 }, 2334 }, 2335 }; 2336 2337 static struct clk_branch disp0_cc_mdss_esc1_clk = { 2338 .halt_reg = 0x2058, 2339 .halt_check = BRANCH_HALT, 2340 .clkr = { 2341 .enable_reg = 0x2058, 2342 .enable_mask = BIT(0), 2343 .hw.init = &(const struct clk_init_data) { 2344 .name = "disp0_cc_mdss_esc1_clk", 2345 .parent_hws = (const struct clk_hw*[]){ 2346 &disp0_cc_mdss_esc1_clk_src.clkr.hw, 2347 }, 2348 .num_parents = 1, 2349 .flags = CLK_SET_RATE_PARENT, 2350 .ops = &clk_branch2_ops, 2351 }, 2352 }, 2353 }; 2354 2355 static struct clk_branch disp1_cc_mdss_esc1_clk = { 2356 .halt_reg = 0x2058, 2357 .halt_check = BRANCH_HALT, 2358 .clkr = { 2359 .enable_reg = 0x2058, 2360 .enable_mask = BIT(0), 2361 .hw.init = &(const struct clk_init_data) { 2362 .name = "disp1_cc_mdss_esc1_clk", 2363 .parent_hws = (const struct clk_hw*[]){ 2364 &disp1_cc_mdss_esc1_clk_src.clkr.hw, 2365 }, 2366 .num_parents = 1, 2367 .flags = CLK_SET_RATE_PARENT, 2368 .ops = &clk_branch2_ops, 2369 }, 2370 }, 2371 }; 2372 2373 static struct clk_branch disp0_cc_mdss_mdp1_clk = { 2374 .halt_reg = 0x2014, 2375 .halt_check = BRANCH_HALT, 2376 .clkr = { 2377 .enable_reg = 0x2014, 2378 .enable_mask = BIT(0), 2379 .hw.init = &(const struct clk_init_data) { 2380 .name = "disp0_cc_mdss_mdp1_clk", 2381 .parent_hws = (const struct clk_hw*[]){ 2382 &disp0_cc_mdss_mdp_clk_src.clkr.hw, 2383 }, 2384 .num_parents = 1, 2385 .flags = CLK_SET_RATE_PARENT, 2386 .ops = &clk_branch2_ops, 2387 }, 2388 }, 2389 }; 2390 2391 static struct clk_branch disp1_cc_mdss_mdp1_clk = { 2392 .halt_reg = 0x2014, 2393 .halt_check = BRANCH_HALT, 2394 .clkr = { 2395 .enable_reg = 0x2014, 2396 .enable_mask = BIT(0), 2397 .hw.init = &(const struct clk_init_data) { 2398 .name = "disp1_cc_mdss_mdp1_clk", 2399 .parent_hws = (const struct clk_hw*[]){ 2400 &disp1_cc_mdss_mdp_clk_src.clkr.hw, 2401 }, 2402 .num_parents = 1, 2403 .flags = CLK_SET_RATE_PARENT, 2404 .ops = &clk_branch2_ops, 2405 }, 2406 }, 2407 }; 2408 2409 static struct clk_branch disp0_cc_mdss_mdp_clk = { 2410 .halt_reg = 0x200c, 2411 .halt_check = BRANCH_HALT, 2412 .clkr = { 2413 .enable_reg = 0x200c, 2414 .enable_mask = BIT(0), 2415 .hw.init = &(const struct clk_init_data) { 2416 .name = "disp0_cc_mdss_mdp_clk", 2417 .parent_hws = (const struct clk_hw*[]){ 2418 &disp0_cc_mdss_mdp_clk_src.clkr.hw, 2419 }, 2420 .num_parents = 1, 2421 .flags = CLK_SET_RATE_PARENT, 2422 .ops = &clk_branch2_ops, 2423 }, 2424 }, 2425 }; 2426 2427 static struct clk_branch disp1_cc_mdss_mdp_clk = { 2428 .halt_reg = 0x200c, 2429 .halt_check = BRANCH_HALT, 2430 .clkr = { 2431 .enable_reg = 0x200c, 2432 .enable_mask = BIT(0), 2433 .hw.init = &(const struct clk_init_data) { 2434 .name = "disp1_cc_mdss_mdp_clk", 2435 .parent_hws = (const struct clk_hw*[]){ 2436 &disp1_cc_mdss_mdp_clk_src.clkr.hw, 2437 }, 2438 .num_parents = 1, 2439 .flags = CLK_SET_RATE_PARENT, 2440 .ops = &clk_branch2_ops, 2441 }, 2442 }, 2443 }; 2444 2445 static struct clk_branch disp0_cc_mdss_mdp_lut1_clk = { 2446 .halt_reg = 0x2034, 2447 .halt_check = BRANCH_HALT, 2448 .clkr = { 2449 .enable_reg = 0x2034, 2450 .enable_mask = BIT(0), 2451 .hw.init = &(const struct clk_init_data) { 2452 .name = "disp0_cc_mdss_mdp_lut1_clk", 2453 .parent_hws = (const struct clk_hw*[]){ 2454 &disp0_cc_mdss_mdp_clk_src.clkr.hw, 2455 }, 2456 .num_parents = 1, 2457 .flags = CLK_SET_RATE_PARENT, 2458 .ops = &clk_branch2_ops, 2459 }, 2460 }, 2461 }; 2462 2463 static struct clk_branch disp1_cc_mdss_mdp_lut1_clk = { 2464 .halt_reg = 0x2034, 2465 .halt_check = BRANCH_HALT, 2466 .clkr = { 2467 .enable_reg = 0x2034, 2468 .enable_mask = BIT(0), 2469 .hw.init = &(const struct clk_init_data) { 2470 .name = "disp1_cc_mdss_mdp_lut1_clk", 2471 .parent_hws = (const struct clk_hw*[]){ 2472 &disp1_cc_mdss_mdp_clk_src.clkr.hw, 2473 }, 2474 .num_parents = 1, 2475 .flags = CLK_SET_RATE_PARENT, 2476 .ops = &clk_branch2_ops, 2477 }, 2478 }, 2479 }; 2480 2481 static struct clk_branch disp0_cc_mdss_mdp_lut_clk = { 2482 .halt_reg = 0x202c, 2483 .halt_check = BRANCH_HALT_VOTED, 2484 .clkr = { 2485 .enable_reg = 0x202c, 2486 .enable_mask = BIT(0), 2487 .hw.init = &(const struct clk_init_data) { 2488 .name = "disp0_cc_mdss_mdp_lut_clk", 2489 .parent_hws = (const struct clk_hw*[]){ 2490 &disp0_cc_mdss_mdp_clk_src.clkr.hw, 2491 }, 2492 .num_parents = 1, 2493 .flags = CLK_SET_RATE_PARENT, 2494 .ops = &clk_branch2_ops, 2495 }, 2496 }, 2497 }; 2498 2499 static struct clk_branch disp1_cc_mdss_mdp_lut_clk = { 2500 .halt_reg = 0x202c, 2501 .halt_check = BRANCH_HALT_VOTED, 2502 .clkr = { 2503 .enable_reg = 0x202c, 2504 .enable_mask = BIT(0), 2505 .hw.init = &(const struct clk_init_data) { 2506 .name = "disp1_cc_mdss_mdp_lut_clk", 2507 .parent_hws = (const struct clk_hw*[]){ 2508 &disp1_cc_mdss_mdp_clk_src.clkr.hw, 2509 }, 2510 .num_parents = 1, 2511 .flags = CLK_SET_RATE_PARENT, 2512 .ops = &clk_branch2_ops, 2513 }, 2514 }, 2515 }; 2516 2517 static struct clk_branch disp0_cc_mdss_non_gdsc_ahb_clk = { 2518 .halt_reg = 0x4004, 2519 .halt_check = BRANCH_HALT_VOTED, 2520 .clkr = { 2521 .enable_reg = 0x4004, 2522 .enable_mask = BIT(0), 2523 .hw.init = &(const struct clk_init_data) { 2524 .name = "disp0_cc_mdss_non_gdsc_ahb_clk", 2525 .parent_hws = (const struct clk_hw*[]){ 2526 &disp0_cc_mdss_ahb_clk_src.clkr.hw, 2527 }, 2528 .num_parents = 1, 2529 .flags = CLK_SET_RATE_PARENT, 2530 .ops = &clk_branch2_ops, 2531 }, 2532 }, 2533 }; 2534 2535 static struct clk_branch disp1_cc_mdss_non_gdsc_ahb_clk = { 2536 .halt_reg = 0x4004, 2537 .halt_check = BRANCH_HALT_VOTED, 2538 .clkr = { 2539 .enable_reg = 0x4004, 2540 .enable_mask = BIT(0), 2541 .hw.init = &(const struct clk_init_data) { 2542 .name = "disp1_cc_mdss_non_gdsc_ahb_clk", 2543 .parent_hws = (const struct clk_hw*[]){ 2544 &disp1_cc_mdss_ahb_clk_src.clkr.hw, 2545 }, 2546 .num_parents = 1, 2547 .flags = CLK_SET_RATE_PARENT, 2548 .ops = &clk_branch2_ops, 2549 }, 2550 }, 2551 }; 2552 2553 static struct clk_branch disp0_cc_mdss_pclk0_clk = { 2554 .halt_reg = 0x2004, 2555 .halt_check = BRANCH_HALT, 2556 .clkr = { 2557 .enable_reg = 0x2004, 2558 .enable_mask = BIT(0), 2559 .hw.init = &(const struct clk_init_data) { 2560 .name = "disp0_cc_mdss_pclk0_clk", 2561 .parent_hws = (const struct clk_hw*[]){ 2562 &disp0_cc_mdss_pclk0_clk_src.clkr.hw, 2563 }, 2564 .num_parents = 1, 2565 .flags = CLK_SET_RATE_PARENT, 2566 .ops = &clk_branch2_ops, 2567 }, 2568 }, 2569 }; 2570 2571 static struct clk_branch disp1_cc_mdss_pclk0_clk = { 2572 .halt_reg = 0x2004, 2573 .halt_check = BRANCH_HALT, 2574 .clkr = { 2575 .enable_reg = 0x2004, 2576 .enable_mask = BIT(0), 2577 .hw.init = &(const struct clk_init_data) { 2578 .name = "disp1_cc_mdss_pclk0_clk", 2579 .parent_hws = (const struct clk_hw*[]){ 2580 &disp1_cc_mdss_pclk0_clk_src.clkr.hw, 2581 }, 2582 .num_parents = 1, 2583 .flags = CLK_SET_RATE_PARENT, 2584 .ops = &clk_branch2_ops, 2585 }, 2586 }, 2587 }; 2588 2589 static struct clk_branch disp0_cc_mdss_pclk1_clk = { 2590 .halt_reg = 0x2008, 2591 .halt_check = BRANCH_HALT, 2592 .clkr = { 2593 .enable_reg = 0x2008, 2594 .enable_mask = BIT(0), 2595 .hw.init = &(const struct clk_init_data) { 2596 .name = "disp0_cc_mdss_pclk1_clk", 2597 .parent_hws = (const struct clk_hw*[]){ 2598 &disp0_cc_mdss_pclk1_clk_src.clkr.hw, 2599 }, 2600 .num_parents = 1, 2601 .flags = CLK_SET_RATE_PARENT, 2602 .ops = &clk_branch2_ops, 2603 }, 2604 }, 2605 }; 2606 2607 static struct clk_branch disp1_cc_mdss_pclk1_clk = { 2608 .halt_reg = 0x2008, 2609 .halt_check = BRANCH_HALT, 2610 .clkr = { 2611 .enable_reg = 0x2008, 2612 .enable_mask = BIT(0), 2613 .hw.init = &(const struct clk_init_data) { 2614 .name = "disp1_cc_mdss_pclk1_clk", 2615 .parent_hws = (const struct clk_hw*[]){ 2616 &disp1_cc_mdss_pclk1_clk_src.clkr.hw, 2617 }, 2618 .num_parents = 1, 2619 .flags = CLK_SET_RATE_PARENT, 2620 .ops = &clk_branch2_ops, 2621 }, 2622 }, 2623 }; 2624 2625 static struct clk_branch disp0_cc_mdss_rot1_clk = { 2626 .halt_reg = 0x2024, 2627 .halt_check = BRANCH_HALT, 2628 .clkr = { 2629 .enable_reg = 0x2024, 2630 .enable_mask = BIT(0), 2631 .hw.init = &(const struct clk_init_data) { 2632 .name = "disp0_cc_mdss_rot1_clk", 2633 .parent_hws = (const struct clk_hw*[]){ 2634 &disp0_cc_mdss_rot_clk_src.clkr.hw, 2635 }, 2636 .num_parents = 1, 2637 .flags = CLK_SET_RATE_PARENT, 2638 .ops = &clk_branch2_ops, 2639 }, 2640 }, 2641 }; 2642 2643 static struct clk_branch disp1_cc_mdss_rot1_clk = { 2644 .halt_reg = 0x2024, 2645 .halt_check = BRANCH_HALT, 2646 .clkr = { 2647 .enable_reg = 0x2024, 2648 .enable_mask = BIT(0), 2649 .hw.init = &(const struct clk_init_data) { 2650 .name = "disp1_cc_mdss_rot1_clk", 2651 .parent_hws = (const struct clk_hw*[]){ 2652 &disp1_cc_mdss_rot_clk_src.clkr.hw, 2653 }, 2654 .num_parents = 1, 2655 .flags = CLK_SET_RATE_PARENT, 2656 .ops = &clk_branch2_ops, 2657 }, 2658 }, 2659 }; 2660 2661 static struct clk_branch disp0_cc_mdss_rot_clk = { 2662 .halt_reg = 0x201c, 2663 .halt_check = BRANCH_HALT, 2664 .clkr = { 2665 .enable_reg = 0x201c, 2666 .enable_mask = BIT(0), 2667 .hw.init = &(const struct clk_init_data) { 2668 .name = "disp0_cc_mdss_rot_clk", 2669 .parent_hws = (const struct clk_hw*[]){ 2670 &disp0_cc_mdss_rot_clk_src.clkr.hw, 2671 }, 2672 .num_parents = 1, 2673 .flags = CLK_SET_RATE_PARENT, 2674 .ops = &clk_branch2_ops, 2675 }, 2676 }, 2677 }; 2678 2679 static struct clk_branch disp1_cc_mdss_rot_clk = { 2680 .halt_reg = 0x201c, 2681 .halt_check = BRANCH_HALT, 2682 .clkr = { 2683 .enable_reg = 0x201c, 2684 .enable_mask = BIT(0), 2685 .hw.init = &(const struct clk_init_data) { 2686 .name = "disp1_cc_mdss_rot_clk", 2687 .parent_hws = (const struct clk_hw*[]){ 2688 &disp1_cc_mdss_rot_clk_src.clkr.hw, 2689 }, 2690 .num_parents = 1, 2691 .flags = CLK_SET_RATE_PARENT, 2692 .ops = &clk_branch2_ops, 2693 }, 2694 }, 2695 }; 2696 2697 static struct clk_branch disp0_cc_mdss_rscc_ahb_clk = { 2698 .halt_reg = 0x400c, 2699 .halt_check = BRANCH_HALT, 2700 .clkr = { 2701 .enable_reg = 0x400c, 2702 .enable_mask = BIT(0), 2703 .hw.init = &(const struct clk_init_data) { 2704 .name = "disp0_cc_mdss_rscc_ahb_clk", 2705 .parent_hws = (const struct clk_hw*[]){ 2706 &disp0_cc_mdss_ahb_clk_src.clkr.hw, 2707 }, 2708 .num_parents = 1, 2709 .flags = CLK_SET_RATE_PARENT, 2710 .ops = &clk_branch2_ops, 2711 }, 2712 }, 2713 }; 2714 2715 static struct clk_branch disp1_cc_mdss_rscc_ahb_clk = { 2716 .halt_reg = 0x400c, 2717 .halt_check = BRANCH_HALT, 2718 .clkr = { 2719 .enable_reg = 0x400c, 2720 .enable_mask = BIT(0), 2721 .hw.init = &(const struct clk_init_data) { 2722 .name = "disp1_cc_mdss_rscc_ahb_clk", 2723 .parent_hws = (const struct clk_hw*[]){ 2724 &disp1_cc_mdss_ahb_clk_src.clkr.hw, 2725 }, 2726 .num_parents = 1, 2727 .flags = CLK_SET_RATE_PARENT, 2728 .ops = &clk_branch2_ops, 2729 }, 2730 }, 2731 }; 2732 2733 static struct clk_branch disp0_cc_mdss_rscc_vsync_clk = { 2734 .halt_reg = 0x4008, 2735 .halt_check = BRANCH_HALT, 2736 .clkr = { 2737 .enable_reg = 0x4008, 2738 .enable_mask = BIT(0), 2739 .hw.init = &(const struct clk_init_data) { 2740 .name = "disp0_cc_mdss_rscc_vsync_clk", 2741 .parent_hws = (const struct clk_hw*[]){ 2742 &disp0_cc_mdss_vsync_clk_src.clkr.hw, 2743 }, 2744 .num_parents = 1, 2745 .flags = CLK_SET_RATE_PARENT, 2746 .ops = &clk_branch2_ops, 2747 }, 2748 }, 2749 }; 2750 2751 static struct clk_branch disp1_cc_mdss_rscc_vsync_clk = { 2752 .halt_reg = 0x4008, 2753 .halt_check = BRANCH_HALT, 2754 .clkr = { 2755 .enable_reg = 0x4008, 2756 .enable_mask = BIT(0), 2757 .hw.init = &(const struct clk_init_data) { 2758 .name = "disp1_cc_mdss_rscc_vsync_clk", 2759 .parent_hws = (const struct clk_hw*[]){ 2760 &disp1_cc_mdss_vsync_clk_src.clkr.hw, 2761 }, 2762 .num_parents = 1, 2763 .flags = CLK_SET_RATE_PARENT, 2764 .ops = &clk_branch2_ops, 2765 }, 2766 }, 2767 }; 2768 2769 static struct clk_branch disp0_cc_mdss_vsync1_clk = { 2770 .halt_reg = 0x2040, 2771 .halt_check = BRANCH_HALT, 2772 .clkr = { 2773 .enable_reg = 0x2040, 2774 .enable_mask = BIT(0), 2775 .hw.init = &(const struct clk_init_data) { 2776 .name = "disp0_cc_mdss_vsync1_clk", 2777 .parent_hws = (const struct clk_hw*[]){ 2778 &disp0_cc_mdss_vsync_clk_src.clkr.hw, 2779 }, 2780 .num_parents = 1, 2781 .flags = CLK_SET_RATE_PARENT, 2782 .ops = &clk_branch2_ops, 2783 }, 2784 }, 2785 }; 2786 2787 static struct clk_branch disp1_cc_mdss_vsync1_clk = { 2788 .halt_reg = 0x2040, 2789 .halt_check = BRANCH_HALT, 2790 .clkr = { 2791 .enable_reg = 0x2040, 2792 .enable_mask = BIT(0), 2793 .hw.init = &(const struct clk_init_data) { 2794 .name = "disp1_cc_mdss_vsync1_clk", 2795 .parent_hws = (const struct clk_hw*[]){ 2796 &disp1_cc_mdss_vsync_clk_src.clkr.hw, 2797 }, 2798 .num_parents = 1, 2799 .flags = CLK_SET_RATE_PARENT, 2800 .ops = &clk_branch2_ops, 2801 }, 2802 }, 2803 }; 2804 2805 static struct clk_branch disp0_cc_mdss_vsync_clk = { 2806 .halt_reg = 0x203c, 2807 .halt_check = BRANCH_HALT, 2808 .clkr = { 2809 .enable_reg = 0x203c, 2810 .enable_mask = BIT(0), 2811 .hw.init = &(const struct clk_init_data) { 2812 .name = "disp0_cc_mdss_vsync_clk", 2813 .parent_hws = (const struct clk_hw*[]){ 2814 &disp0_cc_mdss_vsync_clk_src.clkr.hw, 2815 }, 2816 .num_parents = 1, 2817 .flags = CLK_SET_RATE_PARENT, 2818 .ops = &clk_branch2_ops, 2819 }, 2820 }, 2821 }; 2822 2823 static struct clk_branch disp1_cc_mdss_vsync_clk = { 2824 .halt_reg = 0x203c, 2825 .halt_check = BRANCH_HALT, 2826 .clkr = { 2827 .enable_reg = 0x203c, 2828 .enable_mask = BIT(0), 2829 .hw.init = &(const struct clk_init_data) { 2830 .name = "disp1_cc_mdss_vsync_clk", 2831 .parent_hws = (const struct clk_hw*[]){ 2832 &disp1_cc_mdss_vsync_clk_src.clkr.hw, 2833 }, 2834 .num_parents = 1, 2835 .flags = CLK_SET_RATE_PARENT, 2836 .ops = &clk_branch2_ops, 2837 }, 2838 }, 2839 }; 2840 2841 static struct clk_branch disp0_cc_sleep_clk = { 2842 .halt_reg = 0x6078, 2843 .halt_check = BRANCH_HALT, 2844 .clkr = { 2845 .enable_reg = 0x6078, 2846 .enable_mask = BIT(0), 2847 .hw.init = &(const struct clk_init_data) { 2848 .name = "disp0_cc_sleep_clk", 2849 .parent_hws = (const struct clk_hw*[]){ 2850 &disp0_cc_sleep_clk_src.clkr.hw, 2851 }, 2852 .num_parents = 1, 2853 .flags = CLK_SET_RATE_PARENT, 2854 .ops = &clk_branch2_ops, 2855 }, 2856 }, 2857 }; 2858 2859 static struct clk_branch disp1_cc_sleep_clk = { 2860 .halt_reg = 0x6078, 2861 .halt_check = BRANCH_HALT, 2862 .clkr = { 2863 .enable_reg = 0x6078, 2864 .enable_mask = BIT(0), 2865 .hw.init = &(const struct clk_init_data) { 2866 .name = "disp1_cc_sleep_clk", 2867 .parent_hws = (const struct clk_hw*[]){ 2868 &disp1_cc_sleep_clk_src.clkr.hw, 2869 }, 2870 .num_parents = 1, 2871 .flags = CLK_SET_RATE_PARENT, 2872 .ops = &clk_branch2_ops, 2873 }, 2874 }, 2875 }; 2876 2877 static struct clk_regmap *disp0_cc_sc8280xp_clocks[] = { 2878 [DISP_CC_MDSS_AHB1_CLK] = &disp0_cc_mdss_ahb1_clk.clkr, 2879 [DISP_CC_MDSS_AHB_CLK] = &disp0_cc_mdss_ahb_clk.clkr, 2880 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp0_cc_mdss_ahb_clk_src.clkr, 2881 [DISP_CC_MDSS_BYTE0_CLK] = &disp0_cc_mdss_byte0_clk.clkr, 2882 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp0_cc_mdss_byte0_clk_src.clkr, 2883 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp0_cc_mdss_byte0_div_clk_src.clkr, 2884 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp0_cc_mdss_byte0_intf_clk.clkr, 2885 [DISP_CC_MDSS_BYTE1_CLK] = &disp0_cc_mdss_byte1_clk.clkr, 2886 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp0_cc_mdss_byte1_clk_src.clkr, 2887 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp0_cc_mdss_byte1_div_clk_src.clkr, 2888 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp0_cc_mdss_byte1_intf_clk.clkr, 2889 [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp0_cc_mdss_dptx0_aux_clk.clkr, 2890 [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp0_cc_mdss_dptx0_aux_clk_src.clkr, 2891 [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp0_cc_mdss_dptx0_link_clk.clkr, 2892 [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp0_cc_mdss_dptx0_link_clk_src.clkr, 2893 [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp0_cc_mdss_dptx0_link_div_clk_src.clkr, 2894 [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp0_cc_mdss_dptx0_link_intf_clk.clkr, 2895 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp0_cc_mdss_dptx0_pixel0_clk.clkr, 2896 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp0_cc_mdss_dptx0_pixel0_clk_src.clkr, 2897 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp0_cc_mdss_dptx0_pixel1_clk.clkr, 2898 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp0_cc_mdss_dptx0_pixel1_clk_src.clkr, 2899 [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = &disp0_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, 2900 [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp0_cc_mdss_dptx1_aux_clk.clkr, 2901 [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp0_cc_mdss_dptx1_aux_clk_src.clkr, 2902 [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp0_cc_mdss_dptx1_link_clk.clkr, 2903 [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp0_cc_mdss_dptx1_link_clk_src.clkr, 2904 [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp0_cc_mdss_dptx1_link_div_clk_src.clkr, 2905 [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp0_cc_mdss_dptx1_link_intf_clk.clkr, 2906 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp0_cc_mdss_dptx1_pixel0_clk.clkr, 2907 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp0_cc_mdss_dptx1_pixel0_clk_src.clkr, 2908 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp0_cc_mdss_dptx1_pixel1_clk.clkr, 2909 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp0_cc_mdss_dptx1_pixel1_clk_src.clkr, 2910 [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] = &disp0_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, 2911 [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp0_cc_mdss_dptx2_aux_clk.clkr, 2912 [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp0_cc_mdss_dptx2_aux_clk_src.clkr, 2913 [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp0_cc_mdss_dptx2_link_clk.clkr, 2914 [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp0_cc_mdss_dptx2_link_clk_src.clkr, 2915 [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp0_cc_mdss_dptx2_link_div_clk_src.clkr, 2916 [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp0_cc_mdss_dptx2_link_intf_clk.clkr, 2917 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp0_cc_mdss_dptx2_pixel0_clk.clkr, 2918 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp0_cc_mdss_dptx2_pixel0_clk_src.clkr, 2919 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp0_cc_mdss_dptx2_pixel1_clk.clkr, 2920 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp0_cc_mdss_dptx2_pixel1_clk_src.clkr, 2921 [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp0_cc_mdss_dptx3_aux_clk.clkr, 2922 [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp0_cc_mdss_dptx3_aux_clk_src.clkr, 2923 [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp0_cc_mdss_dptx3_link_clk.clkr, 2924 [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp0_cc_mdss_dptx3_link_clk_src.clkr, 2925 [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp0_cc_mdss_dptx3_link_div_clk_src.clkr, 2926 [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp0_cc_mdss_dptx3_link_intf_clk.clkr, 2927 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp0_cc_mdss_dptx3_pixel0_clk.clkr, 2928 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp0_cc_mdss_dptx3_pixel0_clk_src.clkr, 2929 [DISP_CC_MDSS_ESC0_CLK] = &disp0_cc_mdss_esc0_clk.clkr, 2930 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp0_cc_mdss_esc0_clk_src.clkr, 2931 [DISP_CC_MDSS_ESC1_CLK] = &disp0_cc_mdss_esc1_clk.clkr, 2932 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp0_cc_mdss_esc1_clk_src.clkr, 2933 [DISP_CC_MDSS_MDP1_CLK] = &disp0_cc_mdss_mdp1_clk.clkr, 2934 [DISP_CC_MDSS_MDP_CLK] = &disp0_cc_mdss_mdp_clk.clkr, 2935 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp0_cc_mdss_mdp_clk_src.clkr, 2936 [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp0_cc_mdss_mdp_lut1_clk.clkr, 2937 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp0_cc_mdss_mdp_lut_clk.clkr, 2938 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp0_cc_mdss_non_gdsc_ahb_clk.clkr, 2939 [DISP_CC_MDSS_PCLK0_CLK] = &disp0_cc_mdss_pclk0_clk.clkr, 2940 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp0_cc_mdss_pclk0_clk_src.clkr, 2941 [DISP_CC_MDSS_PCLK1_CLK] = &disp0_cc_mdss_pclk1_clk.clkr, 2942 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp0_cc_mdss_pclk1_clk_src.clkr, 2943 [DISP_CC_MDSS_ROT1_CLK] = &disp0_cc_mdss_rot1_clk.clkr, 2944 [DISP_CC_MDSS_ROT_CLK] = &disp0_cc_mdss_rot_clk.clkr, 2945 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp0_cc_mdss_rot_clk_src.clkr, 2946 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp0_cc_mdss_rscc_ahb_clk.clkr, 2947 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp0_cc_mdss_rscc_vsync_clk.clkr, 2948 [DISP_CC_MDSS_VSYNC1_CLK] = &disp0_cc_mdss_vsync1_clk.clkr, 2949 [DISP_CC_MDSS_VSYNC_CLK] = &disp0_cc_mdss_vsync_clk.clkr, 2950 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp0_cc_mdss_vsync_clk_src.clkr, 2951 [DISP_CC_PLL0] = &disp0_cc_pll0.clkr, 2952 [DISP_CC_PLL1] = &disp0_cc_pll1.clkr, 2953 [DISP_CC_PLL1_OUT_EVEN] = &disp0_cc_pll1_out_even.clkr, 2954 [DISP_CC_PLL2] = &disp0_cc_pll2.clkr, 2955 [DISP_CC_SLEEP_CLK] = &disp0_cc_sleep_clk.clkr, 2956 [DISP_CC_SLEEP_CLK_SRC] = &disp0_cc_sleep_clk_src.clkr, 2957 }; 2958 2959 static struct clk_regmap *disp1_cc_sc8280xp_clocks[] = { 2960 [DISP_CC_MDSS_AHB1_CLK] = &disp1_cc_mdss_ahb1_clk.clkr, 2961 [DISP_CC_MDSS_AHB_CLK] = &disp1_cc_mdss_ahb_clk.clkr, 2962 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp1_cc_mdss_ahb_clk_src.clkr, 2963 [DISP_CC_MDSS_BYTE0_CLK] = &disp1_cc_mdss_byte0_clk.clkr, 2964 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp1_cc_mdss_byte0_clk_src.clkr, 2965 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp1_cc_mdss_byte0_div_clk_src.clkr, 2966 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp1_cc_mdss_byte0_intf_clk.clkr, 2967 [DISP_CC_MDSS_BYTE1_CLK] = &disp1_cc_mdss_byte1_clk.clkr, 2968 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp1_cc_mdss_byte1_clk_src.clkr, 2969 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp1_cc_mdss_byte1_div_clk_src.clkr, 2970 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp1_cc_mdss_byte1_intf_clk.clkr, 2971 [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp1_cc_mdss_dptx0_aux_clk.clkr, 2972 [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp1_cc_mdss_dptx0_aux_clk_src.clkr, 2973 [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp1_cc_mdss_dptx0_link_clk.clkr, 2974 [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp1_cc_mdss_dptx0_link_clk_src.clkr, 2975 [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp1_cc_mdss_dptx0_link_div_clk_src.clkr, 2976 [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp1_cc_mdss_dptx0_link_intf_clk.clkr, 2977 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp1_cc_mdss_dptx0_pixel0_clk.clkr, 2978 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp1_cc_mdss_dptx0_pixel0_clk_src.clkr, 2979 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp1_cc_mdss_dptx0_pixel1_clk.clkr, 2980 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp1_cc_mdss_dptx0_pixel1_clk_src.clkr, 2981 [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = &disp1_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, 2982 [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp1_cc_mdss_dptx1_aux_clk.clkr, 2983 [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp1_cc_mdss_dptx1_aux_clk_src.clkr, 2984 [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp1_cc_mdss_dptx1_link_clk.clkr, 2985 [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp1_cc_mdss_dptx1_link_clk_src.clkr, 2986 [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp1_cc_mdss_dptx1_link_div_clk_src.clkr, 2987 [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp1_cc_mdss_dptx1_link_intf_clk.clkr, 2988 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp1_cc_mdss_dptx1_pixel0_clk.clkr, 2989 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp1_cc_mdss_dptx1_pixel0_clk_src.clkr, 2990 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp1_cc_mdss_dptx1_pixel1_clk.clkr, 2991 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp1_cc_mdss_dptx1_pixel1_clk_src.clkr, 2992 [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] = &disp1_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, 2993 [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp1_cc_mdss_dptx2_aux_clk.clkr, 2994 [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp1_cc_mdss_dptx2_aux_clk_src.clkr, 2995 [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp1_cc_mdss_dptx2_link_clk.clkr, 2996 [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp1_cc_mdss_dptx2_link_clk_src.clkr, 2997 [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp1_cc_mdss_dptx2_link_div_clk_src.clkr, 2998 [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp1_cc_mdss_dptx2_link_intf_clk.clkr, 2999 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp1_cc_mdss_dptx2_pixel0_clk.clkr, 3000 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp1_cc_mdss_dptx2_pixel0_clk_src.clkr, 3001 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp1_cc_mdss_dptx2_pixel1_clk.clkr, 3002 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp1_cc_mdss_dptx2_pixel1_clk_src.clkr, 3003 [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp1_cc_mdss_dptx3_aux_clk.clkr, 3004 [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp1_cc_mdss_dptx3_aux_clk_src.clkr, 3005 [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp1_cc_mdss_dptx3_link_clk.clkr, 3006 [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp1_cc_mdss_dptx3_link_clk_src.clkr, 3007 [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp1_cc_mdss_dptx3_link_div_clk_src.clkr, 3008 [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp1_cc_mdss_dptx3_link_intf_clk.clkr, 3009 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp1_cc_mdss_dptx3_pixel0_clk.clkr, 3010 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp1_cc_mdss_dptx3_pixel0_clk_src.clkr, 3011 [DISP_CC_MDSS_ESC0_CLK] = &disp1_cc_mdss_esc0_clk.clkr, 3012 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp1_cc_mdss_esc0_clk_src.clkr, 3013 [DISP_CC_MDSS_ESC1_CLK] = &disp1_cc_mdss_esc1_clk.clkr, 3014 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp1_cc_mdss_esc1_clk_src.clkr, 3015 [DISP_CC_MDSS_MDP1_CLK] = &disp1_cc_mdss_mdp1_clk.clkr, 3016 [DISP_CC_MDSS_MDP_CLK] = &disp1_cc_mdss_mdp_clk.clkr, 3017 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp1_cc_mdss_mdp_clk_src.clkr, 3018 [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp1_cc_mdss_mdp_lut1_clk.clkr, 3019 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp1_cc_mdss_mdp_lut_clk.clkr, 3020 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp1_cc_mdss_non_gdsc_ahb_clk.clkr, 3021 [DISP_CC_MDSS_PCLK0_CLK] = &disp1_cc_mdss_pclk0_clk.clkr, 3022 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp1_cc_mdss_pclk0_clk_src.clkr, 3023 [DISP_CC_MDSS_PCLK1_CLK] = &disp1_cc_mdss_pclk1_clk.clkr, 3024 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp1_cc_mdss_pclk1_clk_src.clkr, 3025 [DISP_CC_MDSS_ROT1_CLK] = &disp1_cc_mdss_rot1_clk.clkr, 3026 [DISP_CC_MDSS_ROT_CLK] = &disp1_cc_mdss_rot_clk.clkr, 3027 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp1_cc_mdss_rot_clk_src.clkr, 3028 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp1_cc_mdss_rscc_ahb_clk.clkr, 3029 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp1_cc_mdss_rscc_vsync_clk.clkr, 3030 [DISP_CC_MDSS_VSYNC1_CLK] = &disp1_cc_mdss_vsync1_clk.clkr, 3031 [DISP_CC_MDSS_VSYNC_CLK] = &disp1_cc_mdss_vsync_clk.clkr, 3032 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp1_cc_mdss_vsync_clk_src.clkr, 3033 [DISP_CC_PLL0] = &disp1_cc_pll0.clkr, 3034 [DISP_CC_PLL1] = &disp1_cc_pll1.clkr, 3035 [DISP_CC_PLL1_OUT_EVEN] = &disp1_cc_pll1_out_even.clkr, 3036 [DISP_CC_PLL2] = &disp1_cc_pll2.clkr, 3037 [DISP_CC_SLEEP_CLK] = &disp1_cc_sleep_clk.clkr, 3038 [DISP_CC_SLEEP_CLK_SRC] = &disp1_cc_sleep_clk_src.clkr, 3039 }; 3040 3041 static const struct qcom_reset_map disp_cc_sc8280xp_resets[] = { 3042 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 }, 3043 [DISP_CC_MDSS_RSCC_BCR] = { 0x4000 }, 3044 }; 3045 3046 static struct gdsc disp0_mdss_gdsc = { 3047 .gdscr = 0x3000, 3048 .en_rest_wait_val = 0x2, 3049 .en_few_wait_val = 0x2, 3050 .clk_dis_wait_val = 0xf, 3051 .pd = { 3052 .name = "disp0_mdss_gdsc", 3053 }, 3054 .pwrsts = PWRSTS_OFF_ON, 3055 .flags = HW_CTRL | RETAIN_FF_ENABLE, 3056 }; 3057 3058 static struct gdsc disp1_mdss_gdsc = { 3059 .gdscr = 0x3000, 3060 .en_rest_wait_val = 0x2, 3061 .en_few_wait_val = 0x2, 3062 .clk_dis_wait_val = 0xf, 3063 .pd = { 3064 .name = "disp1_mdss_gdsc", 3065 }, 3066 .pwrsts = PWRSTS_OFF_ON, 3067 .flags = HW_CTRL | RETAIN_FF_ENABLE, 3068 }; 3069 3070 static struct gdsc disp0_mdss_int2_gdsc = { 3071 .gdscr = 0xa000, 3072 .en_rest_wait_val = 0x2, 3073 .en_few_wait_val = 0x2, 3074 .clk_dis_wait_val = 0xf, 3075 .pd = { 3076 .name = "disp0_mdss_int2_gdsc", 3077 }, 3078 .pwrsts = PWRSTS_OFF_ON, 3079 .flags = HW_CTRL | RETAIN_FF_ENABLE, 3080 }; 3081 3082 static struct gdsc disp1_mdss_int2_gdsc = { 3083 .gdscr = 0xa000, 3084 .en_rest_wait_val = 0x2, 3085 .en_few_wait_val = 0x2, 3086 .clk_dis_wait_val = 0xf, 3087 .pd = { 3088 .name = "disp1_mdss_int2_gdsc", 3089 }, 3090 .pwrsts = PWRSTS_OFF_ON, 3091 .flags = HW_CTRL | RETAIN_FF_ENABLE, 3092 }; 3093 3094 static struct gdsc *disp0_cc_sc8280xp_gdscs[] = { 3095 [MDSS_GDSC] = &disp0_mdss_gdsc, 3096 [MDSS_INT2_GDSC] = &disp0_mdss_int2_gdsc, 3097 }; 3098 3099 static struct gdsc *disp1_cc_sc8280xp_gdscs[] = { 3100 [MDSS_GDSC] = &disp1_mdss_gdsc, 3101 [MDSS_INT2_GDSC] = &disp1_mdss_int2_gdsc, 3102 }; 3103 3104 static const struct regmap_config disp_cc_sc8280xp_regmap_config = { 3105 .reg_bits = 32, 3106 .reg_stride = 4, 3107 .val_bits = 32, 3108 .max_register = 0x10000, 3109 .fast_io = true, 3110 }; 3111 3112 static const struct qcom_cc_desc disp0_cc_sc8280xp_desc = { 3113 .config = &disp_cc_sc8280xp_regmap_config, 3114 .clks = disp0_cc_sc8280xp_clocks, 3115 .num_clks = ARRAY_SIZE(disp0_cc_sc8280xp_clocks), 3116 .resets = disp_cc_sc8280xp_resets, 3117 .num_resets = ARRAY_SIZE(disp_cc_sc8280xp_resets), 3118 .gdscs = disp0_cc_sc8280xp_gdscs, 3119 .num_gdscs = ARRAY_SIZE(disp0_cc_sc8280xp_gdscs), 3120 }; 3121 3122 static const struct qcom_cc_desc disp1_cc_sc8280xp_desc = { 3123 .config = &disp_cc_sc8280xp_regmap_config, 3124 .clks = disp1_cc_sc8280xp_clocks, 3125 .num_clks = ARRAY_SIZE(disp1_cc_sc8280xp_clocks), 3126 .resets = disp_cc_sc8280xp_resets, 3127 .num_resets = ARRAY_SIZE(disp_cc_sc8280xp_resets), 3128 .gdscs = disp1_cc_sc8280xp_gdscs, 3129 .num_gdscs = ARRAY_SIZE(disp1_cc_sc8280xp_gdscs), 3130 }; 3131 3132 #define clkr_to_alpha_clk_pll(_clkr) container_of(_clkr, struct clk_alpha_pll, clkr) 3133 3134 static int disp_cc_sc8280xp_probe(struct platform_device *pdev) 3135 { 3136 const struct qcom_cc_desc *desc; 3137 struct regmap *regmap; 3138 int ret; 3139 3140 desc = device_get_match_data(&pdev->dev); 3141 3142 ret = devm_pm_runtime_enable(&pdev->dev); 3143 if (ret) 3144 return ret; 3145 3146 ret = devm_pm_clk_create(&pdev->dev); 3147 if (ret) 3148 return ret; 3149 3150 ret = pm_clk_add(&pdev->dev, NULL); 3151 if (ret < 0) { 3152 dev_err(&pdev->dev, "failed to acquire ahb clock\n"); 3153 return ret; 3154 } 3155 3156 ret = pm_runtime_resume_and_get(&pdev->dev); 3157 if (ret) 3158 return ret; 3159 3160 regmap = qcom_cc_map(pdev, desc); 3161 if (IS_ERR(regmap)) { 3162 ret = PTR_ERR(regmap); 3163 goto out_pm_runtime_put; 3164 } 3165 3166 clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL0]), regmap, &disp_cc_pll0_config); 3167 clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL1]), regmap, &disp_cc_pll1_config); 3168 clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL2]), regmap, &disp_cc_pll2_config); 3169 3170 ret = qcom_cc_really_probe(&pdev->dev, desc, regmap); 3171 if (ret) { 3172 dev_err(&pdev->dev, "Failed to register display clock controller\n"); 3173 goto out_pm_runtime_put; 3174 } 3175 3176 /* Keep some clocks always-on */ 3177 qcom_branch_set_clk_en(regmap, 0x605c); /* DISP_CC_XO_CLK */ 3178 3179 out_pm_runtime_put: 3180 pm_runtime_put_sync(&pdev->dev); 3181 3182 return ret; 3183 } 3184 3185 static const struct of_device_id disp_cc_sc8280xp_match_table[] = { 3186 { .compatible = "qcom,sc8280xp-dispcc0", .data = &disp0_cc_sc8280xp_desc }, 3187 { .compatible = "qcom,sc8280xp-dispcc1", .data = &disp1_cc_sc8280xp_desc }, 3188 { } 3189 }; 3190 MODULE_DEVICE_TABLE(of, disp_cc_sc8280xp_match_table); 3191 3192 static struct platform_driver disp_cc_sc8280xp_driver = { 3193 .probe = disp_cc_sc8280xp_probe, 3194 .driver = { 3195 .name = "disp_cc-sc8280xp", 3196 .of_match_table = disp_cc_sc8280xp_match_table, 3197 }, 3198 }; 3199 3200 module_platform_driver(disp_cc_sc8280xp_driver); 3201 3202 MODULE_DESCRIPTION("Qualcomm SC8280XP dispcc driver"); 3203 MODULE_LICENSE("GPL"); 3204