1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Ltd. 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/pm_clock.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/regmap.h> 13 14 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> 15 16 #include "clk-alpha-pll.h" 17 #include "clk-branch.h" 18 #include "clk-rcg.h" 19 #include "clk-regmap-divider.h" 20 #include "common.h" 21 #include "gdsc.h" 22 #include "reset.h" 23 24 /* Need to match the order of clocks in DT binding */ 25 enum { 26 DT_IFACE, 27 DT_BI_TCXO, 28 DT_SLEEP_CLK, 29 DT_DP0_PHY_PLL_LINK_CLK, 30 DT_DP0_PHY_PLL_VCO_DIV_CLK, 31 DT_DP1_PHY_PLL_LINK_CLK, 32 DT_DP1_PHY_PLL_VCO_DIV_CLK, 33 DT_DP2_PHY_PLL_LINK_CLK, 34 DT_DP2_PHY_PLL_VCO_DIV_CLK, 35 DT_DP3_PHY_PLL_LINK_CLK, 36 DT_DP3_PHY_PLL_VCO_DIV_CLK, 37 DT_DSI0_PHY_PLL_OUT_BYTECLK, 38 DT_DSI0_PHY_PLL_OUT_DSICLK, 39 DT_DSI1_PHY_PLL_OUT_BYTECLK, 40 DT_DSI1_PHY_PLL_OUT_DSICLK, 41 }; 42 43 enum { 44 P_BI_TCXO, 45 P_DP0_PHY_PLL_LINK_CLK, 46 P_DP0_PHY_PLL_VCO_DIV_CLK, 47 P_DP1_PHY_PLL_LINK_CLK, 48 P_DP1_PHY_PLL_VCO_DIV_CLK, 49 P_DP2_PHY_PLL_LINK_CLK, 50 P_DP2_PHY_PLL_VCO_DIV_CLK, 51 P_DP3_PHY_PLL_LINK_CLK, 52 P_DP3_PHY_PLL_VCO_DIV_CLK, 53 P_DSI0_PHY_PLL_OUT_BYTECLK, 54 P_DSI0_PHY_PLL_OUT_DSICLK, 55 P_DSI1_PHY_PLL_OUT_BYTECLK, 56 P_DSI1_PHY_PLL_OUT_DSICLK, 57 P_DISPn_CC_PLL0_OUT_MAIN, 58 P_DISPn_CC_PLL1_OUT_EVEN, 59 P_DISPn_CC_PLL1_OUT_MAIN, 60 P_DISPn_CC_PLL2_OUT_MAIN, 61 P_SLEEP_CLK, 62 }; 63 64 static const struct clk_parent_data parent_data_tcxo = { .index = DT_BI_TCXO }; 65 66 static const struct pll_vco lucid_5lpe_vco[] = { 67 { 249600000, 1800000000, 0 }, 68 }; 69 70 static const struct alpha_pll_config disp_cc_pll0_config = { 71 .l = 0x4e, 72 .alpha = 0x2000, 73 .config_ctl_val = 0x20485699, 74 .config_ctl_hi_val = 0x00002261, 75 .config_ctl_hi1_val = 0x2a9a699c, 76 .test_ctl_val = 0x00000000, 77 .test_ctl_hi_val = 0x00000000, 78 .test_ctl_hi1_val = 0x01800000, 79 .user_ctl_val = 0x00000000, 80 .user_ctl_hi_val = 0x00000805, 81 .user_ctl_hi1_val = 0x00000000, 82 }; 83 84 static struct clk_alpha_pll disp0_cc_pll0 = { 85 .offset = 0x0, 86 .vco_table = lucid_5lpe_vco, 87 .num_vco = ARRAY_SIZE(lucid_5lpe_vco), 88 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 89 .clkr = { 90 .hw.init = &(const struct clk_init_data) { 91 .name = "disp0_cc_pll0", 92 .parent_data = &parent_data_tcxo, 93 .num_parents = 1, 94 .ops = &clk_alpha_pll_lucid_5lpe_ops, 95 }, 96 }, 97 }; 98 99 static struct clk_alpha_pll disp1_cc_pll0 = { 100 .offset = 0x0, 101 .vco_table = lucid_5lpe_vco, 102 .num_vco = ARRAY_SIZE(lucid_5lpe_vco), 103 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 104 .clkr = { 105 .hw.init = &(const struct clk_init_data) { 106 .name = "disp1_cc_pll0", 107 .parent_data = &parent_data_tcxo, 108 .num_parents = 1, 109 .ops = &clk_alpha_pll_lucid_5lpe_ops, 110 }, 111 }, 112 }; 113 114 static const struct alpha_pll_config disp_cc_pll1_config = { 115 .l = 0x1f, 116 .alpha = 0x4000, 117 .config_ctl_val = 0x20485699, 118 .config_ctl_hi_val = 0x00002261, 119 .config_ctl_hi1_val = 0x2a9a699c, 120 .test_ctl_val = 0x00000000, 121 .test_ctl_hi_val = 0x00000000, 122 .test_ctl_hi1_val = 0x01800000, 123 .user_ctl_val = 0x00000100, 124 .user_ctl_hi_val = 0x00000805, 125 .user_ctl_hi1_val = 0x00000000, 126 }; 127 128 static struct clk_alpha_pll disp0_cc_pll1 = { 129 .offset = 0x1000, 130 .vco_table = lucid_5lpe_vco, 131 .num_vco = ARRAY_SIZE(lucid_5lpe_vco), 132 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 133 .clkr = { 134 .hw.init = &(const struct clk_init_data) { 135 .name = "disp0_cc_pll1", 136 .parent_data = &parent_data_tcxo, 137 .num_parents = 1, 138 .ops = &clk_alpha_pll_lucid_5lpe_ops, 139 }, 140 }, 141 }; 142 143 static struct clk_alpha_pll disp1_cc_pll1 = { 144 .offset = 0x1000, 145 .vco_table = lucid_5lpe_vco, 146 .num_vco = ARRAY_SIZE(lucid_5lpe_vco), 147 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 148 .clkr = { 149 .hw.init = &(const struct clk_init_data) { 150 .name = "disp1_cc_pll1", 151 .parent_data = &parent_data_tcxo, 152 .num_parents = 1, 153 .ops = &clk_alpha_pll_lucid_5lpe_ops, 154 }, 155 }, 156 }; 157 158 static const struct clk_div_table post_div_table_disp_cc_pll1_out_even[] = { 159 { 0x1, 2 }, 160 { } 161 }; 162 163 static struct clk_alpha_pll_postdiv disp0_cc_pll1_out_even = { 164 .offset = 0x1000, 165 .post_div_shift = 8, 166 .post_div_table = post_div_table_disp_cc_pll1_out_even, 167 .num_post_div = ARRAY_SIZE(post_div_table_disp_cc_pll1_out_even), 168 .width = 4, 169 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 170 .clkr.hw.init = &(const struct clk_init_data) { 171 .name = "disp0_cc_pll1_out_even", 172 .parent_hws = (const struct clk_hw*[]){ 173 &disp0_cc_pll1.clkr.hw, 174 }, 175 .num_parents = 1, 176 .ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops, 177 }, 178 }; 179 180 static struct clk_alpha_pll_postdiv disp1_cc_pll1_out_even = { 181 .offset = 0x1000, 182 .post_div_shift = 8, 183 .post_div_table = post_div_table_disp_cc_pll1_out_even, 184 .num_post_div = ARRAY_SIZE(post_div_table_disp_cc_pll1_out_even), 185 .width = 4, 186 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 187 .clkr.hw.init = &(const struct clk_init_data) { 188 .name = "disp1_cc_pll1_out_even", 189 .parent_hws = (const struct clk_hw*[]){ 190 &disp1_cc_pll1.clkr.hw, 191 }, 192 .num_parents = 1, 193 .ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops, 194 }, 195 }; 196 197 static const struct alpha_pll_config disp_cc_pll2_config = { 198 .l = 0x46, 199 .alpha = 0x5000, 200 .config_ctl_val = 0x20485699, 201 .config_ctl_hi_val = 0x00002261, 202 .config_ctl_hi1_val = 0x2a9a699c, 203 .test_ctl_val = 0x00000000, 204 .test_ctl_hi_val = 0x00000000, 205 .test_ctl_hi1_val = 0x01800000, 206 .user_ctl_val = 0x00000000, 207 .user_ctl_hi_val = 0x00000805, 208 .user_ctl_hi1_val = 0x00000000, 209 }; 210 211 static struct clk_alpha_pll disp0_cc_pll2 = { 212 .offset = 0x9000, 213 .vco_table = lucid_5lpe_vco, 214 .num_vco = ARRAY_SIZE(lucid_5lpe_vco), 215 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 216 .clkr = { 217 .hw.init = &(const struct clk_init_data) { 218 .name = "disp0_cc_pll2", 219 .parent_data = &parent_data_tcxo, 220 .num_parents = 1, 221 .ops = &clk_alpha_pll_lucid_5lpe_ops, 222 }, 223 }, 224 }; 225 226 static struct clk_alpha_pll disp1_cc_pll2 = { 227 .offset = 0x9000, 228 .vco_table = lucid_5lpe_vco, 229 .num_vco = ARRAY_SIZE(lucid_5lpe_vco), 230 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 231 .clkr = { 232 .hw.init = &(const struct clk_init_data) { 233 .name = "disp1_cc_pll2", 234 .parent_data = &parent_data_tcxo, 235 .num_parents = 1, 236 .ops = &clk_alpha_pll_lucid_5lpe_ops, 237 }, 238 }, 239 }; 240 241 static const struct parent_map disp_cc_parent_map_0[] = { 242 { P_BI_TCXO, 0 }, 243 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 244 { P_DP1_PHY_PLL_LINK_CLK, 2 }, 245 { P_DP2_PHY_PLL_LINK_CLK, 3 }, 246 { P_DP3_PHY_PLL_LINK_CLK, 4 }, 247 { P_DISPn_CC_PLL2_OUT_MAIN, 5 }, 248 }; 249 250 static const struct clk_parent_data disp0_cc_parent_data_0[] = { 251 { .index = DT_BI_TCXO }, 252 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 253 { .index = DT_DP1_PHY_PLL_LINK_CLK }, 254 { .index = DT_DP2_PHY_PLL_LINK_CLK }, 255 { .index = DT_DP3_PHY_PLL_LINK_CLK }, 256 { .hw = &disp0_cc_pll2.clkr.hw }, 257 }; 258 259 static const struct clk_parent_data disp1_cc_parent_data_0[] = { 260 { .index = DT_BI_TCXO }, 261 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 262 { .index = DT_DP1_PHY_PLL_LINK_CLK }, 263 { .index = DT_DP2_PHY_PLL_LINK_CLK }, 264 { .index = DT_DP3_PHY_PLL_LINK_CLK }, 265 { .hw = &disp1_cc_pll2.clkr.hw }, 266 }; 267 268 static const struct parent_map disp_cc_parent_map_1[] = { 269 { P_BI_TCXO, 0 }, 270 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 271 { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 }, 272 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, 273 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, 274 { P_DISPn_CC_PLL2_OUT_MAIN, 5 }, 275 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, 276 }; 277 278 static const struct clk_parent_data disp0_cc_parent_data_1[] = { 279 { .index = DT_BI_TCXO }, 280 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 281 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK }, 282 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 283 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 284 { .hw = &disp0_cc_pll2.clkr.hw }, 285 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 286 }; 287 288 static const struct clk_parent_data disp1_cc_parent_data_1[] = { 289 { .index = DT_BI_TCXO }, 290 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 291 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK }, 292 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 293 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 294 { .hw = &disp1_cc_pll2.clkr.hw }, 295 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 296 }; 297 298 static const struct parent_map disp_cc_parent_map_2[] = { 299 { P_BI_TCXO, 0 }, 300 }; 301 302 static const struct clk_parent_data disp_cc_parent_data_2[] = { 303 { .index = DT_BI_TCXO }, 304 }; 305 306 static const struct parent_map disp_cc_parent_map_3[] = { 307 { P_BI_TCXO, 0 }, 308 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 309 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 310 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, 311 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 312 }; 313 314 static const struct clk_parent_data disp_cc_parent_data_3[] = { 315 { .index = DT_BI_TCXO }, 316 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, 317 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 318 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, 319 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 320 }; 321 322 static const struct parent_map disp_cc_parent_map_4[] = { 323 { P_BI_TCXO, 0 }, 324 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 325 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 326 }; 327 328 static const struct clk_parent_data disp_cc_parent_data_4[] = { 329 { .index = DT_BI_TCXO }, 330 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 331 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 332 }; 333 334 static const struct parent_map disp_cc_parent_map_5[] = { 335 { P_BI_TCXO, 0 }, 336 { P_DISPn_CC_PLL0_OUT_MAIN, 1 }, 337 { P_DISPn_CC_PLL1_OUT_MAIN, 4 }, 338 { P_DISPn_CC_PLL2_OUT_MAIN, 5 }, 339 { P_DISPn_CC_PLL1_OUT_EVEN, 6 }, 340 }; 341 342 static const struct clk_parent_data disp0_cc_parent_data_5[] = { 343 { .index = DT_BI_TCXO }, 344 { .hw = &disp0_cc_pll0.clkr.hw }, 345 { .hw = &disp0_cc_pll1.clkr.hw }, 346 { .hw = &disp0_cc_pll2.clkr.hw }, 347 { .hw = &disp0_cc_pll1_out_even.clkr.hw }, 348 }; 349 350 static const struct clk_parent_data disp1_cc_parent_data_5[] = { 351 { .index = DT_BI_TCXO }, 352 { .hw = &disp1_cc_pll0.clkr.hw }, 353 { .hw = &disp1_cc_pll1.clkr.hw }, 354 { .hw = &disp1_cc_pll2.clkr.hw }, 355 { .hw = &disp1_cc_pll1_out_even.clkr.hw }, 356 }; 357 358 static const struct parent_map disp_cc_parent_map_6[] = { 359 { P_BI_TCXO, 0 }, 360 { P_DISPn_CC_PLL1_OUT_MAIN, 4 }, 361 { P_DISPn_CC_PLL1_OUT_EVEN, 6 }, 362 }; 363 364 static const struct clk_parent_data disp0_cc_parent_data_6[] = { 365 { .index = DT_BI_TCXO }, 366 { .hw = &disp0_cc_pll1.clkr.hw }, 367 { .hw = &disp0_cc_pll1_out_even.clkr.hw }, 368 }; 369 370 static const struct clk_parent_data disp1_cc_parent_data_6[] = { 371 { .index = DT_BI_TCXO }, 372 { .hw = &disp1_cc_pll1.clkr.hw }, 373 { .hw = &disp1_cc_pll1_out_even.clkr.hw }, 374 }; 375 376 static const struct parent_map disp_cc_parent_map_7[] = { 377 { P_SLEEP_CLK, 0 }, 378 }; 379 380 static const struct clk_parent_data disp_cc_parent_data_7[] = { 381 { .index = DT_SLEEP_CLK }, 382 }; 383 384 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { 385 F(19200000, P_BI_TCXO, 1, 0, 0), 386 F(37500000, P_DISPn_CC_PLL1_OUT_EVEN, 8, 0, 0), 387 F(75000000, P_DISPn_CC_PLL1_OUT_MAIN, 8, 0, 0), 388 { } 389 }; 390 391 static struct clk_rcg2 disp0_cc_mdss_ahb_clk_src = { 392 .cmd_rcgr = 0x2364, 393 .mnd_width = 0, 394 .hid_width = 5, 395 .parent_map = disp_cc_parent_map_6, 396 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 397 .clkr.hw.init = &(const struct clk_init_data) { 398 .name = "disp0_cc_mdss_ahb_clk_src", 399 .parent_data = disp0_cc_parent_data_6, 400 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_6), 401 .ops = &clk_rcg2_shared_ops, 402 }, 403 }; 404 405 static struct clk_rcg2 disp1_cc_mdss_ahb_clk_src = { 406 .cmd_rcgr = 0x2364, 407 .mnd_width = 0, 408 .hid_width = 5, 409 .parent_map = disp_cc_parent_map_6, 410 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 411 .clkr.hw.init = &(const struct clk_init_data) { 412 .name = "disp1_cc_mdss_ahb_clk_src", 413 .parent_data = disp1_cc_parent_data_6, 414 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_6), 415 .ops = &clk_rcg2_shared_ops, 416 }, 417 }; 418 419 static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = { 420 F(19200000, P_BI_TCXO, 1, 0, 0), 421 { } 422 }; 423 424 static struct clk_rcg2 disp0_cc_mdss_byte0_clk_src = { 425 .cmd_rcgr = 0x213c, 426 .mnd_width = 0, 427 .hid_width = 5, 428 .parent_map = disp_cc_parent_map_3, 429 .clkr.hw.init = &(const struct clk_init_data) { 430 .name = "disp0_cc_mdss_byte0_clk_src", 431 .parent_data = disp_cc_parent_data_3, 432 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 433 .flags = CLK_SET_RATE_PARENT, 434 .ops = &clk_byte2_ops, 435 }, 436 }; 437 438 static struct clk_rcg2 disp1_cc_mdss_byte0_clk_src = { 439 .cmd_rcgr = 0x213c, 440 .mnd_width = 0, 441 .hid_width = 5, 442 .parent_map = disp_cc_parent_map_3, 443 .clkr.hw.init = &(const struct clk_init_data) { 444 .name = "disp1_cc_mdss_byte0_clk_src", 445 .parent_data = disp_cc_parent_data_3, 446 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 447 .flags = CLK_SET_RATE_PARENT, 448 .ops = &clk_byte2_ops, 449 }, 450 }; 451 452 static struct clk_rcg2 disp0_cc_mdss_byte1_clk_src = { 453 .cmd_rcgr = 0x2158, 454 .mnd_width = 0, 455 .hid_width = 5, 456 .parent_map = disp_cc_parent_map_3, 457 .clkr.hw.init = &(const struct clk_init_data) { 458 .name = "disp0_cc_mdss_byte1_clk_src", 459 .parent_data = disp_cc_parent_data_3, 460 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 461 .flags = CLK_SET_RATE_PARENT, 462 .ops = &clk_byte2_ops, 463 }, 464 }; 465 466 static struct clk_rcg2 disp1_cc_mdss_byte1_clk_src = { 467 .cmd_rcgr = 0x2158, 468 .mnd_width = 0, 469 .hid_width = 5, 470 .parent_map = disp_cc_parent_map_3, 471 .clkr.hw.init = &(const struct clk_init_data) { 472 .name = "disp1_cc_mdss_byte1_clk_src", 473 .parent_data = disp_cc_parent_data_3, 474 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 475 .flags = CLK_SET_RATE_PARENT, 476 .ops = &clk_byte2_ops, 477 }, 478 }; 479 480 static struct clk_rcg2 disp0_cc_mdss_dptx0_aux_clk_src = { 481 .cmd_rcgr = 0x2238, 482 .mnd_width = 0, 483 .hid_width = 5, 484 .parent_map = disp_cc_parent_map_2, 485 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 486 .clkr.hw.init = &(const struct clk_init_data) { 487 .name = "disp0_cc_mdss_dptx0_aux_clk_src", 488 .parent_data = disp_cc_parent_data_2, 489 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 490 .ops = &clk_rcg2_ops, 491 }, 492 }; 493 494 static struct clk_rcg2 disp1_cc_mdss_dptx0_aux_clk_src = { 495 .cmd_rcgr = 0x2238, 496 .mnd_width = 0, 497 .hid_width = 5, 498 .parent_map = disp_cc_parent_map_2, 499 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 500 .clkr.hw.init = &(const struct clk_init_data) { 501 .name = "disp1_cc_mdss_dptx0_aux_clk_src", 502 .parent_data = disp_cc_parent_data_2, 503 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 504 .ops = &clk_rcg2_ops, 505 }, 506 }; 507 508 static struct clk_rcg2 disp0_cc_mdss_dptx0_link_clk_src = { 509 .cmd_rcgr = 0x21a4, 510 .mnd_width = 0, 511 .hid_width = 5, 512 .parent_map = disp_cc_parent_map_0, 513 .clkr.hw.init = &(const struct clk_init_data) { 514 .name = "disp0_cc_mdss_dptx0_link_clk_src", 515 .parent_data = disp0_cc_parent_data_0, 516 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_0), 517 .flags = CLK_SET_RATE_PARENT, 518 .ops = &clk_byte2_ops, 519 }, 520 }; 521 522 static struct clk_rcg2 disp1_cc_mdss_dptx0_link_clk_src = { 523 .cmd_rcgr = 0x21a4, 524 .mnd_width = 0, 525 .hid_width = 5, 526 .parent_map = disp_cc_parent_map_0, 527 .clkr.hw.init = &(const struct clk_init_data) { 528 .name = "disp1_cc_mdss_dptx0_link_clk_src", 529 .parent_data = disp1_cc_parent_data_0, 530 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_0), 531 .flags = CLK_SET_RATE_PARENT, 532 .ops = &clk_byte2_ops, 533 }, 534 }; 535 536 static struct clk_rcg2 disp0_cc_mdss_dptx0_pixel0_clk_src = { 537 .cmd_rcgr = 0x21d8, 538 .mnd_width = 16, 539 .hid_width = 5, 540 .parent_map = disp_cc_parent_map_1, 541 .clkr.hw.init = &(const struct clk_init_data) { 542 .name = "disp0_cc_mdss_dptx0_pixel0_clk_src", 543 .parent_data = disp0_cc_parent_data_1, 544 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_1), 545 .flags = CLK_SET_RATE_PARENT, 546 .ops = &clk_dp_ops, 547 }, 548 }; 549 550 static struct clk_rcg2 disp1_cc_mdss_dptx0_pixel0_clk_src = { 551 .cmd_rcgr = 0x21d8, 552 .mnd_width = 16, 553 .hid_width = 5, 554 .parent_map = disp_cc_parent_map_1, 555 .clkr.hw.init = &(const struct clk_init_data) { 556 .name = "disp1_cc_mdss_dptx0_pixel0_clk_src", 557 .parent_data = disp1_cc_parent_data_1, 558 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_1), 559 .flags = CLK_SET_RATE_PARENT, 560 .ops = &clk_dp_ops, 561 }, 562 }; 563 564 static struct clk_rcg2 disp0_cc_mdss_dptx0_pixel1_clk_src = { 565 .cmd_rcgr = 0x21f0, 566 .mnd_width = 16, 567 .hid_width = 5, 568 .parent_map = disp_cc_parent_map_1, 569 .clkr.hw.init = &(const struct clk_init_data) { 570 .name = "disp0_cc_mdss_dptx0_pixel1_clk_src", 571 .parent_data = disp0_cc_parent_data_1, 572 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_1), 573 .flags = CLK_SET_RATE_PARENT, 574 .ops = &clk_dp_ops, 575 }, 576 }; 577 578 static struct clk_rcg2 disp1_cc_mdss_dptx0_pixel1_clk_src = { 579 .cmd_rcgr = 0x21f0, 580 .mnd_width = 16, 581 .hid_width = 5, 582 .parent_map = disp_cc_parent_map_1, 583 .clkr.hw.init = &(const struct clk_init_data) { 584 .name = "disp1_cc_mdss_dptx0_pixel1_clk_src", 585 .parent_data = disp1_cc_parent_data_1, 586 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_1), 587 .flags = CLK_SET_RATE_PARENT, 588 .ops = &clk_dp_ops, 589 }, 590 }; 591 592 static struct clk_rcg2 disp0_cc_mdss_dptx1_aux_clk_src = { 593 .cmd_rcgr = 0x22d0, 594 .mnd_width = 0, 595 .hid_width = 5, 596 .parent_map = disp_cc_parent_map_2, 597 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 598 .clkr.hw.init = &(const struct clk_init_data) { 599 .name = "disp0_cc_mdss_dptx1_aux_clk_src", 600 .parent_data = disp_cc_parent_data_2, 601 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 602 .ops = &clk_rcg2_ops, 603 }, 604 }; 605 606 static struct clk_rcg2 disp1_cc_mdss_dptx1_aux_clk_src = { 607 .cmd_rcgr = 0x22d0, 608 .mnd_width = 0, 609 .hid_width = 5, 610 .parent_map = disp_cc_parent_map_2, 611 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 612 .clkr.hw.init = &(const struct clk_init_data) { 613 .name = "disp1_cc_mdss_dptx1_aux_clk_src", 614 .parent_data = disp_cc_parent_data_2, 615 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 616 .ops = &clk_rcg2_ops, 617 }, 618 }; 619 620 static struct clk_rcg2 disp0_cc_mdss_dptx1_link_clk_src = { 621 .cmd_rcgr = 0x2268, 622 .mnd_width = 0, 623 .hid_width = 5, 624 .parent_map = disp_cc_parent_map_0, 625 .clkr.hw.init = &(const struct clk_init_data) { 626 .name = "disp0_cc_mdss_dptx1_link_clk_src", 627 .parent_data = disp0_cc_parent_data_0, 628 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_0), 629 .flags = CLK_SET_RATE_PARENT, 630 .ops = &clk_byte2_ops, 631 }, 632 }; 633 634 static struct clk_rcg2 disp1_cc_mdss_dptx1_link_clk_src = { 635 .cmd_rcgr = 0x2268, 636 .mnd_width = 0, 637 .hid_width = 5, 638 .parent_map = disp_cc_parent_map_0, 639 .clkr.hw.init = &(const struct clk_init_data) { 640 .name = "disp1_cc_mdss_dptx1_link_clk_src", 641 .parent_data = disp1_cc_parent_data_0, 642 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_0), 643 .flags = CLK_SET_RATE_PARENT, 644 .ops = &clk_byte2_ops, 645 }, 646 }; 647 648 static struct clk_rcg2 disp0_cc_mdss_dptx1_pixel0_clk_src = { 649 .cmd_rcgr = 0x2250, 650 .mnd_width = 16, 651 .hid_width = 5, 652 .parent_map = disp_cc_parent_map_1, 653 .clkr.hw.init = &(const struct clk_init_data) { 654 .name = "disp0_cc_mdss_dptx1_pixel0_clk_src", 655 .parent_data = disp0_cc_parent_data_1, 656 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_1), 657 .flags = CLK_SET_RATE_PARENT, 658 .ops = &clk_dp_ops, 659 }, 660 }; 661 662 static struct clk_rcg2 disp1_cc_mdss_dptx1_pixel0_clk_src = { 663 .cmd_rcgr = 0x2250, 664 .mnd_width = 16, 665 .hid_width = 5, 666 .parent_map = disp_cc_parent_map_1, 667 .clkr.hw.init = &(const struct clk_init_data) { 668 .name = "disp1_cc_mdss_dptx1_pixel0_clk_src", 669 .parent_data = disp1_cc_parent_data_1, 670 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_1), 671 .flags = CLK_SET_RATE_PARENT, 672 .ops = &clk_dp_ops, 673 }, 674 }; 675 676 static struct clk_rcg2 disp0_cc_mdss_dptx1_pixel1_clk_src = { 677 .cmd_rcgr = 0x2370, 678 .mnd_width = 16, 679 .hid_width = 5, 680 .parent_map = disp_cc_parent_map_1, 681 .clkr.hw.init = &(const struct clk_init_data) { 682 .name = "disp0_cc_mdss_dptx1_pixel1_clk_src", 683 .parent_data = disp0_cc_parent_data_1, 684 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_1), 685 .flags = CLK_SET_RATE_PARENT, 686 .ops = &clk_dp_ops, 687 }, 688 }; 689 690 static struct clk_rcg2 disp1_cc_mdss_dptx1_pixel1_clk_src = { 691 .cmd_rcgr = 0x2370, 692 .mnd_width = 16, 693 .hid_width = 5, 694 .parent_map = disp_cc_parent_map_1, 695 .clkr.hw.init = &(const struct clk_init_data) { 696 .name = "disp1_cc_mdss_dptx1_pixel1_clk_src", 697 .parent_data = disp1_cc_parent_data_1, 698 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_1), 699 .flags = CLK_SET_RATE_PARENT, 700 .ops = &clk_dp_ops, 701 }, 702 }; 703 704 static struct clk_rcg2 disp0_cc_mdss_dptx2_aux_clk_src = { 705 .cmd_rcgr = 0x22e8, 706 .mnd_width = 0, 707 .hid_width = 5, 708 .parent_map = disp_cc_parent_map_2, 709 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 710 .clkr.hw.init = &(const struct clk_init_data) { 711 .name = "disp0_cc_mdss_dptx2_aux_clk_src", 712 .parent_data = disp_cc_parent_data_2, 713 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 714 .ops = &clk_rcg2_ops, 715 }, 716 }; 717 718 static struct clk_rcg2 disp1_cc_mdss_dptx2_aux_clk_src = { 719 .cmd_rcgr = 0x22e8, 720 .mnd_width = 0, 721 .hid_width = 5, 722 .parent_map = disp_cc_parent_map_2, 723 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 724 .clkr.hw.init = &(const struct clk_init_data) { 725 .name = "disp1_cc_mdss_dptx2_aux_clk_src", 726 .parent_data = disp_cc_parent_data_2, 727 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 728 .ops = &clk_rcg2_ops, 729 }, 730 }; 731 732 static struct clk_rcg2 disp0_cc_mdss_dptx2_link_clk_src = { 733 .cmd_rcgr = 0x2284, 734 .mnd_width = 0, 735 .hid_width = 5, 736 .parent_map = disp_cc_parent_map_0, 737 .clkr.hw.init = &(const struct clk_init_data) { 738 .name = "disp0_cc_mdss_dptx2_link_clk_src", 739 .parent_data = disp0_cc_parent_data_0, 740 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_0), 741 .flags = CLK_SET_RATE_PARENT, 742 .ops = &clk_byte2_ops, 743 }, 744 }; 745 746 static struct clk_rcg2 disp1_cc_mdss_dptx2_link_clk_src = { 747 .cmd_rcgr = 0x2284, 748 .mnd_width = 0, 749 .hid_width = 5, 750 .parent_map = disp_cc_parent_map_0, 751 .clkr.hw.init = &(const struct clk_init_data) { 752 .name = "disp1_cc_mdss_dptx2_link_clk_src", 753 .parent_data = disp1_cc_parent_data_0, 754 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_0), 755 .flags = CLK_SET_RATE_PARENT, 756 .ops = &clk_byte2_ops, 757 }, 758 }; 759 760 static struct clk_rcg2 disp0_cc_mdss_dptx2_pixel0_clk_src = { 761 .cmd_rcgr = 0x2208, 762 .mnd_width = 16, 763 .hid_width = 5, 764 .parent_map = disp_cc_parent_map_1, 765 .clkr.hw.init = &(const struct clk_init_data) { 766 .name = "disp0_cc_mdss_dptx2_pixel0_clk_src", 767 .parent_data = disp0_cc_parent_data_1, 768 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_1), 769 .flags = CLK_SET_RATE_PARENT, 770 .ops = &clk_dp_ops, 771 }, 772 }; 773 774 static struct clk_rcg2 disp1_cc_mdss_dptx2_pixel0_clk_src = { 775 .cmd_rcgr = 0x2208, 776 .mnd_width = 16, 777 .hid_width = 5, 778 .parent_map = disp_cc_parent_map_1, 779 .clkr.hw.init = &(const struct clk_init_data) { 780 .name = "disp1_cc_mdss_dptx2_pixel0_clk_src", 781 .parent_data = disp1_cc_parent_data_1, 782 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_1), 783 .flags = CLK_SET_RATE_PARENT, 784 .ops = &clk_dp_ops, 785 }, 786 }; 787 788 static struct clk_rcg2 disp0_cc_mdss_dptx2_pixel1_clk_src = { 789 .cmd_rcgr = 0x2220, 790 .mnd_width = 16, 791 .hid_width = 5, 792 .parent_map = disp_cc_parent_map_1, 793 .clkr.hw.init = &(const struct clk_init_data) { 794 .name = "disp0_cc_mdss_dptx2_pixel1_clk_src", 795 .parent_data = disp0_cc_parent_data_1, 796 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_1), 797 .flags = CLK_SET_RATE_PARENT, 798 .ops = &clk_dp_ops, 799 }, 800 }; 801 802 static struct clk_rcg2 disp1_cc_mdss_dptx2_pixel1_clk_src = { 803 .cmd_rcgr = 0x2220, 804 .mnd_width = 16, 805 .hid_width = 5, 806 .parent_map = disp_cc_parent_map_1, 807 .clkr.hw.init = &(const struct clk_init_data) { 808 .name = "disp1_cc_mdss_dptx2_pixel1_clk_src", 809 .parent_data = disp1_cc_parent_data_1, 810 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_1), 811 .flags = CLK_SET_RATE_PARENT, 812 .ops = &clk_dp_ops, 813 }, 814 }; 815 816 static struct clk_rcg2 disp0_cc_mdss_dptx3_aux_clk_src = { 817 .cmd_rcgr = 0x234c, 818 .mnd_width = 0, 819 .hid_width = 5, 820 .parent_map = disp_cc_parent_map_2, 821 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 822 .clkr.hw.init = &(const struct clk_init_data) { 823 .name = "disp0_cc_mdss_dptx3_aux_clk_src", 824 .parent_data = disp_cc_parent_data_2, 825 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 826 .ops = &clk_rcg2_ops, 827 }, 828 }; 829 830 static struct clk_rcg2 disp1_cc_mdss_dptx3_aux_clk_src = { 831 .cmd_rcgr = 0x234c, 832 .mnd_width = 0, 833 .hid_width = 5, 834 .parent_map = disp_cc_parent_map_2, 835 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 836 .clkr.hw.init = &(const struct clk_init_data) { 837 .name = "disp1_cc_mdss_dptx3_aux_clk_src", 838 .parent_data = disp_cc_parent_data_2, 839 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 840 .ops = &clk_rcg2_ops, 841 }, 842 }; 843 844 static struct clk_rcg2 disp0_cc_mdss_dptx3_link_clk_src = { 845 .cmd_rcgr = 0x2318, 846 .mnd_width = 0, 847 .hid_width = 5, 848 .parent_map = disp_cc_parent_map_0, 849 .clkr.hw.init = &(const struct clk_init_data) { 850 .name = "disp0_cc_mdss_dptx3_link_clk_src", 851 .parent_data = disp0_cc_parent_data_0, 852 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_0), 853 .flags = CLK_SET_RATE_PARENT, 854 .ops = &clk_byte2_ops, 855 }, 856 }; 857 858 static struct clk_rcg2 disp1_cc_mdss_dptx3_link_clk_src = { 859 .cmd_rcgr = 0x2318, 860 .mnd_width = 0, 861 .hid_width = 5, 862 .parent_map = disp_cc_parent_map_0, 863 .clkr.hw.init = &(const struct clk_init_data) { 864 .name = "disp1_cc_mdss_dptx3_link_clk_src", 865 .parent_data = disp1_cc_parent_data_0, 866 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_0), 867 .flags = CLK_SET_RATE_PARENT, 868 .ops = &clk_byte2_ops, 869 }, 870 }; 871 872 static struct clk_rcg2 disp0_cc_mdss_dptx3_pixel0_clk_src = { 873 .cmd_rcgr = 0x2300, 874 .mnd_width = 16, 875 .hid_width = 5, 876 .parent_map = disp_cc_parent_map_1, 877 .clkr.hw.init = &(const struct clk_init_data) { 878 .name = "disp0_cc_mdss_dptx3_pixel0_clk_src", 879 .parent_data = disp0_cc_parent_data_1, 880 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_1), 881 .flags = CLK_SET_RATE_PARENT, 882 .ops = &clk_dp_ops, 883 }, 884 }; 885 886 static struct clk_rcg2 disp1_cc_mdss_dptx3_pixel0_clk_src = { 887 .cmd_rcgr = 0x2300, 888 .mnd_width = 16, 889 .hid_width = 5, 890 .parent_map = disp_cc_parent_map_1, 891 .clkr.hw.init = &(const struct clk_init_data) { 892 .name = "disp1_cc_mdss_dptx3_pixel0_clk_src", 893 .parent_data = disp1_cc_parent_data_1, 894 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_1), 895 .flags = CLK_SET_RATE_PARENT, 896 .ops = &clk_dp_ops, 897 }, 898 }; 899 900 static struct clk_rcg2 disp0_cc_mdss_esc0_clk_src = { 901 .cmd_rcgr = 0x2174, 902 .mnd_width = 0, 903 .hid_width = 5, 904 .parent_map = disp_cc_parent_map_4, 905 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 906 .clkr.hw.init = &(const struct clk_init_data) { 907 .name = "disp0_cc_mdss_esc0_clk_src", 908 .parent_data = disp_cc_parent_data_4, 909 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 910 .ops = &clk_rcg2_ops, 911 }, 912 }; 913 914 static struct clk_rcg2 disp1_cc_mdss_esc0_clk_src = { 915 .cmd_rcgr = 0x2174, 916 .mnd_width = 0, 917 .hid_width = 5, 918 .parent_map = disp_cc_parent_map_4, 919 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 920 .clkr.hw.init = &(const struct clk_init_data) { 921 .name = "disp1_cc_mdss_esc0_clk_src", 922 .parent_data = disp_cc_parent_data_4, 923 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 924 .ops = &clk_rcg2_ops, 925 }, 926 }; 927 928 static struct clk_rcg2 disp0_cc_mdss_esc1_clk_src = { 929 .cmd_rcgr = 0x218c, 930 .mnd_width = 0, 931 .hid_width = 5, 932 .parent_map = disp_cc_parent_map_4, 933 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 934 .clkr.hw.init = &(const struct clk_init_data) { 935 .name = "disp0_cc_mdss_esc1_clk_src", 936 .parent_data = disp_cc_parent_data_4, 937 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 938 .ops = &clk_rcg2_ops, 939 }, 940 }; 941 942 static struct clk_rcg2 disp1_cc_mdss_esc1_clk_src = { 943 .cmd_rcgr = 0x218c, 944 .mnd_width = 0, 945 .hid_width = 5, 946 .parent_map = disp_cc_parent_map_4, 947 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 948 .clkr.hw.init = &(const struct clk_init_data) { 949 .name = "disp1_cc_mdss_esc1_clk_src", 950 .parent_data = disp_cc_parent_data_4, 951 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 952 .ops = &clk_rcg2_ops, 953 }, 954 }; 955 956 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { 957 F(19200000, P_BI_TCXO, 1, 0, 0), 958 F(85714286, P_DISPn_CC_PLL1_OUT_MAIN, 7, 0, 0), 959 F(100000000, P_DISPn_CC_PLL1_OUT_MAIN, 6, 0, 0), 960 F(150000000, P_DISPn_CC_PLL1_OUT_MAIN, 4, 0, 0), 961 F(200000000, P_DISPn_CC_PLL1_OUT_MAIN, 3, 0, 0), 962 F(300000000, P_DISPn_CC_PLL1_OUT_MAIN, 2, 0, 0), 963 F(375000000, P_DISPn_CC_PLL0_OUT_MAIN, 4, 0, 0), 964 F(500000000, P_DISPn_CC_PLL0_OUT_MAIN, 3, 0, 0), 965 F(600000000, P_DISPn_CC_PLL1_OUT_MAIN, 1, 0, 0), 966 { } 967 }; 968 969 static struct clk_rcg2 disp0_cc_mdss_mdp_clk_src = { 970 .cmd_rcgr = 0x20f4, 971 .mnd_width = 0, 972 .hid_width = 5, 973 .parent_map = disp_cc_parent_map_5, 974 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 975 .clkr.hw.init = &(const struct clk_init_data) { 976 .name = "disp0_cc_mdss_mdp_clk_src", 977 .parent_data = disp0_cc_parent_data_5, 978 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_5), 979 .ops = &clk_rcg2_shared_no_init_park_ops, 980 }, 981 }; 982 983 static struct clk_rcg2 disp1_cc_mdss_mdp_clk_src = { 984 .cmd_rcgr = 0x20f4, 985 .mnd_width = 0, 986 .hid_width = 5, 987 .parent_map = disp_cc_parent_map_5, 988 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 989 .clkr.hw.init = &(const struct clk_init_data) { 990 .name = "disp1_cc_mdss_mdp_clk_src", 991 .parent_data = disp1_cc_parent_data_5, 992 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_5), 993 .ops = &clk_rcg2_shared_no_init_park_ops, 994 }, 995 }; 996 997 static struct clk_rcg2 disp0_cc_mdss_pclk0_clk_src = { 998 .cmd_rcgr = 0x20c4, 999 .mnd_width = 8, 1000 .hid_width = 5, 1001 .parent_map = disp_cc_parent_map_3, 1002 .clkr.hw.init = &(const struct clk_init_data) { 1003 .name = "disp0_cc_mdss_pclk0_clk_src", 1004 .parent_data = disp_cc_parent_data_3, 1005 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 1006 .flags = CLK_SET_RATE_PARENT, 1007 .ops = &clk_pixel_ops, 1008 }, 1009 }; 1010 1011 static struct clk_rcg2 disp1_cc_mdss_pclk0_clk_src = { 1012 .cmd_rcgr = 0x20c4, 1013 .mnd_width = 8, 1014 .hid_width = 5, 1015 .parent_map = disp_cc_parent_map_3, 1016 .clkr.hw.init = &(const struct clk_init_data) { 1017 .name = "disp1_cc_mdss_pclk0_clk_src", 1018 .parent_data = disp_cc_parent_data_3, 1019 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 1020 .flags = CLK_SET_RATE_PARENT, 1021 .ops = &clk_pixel_ops, 1022 }, 1023 }; 1024 1025 static struct clk_rcg2 disp0_cc_mdss_pclk1_clk_src = { 1026 .cmd_rcgr = 0x20dc, 1027 .mnd_width = 8, 1028 .hid_width = 5, 1029 .parent_map = disp_cc_parent_map_3, 1030 .clkr.hw.init = &(const struct clk_init_data) { 1031 .name = "disp0_cc_mdss_pclk1_clk_src", 1032 .parent_data = disp_cc_parent_data_3, 1033 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 1034 .flags = CLK_SET_RATE_PARENT, 1035 .ops = &clk_pixel_ops, 1036 }, 1037 }; 1038 1039 static struct clk_rcg2 disp1_cc_mdss_pclk1_clk_src = { 1040 .cmd_rcgr = 0x20dc, 1041 .mnd_width = 8, 1042 .hid_width = 5, 1043 .parent_map = disp_cc_parent_map_3, 1044 .clkr.hw.init = &(const struct clk_init_data) { 1045 .name = "disp1_cc_mdss_pclk1_clk_src", 1046 .parent_data = disp_cc_parent_data_3, 1047 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 1048 .flags = CLK_SET_RATE_PARENT, 1049 .ops = &clk_pixel_ops, 1050 }, 1051 }; 1052 1053 static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = { 1054 F(19200000, P_BI_TCXO, 1, 0, 0), 1055 F(200000000, P_DISPn_CC_PLL1_OUT_MAIN, 3, 0, 0), 1056 F(300000000, P_DISPn_CC_PLL1_OUT_MAIN, 2, 0, 0), 1057 F(375000000, P_DISPn_CC_PLL0_OUT_MAIN, 4, 0, 0), 1058 F(500000000, P_DISPn_CC_PLL0_OUT_MAIN, 3, 0, 0), 1059 F(600000000, P_DISPn_CC_PLL1_OUT_MAIN, 1, 0, 0), 1060 { } 1061 }; 1062 1063 static struct clk_rcg2 disp0_cc_mdss_rot_clk_src = { 1064 .cmd_rcgr = 0x210c, 1065 .mnd_width = 0, 1066 .hid_width = 5, 1067 .parent_map = disp_cc_parent_map_5, 1068 .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, 1069 .clkr.hw.init = &(const struct clk_init_data) { 1070 .name = "disp0_cc_mdss_rot_clk_src", 1071 .parent_data = disp0_cc_parent_data_5, 1072 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_5), 1073 .ops = &clk_rcg2_shared_ops, 1074 }, 1075 }; 1076 1077 static struct clk_rcg2 disp1_cc_mdss_rot_clk_src = { 1078 .cmd_rcgr = 0x210c, 1079 .mnd_width = 0, 1080 .hid_width = 5, 1081 .parent_map = disp_cc_parent_map_5, 1082 .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, 1083 .clkr.hw.init = &(const struct clk_init_data) { 1084 .name = "disp1_cc_mdss_rot_clk_src", 1085 .parent_data = disp1_cc_parent_data_5, 1086 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_5), 1087 .ops = &clk_rcg2_shared_ops, 1088 }, 1089 }; 1090 1091 static struct clk_rcg2 disp0_cc_mdss_vsync_clk_src = { 1092 .cmd_rcgr = 0x2124, 1093 .mnd_width = 0, 1094 .hid_width = 5, 1095 .parent_map = disp_cc_parent_map_2, 1096 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 1097 .clkr.hw.init = &(const struct clk_init_data) { 1098 .name = "disp0_cc_mdss_vsync_clk_src", 1099 .parent_data = disp_cc_parent_data_2, 1100 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 1101 .ops = &clk_rcg2_ops, 1102 }, 1103 }; 1104 1105 static struct clk_rcg2 disp1_cc_mdss_vsync_clk_src = { 1106 .cmd_rcgr = 0x2124, 1107 .mnd_width = 0, 1108 .hid_width = 5, 1109 .parent_map = disp_cc_parent_map_2, 1110 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 1111 .clkr.hw.init = &(const struct clk_init_data) { 1112 .name = "disp1_cc_mdss_vsync_clk_src", 1113 .parent_data = disp_cc_parent_data_2, 1114 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 1115 .ops = &clk_rcg2_ops, 1116 }, 1117 }; 1118 1119 static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = { 1120 F(32000, P_SLEEP_CLK, 1, 0, 0), 1121 { } 1122 }; 1123 1124 static struct clk_rcg2 disp0_cc_sleep_clk_src = { 1125 .cmd_rcgr = 0x6060, 1126 .mnd_width = 0, 1127 .hid_width = 5, 1128 .parent_map = disp_cc_parent_map_7, 1129 .freq_tbl = ftbl_disp_cc_sleep_clk_src, 1130 .clkr.hw.init = &(const struct clk_init_data) { 1131 .name = "disp0_cc_sleep_clk_src", 1132 .parent_data = disp_cc_parent_data_7, 1133 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), 1134 .ops = &clk_rcg2_ops, 1135 }, 1136 }; 1137 1138 static struct clk_rcg2 disp1_cc_sleep_clk_src = { 1139 .cmd_rcgr = 0x6060, 1140 .mnd_width = 0, 1141 .hid_width = 5, 1142 .parent_map = disp_cc_parent_map_7, 1143 .freq_tbl = ftbl_disp_cc_sleep_clk_src, 1144 .clkr.hw.init = &(const struct clk_init_data) { 1145 .name = "disp1_cc_sleep_clk_src", 1146 .parent_data = disp_cc_parent_data_7, 1147 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), 1148 .ops = &clk_rcg2_ops, 1149 }, 1150 }; 1151 1152 static struct clk_regmap_div disp0_cc_mdss_byte0_div_clk_src = { 1153 .reg = 0x2154, 1154 .shift = 0, 1155 .width = 4, 1156 .clkr.hw.init = &(const struct clk_init_data) { 1157 .name = "disp0_cc_mdss_byte0_div_clk_src", 1158 .parent_hws = (const struct clk_hw*[]){ 1159 &disp0_cc_mdss_byte0_clk_src.clkr.hw, 1160 }, 1161 .num_parents = 1, 1162 .ops = &clk_regmap_div_ops, 1163 }, 1164 }; 1165 1166 static struct clk_regmap_div disp1_cc_mdss_byte0_div_clk_src = { 1167 .reg = 0x2154, 1168 .shift = 0, 1169 .width = 4, 1170 .clkr.hw.init = &(const struct clk_init_data) { 1171 .name = "disp1_cc_mdss_byte0_div_clk_src", 1172 .parent_hws = (const struct clk_hw*[]){ 1173 &disp1_cc_mdss_byte0_clk_src.clkr.hw, 1174 }, 1175 .num_parents = 1, 1176 .ops = &clk_regmap_div_ops, 1177 }, 1178 }; 1179 1180 static struct clk_regmap_div disp0_cc_mdss_byte1_div_clk_src = { 1181 .reg = 0x2170, 1182 .shift = 0, 1183 .width = 4, 1184 .clkr.hw.init = &(const struct clk_init_data) { 1185 .name = "disp0_cc_mdss_byte1_div_clk_src", 1186 .parent_hws = (const struct clk_hw*[]){ 1187 &disp0_cc_mdss_byte1_clk_src.clkr.hw, 1188 }, 1189 .num_parents = 1, 1190 .ops = &clk_regmap_div_ops, 1191 }, 1192 }; 1193 1194 static struct clk_regmap_div disp1_cc_mdss_byte1_div_clk_src = { 1195 .reg = 0x2170, 1196 .shift = 0, 1197 .width = 4, 1198 .clkr.hw.init = &(const struct clk_init_data) { 1199 .name = "disp1_cc_mdss_byte1_div_clk_src", 1200 .parent_hws = (const struct clk_hw*[]){ 1201 &disp1_cc_mdss_byte1_clk_src.clkr.hw, 1202 }, 1203 .num_parents = 1, 1204 .ops = &clk_regmap_div_ops, 1205 }, 1206 }; 1207 1208 static struct clk_regmap_div disp0_cc_mdss_dptx0_link_div_clk_src = { 1209 .reg = 0x21bc, 1210 .shift = 0, 1211 .width = 4, 1212 .clkr.hw.init = &(const struct clk_init_data) { 1213 .name = "disp0_cc_mdss_dptx0_link_div_clk_src", 1214 .parent_hws = (const struct clk_hw*[]){ 1215 &disp0_cc_mdss_dptx0_link_clk_src.clkr.hw, 1216 }, 1217 .num_parents = 1, 1218 .flags = CLK_SET_RATE_PARENT, 1219 .ops = &clk_regmap_div_ro_ops, 1220 }, 1221 }; 1222 1223 static struct clk_regmap_div disp1_cc_mdss_dptx0_link_div_clk_src = { 1224 .reg = 0x21bc, 1225 .shift = 0, 1226 .width = 4, 1227 .clkr.hw.init = &(const struct clk_init_data) { 1228 .name = "disp1_cc_mdss_dptx0_link_div_clk_src", 1229 .parent_hws = (const struct clk_hw*[]){ 1230 &disp1_cc_mdss_dptx0_link_clk_src.clkr.hw, 1231 }, 1232 .num_parents = 1, 1233 .flags = CLK_SET_RATE_PARENT, 1234 .ops = &clk_regmap_div_ro_ops, 1235 }, 1236 }; 1237 1238 static struct clk_regmap_div disp0_cc_mdss_dptx1_link_div_clk_src = { 1239 .reg = 0x2280, 1240 .shift = 0, 1241 .width = 4, 1242 .clkr.hw.init = &(const struct clk_init_data) { 1243 .name = "disp0_cc_mdss_dptx1_link_div_clk_src", 1244 .parent_hws = (const struct clk_hw*[]){ 1245 &disp0_cc_mdss_dptx1_link_clk_src.clkr.hw, 1246 }, 1247 .num_parents = 1, 1248 .flags = CLK_SET_RATE_PARENT, 1249 .ops = &clk_regmap_div_ro_ops, 1250 }, 1251 }; 1252 1253 static struct clk_regmap_div disp1_cc_mdss_dptx1_link_div_clk_src = { 1254 .reg = 0x2280, 1255 .shift = 0, 1256 .width = 4, 1257 .clkr.hw.init = &(const struct clk_init_data) { 1258 .name = "disp1_cc_mdss_dptx1_link_div_clk_src", 1259 .parent_hws = (const struct clk_hw*[]){ 1260 &disp1_cc_mdss_dptx1_link_clk_src.clkr.hw, 1261 }, 1262 .num_parents = 1, 1263 .flags = CLK_SET_RATE_PARENT, 1264 .ops = &clk_regmap_div_ro_ops, 1265 }, 1266 }; 1267 1268 static struct clk_regmap_div disp0_cc_mdss_dptx2_link_div_clk_src = { 1269 .reg = 0x229c, 1270 .shift = 0, 1271 .width = 4, 1272 .clkr.hw.init = &(const struct clk_init_data) { 1273 .name = "disp0_cc_mdss_dptx2_link_div_clk_src", 1274 .parent_hws = (const struct clk_hw*[]){ 1275 &disp0_cc_mdss_dptx2_link_clk_src.clkr.hw, 1276 }, 1277 .num_parents = 1, 1278 .flags = CLK_SET_RATE_PARENT, 1279 .ops = &clk_regmap_div_ro_ops, 1280 }, 1281 }; 1282 1283 static struct clk_regmap_div disp1_cc_mdss_dptx2_link_div_clk_src = { 1284 .reg = 0x229c, 1285 .shift = 0, 1286 .width = 4, 1287 .clkr.hw.init = &(const struct clk_init_data) { 1288 .name = "disp1_cc_mdss_dptx2_link_div_clk_src", 1289 .parent_hws = (const struct clk_hw*[]){ 1290 &disp1_cc_mdss_dptx2_link_clk_src.clkr.hw, 1291 }, 1292 .num_parents = 1, 1293 .flags = CLK_SET_RATE_PARENT, 1294 .ops = &clk_regmap_div_ro_ops, 1295 }, 1296 }; 1297 1298 static struct clk_regmap_div disp0_cc_mdss_dptx3_link_div_clk_src = { 1299 .reg = 0x2330, 1300 .shift = 0, 1301 .width = 4, 1302 .clkr.hw.init = &(const struct clk_init_data) { 1303 .name = "disp0_cc_mdss_dptx3_link_div_clk_src", 1304 .parent_hws = (const struct clk_hw*[]){ 1305 &disp0_cc_mdss_dptx3_link_clk_src.clkr.hw, 1306 }, 1307 .num_parents = 1, 1308 .flags = CLK_SET_RATE_PARENT, 1309 .ops = &clk_regmap_div_ro_ops, 1310 }, 1311 }; 1312 1313 static struct clk_regmap_div disp1_cc_mdss_dptx3_link_div_clk_src = { 1314 .reg = 0x2330, 1315 .shift = 0, 1316 .width = 4, 1317 .clkr.hw.init = &(const struct clk_init_data) { 1318 .name = "disp1_cc_mdss_dptx3_link_div_clk_src", 1319 .parent_hws = (const struct clk_hw*[]){ 1320 &disp1_cc_mdss_dptx3_link_clk_src.clkr.hw, 1321 }, 1322 .num_parents = 1, 1323 .flags = CLK_SET_RATE_PARENT, 1324 .ops = &clk_regmap_div_ro_ops, 1325 }, 1326 }; 1327 1328 static struct clk_branch disp0_cc_mdss_ahb1_clk = { 1329 .halt_reg = 0x20c0, 1330 .halt_check = BRANCH_HALT, 1331 .clkr = { 1332 .enable_reg = 0x20c0, 1333 .enable_mask = BIT(0), 1334 .hw.init = &(const struct clk_init_data) { 1335 .name = "disp0_cc_mdss_ahb1_clk", 1336 .parent_hws = (const struct clk_hw*[]){ 1337 &disp0_cc_mdss_ahb_clk_src.clkr.hw, 1338 }, 1339 .num_parents = 1, 1340 .flags = CLK_SET_RATE_PARENT, 1341 .ops = &clk_branch2_ops, 1342 }, 1343 }, 1344 }; 1345 1346 static struct clk_branch disp1_cc_mdss_ahb1_clk = { 1347 .halt_reg = 0x20c0, 1348 .halt_check = BRANCH_HALT, 1349 .clkr = { 1350 .enable_reg = 0x20c0, 1351 .enable_mask = BIT(0), 1352 .hw.init = &(const struct clk_init_data) { 1353 .name = "disp1_cc_mdss_ahb1_clk", 1354 .parent_hws = (const struct clk_hw*[]){ 1355 &disp1_cc_mdss_ahb_clk_src.clkr.hw, 1356 }, 1357 .num_parents = 1, 1358 .flags = CLK_SET_RATE_PARENT, 1359 .ops = &clk_branch2_ops, 1360 }, 1361 }, 1362 }; 1363 1364 static struct clk_branch disp0_cc_mdss_ahb_clk = { 1365 .halt_reg = 0x20bc, 1366 .halt_check = BRANCH_HALT, 1367 .clkr = { 1368 .enable_reg = 0x20bc, 1369 .enable_mask = BIT(0), 1370 .hw.init = &(const struct clk_init_data) { 1371 .name = "disp0_cc_mdss_ahb_clk", 1372 .parent_hws = (const struct clk_hw*[]){ 1373 &disp0_cc_mdss_ahb_clk_src.clkr.hw, 1374 }, 1375 .num_parents = 1, 1376 .flags = CLK_SET_RATE_PARENT, 1377 .ops = &clk_branch2_ops, 1378 }, 1379 }, 1380 }; 1381 1382 static struct clk_branch disp1_cc_mdss_ahb_clk = { 1383 .halt_reg = 0x20bc, 1384 .halt_check = BRANCH_HALT, 1385 .clkr = { 1386 .enable_reg = 0x20bc, 1387 .enable_mask = BIT(0), 1388 .hw.init = &(const struct clk_init_data) { 1389 .name = "disp1_cc_mdss_ahb_clk", 1390 .parent_hws = (const struct clk_hw*[]){ 1391 &disp1_cc_mdss_ahb_clk_src.clkr.hw, 1392 }, 1393 .num_parents = 1, 1394 .flags = CLK_SET_RATE_PARENT, 1395 .ops = &clk_branch2_ops, 1396 }, 1397 }, 1398 }; 1399 1400 static struct clk_branch disp0_cc_mdss_byte0_clk = { 1401 .halt_reg = 0x2044, 1402 .halt_check = BRANCH_HALT, 1403 .clkr = { 1404 .enable_reg = 0x2044, 1405 .enable_mask = BIT(0), 1406 .hw.init = &(const struct clk_init_data) { 1407 .name = "disp0_cc_mdss_byte0_clk", 1408 .parent_hws = (const struct clk_hw*[]){ 1409 &disp0_cc_mdss_byte0_clk_src.clkr.hw, 1410 }, 1411 .num_parents = 1, 1412 .flags = CLK_SET_RATE_PARENT, 1413 .ops = &clk_branch2_ops, 1414 }, 1415 }, 1416 }; 1417 1418 static struct clk_branch disp1_cc_mdss_byte0_clk = { 1419 .halt_reg = 0x2044, 1420 .halt_check = BRANCH_HALT, 1421 .clkr = { 1422 .enable_reg = 0x2044, 1423 .enable_mask = BIT(0), 1424 .hw.init = &(const struct clk_init_data) { 1425 .name = "disp1_cc_mdss_byte0_clk", 1426 .parent_hws = (const struct clk_hw*[]){ 1427 &disp1_cc_mdss_byte0_clk_src.clkr.hw, 1428 }, 1429 .num_parents = 1, 1430 .flags = CLK_SET_RATE_PARENT, 1431 .ops = &clk_branch2_ops, 1432 }, 1433 }, 1434 }; 1435 1436 static struct clk_branch disp0_cc_mdss_byte0_intf_clk = { 1437 .halt_reg = 0x2048, 1438 .halt_check = BRANCH_HALT, 1439 .clkr = { 1440 .enable_reg = 0x2048, 1441 .enable_mask = BIT(0), 1442 .hw.init = &(const struct clk_init_data) { 1443 .name = "disp0_cc_mdss_byte0_intf_clk", 1444 .parent_hws = (const struct clk_hw*[]){ 1445 &disp0_cc_mdss_byte0_div_clk_src.clkr.hw, 1446 }, 1447 .num_parents = 1, 1448 .flags = CLK_SET_RATE_PARENT, 1449 .ops = &clk_branch2_ops, 1450 }, 1451 }, 1452 }; 1453 1454 static struct clk_branch disp1_cc_mdss_byte0_intf_clk = { 1455 .halt_reg = 0x2048, 1456 .halt_check = BRANCH_HALT, 1457 .clkr = { 1458 .enable_reg = 0x2048, 1459 .enable_mask = BIT(0), 1460 .hw.init = &(const struct clk_init_data) { 1461 .name = "disp1_cc_mdss_byte0_intf_clk", 1462 .parent_hws = (const struct clk_hw*[]){ 1463 &disp1_cc_mdss_byte0_div_clk_src.clkr.hw, 1464 }, 1465 .num_parents = 1, 1466 .flags = CLK_SET_RATE_PARENT, 1467 .ops = &clk_branch2_ops, 1468 }, 1469 }, 1470 }; 1471 1472 static struct clk_branch disp0_cc_mdss_byte1_clk = { 1473 .halt_reg = 0x204c, 1474 .halt_check = BRANCH_HALT, 1475 .clkr = { 1476 .enable_reg = 0x204c, 1477 .enable_mask = BIT(0), 1478 .hw.init = &(const struct clk_init_data) { 1479 .name = "disp0_cc_mdss_byte1_clk", 1480 .parent_hws = (const struct clk_hw*[]){ 1481 &disp0_cc_mdss_byte1_clk_src.clkr.hw, 1482 }, 1483 .num_parents = 1, 1484 .flags = CLK_SET_RATE_PARENT, 1485 .ops = &clk_branch2_ops, 1486 }, 1487 }, 1488 }; 1489 1490 static struct clk_branch disp1_cc_mdss_byte1_clk = { 1491 .halt_reg = 0x204c, 1492 .halt_check = BRANCH_HALT, 1493 .clkr = { 1494 .enable_reg = 0x204c, 1495 .enable_mask = BIT(0), 1496 .hw.init = &(const struct clk_init_data) { 1497 .name = "disp1_cc_mdss_byte1_clk", 1498 .parent_hws = (const struct clk_hw*[]){ 1499 &disp1_cc_mdss_byte1_clk_src.clkr.hw, 1500 }, 1501 .num_parents = 1, 1502 .flags = CLK_SET_RATE_PARENT, 1503 .ops = &clk_branch2_ops, 1504 }, 1505 }, 1506 }; 1507 1508 static struct clk_branch disp0_cc_mdss_byte1_intf_clk = { 1509 .halt_reg = 0x2050, 1510 .halt_check = BRANCH_HALT, 1511 .clkr = { 1512 .enable_reg = 0x2050, 1513 .enable_mask = BIT(0), 1514 .hw.init = &(const struct clk_init_data) { 1515 .name = "disp0_cc_mdss_byte1_intf_clk", 1516 .parent_hws = (const struct clk_hw*[]){ 1517 &disp0_cc_mdss_byte1_div_clk_src.clkr.hw, 1518 }, 1519 .num_parents = 1, 1520 .flags = CLK_SET_RATE_PARENT, 1521 .ops = &clk_branch2_ops, 1522 }, 1523 }, 1524 }; 1525 1526 static struct clk_branch disp1_cc_mdss_byte1_intf_clk = { 1527 .halt_reg = 0x2050, 1528 .halt_check = BRANCH_HALT, 1529 .clkr = { 1530 .enable_reg = 0x2050, 1531 .enable_mask = BIT(0), 1532 .hw.init = &(const struct clk_init_data) { 1533 .name = "disp1_cc_mdss_byte1_intf_clk", 1534 .parent_hws = (const struct clk_hw*[]){ 1535 &disp1_cc_mdss_byte1_div_clk_src.clkr.hw, 1536 }, 1537 .num_parents = 1, 1538 .flags = CLK_SET_RATE_PARENT, 1539 .ops = &clk_branch2_ops, 1540 }, 1541 }, 1542 }; 1543 1544 static struct clk_branch disp0_cc_mdss_dptx0_aux_clk = { 1545 .halt_reg = 0x206c, 1546 .halt_check = BRANCH_HALT, 1547 .clkr = { 1548 .enable_reg = 0x206c, 1549 .enable_mask = BIT(0), 1550 .hw.init = &(const struct clk_init_data) { 1551 .name = "disp0_cc_mdss_dptx0_aux_clk", 1552 .parent_hws = (const struct clk_hw*[]){ 1553 &disp0_cc_mdss_dptx0_aux_clk_src.clkr.hw, 1554 }, 1555 .num_parents = 1, 1556 .flags = CLK_SET_RATE_PARENT, 1557 .ops = &clk_branch2_ops, 1558 }, 1559 }, 1560 }; 1561 1562 static struct clk_branch disp1_cc_mdss_dptx0_aux_clk = { 1563 .halt_reg = 0x206c, 1564 .halt_check = BRANCH_HALT, 1565 .clkr = { 1566 .enable_reg = 0x206c, 1567 .enable_mask = BIT(0), 1568 .hw.init = &(const struct clk_init_data) { 1569 .name = "disp1_cc_mdss_dptx0_aux_clk", 1570 .parent_hws = (const struct clk_hw*[]){ 1571 &disp1_cc_mdss_dptx0_aux_clk_src.clkr.hw, 1572 }, 1573 .num_parents = 1, 1574 .flags = CLK_SET_RATE_PARENT, 1575 .ops = &clk_branch2_ops, 1576 }, 1577 }, 1578 }; 1579 1580 static struct clk_branch disp0_cc_mdss_dptx0_link_clk = { 1581 .halt_reg = 0x205c, 1582 .halt_check = BRANCH_HALT, 1583 .clkr = { 1584 .enable_reg = 0x205c, 1585 .enable_mask = BIT(0), 1586 .hw.init = &(const struct clk_init_data) { 1587 .name = "disp0_cc_mdss_dptx0_link_clk", 1588 .parent_hws = (const struct clk_hw*[]){ 1589 &disp0_cc_mdss_dptx0_link_clk_src.clkr.hw, 1590 }, 1591 .num_parents = 1, 1592 .flags = CLK_SET_RATE_PARENT, 1593 .ops = &clk_branch2_ops, 1594 }, 1595 }, 1596 }; 1597 1598 static struct clk_branch disp1_cc_mdss_dptx0_link_clk = { 1599 .halt_reg = 0x205c, 1600 .halt_check = BRANCH_HALT, 1601 .clkr = { 1602 .enable_reg = 0x205c, 1603 .enable_mask = BIT(0), 1604 .hw.init = &(const struct clk_init_data) { 1605 .name = "disp1_cc_mdss_dptx0_link_clk", 1606 .parent_hws = (const struct clk_hw*[]){ 1607 &disp1_cc_mdss_dptx0_link_clk_src.clkr.hw, 1608 }, 1609 .num_parents = 1, 1610 .flags = CLK_SET_RATE_PARENT, 1611 .ops = &clk_branch2_ops, 1612 }, 1613 }, 1614 }; 1615 1616 static struct clk_branch disp0_cc_mdss_dptx0_link_intf_clk = { 1617 .halt_reg = 0x2060, 1618 .halt_check = BRANCH_HALT, 1619 .clkr = { 1620 .enable_reg = 0x2060, 1621 .enable_mask = BIT(0), 1622 .hw.init = &(const struct clk_init_data) { 1623 .name = "disp0_cc_mdss_dptx0_link_intf_clk", 1624 .parent_hws = (const struct clk_hw*[]){ 1625 &disp0_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1626 }, 1627 .num_parents = 1, 1628 .flags = CLK_SET_RATE_PARENT, 1629 .ops = &clk_branch2_ops, 1630 }, 1631 }, 1632 }; 1633 1634 static struct clk_branch disp1_cc_mdss_dptx0_link_intf_clk = { 1635 .halt_reg = 0x2060, 1636 .halt_check = BRANCH_HALT, 1637 .clkr = { 1638 .enable_reg = 0x2060, 1639 .enable_mask = BIT(0), 1640 .hw.init = &(const struct clk_init_data) { 1641 .name = "disp1_cc_mdss_dptx0_link_intf_clk", 1642 .parent_hws = (const struct clk_hw*[]){ 1643 &disp1_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1644 }, 1645 .num_parents = 1, 1646 .flags = CLK_SET_RATE_PARENT, 1647 .ops = &clk_branch2_ops, 1648 }, 1649 }, 1650 }; 1651 1652 static struct clk_branch disp0_cc_mdss_dptx0_pixel0_clk = { 1653 .halt_reg = 0x2070, 1654 .halt_check = BRANCH_HALT, 1655 .clkr = { 1656 .enable_reg = 0x2070, 1657 .enable_mask = BIT(0), 1658 .hw.init = &(const struct clk_init_data) { 1659 .name = "disp0_cc_mdss_dptx0_pixel0_clk", 1660 .parent_hws = (const struct clk_hw*[]){ 1661 &disp0_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, 1662 }, 1663 .num_parents = 1, 1664 .flags = CLK_SET_RATE_PARENT, 1665 .ops = &clk_branch2_ops, 1666 }, 1667 }, 1668 }; 1669 1670 static struct clk_branch disp1_cc_mdss_dptx0_pixel0_clk = { 1671 .halt_reg = 0x2070, 1672 .halt_check = BRANCH_HALT, 1673 .clkr = { 1674 .enable_reg = 0x2070, 1675 .enable_mask = BIT(0), 1676 .hw.init = &(const struct clk_init_data) { 1677 .name = "disp1_cc_mdss_dptx0_pixel0_clk", 1678 .parent_hws = (const struct clk_hw*[]){ 1679 &disp1_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, 1680 }, 1681 .num_parents = 1, 1682 .flags = CLK_SET_RATE_PARENT, 1683 .ops = &clk_branch2_ops, 1684 }, 1685 }, 1686 }; 1687 1688 static struct clk_branch disp0_cc_mdss_dptx0_pixel1_clk = { 1689 .halt_reg = 0x2074, 1690 .halt_check = BRANCH_HALT, 1691 .clkr = { 1692 .enable_reg = 0x2074, 1693 .enable_mask = BIT(0), 1694 .hw.init = &(const struct clk_init_data) { 1695 .name = "disp0_cc_mdss_dptx0_pixel1_clk", 1696 .parent_hws = (const struct clk_hw*[]){ 1697 &disp0_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, 1698 }, 1699 .num_parents = 1, 1700 .flags = CLK_SET_RATE_PARENT, 1701 .ops = &clk_branch2_ops, 1702 }, 1703 }, 1704 }; 1705 1706 static struct clk_branch disp1_cc_mdss_dptx0_pixel1_clk = { 1707 .halt_reg = 0x2074, 1708 .halt_check = BRANCH_HALT, 1709 .clkr = { 1710 .enable_reg = 0x2074, 1711 .enable_mask = BIT(0), 1712 .hw.init = &(const struct clk_init_data) { 1713 .name = "disp1_cc_mdss_dptx0_pixel1_clk", 1714 .parent_hws = (const struct clk_hw*[]){ 1715 &disp1_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, 1716 }, 1717 .num_parents = 1, 1718 .flags = CLK_SET_RATE_PARENT, 1719 .ops = &clk_branch2_ops, 1720 }, 1721 }, 1722 }; 1723 1724 static struct clk_branch disp0_cc_mdss_dptx0_usb_router_link_intf_clk = { 1725 .halt_reg = 0x2064, 1726 .halt_check = BRANCH_HALT, 1727 .clkr = { 1728 .enable_reg = 0x2064, 1729 .enable_mask = BIT(0), 1730 .hw.init = &(const struct clk_init_data) { 1731 .name = "disp0_cc_mdss_dptx0_usb_router_link_intf_clk", 1732 .parent_hws = (const struct clk_hw*[]){ 1733 &disp0_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1734 }, 1735 .num_parents = 1, 1736 .flags = CLK_SET_RATE_PARENT, 1737 .ops = &clk_branch2_ops, 1738 }, 1739 }, 1740 }; 1741 1742 static struct clk_branch disp1_cc_mdss_dptx0_usb_router_link_intf_clk = { 1743 .halt_reg = 0x2064, 1744 .halt_check = BRANCH_HALT, 1745 .clkr = { 1746 .enable_reg = 0x2064, 1747 .enable_mask = BIT(0), 1748 .hw.init = &(const struct clk_init_data) { 1749 .name = "disp1_cc_mdss_dptx0_usb_router_link_intf_clk", 1750 .parent_hws = (const struct clk_hw*[]){ 1751 &disp1_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1752 }, 1753 .num_parents = 1, 1754 .flags = CLK_SET_RATE_PARENT, 1755 .ops = &clk_branch2_ops, 1756 }, 1757 }, 1758 }; 1759 1760 static struct clk_branch disp0_cc_mdss_dptx1_aux_clk = { 1761 .halt_reg = 0x20a0, 1762 .halt_check = BRANCH_HALT, 1763 .clkr = { 1764 .enable_reg = 0x20a0, 1765 .enable_mask = BIT(0), 1766 .hw.init = &(const struct clk_init_data) { 1767 .name = "disp0_cc_mdss_dptx1_aux_clk", 1768 .parent_hws = (const struct clk_hw*[]){ 1769 &disp0_cc_mdss_dptx1_aux_clk_src.clkr.hw, 1770 }, 1771 .num_parents = 1, 1772 .flags = CLK_SET_RATE_PARENT, 1773 .ops = &clk_branch2_ops, 1774 }, 1775 }, 1776 }; 1777 1778 static struct clk_branch disp1_cc_mdss_dptx1_aux_clk = { 1779 .halt_reg = 0x20a0, 1780 .halt_check = BRANCH_HALT, 1781 .clkr = { 1782 .enable_reg = 0x20a0, 1783 .enable_mask = BIT(0), 1784 .hw.init = &(const struct clk_init_data) { 1785 .name = "disp1_cc_mdss_dptx1_aux_clk", 1786 .parent_hws = (const struct clk_hw*[]){ 1787 &disp1_cc_mdss_dptx1_aux_clk_src.clkr.hw, 1788 }, 1789 .num_parents = 1, 1790 .flags = CLK_SET_RATE_PARENT, 1791 .ops = &clk_branch2_ops, 1792 }, 1793 }, 1794 }; 1795 1796 static struct clk_branch disp0_cc_mdss_dptx1_link_clk = { 1797 .halt_reg = 0x2084, 1798 .halt_check = BRANCH_HALT, 1799 .clkr = { 1800 .enable_reg = 0x2084, 1801 .enable_mask = BIT(0), 1802 .hw.init = &(const struct clk_init_data) { 1803 .name = "disp0_cc_mdss_dptx1_link_clk", 1804 .parent_hws = (const struct clk_hw*[]){ 1805 &disp0_cc_mdss_dptx1_link_clk_src.clkr.hw, 1806 }, 1807 .num_parents = 1, 1808 .flags = CLK_SET_RATE_PARENT, 1809 .ops = &clk_branch2_ops, 1810 }, 1811 }, 1812 }; 1813 1814 static struct clk_branch disp1_cc_mdss_dptx1_link_clk = { 1815 .halt_reg = 0x2084, 1816 .halt_check = BRANCH_HALT, 1817 .clkr = { 1818 .enable_reg = 0x2084, 1819 .enable_mask = BIT(0), 1820 .hw.init = &(const struct clk_init_data) { 1821 .name = "disp1_cc_mdss_dptx1_link_clk", 1822 .parent_hws = (const struct clk_hw*[]){ 1823 &disp1_cc_mdss_dptx1_link_clk_src.clkr.hw, 1824 }, 1825 .num_parents = 1, 1826 .flags = CLK_SET_RATE_PARENT, 1827 .ops = &clk_branch2_ops, 1828 }, 1829 }, 1830 }; 1831 1832 static struct clk_branch disp0_cc_mdss_dptx1_link_intf_clk = { 1833 .halt_reg = 0x2088, 1834 .halt_check = BRANCH_HALT, 1835 .clkr = { 1836 .enable_reg = 0x2088, 1837 .enable_mask = BIT(0), 1838 .hw.init = &(const struct clk_init_data) { 1839 .name = "disp0_cc_mdss_dptx1_link_intf_clk", 1840 .parent_hws = (const struct clk_hw*[]){ 1841 &disp0_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1842 }, 1843 .num_parents = 1, 1844 .flags = CLK_SET_RATE_PARENT, 1845 .ops = &clk_branch2_ops, 1846 }, 1847 }, 1848 }; 1849 1850 static struct clk_branch disp1_cc_mdss_dptx1_link_intf_clk = { 1851 .halt_reg = 0x2088, 1852 .halt_check = BRANCH_HALT, 1853 .clkr = { 1854 .enable_reg = 0x2088, 1855 .enable_mask = BIT(0), 1856 .hw.init = &(const struct clk_init_data) { 1857 .name = "disp1_cc_mdss_dptx1_link_intf_clk", 1858 .parent_hws = (const struct clk_hw*[]){ 1859 &disp1_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1860 }, 1861 .num_parents = 1, 1862 .flags = CLK_SET_RATE_PARENT, 1863 .ops = &clk_branch2_ops, 1864 }, 1865 }, 1866 }; 1867 1868 static struct clk_branch disp0_cc_mdss_dptx1_pixel0_clk = { 1869 .halt_reg = 0x2078, 1870 .halt_check = BRANCH_HALT, 1871 .clkr = { 1872 .enable_reg = 0x2078, 1873 .enable_mask = BIT(0), 1874 .hw.init = &(const struct clk_init_data) { 1875 .name = "disp0_cc_mdss_dptx1_pixel0_clk", 1876 .parent_hws = (const struct clk_hw*[]){ 1877 &disp0_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, 1878 }, 1879 .num_parents = 1, 1880 .flags = CLK_SET_RATE_PARENT, 1881 .ops = &clk_branch2_ops, 1882 }, 1883 }, 1884 }; 1885 1886 static struct clk_branch disp1_cc_mdss_dptx1_pixel0_clk = { 1887 .halt_reg = 0x2078, 1888 .halt_check = BRANCH_HALT, 1889 .clkr = { 1890 .enable_reg = 0x2078, 1891 .enable_mask = BIT(0), 1892 .hw.init = &(const struct clk_init_data) { 1893 .name = "disp1_cc_mdss_dptx1_pixel0_clk", 1894 .parent_hws = (const struct clk_hw*[]){ 1895 &disp1_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, 1896 }, 1897 .num_parents = 1, 1898 .flags = CLK_SET_RATE_PARENT, 1899 .ops = &clk_branch2_ops, 1900 }, 1901 }, 1902 }; 1903 1904 static struct clk_branch disp0_cc_mdss_dptx1_pixel1_clk = { 1905 .halt_reg = 0x236c, 1906 .halt_check = BRANCH_HALT, 1907 .clkr = { 1908 .enable_reg = 0x236c, 1909 .enable_mask = BIT(0), 1910 .hw.init = &(const struct clk_init_data) { 1911 .name = "disp0_cc_mdss_dptx1_pixel1_clk", 1912 .parent_hws = (const struct clk_hw*[]){ 1913 &disp0_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, 1914 }, 1915 .num_parents = 1, 1916 .flags = CLK_SET_RATE_PARENT, 1917 .ops = &clk_branch2_ops, 1918 }, 1919 }, 1920 }; 1921 1922 static struct clk_branch disp1_cc_mdss_dptx1_pixel1_clk = { 1923 .halt_reg = 0x236c, 1924 .halt_check = BRANCH_HALT, 1925 .clkr = { 1926 .enable_reg = 0x236c, 1927 .enable_mask = BIT(0), 1928 .hw.init = &(const struct clk_init_data) { 1929 .name = "disp1_cc_mdss_dptx1_pixel1_clk", 1930 .parent_hws = (const struct clk_hw*[]){ 1931 &disp1_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, 1932 }, 1933 .num_parents = 1, 1934 .flags = CLK_SET_RATE_PARENT, 1935 .ops = &clk_branch2_ops, 1936 }, 1937 }, 1938 }; 1939 1940 static struct clk_branch disp0_cc_mdss_dptx1_usb_router_link_intf_clk = { 1941 .halt_reg = 0x208c, 1942 .halt_check = BRANCH_HALT, 1943 .clkr = { 1944 .enable_reg = 0x208c, 1945 .enable_mask = BIT(0), 1946 .hw.init = &(const struct clk_init_data) { 1947 .name = "disp0_cc_mdss_dptx1_usb_router_link_intf_clk", 1948 .parent_hws = (const struct clk_hw*[]){ 1949 &disp0_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1950 }, 1951 .num_parents = 1, 1952 .flags = CLK_SET_RATE_PARENT, 1953 .ops = &clk_branch2_ops, 1954 }, 1955 }, 1956 }; 1957 1958 static struct clk_branch disp1_cc_mdss_dptx1_usb_router_link_intf_clk = { 1959 .halt_reg = 0x208c, 1960 .halt_check = BRANCH_HALT, 1961 .clkr = { 1962 .enable_reg = 0x208c, 1963 .enable_mask = BIT(0), 1964 .hw.init = &(const struct clk_init_data) { 1965 .name = "disp1_cc_mdss_dptx1_usb_router_link_intf_clk", 1966 .parent_hws = (const struct clk_hw*[]){ 1967 &disp1_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1968 }, 1969 .num_parents = 1, 1970 .flags = CLK_SET_RATE_PARENT, 1971 .ops = &clk_branch2_ops, 1972 }, 1973 }, 1974 }; 1975 1976 static struct clk_branch disp0_cc_mdss_dptx2_aux_clk = { 1977 .halt_reg = 0x20a4, 1978 .halt_check = BRANCH_HALT, 1979 .clkr = { 1980 .enable_reg = 0x20a4, 1981 .enable_mask = BIT(0), 1982 .hw.init = &(const struct clk_init_data) { 1983 .name = "disp0_cc_mdss_dptx2_aux_clk", 1984 .parent_hws = (const struct clk_hw*[]){ 1985 &disp0_cc_mdss_dptx2_aux_clk_src.clkr.hw, 1986 }, 1987 .num_parents = 1, 1988 .flags = CLK_SET_RATE_PARENT, 1989 .ops = &clk_branch2_ops, 1990 }, 1991 }, 1992 }; 1993 1994 static struct clk_branch disp1_cc_mdss_dptx2_aux_clk = { 1995 .halt_reg = 0x20a4, 1996 .halt_check = BRANCH_HALT, 1997 .clkr = { 1998 .enable_reg = 0x20a4, 1999 .enable_mask = BIT(0), 2000 .hw.init = &(const struct clk_init_data) { 2001 .name = "disp1_cc_mdss_dptx2_aux_clk", 2002 .parent_hws = (const struct clk_hw*[]){ 2003 &disp1_cc_mdss_dptx2_aux_clk_src.clkr.hw, 2004 }, 2005 .num_parents = 1, 2006 .flags = CLK_SET_RATE_PARENT, 2007 .ops = &clk_branch2_ops, 2008 }, 2009 }, 2010 }; 2011 2012 static struct clk_branch disp0_cc_mdss_dptx2_link_clk = { 2013 .halt_reg = 0x2090, 2014 .halt_check = BRANCH_HALT, 2015 .clkr = { 2016 .enable_reg = 0x2090, 2017 .enable_mask = BIT(0), 2018 .hw.init = &(const struct clk_init_data) { 2019 .name = "disp0_cc_mdss_dptx2_link_clk", 2020 .parent_hws = (const struct clk_hw*[]){ 2021 &disp0_cc_mdss_dptx2_link_clk_src.clkr.hw, 2022 }, 2023 .num_parents = 1, 2024 .flags = CLK_SET_RATE_PARENT, 2025 .ops = &clk_branch2_ops, 2026 }, 2027 }, 2028 }; 2029 2030 static struct clk_branch disp1_cc_mdss_dptx2_link_clk = { 2031 .halt_reg = 0x2090, 2032 .halt_check = BRANCH_HALT, 2033 .clkr = { 2034 .enable_reg = 0x2090, 2035 .enable_mask = BIT(0), 2036 .hw.init = &(const struct clk_init_data) { 2037 .name = "disp1_cc_mdss_dptx2_link_clk", 2038 .parent_hws = (const struct clk_hw*[]){ 2039 &disp1_cc_mdss_dptx2_link_clk_src.clkr.hw, 2040 }, 2041 .num_parents = 1, 2042 .flags = CLK_SET_RATE_PARENT, 2043 .ops = &clk_branch2_ops, 2044 }, 2045 }, 2046 }; 2047 2048 static struct clk_branch disp0_cc_mdss_dptx2_link_intf_clk = { 2049 .halt_reg = 0x2094, 2050 .halt_check = BRANCH_HALT, 2051 .clkr = { 2052 .enable_reg = 0x2094, 2053 .enable_mask = BIT(0), 2054 .hw.init = &(const struct clk_init_data) { 2055 .name = "disp0_cc_mdss_dptx2_link_intf_clk", 2056 .parent_hws = (const struct clk_hw*[]){ 2057 &disp0_cc_mdss_dptx2_link_div_clk_src.clkr.hw, 2058 }, 2059 .num_parents = 1, 2060 .flags = CLK_SET_RATE_PARENT, 2061 .ops = &clk_branch2_ops, 2062 }, 2063 }, 2064 }; 2065 2066 static struct clk_branch disp1_cc_mdss_dptx2_link_intf_clk = { 2067 .halt_reg = 0x2094, 2068 .halt_check = BRANCH_HALT, 2069 .clkr = { 2070 .enable_reg = 0x2094, 2071 .enable_mask = BIT(0), 2072 .hw.init = &(const struct clk_init_data) { 2073 .name = "disp1_cc_mdss_dptx2_link_intf_clk", 2074 .parent_hws = (const struct clk_hw*[]){ 2075 &disp1_cc_mdss_dptx2_link_div_clk_src.clkr.hw, 2076 }, 2077 .num_parents = 1, 2078 .flags = CLK_SET_RATE_PARENT, 2079 .ops = &clk_branch2_ops, 2080 }, 2081 }, 2082 }; 2083 2084 static struct clk_branch disp0_cc_mdss_dptx2_pixel0_clk = { 2085 .halt_reg = 0x207c, 2086 .halt_check = BRANCH_HALT, 2087 .clkr = { 2088 .enable_reg = 0x207c, 2089 .enable_mask = BIT(0), 2090 .hw.init = &(const struct clk_init_data) { 2091 .name = "disp0_cc_mdss_dptx2_pixel0_clk", 2092 .parent_hws = (const struct clk_hw*[]){ 2093 &disp0_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, 2094 }, 2095 .num_parents = 1, 2096 .flags = CLK_SET_RATE_PARENT, 2097 .ops = &clk_branch2_ops, 2098 }, 2099 }, 2100 }; 2101 2102 static struct clk_branch disp1_cc_mdss_dptx2_pixel0_clk = { 2103 .halt_reg = 0x207c, 2104 .halt_check = BRANCH_HALT, 2105 .clkr = { 2106 .enable_reg = 0x207c, 2107 .enable_mask = BIT(0), 2108 .hw.init = &(const struct clk_init_data) { 2109 .name = "disp1_cc_mdss_dptx2_pixel0_clk", 2110 .parent_hws = (const struct clk_hw*[]){ 2111 &disp1_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, 2112 }, 2113 .num_parents = 1, 2114 .flags = CLK_SET_RATE_PARENT, 2115 .ops = &clk_branch2_ops, 2116 }, 2117 }, 2118 }; 2119 2120 static struct clk_branch disp0_cc_mdss_dptx2_pixel1_clk = { 2121 .halt_reg = 0x2080, 2122 .halt_check = BRANCH_HALT, 2123 .clkr = { 2124 .enable_reg = 0x2080, 2125 .enable_mask = BIT(0), 2126 .hw.init = &(const struct clk_init_data) { 2127 .name = "disp0_cc_mdss_dptx2_pixel1_clk", 2128 .parent_hws = (const struct clk_hw*[]){ 2129 &disp0_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, 2130 }, 2131 .num_parents = 1, 2132 .flags = CLK_SET_RATE_PARENT, 2133 .ops = &clk_branch2_ops, 2134 }, 2135 }, 2136 }; 2137 2138 static struct clk_branch disp1_cc_mdss_dptx2_pixel1_clk = { 2139 .halt_reg = 0x2080, 2140 .halt_check = BRANCH_HALT, 2141 .clkr = { 2142 .enable_reg = 0x2080, 2143 .enable_mask = BIT(0), 2144 .hw.init = &(const struct clk_init_data) { 2145 .name = "disp1_cc_mdss_dptx2_pixel1_clk", 2146 .parent_hws = (const struct clk_hw*[]){ 2147 &disp1_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, 2148 }, 2149 .num_parents = 1, 2150 .flags = CLK_SET_RATE_PARENT, 2151 .ops = &clk_branch2_ops, 2152 }, 2153 }, 2154 }; 2155 2156 static struct clk_branch disp0_cc_mdss_dptx3_aux_clk = { 2157 .halt_reg = 0x20b8, 2158 .halt_check = BRANCH_HALT, 2159 .clkr = { 2160 .enable_reg = 0x20b8, 2161 .enable_mask = BIT(0), 2162 .hw.init = &(const struct clk_init_data) { 2163 .name = "disp0_cc_mdss_dptx3_aux_clk", 2164 .parent_hws = (const struct clk_hw*[]){ 2165 &disp0_cc_mdss_dptx3_aux_clk_src.clkr.hw, 2166 }, 2167 .num_parents = 1, 2168 .flags = CLK_SET_RATE_PARENT, 2169 .ops = &clk_branch2_ops, 2170 }, 2171 }, 2172 }; 2173 2174 static struct clk_branch disp1_cc_mdss_dptx3_aux_clk = { 2175 .halt_reg = 0x20b8, 2176 .halt_check = BRANCH_HALT, 2177 .clkr = { 2178 .enable_reg = 0x20b8, 2179 .enable_mask = BIT(0), 2180 .hw.init = &(const struct clk_init_data) { 2181 .name = "disp1_cc_mdss_dptx3_aux_clk", 2182 .parent_hws = (const struct clk_hw*[]){ 2183 &disp1_cc_mdss_dptx3_aux_clk_src.clkr.hw, 2184 }, 2185 .num_parents = 1, 2186 .flags = CLK_SET_RATE_PARENT, 2187 .ops = &clk_branch2_ops, 2188 }, 2189 }, 2190 }; 2191 2192 static struct clk_branch disp0_cc_mdss_dptx3_link_clk = { 2193 .halt_reg = 0x20ac, 2194 .halt_check = BRANCH_HALT, 2195 .clkr = { 2196 .enable_reg = 0x20ac, 2197 .enable_mask = BIT(0), 2198 .hw.init = &(const struct clk_init_data) { 2199 .name = "disp0_cc_mdss_dptx3_link_clk", 2200 .parent_hws = (const struct clk_hw*[]){ 2201 &disp0_cc_mdss_dptx3_link_clk_src.clkr.hw, 2202 }, 2203 .num_parents = 1, 2204 .flags = CLK_SET_RATE_PARENT, 2205 .ops = &clk_branch2_ops, 2206 }, 2207 }, 2208 }; 2209 2210 static struct clk_branch disp1_cc_mdss_dptx3_link_clk = { 2211 .halt_reg = 0x20ac, 2212 .halt_check = BRANCH_HALT, 2213 .clkr = { 2214 .enable_reg = 0x20ac, 2215 .enable_mask = BIT(0), 2216 .hw.init = &(const struct clk_init_data) { 2217 .name = "disp1_cc_mdss_dptx3_link_clk", 2218 .parent_hws = (const struct clk_hw*[]){ 2219 &disp1_cc_mdss_dptx3_link_clk_src.clkr.hw, 2220 }, 2221 .num_parents = 1, 2222 .flags = CLK_SET_RATE_PARENT, 2223 .ops = &clk_branch2_ops, 2224 }, 2225 }, 2226 }; 2227 2228 static struct clk_branch disp0_cc_mdss_dptx3_link_intf_clk = { 2229 .halt_reg = 0x20b0, 2230 .halt_check = BRANCH_HALT, 2231 .clkr = { 2232 .enable_reg = 0x20b0, 2233 .enable_mask = BIT(0), 2234 .hw.init = &(const struct clk_init_data) { 2235 .name = "disp0_cc_mdss_dptx3_link_intf_clk", 2236 .parent_hws = (const struct clk_hw*[]){ 2237 &disp0_cc_mdss_dptx3_link_div_clk_src.clkr.hw, 2238 }, 2239 .num_parents = 1, 2240 .flags = CLK_SET_RATE_PARENT, 2241 .ops = &clk_branch2_ops, 2242 }, 2243 }, 2244 }; 2245 2246 static struct clk_branch disp1_cc_mdss_dptx3_link_intf_clk = { 2247 .halt_reg = 0x20b0, 2248 .halt_check = BRANCH_HALT, 2249 .clkr = { 2250 .enable_reg = 0x20b0, 2251 .enable_mask = BIT(0), 2252 .hw.init = &(const struct clk_init_data) { 2253 .name = "disp1_cc_mdss_dptx3_link_intf_clk", 2254 .parent_hws = (const struct clk_hw*[]){ 2255 &disp1_cc_mdss_dptx3_link_div_clk_src.clkr.hw, 2256 }, 2257 .num_parents = 1, 2258 .flags = CLK_SET_RATE_PARENT, 2259 .ops = &clk_branch2_ops, 2260 }, 2261 }, 2262 }; 2263 2264 static struct clk_branch disp0_cc_mdss_dptx3_pixel0_clk = { 2265 .halt_reg = 0x20a8, 2266 .halt_check = BRANCH_HALT, 2267 .clkr = { 2268 .enable_reg = 0x20a8, 2269 .enable_mask = BIT(0), 2270 .hw.init = &(const struct clk_init_data) { 2271 .name = "disp0_cc_mdss_dptx3_pixel0_clk", 2272 .parent_hws = (const struct clk_hw*[]){ 2273 &disp0_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, 2274 }, 2275 .num_parents = 1, 2276 .flags = CLK_SET_RATE_PARENT, 2277 .ops = &clk_branch2_ops, 2278 }, 2279 }, 2280 }; 2281 2282 static struct clk_branch disp1_cc_mdss_dptx3_pixel0_clk = { 2283 .halt_reg = 0x20a8, 2284 .halt_check = BRANCH_HALT, 2285 .clkr = { 2286 .enable_reg = 0x20a8, 2287 .enable_mask = BIT(0), 2288 .hw.init = &(const struct clk_init_data) { 2289 .name = "disp1_cc_mdss_dptx3_pixel0_clk", 2290 .parent_hws = (const struct clk_hw*[]){ 2291 &disp1_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, 2292 }, 2293 .num_parents = 1, 2294 .flags = CLK_SET_RATE_PARENT, 2295 .ops = &clk_branch2_ops, 2296 }, 2297 }, 2298 }; 2299 2300 static struct clk_branch disp0_cc_mdss_esc0_clk = { 2301 .halt_reg = 0x2054, 2302 .halt_check = BRANCH_HALT, 2303 .clkr = { 2304 .enable_reg = 0x2054, 2305 .enable_mask = BIT(0), 2306 .hw.init = &(const struct clk_init_data) { 2307 .name = "disp0_cc_mdss_esc0_clk", 2308 .parent_hws = (const struct clk_hw*[]){ 2309 &disp0_cc_mdss_esc0_clk_src.clkr.hw, 2310 }, 2311 .num_parents = 1, 2312 .flags = CLK_SET_RATE_PARENT, 2313 .ops = &clk_branch2_ops, 2314 }, 2315 }, 2316 }; 2317 2318 static struct clk_branch disp1_cc_mdss_esc0_clk = { 2319 .halt_reg = 0x2054, 2320 .halt_check = BRANCH_HALT, 2321 .clkr = { 2322 .enable_reg = 0x2054, 2323 .enable_mask = BIT(0), 2324 .hw.init = &(const struct clk_init_data) { 2325 .name = "disp1_cc_mdss_esc0_clk", 2326 .parent_hws = (const struct clk_hw*[]){ 2327 &disp1_cc_mdss_esc0_clk_src.clkr.hw, 2328 }, 2329 .num_parents = 1, 2330 .flags = CLK_SET_RATE_PARENT, 2331 .ops = &clk_branch2_ops, 2332 }, 2333 }, 2334 }; 2335 2336 static struct clk_branch disp0_cc_mdss_esc1_clk = { 2337 .halt_reg = 0x2058, 2338 .halt_check = BRANCH_HALT, 2339 .clkr = { 2340 .enable_reg = 0x2058, 2341 .enable_mask = BIT(0), 2342 .hw.init = &(const struct clk_init_data) { 2343 .name = "disp0_cc_mdss_esc1_clk", 2344 .parent_hws = (const struct clk_hw*[]){ 2345 &disp0_cc_mdss_esc1_clk_src.clkr.hw, 2346 }, 2347 .num_parents = 1, 2348 .flags = CLK_SET_RATE_PARENT, 2349 .ops = &clk_branch2_ops, 2350 }, 2351 }, 2352 }; 2353 2354 static struct clk_branch disp1_cc_mdss_esc1_clk = { 2355 .halt_reg = 0x2058, 2356 .halt_check = BRANCH_HALT, 2357 .clkr = { 2358 .enable_reg = 0x2058, 2359 .enable_mask = BIT(0), 2360 .hw.init = &(const struct clk_init_data) { 2361 .name = "disp1_cc_mdss_esc1_clk", 2362 .parent_hws = (const struct clk_hw*[]){ 2363 &disp1_cc_mdss_esc1_clk_src.clkr.hw, 2364 }, 2365 .num_parents = 1, 2366 .flags = CLK_SET_RATE_PARENT, 2367 .ops = &clk_branch2_ops, 2368 }, 2369 }, 2370 }; 2371 2372 static struct clk_branch disp0_cc_mdss_mdp1_clk = { 2373 .halt_reg = 0x2014, 2374 .halt_check = BRANCH_HALT, 2375 .clkr = { 2376 .enable_reg = 0x2014, 2377 .enable_mask = BIT(0), 2378 .hw.init = &(const struct clk_init_data) { 2379 .name = "disp0_cc_mdss_mdp1_clk", 2380 .parent_hws = (const struct clk_hw*[]){ 2381 &disp0_cc_mdss_mdp_clk_src.clkr.hw, 2382 }, 2383 .num_parents = 1, 2384 .flags = CLK_SET_RATE_PARENT, 2385 .ops = &clk_branch2_ops, 2386 }, 2387 }, 2388 }; 2389 2390 static struct clk_branch disp1_cc_mdss_mdp1_clk = { 2391 .halt_reg = 0x2014, 2392 .halt_check = BRANCH_HALT, 2393 .clkr = { 2394 .enable_reg = 0x2014, 2395 .enable_mask = BIT(0), 2396 .hw.init = &(const struct clk_init_data) { 2397 .name = "disp1_cc_mdss_mdp1_clk", 2398 .parent_hws = (const struct clk_hw*[]){ 2399 &disp1_cc_mdss_mdp_clk_src.clkr.hw, 2400 }, 2401 .num_parents = 1, 2402 .flags = CLK_SET_RATE_PARENT, 2403 .ops = &clk_branch2_ops, 2404 }, 2405 }, 2406 }; 2407 2408 static struct clk_branch disp0_cc_mdss_mdp_clk = { 2409 .halt_reg = 0x200c, 2410 .halt_check = BRANCH_HALT, 2411 .clkr = { 2412 .enable_reg = 0x200c, 2413 .enable_mask = BIT(0), 2414 .hw.init = &(const struct clk_init_data) { 2415 .name = "disp0_cc_mdss_mdp_clk", 2416 .parent_hws = (const struct clk_hw*[]){ 2417 &disp0_cc_mdss_mdp_clk_src.clkr.hw, 2418 }, 2419 .num_parents = 1, 2420 .flags = CLK_SET_RATE_PARENT, 2421 .ops = &clk_branch2_ops, 2422 }, 2423 }, 2424 }; 2425 2426 static struct clk_branch disp1_cc_mdss_mdp_clk = { 2427 .halt_reg = 0x200c, 2428 .halt_check = BRANCH_HALT, 2429 .clkr = { 2430 .enable_reg = 0x200c, 2431 .enable_mask = BIT(0), 2432 .hw.init = &(const struct clk_init_data) { 2433 .name = "disp1_cc_mdss_mdp_clk", 2434 .parent_hws = (const struct clk_hw*[]){ 2435 &disp1_cc_mdss_mdp_clk_src.clkr.hw, 2436 }, 2437 .num_parents = 1, 2438 .flags = CLK_SET_RATE_PARENT, 2439 .ops = &clk_branch2_ops, 2440 }, 2441 }, 2442 }; 2443 2444 static struct clk_branch disp0_cc_mdss_mdp_lut1_clk = { 2445 .halt_reg = 0x2034, 2446 .halt_check = BRANCH_HALT, 2447 .clkr = { 2448 .enable_reg = 0x2034, 2449 .enable_mask = BIT(0), 2450 .hw.init = &(const struct clk_init_data) { 2451 .name = "disp0_cc_mdss_mdp_lut1_clk", 2452 .parent_hws = (const struct clk_hw*[]){ 2453 &disp0_cc_mdss_mdp_clk_src.clkr.hw, 2454 }, 2455 .num_parents = 1, 2456 .flags = CLK_SET_RATE_PARENT, 2457 .ops = &clk_branch2_ops, 2458 }, 2459 }, 2460 }; 2461 2462 static struct clk_branch disp1_cc_mdss_mdp_lut1_clk = { 2463 .halt_reg = 0x2034, 2464 .halt_check = BRANCH_HALT, 2465 .clkr = { 2466 .enable_reg = 0x2034, 2467 .enable_mask = BIT(0), 2468 .hw.init = &(const struct clk_init_data) { 2469 .name = "disp1_cc_mdss_mdp_lut1_clk", 2470 .parent_hws = (const struct clk_hw*[]){ 2471 &disp1_cc_mdss_mdp_clk_src.clkr.hw, 2472 }, 2473 .num_parents = 1, 2474 .flags = CLK_SET_RATE_PARENT, 2475 .ops = &clk_branch2_ops, 2476 }, 2477 }, 2478 }; 2479 2480 static struct clk_branch disp0_cc_mdss_mdp_lut_clk = { 2481 .halt_reg = 0x202c, 2482 .halt_check = BRANCH_HALT_VOTED, 2483 .clkr = { 2484 .enable_reg = 0x202c, 2485 .enable_mask = BIT(0), 2486 .hw.init = &(const struct clk_init_data) { 2487 .name = "disp0_cc_mdss_mdp_lut_clk", 2488 .parent_hws = (const struct clk_hw*[]){ 2489 &disp0_cc_mdss_mdp_clk_src.clkr.hw, 2490 }, 2491 .num_parents = 1, 2492 .flags = CLK_SET_RATE_PARENT, 2493 .ops = &clk_branch2_ops, 2494 }, 2495 }, 2496 }; 2497 2498 static struct clk_branch disp1_cc_mdss_mdp_lut_clk = { 2499 .halt_reg = 0x202c, 2500 .halt_check = BRANCH_HALT_VOTED, 2501 .clkr = { 2502 .enable_reg = 0x202c, 2503 .enable_mask = BIT(0), 2504 .hw.init = &(const struct clk_init_data) { 2505 .name = "disp1_cc_mdss_mdp_lut_clk", 2506 .parent_hws = (const struct clk_hw*[]){ 2507 &disp1_cc_mdss_mdp_clk_src.clkr.hw, 2508 }, 2509 .num_parents = 1, 2510 .flags = CLK_SET_RATE_PARENT, 2511 .ops = &clk_branch2_ops, 2512 }, 2513 }, 2514 }; 2515 2516 static struct clk_branch disp0_cc_mdss_non_gdsc_ahb_clk = { 2517 .halt_reg = 0x4004, 2518 .halt_check = BRANCH_HALT_VOTED, 2519 .clkr = { 2520 .enable_reg = 0x4004, 2521 .enable_mask = BIT(0), 2522 .hw.init = &(const struct clk_init_data) { 2523 .name = "disp0_cc_mdss_non_gdsc_ahb_clk", 2524 .parent_hws = (const struct clk_hw*[]){ 2525 &disp0_cc_mdss_ahb_clk_src.clkr.hw, 2526 }, 2527 .num_parents = 1, 2528 .flags = CLK_SET_RATE_PARENT, 2529 .ops = &clk_branch2_ops, 2530 }, 2531 }, 2532 }; 2533 2534 static struct clk_branch disp1_cc_mdss_non_gdsc_ahb_clk = { 2535 .halt_reg = 0x4004, 2536 .halt_check = BRANCH_HALT_VOTED, 2537 .clkr = { 2538 .enable_reg = 0x4004, 2539 .enable_mask = BIT(0), 2540 .hw.init = &(const struct clk_init_data) { 2541 .name = "disp1_cc_mdss_non_gdsc_ahb_clk", 2542 .parent_hws = (const struct clk_hw*[]){ 2543 &disp1_cc_mdss_ahb_clk_src.clkr.hw, 2544 }, 2545 .num_parents = 1, 2546 .flags = CLK_SET_RATE_PARENT, 2547 .ops = &clk_branch2_ops, 2548 }, 2549 }, 2550 }; 2551 2552 static struct clk_branch disp0_cc_mdss_pclk0_clk = { 2553 .halt_reg = 0x2004, 2554 .halt_check = BRANCH_HALT, 2555 .clkr = { 2556 .enable_reg = 0x2004, 2557 .enable_mask = BIT(0), 2558 .hw.init = &(const struct clk_init_data) { 2559 .name = "disp0_cc_mdss_pclk0_clk", 2560 .parent_hws = (const struct clk_hw*[]){ 2561 &disp0_cc_mdss_pclk0_clk_src.clkr.hw, 2562 }, 2563 .num_parents = 1, 2564 .flags = CLK_SET_RATE_PARENT, 2565 .ops = &clk_branch2_ops, 2566 }, 2567 }, 2568 }; 2569 2570 static struct clk_branch disp1_cc_mdss_pclk0_clk = { 2571 .halt_reg = 0x2004, 2572 .halt_check = BRANCH_HALT, 2573 .clkr = { 2574 .enable_reg = 0x2004, 2575 .enable_mask = BIT(0), 2576 .hw.init = &(const struct clk_init_data) { 2577 .name = "disp1_cc_mdss_pclk0_clk", 2578 .parent_hws = (const struct clk_hw*[]){ 2579 &disp1_cc_mdss_pclk0_clk_src.clkr.hw, 2580 }, 2581 .num_parents = 1, 2582 .flags = CLK_SET_RATE_PARENT, 2583 .ops = &clk_branch2_ops, 2584 }, 2585 }, 2586 }; 2587 2588 static struct clk_branch disp0_cc_mdss_pclk1_clk = { 2589 .halt_reg = 0x2008, 2590 .halt_check = BRANCH_HALT, 2591 .clkr = { 2592 .enable_reg = 0x2008, 2593 .enable_mask = BIT(0), 2594 .hw.init = &(const struct clk_init_data) { 2595 .name = "disp0_cc_mdss_pclk1_clk", 2596 .parent_hws = (const struct clk_hw*[]){ 2597 &disp0_cc_mdss_pclk1_clk_src.clkr.hw, 2598 }, 2599 .num_parents = 1, 2600 .flags = CLK_SET_RATE_PARENT, 2601 .ops = &clk_branch2_ops, 2602 }, 2603 }, 2604 }; 2605 2606 static struct clk_branch disp1_cc_mdss_pclk1_clk = { 2607 .halt_reg = 0x2008, 2608 .halt_check = BRANCH_HALT, 2609 .clkr = { 2610 .enable_reg = 0x2008, 2611 .enable_mask = BIT(0), 2612 .hw.init = &(const struct clk_init_data) { 2613 .name = "disp1_cc_mdss_pclk1_clk", 2614 .parent_hws = (const struct clk_hw*[]){ 2615 &disp1_cc_mdss_pclk1_clk_src.clkr.hw, 2616 }, 2617 .num_parents = 1, 2618 .flags = CLK_SET_RATE_PARENT, 2619 .ops = &clk_branch2_ops, 2620 }, 2621 }, 2622 }; 2623 2624 static struct clk_branch disp0_cc_mdss_rot1_clk = { 2625 .halt_reg = 0x2024, 2626 .halt_check = BRANCH_HALT, 2627 .clkr = { 2628 .enable_reg = 0x2024, 2629 .enable_mask = BIT(0), 2630 .hw.init = &(const struct clk_init_data) { 2631 .name = "disp0_cc_mdss_rot1_clk", 2632 .parent_hws = (const struct clk_hw*[]){ 2633 &disp0_cc_mdss_rot_clk_src.clkr.hw, 2634 }, 2635 .num_parents = 1, 2636 .flags = CLK_SET_RATE_PARENT, 2637 .ops = &clk_branch2_ops, 2638 }, 2639 }, 2640 }; 2641 2642 static struct clk_branch disp1_cc_mdss_rot1_clk = { 2643 .halt_reg = 0x2024, 2644 .halt_check = BRANCH_HALT, 2645 .clkr = { 2646 .enable_reg = 0x2024, 2647 .enable_mask = BIT(0), 2648 .hw.init = &(const struct clk_init_data) { 2649 .name = "disp1_cc_mdss_rot1_clk", 2650 .parent_hws = (const struct clk_hw*[]){ 2651 &disp1_cc_mdss_rot_clk_src.clkr.hw, 2652 }, 2653 .num_parents = 1, 2654 .flags = CLK_SET_RATE_PARENT, 2655 .ops = &clk_branch2_ops, 2656 }, 2657 }, 2658 }; 2659 2660 static struct clk_branch disp0_cc_mdss_rot_clk = { 2661 .halt_reg = 0x201c, 2662 .halt_check = BRANCH_HALT, 2663 .clkr = { 2664 .enable_reg = 0x201c, 2665 .enable_mask = BIT(0), 2666 .hw.init = &(const struct clk_init_data) { 2667 .name = "disp0_cc_mdss_rot_clk", 2668 .parent_hws = (const struct clk_hw*[]){ 2669 &disp0_cc_mdss_rot_clk_src.clkr.hw, 2670 }, 2671 .num_parents = 1, 2672 .flags = CLK_SET_RATE_PARENT, 2673 .ops = &clk_branch2_ops, 2674 }, 2675 }, 2676 }; 2677 2678 static struct clk_branch disp1_cc_mdss_rot_clk = { 2679 .halt_reg = 0x201c, 2680 .halt_check = BRANCH_HALT, 2681 .clkr = { 2682 .enable_reg = 0x201c, 2683 .enable_mask = BIT(0), 2684 .hw.init = &(const struct clk_init_data) { 2685 .name = "disp1_cc_mdss_rot_clk", 2686 .parent_hws = (const struct clk_hw*[]){ 2687 &disp1_cc_mdss_rot_clk_src.clkr.hw, 2688 }, 2689 .num_parents = 1, 2690 .flags = CLK_SET_RATE_PARENT, 2691 .ops = &clk_branch2_ops, 2692 }, 2693 }, 2694 }; 2695 2696 static struct clk_branch disp0_cc_mdss_rscc_ahb_clk = { 2697 .halt_reg = 0x400c, 2698 .halt_check = BRANCH_HALT, 2699 .clkr = { 2700 .enable_reg = 0x400c, 2701 .enable_mask = BIT(0), 2702 .hw.init = &(const struct clk_init_data) { 2703 .name = "disp0_cc_mdss_rscc_ahb_clk", 2704 .parent_hws = (const struct clk_hw*[]){ 2705 &disp0_cc_mdss_ahb_clk_src.clkr.hw, 2706 }, 2707 .num_parents = 1, 2708 .flags = CLK_SET_RATE_PARENT, 2709 .ops = &clk_branch2_ops, 2710 }, 2711 }, 2712 }; 2713 2714 static struct clk_branch disp1_cc_mdss_rscc_ahb_clk = { 2715 .halt_reg = 0x400c, 2716 .halt_check = BRANCH_HALT, 2717 .clkr = { 2718 .enable_reg = 0x400c, 2719 .enable_mask = BIT(0), 2720 .hw.init = &(const struct clk_init_data) { 2721 .name = "disp1_cc_mdss_rscc_ahb_clk", 2722 .parent_hws = (const struct clk_hw*[]){ 2723 &disp1_cc_mdss_ahb_clk_src.clkr.hw, 2724 }, 2725 .num_parents = 1, 2726 .flags = CLK_SET_RATE_PARENT, 2727 .ops = &clk_branch2_ops, 2728 }, 2729 }, 2730 }; 2731 2732 static struct clk_branch disp0_cc_mdss_rscc_vsync_clk = { 2733 .halt_reg = 0x4008, 2734 .halt_check = BRANCH_HALT, 2735 .clkr = { 2736 .enable_reg = 0x4008, 2737 .enable_mask = BIT(0), 2738 .hw.init = &(const struct clk_init_data) { 2739 .name = "disp0_cc_mdss_rscc_vsync_clk", 2740 .parent_hws = (const struct clk_hw*[]){ 2741 &disp0_cc_mdss_vsync_clk_src.clkr.hw, 2742 }, 2743 .num_parents = 1, 2744 .flags = CLK_SET_RATE_PARENT, 2745 .ops = &clk_branch2_ops, 2746 }, 2747 }, 2748 }; 2749 2750 static struct clk_branch disp1_cc_mdss_rscc_vsync_clk = { 2751 .halt_reg = 0x4008, 2752 .halt_check = BRANCH_HALT, 2753 .clkr = { 2754 .enable_reg = 0x4008, 2755 .enable_mask = BIT(0), 2756 .hw.init = &(const struct clk_init_data) { 2757 .name = "disp1_cc_mdss_rscc_vsync_clk", 2758 .parent_hws = (const struct clk_hw*[]){ 2759 &disp1_cc_mdss_vsync_clk_src.clkr.hw, 2760 }, 2761 .num_parents = 1, 2762 .flags = CLK_SET_RATE_PARENT, 2763 .ops = &clk_branch2_ops, 2764 }, 2765 }, 2766 }; 2767 2768 static struct clk_branch disp0_cc_mdss_vsync1_clk = { 2769 .halt_reg = 0x2040, 2770 .halt_check = BRANCH_HALT, 2771 .clkr = { 2772 .enable_reg = 0x2040, 2773 .enable_mask = BIT(0), 2774 .hw.init = &(const struct clk_init_data) { 2775 .name = "disp0_cc_mdss_vsync1_clk", 2776 .parent_hws = (const struct clk_hw*[]){ 2777 &disp0_cc_mdss_vsync_clk_src.clkr.hw, 2778 }, 2779 .num_parents = 1, 2780 .flags = CLK_SET_RATE_PARENT, 2781 .ops = &clk_branch2_ops, 2782 }, 2783 }, 2784 }; 2785 2786 static struct clk_branch disp1_cc_mdss_vsync1_clk = { 2787 .halt_reg = 0x2040, 2788 .halt_check = BRANCH_HALT, 2789 .clkr = { 2790 .enable_reg = 0x2040, 2791 .enable_mask = BIT(0), 2792 .hw.init = &(const struct clk_init_data) { 2793 .name = "disp1_cc_mdss_vsync1_clk", 2794 .parent_hws = (const struct clk_hw*[]){ 2795 &disp1_cc_mdss_vsync_clk_src.clkr.hw, 2796 }, 2797 .num_parents = 1, 2798 .flags = CLK_SET_RATE_PARENT, 2799 .ops = &clk_branch2_ops, 2800 }, 2801 }, 2802 }; 2803 2804 static struct clk_branch disp0_cc_mdss_vsync_clk = { 2805 .halt_reg = 0x203c, 2806 .halt_check = BRANCH_HALT, 2807 .clkr = { 2808 .enable_reg = 0x203c, 2809 .enable_mask = BIT(0), 2810 .hw.init = &(const struct clk_init_data) { 2811 .name = "disp0_cc_mdss_vsync_clk", 2812 .parent_hws = (const struct clk_hw*[]){ 2813 &disp0_cc_mdss_vsync_clk_src.clkr.hw, 2814 }, 2815 .num_parents = 1, 2816 .flags = CLK_SET_RATE_PARENT, 2817 .ops = &clk_branch2_ops, 2818 }, 2819 }, 2820 }; 2821 2822 static struct clk_branch disp1_cc_mdss_vsync_clk = { 2823 .halt_reg = 0x203c, 2824 .halt_check = BRANCH_HALT, 2825 .clkr = { 2826 .enable_reg = 0x203c, 2827 .enable_mask = BIT(0), 2828 .hw.init = &(const struct clk_init_data) { 2829 .name = "disp1_cc_mdss_vsync_clk", 2830 .parent_hws = (const struct clk_hw*[]){ 2831 &disp1_cc_mdss_vsync_clk_src.clkr.hw, 2832 }, 2833 .num_parents = 1, 2834 .flags = CLK_SET_RATE_PARENT, 2835 .ops = &clk_branch2_ops, 2836 }, 2837 }, 2838 }; 2839 2840 static struct clk_branch disp0_cc_sleep_clk = { 2841 .halt_reg = 0x6078, 2842 .halt_check = BRANCH_HALT, 2843 .clkr = { 2844 .enable_reg = 0x6078, 2845 .enable_mask = BIT(0), 2846 .hw.init = &(const struct clk_init_data) { 2847 .name = "disp0_cc_sleep_clk", 2848 .parent_hws = (const struct clk_hw*[]){ 2849 &disp0_cc_sleep_clk_src.clkr.hw, 2850 }, 2851 .num_parents = 1, 2852 .flags = CLK_SET_RATE_PARENT, 2853 .ops = &clk_branch2_ops, 2854 }, 2855 }, 2856 }; 2857 2858 static struct clk_branch disp1_cc_sleep_clk = { 2859 .halt_reg = 0x6078, 2860 .halt_check = BRANCH_HALT, 2861 .clkr = { 2862 .enable_reg = 0x6078, 2863 .enable_mask = BIT(0), 2864 .hw.init = &(const struct clk_init_data) { 2865 .name = "disp1_cc_sleep_clk", 2866 .parent_hws = (const struct clk_hw*[]){ 2867 &disp1_cc_sleep_clk_src.clkr.hw, 2868 }, 2869 .num_parents = 1, 2870 .flags = CLK_SET_RATE_PARENT, 2871 .ops = &clk_branch2_ops, 2872 }, 2873 }, 2874 }; 2875 2876 static struct clk_regmap *disp0_cc_sc8280xp_clocks[] = { 2877 [DISP_CC_MDSS_AHB1_CLK] = &disp0_cc_mdss_ahb1_clk.clkr, 2878 [DISP_CC_MDSS_AHB_CLK] = &disp0_cc_mdss_ahb_clk.clkr, 2879 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp0_cc_mdss_ahb_clk_src.clkr, 2880 [DISP_CC_MDSS_BYTE0_CLK] = &disp0_cc_mdss_byte0_clk.clkr, 2881 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp0_cc_mdss_byte0_clk_src.clkr, 2882 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp0_cc_mdss_byte0_div_clk_src.clkr, 2883 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp0_cc_mdss_byte0_intf_clk.clkr, 2884 [DISP_CC_MDSS_BYTE1_CLK] = &disp0_cc_mdss_byte1_clk.clkr, 2885 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp0_cc_mdss_byte1_clk_src.clkr, 2886 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp0_cc_mdss_byte1_div_clk_src.clkr, 2887 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp0_cc_mdss_byte1_intf_clk.clkr, 2888 [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp0_cc_mdss_dptx0_aux_clk.clkr, 2889 [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp0_cc_mdss_dptx0_aux_clk_src.clkr, 2890 [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp0_cc_mdss_dptx0_link_clk.clkr, 2891 [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp0_cc_mdss_dptx0_link_clk_src.clkr, 2892 [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp0_cc_mdss_dptx0_link_div_clk_src.clkr, 2893 [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp0_cc_mdss_dptx0_link_intf_clk.clkr, 2894 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp0_cc_mdss_dptx0_pixel0_clk.clkr, 2895 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp0_cc_mdss_dptx0_pixel0_clk_src.clkr, 2896 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp0_cc_mdss_dptx0_pixel1_clk.clkr, 2897 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp0_cc_mdss_dptx0_pixel1_clk_src.clkr, 2898 [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = &disp0_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, 2899 [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp0_cc_mdss_dptx1_aux_clk.clkr, 2900 [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp0_cc_mdss_dptx1_aux_clk_src.clkr, 2901 [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp0_cc_mdss_dptx1_link_clk.clkr, 2902 [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp0_cc_mdss_dptx1_link_clk_src.clkr, 2903 [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp0_cc_mdss_dptx1_link_div_clk_src.clkr, 2904 [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp0_cc_mdss_dptx1_link_intf_clk.clkr, 2905 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp0_cc_mdss_dptx1_pixel0_clk.clkr, 2906 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp0_cc_mdss_dptx1_pixel0_clk_src.clkr, 2907 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp0_cc_mdss_dptx1_pixel1_clk.clkr, 2908 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp0_cc_mdss_dptx1_pixel1_clk_src.clkr, 2909 [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] = &disp0_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, 2910 [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp0_cc_mdss_dptx2_aux_clk.clkr, 2911 [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp0_cc_mdss_dptx2_aux_clk_src.clkr, 2912 [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp0_cc_mdss_dptx2_link_clk.clkr, 2913 [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp0_cc_mdss_dptx2_link_clk_src.clkr, 2914 [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp0_cc_mdss_dptx2_link_div_clk_src.clkr, 2915 [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp0_cc_mdss_dptx2_link_intf_clk.clkr, 2916 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp0_cc_mdss_dptx2_pixel0_clk.clkr, 2917 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp0_cc_mdss_dptx2_pixel0_clk_src.clkr, 2918 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp0_cc_mdss_dptx2_pixel1_clk.clkr, 2919 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp0_cc_mdss_dptx2_pixel1_clk_src.clkr, 2920 [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp0_cc_mdss_dptx3_aux_clk.clkr, 2921 [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp0_cc_mdss_dptx3_aux_clk_src.clkr, 2922 [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp0_cc_mdss_dptx3_link_clk.clkr, 2923 [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp0_cc_mdss_dptx3_link_clk_src.clkr, 2924 [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp0_cc_mdss_dptx3_link_div_clk_src.clkr, 2925 [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp0_cc_mdss_dptx3_link_intf_clk.clkr, 2926 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp0_cc_mdss_dptx3_pixel0_clk.clkr, 2927 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp0_cc_mdss_dptx3_pixel0_clk_src.clkr, 2928 [DISP_CC_MDSS_ESC0_CLK] = &disp0_cc_mdss_esc0_clk.clkr, 2929 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp0_cc_mdss_esc0_clk_src.clkr, 2930 [DISP_CC_MDSS_ESC1_CLK] = &disp0_cc_mdss_esc1_clk.clkr, 2931 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp0_cc_mdss_esc1_clk_src.clkr, 2932 [DISP_CC_MDSS_MDP1_CLK] = &disp0_cc_mdss_mdp1_clk.clkr, 2933 [DISP_CC_MDSS_MDP_CLK] = &disp0_cc_mdss_mdp_clk.clkr, 2934 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp0_cc_mdss_mdp_clk_src.clkr, 2935 [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp0_cc_mdss_mdp_lut1_clk.clkr, 2936 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp0_cc_mdss_mdp_lut_clk.clkr, 2937 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp0_cc_mdss_non_gdsc_ahb_clk.clkr, 2938 [DISP_CC_MDSS_PCLK0_CLK] = &disp0_cc_mdss_pclk0_clk.clkr, 2939 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp0_cc_mdss_pclk0_clk_src.clkr, 2940 [DISP_CC_MDSS_PCLK1_CLK] = &disp0_cc_mdss_pclk1_clk.clkr, 2941 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp0_cc_mdss_pclk1_clk_src.clkr, 2942 [DISP_CC_MDSS_ROT1_CLK] = &disp0_cc_mdss_rot1_clk.clkr, 2943 [DISP_CC_MDSS_ROT_CLK] = &disp0_cc_mdss_rot_clk.clkr, 2944 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp0_cc_mdss_rot_clk_src.clkr, 2945 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp0_cc_mdss_rscc_ahb_clk.clkr, 2946 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp0_cc_mdss_rscc_vsync_clk.clkr, 2947 [DISP_CC_MDSS_VSYNC1_CLK] = &disp0_cc_mdss_vsync1_clk.clkr, 2948 [DISP_CC_MDSS_VSYNC_CLK] = &disp0_cc_mdss_vsync_clk.clkr, 2949 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp0_cc_mdss_vsync_clk_src.clkr, 2950 [DISP_CC_PLL0] = &disp0_cc_pll0.clkr, 2951 [DISP_CC_PLL1] = &disp0_cc_pll1.clkr, 2952 [DISP_CC_PLL1_OUT_EVEN] = &disp0_cc_pll1_out_even.clkr, 2953 [DISP_CC_PLL2] = &disp0_cc_pll2.clkr, 2954 [DISP_CC_SLEEP_CLK] = &disp0_cc_sleep_clk.clkr, 2955 [DISP_CC_SLEEP_CLK_SRC] = &disp0_cc_sleep_clk_src.clkr, 2956 }; 2957 2958 static struct clk_regmap *disp1_cc_sc8280xp_clocks[] = { 2959 [DISP_CC_MDSS_AHB1_CLK] = &disp1_cc_mdss_ahb1_clk.clkr, 2960 [DISP_CC_MDSS_AHB_CLK] = &disp1_cc_mdss_ahb_clk.clkr, 2961 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp1_cc_mdss_ahb_clk_src.clkr, 2962 [DISP_CC_MDSS_BYTE0_CLK] = &disp1_cc_mdss_byte0_clk.clkr, 2963 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp1_cc_mdss_byte0_clk_src.clkr, 2964 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp1_cc_mdss_byte0_div_clk_src.clkr, 2965 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp1_cc_mdss_byte0_intf_clk.clkr, 2966 [DISP_CC_MDSS_BYTE1_CLK] = &disp1_cc_mdss_byte1_clk.clkr, 2967 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp1_cc_mdss_byte1_clk_src.clkr, 2968 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp1_cc_mdss_byte1_div_clk_src.clkr, 2969 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp1_cc_mdss_byte1_intf_clk.clkr, 2970 [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp1_cc_mdss_dptx0_aux_clk.clkr, 2971 [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp1_cc_mdss_dptx0_aux_clk_src.clkr, 2972 [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp1_cc_mdss_dptx0_link_clk.clkr, 2973 [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp1_cc_mdss_dptx0_link_clk_src.clkr, 2974 [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp1_cc_mdss_dptx0_link_div_clk_src.clkr, 2975 [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp1_cc_mdss_dptx0_link_intf_clk.clkr, 2976 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp1_cc_mdss_dptx0_pixel0_clk.clkr, 2977 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp1_cc_mdss_dptx0_pixel0_clk_src.clkr, 2978 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp1_cc_mdss_dptx0_pixel1_clk.clkr, 2979 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp1_cc_mdss_dptx0_pixel1_clk_src.clkr, 2980 [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = &disp1_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, 2981 [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp1_cc_mdss_dptx1_aux_clk.clkr, 2982 [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp1_cc_mdss_dptx1_aux_clk_src.clkr, 2983 [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp1_cc_mdss_dptx1_link_clk.clkr, 2984 [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp1_cc_mdss_dptx1_link_clk_src.clkr, 2985 [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp1_cc_mdss_dptx1_link_div_clk_src.clkr, 2986 [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp1_cc_mdss_dptx1_link_intf_clk.clkr, 2987 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp1_cc_mdss_dptx1_pixel0_clk.clkr, 2988 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp1_cc_mdss_dptx1_pixel0_clk_src.clkr, 2989 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp1_cc_mdss_dptx1_pixel1_clk.clkr, 2990 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp1_cc_mdss_dptx1_pixel1_clk_src.clkr, 2991 [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] = &disp1_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, 2992 [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp1_cc_mdss_dptx2_aux_clk.clkr, 2993 [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp1_cc_mdss_dptx2_aux_clk_src.clkr, 2994 [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp1_cc_mdss_dptx2_link_clk.clkr, 2995 [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp1_cc_mdss_dptx2_link_clk_src.clkr, 2996 [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp1_cc_mdss_dptx2_link_div_clk_src.clkr, 2997 [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp1_cc_mdss_dptx2_link_intf_clk.clkr, 2998 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp1_cc_mdss_dptx2_pixel0_clk.clkr, 2999 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp1_cc_mdss_dptx2_pixel0_clk_src.clkr, 3000 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp1_cc_mdss_dptx2_pixel1_clk.clkr, 3001 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp1_cc_mdss_dptx2_pixel1_clk_src.clkr, 3002 [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp1_cc_mdss_dptx3_aux_clk.clkr, 3003 [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp1_cc_mdss_dptx3_aux_clk_src.clkr, 3004 [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp1_cc_mdss_dptx3_link_clk.clkr, 3005 [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp1_cc_mdss_dptx3_link_clk_src.clkr, 3006 [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp1_cc_mdss_dptx3_link_div_clk_src.clkr, 3007 [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp1_cc_mdss_dptx3_link_intf_clk.clkr, 3008 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp1_cc_mdss_dptx3_pixel0_clk.clkr, 3009 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp1_cc_mdss_dptx3_pixel0_clk_src.clkr, 3010 [DISP_CC_MDSS_ESC0_CLK] = &disp1_cc_mdss_esc0_clk.clkr, 3011 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp1_cc_mdss_esc0_clk_src.clkr, 3012 [DISP_CC_MDSS_ESC1_CLK] = &disp1_cc_mdss_esc1_clk.clkr, 3013 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp1_cc_mdss_esc1_clk_src.clkr, 3014 [DISP_CC_MDSS_MDP1_CLK] = &disp1_cc_mdss_mdp1_clk.clkr, 3015 [DISP_CC_MDSS_MDP_CLK] = &disp1_cc_mdss_mdp_clk.clkr, 3016 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp1_cc_mdss_mdp_clk_src.clkr, 3017 [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp1_cc_mdss_mdp_lut1_clk.clkr, 3018 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp1_cc_mdss_mdp_lut_clk.clkr, 3019 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp1_cc_mdss_non_gdsc_ahb_clk.clkr, 3020 [DISP_CC_MDSS_PCLK0_CLK] = &disp1_cc_mdss_pclk0_clk.clkr, 3021 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp1_cc_mdss_pclk0_clk_src.clkr, 3022 [DISP_CC_MDSS_PCLK1_CLK] = &disp1_cc_mdss_pclk1_clk.clkr, 3023 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp1_cc_mdss_pclk1_clk_src.clkr, 3024 [DISP_CC_MDSS_ROT1_CLK] = &disp1_cc_mdss_rot1_clk.clkr, 3025 [DISP_CC_MDSS_ROT_CLK] = &disp1_cc_mdss_rot_clk.clkr, 3026 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp1_cc_mdss_rot_clk_src.clkr, 3027 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp1_cc_mdss_rscc_ahb_clk.clkr, 3028 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp1_cc_mdss_rscc_vsync_clk.clkr, 3029 [DISP_CC_MDSS_VSYNC1_CLK] = &disp1_cc_mdss_vsync1_clk.clkr, 3030 [DISP_CC_MDSS_VSYNC_CLK] = &disp1_cc_mdss_vsync_clk.clkr, 3031 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp1_cc_mdss_vsync_clk_src.clkr, 3032 [DISP_CC_PLL0] = &disp1_cc_pll0.clkr, 3033 [DISP_CC_PLL1] = &disp1_cc_pll1.clkr, 3034 [DISP_CC_PLL1_OUT_EVEN] = &disp1_cc_pll1_out_even.clkr, 3035 [DISP_CC_PLL2] = &disp1_cc_pll2.clkr, 3036 [DISP_CC_SLEEP_CLK] = &disp1_cc_sleep_clk.clkr, 3037 [DISP_CC_SLEEP_CLK_SRC] = &disp1_cc_sleep_clk_src.clkr, 3038 }; 3039 3040 static const struct qcom_reset_map disp_cc_sc8280xp_resets[] = { 3041 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 }, 3042 [DISP_CC_MDSS_RSCC_BCR] = { 0x4000 }, 3043 }; 3044 3045 static struct gdsc disp0_mdss_gdsc = { 3046 .gdscr = 0x3000, 3047 .en_rest_wait_val = 0x2, 3048 .en_few_wait_val = 0x2, 3049 .clk_dis_wait_val = 0xf, 3050 .pd = { 3051 .name = "disp0_mdss_gdsc", 3052 }, 3053 .pwrsts = PWRSTS_OFF_ON, 3054 .flags = HW_CTRL | RETAIN_FF_ENABLE, 3055 }; 3056 3057 static struct gdsc disp1_mdss_gdsc = { 3058 .gdscr = 0x3000, 3059 .en_rest_wait_val = 0x2, 3060 .en_few_wait_val = 0x2, 3061 .clk_dis_wait_val = 0xf, 3062 .pd = { 3063 .name = "disp1_mdss_gdsc", 3064 }, 3065 .pwrsts = PWRSTS_OFF_ON, 3066 .flags = HW_CTRL | RETAIN_FF_ENABLE, 3067 }; 3068 3069 static struct gdsc disp0_mdss_int2_gdsc = { 3070 .gdscr = 0xa000, 3071 .en_rest_wait_val = 0x2, 3072 .en_few_wait_val = 0x2, 3073 .clk_dis_wait_val = 0xf, 3074 .pd = { 3075 .name = "disp0_mdss_int2_gdsc", 3076 }, 3077 .pwrsts = PWRSTS_OFF_ON, 3078 .flags = HW_CTRL | RETAIN_FF_ENABLE, 3079 }; 3080 3081 static struct gdsc disp1_mdss_int2_gdsc = { 3082 .gdscr = 0xa000, 3083 .en_rest_wait_val = 0x2, 3084 .en_few_wait_val = 0x2, 3085 .clk_dis_wait_val = 0xf, 3086 .pd = { 3087 .name = "disp1_mdss_int2_gdsc", 3088 }, 3089 .pwrsts = PWRSTS_OFF_ON, 3090 .flags = HW_CTRL | RETAIN_FF_ENABLE, 3091 }; 3092 3093 static struct gdsc *disp0_cc_sc8280xp_gdscs[] = { 3094 [MDSS_GDSC] = &disp0_mdss_gdsc, 3095 [MDSS_INT2_GDSC] = &disp0_mdss_int2_gdsc, 3096 }; 3097 3098 static struct gdsc *disp1_cc_sc8280xp_gdscs[] = { 3099 [MDSS_GDSC] = &disp1_mdss_gdsc, 3100 [MDSS_INT2_GDSC] = &disp1_mdss_int2_gdsc, 3101 }; 3102 3103 static const struct regmap_config disp_cc_sc8280xp_regmap_config = { 3104 .reg_bits = 32, 3105 .reg_stride = 4, 3106 .val_bits = 32, 3107 .max_register = 0x10000, 3108 .fast_io = true, 3109 }; 3110 3111 static const struct qcom_cc_desc disp0_cc_sc8280xp_desc = { 3112 .config = &disp_cc_sc8280xp_regmap_config, 3113 .clks = disp0_cc_sc8280xp_clocks, 3114 .num_clks = ARRAY_SIZE(disp0_cc_sc8280xp_clocks), 3115 .resets = disp_cc_sc8280xp_resets, 3116 .num_resets = ARRAY_SIZE(disp_cc_sc8280xp_resets), 3117 .gdscs = disp0_cc_sc8280xp_gdscs, 3118 .num_gdscs = ARRAY_SIZE(disp0_cc_sc8280xp_gdscs), 3119 }; 3120 3121 static const struct qcom_cc_desc disp1_cc_sc8280xp_desc = { 3122 .config = &disp_cc_sc8280xp_regmap_config, 3123 .clks = disp1_cc_sc8280xp_clocks, 3124 .num_clks = ARRAY_SIZE(disp1_cc_sc8280xp_clocks), 3125 .resets = disp_cc_sc8280xp_resets, 3126 .num_resets = ARRAY_SIZE(disp_cc_sc8280xp_resets), 3127 .gdscs = disp1_cc_sc8280xp_gdscs, 3128 .num_gdscs = ARRAY_SIZE(disp1_cc_sc8280xp_gdscs), 3129 }; 3130 3131 #define clkr_to_alpha_clk_pll(_clkr) container_of(_clkr, struct clk_alpha_pll, clkr) 3132 3133 static int disp_cc_sc8280xp_probe(struct platform_device *pdev) 3134 { 3135 const struct qcom_cc_desc *desc; 3136 struct regmap *regmap; 3137 int ret; 3138 3139 desc = device_get_match_data(&pdev->dev); 3140 3141 ret = devm_pm_runtime_enable(&pdev->dev); 3142 if (ret) 3143 return ret; 3144 3145 ret = devm_pm_clk_create(&pdev->dev); 3146 if (ret) 3147 return ret; 3148 3149 ret = pm_clk_add(&pdev->dev, NULL); 3150 if (ret < 0) { 3151 dev_err(&pdev->dev, "failed to acquire ahb clock\n"); 3152 return ret; 3153 } 3154 3155 ret = pm_runtime_resume_and_get(&pdev->dev); 3156 if (ret) 3157 return ret; 3158 3159 regmap = qcom_cc_map(pdev, desc); 3160 if (IS_ERR(regmap)) { 3161 ret = PTR_ERR(regmap); 3162 goto out_pm_runtime_put; 3163 } 3164 3165 clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL0]), regmap, &disp_cc_pll0_config); 3166 clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL1]), regmap, &disp_cc_pll1_config); 3167 clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL2]), regmap, &disp_cc_pll2_config); 3168 3169 ret = qcom_cc_really_probe(&pdev->dev, desc, regmap); 3170 if (ret) { 3171 dev_err(&pdev->dev, "Failed to register display clock controller\n"); 3172 goto out_pm_runtime_put; 3173 } 3174 3175 /* Keep some clocks always-on */ 3176 qcom_branch_set_clk_en(regmap, 0x605c); /* DISP_CC_XO_CLK */ 3177 3178 out_pm_runtime_put: 3179 pm_runtime_put_sync(&pdev->dev); 3180 3181 return ret; 3182 } 3183 3184 static const struct of_device_id disp_cc_sc8280xp_match_table[] = { 3185 { .compatible = "qcom,sc8280xp-dispcc0", .data = &disp0_cc_sc8280xp_desc }, 3186 { .compatible = "qcom,sc8280xp-dispcc1", .data = &disp1_cc_sc8280xp_desc }, 3187 { } 3188 }; 3189 MODULE_DEVICE_TABLE(of, disp_cc_sc8280xp_match_table); 3190 3191 static struct platform_driver disp_cc_sc8280xp_driver = { 3192 .probe = disp_cc_sc8280xp_probe, 3193 .driver = { 3194 .name = "disp_cc-sc8280xp", 3195 .of_match_table = disp_cc_sc8280xp_match_table, 3196 }, 3197 }; 3198 3199 module_platform_driver(disp_cc_sc8280xp_driver); 3200 3201 MODULE_DESCRIPTION("Qualcomm SC8280XP dispcc driver"); 3202 MODULE_LICENSE("GPL"); 3203