1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Ltd. 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/mod_devicetable.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/pm_clock.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 15 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> 16 17 #include "clk-alpha-pll.h" 18 #include "clk-branch.h" 19 #include "clk-rcg.h" 20 #include "clk-regmap-divider.h" 21 #include "common.h" 22 #include "gdsc.h" 23 #include "reset.h" 24 25 /* Need to match the order of clocks in DT binding */ 26 enum { 27 DT_IFACE, 28 DT_BI_TCXO, 29 DT_SLEEP_CLK, 30 DT_DP0_PHY_PLL_LINK_CLK, 31 DT_DP0_PHY_PLL_VCO_DIV_CLK, 32 DT_DP1_PHY_PLL_LINK_CLK, 33 DT_DP1_PHY_PLL_VCO_DIV_CLK, 34 DT_DP2_PHY_PLL_LINK_CLK, 35 DT_DP2_PHY_PLL_VCO_DIV_CLK, 36 DT_DP3_PHY_PLL_LINK_CLK, 37 DT_DP3_PHY_PLL_VCO_DIV_CLK, 38 DT_DSI0_PHY_PLL_OUT_BYTECLK, 39 DT_DSI0_PHY_PLL_OUT_DSICLK, 40 DT_DSI1_PHY_PLL_OUT_BYTECLK, 41 DT_DSI1_PHY_PLL_OUT_DSICLK, 42 }; 43 44 enum { 45 P_BI_TCXO, 46 P_DP0_PHY_PLL_LINK_CLK, 47 P_DP0_PHY_PLL_VCO_DIV_CLK, 48 P_DP1_PHY_PLL_LINK_CLK, 49 P_DP1_PHY_PLL_VCO_DIV_CLK, 50 P_DP2_PHY_PLL_LINK_CLK, 51 P_DP2_PHY_PLL_VCO_DIV_CLK, 52 P_DP3_PHY_PLL_LINK_CLK, 53 P_DP3_PHY_PLL_VCO_DIV_CLK, 54 P_DSI0_PHY_PLL_OUT_BYTECLK, 55 P_DSI0_PHY_PLL_OUT_DSICLK, 56 P_DSI1_PHY_PLL_OUT_BYTECLK, 57 P_DSI1_PHY_PLL_OUT_DSICLK, 58 P_DISPn_CC_PLL0_OUT_MAIN, 59 P_DISPn_CC_PLL1_OUT_EVEN, 60 P_DISPn_CC_PLL1_OUT_MAIN, 61 P_DISPn_CC_PLL2_OUT_MAIN, 62 P_SLEEP_CLK, 63 }; 64 65 static const struct clk_parent_data parent_data_tcxo = { .index = DT_BI_TCXO }; 66 67 static const struct pll_vco lucid_5lpe_vco[] = { 68 { 249600000, 1800000000, 0 }, 69 }; 70 71 static const struct alpha_pll_config disp_cc_pll0_config = { 72 .l = 0x4e, 73 .alpha = 0x2000, 74 .config_ctl_val = 0x20485699, 75 .config_ctl_hi_val = 0x00002261, 76 .config_ctl_hi1_val = 0x2a9a699c, 77 .test_ctl_val = 0x00000000, 78 .test_ctl_hi_val = 0x00000000, 79 .test_ctl_hi1_val = 0x01800000, 80 .user_ctl_val = 0x00000000, 81 .user_ctl_hi_val = 0x00000805, 82 .user_ctl_hi1_val = 0x00000000, 83 }; 84 85 static struct clk_alpha_pll disp0_cc_pll0 = { 86 .offset = 0x0, 87 .vco_table = lucid_5lpe_vco, 88 .num_vco = ARRAY_SIZE(lucid_5lpe_vco), 89 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 90 .clkr = { 91 .hw.init = &(const struct clk_init_data) { 92 .name = "disp0_cc_pll0", 93 .parent_data = &parent_data_tcxo, 94 .num_parents = 1, 95 .ops = &clk_alpha_pll_lucid_5lpe_ops, 96 }, 97 }, 98 }; 99 100 static struct clk_alpha_pll disp1_cc_pll0 = { 101 .offset = 0x0, 102 .vco_table = lucid_5lpe_vco, 103 .num_vco = ARRAY_SIZE(lucid_5lpe_vco), 104 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 105 .clkr = { 106 .hw.init = &(const struct clk_init_data) { 107 .name = "disp1_cc_pll0", 108 .parent_data = &parent_data_tcxo, 109 .num_parents = 1, 110 .ops = &clk_alpha_pll_lucid_5lpe_ops, 111 }, 112 }, 113 }; 114 115 static const struct alpha_pll_config disp_cc_pll1_config = { 116 .l = 0x1f, 117 .alpha = 0x4000, 118 .config_ctl_val = 0x20485699, 119 .config_ctl_hi_val = 0x00002261, 120 .config_ctl_hi1_val = 0x2a9a699c, 121 .test_ctl_val = 0x00000000, 122 .test_ctl_hi_val = 0x00000000, 123 .test_ctl_hi1_val = 0x01800000, 124 .user_ctl_val = 0x00000100, 125 .user_ctl_hi_val = 0x00000805, 126 .user_ctl_hi1_val = 0x00000000, 127 }; 128 129 static struct clk_alpha_pll disp0_cc_pll1 = { 130 .offset = 0x1000, 131 .vco_table = lucid_5lpe_vco, 132 .num_vco = ARRAY_SIZE(lucid_5lpe_vco), 133 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 134 .clkr = { 135 .hw.init = &(const struct clk_init_data) { 136 .name = "disp0_cc_pll1", 137 .parent_data = &parent_data_tcxo, 138 .num_parents = 1, 139 .ops = &clk_alpha_pll_lucid_5lpe_ops, 140 }, 141 }, 142 }; 143 144 static struct clk_alpha_pll disp1_cc_pll1 = { 145 .offset = 0x1000, 146 .vco_table = lucid_5lpe_vco, 147 .num_vco = ARRAY_SIZE(lucid_5lpe_vco), 148 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 149 .clkr = { 150 .hw.init = &(const struct clk_init_data) { 151 .name = "disp1_cc_pll1", 152 .parent_data = &parent_data_tcxo, 153 .num_parents = 1, 154 .ops = &clk_alpha_pll_lucid_5lpe_ops, 155 }, 156 }, 157 }; 158 159 static const struct clk_div_table post_div_table_disp_cc_pll1_out_even[] = { 160 { 0x1, 2 }, 161 { } 162 }; 163 164 static struct clk_alpha_pll_postdiv disp0_cc_pll1_out_even = { 165 .offset = 0x1000, 166 .post_div_shift = 8, 167 .post_div_table = post_div_table_disp_cc_pll1_out_even, 168 .num_post_div = ARRAY_SIZE(post_div_table_disp_cc_pll1_out_even), 169 .width = 4, 170 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 171 .clkr.hw.init = &(const struct clk_init_data) { 172 .name = "disp0_cc_pll1_out_even", 173 .parent_hws = (const struct clk_hw*[]){ 174 &disp0_cc_pll1.clkr.hw, 175 }, 176 .num_parents = 1, 177 .ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops, 178 }, 179 }; 180 181 static struct clk_alpha_pll_postdiv disp1_cc_pll1_out_even = { 182 .offset = 0x1000, 183 .post_div_shift = 8, 184 .post_div_table = post_div_table_disp_cc_pll1_out_even, 185 .num_post_div = ARRAY_SIZE(post_div_table_disp_cc_pll1_out_even), 186 .width = 4, 187 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 188 .clkr.hw.init = &(const struct clk_init_data) { 189 .name = "disp1_cc_pll1_out_even", 190 .parent_hws = (const struct clk_hw*[]){ 191 &disp1_cc_pll1.clkr.hw, 192 }, 193 .num_parents = 1, 194 .ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops, 195 }, 196 }; 197 198 static const struct alpha_pll_config disp_cc_pll2_config = { 199 .l = 0x46, 200 .alpha = 0x5000, 201 .config_ctl_val = 0x20485699, 202 .config_ctl_hi_val = 0x00002261, 203 .config_ctl_hi1_val = 0x2a9a699c, 204 .test_ctl_val = 0x00000000, 205 .test_ctl_hi_val = 0x00000000, 206 .test_ctl_hi1_val = 0x01800000, 207 .user_ctl_val = 0x00000000, 208 .user_ctl_hi_val = 0x00000805, 209 .user_ctl_hi1_val = 0x00000000, 210 }; 211 212 static struct clk_alpha_pll disp0_cc_pll2 = { 213 .offset = 0x9000, 214 .vco_table = lucid_5lpe_vco, 215 .num_vco = ARRAY_SIZE(lucid_5lpe_vco), 216 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 217 .clkr = { 218 .hw.init = &(const struct clk_init_data) { 219 .name = "disp0_cc_pll2", 220 .parent_data = &parent_data_tcxo, 221 .num_parents = 1, 222 .ops = &clk_alpha_pll_lucid_5lpe_ops, 223 }, 224 }, 225 }; 226 227 static struct clk_alpha_pll disp1_cc_pll2 = { 228 .offset = 0x9000, 229 .vco_table = lucid_5lpe_vco, 230 .num_vco = ARRAY_SIZE(lucid_5lpe_vco), 231 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 232 .clkr = { 233 .hw.init = &(const struct clk_init_data) { 234 .name = "disp1_cc_pll2", 235 .parent_data = &parent_data_tcxo, 236 .num_parents = 1, 237 .ops = &clk_alpha_pll_lucid_5lpe_ops, 238 }, 239 }, 240 }; 241 242 static const struct parent_map disp_cc_parent_map_0[] = { 243 { P_BI_TCXO, 0 }, 244 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 245 { P_DP1_PHY_PLL_LINK_CLK, 2 }, 246 { P_DP2_PHY_PLL_LINK_CLK, 3 }, 247 { P_DP3_PHY_PLL_LINK_CLK, 4 }, 248 { P_DISPn_CC_PLL2_OUT_MAIN, 5 }, 249 }; 250 251 static const struct clk_parent_data disp0_cc_parent_data_0[] = { 252 { .index = DT_BI_TCXO }, 253 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 254 { .index = DT_DP1_PHY_PLL_LINK_CLK }, 255 { .index = DT_DP2_PHY_PLL_LINK_CLK }, 256 { .index = DT_DP3_PHY_PLL_LINK_CLK }, 257 { .hw = &disp0_cc_pll2.clkr.hw }, 258 }; 259 260 static const struct clk_parent_data disp1_cc_parent_data_0[] = { 261 { .index = DT_BI_TCXO }, 262 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 263 { .index = DT_DP1_PHY_PLL_LINK_CLK }, 264 { .index = DT_DP2_PHY_PLL_LINK_CLK }, 265 { .index = DT_DP3_PHY_PLL_LINK_CLK }, 266 { .hw = &disp1_cc_pll2.clkr.hw }, 267 }; 268 269 static const struct parent_map disp_cc_parent_map_1[] = { 270 { P_BI_TCXO, 0 }, 271 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 272 { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 }, 273 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, 274 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, 275 { P_DISPn_CC_PLL2_OUT_MAIN, 5 }, 276 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, 277 }; 278 279 static const struct clk_parent_data disp0_cc_parent_data_1[] = { 280 { .index = DT_BI_TCXO }, 281 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 282 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK }, 283 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 284 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 285 { .hw = &disp0_cc_pll2.clkr.hw }, 286 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 287 }; 288 289 static const struct clk_parent_data disp1_cc_parent_data_1[] = { 290 { .index = DT_BI_TCXO }, 291 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 292 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK }, 293 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 294 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 295 { .hw = &disp1_cc_pll2.clkr.hw }, 296 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 297 }; 298 299 static const struct parent_map disp_cc_parent_map_2[] = { 300 { P_BI_TCXO, 0 }, 301 }; 302 303 static const struct clk_parent_data disp_cc_parent_data_2[] = { 304 { .index = DT_BI_TCXO }, 305 }; 306 307 static const struct parent_map disp_cc_parent_map_3[] = { 308 { P_BI_TCXO, 0 }, 309 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 310 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 311 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, 312 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 313 }; 314 315 static const struct clk_parent_data disp_cc_parent_data_3[] = { 316 { .index = DT_BI_TCXO }, 317 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, 318 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 319 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, 320 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 321 }; 322 323 static const struct parent_map disp_cc_parent_map_4[] = { 324 { P_BI_TCXO, 0 }, 325 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 326 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 327 }; 328 329 static const struct clk_parent_data disp_cc_parent_data_4[] = { 330 { .index = DT_BI_TCXO }, 331 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 332 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 333 }; 334 335 static const struct parent_map disp_cc_parent_map_5[] = { 336 { P_BI_TCXO, 0 }, 337 { P_DISPn_CC_PLL0_OUT_MAIN, 1 }, 338 { P_DISPn_CC_PLL1_OUT_MAIN, 4 }, 339 { P_DISPn_CC_PLL2_OUT_MAIN, 5 }, 340 { P_DISPn_CC_PLL1_OUT_EVEN, 6 }, 341 }; 342 343 static const struct clk_parent_data disp0_cc_parent_data_5[] = { 344 { .index = DT_BI_TCXO }, 345 { .hw = &disp0_cc_pll0.clkr.hw }, 346 { .hw = &disp0_cc_pll1.clkr.hw }, 347 { .hw = &disp0_cc_pll2.clkr.hw }, 348 { .hw = &disp0_cc_pll1_out_even.clkr.hw }, 349 }; 350 351 static const struct clk_parent_data disp1_cc_parent_data_5[] = { 352 { .index = DT_BI_TCXO }, 353 { .hw = &disp1_cc_pll0.clkr.hw }, 354 { .hw = &disp1_cc_pll1.clkr.hw }, 355 { .hw = &disp1_cc_pll2.clkr.hw }, 356 { .hw = &disp1_cc_pll1_out_even.clkr.hw }, 357 }; 358 359 static const struct parent_map disp_cc_parent_map_6[] = { 360 { P_BI_TCXO, 0 }, 361 { P_DISPn_CC_PLL1_OUT_MAIN, 4 }, 362 { P_DISPn_CC_PLL1_OUT_EVEN, 6 }, 363 }; 364 365 static const struct clk_parent_data disp0_cc_parent_data_6[] = { 366 { .index = DT_BI_TCXO }, 367 { .hw = &disp0_cc_pll1.clkr.hw }, 368 { .hw = &disp0_cc_pll1_out_even.clkr.hw }, 369 }; 370 371 static const struct clk_parent_data disp1_cc_parent_data_6[] = { 372 { .index = DT_BI_TCXO }, 373 { .hw = &disp1_cc_pll1.clkr.hw }, 374 { .hw = &disp1_cc_pll1_out_even.clkr.hw }, 375 }; 376 377 static const struct parent_map disp_cc_parent_map_7[] = { 378 { P_SLEEP_CLK, 0 }, 379 }; 380 381 static const struct clk_parent_data disp_cc_parent_data_7[] = { 382 { .index = DT_SLEEP_CLK }, 383 }; 384 385 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { 386 F(19200000, P_BI_TCXO, 1, 0, 0), 387 F(37500000, P_DISPn_CC_PLL1_OUT_EVEN, 8, 0, 0), 388 F(75000000, P_DISPn_CC_PLL1_OUT_MAIN, 8, 0, 0), 389 { } 390 }; 391 392 static struct clk_rcg2 disp0_cc_mdss_ahb_clk_src = { 393 .cmd_rcgr = 0x2364, 394 .mnd_width = 0, 395 .hid_width = 5, 396 .parent_map = disp_cc_parent_map_6, 397 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 398 .clkr.hw.init = &(const struct clk_init_data) { 399 .name = "disp0_cc_mdss_ahb_clk_src", 400 .parent_data = disp0_cc_parent_data_6, 401 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_6), 402 .ops = &clk_rcg2_shared_ops, 403 }, 404 }; 405 406 static struct clk_rcg2 disp1_cc_mdss_ahb_clk_src = { 407 .cmd_rcgr = 0x2364, 408 .mnd_width = 0, 409 .hid_width = 5, 410 .parent_map = disp_cc_parent_map_6, 411 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 412 .clkr.hw.init = &(const struct clk_init_data) { 413 .name = "disp1_cc_mdss_ahb_clk_src", 414 .parent_data = disp1_cc_parent_data_6, 415 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_6), 416 .ops = &clk_rcg2_shared_ops, 417 }, 418 }; 419 420 static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = { 421 F(19200000, P_BI_TCXO, 1, 0, 0), 422 { } 423 }; 424 425 static struct clk_rcg2 disp0_cc_mdss_byte0_clk_src = { 426 .cmd_rcgr = 0x213c, 427 .mnd_width = 0, 428 .hid_width = 5, 429 .parent_map = disp_cc_parent_map_3, 430 .clkr.hw.init = &(const struct clk_init_data) { 431 .name = "disp0_cc_mdss_byte0_clk_src", 432 .parent_data = disp_cc_parent_data_3, 433 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 434 .flags = CLK_SET_RATE_PARENT, 435 .ops = &clk_byte2_ops, 436 }, 437 }; 438 439 static struct clk_rcg2 disp1_cc_mdss_byte0_clk_src = { 440 .cmd_rcgr = 0x213c, 441 .mnd_width = 0, 442 .hid_width = 5, 443 .parent_map = disp_cc_parent_map_3, 444 .clkr.hw.init = &(const struct clk_init_data) { 445 .name = "disp1_cc_mdss_byte0_clk_src", 446 .parent_data = disp_cc_parent_data_3, 447 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 448 .flags = CLK_SET_RATE_PARENT, 449 .ops = &clk_byte2_ops, 450 }, 451 }; 452 453 static struct clk_rcg2 disp0_cc_mdss_byte1_clk_src = { 454 .cmd_rcgr = 0x2158, 455 .mnd_width = 0, 456 .hid_width = 5, 457 .parent_map = disp_cc_parent_map_3, 458 .clkr.hw.init = &(const struct clk_init_data) { 459 .name = "disp0_cc_mdss_byte1_clk_src", 460 .parent_data = disp_cc_parent_data_3, 461 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 462 .flags = CLK_SET_RATE_PARENT, 463 .ops = &clk_byte2_ops, 464 }, 465 }; 466 467 static struct clk_rcg2 disp1_cc_mdss_byte1_clk_src = { 468 .cmd_rcgr = 0x2158, 469 .mnd_width = 0, 470 .hid_width = 5, 471 .parent_map = disp_cc_parent_map_3, 472 .clkr.hw.init = &(const struct clk_init_data) { 473 .name = "disp1_cc_mdss_byte1_clk_src", 474 .parent_data = disp_cc_parent_data_3, 475 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 476 .flags = CLK_SET_RATE_PARENT, 477 .ops = &clk_byte2_ops, 478 }, 479 }; 480 481 static struct clk_rcg2 disp0_cc_mdss_dptx0_aux_clk_src = { 482 .cmd_rcgr = 0x2238, 483 .mnd_width = 0, 484 .hid_width = 5, 485 .parent_map = disp_cc_parent_map_2, 486 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 487 .clkr.hw.init = &(const struct clk_init_data) { 488 .name = "disp0_cc_mdss_dptx0_aux_clk_src", 489 .parent_data = disp_cc_parent_data_2, 490 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 491 .ops = &clk_rcg2_ops, 492 }, 493 }; 494 495 static struct clk_rcg2 disp1_cc_mdss_dptx0_aux_clk_src = { 496 .cmd_rcgr = 0x2238, 497 .mnd_width = 0, 498 .hid_width = 5, 499 .parent_map = disp_cc_parent_map_2, 500 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 501 .clkr.hw.init = &(const struct clk_init_data) { 502 .name = "disp1_cc_mdss_dptx0_aux_clk_src", 503 .parent_data = disp_cc_parent_data_2, 504 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 505 .ops = &clk_rcg2_ops, 506 }, 507 }; 508 509 static struct clk_rcg2 disp0_cc_mdss_dptx0_link_clk_src = { 510 .cmd_rcgr = 0x21a4, 511 .mnd_width = 0, 512 .hid_width = 5, 513 .parent_map = disp_cc_parent_map_0, 514 .clkr.hw.init = &(const struct clk_init_data) { 515 .name = "disp0_cc_mdss_dptx0_link_clk_src", 516 .parent_data = disp0_cc_parent_data_0, 517 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_0), 518 .flags = CLK_SET_RATE_PARENT, 519 .ops = &clk_byte2_ops, 520 }, 521 }; 522 523 static struct clk_rcg2 disp1_cc_mdss_dptx0_link_clk_src = { 524 .cmd_rcgr = 0x21a4, 525 .mnd_width = 0, 526 .hid_width = 5, 527 .parent_map = disp_cc_parent_map_0, 528 .clkr.hw.init = &(const struct clk_init_data) { 529 .name = "disp1_cc_mdss_dptx0_link_clk_src", 530 .parent_data = disp1_cc_parent_data_0, 531 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_0), 532 .flags = CLK_SET_RATE_PARENT, 533 .ops = &clk_byte2_ops, 534 }, 535 }; 536 537 static struct clk_rcg2 disp0_cc_mdss_dptx0_pixel0_clk_src = { 538 .cmd_rcgr = 0x21d8, 539 .mnd_width = 16, 540 .hid_width = 5, 541 .parent_map = disp_cc_parent_map_1, 542 .clkr.hw.init = &(const struct clk_init_data) { 543 .name = "disp0_cc_mdss_dptx0_pixel0_clk_src", 544 .parent_data = disp0_cc_parent_data_1, 545 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_1), 546 .flags = CLK_SET_RATE_PARENT, 547 .ops = &clk_dp_ops, 548 }, 549 }; 550 551 static struct clk_rcg2 disp1_cc_mdss_dptx0_pixel0_clk_src = { 552 .cmd_rcgr = 0x21d8, 553 .mnd_width = 16, 554 .hid_width = 5, 555 .parent_map = disp_cc_parent_map_1, 556 .clkr.hw.init = &(const struct clk_init_data) { 557 .name = "disp1_cc_mdss_dptx0_pixel0_clk_src", 558 .parent_data = disp1_cc_parent_data_1, 559 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_1), 560 .flags = CLK_SET_RATE_PARENT, 561 .ops = &clk_dp_ops, 562 }, 563 }; 564 565 static struct clk_rcg2 disp0_cc_mdss_dptx0_pixel1_clk_src = { 566 .cmd_rcgr = 0x21f0, 567 .mnd_width = 16, 568 .hid_width = 5, 569 .parent_map = disp_cc_parent_map_1, 570 .clkr.hw.init = &(const struct clk_init_data) { 571 .name = "disp0_cc_mdss_dptx0_pixel1_clk_src", 572 .parent_data = disp0_cc_parent_data_1, 573 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_1), 574 .flags = CLK_SET_RATE_PARENT, 575 .ops = &clk_dp_ops, 576 }, 577 }; 578 579 static struct clk_rcg2 disp1_cc_mdss_dptx0_pixel1_clk_src = { 580 .cmd_rcgr = 0x21f0, 581 .mnd_width = 16, 582 .hid_width = 5, 583 .parent_map = disp_cc_parent_map_1, 584 .clkr.hw.init = &(const struct clk_init_data) { 585 .name = "disp1_cc_mdss_dptx0_pixel1_clk_src", 586 .parent_data = disp1_cc_parent_data_1, 587 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_1), 588 .flags = CLK_SET_RATE_PARENT, 589 .ops = &clk_dp_ops, 590 }, 591 }; 592 593 static struct clk_rcg2 disp0_cc_mdss_dptx1_aux_clk_src = { 594 .cmd_rcgr = 0x22d0, 595 .mnd_width = 0, 596 .hid_width = 5, 597 .parent_map = disp_cc_parent_map_2, 598 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 599 .clkr.hw.init = &(const struct clk_init_data) { 600 .name = "disp0_cc_mdss_dptx1_aux_clk_src", 601 .parent_data = disp_cc_parent_data_2, 602 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 603 .ops = &clk_rcg2_ops, 604 }, 605 }; 606 607 static struct clk_rcg2 disp1_cc_mdss_dptx1_aux_clk_src = { 608 .cmd_rcgr = 0x22d0, 609 .mnd_width = 0, 610 .hid_width = 5, 611 .parent_map = disp_cc_parent_map_2, 612 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 613 .clkr.hw.init = &(const struct clk_init_data) { 614 .name = "disp1_cc_mdss_dptx1_aux_clk_src", 615 .parent_data = disp_cc_parent_data_2, 616 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 617 .ops = &clk_rcg2_ops, 618 }, 619 }; 620 621 static struct clk_rcg2 disp0_cc_mdss_dptx1_link_clk_src = { 622 .cmd_rcgr = 0x2268, 623 .mnd_width = 0, 624 .hid_width = 5, 625 .parent_map = disp_cc_parent_map_0, 626 .clkr.hw.init = &(const struct clk_init_data) { 627 .name = "disp0_cc_mdss_dptx1_link_clk_src", 628 .parent_data = disp0_cc_parent_data_0, 629 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_0), 630 .flags = CLK_SET_RATE_PARENT, 631 .ops = &clk_byte2_ops, 632 }, 633 }; 634 635 static struct clk_rcg2 disp1_cc_mdss_dptx1_link_clk_src = { 636 .cmd_rcgr = 0x2268, 637 .mnd_width = 0, 638 .hid_width = 5, 639 .parent_map = disp_cc_parent_map_0, 640 .clkr.hw.init = &(const struct clk_init_data) { 641 .name = "disp1_cc_mdss_dptx1_link_clk_src", 642 .parent_data = disp1_cc_parent_data_0, 643 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_0), 644 .flags = CLK_SET_RATE_PARENT, 645 .ops = &clk_byte2_ops, 646 }, 647 }; 648 649 static struct clk_rcg2 disp0_cc_mdss_dptx1_pixel0_clk_src = { 650 .cmd_rcgr = 0x2250, 651 .mnd_width = 16, 652 .hid_width = 5, 653 .parent_map = disp_cc_parent_map_1, 654 .clkr.hw.init = &(const struct clk_init_data) { 655 .name = "disp0_cc_mdss_dptx1_pixel0_clk_src", 656 .parent_data = disp0_cc_parent_data_1, 657 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_1), 658 .flags = CLK_SET_RATE_PARENT, 659 .ops = &clk_dp_ops, 660 }, 661 }; 662 663 static struct clk_rcg2 disp1_cc_mdss_dptx1_pixel0_clk_src = { 664 .cmd_rcgr = 0x2250, 665 .mnd_width = 16, 666 .hid_width = 5, 667 .parent_map = disp_cc_parent_map_1, 668 .clkr.hw.init = &(const struct clk_init_data) { 669 .name = "disp1_cc_mdss_dptx1_pixel0_clk_src", 670 .parent_data = disp1_cc_parent_data_1, 671 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_1), 672 .flags = CLK_SET_RATE_PARENT, 673 .ops = &clk_dp_ops, 674 }, 675 }; 676 677 static struct clk_rcg2 disp0_cc_mdss_dptx1_pixel1_clk_src = { 678 .cmd_rcgr = 0x2370, 679 .mnd_width = 16, 680 .hid_width = 5, 681 .parent_map = disp_cc_parent_map_1, 682 .clkr.hw.init = &(const struct clk_init_data) { 683 .name = "disp0_cc_mdss_dptx1_pixel1_clk_src", 684 .parent_data = disp0_cc_parent_data_1, 685 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_1), 686 .flags = CLK_SET_RATE_PARENT, 687 .ops = &clk_dp_ops, 688 }, 689 }; 690 691 static struct clk_rcg2 disp1_cc_mdss_dptx1_pixel1_clk_src = { 692 .cmd_rcgr = 0x2370, 693 .mnd_width = 16, 694 .hid_width = 5, 695 .parent_map = disp_cc_parent_map_1, 696 .clkr.hw.init = &(const struct clk_init_data) { 697 .name = "disp1_cc_mdss_dptx1_pixel1_clk_src", 698 .parent_data = disp1_cc_parent_data_1, 699 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_1), 700 .flags = CLK_SET_RATE_PARENT, 701 .ops = &clk_dp_ops, 702 }, 703 }; 704 705 static struct clk_rcg2 disp0_cc_mdss_dptx2_aux_clk_src = { 706 .cmd_rcgr = 0x22e8, 707 .mnd_width = 0, 708 .hid_width = 5, 709 .parent_map = disp_cc_parent_map_2, 710 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 711 .clkr.hw.init = &(const struct clk_init_data) { 712 .name = "disp0_cc_mdss_dptx2_aux_clk_src", 713 .parent_data = disp_cc_parent_data_2, 714 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 715 .ops = &clk_rcg2_ops, 716 }, 717 }; 718 719 static struct clk_rcg2 disp1_cc_mdss_dptx2_aux_clk_src = { 720 .cmd_rcgr = 0x22e8, 721 .mnd_width = 0, 722 .hid_width = 5, 723 .parent_map = disp_cc_parent_map_2, 724 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 725 .clkr.hw.init = &(const struct clk_init_data) { 726 .name = "disp1_cc_mdss_dptx2_aux_clk_src", 727 .parent_data = disp_cc_parent_data_2, 728 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 729 .ops = &clk_rcg2_ops, 730 }, 731 }; 732 733 static struct clk_rcg2 disp0_cc_mdss_dptx2_link_clk_src = { 734 .cmd_rcgr = 0x2284, 735 .mnd_width = 0, 736 .hid_width = 5, 737 .parent_map = disp_cc_parent_map_0, 738 .clkr.hw.init = &(const struct clk_init_data) { 739 .name = "disp0_cc_mdss_dptx2_link_clk_src", 740 .parent_data = disp0_cc_parent_data_0, 741 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_0), 742 .flags = CLK_SET_RATE_PARENT, 743 .ops = &clk_byte2_ops, 744 }, 745 }; 746 747 static struct clk_rcg2 disp1_cc_mdss_dptx2_link_clk_src = { 748 .cmd_rcgr = 0x2284, 749 .mnd_width = 0, 750 .hid_width = 5, 751 .parent_map = disp_cc_parent_map_0, 752 .clkr.hw.init = &(const struct clk_init_data) { 753 .name = "disp1_cc_mdss_dptx2_link_clk_src", 754 .parent_data = disp1_cc_parent_data_0, 755 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_0), 756 .flags = CLK_SET_RATE_PARENT, 757 .ops = &clk_byte2_ops, 758 }, 759 }; 760 761 static struct clk_rcg2 disp0_cc_mdss_dptx2_pixel0_clk_src = { 762 .cmd_rcgr = 0x2208, 763 .mnd_width = 16, 764 .hid_width = 5, 765 .parent_map = disp_cc_parent_map_1, 766 .clkr.hw.init = &(const struct clk_init_data) { 767 .name = "disp0_cc_mdss_dptx2_pixel0_clk_src", 768 .parent_data = disp0_cc_parent_data_1, 769 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_1), 770 .flags = CLK_SET_RATE_PARENT, 771 .ops = &clk_dp_ops, 772 }, 773 }; 774 775 static struct clk_rcg2 disp1_cc_mdss_dptx2_pixel0_clk_src = { 776 .cmd_rcgr = 0x2208, 777 .mnd_width = 16, 778 .hid_width = 5, 779 .parent_map = disp_cc_parent_map_1, 780 .clkr.hw.init = &(const struct clk_init_data) { 781 .name = "disp1_cc_mdss_dptx2_pixel0_clk_src", 782 .parent_data = disp1_cc_parent_data_1, 783 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_1), 784 .flags = CLK_SET_RATE_PARENT, 785 .ops = &clk_dp_ops, 786 }, 787 }; 788 789 static struct clk_rcg2 disp0_cc_mdss_dptx2_pixel1_clk_src = { 790 .cmd_rcgr = 0x2220, 791 .mnd_width = 16, 792 .hid_width = 5, 793 .parent_map = disp_cc_parent_map_1, 794 .clkr.hw.init = &(const struct clk_init_data) { 795 .name = "disp0_cc_mdss_dptx2_pixel1_clk_src", 796 .parent_data = disp0_cc_parent_data_1, 797 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_1), 798 .flags = CLK_SET_RATE_PARENT, 799 .ops = &clk_dp_ops, 800 }, 801 }; 802 803 static struct clk_rcg2 disp1_cc_mdss_dptx2_pixel1_clk_src = { 804 .cmd_rcgr = 0x2220, 805 .mnd_width = 16, 806 .hid_width = 5, 807 .parent_map = disp_cc_parent_map_1, 808 .clkr.hw.init = &(const struct clk_init_data) { 809 .name = "disp1_cc_mdss_dptx2_pixel1_clk_src", 810 .parent_data = disp1_cc_parent_data_1, 811 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_1), 812 .flags = CLK_SET_RATE_PARENT, 813 .ops = &clk_dp_ops, 814 }, 815 }; 816 817 static struct clk_rcg2 disp0_cc_mdss_dptx3_aux_clk_src = { 818 .cmd_rcgr = 0x234c, 819 .mnd_width = 0, 820 .hid_width = 5, 821 .parent_map = disp_cc_parent_map_2, 822 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 823 .clkr.hw.init = &(const struct clk_init_data) { 824 .name = "disp0_cc_mdss_dptx3_aux_clk_src", 825 .parent_data = disp_cc_parent_data_2, 826 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 827 .ops = &clk_rcg2_ops, 828 }, 829 }; 830 831 static struct clk_rcg2 disp1_cc_mdss_dptx3_aux_clk_src = { 832 .cmd_rcgr = 0x234c, 833 .mnd_width = 0, 834 .hid_width = 5, 835 .parent_map = disp_cc_parent_map_2, 836 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 837 .clkr.hw.init = &(const struct clk_init_data) { 838 .name = "disp1_cc_mdss_dptx3_aux_clk_src", 839 .parent_data = disp_cc_parent_data_2, 840 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 841 .ops = &clk_rcg2_ops, 842 }, 843 }; 844 845 static struct clk_rcg2 disp0_cc_mdss_dptx3_link_clk_src = { 846 .cmd_rcgr = 0x2318, 847 .mnd_width = 0, 848 .hid_width = 5, 849 .parent_map = disp_cc_parent_map_0, 850 .clkr.hw.init = &(const struct clk_init_data) { 851 .name = "disp0_cc_mdss_dptx3_link_clk_src", 852 .parent_data = disp0_cc_parent_data_0, 853 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_0), 854 .flags = CLK_SET_RATE_PARENT, 855 .ops = &clk_byte2_ops, 856 }, 857 }; 858 859 static struct clk_rcg2 disp1_cc_mdss_dptx3_link_clk_src = { 860 .cmd_rcgr = 0x2318, 861 .mnd_width = 0, 862 .hid_width = 5, 863 .parent_map = disp_cc_parent_map_0, 864 .clkr.hw.init = &(const struct clk_init_data) { 865 .name = "disp1_cc_mdss_dptx3_link_clk_src", 866 .parent_data = disp1_cc_parent_data_0, 867 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_0), 868 .flags = CLK_SET_RATE_PARENT, 869 .ops = &clk_byte2_ops, 870 }, 871 }; 872 873 static struct clk_rcg2 disp0_cc_mdss_dptx3_pixel0_clk_src = { 874 .cmd_rcgr = 0x2300, 875 .mnd_width = 16, 876 .hid_width = 5, 877 .parent_map = disp_cc_parent_map_1, 878 .clkr.hw.init = &(const struct clk_init_data) { 879 .name = "disp0_cc_mdss_dptx3_pixel0_clk_src", 880 .parent_data = disp0_cc_parent_data_1, 881 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_1), 882 .flags = CLK_SET_RATE_PARENT, 883 .ops = &clk_dp_ops, 884 }, 885 }; 886 887 static struct clk_rcg2 disp1_cc_mdss_dptx3_pixel0_clk_src = { 888 .cmd_rcgr = 0x2300, 889 .mnd_width = 16, 890 .hid_width = 5, 891 .parent_map = disp_cc_parent_map_1, 892 .clkr.hw.init = &(const struct clk_init_data) { 893 .name = "disp1_cc_mdss_dptx3_pixel0_clk_src", 894 .parent_data = disp1_cc_parent_data_1, 895 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_1), 896 .flags = CLK_SET_RATE_PARENT, 897 .ops = &clk_dp_ops, 898 }, 899 }; 900 901 static struct clk_rcg2 disp0_cc_mdss_esc0_clk_src = { 902 .cmd_rcgr = 0x2174, 903 .mnd_width = 0, 904 .hid_width = 5, 905 .parent_map = disp_cc_parent_map_4, 906 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 907 .clkr.hw.init = &(const struct clk_init_data) { 908 .name = "disp0_cc_mdss_esc0_clk_src", 909 .parent_data = disp_cc_parent_data_4, 910 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 911 .ops = &clk_rcg2_ops, 912 }, 913 }; 914 915 static struct clk_rcg2 disp1_cc_mdss_esc0_clk_src = { 916 .cmd_rcgr = 0x2174, 917 .mnd_width = 0, 918 .hid_width = 5, 919 .parent_map = disp_cc_parent_map_4, 920 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 921 .clkr.hw.init = &(const struct clk_init_data) { 922 .name = "disp1_cc_mdss_esc0_clk_src", 923 .parent_data = disp_cc_parent_data_4, 924 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 925 .ops = &clk_rcg2_ops, 926 }, 927 }; 928 929 static struct clk_rcg2 disp0_cc_mdss_esc1_clk_src = { 930 .cmd_rcgr = 0x218c, 931 .mnd_width = 0, 932 .hid_width = 5, 933 .parent_map = disp_cc_parent_map_4, 934 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 935 .clkr.hw.init = &(const struct clk_init_data) { 936 .name = "disp0_cc_mdss_esc1_clk_src", 937 .parent_data = disp_cc_parent_data_4, 938 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 939 .ops = &clk_rcg2_ops, 940 }, 941 }; 942 943 static struct clk_rcg2 disp1_cc_mdss_esc1_clk_src = { 944 .cmd_rcgr = 0x218c, 945 .mnd_width = 0, 946 .hid_width = 5, 947 .parent_map = disp_cc_parent_map_4, 948 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 949 .clkr.hw.init = &(const struct clk_init_data) { 950 .name = "disp1_cc_mdss_esc1_clk_src", 951 .parent_data = disp_cc_parent_data_4, 952 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 953 .ops = &clk_rcg2_ops, 954 }, 955 }; 956 957 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { 958 F(19200000, P_BI_TCXO, 1, 0, 0), 959 F(85714286, P_DISPn_CC_PLL1_OUT_MAIN, 7, 0, 0), 960 F(100000000, P_DISPn_CC_PLL1_OUT_MAIN, 6, 0, 0), 961 F(150000000, P_DISPn_CC_PLL1_OUT_MAIN, 4, 0, 0), 962 F(200000000, P_DISPn_CC_PLL1_OUT_MAIN, 3, 0, 0), 963 F(300000000, P_DISPn_CC_PLL1_OUT_MAIN, 2, 0, 0), 964 F(375000000, P_DISPn_CC_PLL0_OUT_MAIN, 4, 0, 0), 965 F(500000000, P_DISPn_CC_PLL0_OUT_MAIN, 3, 0, 0), 966 F(600000000, P_DISPn_CC_PLL1_OUT_MAIN, 1, 0, 0), 967 { } 968 }; 969 970 static struct clk_rcg2 disp0_cc_mdss_mdp_clk_src = { 971 .cmd_rcgr = 0x20f4, 972 .mnd_width = 0, 973 .hid_width = 5, 974 .parent_map = disp_cc_parent_map_5, 975 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 976 .clkr.hw.init = &(const struct clk_init_data) { 977 .name = "disp0_cc_mdss_mdp_clk_src", 978 .parent_data = disp0_cc_parent_data_5, 979 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_5), 980 .ops = &clk_rcg2_shared_ops, 981 }, 982 }; 983 984 static struct clk_rcg2 disp1_cc_mdss_mdp_clk_src = { 985 .cmd_rcgr = 0x20f4, 986 .mnd_width = 0, 987 .hid_width = 5, 988 .parent_map = disp_cc_parent_map_5, 989 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 990 .clkr.hw.init = &(const struct clk_init_data) { 991 .name = "disp1_cc_mdss_mdp_clk_src", 992 .parent_data = disp1_cc_parent_data_5, 993 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_5), 994 .ops = &clk_rcg2_shared_ops, 995 }, 996 }; 997 998 static struct clk_rcg2 disp0_cc_mdss_pclk0_clk_src = { 999 .cmd_rcgr = 0x20c4, 1000 .mnd_width = 8, 1001 .hid_width = 5, 1002 .parent_map = disp_cc_parent_map_3, 1003 .clkr.hw.init = &(const struct clk_init_data) { 1004 .name = "disp0_cc_mdss_pclk0_clk_src", 1005 .parent_data = disp_cc_parent_data_3, 1006 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 1007 .flags = CLK_SET_RATE_PARENT, 1008 .ops = &clk_pixel_ops, 1009 }, 1010 }; 1011 1012 static struct clk_rcg2 disp1_cc_mdss_pclk0_clk_src = { 1013 .cmd_rcgr = 0x20c4, 1014 .mnd_width = 8, 1015 .hid_width = 5, 1016 .parent_map = disp_cc_parent_map_3, 1017 .clkr.hw.init = &(const struct clk_init_data) { 1018 .name = "disp1_cc_mdss_pclk0_clk_src", 1019 .parent_data = disp_cc_parent_data_3, 1020 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 1021 .flags = CLK_SET_RATE_PARENT, 1022 .ops = &clk_pixel_ops, 1023 }, 1024 }; 1025 1026 static struct clk_rcg2 disp0_cc_mdss_pclk1_clk_src = { 1027 .cmd_rcgr = 0x20dc, 1028 .mnd_width = 8, 1029 .hid_width = 5, 1030 .parent_map = disp_cc_parent_map_3, 1031 .clkr.hw.init = &(const struct clk_init_data) { 1032 .name = "disp0_cc_mdss_pclk1_clk_src", 1033 .parent_data = disp_cc_parent_data_3, 1034 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 1035 .flags = CLK_SET_RATE_PARENT, 1036 .ops = &clk_pixel_ops, 1037 }, 1038 }; 1039 1040 static struct clk_rcg2 disp1_cc_mdss_pclk1_clk_src = { 1041 .cmd_rcgr = 0x20dc, 1042 .mnd_width = 8, 1043 .hid_width = 5, 1044 .parent_map = disp_cc_parent_map_3, 1045 .clkr.hw.init = &(const struct clk_init_data) { 1046 .name = "disp1_cc_mdss_pclk1_clk_src", 1047 .parent_data = disp_cc_parent_data_3, 1048 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 1049 .flags = CLK_SET_RATE_PARENT, 1050 .ops = &clk_pixel_ops, 1051 }, 1052 }; 1053 1054 static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = { 1055 F(19200000, P_BI_TCXO, 1, 0, 0), 1056 F(200000000, P_DISPn_CC_PLL1_OUT_MAIN, 3, 0, 0), 1057 F(300000000, P_DISPn_CC_PLL1_OUT_MAIN, 2, 0, 0), 1058 F(375000000, P_DISPn_CC_PLL0_OUT_MAIN, 4, 0, 0), 1059 F(500000000, P_DISPn_CC_PLL0_OUT_MAIN, 3, 0, 0), 1060 F(600000000, P_DISPn_CC_PLL1_OUT_MAIN, 1, 0, 0), 1061 { } 1062 }; 1063 1064 static struct clk_rcg2 disp0_cc_mdss_rot_clk_src = { 1065 .cmd_rcgr = 0x210c, 1066 .mnd_width = 0, 1067 .hid_width = 5, 1068 .parent_map = disp_cc_parent_map_5, 1069 .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, 1070 .clkr.hw.init = &(const struct clk_init_data) { 1071 .name = "disp0_cc_mdss_rot_clk_src", 1072 .parent_data = disp0_cc_parent_data_5, 1073 .num_parents = ARRAY_SIZE(disp0_cc_parent_data_5), 1074 .ops = &clk_rcg2_shared_ops, 1075 }, 1076 }; 1077 1078 static struct clk_rcg2 disp1_cc_mdss_rot_clk_src = { 1079 .cmd_rcgr = 0x210c, 1080 .mnd_width = 0, 1081 .hid_width = 5, 1082 .parent_map = disp_cc_parent_map_5, 1083 .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, 1084 .clkr.hw.init = &(const struct clk_init_data) { 1085 .name = "disp1_cc_mdss_rot_clk_src", 1086 .parent_data = disp1_cc_parent_data_5, 1087 .num_parents = ARRAY_SIZE(disp1_cc_parent_data_5), 1088 .ops = &clk_rcg2_shared_ops, 1089 }, 1090 }; 1091 1092 static struct clk_rcg2 disp0_cc_mdss_vsync_clk_src = { 1093 .cmd_rcgr = 0x2124, 1094 .mnd_width = 0, 1095 .hid_width = 5, 1096 .parent_map = disp_cc_parent_map_2, 1097 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 1098 .clkr.hw.init = &(const struct clk_init_data) { 1099 .name = "disp0_cc_mdss_vsync_clk_src", 1100 .parent_data = disp_cc_parent_data_2, 1101 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 1102 .ops = &clk_rcg2_ops, 1103 }, 1104 }; 1105 1106 static struct clk_rcg2 disp1_cc_mdss_vsync_clk_src = { 1107 .cmd_rcgr = 0x2124, 1108 .mnd_width = 0, 1109 .hid_width = 5, 1110 .parent_map = disp_cc_parent_map_2, 1111 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 1112 .clkr.hw.init = &(const struct clk_init_data) { 1113 .name = "disp1_cc_mdss_vsync_clk_src", 1114 .parent_data = disp_cc_parent_data_2, 1115 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 1116 .ops = &clk_rcg2_ops, 1117 }, 1118 }; 1119 1120 static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = { 1121 F(32000, P_SLEEP_CLK, 1, 0, 0), 1122 { } 1123 }; 1124 1125 static struct clk_rcg2 disp0_cc_sleep_clk_src = { 1126 .cmd_rcgr = 0x6060, 1127 .mnd_width = 0, 1128 .hid_width = 5, 1129 .parent_map = disp_cc_parent_map_7, 1130 .freq_tbl = ftbl_disp_cc_sleep_clk_src, 1131 .clkr.hw.init = &(const struct clk_init_data) { 1132 .name = "disp0_cc_sleep_clk_src", 1133 .parent_data = disp_cc_parent_data_7, 1134 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), 1135 .ops = &clk_rcg2_ops, 1136 }, 1137 }; 1138 1139 static struct clk_rcg2 disp1_cc_sleep_clk_src = { 1140 .cmd_rcgr = 0x6060, 1141 .mnd_width = 0, 1142 .hid_width = 5, 1143 .parent_map = disp_cc_parent_map_7, 1144 .freq_tbl = ftbl_disp_cc_sleep_clk_src, 1145 .clkr.hw.init = &(const struct clk_init_data) { 1146 .name = "disp1_cc_sleep_clk_src", 1147 .parent_data = disp_cc_parent_data_7, 1148 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), 1149 .ops = &clk_rcg2_ops, 1150 }, 1151 }; 1152 1153 static struct clk_regmap_div disp0_cc_mdss_byte0_div_clk_src = { 1154 .reg = 0x2154, 1155 .shift = 0, 1156 .width = 4, 1157 .clkr.hw.init = &(const struct clk_init_data) { 1158 .name = "disp0_cc_mdss_byte0_div_clk_src", 1159 .parent_hws = (const struct clk_hw*[]){ 1160 &disp0_cc_mdss_byte0_clk_src.clkr.hw, 1161 }, 1162 .num_parents = 1, 1163 .flags = CLK_SET_RATE_PARENT, 1164 .ops = &clk_regmap_div_ops, 1165 }, 1166 }; 1167 1168 static struct clk_regmap_div disp1_cc_mdss_byte0_div_clk_src = { 1169 .reg = 0x2154, 1170 .shift = 0, 1171 .width = 4, 1172 .clkr.hw.init = &(const struct clk_init_data) { 1173 .name = "disp1_cc_mdss_byte0_div_clk_src", 1174 .parent_hws = (const struct clk_hw*[]){ 1175 &disp1_cc_mdss_byte0_clk_src.clkr.hw, 1176 }, 1177 .num_parents = 1, 1178 .flags = CLK_SET_RATE_PARENT, 1179 .ops = &clk_regmap_div_ops, 1180 }, 1181 }; 1182 1183 static struct clk_regmap_div disp0_cc_mdss_byte1_div_clk_src = { 1184 .reg = 0x2170, 1185 .shift = 0, 1186 .width = 4, 1187 .clkr.hw.init = &(const struct clk_init_data) { 1188 .name = "disp0_cc_mdss_byte1_div_clk_src", 1189 .parent_hws = (const struct clk_hw*[]){ 1190 &disp0_cc_mdss_byte1_clk_src.clkr.hw, 1191 }, 1192 .num_parents = 1, 1193 .flags = CLK_SET_RATE_PARENT, 1194 .ops = &clk_regmap_div_ops, 1195 }, 1196 }; 1197 1198 static struct clk_regmap_div disp1_cc_mdss_byte1_div_clk_src = { 1199 .reg = 0x2170, 1200 .shift = 0, 1201 .width = 4, 1202 .clkr.hw.init = &(const struct clk_init_data) { 1203 .name = "disp1_cc_mdss_byte1_div_clk_src", 1204 .parent_hws = (const struct clk_hw*[]){ 1205 &disp1_cc_mdss_byte1_clk_src.clkr.hw, 1206 }, 1207 .num_parents = 1, 1208 .flags = CLK_SET_RATE_PARENT, 1209 .ops = &clk_regmap_div_ops, 1210 }, 1211 }; 1212 1213 static struct clk_regmap_div disp0_cc_mdss_dptx0_link_div_clk_src = { 1214 .reg = 0x21bc, 1215 .shift = 0, 1216 .width = 4, 1217 .clkr.hw.init = &(const struct clk_init_data) { 1218 .name = "disp0_cc_mdss_dptx0_link_div_clk_src", 1219 .parent_hws = (const struct clk_hw*[]){ 1220 &disp0_cc_mdss_dptx0_link_clk_src.clkr.hw, 1221 }, 1222 .num_parents = 1, 1223 .flags = CLK_SET_RATE_PARENT, 1224 .ops = &clk_regmap_div_ro_ops, 1225 }, 1226 }; 1227 1228 static struct clk_regmap_div disp1_cc_mdss_dptx0_link_div_clk_src = { 1229 .reg = 0x21bc, 1230 .shift = 0, 1231 .width = 4, 1232 .clkr.hw.init = &(const struct clk_init_data) { 1233 .name = "disp1_cc_mdss_dptx0_link_div_clk_src", 1234 .parent_hws = (const struct clk_hw*[]){ 1235 &disp1_cc_mdss_dptx0_link_clk_src.clkr.hw, 1236 }, 1237 .num_parents = 1, 1238 .flags = CLK_SET_RATE_PARENT, 1239 .ops = &clk_regmap_div_ro_ops, 1240 }, 1241 }; 1242 1243 static struct clk_regmap_div disp0_cc_mdss_dptx1_link_div_clk_src = { 1244 .reg = 0x2280, 1245 .shift = 0, 1246 .width = 4, 1247 .clkr.hw.init = &(const struct clk_init_data) { 1248 .name = "disp0_cc_mdss_dptx1_link_div_clk_src", 1249 .parent_hws = (const struct clk_hw*[]){ 1250 &disp0_cc_mdss_dptx1_link_clk_src.clkr.hw, 1251 }, 1252 .num_parents = 1, 1253 .flags = CLK_SET_RATE_PARENT, 1254 .ops = &clk_regmap_div_ro_ops, 1255 }, 1256 }; 1257 1258 static struct clk_regmap_div disp1_cc_mdss_dptx1_link_div_clk_src = { 1259 .reg = 0x2280, 1260 .shift = 0, 1261 .width = 4, 1262 .clkr.hw.init = &(const struct clk_init_data) { 1263 .name = "disp1_cc_mdss_dptx1_link_div_clk_src", 1264 .parent_hws = (const struct clk_hw*[]){ 1265 &disp1_cc_mdss_dptx1_link_clk_src.clkr.hw, 1266 }, 1267 .num_parents = 1, 1268 .flags = CLK_SET_RATE_PARENT, 1269 .ops = &clk_regmap_div_ro_ops, 1270 }, 1271 }; 1272 1273 static struct clk_regmap_div disp0_cc_mdss_dptx2_link_div_clk_src = { 1274 .reg = 0x229c, 1275 .shift = 0, 1276 .width = 4, 1277 .clkr.hw.init = &(const struct clk_init_data) { 1278 .name = "disp0_cc_mdss_dptx2_link_div_clk_src", 1279 .parent_hws = (const struct clk_hw*[]){ 1280 &disp0_cc_mdss_dptx2_link_clk_src.clkr.hw, 1281 }, 1282 .num_parents = 1, 1283 .flags = CLK_SET_RATE_PARENT, 1284 .ops = &clk_regmap_div_ro_ops, 1285 }, 1286 }; 1287 1288 static struct clk_regmap_div disp1_cc_mdss_dptx2_link_div_clk_src = { 1289 .reg = 0x229c, 1290 .shift = 0, 1291 .width = 4, 1292 .clkr.hw.init = &(const struct clk_init_data) { 1293 .name = "disp1_cc_mdss_dptx2_link_div_clk_src", 1294 .parent_hws = (const struct clk_hw*[]){ 1295 &disp1_cc_mdss_dptx2_link_clk_src.clkr.hw, 1296 }, 1297 .num_parents = 1, 1298 .flags = CLK_SET_RATE_PARENT, 1299 .ops = &clk_regmap_div_ro_ops, 1300 }, 1301 }; 1302 1303 static struct clk_regmap_div disp0_cc_mdss_dptx3_link_div_clk_src = { 1304 .reg = 0x2330, 1305 .shift = 0, 1306 .width = 4, 1307 .clkr.hw.init = &(const struct clk_init_data) { 1308 .name = "disp0_cc_mdss_dptx3_link_div_clk_src", 1309 .parent_hws = (const struct clk_hw*[]){ 1310 &disp0_cc_mdss_dptx3_link_clk_src.clkr.hw, 1311 }, 1312 .num_parents = 1, 1313 .flags = CLK_SET_RATE_PARENT, 1314 .ops = &clk_regmap_div_ro_ops, 1315 }, 1316 }; 1317 1318 static struct clk_regmap_div disp1_cc_mdss_dptx3_link_div_clk_src = { 1319 .reg = 0x2330, 1320 .shift = 0, 1321 .width = 4, 1322 .clkr.hw.init = &(const struct clk_init_data) { 1323 .name = "disp1_cc_mdss_dptx3_link_div_clk_src", 1324 .parent_hws = (const struct clk_hw*[]){ 1325 &disp1_cc_mdss_dptx3_link_clk_src.clkr.hw, 1326 }, 1327 .num_parents = 1, 1328 .flags = CLK_SET_RATE_PARENT, 1329 .ops = &clk_regmap_div_ro_ops, 1330 }, 1331 }; 1332 1333 static struct clk_branch disp0_cc_mdss_ahb1_clk = { 1334 .halt_reg = 0x20c0, 1335 .halt_check = BRANCH_HALT, 1336 .clkr = { 1337 .enable_reg = 0x20c0, 1338 .enable_mask = BIT(0), 1339 .hw.init = &(const struct clk_init_data) { 1340 .name = "disp0_cc_mdss_ahb1_clk", 1341 .parent_hws = (const struct clk_hw*[]){ 1342 &disp0_cc_mdss_ahb_clk_src.clkr.hw, 1343 }, 1344 .num_parents = 1, 1345 .flags = CLK_SET_RATE_PARENT, 1346 .ops = &clk_branch2_ops, 1347 }, 1348 }, 1349 }; 1350 1351 static struct clk_branch disp1_cc_mdss_ahb1_clk = { 1352 .halt_reg = 0x20c0, 1353 .halt_check = BRANCH_HALT, 1354 .clkr = { 1355 .enable_reg = 0x20c0, 1356 .enable_mask = BIT(0), 1357 .hw.init = &(const struct clk_init_data) { 1358 .name = "disp1_cc_mdss_ahb1_clk", 1359 .parent_hws = (const struct clk_hw*[]){ 1360 &disp1_cc_mdss_ahb_clk_src.clkr.hw, 1361 }, 1362 .num_parents = 1, 1363 .flags = CLK_SET_RATE_PARENT, 1364 .ops = &clk_branch2_ops, 1365 }, 1366 }, 1367 }; 1368 1369 static struct clk_branch disp0_cc_mdss_ahb_clk = { 1370 .halt_reg = 0x20bc, 1371 .halt_check = BRANCH_HALT, 1372 .clkr = { 1373 .enable_reg = 0x20bc, 1374 .enable_mask = BIT(0), 1375 .hw.init = &(const struct clk_init_data) { 1376 .name = "disp0_cc_mdss_ahb_clk", 1377 .parent_hws = (const struct clk_hw*[]){ 1378 &disp0_cc_mdss_ahb_clk_src.clkr.hw, 1379 }, 1380 .num_parents = 1, 1381 .flags = CLK_SET_RATE_PARENT, 1382 .ops = &clk_branch2_ops, 1383 }, 1384 }, 1385 }; 1386 1387 static struct clk_branch disp1_cc_mdss_ahb_clk = { 1388 .halt_reg = 0x20bc, 1389 .halt_check = BRANCH_HALT, 1390 .clkr = { 1391 .enable_reg = 0x20bc, 1392 .enable_mask = BIT(0), 1393 .hw.init = &(const struct clk_init_data) { 1394 .name = "disp1_cc_mdss_ahb_clk", 1395 .parent_hws = (const struct clk_hw*[]){ 1396 &disp1_cc_mdss_ahb_clk_src.clkr.hw, 1397 }, 1398 .num_parents = 1, 1399 .flags = CLK_SET_RATE_PARENT, 1400 .ops = &clk_branch2_ops, 1401 }, 1402 }, 1403 }; 1404 1405 static struct clk_branch disp0_cc_mdss_byte0_clk = { 1406 .halt_reg = 0x2044, 1407 .halt_check = BRANCH_HALT, 1408 .clkr = { 1409 .enable_reg = 0x2044, 1410 .enable_mask = BIT(0), 1411 .hw.init = &(const struct clk_init_data) { 1412 .name = "disp0_cc_mdss_byte0_clk", 1413 .parent_hws = (const struct clk_hw*[]){ 1414 &disp0_cc_mdss_byte0_clk_src.clkr.hw, 1415 }, 1416 .num_parents = 1, 1417 .flags = CLK_SET_RATE_PARENT, 1418 .ops = &clk_branch2_ops, 1419 }, 1420 }, 1421 }; 1422 1423 static struct clk_branch disp1_cc_mdss_byte0_clk = { 1424 .halt_reg = 0x2044, 1425 .halt_check = BRANCH_HALT, 1426 .clkr = { 1427 .enable_reg = 0x2044, 1428 .enable_mask = BIT(0), 1429 .hw.init = &(const struct clk_init_data) { 1430 .name = "disp1_cc_mdss_byte0_clk", 1431 .parent_hws = (const struct clk_hw*[]){ 1432 &disp1_cc_mdss_byte0_clk_src.clkr.hw, 1433 }, 1434 .num_parents = 1, 1435 .flags = CLK_SET_RATE_PARENT, 1436 .ops = &clk_branch2_ops, 1437 }, 1438 }, 1439 }; 1440 1441 static struct clk_branch disp0_cc_mdss_byte0_intf_clk = { 1442 .halt_reg = 0x2048, 1443 .halt_check = BRANCH_HALT, 1444 .clkr = { 1445 .enable_reg = 0x2048, 1446 .enable_mask = BIT(0), 1447 .hw.init = &(const struct clk_init_data) { 1448 .name = "disp0_cc_mdss_byte0_intf_clk", 1449 .parent_hws = (const struct clk_hw*[]){ 1450 &disp0_cc_mdss_byte0_div_clk_src.clkr.hw, 1451 }, 1452 .num_parents = 1, 1453 .flags = CLK_SET_RATE_PARENT, 1454 .ops = &clk_branch2_ops, 1455 }, 1456 }, 1457 }; 1458 1459 static struct clk_branch disp1_cc_mdss_byte0_intf_clk = { 1460 .halt_reg = 0x2048, 1461 .halt_check = BRANCH_HALT, 1462 .clkr = { 1463 .enable_reg = 0x2048, 1464 .enable_mask = BIT(0), 1465 .hw.init = &(const struct clk_init_data) { 1466 .name = "disp1_cc_mdss_byte0_intf_clk", 1467 .parent_hws = (const struct clk_hw*[]){ 1468 &disp1_cc_mdss_byte0_div_clk_src.clkr.hw, 1469 }, 1470 .num_parents = 1, 1471 .flags = CLK_SET_RATE_PARENT, 1472 .ops = &clk_branch2_ops, 1473 }, 1474 }, 1475 }; 1476 1477 static struct clk_branch disp0_cc_mdss_byte1_clk = { 1478 .halt_reg = 0x204c, 1479 .halt_check = BRANCH_HALT, 1480 .clkr = { 1481 .enable_reg = 0x204c, 1482 .enable_mask = BIT(0), 1483 .hw.init = &(const struct clk_init_data) { 1484 .name = "disp0_cc_mdss_byte1_clk", 1485 .parent_hws = (const struct clk_hw*[]){ 1486 &disp0_cc_mdss_byte1_clk_src.clkr.hw, 1487 }, 1488 .num_parents = 1, 1489 .flags = CLK_SET_RATE_PARENT, 1490 .ops = &clk_branch2_ops, 1491 }, 1492 }, 1493 }; 1494 1495 static struct clk_branch disp1_cc_mdss_byte1_clk = { 1496 .halt_reg = 0x204c, 1497 .halt_check = BRANCH_HALT, 1498 .clkr = { 1499 .enable_reg = 0x204c, 1500 .enable_mask = BIT(0), 1501 .hw.init = &(const struct clk_init_data) { 1502 .name = "disp1_cc_mdss_byte1_clk", 1503 .parent_hws = (const struct clk_hw*[]){ 1504 &disp1_cc_mdss_byte1_clk_src.clkr.hw, 1505 }, 1506 .num_parents = 1, 1507 .flags = CLK_SET_RATE_PARENT, 1508 .ops = &clk_branch2_ops, 1509 }, 1510 }, 1511 }; 1512 1513 static struct clk_branch disp0_cc_mdss_byte1_intf_clk = { 1514 .halt_reg = 0x2050, 1515 .halt_check = BRANCH_HALT, 1516 .clkr = { 1517 .enable_reg = 0x2050, 1518 .enable_mask = BIT(0), 1519 .hw.init = &(const struct clk_init_data) { 1520 .name = "disp0_cc_mdss_byte1_intf_clk", 1521 .parent_hws = (const struct clk_hw*[]){ 1522 &disp0_cc_mdss_byte1_div_clk_src.clkr.hw, 1523 }, 1524 .num_parents = 1, 1525 .flags = CLK_SET_RATE_PARENT, 1526 .ops = &clk_branch2_ops, 1527 }, 1528 }, 1529 }; 1530 1531 static struct clk_branch disp1_cc_mdss_byte1_intf_clk = { 1532 .halt_reg = 0x2050, 1533 .halt_check = BRANCH_HALT, 1534 .clkr = { 1535 .enable_reg = 0x2050, 1536 .enable_mask = BIT(0), 1537 .hw.init = &(const struct clk_init_data) { 1538 .name = "disp1_cc_mdss_byte1_intf_clk", 1539 .parent_hws = (const struct clk_hw*[]){ 1540 &disp1_cc_mdss_byte1_div_clk_src.clkr.hw, 1541 }, 1542 .num_parents = 1, 1543 .flags = CLK_SET_RATE_PARENT, 1544 .ops = &clk_branch2_ops, 1545 }, 1546 }, 1547 }; 1548 1549 static struct clk_branch disp0_cc_mdss_dptx0_aux_clk = { 1550 .halt_reg = 0x206c, 1551 .halt_check = BRANCH_HALT, 1552 .clkr = { 1553 .enable_reg = 0x206c, 1554 .enable_mask = BIT(0), 1555 .hw.init = &(const struct clk_init_data) { 1556 .name = "disp0_cc_mdss_dptx0_aux_clk", 1557 .parent_hws = (const struct clk_hw*[]){ 1558 &disp0_cc_mdss_dptx0_aux_clk_src.clkr.hw, 1559 }, 1560 .num_parents = 1, 1561 .flags = CLK_SET_RATE_PARENT, 1562 .ops = &clk_branch2_ops, 1563 }, 1564 }, 1565 }; 1566 1567 static struct clk_branch disp1_cc_mdss_dptx0_aux_clk = { 1568 .halt_reg = 0x206c, 1569 .halt_check = BRANCH_HALT, 1570 .clkr = { 1571 .enable_reg = 0x206c, 1572 .enable_mask = BIT(0), 1573 .hw.init = &(const struct clk_init_data) { 1574 .name = "disp1_cc_mdss_dptx0_aux_clk", 1575 .parent_hws = (const struct clk_hw*[]){ 1576 &disp1_cc_mdss_dptx0_aux_clk_src.clkr.hw, 1577 }, 1578 .num_parents = 1, 1579 .flags = CLK_SET_RATE_PARENT, 1580 .ops = &clk_branch2_ops, 1581 }, 1582 }, 1583 }; 1584 1585 static struct clk_branch disp0_cc_mdss_dptx0_link_clk = { 1586 .halt_reg = 0x205c, 1587 .halt_check = BRANCH_HALT, 1588 .clkr = { 1589 .enable_reg = 0x205c, 1590 .enable_mask = BIT(0), 1591 .hw.init = &(const struct clk_init_data) { 1592 .name = "disp0_cc_mdss_dptx0_link_clk", 1593 .parent_hws = (const struct clk_hw*[]){ 1594 &disp0_cc_mdss_dptx0_link_clk_src.clkr.hw, 1595 }, 1596 .num_parents = 1, 1597 .flags = CLK_SET_RATE_PARENT, 1598 .ops = &clk_branch2_ops, 1599 }, 1600 }, 1601 }; 1602 1603 static struct clk_branch disp1_cc_mdss_dptx0_link_clk = { 1604 .halt_reg = 0x205c, 1605 .halt_check = BRANCH_HALT, 1606 .clkr = { 1607 .enable_reg = 0x205c, 1608 .enable_mask = BIT(0), 1609 .hw.init = &(const struct clk_init_data) { 1610 .name = "disp1_cc_mdss_dptx0_link_clk", 1611 .parent_hws = (const struct clk_hw*[]){ 1612 &disp1_cc_mdss_dptx0_link_clk_src.clkr.hw, 1613 }, 1614 .num_parents = 1, 1615 .flags = CLK_SET_RATE_PARENT, 1616 .ops = &clk_branch2_ops, 1617 }, 1618 }, 1619 }; 1620 1621 static struct clk_branch disp0_cc_mdss_dptx0_link_intf_clk = { 1622 .halt_reg = 0x2060, 1623 .halt_check = BRANCH_HALT, 1624 .clkr = { 1625 .enable_reg = 0x2060, 1626 .enable_mask = BIT(0), 1627 .hw.init = &(const struct clk_init_data) { 1628 .name = "disp0_cc_mdss_dptx0_link_intf_clk", 1629 .parent_hws = (const struct clk_hw*[]){ 1630 &disp0_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1631 }, 1632 .num_parents = 1, 1633 .flags = CLK_SET_RATE_PARENT, 1634 .ops = &clk_branch2_ops, 1635 }, 1636 }, 1637 }; 1638 1639 static struct clk_branch disp1_cc_mdss_dptx0_link_intf_clk = { 1640 .halt_reg = 0x2060, 1641 .halt_check = BRANCH_HALT, 1642 .clkr = { 1643 .enable_reg = 0x2060, 1644 .enable_mask = BIT(0), 1645 .hw.init = &(const struct clk_init_data) { 1646 .name = "disp1_cc_mdss_dptx0_link_intf_clk", 1647 .parent_hws = (const struct clk_hw*[]){ 1648 &disp1_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1649 }, 1650 .num_parents = 1, 1651 .flags = CLK_SET_RATE_PARENT, 1652 .ops = &clk_branch2_ops, 1653 }, 1654 }, 1655 }; 1656 1657 static struct clk_branch disp0_cc_mdss_dptx0_pixel0_clk = { 1658 .halt_reg = 0x2070, 1659 .halt_check = BRANCH_HALT, 1660 .clkr = { 1661 .enable_reg = 0x2070, 1662 .enable_mask = BIT(0), 1663 .hw.init = &(const struct clk_init_data) { 1664 .name = "disp0_cc_mdss_dptx0_pixel0_clk", 1665 .parent_hws = (const struct clk_hw*[]){ 1666 &disp0_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, 1667 }, 1668 .num_parents = 1, 1669 .flags = CLK_SET_RATE_PARENT, 1670 .ops = &clk_branch2_ops, 1671 }, 1672 }, 1673 }; 1674 1675 static struct clk_branch disp1_cc_mdss_dptx0_pixel0_clk = { 1676 .halt_reg = 0x2070, 1677 .halt_check = BRANCH_HALT, 1678 .clkr = { 1679 .enable_reg = 0x2070, 1680 .enable_mask = BIT(0), 1681 .hw.init = &(const struct clk_init_data) { 1682 .name = "disp1_cc_mdss_dptx0_pixel0_clk", 1683 .parent_hws = (const struct clk_hw*[]){ 1684 &disp1_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, 1685 }, 1686 .num_parents = 1, 1687 .flags = CLK_SET_RATE_PARENT, 1688 .ops = &clk_branch2_ops, 1689 }, 1690 }, 1691 }; 1692 1693 static struct clk_branch disp0_cc_mdss_dptx0_pixel1_clk = { 1694 .halt_reg = 0x2074, 1695 .halt_check = BRANCH_HALT, 1696 .clkr = { 1697 .enable_reg = 0x2074, 1698 .enable_mask = BIT(0), 1699 .hw.init = &(const struct clk_init_data) { 1700 .name = "disp0_cc_mdss_dptx0_pixel1_clk", 1701 .parent_hws = (const struct clk_hw*[]){ 1702 &disp0_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, 1703 }, 1704 .num_parents = 1, 1705 .flags = CLK_SET_RATE_PARENT, 1706 .ops = &clk_branch2_ops, 1707 }, 1708 }, 1709 }; 1710 1711 static struct clk_branch disp1_cc_mdss_dptx0_pixel1_clk = { 1712 .halt_reg = 0x2074, 1713 .halt_check = BRANCH_HALT, 1714 .clkr = { 1715 .enable_reg = 0x2074, 1716 .enable_mask = BIT(0), 1717 .hw.init = &(const struct clk_init_data) { 1718 .name = "disp1_cc_mdss_dptx0_pixel1_clk", 1719 .parent_hws = (const struct clk_hw*[]){ 1720 &disp1_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, 1721 }, 1722 .num_parents = 1, 1723 .flags = CLK_SET_RATE_PARENT, 1724 .ops = &clk_branch2_ops, 1725 }, 1726 }, 1727 }; 1728 1729 static struct clk_branch disp0_cc_mdss_dptx0_usb_router_link_intf_clk = { 1730 .halt_reg = 0x2064, 1731 .halt_check = BRANCH_HALT, 1732 .clkr = { 1733 .enable_reg = 0x2064, 1734 .enable_mask = BIT(0), 1735 .hw.init = &(const struct clk_init_data) { 1736 .name = "disp0_cc_mdss_dptx0_usb_router_link_intf_clk", 1737 .parent_hws = (const struct clk_hw*[]){ 1738 &disp0_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1739 }, 1740 .num_parents = 1, 1741 .flags = CLK_SET_RATE_PARENT, 1742 .ops = &clk_branch2_ops, 1743 }, 1744 }, 1745 }; 1746 1747 static struct clk_branch disp1_cc_mdss_dptx0_usb_router_link_intf_clk = { 1748 .halt_reg = 0x2064, 1749 .halt_check = BRANCH_HALT, 1750 .clkr = { 1751 .enable_reg = 0x2064, 1752 .enable_mask = BIT(0), 1753 .hw.init = &(const struct clk_init_data) { 1754 .name = "disp1_cc_mdss_dptx0_usb_router_link_intf_clk", 1755 .parent_hws = (const struct clk_hw*[]){ 1756 &disp1_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1757 }, 1758 .num_parents = 1, 1759 .flags = CLK_SET_RATE_PARENT, 1760 .ops = &clk_branch2_ops, 1761 }, 1762 }, 1763 }; 1764 1765 static struct clk_branch disp0_cc_mdss_dptx1_aux_clk = { 1766 .halt_reg = 0x20a0, 1767 .halt_check = BRANCH_HALT, 1768 .clkr = { 1769 .enable_reg = 0x20a0, 1770 .enable_mask = BIT(0), 1771 .hw.init = &(const struct clk_init_data) { 1772 .name = "disp0_cc_mdss_dptx1_aux_clk", 1773 .parent_hws = (const struct clk_hw*[]){ 1774 &disp0_cc_mdss_dptx1_aux_clk_src.clkr.hw, 1775 }, 1776 .num_parents = 1, 1777 .flags = CLK_SET_RATE_PARENT, 1778 .ops = &clk_branch2_ops, 1779 }, 1780 }, 1781 }; 1782 1783 static struct clk_branch disp1_cc_mdss_dptx1_aux_clk = { 1784 .halt_reg = 0x20a0, 1785 .halt_check = BRANCH_HALT, 1786 .clkr = { 1787 .enable_reg = 0x20a0, 1788 .enable_mask = BIT(0), 1789 .hw.init = &(const struct clk_init_data) { 1790 .name = "disp1_cc_mdss_dptx1_aux_clk", 1791 .parent_hws = (const struct clk_hw*[]){ 1792 &disp1_cc_mdss_dptx1_aux_clk_src.clkr.hw, 1793 }, 1794 .num_parents = 1, 1795 .flags = CLK_SET_RATE_PARENT, 1796 .ops = &clk_branch2_ops, 1797 }, 1798 }, 1799 }; 1800 1801 static struct clk_branch disp0_cc_mdss_dptx1_link_clk = { 1802 .halt_reg = 0x2084, 1803 .halt_check = BRANCH_HALT, 1804 .clkr = { 1805 .enable_reg = 0x2084, 1806 .enable_mask = BIT(0), 1807 .hw.init = &(const struct clk_init_data) { 1808 .name = "disp0_cc_mdss_dptx1_link_clk", 1809 .parent_hws = (const struct clk_hw*[]){ 1810 &disp0_cc_mdss_dptx1_link_clk_src.clkr.hw, 1811 }, 1812 .num_parents = 1, 1813 .flags = CLK_SET_RATE_PARENT, 1814 .ops = &clk_branch2_ops, 1815 }, 1816 }, 1817 }; 1818 1819 static struct clk_branch disp1_cc_mdss_dptx1_link_clk = { 1820 .halt_reg = 0x2084, 1821 .halt_check = BRANCH_HALT, 1822 .clkr = { 1823 .enable_reg = 0x2084, 1824 .enable_mask = BIT(0), 1825 .hw.init = &(const struct clk_init_data) { 1826 .name = "disp1_cc_mdss_dptx1_link_clk", 1827 .parent_hws = (const struct clk_hw*[]){ 1828 &disp1_cc_mdss_dptx1_link_clk_src.clkr.hw, 1829 }, 1830 .num_parents = 1, 1831 .flags = CLK_SET_RATE_PARENT, 1832 .ops = &clk_branch2_ops, 1833 }, 1834 }, 1835 }; 1836 1837 static struct clk_branch disp0_cc_mdss_dptx1_link_intf_clk = { 1838 .halt_reg = 0x2088, 1839 .halt_check = BRANCH_HALT, 1840 .clkr = { 1841 .enable_reg = 0x2088, 1842 .enable_mask = BIT(0), 1843 .hw.init = &(const struct clk_init_data) { 1844 .name = "disp0_cc_mdss_dptx1_link_intf_clk", 1845 .parent_hws = (const struct clk_hw*[]){ 1846 &disp0_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1847 }, 1848 .num_parents = 1, 1849 .flags = CLK_SET_RATE_PARENT, 1850 .ops = &clk_branch2_ops, 1851 }, 1852 }, 1853 }; 1854 1855 static struct clk_branch disp1_cc_mdss_dptx1_link_intf_clk = { 1856 .halt_reg = 0x2088, 1857 .halt_check = BRANCH_HALT, 1858 .clkr = { 1859 .enable_reg = 0x2088, 1860 .enable_mask = BIT(0), 1861 .hw.init = &(const struct clk_init_data) { 1862 .name = "disp1_cc_mdss_dptx1_link_intf_clk", 1863 .parent_hws = (const struct clk_hw*[]){ 1864 &disp1_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1865 }, 1866 .num_parents = 1, 1867 .flags = CLK_SET_RATE_PARENT, 1868 .ops = &clk_branch2_ops, 1869 }, 1870 }, 1871 }; 1872 1873 static struct clk_branch disp0_cc_mdss_dptx1_pixel0_clk = { 1874 .halt_reg = 0x2078, 1875 .halt_check = BRANCH_HALT, 1876 .clkr = { 1877 .enable_reg = 0x2078, 1878 .enable_mask = BIT(0), 1879 .hw.init = &(const struct clk_init_data) { 1880 .name = "disp0_cc_mdss_dptx1_pixel0_clk", 1881 .parent_hws = (const struct clk_hw*[]){ 1882 &disp0_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, 1883 }, 1884 .num_parents = 1, 1885 .flags = CLK_SET_RATE_PARENT, 1886 .ops = &clk_branch2_ops, 1887 }, 1888 }, 1889 }; 1890 1891 static struct clk_branch disp1_cc_mdss_dptx1_pixel0_clk = { 1892 .halt_reg = 0x2078, 1893 .halt_check = BRANCH_HALT, 1894 .clkr = { 1895 .enable_reg = 0x2078, 1896 .enable_mask = BIT(0), 1897 .hw.init = &(const struct clk_init_data) { 1898 .name = "disp1_cc_mdss_dptx1_pixel0_clk", 1899 .parent_hws = (const struct clk_hw*[]){ 1900 &disp1_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, 1901 }, 1902 .num_parents = 1, 1903 .flags = CLK_SET_RATE_PARENT, 1904 .ops = &clk_branch2_ops, 1905 }, 1906 }, 1907 }; 1908 1909 static struct clk_branch disp0_cc_mdss_dptx1_pixel1_clk = { 1910 .halt_reg = 0x236c, 1911 .halt_check = BRANCH_HALT, 1912 .clkr = { 1913 .enable_reg = 0x236c, 1914 .enable_mask = BIT(0), 1915 .hw.init = &(const struct clk_init_data) { 1916 .name = "disp0_cc_mdss_dptx1_pixel1_clk", 1917 .parent_hws = (const struct clk_hw*[]){ 1918 &disp0_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, 1919 }, 1920 .num_parents = 1, 1921 .flags = CLK_SET_RATE_PARENT, 1922 .ops = &clk_branch2_ops, 1923 }, 1924 }, 1925 }; 1926 1927 static struct clk_branch disp1_cc_mdss_dptx1_pixel1_clk = { 1928 .halt_reg = 0x236c, 1929 .halt_check = BRANCH_HALT, 1930 .clkr = { 1931 .enable_reg = 0x236c, 1932 .enable_mask = BIT(0), 1933 .hw.init = &(const struct clk_init_data) { 1934 .name = "disp1_cc_mdss_dptx1_pixel1_clk", 1935 .parent_hws = (const struct clk_hw*[]){ 1936 &disp1_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, 1937 }, 1938 .num_parents = 1, 1939 .flags = CLK_SET_RATE_PARENT, 1940 .ops = &clk_branch2_ops, 1941 }, 1942 }, 1943 }; 1944 1945 static struct clk_branch disp0_cc_mdss_dptx1_usb_router_link_intf_clk = { 1946 .halt_reg = 0x208c, 1947 .halt_check = BRANCH_HALT, 1948 .clkr = { 1949 .enable_reg = 0x208c, 1950 .enable_mask = BIT(0), 1951 .hw.init = &(const struct clk_init_data) { 1952 .name = "disp0_cc_mdss_dptx1_usb_router_link_intf_clk", 1953 .parent_hws = (const struct clk_hw*[]){ 1954 &disp0_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1955 }, 1956 .num_parents = 1, 1957 .flags = CLK_SET_RATE_PARENT, 1958 .ops = &clk_branch2_ops, 1959 }, 1960 }, 1961 }; 1962 1963 static struct clk_branch disp1_cc_mdss_dptx1_usb_router_link_intf_clk = { 1964 .halt_reg = 0x208c, 1965 .halt_check = BRANCH_HALT, 1966 .clkr = { 1967 .enable_reg = 0x208c, 1968 .enable_mask = BIT(0), 1969 .hw.init = &(const struct clk_init_data) { 1970 .name = "disp1_cc_mdss_dptx1_usb_router_link_intf_clk", 1971 .parent_hws = (const struct clk_hw*[]){ 1972 &disp1_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1973 }, 1974 .num_parents = 1, 1975 .flags = CLK_SET_RATE_PARENT, 1976 .ops = &clk_branch2_ops, 1977 }, 1978 }, 1979 }; 1980 1981 static struct clk_branch disp0_cc_mdss_dptx2_aux_clk = { 1982 .halt_reg = 0x20a4, 1983 .halt_check = BRANCH_HALT, 1984 .clkr = { 1985 .enable_reg = 0x20a4, 1986 .enable_mask = BIT(0), 1987 .hw.init = &(const struct clk_init_data) { 1988 .name = "disp0_cc_mdss_dptx2_aux_clk", 1989 .parent_hws = (const struct clk_hw*[]){ 1990 &disp0_cc_mdss_dptx2_aux_clk_src.clkr.hw, 1991 }, 1992 .num_parents = 1, 1993 .flags = CLK_SET_RATE_PARENT, 1994 .ops = &clk_branch2_ops, 1995 }, 1996 }, 1997 }; 1998 1999 static struct clk_branch disp1_cc_mdss_dptx2_aux_clk = { 2000 .halt_reg = 0x20a4, 2001 .halt_check = BRANCH_HALT, 2002 .clkr = { 2003 .enable_reg = 0x20a4, 2004 .enable_mask = BIT(0), 2005 .hw.init = &(const struct clk_init_data) { 2006 .name = "disp1_cc_mdss_dptx2_aux_clk", 2007 .parent_hws = (const struct clk_hw*[]){ 2008 &disp1_cc_mdss_dptx2_aux_clk_src.clkr.hw, 2009 }, 2010 .num_parents = 1, 2011 .flags = CLK_SET_RATE_PARENT, 2012 .ops = &clk_branch2_ops, 2013 }, 2014 }, 2015 }; 2016 2017 static struct clk_branch disp0_cc_mdss_dptx2_link_clk = { 2018 .halt_reg = 0x2090, 2019 .halt_check = BRANCH_HALT, 2020 .clkr = { 2021 .enable_reg = 0x2090, 2022 .enable_mask = BIT(0), 2023 .hw.init = &(const struct clk_init_data) { 2024 .name = "disp0_cc_mdss_dptx2_link_clk", 2025 .parent_hws = (const struct clk_hw*[]){ 2026 &disp0_cc_mdss_dptx2_link_clk_src.clkr.hw, 2027 }, 2028 .num_parents = 1, 2029 .flags = CLK_SET_RATE_PARENT, 2030 .ops = &clk_branch2_ops, 2031 }, 2032 }, 2033 }; 2034 2035 static struct clk_branch disp1_cc_mdss_dptx2_link_clk = { 2036 .halt_reg = 0x2090, 2037 .halt_check = BRANCH_HALT, 2038 .clkr = { 2039 .enable_reg = 0x2090, 2040 .enable_mask = BIT(0), 2041 .hw.init = &(const struct clk_init_data) { 2042 .name = "disp1_cc_mdss_dptx2_link_clk", 2043 .parent_hws = (const struct clk_hw*[]){ 2044 &disp1_cc_mdss_dptx2_link_clk_src.clkr.hw, 2045 }, 2046 .num_parents = 1, 2047 .flags = CLK_SET_RATE_PARENT, 2048 .ops = &clk_branch2_ops, 2049 }, 2050 }, 2051 }; 2052 2053 static struct clk_branch disp0_cc_mdss_dptx2_link_intf_clk = { 2054 .halt_reg = 0x2094, 2055 .halt_check = BRANCH_HALT, 2056 .clkr = { 2057 .enable_reg = 0x2094, 2058 .enable_mask = BIT(0), 2059 .hw.init = &(const struct clk_init_data) { 2060 .name = "disp0_cc_mdss_dptx2_link_intf_clk", 2061 .parent_hws = (const struct clk_hw*[]){ 2062 &disp0_cc_mdss_dptx2_link_div_clk_src.clkr.hw, 2063 }, 2064 .num_parents = 1, 2065 .flags = CLK_SET_RATE_PARENT, 2066 .ops = &clk_branch2_ops, 2067 }, 2068 }, 2069 }; 2070 2071 static struct clk_branch disp1_cc_mdss_dptx2_link_intf_clk = { 2072 .halt_reg = 0x2094, 2073 .halt_check = BRANCH_HALT, 2074 .clkr = { 2075 .enable_reg = 0x2094, 2076 .enable_mask = BIT(0), 2077 .hw.init = &(const struct clk_init_data) { 2078 .name = "disp1_cc_mdss_dptx2_link_intf_clk", 2079 .parent_hws = (const struct clk_hw*[]){ 2080 &disp1_cc_mdss_dptx2_link_div_clk_src.clkr.hw, 2081 }, 2082 .num_parents = 1, 2083 .flags = CLK_SET_RATE_PARENT, 2084 .ops = &clk_branch2_ops, 2085 }, 2086 }, 2087 }; 2088 2089 static struct clk_branch disp0_cc_mdss_dptx2_pixel0_clk = { 2090 .halt_reg = 0x207c, 2091 .halt_check = BRANCH_HALT, 2092 .clkr = { 2093 .enable_reg = 0x207c, 2094 .enable_mask = BIT(0), 2095 .hw.init = &(const struct clk_init_data) { 2096 .name = "disp0_cc_mdss_dptx2_pixel0_clk", 2097 .parent_hws = (const struct clk_hw*[]){ 2098 &disp0_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, 2099 }, 2100 .num_parents = 1, 2101 .flags = CLK_SET_RATE_PARENT, 2102 .ops = &clk_branch2_ops, 2103 }, 2104 }, 2105 }; 2106 2107 static struct clk_branch disp1_cc_mdss_dptx2_pixel0_clk = { 2108 .halt_reg = 0x207c, 2109 .halt_check = BRANCH_HALT, 2110 .clkr = { 2111 .enable_reg = 0x207c, 2112 .enable_mask = BIT(0), 2113 .hw.init = &(const struct clk_init_data) { 2114 .name = "disp1_cc_mdss_dptx2_pixel0_clk", 2115 .parent_hws = (const struct clk_hw*[]){ 2116 &disp1_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, 2117 }, 2118 .num_parents = 1, 2119 .flags = CLK_SET_RATE_PARENT, 2120 .ops = &clk_branch2_ops, 2121 }, 2122 }, 2123 }; 2124 2125 static struct clk_branch disp0_cc_mdss_dptx2_pixel1_clk = { 2126 .halt_reg = 0x2080, 2127 .halt_check = BRANCH_HALT, 2128 .clkr = { 2129 .enable_reg = 0x2080, 2130 .enable_mask = BIT(0), 2131 .hw.init = &(const struct clk_init_data) { 2132 .name = "disp0_cc_mdss_dptx2_pixel1_clk", 2133 .parent_hws = (const struct clk_hw*[]){ 2134 &disp0_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, 2135 }, 2136 .num_parents = 1, 2137 .flags = CLK_SET_RATE_PARENT, 2138 .ops = &clk_branch2_ops, 2139 }, 2140 }, 2141 }; 2142 2143 static struct clk_branch disp1_cc_mdss_dptx2_pixel1_clk = { 2144 .halt_reg = 0x2080, 2145 .halt_check = BRANCH_HALT, 2146 .clkr = { 2147 .enable_reg = 0x2080, 2148 .enable_mask = BIT(0), 2149 .hw.init = &(const struct clk_init_data) { 2150 .name = "disp1_cc_mdss_dptx2_pixel1_clk", 2151 .parent_hws = (const struct clk_hw*[]){ 2152 &disp1_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, 2153 }, 2154 .num_parents = 1, 2155 .flags = CLK_SET_RATE_PARENT, 2156 .ops = &clk_branch2_ops, 2157 }, 2158 }, 2159 }; 2160 2161 static struct clk_branch disp0_cc_mdss_dptx3_aux_clk = { 2162 .halt_reg = 0x20b8, 2163 .halt_check = BRANCH_HALT, 2164 .clkr = { 2165 .enable_reg = 0x20b8, 2166 .enable_mask = BIT(0), 2167 .hw.init = &(const struct clk_init_data) { 2168 .name = "disp0_cc_mdss_dptx3_aux_clk", 2169 .parent_hws = (const struct clk_hw*[]){ 2170 &disp0_cc_mdss_dptx3_aux_clk_src.clkr.hw, 2171 }, 2172 .num_parents = 1, 2173 .flags = CLK_SET_RATE_PARENT, 2174 .ops = &clk_branch2_ops, 2175 }, 2176 }, 2177 }; 2178 2179 static struct clk_branch disp1_cc_mdss_dptx3_aux_clk = { 2180 .halt_reg = 0x20b8, 2181 .halt_check = BRANCH_HALT, 2182 .clkr = { 2183 .enable_reg = 0x20b8, 2184 .enable_mask = BIT(0), 2185 .hw.init = &(const struct clk_init_data) { 2186 .name = "disp1_cc_mdss_dptx3_aux_clk", 2187 .parent_hws = (const struct clk_hw*[]){ 2188 &disp1_cc_mdss_dptx3_aux_clk_src.clkr.hw, 2189 }, 2190 .num_parents = 1, 2191 .flags = CLK_SET_RATE_PARENT, 2192 .ops = &clk_branch2_ops, 2193 }, 2194 }, 2195 }; 2196 2197 static struct clk_branch disp0_cc_mdss_dptx3_link_clk = { 2198 .halt_reg = 0x20ac, 2199 .halt_check = BRANCH_HALT, 2200 .clkr = { 2201 .enable_reg = 0x20ac, 2202 .enable_mask = BIT(0), 2203 .hw.init = &(const struct clk_init_data) { 2204 .name = "disp0_cc_mdss_dptx3_link_clk", 2205 .parent_hws = (const struct clk_hw*[]){ 2206 &disp0_cc_mdss_dptx3_link_clk_src.clkr.hw, 2207 }, 2208 .num_parents = 1, 2209 .flags = CLK_SET_RATE_PARENT, 2210 .ops = &clk_branch2_ops, 2211 }, 2212 }, 2213 }; 2214 2215 static struct clk_branch disp1_cc_mdss_dptx3_link_clk = { 2216 .halt_reg = 0x20ac, 2217 .halt_check = BRANCH_HALT, 2218 .clkr = { 2219 .enable_reg = 0x20ac, 2220 .enable_mask = BIT(0), 2221 .hw.init = &(const struct clk_init_data) { 2222 .name = "disp1_cc_mdss_dptx3_link_clk", 2223 .parent_hws = (const struct clk_hw*[]){ 2224 &disp1_cc_mdss_dptx3_link_clk_src.clkr.hw, 2225 }, 2226 .num_parents = 1, 2227 .flags = CLK_SET_RATE_PARENT, 2228 .ops = &clk_branch2_ops, 2229 }, 2230 }, 2231 }; 2232 2233 static struct clk_branch disp0_cc_mdss_dptx3_link_intf_clk = { 2234 .halt_reg = 0x20b0, 2235 .halt_check = BRANCH_HALT, 2236 .clkr = { 2237 .enable_reg = 0x20b0, 2238 .enable_mask = BIT(0), 2239 .hw.init = &(const struct clk_init_data) { 2240 .name = "disp0_cc_mdss_dptx3_link_intf_clk", 2241 .parent_hws = (const struct clk_hw*[]){ 2242 &disp0_cc_mdss_dptx3_link_div_clk_src.clkr.hw, 2243 }, 2244 .num_parents = 1, 2245 .flags = CLK_SET_RATE_PARENT, 2246 .ops = &clk_branch2_ops, 2247 }, 2248 }, 2249 }; 2250 2251 static struct clk_branch disp1_cc_mdss_dptx3_link_intf_clk = { 2252 .halt_reg = 0x20b0, 2253 .halt_check = BRANCH_HALT, 2254 .clkr = { 2255 .enable_reg = 0x20b0, 2256 .enable_mask = BIT(0), 2257 .hw.init = &(const struct clk_init_data) { 2258 .name = "disp1_cc_mdss_dptx3_link_intf_clk", 2259 .parent_hws = (const struct clk_hw*[]){ 2260 &disp1_cc_mdss_dptx3_link_div_clk_src.clkr.hw, 2261 }, 2262 .num_parents = 1, 2263 .flags = CLK_SET_RATE_PARENT, 2264 .ops = &clk_branch2_ops, 2265 }, 2266 }, 2267 }; 2268 2269 static struct clk_branch disp0_cc_mdss_dptx3_pixel0_clk = { 2270 .halt_reg = 0x20a8, 2271 .halt_check = BRANCH_HALT, 2272 .clkr = { 2273 .enable_reg = 0x20a8, 2274 .enable_mask = BIT(0), 2275 .hw.init = &(const struct clk_init_data) { 2276 .name = "disp0_cc_mdss_dptx3_pixel0_clk", 2277 .parent_hws = (const struct clk_hw*[]){ 2278 &disp0_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, 2279 }, 2280 .num_parents = 1, 2281 .flags = CLK_SET_RATE_PARENT, 2282 .ops = &clk_branch2_ops, 2283 }, 2284 }, 2285 }; 2286 2287 static struct clk_branch disp1_cc_mdss_dptx3_pixel0_clk = { 2288 .halt_reg = 0x20a8, 2289 .halt_check = BRANCH_HALT, 2290 .clkr = { 2291 .enable_reg = 0x20a8, 2292 .enable_mask = BIT(0), 2293 .hw.init = &(const struct clk_init_data) { 2294 .name = "disp1_cc_mdss_dptx3_pixel0_clk", 2295 .parent_hws = (const struct clk_hw*[]){ 2296 &disp1_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, 2297 }, 2298 .num_parents = 1, 2299 .flags = CLK_SET_RATE_PARENT, 2300 .ops = &clk_branch2_ops, 2301 }, 2302 }, 2303 }; 2304 2305 static struct clk_branch disp0_cc_mdss_esc0_clk = { 2306 .halt_reg = 0x2054, 2307 .halt_check = BRANCH_HALT, 2308 .clkr = { 2309 .enable_reg = 0x2054, 2310 .enable_mask = BIT(0), 2311 .hw.init = &(const struct clk_init_data) { 2312 .name = "disp0_cc_mdss_esc0_clk", 2313 .parent_hws = (const struct clk_hw*[]){ 2314 &disp0_cc_mdss_esc0_clk_src.clkr.hw, 2315 }, 2316 .num_parents = 1, 2317 .flags = CLK_SET_RATE_PARENT, 2318 .ops = &clk_branch2_ops, 2319 }, 2320 }, 2321 }; 2322 2323 static struct clk_branch disp1_cc_mdss_esc0_clk = { 2324 .halt_reg = 0x2054, 2325 .halt_check = BRANCH_HALT, 2326 .clkr = { 2327 .enable_reg = 0x2054, 2328 .enable_mask = BIT(0), 2329 .hw.init = &(const struct clk_init_data) { 2330 .name = "disp1_cc_mdss_esc0_clk", 2331 .parent_hws = (const struct clk_hw*[]){ 2332 &disp1_cc_mdss_esc0_clk_src.clkr.hw, 2333 }, 2334 .num_parents = 1, 2335 .flags = CLK_SET_RATE_PARENT, 2336 .ops = &clk_branch2_ops, 2337 }, 2338 }, 2339 }; 2340 2341 static struct clk_branch disp0_cc_mdss_esc1_clk = { 2342 .halt_reg = 0x2058, 2343 .halt_check = BRANCH_HALT, 2344 .clkr = { 2345 .enable_reg = 0x2058, 2346 .enable_mask = BIT(0), 2347 .hw.init = &(const struct clk_init_data) { 2348 .name = "disp0_cc_mdss_esc1_clk", 2349 .parent_hws = (const struct clk_hw*[]){ 2350 &disp0_cc_mdss_esc1_clk_src.clkr.hw, 2351 }, 2352 .num_parents = 1, 2353 .flags = CLK_SET_RATE_PARENT, 2354 .ops = &clk_branch2_ops, 2355 }, 2356 }, 2357 }; 2358 2359 static struct clk_branch disp1_cc_mdss_esc1_clk = { 2360 .halt_reg = 0x2058, 2361 .halt_check = BRANCH_HALT, 2362 .clkr = { 2363 .enable_reg = 0x2058, 2364 .enable_mask = BIT(0), 2365 .hw.init = &(const struct clk_init_data) { 2366 .name = "disp1_cc_mdss_esc1_clk", 2367 .parent_hws = (const struct clk_hw*[]){ 2368 &disp1_cc_mdss_esc1_clk_src.clkr.hw, 2369 }, 2370 .num_parents = 1, 2371 .flags = CLK_SET_RATE_PARENT, 2372 .ops = &clk_branch2_ops, 2373 }, 2374 }, 2375 }; 2376 2377 static struct clk_branch disp0_cc_mdss_mdp1_clk = { 2378 .halt_reg = 0x2014, 2379 .halt_check = BRANCH_HALT, 2380 .clkr = { 2381 .enable_reg = 0x2014, 2382 .enable_mask = BIT(0), 2383 .hw.init = &(const struct clk_init_data) { 2384 .name = "disp0_cc_mdss_mdp1_clk", 2385 .parent_hws = (const struct clk_hw*[]){ 2386 &disp0_cc_mdss_mdp_clk_src.clkr.hw, 2387 }, 2388 .num_parents = 1, 2389 .flags = CLK_SET_RATE_PARENT, 2390 .ops = &clk_branch2_ops, 2391 }, 2392 }, 2393 }; 2394 2395 static struct clk_branch disp1_cc_mdss_mdp1_clk = { 2396 .halt_reg = 0x2014, 2397 .halt_check = BRANCH_HALT, 2398 .clkr = { 2399 .enable_reg = 0x2014, 2400 .enable_mask = BIT(0), 2401 .hw.init = &(const struct clk_init_data) { 2402 .name = "disp1_cc_mdss_mdp1_clk", 2403 .parent_hws = (const struct clk_hw*[]){ 2404 &disp1_cc_mdss_mdp_clk_src.clkr.hw, 2405 }, 2406 .num_parents = 1, 2407 .flags = CLK_SET_RATE_PARENT, 2408 .ops = &clk_branch2_ops, 2409 }, 2410 }, 2411 }; 2412 2413 static struct clk_branch disp0_cc_mdss_mdp_clk = { 2414 .halt_reg = 0x200c, 2415 .halt_check = BRANCH_HALT, 2416 .clkr = { 2417 .enable_reg = 0x200c, 2418 .enable_mask = BIT(0), 2419 .hw.init = &(const struct clk_init_data) { 2420 .name = "disp0_cc_mdss_mdp_clk", 2421 .parent_hws = (const struct clk_hw*[]){ 2422 &disp0_cc_mdss_mdp_clk_src.clkr.hw, 2423 }, 2424 .num_parents = 1, 2425 .flags = CLK_SET_RATE_PARENT, 2426 .ops = &clk_branch2_ops, 2427 }, 2428 }, 2429 }; 2430 2431 static struct clk_branch disp1_cc_mdss_mdp_clk = { 2432 .halt_reg = 0x200c, 2433 .halt_check = BRANCH_HALT, 2434 .clkr = { 2435 .enable_reg = 0x200c, 2436 .enable_mask = BIT(0), 2437 .hw.init = &(const struct clk_init_data) { 2438 .name = "disp1_cc_mdss_mdp_clk", 2439 .parent_hws = (const struct clk_hw*[]){ 2440 &disp1_cc_mdss_mdp_clk_src.clkr.hw, 2441 }, 2442 .num_parents = 1, 2443 .flags = CLK_SET_RATE_PARENT, 2444 .ops = &clk_branch2_ops, 2445 }, 2446 }, 2447 }; 2448 2449 static struct clk_branch disp0_cc_mdss_mdp_lut1_clk = { 2450 .halt_reg = 0x2034, 2451 .halt_check = BRANCH_HALT, 2452 .clkr = { 2453 .enable_reg = 0x2034, 2454 .enable_mask = BIT(0), 2455 .hw.init = &(const struct clk_init_data) { 2456 .name = "disp0_cc_mdss_mdp_lut1_clk", 2457 .parent_hws = (const struct clk_hw*[]){ 2458 &disp0_cc_mdss_mdp_clk_src.clkr.hw, 2459 }, 2460 .num_parents = 1, 2461 .flags = CLK_SET_RATE_PARENT, 2462 .ops = &clk_branch2_ops, 2463 }, 2464 }, 2465 }; 2466 2467 static struct clk_branch disp1_cc_mdss_mdp_lut1_clk = { 2468 .halt_reg = 0x2034, 2469 .halt_check = BRANCH_HALT, 2470 .clkr = { 2471 .enable_reg = 0x2034, 2472 .enable_mask = BIT(0), 2473 .hw.init = &(const struct clk_init_data) { 2474 .name = "disp1_cc_mdss_mdp_lut1_clk", 2475 .parent_hws = (const struct clk_hw*[]){ 2476 &disp1_cc_mdss_mdp_clk_src.clkr.hw, 2477 }, 2478 .num_parents = 1, 2479 .flags = CLK_SET_RATE_PARENT, 2480 .ops = &clk_branch2_ops, 2481 }, 2482 }, 2483 }; 2484 2485 static struct clk_branch disp0_cc_mdss_mdp_lut_clk = { 2486 .halt_reg = 0x202c, 2487 .halt_check = BRANCH_HALT_VOTED, 2488 .clkr = { 2489 .enable_reg = 0x202c, 2490 .enable_mask = BIT(0), 2491 .hw.init = &(const struct clk_init_data) { 2492 .name = "disp0_cc_mdss_mdp_lut_clk", 2493 .parent_hws = (const struct clk_hw*[]){ 2494 &disp0_cc_mdss_mdp_clk_src.clkr.hw, 2495 }, 2496 .num_parents = 1, 2497 .flags = CLK_SET_RATE_PARENT, 2498 .ops = &clk_branch2_ops, 2499 }, 2500 }, 2501 }; 2502 2503 static struct clk_branch disp1_cc_mdss_mdp_lut_clk = { 2504 .halt_reg = 0x202c, 2505 .halt_check = BRANCH_HALT_VOTED, 2506 .clkr = { 2507 .enable_reg = 0x202c, 2508 .enable_mask = BIT(0), 2509 .hw.init = &(const struct clk_init_data) { 2510 .name = "disp1_cc_mdss_mdp_lut_clk", 2511 .parent_hws = (const struct clk_hw*[]){ 2512 &disp1_cc_mdss_mdp_clk_src.clkr.hw, 2513 }, 2514 .num_parents = 1, 2515 .flags = CLK_SET_RATE_PARENT, 2516 .ops = &clk_branch2_ops, 2517 }, 2518 }, 2519 }; 2520 2521 static struct clk_branch disp0_cc_mdss_non_gdsc_ahb_clk = { 2522 .halt_reg = 0x4004, 2523 .halt_check = BRANCH_HALT_VOTED, 2524 .clkr = { 2525 .enable_reg = 0x4004, 2526 .enable_mask = BIT(0), 2527 .hw.init = &(const struct clk_init_data) { 2528 .name = "disp0_cc_mdss_non_gdsc_ahb_clk", 2529 .parent_hws = (const struct clk_hw*[]){ 2530 &disp0_cc_mdss_ahb_clk_src.clkr.hw, 2531 }, 2532 .num_parents = 1, 2533 .flags = CLK_SET_RATE_PARENT, 2534 .ops = &clk_branch2_ops, 2535 }, 2536 }, 2537 }; 2538 2539 static struct clk_branch disp1_cc_mdss_non_gdsc_ahb_clk = { 2540 .halt_reg = 0x4004, 2541 .halt_check = BRANCH_HALT_VOTED, 2542 .clkr = { 2543 .enable_reg = 0x4004, 2544 .enable_mask = BIT(0), 2545 .hw.init = &(const struct clk_init_data) { 2546 .name = "disp1_cc_mdss_non_gdsc_ahb_clk", 2547 .parent_hws = (const struct clk_hw*[]){ 2548 &disp1_cc_mdss_ahb_clk_src.clkr.hw, 2549 }, 2550 .num_parents = 1, 2551 .flags = CLK_SET_RATE_PARENT, 2552 .ops = &clk_branch2_ops, 2553 }, 2554 }, 2555 }; 2556 2557 static struct clk_branch disp0_cc_mdss_pclk0_clk = { 2558 .halt_reg = 0x2004, 2559 .halt_check = BRANCH_HALT, 2560 .clkr = { 2561 .enable_reg = 0x2004, 2562 .enable_mask = BIT(0), 2563 .hw.init = &(const struct clk_init_data) { 2564 .name = "disp0_cc_mdss_pclk0_clk", 2565 .parent_hws = (const struct clk_hw*[]){ 2566 &disp0_cc_mdss_pclk0_clk_src.clkr.hw, 2567 }, 2568 .num_parents = 1, 2569 .flags = CLK_SET_RATE_PARENT, 2570 .ops = &clk_branch2_ops, 2571 }, 2572 }, 2573 }; 2574 2575 static struct clk_branch disp1_cc_mdss_pclk0_clk = { 2576 .halt_reg = 0x2004, 2577 .halt_check = BRANCH_HALT, 2578 .clkr = { 2579 .enable_reg = 0x2004, 2580 .enable_mask = BIT(0), 2581 .hw.init = &(const struct clk_init_data) { 2582 .name = "disp1_cc_mdss_pclk0_clk", 2583 .parent_hws = (const struct clk_hw*[]){ 2584 &disp1_cc_mdss_pclk0_clk_src.clkr.hw, 2585 }, 2586 .num_parents = 1, 2587 .flags = CLK_SET_RATE_PARENT, 2588 .ops = &clk_branch2_ops, 2589 }, 2590 }, 2591 }; 2592 2593 static struct clk_branch disp0_cc_mdss_pclk1_clk = { 2594 .halt_reg = 0x2008, 2595 .halt_check = BRANCH_HALT, 2596 .clkr = { 2597 .enable_reg = 0x2008, 2598 .enable_mask = BIT(0), 2599 .hw.init = &(const struct clk_init_data) { 2600 .name = "disp0_cc_mdss_pclk1_clk", 2601 .parent_hws = (const struct clk_hw*[]){ 2602 &disp0_cc_mdss_pclk1_clk_src.clkr.hw, 2603 }, 2604 .num_parents = 1, 2605 .flags = CLK_SET_RATE_PARENT, 2606 .ops = &clk_branch2_ops, 2607 }, 2608 }, 2609 }; 2610 2611 static struct clk_branch disp1_cc_mdss_pclk1_clk = { 2612 .halt_reg = 0x2008, 2613 .halt_check = BRANCH_HALT, 2614 .clkr = { 2615 .enable_reg = 0x2008, 2616 .enable_mask = BIT(0), 2617 .hw.init = &(const struct clk_init_data) { 2618 .name = "disp1_cc_mdss_pclk1_clk", 2619 .parent_hws = (const struct clk_hw*[]){ 2620 &disp1_cc_mdss_pclk1_clk_src.clkr.hw, 2621 }, 2622 .num_parents = 1, 2623 .flags = CLK_SET_RATE_PARENT, 2624 .ops = &clk_branch2_ops, 2625 }, 2626 }, 2627 }; 2628 2629 static struct clk_branch disp0_cc_mdss_rot1_clk = { 2630 .halt_reg = 0x2024, 2631 .halt_check = BRANCH_HALT, 2632 .clkr = { 2633 .enable_reg = 0x2024, 2634 .enable_mask = BIT(0), 2635 .hw.init = &(const struct clk_init_data) { 2636 .name = "disp0_cc_mdss_rot1_clk", 2637 .parent_hws = (const struct clk_hw*[]){ 2638 &disp0_cc_mdss_rot_clk_src.clkr.hw, 2639 }, 2640 .num_parents = 1, 2641 .flags = CLK_SET_RATE_PARENT, 2642 .ops = &clk_branch2_ops, 2643 }, 2644 }, 2645 }; 2646 2647 static struct clk_branch disp1_cc_mdss_rot1_clk = { 2648 .halt_reg = 0x2024, 2649 .halt_check = BRANCH_HALT, 2650 .clkr = { 2651 .enable_reg = 0x2024, 2652 .enable_mask = BIT(0), 2653 .hw.init = &(const struct clk_init_data) { 2654 .name = "disp1_cc_mdss_rot1_clk", 2655 .parent_hws = (const struct clk_hw*[]){ 2656 &disp1_cc_mdss_rot_clk_src.clkr.hw, 2657 }, 2658 .num_parents = 1, 2659 .flags = CLK_SET_RATE_PARENT, 2660 .ops = &clk_branch2_ops, 2661 }, 2662 }, 2663 }; 2664 2665 static struct clk_branch disp0_cc_mdss_rot_clk = { 2666 .halt_reg = 0x201c, 2667 .halt_check = BRANCH_HALT, 2668 .clkr = { 2669 .enable_reg = 0x201c, 2670 .enable_mask = BIT(0), 2671 .hw.init = &(const struct clk_init_data) { 2672 .name = "disp0_cc_mdss_rot_clk", 2673 .parent_hws = (const struct clk_hw*[]){ 2674 &disp0_cc_mdss_rot_clk_src.clkr.hw, 2675 }, 2676 .num_parents = 1, 2677 .flags = CLK_SET_RATE_PARENT, 2678 .ops = &clk_branch2_ops, 2679 }, 2680 }, 2681 }; 2682 2683 static struct clk_branch disp1_cc_mdss_rot_clk = { 2684 .halt_reg = 0x201c, 2685 .halt_check = BRANCH_HALT, 2686 .clkr = { 2687 .enable_reg = 0x201c, 2688 .enable_mask = BIT(0), 2689 .hw.init = &(const struct clk_init_data) { 2690 .name = "disp1_cc_mdss_rot_clk", 2691 .parent_hws = (const struct clk_hw*[]){ 2692 &disp1_cc_mdss_rot_clk_src.clkr.hw, 2693 }, 2694 .num_parents = 1, 2695 .flags = CLK_SET_RATE_PARENT, 2696 .ops = &clk_branch2_ops, 2697 }, 2698 }, 2699 }; 2700 2701 static struct clk_branch disp0_cc_mdss_rscc_ahb_clk = { 2702 .halt_reg = 0x400c, 2703 .halt_check = BRANCH_HALT, 2704 .clkr = { 2705 .enable_reg = 0x400c, 2706 .enable_mask = BIT(0), 2707 .hw.init = &(const struct clk_init_data) { 2708 .name = "disp0_cc_mdss_rscc_ahb_clk", 2709 .parent_hws = (const struct clk_hw*[]){ 2710 &disp0_cc_mdss_ahb_clk_src.clkr.hw, 2711 }, 2712 .num_parents = 1, 2713 .flags = CLK_SET_RATE_PARENT, 2714 .ops = &clk_branch2_ops, 2715 }, 2716 }, 2717 }; 2718 2719 static struct clk_branch disp1_cc_mdss_rscc_ahb_clk = { 2720 .halt_reg = 0x400c, 2721 .halt_check = BRANCH_HALT, 2722 .clkr = { 2723 .enable_reg = 0x400c, 2724 .enable_mask = BIT(0), 2725 .hw.init = &(const struct clk_init_data) { 2726 .name = "disp1_cc_mdss_rscc_ahb_clk", 2727 .parent_hws = (const struct clk_hw*[]){ 2728 &disp1_cc_mdss_ahb_clk_src.clkr.hw, 2729 }, 2730 .num_parents = 1, 2731 .flags = CLK_SET_RATE_PARENT, 2732 .ops = &clk_branch2_ops, 2733 }, 2734 }, 2735 }; 2736 2737 static struct clk_branch disp0_cc_mdss_rscc_vsync_clk = { 2738 .halt_reg = 0x4008, 2739 .halt_check = BRANCH_HALT, 2740 .clkr = { 2741 .enable_reg = 0x4008, 2742 .enable_mask = BIT(0), 2743 .hw.init = &(const struct clk_init_data) { 2744 .name = "disp0_cc_mdss_rscc_vsync_clk", 2745 .parent_hws = (const struct clk_hw*[]){ 2746 &disp0_cc_mdss_vsync_clk_src.clkr.hw, 2747 }, 2748 .num_parents = 1, 2749 .flags = CLK_SET_RATE_PARENT, 2750 .ops = &clk_branch2_ops, 2751 }, 2752 }, 2753 }; 2754 2755 static struct clk_branch disp1_cc_mdss_rscc_vsync_clk = { 2756 .halt_reg = 0x4008, 2757 .halt_check = BRANCH_HALT, 2758 .clkr = { 2759 .enable_reg = 0x4008, 2760 .enable_mask = BIT(0), 2761 .hw.init = &(const struct clk_init_data) { 2762 .name = "disp1_cc_mdss_rscc_vsync_clk", 2763 .parent_hws = (const struct clk_hw*[]){ 2764 &disp1_cc_mdss_vsync_clk_src.clkr.hw, 2765 }, 2766 .num_parents = 1, 2767 .flags = CLK_SET_RATE_PARENT, 2768 .ops = &clk_branch2_ops, 2769 }, 2770 }, 2771 }; 2772 2773 static struct clk_branch disp0_cc_mdss_vsync1_clk = { 2774 .halt_reg = 0x2040, 2775 .halt_check = BRANCH_HALT, 2776 .clkr = { 2777 .enable_reg = 0x2040, 2778 .enable_mask = BIT(0), 2779 .hw.init = &(const struct clk_init_data) { 2780 .name = "disp0_cc_mdss_vsync1_clk", 2781 .parent_hws = (const struct clk_hw*[]){ 2782 &disp0_cc_mdss_vsync_clk_src.clkr.hw, 2783 }, 2784 .num_parents = 1, 2785 .flags = CLK_SET_RATE_PARENT, 2786 .ops = &clk_branch2_ops, 2787 }, 2788 }, 2789 }; 2790 2791 static struct clk_branch disp1_cc_mdss_vsync1_clk = { 2792 .halt_reg = 0x2040, 2793 .halt_check = BRANCH_HALT, 2794 .clkr = { 2795 .enable_reg = 0x2040, 2796 .enable_mask = BIT(0), 2797 .hw.init = &(const struct clk_init_data) { 2798 .name = "disp1_cc_mdss_vsync1_clk", 2799 .parent_hws = (const struct clk_hw*[]){ 2800 &disp1_cc_mdss_vsync_clk_src.clkr.hw, 2801 }, 2802 .num_parents = 1, 2803 .flags = CLK_SET_RATE_PARENT, 2804 .ops = &clk_branch2_ops, 2805 }, 2806 }, 2807 }; 2808 2809 static struct clk_branch disp0_cc_mdss_vsync_clk = { 2810 .halt_reg = 0x203c, 2811 .halt_check = BRANCH_HALT, 2812 .clkr = { 2813 .enable_reg = 0x203c, 2814 .enable_mask = BIT(0), 2815 .hw.init = &(const struct clk_init_data) { 2816 .name = "disp0_cc_mdss_vsync_clk", 2817 .parent_hws = (const struct clk_hw*[]){ 2818 &disp0_cc_mdss_vsync_clk_src.clkr.hw, 2819 }, 2820 .num_parents = 1, 2821 .flags = CLK_SET_RATE_PARENT, 2822 .ops = &clk_branch2_ops, 2823 }, 2824 }, 2825 }; 2826 2827 static struct clk_branch disp1_cc_mdss_vsync_clk = { 2828 .halt_reg = 0x203c, 2829 .halt_check = BRANCH_HALT, 2830 .clkr = { 2831 .enable_reg = 0x203c, 2832 .enable_mask = BIT(0), 2833 .hw.init = &(const struct clk_init_data) { 2834 .name = "disp1_cc_mdss_vsync_clk", 2835 .parent_hws = (const struct clk_hw*[]){ 2836 &disp1_cc_mdss_vsync_clk_src.clkr.hw, 2837 }, 2838 .num_parents = 1, 2839 .flags = CLK_SET_RATE_PARENT, 2840 .ops = &clk_branch2_ops, 2841 }, 2842 }, 2843 }; 2844 2845 static struct clk_branch disp0_cc_sleep_clk = { 2846 .halt_reg = 0x6078, 2847 .halt_check = BRANCH_HALT, 2848 .clkr = { 2849 .enable_reg = 0x6078, 2850 .enable_mask = BIT(0), 2851 .hw.init = &(const struct clk_init_data) { 2852 .name = "disp0_cc_sleep_clk", 2853 .parent_hws = (const struct clk_hw*[]){ 2854 &disp0_cc_sleep_clk_src.clkr.hw, 2855 }, 2856 .num_parents = 1, 2857 .flags = CLK_SET_RATE_PARENT, 2858 .ops = &clk_branch2_ops, 2859 }, 2860 }, 2861 }; 2862 2863 static struct clk_branch disp1_cc_sleep_clk = { 2864 .halt_reg = 0x6078, 2865 .halt_check = BRANCH_HALT, 2866 .clkr = { 2867 .enable_reg = 0x6078, 2868 .enable_mask = BIT(0), 2869 .hw.init = &(const struct clk_init_data) { 2870 .name = "disp1_cc_sleep_clk", 2871 .parent_hws = (const struct clk_hw*[]){ 2872 &disp1_cc_sleep_clk_src.clkr.hw, 2873 }, 2874 .num_parents = 1, 2875 .flags = CLK_SET_RATE_PARENT, 2876 .ops = &clk_branch2_ops, 2877 }, 2878 }, 2879 }; 2880 2881 static struct clk_regmap *disp0_cc_sc8280xp_clocks[] = { 2882 [DISP_CC_MDSS_AHB1_CLK] = &disp0_cc_mdss_ahb1_clk.clkr, 2883 [DISP_CC_MDSS_AHB_CLK] = &disp0_cc_mdss_ahb_clk.clkr, 2884 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp0_cc_mdss_ahb_clk_src.clkr, 2885 [DISP_CC_MDSS_BYTE0_CLK] = &disp0_cc_mdss_byte0_clk.clkr, 2886 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp0_cc_mdss_byte0_clk_src.clkr, 2887 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp0_cc_mdss_byte0_div_clk_src.clkr, 2888 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp0_cc_mdss_byte0_intf_clk.clkr, 2889 [DISP_CC_MDSS_BYTE1_CLK] = &disp0_cc_mdss_byte1_clk.clkr, 2890 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp0_cc_mdss_byte1_clk_src.clkr, 2891 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp0_cc_mdss_byte1_div_clk_src.clkr, 2892 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp0_cc_mdss_byte1_intf_clk.clkr, 2893 [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp0_cc_mdss_dptx0_aux_clk.clkr, 2894 [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp0_cc_mdss_dptx0_aux_clk_src.clkr, 2895 [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp0_cc_mdss_dptx0_link_clk.clkr, 2896 [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp0_cc_mdss_dptx0_link_clk_src.clkr, 2897 [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp0_cc_mdss_dptx0_link_div_clk_src.clkr, 2898 [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp0_cc_mdss_dptx0_link_intf_clk.clkr, 2899 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp0_cc_mdss_dptx0_pixel0_clk.clkr, 2900 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp0_cc_mdss_dptx0_pixel0_clk_src.clkr, 2901 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp0_cc_mdss_dptx0_pixel1_clk.clkr, 2902 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp0_cc_mdss_dptx0_pixel1_clk_src.clkr, 2903 [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = &disp0_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, 2904 [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp0_cc_mdss_dptx1_aux_clk.clkr, 2905 [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp0_cc_mdss_dptx1_aux_clk_src.clkr, 2906 [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp0_cc_mdss_dptx1_link_clk.clkr, 2907 [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp0_cc_mdss_dptx1_link_clk_src.clkr, 2908 [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp0_cc_mdss_dptx1_link_div_clk_src.clkr, 2909 [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp0_cc_mdss_dptx1_link_intf_clk.clkr, 2910 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp0_cc_mdss_dptx1_pixel0_clk.clkr, 2911 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp0_cc_mdss_dptx1_pixel0_clk_src.clkr, 2912 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp0_cc_mdss_dptx1_pixel1_clk.clkr, 2913 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp0_cc_mdss_dptx1_pixel1_clk_src.clkr, 2914 [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] = &disp0_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, 2915 [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp0_cc_mdss_dptx2_aux_clk.clkr, 2916 [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp0_cc_mdss_dptx2_aux_clk_src.clkr, 2917 [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp0_cc_mdss_dptx2_link_clk.clkr, 2918 [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp0_cc_mdss_dptx2_link_clk_src.clkr, 2919 [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp0_cc_mdss_dptx2_link_div_clk_src.clkr, 2920 [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp0_cc_mdss_dptx2_link_intf_clk.clkr, 2921 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp0_cc_mdss_dptx2_pixel0_clk.clkr, 2922 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp0_cc_mdss_dptx2_pixel0_clk_src.clkr, 2923 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp0_cc_mdss_dptx2_pixel1_clk.clkr, 2924 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp0_cc_mdss_dptx2_pixel1_clk_src.clkr, 2925 [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp0_cc_mdss_dptx3_aux_clk.clkr, 2926 [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp0_cc_mdss_dptx3_aux_clk_src.clkr, 2927 [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp0_cc_mdss_dptx3_link_clk.clkr, 2928 [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp0_cc_mdss_dptx3_link_clk_src.clkr, 2929 [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp0_cc_mdss_dptx3_link_div_clk_src.clkr, 2930 [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp0_cc_mdss_dptx3_link_intf_clk.clkr, 2931 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp0_cc_mdss_dptx3_pixel0_clk.clkr, 2932 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp0_cc_mdss_dptx3_pixel0_clk_src.clkr, 2933 [DISP_CC_MDSS_ESC0_CLK] = &disp0_cc_mdss_esc0_clk.clkr, 2934 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp0_cc_mdss_esc0_clk_src.clkr, 2935 [DISP_CC_MDSS_ESC1_CLK] = &disp0_cc_mdss_esc1_clk.clkr, 2936 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp0_cc_mdss_esc1_clk_src.clkr, 2937 [DISP_CC_MDSS_MDP1_CLK] = &disp0_cc_mdss_mdp1_clk.clkr, 2938 [DISP_CC_MDSS_MDP_CLK] = &disp0_cc_mdss_mdp_clk.clkr, 2939 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp0_cc_mdss_mdp_clk_src.clkr, 2940 [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp0_cc_mdss_mdp_lut1_clk.clkr, 2941 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp0_cc_mdss_mdp_lut_clk.clkr, 2942 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp0_cc_mdss_non_gdsc_ahb_clk.clkr, 2943 [DISP_CC_MDSS_PCLK0_CLK] = &disp0_cc_mdss_pclk0_clk.clkr, 2944 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp0_cc_mdss_pclk0_clk_src.clkr, 2945 [DISP_CC_MDSS_PCLK1_CLK] = &disp0_cc_mdss_pclk1_clk.clkr, 2946 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp0_cc_mdss_pclk1_clk_src.clkr, 2947 [DISP_CC_MDSS_ROT1_CLK] = &disp0_cc_mdss_rot1_clk.clkr, 2948 [DISP_CC_MDSS_ROT_CLK] = &disp0_cc_mdss_rot_clk.clkr, 2949 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp0_cc_mdss_rot_clk_src.clkr, 2950 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp0_cc_mdss_rscc_ahb_clk.clkr, 2951 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp0_cc_mdss_rscc_vsync_clk.clkr, 2952 [DISP_CC_MDSS_VSYNC1_CLK] = &disp0_cc_mdss_vsync1_clk.clkr, 2953 [DISP_CC_MDSS_VSYNC_CLK] = &disp0_cc_mdss_vsync_clk.clkr, 2954 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp0_cc_mdss_vsync_clk_src.clkr, 2955 [DISP_CC_PLL0] = &disp0_cc_pll0.clkr, 2956 [DISP_CC_PLL1] = &disp0_cc_pll1.clkr, 2957 [DISP_CC_PLL1_OUT_EVEN] = &disp0_cc_pll1_out_even.clkr, 2958 [DISP_CC_PLL2] = &disp0_cc_pll2.clkr, 2959 [DISP_CC_SLEEP_CLK] = &disp0_cc_sleep_clk.clkr, 2960 [DISP_CC_SLEEP_CLK_SRC] = &disp0_cc_sleep_clk_src.clkr, 2961 }; 2962 2963 static struct clk_regmap *disp1_cc_sc8280xp_clocks[] = { 2964 [DISP_CC_MDSS_AHB1_CLK] = &disp1_cc_mdss_ahb1_clk.clkr, 2965 [DISP_CC_MDSS_AHB_CLK] = &disp1_cc_mdss_ahb_clk.clkr, 2966 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp1_cc_mdss_ahb_clk_src.clkr, 2967 [DISP_CC_MDSS_BYTE0_CLK] = &disp1_cc_mdss_byte0_clk.clkr, 2968 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp1_cc_mdss_byte0_clk_src.clkr, 2969 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp1_cc_mdss_byte0_div_clk_src.clkr, 2970 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp1_cc_mdss_byte0_intf_clk.clkr, 2971 [DISP_CC_MDSS_BYTE1_CLK] = &disp1_cc_mdss_byte1_clk.clkr, 2972 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp1_cc_mdss_byte1_clk_src.clkr, 2973 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp1_cc_mdss_byte1_div_clk_src.clkr, 2974 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp1_cc_mdss_byte1_intf_clk.clkr, 2975 [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp1_cc_mdss_dptx0_aux_clk.clkr, 2976 [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp1_cc_mdss_dptx0_aux_clk_src.clkr, 2977 [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp1_cc_mdss_dptx0_link_clk.clkr, 2978 [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp1_cc_mdss_dptx0_link_clk_src.clkr, 2979 [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp1_cc_mdss_dptx0_link_div_clk_src.clkr, 2980 [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp1_cc_mdss_dptx0_link_intf_clk.clkr, 2981 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp1_cc_mdss_dptx0_pixel0_clk.clkr, 2982 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp1_cc_mdss_dptx0_pixel0_clk_src.clkr, 2983 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp1_cc_mdss_dptx0_pixel1_clk.clkr, 2984 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp1_cc_mdss_dptx0_pixel1_clk_src.clkr, 2985 [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = &disp1_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, 2986 [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp1_cc_mdss_dptx1_aux_clk.clkr, 2987 [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp1_cc_mdss_dptx1_aux_clk_src.clkr, 2988 [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp1_cc_mdss_dptx1_link_clk.clkr, 2989 [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp1_cc_mdss_dptx1_link_clk_src.clkr, 2990 [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp1_cc_mdss_dptx1_link_div_clk_src.clkr, 2991 [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp1_cc_mdss_dptx1_link_intf_clk.clkr, 2992 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp1_cc_mdss_dptx1_pixel0_clk.clkr, 2993 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp1_cc_mdss_dptx1_pixel0_clk_src.clkr, 2994 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp1_cc_mdss_dptx1_pixel1_clk.clkr, 2995 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp1_cc_mdss_dptx1_pixel1_clk_src.clkr, 2996 [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] = &disp1_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, 2997 [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp1_cc_mdss_dptx2_aux_clk.clkr, 2998 [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp1_cc_mdss_dptx2_aux_clk_src.clkr, 2999 [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp1_cc_mdss_dptx2_link_clk.clkr, 3000 [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp1_cc_mdss_dptx2_link_clk_src.clkr, 3001 [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp1_cc_mdss_dptx2_link_div_clk_src.clkr, 3002 [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp1_cc_mdss_dptx2_link_intf_clk.clkr, 3003 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp1_cc_mdss_dptx2_pixel0_clk.clkr, 3004 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp1_cc_mdss_dptx2_pixel0_clk_src.clkr, 3005 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp1_cc_mdss_dptx2_pixel1_clk.clkr, 3006 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp1_cc_mdss_dptx2_pixel1_clk_src.clkr, 3007 [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp1_cc_mdss_dptx3_aux_clk.clkr, 3008 [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp1_cc_mdss_dptx3_aux_clk_src.clkr, 3009 [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp1_cc_mdss_dptx3_link_clk.clkr, 3010 [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp1_cc_mdss_dptx3_link_clk_src.clkr, 3011 [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp1_cc_mdss_dptx3_link_div_clk_src.clkr, 3012 [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp1_cc_mdss_dptx3_link_intf_clk.clkr, 3013 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp1_cc_mdss_dptx3_pixel0_clk.clkr, 3014 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp1_cc_mdss_dptx3_pixel0_clk_src.clkr, 3015 [DISP_CC_MDSS_ESC0_CLK] = &disp1_cc_mdss_esc0_clk.clkr, 3016 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp1_cc_mdss_esc0_clk_src.clkr, 3017 [DISP_CC_MDSS_ESC1_CLK] = &disp1_cc_mdss_esc1_clk.clkr, 3018 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp1_cc_mdss_esc1_clk_src.clkr, 3019 [DISP_CC_MDSS_MDP1_CLK] = &disp1_cc_mdss_mdp1_clk.clkr, 3020 [DISP_CC_MDSS_MDP_CLK] = &disp1_cc_mdss_mdp_clk.clkr, 3021 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp1_cc_mdss_mdp_clk_src.clkr, 3022 [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp1_cc_mdss_mdp_lut1_clk.clkr, 3023 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp1_cc_mdss_mdp_lut_clk.clkr, 3024 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp1_cc_mdss_non_gdsc_ahb_clk.clkr, 3025 [DISP_CC_MDSS_PCLK0_CLK] = &disp1_cc_mdss_pclk0_clk.clkr, 3026 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp1_cc_mdss_pclk0_clk_src.clkr, 3027 [DISP_CC_MDSS_PCLK1_CLK] = &disp1_cc_mdss_pclk1_clk.clkr, 3028 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp1_cc_mdss_pclk1_clk_src.clkr, 3029 [DISP_CC_MDSS_ROT1_CLK] = &disp1_cc_mdss_rot1_clk.clkr, 3030 [DISP_CC_MDSS_ROT_CLK] = &disp1_cc_mdss_rot_clk.clkr, 3031 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp1_cc_mdss_rot_clk_src.clkr, 3032 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp1_cc_mdss_rscc_ahb_clk.clkr, 3033 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp1_cc_mdss_rscc_vsync_clk.clkr, 3034 [DISP_CC_MDSS_VSYNC1_CLK] = &disp1_cc_mdss_vsync1_clk.clkr, 3035 [DISP_CC_MDSS_VSYNC_CLK] = &disp1_cc_mdss_vsync_clk.clkr, 3036 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp1_cc_mdss_vsync_clk_src.clkr, 3037 [DISP_CC_PLL0] = &disp1_cc_pll0.clkr, 3038 [DISP_CC_PLL1] = &disp1_cc_pll1.clkr, 3039 [DISP_CC_PLL1_OUT_EVEN] = &disp1_cc_pll1_out_even.clkr, 3040 [DISP_CC_PLL2] = &disp1_cc_pll2.clkr, 3041 [DISP_CC_SLEEP_CLK] = &disp1_cc_sleep_clk.clkr, 3042 [DISP_CC_SLEEP_CLK_SRC] = &disp1_cc_sleep_clk_src.clkr, 3043 }; 3044 3045 static const struct qcom_reset_map disp_cc_sc8280xp_resets[] = { 3046 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 }, 3047 [DISP_CC_MDSS_RSCC_BCR] = { 0x4000 }, 3048 }; 3049 3050 static struct gdsc disp0_mdss_gdsc = { 3051 .gdscr = 0x3000, 3052 .en_rest_wait_val = 0x2, 3053 .en_few_wait_val = 0x2, 3054 .clk_dis_wait_val = 0xf, 3055 .pd = { 3056 .name = "disp0_mdss_gdsc", 3057 }, 3058 .pwrsts = PWRSTS_OFF_ON, 3059 .flags = HW_CTRL | RETAIN_FF_ENABLE, 3060 }; 3061 3062 static struct gdsc disp1_mdss_gdsc = { 3063 .gdscr = 0x3000, 3064 .en_rest_wait_val = 0x2, 3065 .en_few_wait_val = 0x2, 3066 .clk_dis_wait_val = 0xf, 3067 .pd = { 3068 .name = "disp1_mdss_gdsc", 3069 }, 3070 .pwrsts = PWRSTS_OFF_ON, 3071 .flags = HW_CTRL | RETAIN_FF_ENABLE, 3072 }; 3073 3074 static struct gdsc disp0_mdss_int2_gdsc = { 3075 .gdscr = 0xa000, 3076 .en_rest_wait_val = 0x2, 3077 .en_few_wait_val = 0x2, 3078 .clk_dis_wait_val = 0xf, 3079 .pd = { 3080 .name = "disp0_mdss_int2_gdsc", 3081 }, 3082 .pwrsts = PWRSTS_OFF_ON, 3083 .flags = HW_CTRL | RETAIN_FF_ENABLE, 3084 }; 3085 3086 static struct gdsc disp1_mdss_int2_gdsc = { 3087 .gdscr = 0xa000, 3088 .en_rest_wait_val = 0x2, 3089 .en_few_wait_val = 0x2, 3090 .clk_dis_wait_val = 0xf, 3091 .pd = { 3092 .name = "disp1_mdss_int2_gdsc", 3093 }, 3094 .pwrsts = PWRSTS_OFF_ON, 3095 .flags = HW_CTRL | RETAIN_FF_ENABLE, 3096 }; 3097 3098 static struct gdsc *disp0_cc_sc8280xp_gdscs[] = { 3099 [MDSS_GDSC] = &disp0_mdss_gdsc, 3100 [MDSS_INT2_GDSC] = &disp0_mdss_int2_gdsc, 3101 }; 3102 3103 static struct gdsc *disp1_cc_sc8280xp_gdscs[] = { 3104 [MDSS_GDSC] = &disp1_mdss_gdsc, 3105 [MDSS_INT2_GDSC] = &disp1_mdss_int2_gdsc, 3106 }; 3107 3108 static const struct regmap_config disp_cc_sc8280xp_regmap_config = { 3109 .reg_bits = 32, 3110 .reg_stride = 4, 3111 .val_bits = 32, 3112 .max_register = 0x10000, 3113 .fast_io = true, 3114 }; 3115 3116 static const struct qcom_cc_desc disp0_cc_sc8280xp_desc = { 3117 .config = &disp_cc_sc8280xp_regmap_config, 3118 .clks = disp0_cc_sc8280xp_clocks, 3119 .num_clks = ARRAY_SIZE(disp0_cc_sc8280xp_clocks), 3120 .resets = disp_cc_sc8280xp_resets, 3121 .num_resets = ARRAY_SIZE(disp_cc_sc8280xp_resets), 3122 .gdscs = disp0_cc_sc8280xp_gdscs, 3123 .num_gdscs = ARRAY_SIZE(disp0_cc_sc8280xp_gdscs), 3124 }; 3125 3126 static const struct qcom_cc_desc disp1_cc_sc8280xp_desc = { 3127 .config = &disp_cc_sc8280xp_regmap_config, 3128 .clks = disp1_cc_sc8280xp_clocks, 3129 .num_clks = ARRAY_SIZE(disp1_cc_sc8280xp_clocks), 3130 .resets = disp_cc_sc8280xp_resets, 3131 .num_resets = ARRAY_SIZE(disp_cc_sc8280xp_resets), 3132 .gdscs = disp1_cc_sc8280xp_gdscs, 3133 .num_gdscs = ARRAY_SIZE(disp1_cc_sc8280xp_gdscs), 3134 }; 3135 3136 #define clkr_to_alpha_clk_pll(_clkr) container_of(_clkr, struct clk_alpha_pll, clkr) 3137 3138 static int disp_cc_sc8280xp_probe(struct platform_device *pdev) 3139 { 3140 const struct qcom_cc_desc *desc; 3141 struct regmap *regmap; 3142 int ret; 3143 3144 desc = device_get_match_data(&pdev->dev); 3145 3146 ret = devm_pm_runtime_enable(&pdev->dev); 3147 if (ret) 3148 return ret; 3149 3150 ret = devm_pm_clk_create(&pdev->dev); 3151 if (ret) 3152 return ret; 3153 3154 ret = pm_clk_add(&pdev->dev, NULL); 3155 if (ret < 0) { 3156 dev_err(&pdev->dev, "failed to acquire ahb clock\n"); 3157 return ret; 3158 } 3159 3160 ret = pm_runtime_resume_and_get(&pdev->dev); 3161 if (ret) 3162 return ret; 3163 3164 regmap = qcom_cc_map(pdev, desc); 3165 if (IS_ERR(regmap)) { 3166 ret = PTR_ERR(regmap); 3167 goto out_pm_runtime_put; 3168 } 3169 3170 clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL0]), regmap, &disp_cc_pll0_config); 3171 clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL1]), regmap, &disp_cc_pll1_config); 3172 clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL2]), regmap, &disp_cc_pll2_config); 3173 3174 ret = qcom_cc_really_probe(&pdev->dev, desc, regmap); 3175 if (ret) { 3176 dev_err(&pdev->dev, "Failed to register display clock controller\n"); 3177 goto out_pm_runtime_put; 3178 } 3179 3180 /* Keep some clocks always-on */ 3181 qcom_branch_set_clk_en(regmap, 0x605c); /* DISP_CC_XO_CLK */ 3182 3183 out_pm_runtime_put: 3184 pm_runtime_put_sync(&pdev->dev); 3185 3186 return ret; 3187 } 3188 3189 static const struct of_device_id disp_cc_sc8280xp_match_table[] = { 3190 { .compatible = "qcom,sc8280xp-dispcc0", .data = &disp0_cc_sc8280xp_desc }, 3191 { .compatible = "qcom,sc8280xp-dispcc1", .data = &disp1_cc_sc8280xp_desc }, 3192 { } 3193 }; 3194 MODULE_DEVICE_TABLE(of, disp_cc_sc8280xp_match_table); 3195 3196 static struct platform_driver disp_cc_sc8280xp_driver = { 3197 .probe = disp_cc_sc8280xp_probe, 3198 .driver = { 3199 .name = "disp_cc-sc8280xp", 3200 .of_match_table = disp_cc_sc8280xp_match_table, 3201 }, 3202 }; 3203 3204 module_platform_driver(disp_cc_sc8280xp_driver); 3205 3206 MODULE_DESCRIPTION("Qualcomm SC8280XP dispcc driver"); 3207 MODULE_LICENSE("GPL"); 3208