1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/kernel.h> 9 #include <linux/mod_devicetable.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/regmap.h> 13 14 #include <dt-bindings/clock/qcom,milos-dispcc.h> 15 16 #include "common.h" 17 #include "clk-alpha-pll.h" 18 #include "clk-branch.h" 19 #include "clk-pll.h" 20 #include "clk-rcg.h" 21 #include "clk-regmap.h" 22 #include "clk-regmap-divider.h" 23 #include "clk-regmap-mux.h" 24 #include "reset.h" 25 #include "gdsc.h" 26 27 /* Need to match the order of clocks in DT binding */ 28 enum { 29 DT_BI_TCXO, 30 DT_SLEEP_CLK, 31 DT_AHB_CLK, 32 DT_GCC_DISP_GPLL0_CLK, 33 DT_DSI0_PHY_PLL_OUT_BYTECLK, 34 DT_DSI0_PHY_PLL_OUT_DSICLK, 35 DT_DP0_PHY_PLL_LINK_CLK, 36 DT_DP0_PHY_PLL_VCO_DIV_CLK, 37 }; 38 39 #define DISP_CC_MISC_CMD 0xF000 40 41 enum { 42 P_BI_TCXO, 43 P_DISP_CC_PLL0_OUT_EVEN, 44 P_DISP_CC_PLL0_OUT_MAIN, 45 P_DP0_PHY_PLL_LINK_CLK, 46 P_DP0_PHY_PLL_VCO_DIV_CLK, 47 P_DSI0_PHY_PLL_OUT_BYTECLK, 48 P_DSI0_PHY_PLL_OUT_DSICLK, 49 P_GCC_DISP_GPLL0_CLK, 50 P_SLEEP_CLK, 51 }; 52 53 static const struct pll_vco lucid_ole_vco[] = { 54 { 249600000, 2300000000, 0 }, 55 }; 56 57 /* 257.142858 MHz Configuration */ 58 static const struct alpha_pll_config disp_cc_pll0_config = { 59 .l = 0xd, 60 .alpha = 0x6492, 61 .config_ctl_val = 0x20485699, 62 .config_ctl_hi_val = 0x00182261, 63 .config_ctl_hi1_val = 0x82aa299c, 64 .test_ctl_val = 0x00000000, 65 .test_ctl_hi_val = 0x00000003, 66 .test_ctl_hi1_val = 0x00009000, 67 .test_ctl_hi2_val = 0x00000034, 68 .user_ctl_val = 0x00000000, 69 .user_ctl_hi_val = 0x00000005, 70 }; 71 72 static struct clk_alpha_pll disp_cc_pll0 = { 73 .offset = 0x0, 74 .config = &disp_cc_pll0_config, 75 .vco_table = lucid_ole_vco, 76 .num_vco = ARRAY_SIZE(lucid_ole_vco), 77 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 78 .clkr = { 79 .hw.init = &(const struct clk_init_data) { 80 .name = "disp_cc_pll0", 81 .parent_data = &(const struct clk_parent_data) { 82 .index = DT_BI_TCXO, 83 }, 84 .num_parents = 1, 85 .ops = &clk_alpha_pll_lucid_evo_ops, 86 }, 87 }, 88 }; 89 90 static const struct parent_map disp_cc_parent_map_0[] = { 91 { P_BI_TCXO, 0 }, 92 }; 93 94 static const struct clk_parent_data disp_cc_parent_data_0[] = { 95 { .index = DT_BI_TCXO }, 96 }; 97 98 static const struct parent_map disp_cc_parent_map_1[] = { 99 { P_BI_TCXO, 0 }, 100 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 101 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 102 }; 103 104 static const struct clk_parent_data disp_cc_parent_data_1[] = { 105 { .index = DT_BI_TCXO }, 106 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, 107 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 108 }; 109 110 static const struct parent_map disp_cc_parent_map_2[] = { 111 { P_BI_TCXO, 0 }, 112 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 113 { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 }, 114 }; 115 116 static const struct clk_parent_data disp_cc_parent_data_2[] = { 117 { .index = DT_BI_TCXO }, 118 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 119 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK }, 120 }; 121 122 static const struct parent_map disp_cc_parent_map_3[] = { 123 { P_BI_TCXO, 0 }, 124 { P_GCC_DISP_GPLL0_CLK, 4 }, 125 }; 126 127 static const struct clk_parent_data disp_cc_parent_data_3[] = { 128 { .index = DT_BI_TCXO }, 129 { .index = DT_GCC_DISP_GPLL0_CLK }, 130 }; 131 132 static const struct parent_map disp_cc_parent_map_4[] = { 133 { P_BI_TCXO, 0 }, 134 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 135 }; 136 137 static const struct clk_parent_data disp_cc_parent_data_4[] = { 138 { .index = DT_BI_TCXO }, 139 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 140 }; 141 142 static const struct parent_map disp_cc_parent_map_5[] = { 143 { P_BI_TCXO, 0 }, 144 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 145 }; 146 147 static const struct clk_parent_data disp_cc_parent_data_5[] = { 148 { .index = DT_BI_TCXO }, 149 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 150 }; 151 152 static const struct parent_map disp_cc_parent_map_6[] = { 153 { P_BI_TCXO, 0 }, 154 { P_DISP_CC_PLL0_OUT_MAIN, 1 }, 155 { P_GCC_DISP_GPLL0_CLK, 4 }, 156 { P_DISP_CC_PLL0_OUT_EVEN, 6 }, 157 }; 158 159 static const struct clk_parent_data disp_cc_parent_data_6[] = { 160 { .index = DT_BI_TCXO }, 161 { .hw = &disp_cc_pll0.clkr.hw }, 162 { .index = DT_GCC_DISP_GPLL0_CLK }, 163 { .hw = &disp_cc_pll0.clkr.hw }, 164 }; 165 166 static const struct parent_map disp_cc_parent_map_7[] = { 167 { P_SLEEP_CLK, 0 }, 168 }; 169 170 static const struct clk_parent_data disp_cc_parent_data_7_ao[] = { 171 { .index = DT_SLEEP_CLK }, 172 }; 173 174 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { 175 F(19200000, P_BI_TCXO, 1, 0, 0), 176 F(37500000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0), 177 F(75000000, P_GCC_DISP_GPLL0_CLK, 4, 0, 0), 178 { } 179 }; 180 181 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { 182 .cmd_rcgr = 0x8130, 183 .mnd_width = 0, 184 .hid_width = 5, 185 .parent_map = disp_cc_parent_map_3, 186 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 187 .clkr.hw.init = &(const struct clk_init_data) { 188 .name = "disp_cc_mdss_ahb_clk_src", 189 .parent_data = disp_cc_parent_data_3, 190 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 191 .flags = CLK_SET_RATE_PARENT, 192 .ops = &clk_rcg2_shared_ops, 193 }, 194 }; 195 196 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { 197 .cmd_rcgr = 0x8098, 198 .mnd_width = 0, 199 .hid_width = 5, 200 .parent_map = disp_cc_parent_map_1, 201 .clkr.hw.init = &(const struct clk_init_data) { 202 .name = "disp_cc_mdss_byte0_clk_src", 203 .parent_data = disp_cc_parent_data_1, 204 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 205 .flags = CLK_SET_RATE_PARENT, 206 .ops = &clk_byte2_ops, 207 }, 208 }; 209 210 static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_aux_clk_src[] = { 211 F(19200000, P_BI_TCXO, 1, 0, 0), 212 { } 213 }; 214 215 static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { 216 .cmd_rcgr = 0x8118, 217 .mnd_width = 0, 218 .hid_width = 5, 219 .parent_map = disp_cc_parent_map_0, 220 .freq_tbl = ftbl_disp_cc_mdss_dptx0_aux_clk_src, 221 .clkr.hw.init = &(const struct clk_init_data) { 222 .name = "disp_cc_mdss_dptx0_aux_clk_src", 223 .parent_data = disp_cc_parent_data_0, 224 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 225 .flags = CLK_SET_RATE_PARENT, 226 .ops = &clk_rcg2_ops, 227 }, 228 }; 229 230 static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { 231 .cmd_rcgr = 0x80cc, 232 .mnd_width = 0, 233 .hid_width = 5, 234 .parent_map = disp_cc_parent_map_4, 235 .clkr.hw.init = &(const struct clk_init_data) { 236 .name = "disp_cc_mdss_dptx0_link_clk_src", 237 .parent_data = disp_cc_parent_data_4, 238 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 239 .flags = CLK_SET_RATE_PARENT, 240 .ops = &clk_byte2_ops, 241 }, 242 }; 243 244 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = { 245 .cmd_rcgr = 0x80e8, 246 .mnd_width = 16, 247 .hid_width = 5, 248 .parent_map = disp_cc_parent_map_2, 249 .clkr.hw.init = &(const struct clk_init_data) { 250 .name = "disp_cc_mdss_dptx0_pixel0_clk_src", 251 .parent_data = disp_cc_parent_data_2, 252 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 253 .flags = CLK_SET_RATE_PARENT, 254 .ops = &clk_dp_ops, 255 }, 256 }; 257 258 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = { 259 .cmd_rcgr = 0x8100, 260 .mnd_width = 16, 261 .hid_width = 5, 262 .parent_map = disp_cc_parent_map_2, 263 .clkr.hw.init = &(const struct clk_init_data) { 264 .name = "disp_cc_mdss_dptx0_pixel1_clk_src", 265 .parent_data = disp_cc_parent_data_2, 266 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 267 .flags = CLK_SET_RATE_PARENT, 268 .ops = &clk_dp_ops, 269 }, 270 }; 271 272 static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = { 273 F(9600000, P_BI_TCXO, 2, 0, 0), 274 F(12800000, P_BI_TCXO, 1.5, 0, 0), 275 F(19200000, P_BI_TCXO, 1, 0, 0), 276 { } 277 }; 278 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { 279 .cmd_rcgr = 0x80b4, 280 .mnd_width = 0, 281 .hid_width = 5, 282 .parent_map = disp_cc_parent_map_5, 283 .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, 284 .clkr.hw.init = &(const struct clk_init_data) { 285 .name = "disp_cc_mdss_esc0_clk_src", 286 .parent_data = disp_cc_parent_data_5, 287 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 288 .flags = CLK_SET_RATE_PARENT, 289 .ops = &clk_rcg2_ops, 290 }, 291 }; 292 293 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { 294 F(19200000, P_BI_TCXO, 1, 0, 0), 295 F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 296 F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 297 F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 298 F(342000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 299 F(402000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 300 F(535000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 301 F(600000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 302 F(630000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 303 { } 304 }; 305 306 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { 307 .cmd_rcgr = 0x8068, 308 .mnd_width = 0, 309 .hid_width = 5, 310 .parent_map = disp_cc_parent_map_6, 311 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 312 .clkr.hw.init = &(const struct clk_init_data) { 313 .name = "disp_cc_mdss_mdp_clk_src", 314 .parent_data = disp_cc_parent_data_6, 315 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 316 .flags = CLK_SET_RATE_PARENT, 317 .ops = &clk_rcg2_shared_ops, 318 }, 319 }; 320 321 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { 322 .cmd_rcgr = 0x8050, 323 .mnd_width = 8, 324 .hid_width = 5, 325 .parent_map = disp_cc_parent_map_1, 326 .clkr.hw.init = &(const struct clk_init_data) { 327 .name = "disp_cc_mdss_pclk0_clk_src", 328 .parent_data = disp_cc_parent_data_1, 329 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 330 .flags = CLK_SET_RATE_PARENT, 331 .ops = &clk_pixel_ops, 332 }, 333 }; 334 335 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { 336 .cmd_rcgr = 0x8080, 337 .mnd_width = 0, 338 .hid_width = 5, 339 .parent_map = disp_cc_parent_map_0, 340 .freq_tbl = ftbl_disp_cc_mdss_dptx0_aux_clk_src, 341 .clkr.hw.init = &(const struct clk_init_data) { 342 .name = "disp_cc_mdss_vsync_clk_src", 343 .parent_data = disp_cc_parent_data_0, 344 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 345 .flags = CLK_SET_RATE_PARENT, 346 .ops = &clk_rcg2_ops, 347 }, 348 }; 349 350 static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = { 351 F(32000, P_SLEEP_CLK, 1, 0, 0), 352 { } 353 }; 354 355 static struct clk_rcg2 disp_cc_sleep_clk_src = { 356 .cmd_rcgr = 0xe054, 357 .mnd_width = 0, 358 .hid_width = 5, 359 .parent_map = disp_cc_parent_map_7, 360 .freq_tbl = ftbl_disp_cc_sleep_clk_src, 361 .clkr.hw.init = &(const struct clk_init_data) { 362 .name = "disp_cc_sleep_clk_src", 363 .parent_data = disp_cc_parent_data_7_ao, 364 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7_ao), 365 .flags = CLK_SET_RATE_PARENT, 366 .ops = &clk_rcg2_ops, 367 }, 368 }; 369 370 static struct clk_rcg2 disp_cc_xo_clk_src = { 371 .cmd_rcgr = 0xe034, 372 .mnd_width = 0, 373 .hid_width = 5, 374 .parent_map = disp_cc_parent_map_0, 375 .freq_tbl = ftbl_disp_cc_mdss_dptx0_aux_clk_src, 376 .clkr.hw.init = &(const struct clk_init_data) { 377 .name = "disp_cc_xo_clk_src", 378 .parent_data = disp_cc_parent_data_0, 379 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 380 .flags = CLK_SET_RATE_PARENT, 381 .ops = &clk_rcg2_ops, 382 }, 383 }; 384 385 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { 386 .reg = 0x80b0, 387 .shift = 0, 388 .width = 4, 389 .clkr.hw.init = &(const struct clk_init_data) { 390 .name = "disp_cc_mdss_byte0_div_clk_src", 391 .parent_hws = (const struct clk_hw*[]) { 392 &disp_cc_mdss_byte0_clk_src.clkr.hw, 393 }, 394 .num_parents = 1, 395 .ops = &clk_regmap_div_ops, 396 }, 397 }; 398 399 static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = { 400 .reg = 0x80e4, 401 .shift = 0, 402 .width = 4, 403 .clkr.hw.init = &(const struct clk_init_data) { 404 .name = "disp_cc_mdss_dptx0_link_div_clk_src", 405 .parent_hws = (const struct clk_hw*[]) { 406 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 407 }, 408 .num_parents = 1, 409 .flags = CLK_SET_RATE_PARENT, 410 .ops = &clk_regmap_div_ro_ops, 411 }, 412 }; 413 414 static struct clk_branch disp_cc_mdss_accu_clk = { 415 .halt_reg = 0xe050, 416 .halt_check = BRANCH_HALT_VOTED, 417 .clkr = { 418 .enable_reg = 0xe050, 419 .enable_mask = BIT(0), 420 .hw.init = &(const struct clk_init_data) { 421 .name = "disp_cc_mdss_accu_clk", 422 .parent_hws = (const struct clk_hw*[]) { 423 &disp_cc_xo_clk_src.clkr.hw, 424 }, 425 .num_parents = 1, 426 .flags = CLK_SET_RATE_PARENT, 427 .ops = &clk_branch2_ops, 428 }, 429 }, 430 }; 431 432 static struct clk_branch disp_cc_mdss_ahb1_clk = { 433 .halt_reg = 0xa020, 434 .halt_check = BRANCH_HALT, 435 .clkr = { 436 .enable_reg = 0xa020, 437 .enable_mask = BIT(0), 438 .hw.init = &(const struct clk_init_data) { 439 .name = "disp_cc_mdss_ahb1_clk", 440 .parent_hws = (const struct clk_hw*[]) { 441 &disp_cc_mdss_ahb_clk_src.clkr.hw, 442 }, 443 .num_parents = 1, 444 .flags = CLK_SET_RATE_PARENT, 445 .ops = &clk_branch2_ops, 446 }, 447 }, 448 }; 449 450 static struct clk_branch disp_cc_mdss_ahb_clk = { 451 .halt_reg = 0x804c, 452 .halt_check = BRANCH_HALT, 453 .clkr = { 454 .enable_reg = 0x804c, 455 .enable_mask = BIT(0), 456 .hw.init = &(const struct clk_init_data) { 457 .name = "disp_cc_mdss_ahb_clk", 458 .parent_hws = (const struct clk_hw*[]) { 459 &disp_cc_mdss_ahb_clk_src.clkr.hw, 460 }, 461 .num_parents = 1, 462 .flags = CLK_SET_RATE_PARENT, 463 .ops = &clk_branch2_ops, 464 }, 465 }, 466 }; 467 468 static struct clk_branch disp_cc_mdss_byte0_clk = { 469 .halt_reg = 0x8024, 470 .halt_check = BRANCH_HALT, 471 .clkr = { 472 .enable_reg = 0x8024, 473 .enable_mask = BIT(0), 474 .hw.init = &(const struct clk_init_data) { 475 .name = "disp_cc_mdss_byte0_clk", 476 .parent_hws = (const struct clk_hw*[]) { 477 &disp_cc_mdss_byte0_clk_src.clkr.hw, 478 }, 479 .num_parents = 1, 480 .flags = CLK_SET_RATE_PARENT, 481 .ops = &clk_branch2_ops, 482 }, 483 }, 484 }; 485 486 static struct clk_branch disp_cc_mdss_byte0_intf_clk = { 487 .halt_reg = 0x8028, 488 .halt_check = BRANCH_HALT, 489 .clkr = { 490 .enable_reg = 0x8028, 491 .enable_mask = BIT(0), 492 .hw.init = &(const struct clk_init_data) { 493 .name = "disp_cc_mdss_byte0_intf_clk", 494 .parent_hws = (const struct clk_hw*[]) { 495 &disp_cc_mdss_byte0_div_clk_src.clkr.hw, 496 }, 497 .num_parents = 1, 498 .flags = CLK_SET_RATE_PARENT, 499 .ops = &clk_branch2_ops, 500 }, 501 }, 502 }; 503 504 static struct clk_branch disp_cc_mdss_dptx0_aux_clk = { 505 .halt_reg = 0x8048, 506 .halt_check = BRANCH_HALT, 507 .clkr = { 508 .enable_reg = 0x8048, 509 .enable_mask = BIT(0), 510 .hw.init = &(const struct clk_init_data) { 511 .name = "disp_cc_mdss_dptx0_aux_clk", 512 .parent_hws = (const struct clk_hw*[]) { 513 &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, 514 }, 515 .num_parents = 1, 516 .flags = CLK_SET_RATE_PARENT, 517 .ops = &clk_branch2_ops, 518 }, 519 }, 520 }; 521 522 static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = { 523 .halt_reg = 0x803c, 524 .halt_check = BRANCH_HALT, 525 .clkr = { 526 .enable_reg = 0x803c, 527 .enable_mask = BIT(0), 528 .hw.init = &(const struct clk_init_data) { 529 .name = "disp_cc_mdss_dptx0_crypto_clk", 530 .parent_hws = (const struct clk_hw*[]) { 531 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 532 }, 533 .num_parents = 1, 534 .flags = CLK_SET_RATE_PARENT, 535 .ops = &clk_branch2_ops, 536 }, 537 }, 538 }; 539 540 static struct clk_branch disp_cc_mdss_dptx0_link_clk = { 541 .halt_reg = 0x8030, 542 .halt_check = BRANCH_HALT, 543 .clkr = { 544 .enable_reg = 0x8030, 545 .enable_mask = BIT(0), 546 .hw.init = &(const struct clk_init_data) { 547 .name = "disp_cc_mdss_dptx0_link_clk", 548 .parent_hws = (const struct clk_hw*[]) { 549 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 550 }, 551 .num_parents = 1, 552 .flags = CLK_SET_RATE_PARENT, 553 .ops = &clk_branch2_ops, 554 }, 555 }, 556 }; 557 558 static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = { 559 .halt_reg = 0x8038, 560 .halt_check = BRANCH_HALT, 561 .clkr = { 562 .enable_reg = 0x8038, 563 .enable_mask = BIT(0), 564 .hw.init = &(const struct clk_init_data) { 565 .name = "disp_cc_mdss_dptx0_link_intf_clk", 566 .parent_hws = (const struct clk_hw*[]) { 567 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 568 }, 569 .num_parents = 1, 570 .flags = CLK_SET_RATE_PARENT, 571 .ops = &clk_branch2_ops, 572 }, 573 }, 574 }; 575 576 static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = { 577 .halt_reg = 0x8040, 578 .halt_check = BRANCH_HALT, 579 .clkr = { 580 .enable_reg = 0x8040, 581 .enable_mask = BIT(0), 582 .hw.init = &(const struct clk_init_data) { 583 .name = "disp_cc_mdss_dptx0_pixel0_clk", 584 .parent_hws = (const struct clk_hw*[]) { 585 &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, 586 }, 587 .num_parents = 1, 588 .flags = CLK_SET_RATE_PARENT, 589 .ops = &clk_branch2_ops, 590 }, 591 }, 592 }; 593 594 static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = { 595 .halt_reg = 0x8044, 596 .halt_check = BRANCH_HALT, 597 .clkr = { 598 .enable_reg = 0x8044, 599 .enable_mask = BIT(0), 600 .hw.init = &(const struct clk_init_data) { 601 .name = "disp_cc_mdss_dptx0_pixel1_clk", 602 .parent_hws = (const struct clk_hw*[]) { 603 &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, 604 }, 605 .num_parents = 1, 606 .flags = CLK_SET_RATE_PARENT, 607 .ops = &clk_branch2_ops, 608 }, 609 }, 610 }; 611 612 static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = { 613 .halt_reg = 0x8034, 614 .halt_check = BRANCH_HALT, 615 .clkr = { 616 .enable_reg = 0x8034, 617 .enable_mask = BIT(0), 618 .hw.init = &(const struct clk_init_data) { 619 .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk", 620 .parent_hws = (const struct clk_hw*[]) { 621 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 622 }, 623 .num_parents = 1, 624 .flags = CLK_SET_RATE_PARENT, 625 .ops = &clk_branch2_ops, 626 }, 627 }, 628 }; 629 630 static struct clk_branch disp_cc_mdss_esc0_clk = { 631 .halt_reg = 0x802c, 632 .halt_check = BRANCH_HALT, 633 .clkr = { 634 .enable_reg = 0x802c, 635 .enable_mask = BIT(0), 636 .hw.init = &(const struct clk_init_data) { 637 .name = "disp_cc_mdss_esc0_clk", 638 .parent_hws = (const struct clk_hw*[]) { 639 &disp_cc_mdss_esc0_clk_src.clkr.hw, 640 }, 641 .num_parents = 1, 642 .flags = CLK_SET_RATE_PARENT, 643 .ops = &clk_branch2_ops, 644 }, 645 }, 646 }; 647 648 static struct clk_branch disp_cc_mdss_mdp1_clk = { 649 .halt_reg = 0xa004, 650 .halt_check = BRANCH_HALT, 651 .clkr = { 652 .enable_reg = 0xa004, 653 .enable_mask = BIT(0), 654 .hw.init = &(const struct clk_init_data) { 655 .name = "disp_cc_mdss_mdp1_clk", 656 .parent_hws = (const struct clk_hw*[]) { 657 &disp_cc_mdss_mdp_clk_src.clkr.hw, 658 }, 659 .num_parents = 1, 660 .flags = CLK_SET_RATE_PARENT, 661 .ops = &clk_branch2_ops, 662 }, 663 }, 664 }; 665 666 static struct clk_branch disp_cc_mdss_mdp_clk = { 667 .halt_reg = 0x8008, 668 .halt_check = BRANCH_HALT, 669 .clkr = { 670 .enable_reg = 0x8008, 671 .enable_mask = BIT(0), 672 .hw.init = &(const struct clk_init_data) { 673 .name = "disp_cc_mdss_mdp_clk", 674 .parent_hws = (const struct clk_hw*[]) { 675 &disp_cc_mdss_mdp_clk_src.clkr.hw, 676 }, 677 .num_parents = 1, 678 .flags = CLK_SET_RATE_PARENT, 679 .ops = &clk_branch2_ops, 680 }, 681 }, 682 }; 683 684 static struct clk_branch disp_cc_mdss_mdp_lut1_clk = { 685 .halt_reg = 0xa010, 686 .halt_check = BRANCH_HALT, 687 .clkr = { 688 .enable_reg = 0xa010, 689 .enable_mask = BIT(0), 690 .hw.init = &(const struct clk_init_data) { 691 .name = "disp_cc_mdss_mdp_lut1_clk", 692 .parent_hws = (const struct clk_hw*[]) { 693 &disp_cc_mdss_mdp_clk_src.clkr.hw, 694 }, 695 .num_parents = 1, 696 .flags = CLK_SET_RATE_PARENT, 697 .ops = &clk_branch2_ops, 698 }, 699 }, 700 }; 701 702 static struct clk_branch disp_cc_mdss_mdp_lut_clk = { 703 .halt_reg = 0x8014, 704 .halt_check = BRANCH_HALT_VOTED, 705 .clkr = { 706 .enable_reg = 0x8014, 707 .enable_mask = BIT(0), 708 .hw.init = &(const struct clk_init_data) { 709 .name = "disp_cc_mdss_mdp_lut_clk", 710 .parent_hws = (const struct clk_hw*[]) { 711 &disp_cc_mdss_mdp_clk_src.clkr.hw, 712 }, 713 .num_parents = 1, 714 .flags = CLK_SET_RATE_PARENT, 715 .ops = &clk_branch2_ops, 716 }, 717 }, 718 }; 719 720 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { 721 .halt_reg = 0xc004, 722 .halt_check = BRANCH_HALT_VOTED, 723 .clkr = { 724 .enable_reg = 0xc004, 725 .enable_mask = BIT(0), 726 .hw.init = &(const struct clk_init_data) { 727 .name = "disp_cc_mdss_non_gdsc_ahb_clk", 728 .parent_hws = (const struct clk_hw*[]) { 729 &disp_cc_mdss_ahb_clk_src.clkr.hw, 730 }, 731 .num_parents = 1, 732 .flags = CLK_SET_RATE_PARENT, 733 .ops = &clk_branch2_ops, 734 }, 735 }, 736 }; 737 738 static struct clk_branch disp_cc_mdss_pclk0_clk = { 739 .halt_reg = 0x8004, 740 .halt_check = BRANCH_HALT, 741 .clkr = { 742 .enable_reg = 0x8004, 743 .enable_mask = BIT(0), 744 .hw.init = &(const struct clk_init_data) { 745 .name = "disp_cc_mdss_pclk0_clk", 746 .parent_hws = (const struct clk_hw*[]) { 747 &disp_cc_mdss_pclk0_clk_src.clkr.hw, 748 }, 749 .num_parents = 1, 750 .flags = CLK_SET_RATE_PARENT, 751 .ops = &clk_branch2_ops, 752 }, 753 }, 754 }; 755 756 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { 757 .halt_reg = 0xc00c, 758 .halt_check = BRANCH_HALT, 759 .clkr = { 760 .enable_reg = 0xc00c, 761 .enable_mask = BIT(0), 762 .hw.init = &(const struct clk_init_data) { 763 .name = "disp_cc_mdss_rscc_ahb_clk", 764 .parent_hws = (const struct clk_hw*[]) { 765 &disp_cc_mdss_ahb_clk_src.clkr.hw, 766 }, 767 .num_parents = 1, 768 .flags = CLK_SET_RATE_PARENT, 769 .ops = &clk_branch2_ops, 770 }, 771 }, 772 }; 773 774 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { 775 .halt_reg = 0xc008, 776 .halt_check = BRANCH_HALT, 777 .clkr = { 778 .enable_reg = 0xc008, 779 .enable_mask = BIT(0), 780 .hw.init = &(const struct clk_init_data) { 781 .name = "disp_cc_mdss_rscc_vsync_clk", 782 .parent_hws = (const struct clk_hw*[]) { 783 &disp_cc_mdss_vsync_clk_src.clkr.hw, 784 }, 785 .num_parents = 1, 786 .flags = CLK_SET_RATE_PARENT, 787 .ops = &clk_branch2_ops, 788 }, 789 }, 790 }; 791 792 static struct clk_branch disp_cc_mdss_vsync1_clk = { 793 .halt_reg = 0xa01c, 794 .halt_check = BRANCH_HALT, 795 .clkr = { 796 .enable_reg = 0xa01c, 797 .enable_mask = BIT(0), 798 .hw.init = &(const struct clk_init_data) { 799 .name = "disp_cc_mdss_vsync1_clk", 800 .parent_hws = (const struct clk_hw*[]) { 801 &disp_cc_mdss_vsync_clk_src.clkr.hw, 802 }, 803 .num_parents = 1, 804 .flags = CLK_SET_RATE_PARENT, 805 .ops = &clk_branch2_ops, 806 }, 807 }, 808 }; 809 810 static struct clk_branch disp_cc_mdss_vsync_clk = { 811 .halt_reg = 0x8020, 812 .halt_check = BRANCH_HALT, 813 .clkr = { 814 .enable_reg = 0x8020, 815 .enable_mask = BIT(0), 816 .hw.init = &(const struct clk_init_data) { 817 .name = "disp_cc_mdss_vsync_clk", 818 .parent_hws = (const struct clk_hw*[]) { 819 &disp_cc_mdss_vsync_clk_src.clkr.hw, 820 }, 821 .num_parents = 1, 822 .flags = CLK_SET_RATE_PARENT, 823 .ops = &clk_branch2_ops, 824 }, 825 }, 826 }; 827 828 static struct gdsc disp_cc_mdss_core_gdsc = { 829 .gdscr = 0x9000, 830 .en_rest_wait_val = 0x2, 831 .en_few_wait_val = 0x2, 832 .clk_dis_wait_val = 0xf, 833 .pd = { 834 .name = "disp_cc_mdss_core_gdsc", 835 }, 836 .pwrsts = PWRSTS_OFF_ON, 837 .flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE, 838 }; 839 840 static struct gdsc disp_cc_mdss_core_int2_gdsc = { 841 .gdscr = 0xb000, 842 .en_rest_wait_val = 0x2, 843 .en_few_wait_val = 0x2, 844 .clk_dis_wait_val = 0xf, 845 .pd = { 846 .name = "disp_cc_mdss_core_int2_gdsc", 847 }, 848 .pwrsts = PWRSTS_OFF_ON, 849 .flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE, 850 }; 851 852 static struct clk_regmap *disp_cc_milos_clocks[] = { 853 [DISP_CC_MDSS_ACCU_CLK] = &disp_cc_mdss_accu_clk.clkr, 854 [DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr, 855 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, 856 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, 857 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, 858 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, 859 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, 860 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, 861 [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr, 862 [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr, 863 [DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr, 864 [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr, 865 [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr, 866 [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr, 867 [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr, 868 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr, 869 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr, 870 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr, 871 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr, 872 [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = 873 &disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, 874 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, 875 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, 876 [DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr, 877 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, 878 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, 879 [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr, 880 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, 881 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, 882 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, 883 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, 884 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, 885 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, 886 [DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr, 887 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, 888 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, 889 [DISP_CC_PLL0] = &disp_cc_pll0.clkr, 890 [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr, 891 [DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr, 892 }; 893 894 static const struct qcom_reset_map disp_cc_milos_resets[] = { 895 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 }, 896 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 }, 897 [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 }, 898 }; 899 900 static struct gdsc *disp_cc_milos_gdscs[] = { 901 [DISP_CC_MDSS_CORE_GDSC] = &disp_cc_mdss_core_gdsc, 902 [DISP_CC_MDSS_CORE_INT2_GDSC] = &disp_cc_mdss_core_int2_gdsc, 903 }; 904 905 static struct clk_alpha_pll *disp_cc_milos_plls[] = { 906 &disp_cc_pll0, 907 }; 908 909 static const u32 disp_cc_milos_critical_cbcrs[] = { 910 0xe06c, /* DISP_CC_SLEEP_CLK */ 911 0xe04c, /* DISP_CC_XO_CLK */ 912 }; 913 914 static const struct regmap_config disp_cc_milos_regmap_config = { 915 .reg_bits = 32, 916 .reg_stride = 4, 917 .val_bits = 32, 918 .max_register = 0x11008, 919 .fast_io = true, 920 }; 921 922 static void disp_cc_milos_clk_regs_configure(struct device *dev, struct regmap *regmap) 923 { 924 /* Enable clock gating for MDP clocks */ 925 regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); 926 } 927 928 929 static const struct qcom_cc_driver_data disp_cc_milos_driver_data = { 930 .alpha_plls = disp_cc_milos_plls, 931 .num_alpha_plls = ARRAY_SIZE(disp_cc_milos_plls), 932 .clk_cbcrs = disp_cc_milos_critical_cbcrs, 933 .num_clk_cbcrs = ARRAY_SIZE(disp_cc_milos_critical_cbcrs), 934 .clk_regs_configure = disp_cc_milos_clk_regs_configure, 935 }; 936 937 static const struct qcom_cc_desc disp_cc_milos_desc = { 938 .config = &disp_cc_milos_regmap_config, 939 .clks = disp_cc_milos_clocks, 940 .num_clks = ARRAY_SIZE(disp_cc_milos_clocks), 941 .resets = disp_cc_milos_resets, 942 .num_resets = ARRAY_SIZE(disp_cc_milos_resets), 943 .gdscs = disp_cc_milos_gdscs, 944 .num_gdscs = ARRAY_SIZE(disp_cc_milos_gdscs), 945 .use_rpm = true, 946 .driver_data = &disp_cc_milos_driver_data, 947 }; 948 949 static const struct of_device_id disp_cc_milos_match_table[] = { 950 { .compatible = "qcom,milos-dispcc" }, 951 { } 952 }; 953 MODULE_DEVICE_TABLE(of, disp_cc_milos_match_table); 954 955 static int disp_cc_milos_probe(struct platform_device *pdev) 956 { 957 return qcom_cc_probe(pdev, &disp_cc_milos_desc); 958 } 959 960 static struct platform_driver disp_cc_milos_driver = { 961 .probe = disp_cc_milos_probe, 962 .driver = { 963 .name = "disp_cc-milos", 964 .of_match_table = disp_cc_milos_match_table, 965 }, 966 }; 967 968 module_platform_driver(disp_cc_milos_driver); 969 970 MODULE_DESCRIPTION("QTI DISP_CC Milos Driver"); 971 MODULE_LICENSE("GPL"); 972