1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2025, Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,glymur-dispcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-pll.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "clk-regmap-divider.h" 20 #include "clk-regmap-mux.h" 21 #include "common.h" 22 #include "gdsc.h" 23 #include "reset.h" 24 25 enum { 26 DT_BI_TCXO, 27 DT_SLEEP_CLK, 28 DT_DP0_PHY_PLL_LINK_CLK, 29 DT_DP0_PHY_PLL_VCO_DIV_CLK, 30 DT_DP1_PHY_PLL_LINK_CLK, 31 DT_DP1_PHY_PLL_VCO_DIV_CLK, 32 DT_DP2_PHY_PLL_LINK_CLK, 33 DT_DP2_PHY_PLL_VCO_DIV_CLK, 34 DT_DP3_PHY_PLL_LINK_CLK, 35 DT_DP3_PHY_PLL_VCO_DIV_CLK, 36 DT_DSI0_PHY_PLL_OUT_BYTECLK, 37 DT_DSI0_PHY_PLL_OUT_DSICLK, 38 DT_DSI1_PHY_PLL_OUT_BYTECLK, 39 DT_DSI1_PHY_PLL_OUT_DSICLK, 40 DT_STANDALONE_PHY_PLL0_LINK_CLK, 41 DT_STANDALONE_PHY_PLL0_VCO_DIV_CLK, 42 DT_STANDALONE_PHY_PLL1_LINK_CLK, 43 DT_STANDALONE_PHY_PLL1_VCO_DIV_CLK, 44 }; 45 46 enum { 47 P_BI_TCXO, 48 P_SLEEP_CLK, 49 P_DISP_CC_PLL0_OUT_MAIN, 50 P_DISP_CC_PLL1_OUT_EVEN, 51 P_DISP_CC_PLL1_OUT_MAIN, 52 P_DP0_PHY_PLL_LINK_CLK, 53 P_DP0_PHY_PLL_VCO_DIV_CLK, 54 P_DP1_PHY_PLL_LINK_CLK, 55 P_DP1_PHY_PLL_VCO_DIV_CLK, 56 P_DP2_PHY_PLL_LINK_CLK, 57 P_DP2_PHY_PLL_VCO_DIV_CLK, 58 P_DP3_PHY_PLL_LINK_CLK, 59 P_DP3_PHY_PLL_VCO_DIV_CLK, 60 P_DSI0_PHY_PLL_OUT_BYTECLK, 61 P_DSI0_PHY_PLL_OUT_DSICLK, 62 P_DSI1_PHY_PLL_OUT_BYTECLK, 63 P_DSI1_PHY_PLL_OUT_DSICLK, 64 P_STANDALONE_PHY_PLL0_LINK_CLK, 65 P_STANDALONE_PHY_PLL0_VCO_DIV_CLK, 66 P_STANDALONE_PHY_PLL1_LINK_CLK, 67 P_STANDALONE_PHY_PLL1_VCO_DIV_CLK, 68 }; 69 70 static const struct pll_vco taycan_eko_t_vco[] = { 71 { 249600000, 2500000000, 0 }, 72 }; 73 74 /* 257.142858 MHz Configuration */ 75 static const struct alpha_pll_config disp_cc_pll0_config = { 76 .l = 0xd, 77 .alpha = 0x6492, 78 .config_ctl_val = 0x25c400e7, 79 .config_ctl_hi_val = 0x0a8060e0, 80 .config_ctl_hi1_val = 0xf51dea20, 81 .user_ctl_val = 0x00000008, 82 .user_ctl_hi_val = 0x00000002, 83 }; 84 85 static struct clk_alpha_pll disp_cc_pll0 = { 86 .offset = 0x0, 87 .config = &disp_cc_pll0_config, 88 .vco_table = taycan_eko_t_vco, 89 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 90 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 91 .clkr = { 92 .hw.init = &(const struct clk_init_data) { 93 .name = "disp_cc_pll0", 94 .parent_data = &(const struct clk_parent_data) { 95 .index = DT_BI_TCXO, 96 }, 97 .num_parents = 1, 98 .ops = &clk_alpha_pll_taycan_eko_t_ops, 99 }, 100 }, 101 }; 102 103 /* 600.0 MHz Configuration */ 104 static const struct alpha_pll_config disp_cc_pll1_config = { 105 .l = 0x1f, 106 .alpha = 0x4000, 107 .config_ctl_val = 0x25c400e7, 108 .config_ctl_hi_val = 0x0a8060e0, 109 .config_ctl_hi1_val = 0xf51dea20, 110 .user_ctl_val = 0x00000008, 111 .user_ctl_hi_val = 0x00000002, 112 }; 113 114 static struct clk_alpha_pll disp_cc_pll1 = { 115 .offset = 0x1000, 116 .config = &disp_cc_pll1_config, 117 .vco_table = taycan_eko_t_vco, 118 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 119 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 120 .clkr = { 121 .hw.init = &(const struct clk_init_data) { 122 .name = "disp_cc_pll1", 123 .parent_data = &(const struct clk_parent_data) { 124 .index = DT_BI_TCXO, 125 }, 126 .num_parents = 1, 127 .ops = &clk_alpha_pll_taycan_eko_t_ops, 128 }, 129 }, 130 }; 131 132 static const struct parent_map disp_cc_parent_map_0[] = { 133 { P_BI_TCXO, 0 }, 134 { P_STANDALONE_PHY_PLL0_VCO_DIV_CLK, 1 }, 135 { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 }, 136 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, 137 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, 138 { P_STANDALONE_PHY_PLL1_VCO_DIV_CLK, 5 }, 139 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, 140 }; 141 142 static const struct clk_parent_data disp_cc_parent_data_0[] = { 143 { .index = DT_BI_TCXO }, 144 { .index = DT_STANDALONE_PHY_PLL0_VCO_DIV_CLK }, 145 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK }, 146 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 147 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 148 { .index = DT_STANDALONE_PHY_PLL1_VCO_DIV_CLK }, 149 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 150 }; 151 152 static const struct parent_map disp_cc_parent_map_1[] = { 153 { P_BI_TCXO, 0 }, 154 }; 155 156 static const struct clk_parent_data disp_cc_parent_data_1[] = { 157 { .index = DT_BI_TCXO }, 158 }; 159 160 static const struct parent_map disp_cc_parent_map_2[] = { 161 { P_BI_TCXO, 0 }, 162 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 163 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 164 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, 165 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 166 }; 167 168 static const struct clk_parent_data disp_cc_parent_data_2[] = { 169 { .index = DT_BI_TCXO }, 170 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, 171 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 172 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, 173 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 174 }; 175 176 static const struct parent_map disp_cc_parent_map_3[] = { 177 { P_BI_TCXO, 0 }, 178 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 179 { P_DP1_PHY_PLL_LINK_CLK, 2 }, 180 { P_DP2_PHY_PLL_LINK_CLK, 3 }, 181 { P_DP3_PHY_PLL_LINK_CLK, 4 }, 182 { P_STANDALONE_PHY_PLL1_LINK_CLK, 5 }, 183 { P_STANDALONE_PHY_PLL0_LINK_CLK, 6 }, 184 }; 185 186 static const struct clk_parent_data disp_cc_parent_data_3[] = { 187 { .index = DT_BI_TCXO }, 188 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 189 { .index = DT_DP1_PHY_PLL_LINK_CLK }, 190 { .index = DT_DP2_PHY_PLL_LINK_CLK }, 191 { .index = DT_DP3_PHY_PLL_LINK_CLK }, 192 { .index = DT_STANDALONE_PHY_PLL1_LINK_CLK }, 193 { .index = DT_STANDALONE_PHY_PLL0_LINK_CLK }, 194 }; 195 196 static const struct parent_map disp_cc_parent_map_4[] = { 197 { P_BI_TCXO, 0 }, 198 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 199 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, 200 }; 201 202 static const struct clk_parent_data disp_cc_parent_data_4[] = { 203 { .index = DT_BI_TCXO }, 204 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, 205 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, 206 }; 207 208 static const struct parent_map disp_cc_parent_map_5[] = { 209 { P_BI_TCXO, 0 }, 210 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 211 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 212 }; 213 214 static const struct clk_parent_data disp_cc_parent_data_5[] = { 215 { .index = DT_BI_TCXO }, 216 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 217 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 218 }; 219 220 static const struct parent_map disp_cc_parent_map_6[] = { 221 { P_BI_TCXO, 0 }, 222 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 223 { P_DISP_CC_PLL1_OUT_EVEN, 6 }, 224 }; 225 226 static const struct clk_parent_data disp_cc_parent_data_6[] = { 227 { .index = DT_BI_TCXO }, 228 { .hw = &disp_cc_pll1.clkr.hw }, 229 { .hw = &disp_cc_pll1.clkr.hw }, 230 }; 231 232 static const struct parent_map disp_cc_parent_map_7[] = { 233 { P_BI_TCXO, 0 }, 234 { P_DISP_CC_PLL0_OUT_MAIN, 1 }, 235 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 236 { P_DISP_CC_PLL1_OUT_EVEN, 6 }, 237 }; 238 239 static const struct clk_parent_data disp_cc_parent_data_7[] = { 240 { .index = DT_BI_TCXO }, 241 { .hw = &disp_cc_pll0.clkr.hw }, 242 { .hw = &disp_cc_pll1.clkr.hw }, 243 { .hw = &disp_cc_pll1.clkr.hw }, 244 }; 245 246 static const struct parent_map disp_cc_parent_map_8[] = { 247 { P_BI_TCXO, 0 }, 248 }; 249 250 static const struct clk_parent_data disp_cc_parent_data_8[] = { 251 { .index = DT_BI_TCXO }, 252 }; 253 254 static const struct parent_map disp_cc_parent_map_9[] = { 255 { P_SLEEP_CLK, 0 }, 256 }; 257 258 static const struct clk_parent_data disp_cc_parent_data_9[] = { 259 { .index = DT_SLEEP_CLK }, 260 }; 261 262 static const struct freq_tbl ftbl_disp_cc_esync0_clk_src[] = { 263 F(19200000, P_BI_TCXO, 1, 0, 0), 264 { } 265 }; 266 267 static struct clk_rcg2 disp_cc_esync0_clk_src = { 268 .cmd_rcgr = 0x80c0, 269 .mnd_width = 16, 270 .hid_width = 5, 271 .parent_map = disp_cc_parent_map_4, 272 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 273 .clkr.hw.init = &(const struct clk_init_data) { 274 .name = "disp_cc_esync0_clk_src", 275 .parent_data = disp_cc_parent_data_4, 276 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 277 .flags = CLK_SET_RATE_PARENT, 278 .ops = &clk_rcg2_shared_ops, 279 }, 280 }; 281 282 static struct clk_rcg2 disp_cc_esync1_clk_src = { 283 .cmd_rcgr = 0x80d8, 284 .mnd_width = 16, 285 .hid_width = 5, 286 .parent_map = disp_cc_parent_map_4, 287 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 288 .clkr.hw.init = &(const struct clk_init_data) { 289 .name = "disp_cc_esync1_clk_src", 290 .parent_data = disp_cc_parent_data_4, 291 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 292 .flags = CLK_SET_RATE_PARENT, 293 .ops = &clk_rcg2_shared_ops, 294 }, 295 }; 296 297 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { 298 F(19200000, P_BI_TCXO, 1, 0, 0), 299 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), 300 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), 301 { } 302 }; 303 304 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { 305 .cmd_rcgr = 0x8360, 306 .mnd_width = 0, 307 .hid_width = 5, 308 .parent_map = disp_cc_parent_map_6, 309 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 310 .hw_clk_ctrl = true, 311 .clkr.hw.init = &(const struct clk_init_data) { 312 .name = "disp_cc_mdss_ahb_clk_src", 313 .parent_data = disp_cc_parent_data_6, 314 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 315 .flags = CLK_SET_RATE_PARENT, 316 .ops = &clk_rcg2_shared_ops, 317 }, 318 }; 319 320 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { 321 .cmd_rcgr = 0x8180, 322 .mnd_width = 0, 323 .hid_width = 5, 324 .parent_map = disp_cc_parent_map_2, 325 .clkr.hw.init = &(const struct clk_init_data) { 326 .name = "disp_cc_mdss_byte0_clk_src", 327 .parent_data = disp_cc_parent_data_2, 328 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 329 .flags = CLK_SET_RATE_PARENT, 330 .ops = &clk_byte2_ops, 331 }, 332 }; 333 334 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { 335 .cmd_rcgr = 0x819c, 336 .mnd_width = 0, 337 .hid_width = 5, 338 .parent_map = disp_cc_parent_map_2, 339 .clkr.hw.init = &(const struct clk_init_data) { 340 .name = "disp_cc_mdss_byte1_clk_src", 341 .parent_data = disp_cc_parent_data_2, 342 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 343 .flags = CLK_SET_RATE_PARENT, 344 .ops = &clk_byte2_ops, 345 }, 346 }; 347 348 static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { 349 .cmd_rcgr = 0x8234, 350 .mnd_width = 0, 351 .hid_width = 5, 352 .parent_map = disp_cc_parent_map_1, 353 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 354 .clkr.hw.init = &(const struct clk_init_data) { 355 .name = "disp_cc_mdss_dptx0_aux_clk_src", 356 .parent_data = disp_cc_parent_data_1, 357 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 358 .flags = CLK_SET_RATE_PARENT, 359 .ops = &clk_rcg2_shared_ops, 360 }, 361 }; 362 363 static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { 364 .cmd_rcgr = 0x81e8, 365 .mnd_width = 0, 366 .hid_width = 5, 367 .parent_map = disp_cc_parent_map_3, 368 .clkr.hw.init = &(const struct clk_init_data) { 369 .name = "disp_cc_mdss_dptx0_link_clk_src", 370 .parent_data = disp_cc_parent_data_3, 371 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 372 .flags = CLK_SET_RATE_PARENT, 373 .ops = &clk_byte2_ops, 374 }, 375 }; 376 377 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = { 378 .cmd_rcgr = 0x8204, 379 .mnd_width = 16, 380 .hid_width = 5, 381 .parent_map = disp_cc_parent_map_0, 382 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 383 .clkr.hw.init = &(const struct clk_init_data) { 384 .name = "disp_cc_mdss_dptx0_pixel0_clk_src", 385 .parent_data = disp_cc_parent_data_0, 386 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 387 .flags = CLK_SET_RATE_PARENT, 388 .ops = &clk_dp_ops, 389 }, 390 }; 391 392 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = { 393 .cmd_rcgr = 0x821c, 394 .mnd_width = 16, 395 .hid_width = 5, 396 .parent_map = disp_cc_parent_map_0, 397 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 398 .clkr.hw.init = &(const struct clk_init_data) { 399 .name = "disp_cc_mdss_dptx0_pixel1_clk_src", 400 .parent_data = disp_cc_parent_data_0, 401 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 402 .flags = CLK_SET_RATE_PARENT, 403 .ops = &clk_dp_ops, 404 }, 405 }; 406 407 static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { 408 .cmd_rcgr = 0x8298, 409 .mnd_width = 0, 410 .hid_width = 5, 411 .parent_map = disp_cc_parent_map_1, 412 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 413 .clkr.hw.init = &(const struct clk_init_data) { 414 .name = "disp_cc_mdss_dptx1_aux_clk_src", 415 .parent_data = disp_cc_parent_data_1, 416 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 417 .flags = CLK_SET_RATE_PARENT, 418 .ops = &clk_rcg2_shared_ops, 419 }, 420 }; 421 422 static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { 423 .cmd_rcgr = 0x827c, 424 .mnd_width = 0, 425 .hid_width = 5, 426 .parent_map = disp_cc_parent_map_3, 427 .clkr.hw.init = &(const struct clk_init_data) { 428 .name = "disp_cc_mdss_dptx1_link_clk_src", 429 .parent_data = disp_cc_parent_data_3, 430 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 431 .flags = CLK_SET_RATE_PARENT, 432 .ops = &clk_byte2_ops, 433 }, 434 }; 435 436 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = { 437 .cmd_rcgr = 0x824c, 438 .mnd_width = 16, 439 .hid_width = 5, 440 .parent_map = disp_cc_parent_map_0, 441 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 442 .clkr.hw.init = &(const struct clk_init_data) { 443 .name = "disp_cc_mdss_dptx1_pixel0_clk_src", 444 .parent_data = disp_cc_parent_data_0, 445 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 446 .flags = CLK_SET_RATE_PARENT, 447 .ops = &clk_dp_ops, 448 }, 449 }; 450 451 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = { 452 .cmd_rcgr = 0x8264, 453 .mnd_width = 16, 454 .hid_width = 5, 455 .parent_map = disp_cc_parent_map_0, 456 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 457 .clkr.hw.init = &(const struct clk_init_data) { 458 .name = "disp_cc_mdss_dptx1_pixel1_clk_src", 459 .parent_data = disp_cc_parent_data_0, 460 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 461 .flags = CLK_SET_RATE_PARENT, 462 .ops = &clk_dp_ops, 463 }, 464 }; 465 466 static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = { 467 .cmd_rcgr = 0x82fc, 468 .mnd_width = 0, 469 .hid_width = 5, 470 .parent_map = disp_cc_parent_map_1, 471 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 472 .clkr.hw.init = &(const struct clk_init_data) { 473 .name = "disp_cc_mdss_dptx2_aux_clk_src", 474 .parent_data = disp_cc_parent_data_1, 475 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 476 .flags = CLK_SET_RATE_PARENT, 477 .ops = &clk_rcg2_shared_ops, 478 }, 479 }; 480 481 static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { 482 .cmd_rcgr = 0x82b0, 483 .mnd_width = 0, 484 .hid_width = 5, 485 .parent_map = disp_cc_parent_map_3, 486 .clkr.hw.init = &(const struct clk_init_data) { 487 .name = "disp_cc_mdss_dptx2_link_clk_src", 488 .parent_data = disp_cc_parent_data_3, 489 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 490 .flags = CLK_SET_RATE_PARENT, 491 .ops = &clk_byte2_ops, 492 }, 493 }; 494 495 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = { 496 .cmd_rcgr = 0x82cc, 497 .mnd_width = 16, 498 .hid_width = 5, 499 .parent_map = disp_cc_parent_map_0, 500 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 501 .clkr.hw.init = &(const struct clk_init_data) { 502 .name = "disp_cc_mdss_dptx2_pixel0_clk_src", 503 .parent_data = disp_cc_parent_data_0, 504 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 505 .flags = CLK_SET_RATE_PARENT, 506 .ops = &clk_dp_ops, 507 }, 508 }; 509 510 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = { 511 .cmd_rcgr = 0x82e4, 512 .mnd_width = 16, 513 .hid_width = 5, 514 .parent_map = disp_cc_parent_map_0, 515 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 516 .clkr.hw.init = &(const struct clk_init_data) { 517 .name = "disp_cc_mdss_dptx2_pixel1_clk_src", 518 .parent_data = disp_cc_parent_data_0, 519 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 520 .flags = CLK_SET_RATE_PARENT, 521 .ops = &clk_dp_ops, 522 }, 523 }; 524 525 static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = { 526 .cmd_rcgr = 0x8348, 527 .mnd_width = 0, 528 .hid_width = 5, 529 .parent_map = disp_cc_parent_map_1, 530 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 531 .clkr.hw.init = &(const struct clk_init_data) { 532 .name = "disp_cc_mdss_dptx3_aux_clk_src", 533 .parent_data = disp_cc_parent_data_1, 534 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 535 .flags = CLK_SET_RATE_PARENT, 536 .ops = &clk_rcg2_shared_ops, 537 }, 538 }; 539 540 static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { 541 .cmd_rcgr = 0x832c, 542 .mnd_width = 0, 543 .hid_width = 5, 544 .parent_map = disp_cc_parent_map_3, 545 .clkr.hw.init = &(const struct clk_init_data) { 546 .name = "disp_cc_mdss_dptx3_link_clk_src", 547 .parent_data = disp_cc_parent_data_3, 548 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 549 .flags = CLK_SET_RATE_PARENT, 550 .ops = &clk_byte2_ops, 551 }, 552 }; 553 554 static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = { 555 .cmd_rcgr = 0x8314, 556 .mnd_width = 16, 557 .hid_width = 5, 558 .parent_map = disp_cc_parent_map_0, 559 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 560 .clkr.hw.init = &(const struct clk_init_data) { 561 .name = "disp_cc_mdss_dptx3_pixel0_clk_src", 562 .parent_data = disp_cc_parent_data_0, 563 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 564 .flags = CLK_SET_RATE_PARENT, 565 .ops = &clk_dp_ops, 566 }, 567 }; 568 569 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { 570 .cmd_rcgr = 0x81b8, 571 .mnd_width = 0, 572 .hid_width = 5, 573 .parent_map = disp_cc_parent_map_5, 574 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 575 .clkr.hw.init = &(const struct clk_init_data) { 576 .name = "disp_cc_mdss_esc0_clk_src", 577 .parent_data = disp_cc_parent_data_5, 578 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 579 .flags = CLK_SET_RATE_PARENT, 580 .ops = &clk_rcg2_shared_ops, 581 }, 582 }; 583 584 static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { 585 .cmd_rcgr = 0x81d0, 586 .mnd_width = 0, 587 .hid_width = 5, 588 .parent_map = disp_cc_parent_map_5, 589 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 590 .clkr.hw.init = &(const struct clk_init_data) { 591 .name = "disp_cc_mdss_esc1_clk_src", 592 .parent_data = disp_cc_parent_data_5, 593 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 594 .flags = CLK_SET_RATE_PARENT, 595 .ops = &clk_rcg2_shared_ops, 596 }, 597 }; 598 599 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { 600 F(19200000, P_BI_TCXO, 1, 0, 0), 601 F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 602 F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 603 F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 604 F(156000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 605 F(205000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 606 F(337000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 607 F(417000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 608 F(532000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 609 F(600000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 610 F(660000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 611 F(717000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 612 { } 613 }; 614 615 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { 616 .cmd_rcgr = 0x8150, 617 .mnd_width = 0, 618 .hid_width = 5, 619 .parent_map = disp_cc_parent_map_7, 620 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 621 .hw_clk_ctrl = true, 622 .clkr.hw.init = &(const struct clk_init_data) { 623 .name = "disp_cc_mdss_mdp_clk_src", 624 .parent_data = disp_cc_parent_data_7, 625 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), 626 .flags = CLK_SET_RATE_PARENT, 627 .ops = &clk_rcg2_shared_ops, 628 }, 629 }; 630 631 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { 632 .cmd_rcgr = 0x8108, 633 .mnd_width = 8, 634 .hid_width = 5, 635 .parent_map = disp_cc_parent_map_2, 636 .clkr.hw.init = &(const struct clk_init_data) { 637 .name = "disp_cc_mdss_pclk0_clk_src", 638 .parent_data = disp_cc_parent_data_2, 639 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 640 .flags = CLK_SET_RATE_PARENT, 641 .ops = &clk_pixel_ops, 642 }, 643 }; 644 645 static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { 646 .cmd_rcgr = 0x8120, 647 .mnd_width = 8, 648 .hid_width = 5, 649 .parent_map = disp_cc_parent_map_2, 650 .clkr.hw.init = &(const struct clk_init_data) { 651 .name = "disp_cc_mdss_pclk1_clk_src", 652 .parent_data = disp_cc_parent_data_2, 653 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 654 .flags = CLK_SET_RATE_PARENT, 655 .ops = &clk_pixel_ops, 656 }, 657 }; 658 659 static struct clk_rcg2 disp_cc_mdss_pclk2_clk_src = { 660 .cmd_rcgr = 0x8138, 661 .mnd_width = 8, 662 .hid_width = 5, 663 .parent_map = disp_cc_parent_map_2, 664 .clkr.hw.init = &(const struct clk_init_data) { 665 .name = "disp_cc_mdss_pclk2_clk_src", 666 .parent_data = disp_cc_parent_data_2, 667 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 668 .flags = CLK_SET_RATE_PARENT, 669 .ops = &clk_pixel_ops, 670 }, 671 }; 672 673 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { 674 .cmd_rcgr = 0x8168, 675 .mnd_width = 0, 676 .hid_width = 5, 677 .parent_map = disp_cc_parent_map_1, 678 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 679 .clkr.hw.init = &(const struct clk_init_data) { 680 .name = "disp_cc_mdss_vsync_clk_src", 681 .parent_data = disp_cc_parent_data_1, 682 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 683 .flags = CLK_SET_RATE_PARENT, 684 .ops = &clk_rcg2_shared_ops, 685 }, 686 }; 687 688 static struct clk_rcg2 disp_cc_osc_clk_src = { 689 .cmd_rcgr = 0x80f0, 690 .mnd_width = 0, 691 .hid_width = 5, 692 .parent_map = disp_cc_parent_map_8, 693 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 694 .clkr.hw.init = &(const struct clk_init_data) { 695 .name = "disp_cc_osc_clk_src", 696 .parent_data = disp_cc_parent_data_8, 697 .num_parents = ARRAY_SIZE(disp_cc_parent_data_8), 698 .flags = CLK_SET_RATE_PARENT, 699 .ops = &clk_rcg2_shared_ops, 700 }, 701 }; 702 703 static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = { 704 F(32000, P_SLEEP_CLK, 1, 0, 0), 705 { } 706 }; 707 708 static struct clk_rcg2 disp_cc_sleep_clk_src = { 709 .cmd_rcgr = 0xe064, 710 .mnd_width = 0, 711 .hid_width = 5, 712 .parent_map = disp_cc_parent_map_9, 713 .freq_tbl = ftbl_disp_cc_sleep_clk_src, 714 .clkr.hw.init = &(const struct clk_init_data) { 715 .name = "disp_cc_sleep_clk_src", 716 .parent_data = disp_cc_parent_data_9, 717 .num_parents = ARRAY_SIZE(disp_cc_parent_data_9), 718 .flags = CLK_SET_RATE_PARENT, 719 .ops = &clk_rcg2_shared_ops, 720 }, 721 }; 722 723 static struct clk_rcg2 disp_cc_xo_clk_src = { 724 .cmd_rcgr = 0xe044, 725 .mnd_width = 0, 726 .hid_width = 5, 727 .parent_map = disp_cc_parent_map_1, 728 .freq_tbl = ftbl_disp_cc_esync0_clk_src, 729 .clkr.hw.init = &(const struct clk_init_data) { 730 .name = "disp_cc_xo_clk_src", 731 .parent_data = disp_cc_parent_data_1, 732 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 733 .flags = CLK_SET_RATE_PARENT, 734 .ops = &clk_rcg2_shared_ops, 735 }, 736 }; 737 738 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { 739 .reg = 0x8198, 740 .shift = 0, 741 .width = 4, 742 .clkr.hw.init = &(const struct clk_init_data) { 743 .name = "disp_cc_mdss_byte0_div_clk_src", 744 .parent_hws = (const struct clk_hw*[]) { 745 &disp_cc_mdss_byte0_clk_src.clkr.hw, 746 }, 747 .num_parents = 1, 748 .ops = &clk_regmap_div_ops, 749 }, 750 }; 751 752 static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { 753 .reg = 0x81b4, 754 .shift = 0, 755 .width = 4, 756 .clkr.hw.init = &(const struct clk_init_data) { 757 .name = "disp_cc_mdss_byte1_div_clk_src", 758 .parent_hws = (const struct clk_hw*[]) { 759 &disp_cc_mdss_byte1_clk_src.clkr.hw, 760 }, 761 .num_parents = 1, 762 .ops = &clk_regmap_div_ops, 763 }, 764 }; 765 766 static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = { 767 .reg = 0x8200, 768 .shift = 0, 769 .width = 4, 770 .clkr.hw.init = &(const struct clk_init_data) { 771 .name = "disp_cc_mdss_dptx0_link_div_clk_src", 772 .parent_hws = (const struct clk_hw*[]) { 773 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 774 }, 775 .num_parents = 1, 776 .flags = CLK_SET_RATE_PARENT, 777 .ops = &clk_regmap_div_ro_ops, 778 }, 779 }; 780 781 static struct clk_regmap_div disp_cc_mdss_dptx0_link_dpin_div_clk_src = { 782 .reg = 0x838c, 783 .shift = 0, 784 .width = 4, 785 .clkr.hw.init = &(const struct clk_init_data) { 786 .name = "disp_cc_mdss_dptx0_link_dpin_div_clk_src", 787 .parent_hws = (const struct clk_hw*[]) { 788 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 789 }, 790 .num_parents = 1, 791 .flags = CLK_SET_RATE_PARENT, 792 .ops = &clk_regmap_div_ro_ops, 793 }, 794 }; 795 796 static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = { 797 .reg = 0x8294, 798 .shift = 0, 799 .width = 4, 800 .clkr.hw.init = &(const struct clk_init_data) { 801 .name = "disp_cc_mdss_dptx1_link_div_clk_src", 802 .parent_hws = (const struct clk_hw*[]) { 803 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 804 }, 805 .num_parents = 1, 806 .flags = CLK_SET_RATE_PARENT, 807 .ops = &clk_regmap_div_ro_ops, 808 }, 809 }; 810 811 static struct clk_regmap_div disp_cc_mdss_dptx1_link_dpin_div_clk_src = { 812 .reg = 0x8390, 813 .shift = 0, 814 .width = 4, 815 .clkr.hw.init = &(const struct clk_init_data) { 816 .name = "disp_cc_mdss_dptx1_link_dpin_div_clk_src", 817 .parent_hws = (const struct clk_hw*[]) { 818 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 819 }, 820 .num_parents = 1, 821 .flags = CLK_SET_RATE_PARENT, 822 .ops = &clk_regmap_div_ro_ops, 823 }, 824 }; 825 826 static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = { 827 .reg = 0x82c8, 828 .shift = 0, 829 .width = 4, 830 .clkr.hw.init = &(const struct clk_init_data) { 831 .name = "disp_cc_mdss_dptx2_link_div_clk_src", 832 .parent_hws = (const struct clk_hw*[]) { 833 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 834 }, 835 .num_parents = 1, 836 .flags = CLK_SET_RATE_PARENT, 837 .ops = &clk_regmap_div_ro_ops, 838 }, 839 }; 840 841 static struct clk_regmap_div disp_cc_mdss_dptx2_link_dpin_div_clk_src = { 842 .reg = 0x8394, 843 .shift = 0, 844 .width = 4, 845 .clkr.hw.init = &(const struct clk_init_data) { 846 .name = "disp_cc_mdss_dptx2_link_dpin_div_clk_src", 847 .parent_hws = (const struct clk_hw*[]) { 848 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 849 }, 850 .num_parents = 1, 851 .flags = CLK_SET_RATE_PARENT, 852 .ops = &clk_regmap_div_ro_ops, 853 }, 854 }; 855 856 static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = { 857 .reg = 0x8344, 858 .shift = 0, 859 .width = 4, 860 .clkr.hw.init = &(const struct clk_init_data) { 861 .name = "disp_cc_mdss_dptx3_link_div_clk_src", 862 .parent_hws = (const struct clk_hw*[]) { 863 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 864 }, 865 .num_parents = 1, 866 .flags = CLK_SET_RATE_PARENT, 867 .ops = &clk_regmap_div_ro_ops, 868 }, 869 }; 870 871 static struct clk_regmap_div disp_cc_mdss_dptx3_link_dpin_div_clk_src = { 872 .reg = 0x8398, 873 .shift = 0, 874 .width = 4, 875 .clkr.hw.init = &(const struct clk_init_data) { 876 .name = "disp_cc_mdss_dptx3_link_dpin_div_clk_src", 877 .parent_hws = (const struct clk_hw*[]) { 878 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 879 }, 880 .num_parents = 1, 881 .flags = CLK_SET_RATE_PARENT, 882 .ops = &clk_regmap_div_ro_ops, 883 }, 884 }; 885 886 static struct clk_branch disp_cc_esync0_clk = { 887 .halt_reg = 0x80b8, 888 .halt_check = BRANCH_HALT, 889 .clkr = { 890 .enable_reg = 0x80b8, 891 .enable_mask = BIT(0), 892 .hw.init = &(const struct clk_init_data) { 893 .name = "disp_cc_esync0_clk", 894 .parent_hws = (const struct clk_hw*[]) { 895 &disp_cc_esync0_clk_src.clkr.hw, 896 }, 897 .num_parents = 1, 898 .flags = CLK_SET_RATE_PARENT, 899 .ops = &clk_branch2_ops, 900 }, 901 }, 902 }; 903 904 static struct clk_branch disp_cc_esync1_clk = { 905 .halt_reg = 0x80bc, 906 .halt_check = BRANCH_HALT, 907 .clkr = { 908 .enable_reg = 0x80bc, 909 .enable_mask = BIT(0), 910 .hw.init = &(const struct clk_init_data) { 911 .name = "disp_cc_esync1_clk", 912 .parent_hws = (const struct clk_hw*[]) { 913 &disp_cc_esync1_clk_src.clkr.hw, 914 }, 915 .num_parents = 1, 916 .flags = CLK_SET_RATE_PARENT, 917 .ops = &clk_branch2_ops, 918 }, 919 }, 920 }; 921 922 static struct clk_branch disp_cc_mdss_accu_shift_clk = { 923 .halt_reg = 0xe060, 924 .halt_check = BRANCH_HALT_VOTED, 925 .clkr = { 926 .enable_reg = 0xe060, 927 .enable_mask = BIT(0), 928 .hw.init = &(const struct clk_init_data) { 929 .name = "disp_cc_mdss_accu_shift_clk", 930 .parent_hws = (const struct clk_hw*[]) { 931 &disp_cc_xo_clk_src.clkr.hw, 932 }, 933 .num_parents = 1, 934 .flags = CLK_SET_RATE_PARENT, 935 .ops = &clk_branch2_ops, 936 }, 937 }, 938 }; 939 940 static struct clk_branch disp_cc_mdss_ahb1_clk = { 941 .halt_reg = 0xa028, 942 .halt_check = BRANCH_HALT, 943 .clkr = { 944 .enable_reg = 0xa028, 945 .enable_mask = BIT(0), 946 .hw.init = &(const struct clk_init_data) { 947 .name = "disp_cc_mdss_ahb1_clk", 948 .parent_hws = (const struct clk_hw*[]) { 949 &disp_cc_mdss_ahb_clk_src.clkr.hw, 950 }, 951 .num_parents = 1, 952 .flags = CLK_SET_RATE_PARENT, 953 .ops = &clk_branch2_ops, 954 }, 955 }, 956 }; 957 958 static struct clk_branch disp_cc_mdss_ahb_clk = { 959 .halt_reg = 0x80b0, 960 .halt_check = BRANCH_HALT, 961 .clkr = { 962 .enable_reg = 0x80b0, 963 .enable_mask = BIT(0), 964 .hw.init = &(const struct clk_init_data) { 965 .name = "disp_cc_mdss_ahb_clk", 966 .parent_hws = (const struct clk_hw*[]) { 967 &disp_cc_mdss_ahb_clk_src.clkr.hw, 968 }, 969 .num_parents = 1, 970 .flags = CLK_SET_RATE_PARENT, 971 .ops = &clk_branch2_ops, 972 }, 973 }, 974 }; 975 976 static struct clk_branch disp_cc_mdss_byte0_clk = { 977 .halt_reg = 0x8034, 978 .halt_check = BRANCH_HALT, 979 .clkr = { 980 .enable_reg = 0x8034, 981 .enable_mask = BIT(0), 982 .hw.init = &(const struct clk_init_data) { 983 .name = "disp_cc_mdss_byte0_clk", 984 .parent_hws = (const struct clk_hw*[]) { 985 &disp_cc_mdss_byte0_clk_src.clkr.hw, 986 }, 987 .num_parents = 1, 988 .flags = CLK_SET_RATE_PARENT, 989 .ops = &clk_branch2_ops, 990 }, 991 }, 992 }; 993 994 static struct clk_branch disp_cc_mdss_byte0_intf_clk = { 995 .halt_reg = 0x8038, 996 .halt_check = BRANCH_HALT, 997 .clkr = { 998 .enable_reg = 0x8038, 999 .enable_mask = BIT(0), 1000 .hw.init = &(const struct clk_init_data) { 1001 .name = "disp_cc_mdss_byte0_intf_clk", 1002 .parent_hws = (const struct clk_hw*[]) { 1003 &disp_cc_mdss_byte0_div_clk_src.clkr.hw, 1004 }, 1005 .num_parents = 1, 1006 .flags = CLK_SET_RATE_PARENT, 1007 .ops = &clk_branch2_ops, 1008 }, 1009 }, 1010 }; 1011 1012 static struct clk_branch disp_cc_mdss_byte1_clk = { 1013 .halt_reg = 0x803c, 1014 .halt_check = BRANCH_HALT, 1015 .clkr = { 1016 .enable_reg = 0x803c, 1017 .enable_mask = BIT(0), 1018 .hw.init = &(const struct clk_init_data) { 1019 .name = "disp_cc_mdss_byte1_clk", 1020 .parent_hws = (const struct clk_hw*[]) { 1021 &disp_cc_mdss_byte1_clk_src.clkr.hw, 1022 }, 1023 .num_parents = 1, 1024 .flags = CLK_SET_RATE_PARENT, 1025 .ops = &clk_branch2_ops, 1026 }, 1027 }, 1028 }; 1029 1030 static struct clk_branch disp_cc_mdss_byte1_intf_clk = { 1031 .halt_reg = 0x8040, 1032 .halt_check = BRANCH_HALT, 1033 .clkr = { 1034 .enable_reg = 0x8040, 1035 .enable_mask = BIT(0), 1036 .hw.init = &(const struct clk_init_data) { 1037 .name = "disp_cc_mdss_byte1_intf_clk", 1038 .parent_hws = (const struct clk_hw*[]) { 1039 &disp_cc_mdss_byte1_div_clk_src.clkr.hw, 1040 }, 1041 .num_parents = 1, 1042 .flags = CLK_SET_RATE_PARENT, 1043 .ops = &clk_branch2_ops, 1044 }, 1045 }, 1046 }; 1047 1048 static struct clk_branch disp_cc_mdss_dptx0_aux_clk = { 1049 .halt_reg = 0x8064, 1050 .halt_check = BRANCH_HALT, 1051 .clkr = { 1052 .enable_reg = 0x8064, 1053 .enable_mask = BIT(0), 1054 .hw.init = &(const struct clk_init_data) { 1055 .name = "disp_cc_mdss_dptx0_aux_clk", 1056 .parent_hws = (const struct clk_hw*[]) { 1057 &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, 1058 }, 1059 .num_parents = 1, 1060 .flags = CLK_SET_RATE_PARENT, 1061 .ops = &clk_branch2_ops, 1062 }, 1063 }, 1064 }; 1065 1066 static struct clk_branch disp_cc_mdss_dptx0_link_clk = { 1067 .halt_reg = 0x804c, 1068 .halt_check = BRANCH_HALT, 1069 .clkr = { 1070 .enable_reg = 0x804c, 1071 .enable_mask = BIT(0), 1072 .hw.init = &(const struct clk_init_data) { 1073 .name = "disp_cc_mdss_dptx0_link_clk", 1074 .parent_hws = (const struct clk_hw*[]) { 1075 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 1076 }, 1077 .num_parents = 1, 1078 .flags = CLK_SET_RATE_PARENT, 1079 .ops = &clk_branch2_ops, 1080 }, 1081 }, 1082 }; 1083 1084 static struct clk_branch disp_cc_mdss_dptx0_link_dpin_clk = { 1085 .halt_reg = 0x837c, 1086 .halt_check = BRANCH_HALT, 1087 .clkr = { 1088 .enable_reg = 0x837c, 1089 .enable_mask = BIT(0), 1090 .hw.init = &(const struct clk_init_data) { 1091 .name = "disp_cc_mdss_dptx0_link_dpin_clk", 1092 .parent_hws = (const struct clk_hw*[]) { 1093 &disp_cc_mdss_dptx0_link_dpin_div_clk_src.clkr.hw, 1094 }, 1095 .num_parents = 1, 1096 .flags = CLK_SET_RATE_PARENT, 1097 .ops = &clk_branch2_ops, 1098 }, 1099 }, 1100 }; 1101 1102 static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = { 1103 .halt_reg = 0x8054, 1104 .halt_check = BRANCH_HALT, 1105 .clkr = { 1106 .enable_reg = 0x8054, 1107 .enable_mask = BIT(0), 1108 .hw.init = &(const struct clk_init_data) { 1109 .name = "disp_cc_mdss_dptx0_link_intf_clk", 1110 .parent_hws = (const struct clk_hw*[]) { 1111 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1112 }, 1113 .num_parents = 1, 1114 .flags = CLK_SET_RATE_PARENT, 1115 .ops = &clk_branch2_ops, 1116 }, 1117 }, 1118 }; 1119 1120 static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = { 1121 .halt_reg = 0x805c, 1122 .halt_check = BRANCH_HALT, 1123 .clkr = { 1124 .enable_reg = 0x805c, 1125 .enable_mask = BIT(0), 1126 .hw.init = &(const struct clk_init_data) { 1127 .name = "disp_cc_mdss_dptx0_pixel0_clk", 1128 .parent_hws = (const struct clk_hw*[]) { 1129 &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, 1130 }, 1131 .num_parents = 1, 1132 .flags = CLK_SET_RATE_PARENT, 1133 .ops = &clk_branch2_ops, 1134 }, 1135 }, 1136 }; 1137 1138 static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = { 1139 .halt_reg = 0x8060, 1140 .halt_check = BRANCH_HALT, 1141 .clkr = { 1142 .enable_reg = 0x8060, 1143 .enable_mask = BIT(0), 1144 .hw.init = &(const struct clk_init_data) { 1145 .name = "disp_cc_mdss_dptx0_pixel1_clk", 1146 .parent_hws = (const struct clk_hw*[]) { 1147 &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, 1148 }, 1149 .num_parents = 1, 1150 .flags = CLK_SET_RATE_PARENT, 1151 .ops = &clk_branch2_ops, 1152 }, 1153 }, 1154 }; 1155 1156 static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = { 1157 .halt_reg = 0x8050, 1158 .halt_check = BRANCH_HALT, 1159 .clkr = { 1160 .enable_reg = 0x8050, 1161 .enable_mask = BIT(0), 1162 .hw.init = &(const struct clk_init_data) { 1163 .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk", 1164 .parent_hws = (const struct clk_hw*[]) { 1165 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1166 }, 1167 .num_parents = 1, 1168 .flags = CLK_SET_RATE_PARENT, 1169 .ops = &clk_branch2_ops, 1170 }, 1171 }, 1172 }; 1173 1174 static struct clk_branch disp_cc_mdss_dptx1_aux_clk = { 1175 .halt_reg = 0x8080, 1176 .halt_check = BRANCH_HALT, 1177 .clkr = { 1178 .enable_reg = 0x8080, 1179 .enable_mask = BIT(0), 1180 .hw.init = &(const struct clk_init_data) { 1181 .name = "disp_cc_mdss_dptx1_aux_clk", 1182 .parent_hws = (const struct clk_hw*[]) { 1183 &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, 1184 }, 1185 .num_parents = 1, 1186 .flags = CLK_SET_RATE_PARENT, 1187 .ops = &clk_branch2_ops, 1188 }, 1189 }, 1190 }; 1191 1192 static struct clk_branch disp_cc_mdss_dptx1_link_clk = { 1193 .halt_reg = 0x8070, 1194 .halt_check = BRANCH_HALT, 1195 .clkr = { 1196 .enable_reg = 0x8070, 1197 .enable_mask = BIT(0), 1198 .hw.init = &(const struct clk_init_data) { 1199 .name = "disp_cc_mdss_dptx1_link_clk", 1200 .parent_hws = (const struct clk_hw*[]) { 1201 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 1202 }, 1203 .num_parents = 1, 1204 .flags = CLK_SET_RATE_PARENT, 1205 .ops = &clk_branch2_ops, 1206 }, 1207 }, 1208 }; 1209 1210 static struct clk_branch disp_cc_mdss_dptx1_link_dpin_clk = { 1211 .halt_reg = 0x8380, 1212 .halt_check = BRANCH_HALT, 1213 .clkr = { 1214 .enable_reg = 0x8380, 1215 .enable_mask = BIT(0), 1216 .hw.init = &(const struct clk_init_data) { 1217 .name = "disp_cc_mdss_dptx1_link_dpin_clk", 1218 .parent_hws = (const struct clk_hw*[]) { 1219 &disp_cc_mdss_dptx1_link_dpin_div_clk_src.clkr.hw, 1220 }, 1221 .num_parents = 1, 1222 .flags = CLK_SET_RATE_PARENT, 1223 .ops = &clk_branch2_ops, 1224 }, 1225 }, 1226 }; 1227 1228 static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = { 1229 .halt_reg = 0x8078, 1230 .halt_check = BRANCH_HALT, 1231 .clkr = { 1232 .enable_reg = 0x8078, 1233 .enable_mask = BIT(0), 1234 .hw.init = &(const struct clk_init_data) { 1235 .name = "disp_cc_mdss_dptx1_link_intf_clk", 1236 .parent_hws = (const struct clk_hw*[]) { 1237 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1238 }, 1239 .num_parents = 1, 1240 .flags = CLK_SET_RATE_PARENT, 1241 .ops = &clk_branch2_ops, 1242 }, 1243 }, 1244 }; 1245 1246 static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = { 1247 .halt_reg = 0x8068, 1248 .halt_check = BRANCH_HALT, 1249 .clkr = { 1250 .enable_reg = 0x8068, 1251 .enable_mask = BIT(0), 1252 .hw.init = &(const struct clk_init_data) { 1253 .name = "disp_cc_mdss_dptx1_pixel0_clk", 1254 .parent_hws = (const struct clk_hw*[]) { 1255 &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, 1256 }, 1257 .num_parents = 1, 1258 .flags = CLK_SET_RATE_PARENT, 1259 .ops = &clk_branch2_ops, 1260 }, 1261 }, 1262 }; 1263 1264 static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = { 1265 .halt_reg = 0x806c, 1266 .halt_check = BRANCH_HALT, 1267 .clkr = { 1268 .enable_reg = 0x806c, 1269 .enable_mask = BIT(0), 1270 .hw.init = &(const struct clk_init_data) { 1271 .name = "disp_cc_mdss_dptx1_pixel1_clk", 1272 .parent_hws = (const struct clk_hw*[]) { 1273 &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, 1274 }, 1275 .num_parents = 1, 1276 .flags = CLK_SET_RATE_PARENT, 1277 .ops = &clk_branch2_ops, 1278 }, 1279 }, 1280 }; 1281 1282 static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = { 1283 .halt_reg = 0x8074, 1284 .halt_check = BRANCH_HALT, 1285 .clkr = { 1286 .enable_reg = 0x8074, 1287 .enable_mask = BIT(0), 1288 .hw.init = &(const struct clk_init_data) { 1289 .name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk", 1290 .parent_hws = (const struct clk_hw*[]) { 1291 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1292 }, 1293 .num_parents = 1, 1294 .flags = CLK_SET_RATE_PARENT, 1295 .ops = &clk_branch2_ops, 1296 }, 1297 }, 1298 }; 1299 1300 static struct clk_branch disp_cc_mdss_dptx2_aux_clk = { 1301 .halt_reg = 0x8098, 1302 .halt_check = BRANCH_HALT, 1303 .clkr = { 1304 .enable_reg = 0x8098, 1305 .enable_mask = BIT(0), 1306 .hw.init = &(const struct clk_init_data) { 1307 .name = "disp_cc_mdss_dptx2_aux_clk", 1308 .parent_hws = (const struct clk_hw*[]) { 1309 &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw, 1310 }, 1311 .num_parents = 1, 1312 .flags = CLK_SET_RATE_PARENT, 1313 .ops = &clk_branch2_ops, 1314 }, 1315 }, 1316 }; 1317 1318 static struct clk_branch disp_cc_mdss_dptx2_link_clk = { 1319 .halt_reg = 0x808c, 1320 .halt_check = BRANCH_HALT, 1321 .clkr = { 1322 .enable_reg = 0x808c, 1323 .enable_mask = BIT(0), 1324 .hw.init = &(const struct clk_init_data) { 1325 .name = "disp_cc_mdss_dptx2_link_clk", 1326 .parent_hws = (const struct clk_hw*[]) { 1327 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 1328 }, 1329 .num_parents = 1, 1330 .flags = CLK_SET_RATE_PARENT, 1331 .ops = &clk_branch2_ops, 1332 }, 1333 }, 1334 }; 1335 1336 static struct clk_branch disp_cc_mdss_dptx2_link_dpin_clk = { 1337 .halt_reg = 0x8384, 1338 .halt_check = BRANCH_HALT, 1339 .clkr = { 1340 .enable_reg = 0x8384, 1341 .enable_mask = BIT(0), 1342 .hw.init = &(const struct clk_init_data) { 1343 .name = "disp_cc_mdss_dptx2_link_dpin_clk", 1344 .parent_hws = (const struct clk_hw*[]) { 1345 &disp_cc_mdss_dptx2_link_dpin_div_clk_src.clkr.hw, 1346 }, 1347 .num_parents = 1, 1348 .flags = CLK_SET_RATE_PARENT, 1349 .ops = &clk_branch2_ops, 1350 }, 1351 }, 1352 }; 1353 1354 static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = { 1355 .halt_reg = 0x8090, 1356 .halt_check = BRANCH_HALT, 1357 .clkr = { 1358 .enable_reg = 0x8090, 1359 .enable_mask = BIT(0), 1360 .hw.init = &(const struct clk_init_data) { 1361 .name = "disp_cc_mdss_dptx2_link_intf_clk", 1362 .parent_hws = (const struct clk_hw*[]) { 1363 &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, 1364 }, 1365 .num_parents = 1, 1366 .flags = CLK_SET_RATE_PARENT, 1367 .ops = &clk_branch2_ops, 1368 }, 1369 }, 1370 }; 1371 1372 static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = { 1373 .halt_reg = 0x8084, 1374 .halt_check = BRANCH_HALT, 1375 .clkr = { 1376 .enable_reg = 0x8084, 1377 .enable_mask = BIT(0), 1378 .hw.init = &(const struct clk_init_data) { 1379 .name = "disp_cc_mdss_dptx2_pixel0_clk", 1380 .parent_hws = (const struct clk_hw*[]) { 1381 &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, 1382 }, 1383 .num_parents = 1, 1384 .flags = CLK_SET_RATE_PARENT, 1385 .ops = &clk_branch2_ops, 1386 }, 1387 }, 1388 }; 1389 1390 static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = { 1391 .halt_reg = 0x8088, 1392 .halt_check = BRANCH_HALT, 1393 .clkr = { 1394 .enable_reg = 0x8088, 1395 .enable_mask = BIT(0), 1396 .hw.init = &(const struct clk_init_data) { 1397 .name = "disp_cc_mdss_dptx2_pixel1_clk", 1398 .parent_hws = (const struct clk_hw*[]) { 1399 &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, 1400 }, 1401 .num_parents = 1, 1402 .flags = CLK_SET_RATE_PARENT, 1403 .ops = &clk_branch2_ops, 1404 }, 1405 }, 1406 }; 1407 1408 static struct clk_branch disp_cc_mdss_dptx2_usb_router_link_intf_clk = { 1409 .halt_reg = 0x8378, 1410 .halt_check = BRANCH_HALT, 1411 .clkr = { 1412 .enable_reg = 0x8378, 1413 .enable_mask = BIT(0), 1414 .hw.init = &(const struct clk_init_data) { 1415 .name = "disp_cc_mdss_dptx2_usb_router_link_intf_clk", 1416 .parent_hws = (const struct clk_hw*[]) { 1417 &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, 1418 }, 1419 .num_parents = 1, 1420 .flags = CLK_SET_RATE_PARENT, 1421 .ops = &clk_branch2_ops, 1422 }, 1423 }, 1424 }; 1425 1426 static struct clk_branch disp_cc_mdss_dptx3_aux_clk = { 1427 .halt_reg = 0x80a8, 1428 .halt_check = BRANCH_HALT, 1429 .clkr = { 1430 .enable_reg = 0x80a8, 1431 .enable_mask = BIT(0), 1432 .hw.init = &(const struct clk_init_data) { 1433 .name = "disp_cc_mdss_dptx3_aux_clk", 1434 .parent_hws = (const struct clk_hw*[]) { 1435 &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw, 1436 }, 1437 .num_parents = 1, 1438 .flags = CLK_SET_RATE_PARENT, 1439 .ops = &clk_branch2_ops, 1440 }, 1441 }, 1442 }; 1443 1444 static struct clk_branch disp_cc_mdss_dptx3_link_clk = { 1445 .halt_reg = 0x80a0, 1446 .halt_check = BRANCH_HALT, 1447 .clkr = { 1448 .enable_reg = 0x80a0, 1449 .enable_mask = BIT(0), 1450 .hw.init = &(const struct clk_init_data) { 1451 .name = "disp_cc_mdss_dptx3_link_clk", 1452 .parent_hws = (const struct clk_hw*[]) { 1453 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 1454 }, 1455 .num_parents = 1, 1456 .flags = CLK_SET_RATE_PARENT, 1457 .ops = &clk_branch2_ops, 1458 }, 1459 }, 1460 }; 1461 1462 static struct clk_branch disp_cc_mdss_dptx3_link_dpin_clk = { 1463 .halt_reg = 0x8388, 1464 .halt_check = BRANCH_HALT, 1465 .clkr = { 1466 .enable_reg = 0x8388, 1467 .enable_mask = BIT(0), 1468 .hw.init = &(const struct clk_init_data) { 1469 .name = "disp_cc_mdss_dptx3_link_dpin_clk", 1470 .parent_hws = (const struct clk_hw*[]) { 1471 &disp_cc_mdss_dptx3_link_dpin_div_clk_src.clkr.hw, 1472 }, 1473 .num_parents = 1, 1474 .flags = CLK_SET_RATE_PARENT, 1475 .ops = &clk_branch2_ops, 1476 }, 1477 }, 1478 }; 1479 1480 static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = { 1481 .halt_reg = 0x80a4, 1482 .halt_check = BRANCH_HALT, 1483 .clkr = { 1484 .enable_reg = 0x80a4, 1485 .enable_mask = BIT(0), 1486 .hw.init = &(const struct clk_init_data) { 1487 .name = "disp_cc_mdss_dptx3_link_intf_clk", 1488 .parent_hws = (const struct clk_hw*[]) { 1489 &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw, 1490 }, 1491 .num_parents = 1, 1492 .flags = CLK_SET_RATE_PARENT, 1493 .ops = &clk_branch2_ops, 1494 }, 1495 }, 1496 }; 1497 1498 static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = { 1499 .halt_reg = 0x809c, 1500 .halt_check = BRANCH_HALT, 1501 .clkr = { 1502 .enable_reg = 0x809c, 1503 .enable_mask = BIT(0), 1504 .hw.init = &(const struct clk_init_data) { 1505 .name = "disp_cc_mdss_dptx3_pixel0_clk", 1506 .parent_hws = (const struct clk_hw*[]) { 1507 &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, 1508 }, 1509 .num_parents = 1, 1510 .flags = CLK_SET_RATE_PARENT, 1511 .ops = &clk_branch2_ops, 1512 }, 1513 }, 1514 }; 1515 1516 static struct clk_branch disp_cc_mdss_esc0_clk = { 1517 .halt_reg = 0x8044, 1518 .halt_check = BRANCH_HALT, 1519 .clkr = { 1520 .enable_reg = 0x8044, 1521 .enable_mask = BIT(0), 1522 .hw.init = &(const struct clk_init_data) { 1523 .name = "disp_cc_mdss_esc0_clk", 1524 .parent_hws = (const struct clk_hw*[]) { 1525 &disp_cc_mdss_esc0_clk_src.clkr.hw, 1526 }, 1527 .num_parents = 1, 1528 .flags = CLK_SET_RATE_PARENT, 1529 .ops = &clk_branch2_ops, 1530 }, 1531 }, 1532 }; 1533 1534 static struct clk_branch disp_cc_mdss_esc1_clk = { 1535 .halt_reg = 0x8048, 1536 .halt_check = BRANCH_HALT, 1537 .clkr = { 1538 .enable_reg = 0x8048, 1539 .enable_mask = BIT(0), 1540 .hw.init = &(const struct clk_init_data) { 1541 .name = "disp_cc_mdss_esc1_clk", 1542 .parent_hws = (const struct clk_hw*[]) { 1543 &disp_cc_mdss_esc1_clk_src.clkr.hw, 1544 }, 1545 .num_parents = 1, 1546 .flags = CLK_SET_RATE_PARENT, 1547 .ops = &clk_branch2_ops, 1548 }, 1549 }, 1550 }; 1551 1552 static struct clk_branch disp_cc_mdss_mdp1_clk = { 1553 .halt_reg = 0xa004, 1554 .halt_check = BRANCH_HALT, 1555 .clkr = { 1556 .enable_reg = 0xa004, 1557 .enable_mask = BIT(0), 1558 .hw.init = &(const struct clk_init_data) { 1559 .name = "disp_cc_mdss_mdp1_clk", 1560 .parent_hws = (const struct clk_hw*[]) { 1561 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1562 }, 1563 .num_parents = 1, 1564 .flags = CLK_SET_RATE_PARENT, 1565 .ops = &clk_branch2_ops, 1566 }, 1567 }, 1568 }; 1569 1570 static struct clk_branch disp_cc_mdss_mdp_clk = { 1571 .halt_reg = 0x8010, 1572 .halt_check = BRANCH_HALT, 1573 .clkr = { 1574 .enable_reg = 0x8010, 1575 .enable_mask = BIT(0), 1576 .hw.init = &(const struct clk_init_data) { 1577 .name = "disp_cc_mdss_mdp_clk", 1578 .parent_hws = (const struct clk_hw*[]) { 1579 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1580 }, 1581 .num_parents = 1, 1582 .flags = CLK_SET_RATE_PARENT, 1583 .ops = &clk_branch2_ops, 1584 }, 1585 }, 1586 }; 1587 1588 static struct clk_branch disp_cc_mdss_mdp_lut1_clk = { 1589 .halt_reg = 0xa014, 1590 .halt_check = BRANCH_HALT_VOTED, 1591 .clkr = { 1592 .enable_reg = 0xa014, 1593 .enable_mask = BIT(0), 1594 .hw.init = &(const struct clk_init_data) { 1595 .name = "disp_cc_mdss_mdp_lut1_clk", 1596 .parent_hws = (const struct clk_hw*[]) { 1597 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1598 }, 1599 .num_parents = 1, 1600 .flags = CLK_SET_RATE_PARENT, 1601 .ops = &clk_branch2_ops, 1602 }, 1603 }, 1604 }; 1605 1606 static struct clk_branch disp_cc_mdss_mdp_lut_clk = { 1607 .halt_reg = 0x8020, 1608 .halt_check = BRANCH_HALT_VOTED, 1609 .clkr = { 1610 .enable_reg = 0x8020, 1611 .enable_mask = BIT(0), 1612 .hw.init = &(const struct clk_init_data) { 1613 .name = "disp_cc_mdss_mdp_lut_clk", 1614 .parent_hws = (const struct clk_hw*[]) { 1615 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1616 }, 1617 .num_parents = 1, 1618 .flags = CLK_SET_RATE_PARENT, 1619 .ops = &clk_branch2_ops, 1620 }, 1621 }, 1622 }; 1623 1624 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { 1625 .halt_reg = 0xc004, 1626 .halt_check = BRANCH_HALT_VOTED, 1627 .clkr = { 1628 .enable_reg = 0xc004, 1629 .enable_mask = BIT(0), 1630 .hw.init = &(const struct clk_init_data) { 1631 .name = "disp_cc_mdss_non_gdsc_ahb_clk", 1632 .parent_hws = (const struct clk_hw*[]) { 1633 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1634 }, 1635 .num_parents = 1, 1636 .flags = CLK_SET_RATE_PARENT, 1637 .ops = &clk_branch2_ops, 1638 }, 1639 }, 1640 }; 1641 1642 static struct clk_branch disp_cc_mdss_pclk0_clk = { 1643 .halt_reg = 0x8004, 1644 .halt_check = BRANCH_HALT, 1645 .clkr = { 1646 .enable_reg = 0x8004, 1647 .enable_mask = BIT(0), 1648 .hw.init = &(const struct clk_init_data) { 1649 .name = "disp_cc_mdss_pclk0_clk", 1650 .parent_hws = (const struct clk_hw*[]) { 1651 &disp_cc_mdss_pclk0_clk_src.clkr.hw, 1652 }, 1653 .num_parents = 1, 1654 .flags = CLK_SET_RATE_PARENT, 1655 .ops = &clk_branch2_ops, 1656 }, 1657 }, 1658 }; 1659 1660 static struct clk_branch disp_cc_mdss_pclk1_clk = { 1661 .halt_reg = 0x8008, 1662 .halt_check = BRANCH_HALT, 1663 .clkr = { 1664 .enable_reg = 0x8008, 1665 .enable_mask = BIT(0), 1666 .hw.init = &(const struct clk_init_data) { 1667 .name = "disp_cc_mdss_pclk1_clk", 1668 .parent_hws = (const struct clk_hw*[]) { 1669 &disp_cc_mdss_pclk1_clk_src.clkr.hw, 1670 }, 1671 .num_parents = 1, 1672 .flags = CLK_SET_RATE_PARENT, 1673 .ops = &clk_branch2_ops, 1674 }, 1675 }, 1676 }; 1677 1678 static struct clk_branch disp_cc_mdss_pclk2_clk = { 1679 .halt_reg = 0x800c, 1680 .halt_check = BRANCH_HALT, 1681 .clkr = { 1682 .enable_reg = 0x800c, 1683 .enable_mask = BIT(0), 1684 .hw.init = &(const struct clk_init_data) { 1685 .name = "disp_cc_mdss_pclk2_clk", 1686 .parent_hws = (const struct clk_hw*[]) { 1687 &disp_cc_mdss_pclk2_clk_src.clkr.hw, 1688 }, 1689 .num_parents = 1, 1690 .flags = CLK_SET_RATE_PARENT, 1691 .ops = &clk_branch2_ops, 1692 }, 1693 }, 1694 }; 1695 1696 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { 1697 .halt_reg = 0xc00c, 1698 .halt_check = BRANCH_HALT, 1699 .clkr = { 1700 .enable_reg = 0xc00c, 1701 .enable_mask = BIT(0), 1702 .hw.init = &(const struct clk_init_data) { 1703 .name = "disp_cc_mdss_rscc_ahb_clk", 1704 .parent_hws = (const struct clk_hw*[]) { 1705 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1706 }, 1707 .num_parents = 1, 1708 .flags = CLK_SET_RATE_PARENT, 1709 .ops = &clk_branch2_ops, 1710 }, 1711 }, 1712 }; 1713 1714 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { 1715 .halt_reg = 0xc008, 1716 .halt_check = BRANCH_HALT, 1717 .clkr = { 1718 .enable_reg = 0xc008, 1719 .enable_mask = BIT(0), 1720 .hw.init = &(const struct clk_init_data) { 1721 .name = "disp_cc_mdss_rscc_vsync_clk", 1722 .parent_hws = (const struct clk_hw*[]) { 1723 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1724 }, 1725 .num_parents = 1, 1726 .flags = CLK_SET_RATE_PARENT, 1727 .ops = &clk_branch2_ops, 1728 }, 1729 }, 1730 }; 1731 1732 static struct clk_branch disp_cc_mdss_vsync1_clk = { 1733 .halt_reg = 0xa024, 1734 .halt_check = BRANCH_HALT, 1735 .clkr = { 1736 .enable_reg = 0xa024, 1737 .enable_mask = BIT(0), 1738 .hw.init = &(const struct clk_init_data) { 1739 .name = "disp_cc_mdss_vsync1_clk", 1740 .parent_hws = (const struct clk_hw*[]) { 1741 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1742 }, 1743 .num_parents = 1, 1744 .flags = CLK_SET_RATE_PARENT, 1745 .ops = &clk_branch2_ops, 1746 }, 1747 }, 1748 }; 1749 1750 static struct clk_branch disp_cc_mdss_vsync_clk = { 1751 .halt_reg = 0x8030, 1752 .halt_check = BRANCH_HALT, 1753 .clkr = { 1754 .enable_reg = 0x8030, 1755 .enable_mask = BIT(0), 1756 .hw.init = &(const struct clk_init_data) { 1757 .name = "disp_cc_mdss_vsync_clk", 1758 .parent_hws = (const struct clk_hw*[]) { 1759 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1760 }, 1761 .num_parents = 1, 1762 .flags = CLK_SET_RATE_PARENT, 1763 .ops = &clk_branch2_ops, 1764 }, 1765 }, 1766 }; 1767 1768 static struct clk_branch disp_cc_osc_clk = { 1769 .halt_reg = 0x80b4, 1770 .halt_check = BRANCH_HALT, 1771 .clkr = { 1772 .enable_reg = 0x80b4, 1773 .enable_mask = BIT(0), 1774 .hw.init = &(const struct clk_init_data) { 1775 .name = "disp_cc_osc_clk", 1776 .parent_hws = (const struct clk_hw*[]) { 1777 &disp_cc_osc_clk_src.clkr.hw, 1778 }, 1779 .num_parents = 1, 1780 .flags = CLK_SET_RATE_PARENT, 1781 .ops = &clk_branch2_ops, 1782 }, 1783 }, 1784 }; 1785 1786 static struct gdsc disp_cc_mdss_core_gdsc = { 1787 .gdscr = 0x9000, 1788 .en_rest_wait_val = 0x2, 1789 .en_few_wait_val = 0x2, 1790 .clk_dis_wait_val = 0xf, 1791 .pd = { 1792 .name = "disp_cc_mdss_core_gdsc", 1793 }, 1794 .pwrsts = PWRSTS_OFF_ON, 1795 .flags = HW_CTRL | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1796 }; 1797 1798 static struct gdsc disp_cc_mdss_core_int2_gdsc = { 1799 .gdscr = 0xb000, 1800 .en_rest_wait_val = 0x2, 1801 .en_few_wait_val = 0x2, 1802 .clk_dis_wait_val = 0xf, 1803 .pd = { 1804 .name = "disp_cc_mdss_core_int2_gdsc", 1805 }, 1806 .pwrsts = PWRSTS_OFF_ON, 1807 .flags = HW_CTRL | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1808 }; 1809 1810 static struct clk_regmap *disp_cc_glymur_clocks[] = { 1811 [DISP_CC_ESYNC0_CLK] = &disp_cc_esync0_clk.clkr, 1812 [DISP_CC_ESYNC0_CLK_SRC] = &disp_cc_esync0_clk_src.clkr, 1813 [DISP_CC_ESYNC1_CLK] = &disp_cc_esync1_clk.clkr, 1814 [DISP_CC_ESYNC1_CLK_SRC] = &disp_cc_esync1_clk_src.clkr, 1815 [DISP_CC_MDSS_ACCU_SHIFT_CLK] = &disp_cc_mdss_accu_shift_clk.clkr, 1816 [DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr, 1817 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, 1818 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, 1819 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, 1820 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, 1821 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, 1822 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, 1823 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr, 1824 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr, 1825 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr, 1826 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, 1827 [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr, 1828 [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr, 1829 [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr, 1830 [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr, 1831 [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr, 1832 [DISP_CC_MDSS_DPTX0_LINK_DPIN_CLK] = &disp_cc_mdss_dptx0_link_dpin_clk.clkr, 1833 [DISP_CC_MDSS_DPTX0_LINK_DPIN_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_dpin_div_clk_src.clkr, 1834 [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr, 1835 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr, 1836 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr, 1837 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr, 1838 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr, 1839 [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = 1840 &disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, 1841 [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr, 1842 [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr, 1843 [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr, 1844 [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr, 1845 [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr, 1846 [DISP_CC_MDSS_DPTX1_LINK_DPIN_CLK] = &disp_cc_mdss_dptx1_link_dpin_clk.clkr, 1847 [DISP_CC_MDSS_DPTX1_LINK_DPIN_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_dpin_div_clk_src.clkr, 1848 [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr, 1849 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr, 1850 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr, 1851 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr, 1852 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr, 1853 [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] = 1854 &disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, 1855 [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr, 1856 [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr, 1857 [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr, 1858 [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr, 1859 [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr, 1860 [DISP_CC_MDSS_DPTX2_LINK_DPIN_CLK] = &disp_cc_mdss_dptx2_link_dpin_clk.clkr, 1861 [DISP_CC_MDSS_DPTX2_LINK_DPIN_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_dpin_div_clk_src.clkr, 1862 [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr, 1863 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr, 1864 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr, 1865 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr, 1866 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr, 1867 [DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK] = 1868 &disp_cc_mdss_dptx2_usb_router_link_intf_clk.clkr, 1869 [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr, 1870 [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr, 1871 [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr, 1872 [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr, 1873 [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr, 1874 [DISP_CC_MDSS_DPTX3_LINK_DPIN_CLK] = &disp_cc_mdss_dptx3_link_dpin_clk.clkr, 1875 [DISP_CC_MDSS_DPTX3_LINK_DPIN_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_dpin_div_clk_src.clkr, 1876 [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr, 1877 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr, 1878 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr, 1879 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, 1880 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, 1881 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, 1882 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr, 1883 [DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr, 1884 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, 1885 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, 1886 [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr, 1887 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, 1888 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, 1889 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, 1890 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, 1891 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr, 1892 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr, 1893 [DISP_CC_MDSS_PCLK2_CLK] = &disp_cc_mdss_pclk2_clk.clkr, 1894 [DISP_CC_MDSS_PCLK2_CLK_SRC] = &disp_cc_mdss_pclk2_clk_src.clkr, 1895 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, 1896 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, 1897 [DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr, 1898 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, 1899 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, 1900 [DISP_CC_OSC_CLK] = &disp_cc_osc_clk.clkr, 1901 [DISP_CC_OSC_CLK_SRC] = &disp_cc_osc_clk_src.clkr, 1902 [DISP_CC_PLL0] = &disp_cc_pll0.clkr, 1903 [DISP_CC_PLL1] = &disp_cc_pll1.clkr, 1904 [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr, 1905 [DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr, 1906 }; 1907 1908 static struct gdsc *disp_cc_glymur_gdscs[] = { 1909 [DISP_CC_MDSS_CORE_GDSC] = &disp_cc_mdss_core_gdsc, 1910 [DISP_CC_MDSS_CORE_INT2_GDSC] = &disp_cc_mdss_core_int2_gdsc, 1911 }; 1912 1913 static const struct qcom_reset_map disp_cc_glymur_resets[] = { 1914 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 }, 1915 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 }, 1916 [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 }, 1917 }; 1918 1919 static struct clk_alpha_pll *disp_cc_glymur_plls[] = { 1920 &disp_cc_pll0, 1921 &disp_cc_pll1, 1922 }; 1923 1924 static const u32 disp_cc_glymur_critical_cbcrs[] = { 1925 0xe07c, /* DISP_CC_SLEEP_CLK */ 1926 0xe05c, /* DISP_CC_XO_CLK */ 1927 }; 1928 1929 static const struct regmap_config disp_cc_glymur_regmap_config = { 1930 .reg_bits = 32, 1931 .reg_stride = 4, 1932 .val_bits = 32, 1933 .max_register = 0x11014, 1934 .fast_io = true, 1935 }; 1936 1937 static const struct qcom_cc_driver_data disp_cc_glymur_driver_data = { 1938 .alpha_plls = disp_cc_glymur_plls, 1939 .num_alpha_plls = ARRAY_SIZE(disp_cc_glymur_plls), 1940 .clk_cbcrs = disp_cc_glymur_critical_cbcrs, 1941 .num_clk_cbcrs = ARRAY_SIZE(disp_cc_glymur_critical_cbcrs), 1942 }; 1943 1944 static const struct qcom_cc_desc disp_cc_glymur_desc = { 1945 .config = &disp_cc_glymur_regmap_config, 1946 .clks = disp_cc_glymur_clocks, 1947 .num_clks = ARRAY_SIZE(disp_cc_glymur_clocks), 1948 .resets = disp_cc_glymur_resets, 1949 .num_resets = ARRAY_SIZE(disp_cc_glymur_resets), 1950 .gdscs = disp_cc_glymur_gdscs, 1951 .num_gdscs = ARRAY_SIZE(disp_cc_glymur_gdscs), 1952 .use_rpm = true, 1953 .driver_data = &disp_cc_glymur_driver_data, 1954 }; 1955 1956 static const struct of_device_id disp_cc_glymur_match_table[] = { 1957 { .compatible = "qcom,glymur-dispcc" }, 1958 { } 1959 }; 1960 MODULE_DEVICE_TABLE(of, disp_cc_glymur_match_table); 1961 1962 static int disp_cc_glymur_probe(struct platform_device *pdev) 1963 { 1964 return qcom_cc_probe(pdev, &disp_cc_glymur_desc); 1965 } 1966 1967 static struct platform_driver disp_cc_glymur_driver = { 1968 .probe = disp_cc_glymur_probe, 1969 .driver = { 1970 .name = "dispcc-glymur", 1971 .of_match_table = disp_cc_glymur_match_table, 1972 }, 1973 }; 1974 1975 module_platform_driver(disp_cc_glymur_driver); 1976 1977 MODULE_DESCRIPTION("QTI DISPCC Glymur Driver"); 1978 MODULE_LICENSE("GPL"); 1979