1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/export.h> 7 #include <linux/module.h> 8 #include <linux/regmap.h> 9 #include <linux/platform_device.h> 10 #include <linux/clk-provider.h> 11 #include <linux/interconnect-clk.h> 12 #include <linux/reset-controller.h> 13 #include <linux/of.h> 14 15 #include "common.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "reset.h" 19 #include "gdsc.h" 20 21 struct qcom_cc { 22 struct qcom_reset_controller reset; 23 struct clk_regmap **rclks; 24 size_t num_rclks; 25 }; 26 27 const 28 struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate) 29 { 30 if (!f) 31 return NULL; 32 33 if (!f->freq) 34 return f; 35 36 for (; f->freq; f++) 37 if (rate <= f->freq) 38 return f; 39 40 /* Default to our fastest rate */ 41 return f - 1; 42 } 43 EXPORT_SYMBOL_GPL(qcom_find_freq); 44 45 const struct freq_multi_tbl *qcom_find_freq_multi(const struct freq_multi_tbl *f, 46 unsigned long rate) 47 { 48 if (!f) 49 return NULL; 50 51 if (!f->freq) 52 return f; 53 54 for (; f->freq; f++) 55 if (rate <= f->freq) 56 return f; 57 58 /* Default to our fastest rate */ 59 return f - 1; 60 } 61 EXPORT_SYMBOL_GPL(qcom_find_freq_multi); 62 63 const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f, 64 unsigned long rate) 65 { 66 const struct freq_tbl *best = NULL; 67 68 for ( ; f->freq; f++) { 69 if (rate >= f->freq) 70 best = f; 71 else 72 break; 73 } 74 75 return best; 76 } 77 EXPORT_SYMBOL_GPL(qcom_find_freq_floor); 78 79 int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src) 80 { 81 int i, num_parents = clk_hw_get_num_parents(hw); 82 83 for (i = 0; i < num_parents; i++) 84 if (src == map[i].src) 85 return i; 86 87 return -ENOENT; 88 } 89 EXPORT_SYMBOL_GPL(qcom_find_src_index); 90 91 int qcom_find_cfg_index(struct clk_hw *hw, const struct parent_map *map, u8 cfg) 92 { 93 int i, num_parents = clk_hw_get_num_parents(hw); 94 95 for (i = 0; i < num_parents; i++) 96 if (cfg == map[i].cfg) 97 return i; 98 99 return -ENOENT; 100 } 101 EXPORT_SYMBOL_GPL(qcom_find_cfg_index); 102 103 struct regmap * 104 qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc) 105 { 106 void __iomem *base; 107 struct device *dev = &pdev->dev; 108 109 base = devm_platform_ioremap_resource(pdev, 0); 110 if (IS_ERR(base)) 111 return ERR_CAST(base); 112 113 return devm_regmap_init_mmio(dev, base, desc->config); 114 } 115 EXPORT_SYMBOL_GPL(qcom_cc_map); 116 117 void 118 qcom_pll_set_fsm_mode(struct regmap *map, u32 reg, u8 bias_count, u8 lock_count) 119 { 120 u32 val; 121 u32 mask; 122 123 /* De-assert reset to FSM */ 124 regmap_update_bits(map, reg, PLL_VOTE_FSM_RESET, 0); 125 126 /* Program bias count and lock count */ 127 val = bias_count << PLL_BIAS_COUNT_SHIFT | 128 lock_count << PLL_LOCK_COUNT_SHIFT; 129 mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT; 130 mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT; 131 regmap_update_bits(map, reg, mask, val); 132 133 /* Enable PLL FSM voting */ 134 regmap_update_bits(map, reg, PLL_VOTE_FSM_ENA, PLL_VOTE_FSM_ENA); 135 } 136 EXPORT_SYMBOL_GPL(qcom_pll_set_fsm_mode); 137 138 static void qcom_cc_gdsc_unregister(void *data) 139 { 140 gdsc_unregister(data); 141 } 142 143 /* 144 * Backwards compatibility with old DTs. Register a pass-through factor 1/1 145 * clock to translate 'path' clk into 'name' clk and register the 'path' 146 * clk as a fixed rate clock if it isn't present. 147 */ 148 static int _qcom_cc_register_board_clk(struct device *dev, const char *path, 149 const char *name, unsigned long rate, 150 bool add_factor) 151 { 152 struct device_node *node = NULL; 153 struct device_node *clocks_node; 154 struct clk_fixed_factor *factor; 155 struct clk_fixed_rate *fixed; 156 struct clk_init_data init_data = { }; 157 int ret; 158 159 clocks_node = of_find_node_by_path("/clocks"); 160 if (clocks_node) { 161 node = of_get_child_by_name(clocks_node, path); 162 of_node_put(clocks_node); 163 } 164 165 if (!node) { 166 fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL); 167 if (!fixed) 168 return -EINVAL; 169 170 fixed->fixed_rate = rate; 171 fixed->hw.init = &init_data; 172 173 init_data.name = path; 174 init_data.ops = &clk_fixed_rate_ops; 175 176 ret = devm_clk_hw_register(dev, &fixed->hw); 177 if (ret) 178 return ret; 179 } 180 of_node_put(node); 181 182 if (add_factor) { 183 factor = devm_kzalloc(dev, sizeof(*factor), GFP_KERNEL); 184 if (!factor) 185 return -EINVAL; 186 187 factor->mult = factor->div = 1; 188 factor->hw.init = &init_data; 189 190 init_data.name = name; 191 init_data.parent_names = &path; 192 init_data.num_parents = 1; 193 init_data.flags = 0; 194 init_data.ops = &clk_fixed_factor_ops; 195 196 ret = devm_clk_hw_register(dev, &factor->hw); 197 if (ret) 198 return ret; 199 } 200 201 return 0; 202 } 203 204 int qcom_cc_register_board_clk(struct device *dev, const char *path, 205 const char *name, unsigned long rate) 206 { 207 bool add_factor = true; 208 209 /* 210 * TODO: The RPM clock driver currently does not support the xo clock. 211 * When xo is added to the RPM clock driver, we should change this 212 * function to skip registration of xo factor clocks. 213 */ 214 215 return _qcom_cc_register_board_clk(dev, path, name, rate, add_factor); 216 } 217 EXPORT_SYMBOL_GPL(qcom_cc_register_board_clk); 218 219 int qcom_cc_register_sleep_clk(struct device *dev) 220 { 221 return _qcom_cc_register_board_clk(dev, "sleep_clk", "sleep_clk_src", 222 32768, true); 223 } 224 EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk); 225 226 /* Drop 'protected-clocks' from the list of clocks to register */ 227 static void qcom_cc_drop_protected(struct device *dev, struct qcom_cc *cc) 228 { 229 struct device_node *np = dev->of_node; 230 struct property *prop; 231 const __be32 *p; 232 u32 i; 233 234 of_property_for_each_u32(np, "protected-clocks", prop, p, i) { 235 if (i >= cc->num_rclks) 236 continue; 237 238 cc->rclks[i] = NULL; 239 } 240 } 241 242 static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec, 243 void *data) 244 { 245 struct qcom_cc *cc = data; 246 unsigned int idx = clkspec->args[0]; 247 248 if (idx >= cc->num_rclks) { 249 pr_err("%s: invalid index %u\n", __func__, idx); 250 return ERR_PTR(-EINVAL); 251 } 252 253 return cc->rclks[idx] ? &cc->rclks[idx]->hw : NULL; 254 } 255 256 static int qcom_cc_icc_register(struct device *dev, 257 const struct qcom_cc_desc *desc) 258 { 259 struct icc_clk_data *icd; 260 struct clk_hw *hws; 261 int i; 262 263 if (!IS_ENABLED(CONFIG_INTERCONNECT_CLK)) 264 return 0; 265 266 if (!desc->icc_hws) 267 return 0; 268 269 icd = devm_kcalloc(dev, desc->num_icc_hws, sizeof(*icd), GFP_KERNEL); 270 if (!icd) 271 return -ENOMEM; 272 273 for (i = 0; i < desc->num_icc_hws; i++) { 274 icd[i].master_id = desc->icc_hws[i].master_id; 275 icd[i].slave_id = desc->icc_hws[i].slave_id; 276 hws = &desc->clks[desc->icc_hws[i].clk_id]->hw; 277 icd[i].clk = devm_clk_hw_get_clk(dev, hws, "icc"); 278 if (!icd[i].clk) 279 return dev_err_probe(dev, -ENOENT, 280 "(%d) clock entry is null\n", i); 281 icd[i].name = clk_hw_get_name(hws); 282 } 283 284 return devm_icc_clk_register(dev, desc->icc_first_node_id, 285 desc->num_icc_hws, icd); 286 } 287 288 int qcom_cc_really_probe(struct device *dev, 289 const struct qcom_cc_desc *desc, struct regmap *regmap) 290 { 291 int i, ret; 292 struct qcom_reset_controller *reset; 293 struct qcom_cc *cc; 294 struct gdsc_desc *scd; 295 size_t num_clks = desc->num_clks; 296 struct clk_regmap **rclks = desc->clks; 297 size_t num_clk_hws = desc->num_clk_hws; 298 struct clk_hw **clk_hws = desc->clk_hws; 299 300 cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL); 301 if (!cc) 302 return -ENOMEM; 303 304 reset = &cc->reset; 305 reset->rcdev.of_node = dev->of_node; 306 reset->rcdev.ops = &qcom_reset_ops; 307 reset->rcdev.owner = dev->driver->owner; 308 reset->rcdev.nr_resets = desc->num_resets; 309 reset->regmap = regmap; 310 reset->reset_map = desc->resets; 311 312 ret = devm_reset_controller_register(dev, &reset->rcdev); 313 if (ret) 314 return ret; 315 316 if (desc->gdscs && desc->num_gdscs) { 317 scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL); 318 if (!scd) 319 return -ENOMEM; 320 scd->dev = dev; 321 scd->scs = desc->gdscs; 322 scd->num = desc->num_gdscs; 323 ret = gdsc_register(scd, &reset->rcdev, regmap); 324 if (ret) 325 return ret; 326 ret = devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister, 327 scd); 328 if (ret) 329 return ret; 330 } 331 332 cc->rclks = rclks; 333 cc->num_rclks = num_clks; 334 335 qcom_cc_drop_protected(dev, cc); 336 337 for (i = 0; i < num_clk_hws; i++) { 338 ret = devm_clk_hw_register(dev, clk_hws[i]); 339 if (ret) 340 return ret; 341 } 342 343 for (i = 0; i < num_clks; i++) { 344 if (!rclks[i]) 345 continue; 346 347 ret = devm_clk_register_regmap(dev, rclks[i]); 348 if (ret) 349 return ret; 350 } 351 352 ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc); 353 if (ret) 354 return ret; 355 356 return qcom_cc_icc_register(dev, desc); 357 } 358 EXPORT_SYMBOL_GPL(qcom_cc_really_probe); 359 360 int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc) 361 { 362 struct regmap *regmap; 363 364 regmap = qcom_cc_map(pdev, desc); 365 if (IS_ERR(regmap)) 366 return PTR_ERR(regmap); 367 368 return qcom_cc_really_probe(&pdev->dev, desc, regmap); 369 } 370 EXPORT_SYMBOL_GPL(qcom_cc_probe); 371 372 int qcom_cc_probe_by_index(struct platform_device *pdev, int index, 373 const struct qcom_cc_desc *desc) 374 { 375 struct regmap *regmap; 376 void __iomem *base; 377 378 base = devm_platform_ioremap_resource(pdev, index); 379 if (IS_ERR(base)) 380 return -ENOMEM; 381 382 regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config); 383 if (IS_ERR(regmap)) 384 return PTR_ERR(regmap); 385 386 return qcom_cc_really_probe(&pdev->dev, desc, regmap); 387 } 388 EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index); 389 390 MODULE_LICENSE("GPL v2"); 391 MODULE_DESCRIPTION("QTI Common Clock module"); 392