xref: /linux/drivers/clk/qcom/common.c (revision 9a95c5bfbf02a0a7f5983280fe284a0ff0836c34)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/export.h>
7 #include <linux/module.h>
8 #include <linux/regmap.h>
9 #include <linux/platform_device.h>
10 #include <linux/clk-provider.h>
11 #include <linux/reset-controller.h>
12 #include <linux/of.h>
13 
14 #include "common.h"
15 #include "clk-rcg.h"
16 #include "clk-regmap.h"
17 #include "reset.h"
18 #include "gdsc.h"
19 
20 struct qcom_cc {
21 	struct qcom_reset_controller reset;
22 	struct clk_regmap **rclks;
23 	size_t num_rclks;
24 };
25 
26 const
27 struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate)
28 {
29 	if (!f)
30 		return NULL;
31 
32 	if (!f->freq)
33 		return f;
34 
35 	for (; f->freq; f++)
36 		if (rate <= f->freq)
37 			return f;
38 
39 	/* Default to our fastest rate */
40 	return f - 1;
41 }
42 EXPORT_SYMBOL_GPL(qcom_find_freq);
43 
44 const struct freq_multi_tbl *qcom_find_freq_multi(const struct freq_multi_tbl *f,
45 						  unsigned long rate)
46 {
47 	if (!f)
48 		return NULL;
49 
50 	if (!f->freq)
51 		return f;
52 
53 	for (; f->freq; f++)
54 		if (rate <= f->freq)
55 			return f;
56 
57 	/* Default to our fastest rate */
58 	return f - 1;
59 }
60 EXPORT_SYMBOL_GPL(qcom_find_freq_multi);
61 
62 const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
63 					    unsigned long rate)
64 {
65 	const struct freq_tbl *best = NULL;
66 
67 	for ( ; f->freq; f++) {
68 		if (rate >= f->freq)
69 			best = f;
70 		else
71 			break;
72 	}
73 
74 	return best;
75 }
76 EXPORT_SYMBOL_GPL(qcom_find_freq_floor);
77 
78 int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src)
79 {
80 	int i, num_parents = clk_hw_get_num_parents(hw);
81 
82 	for (i = 0; i < num_parents; i++)
83 		if (src == map[i].src)
84 			return i;
85 
86 	return -ENOENT;
87 }
88 EXPORT_SYMBOL_GPL(qcom_find_src_index);
89 
90 int qcom_find_cfg_index(struct clk_hw *hw, const struct parent_map *map, u8 cfg)
91 {
92 	int i, num_parents = clk_hw_get_num_parents(hw);
93 
94 	for (i = 0; i < num_parents; i++)
95 		if (cfg == map[i].cfg)
96 			return i;
97 
98 	return -ENOENT;
99 }
100 EXPORT_SYMBOL_GPL(qcom_find_cfg_index);
101 
102 struct regmap *
103 qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc)
104 {
105 	void __iomem *base;
106 	struct device *dev = &pdev->dev;
107 
108 	base = devm_platform_ioremap_resource(pdev, 0);
109 	if (IS_ERR(base))
110 		return ERR_CAST(base);
111 
112 	return devm_regmap_init_mmio(dev, base, desc->config);
113 }
114 EXPORT_SYMBOL_GPL(qcom_cc_map);
115 
116 void
117 qcom_pll_set_fsm_mode(struct regmap *map, u32 reg, u8 bias_count, u8 lock_count)
118 {
119 	u32 val;
120 	u32 mask;
121 
122 	/* De-assert reset to FSM */
123 	regmap_update_bits(map, reg, PLL_VOTE_FSM_RESET, 0);
124 
125 	/* Program bias count and lock count */
126 	val = bias_count << PLL_BIAS_COUNT_SHIFT |
127 		lock_count << PLL_LOCK_COUNT_SHIFT;
128 	mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
129 	mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
130 	regmap_update_bits(map, reg, mask, val);
131 
132 	/* Enable PLL FSM voting */
133 	regmap_update_bits(map, reg, PLL_VOTE_FSM_ENA, PLL_VOTE_FSM_ENA);
134 }
135 EXPORT_SYMBOL_GPL(qcom_pll_set_fsm_mode);
136 
137 static void qcom_cc_gdsc_unregister(void *data)
138 {
139 	gdsc_unregister(data);
140 }
141 
142 /*
143  * Backwards compatibility with old DTs. Register a pass-through factor 1/1
144  * clock to translate 'path' clk into 'name' clk and register the 'path'
145  * clk as a fixed rate clock if it isn't present.
146  */
147 static int _qcom_cc_register_board_clk(struct device *dev, const char *path,
148 				       const char *name, unsigned long rate,
149 				       bool add_factor)
150 {
151 	struct device_node *node = NULL;
152 	struct device_node *clocks_node;
153 	struct clk_fixed_factor *factor;
154 	struct clk_fixed_rate *fixed;
155 	struct clk_init_data init_data = { };
156 	int ret;
157 
158 	clocks_node = of_find_node_by_path("/clocks");
159 	if (clocks_node) {
160 		node = of_get_child_by_name(clocks_node, path);
161 		of_node_put(clocks_node);
162 	}
163 
164 	if (!node) {
165 		fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
166 		if (!fixed)
167 			return -EINVAL;
168 
169 		fixed->fixed_rate = rate;
170 		fixed->hw.init = &init_data;
171 
172 		init_data.name = path;
173 		init_data.ops = &clk_fixed_rate_ops;
174 
175 		ret = devm_clk_hw_register(dev, &fixed->hw);
176 		if (ret)
177 			return ret;
178 	}
179 	of_node_put(node);
180 
181 	if (add_factor) {
182 		factor = devm_kzalloc(dev, sizeof(*factor), GFP_KERNEL);
183 		if (!factor)
184 			return -EINVAL;
185 
186 		factor->mult = factor->div = 1;
187 		factor->hw.init = &init_data;
188 
189 		init_data.name = name;
190 		init_data.parent_names = &path;
191 		init_data.num_parents = 1;
192 		init_data.flags = 0;
193 		init_data.ops = &clk_fixed_factor_ops;
194 
195 		ret = devm_clk_hw_register(dev, &factor->hw);
196 		if (ret)
197 			return ret;
198 	}
199 
200 	return 0;
201 }
202 
203 int qcom_cc_register_board_clk(struct device *dev, const char *path,
204 			       const char *name, unsigned long rate)
205 {
206 	bool add_factor = true;
207 
208 	/*
209 	 * TODO: The RPM clock driver currently does not support the xo clock.
210 	 * When xo is added to the RPM clock driver, we should change this
211 	 * function to skip registration of xo factor clocks.
212 	 */
213 
214 	return _qcom_cc_register_board_clk(dev, path, name, rate, add_factor);
215 }
216 EXPORT_SYMBOL_GPL(qcom_cc_register_board_clk);
217 
218 int qcom_cc_register_sleep_clk(struct device *dev)
219 {
220 	return _qcom_cc_register_board_clk(dev, "sleep_clk", "sleep_clk_src",
221 					   32768, true);
222 }
223 EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk);
224 
225 /* Drop 'protected-clocks' from the list of clocks to register */
226 static void qcom_cc_drop_protected(struct device *dev, struct qcom_cc *cc)
227 {
228 	struct device_node *np = dev->of_node;
229 	struct property *prop;
230 	const __be32 *p;
231 	u32 i;
232 
233 	of_property_for_each_u32(np, "protected-clocks", prop, p, i) {
234 		if (i >= cc->num_rclks)
235 			continue;
236 
237 		cc->rclks[i] = NULL;
238 	}
239 }
240 
241 static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec,
242 					 void *data)
243 {
244 	struct qcom_cc *cc = data;
245 	unsigned int idx = clkspec->args[0];
246 
247 	if (idx >= cc->num_rclks) {
248 		pr_err("%s: invalid index %u\n", __func__, idx);
249 		return ERR_PTR(-EINVAL);
250 	}
251 
252 	return cc->rclks[idx] ? &cc->rclks[idx]->hw : NULL;
253 }
254 
255 int qcom_cc_really_probe(struct platform_device *pdev,
256 			 const struct qcom_cc_desc *desc, struct regmap *regmap)
257 {
258 	int i, ret;
259 	struct device *dev = &pdev->dev;
260 	struct qcom_reset_controller *reset;
261 	struct qcom_cc *cc;
262 	struct gdsc_desc *scd;
263 	size_t num_clks = desc->num_clks;
264 	struct clk_regmap **rclks = desc->clks;
265 	size_t num_clk_hws = desc->num_clk_hws;
266 	struct clk_hw **clk_hws = desc->clk_hws;
267 
268 	cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
269 	if (!cc)
270 		return -ENOMEM;
271 
272 	reset = &cc->reset;
273 	reset->rcdev.of_node = dev->of_node;
274 	reset->rcdev.ops = &qcom_reset_ops;
275 	reset->rcdev.owner = dev->driver->owner;
276 	reset->rcdev.nr_resets = desc->num_resets;
277 	reset->regmap = regmap;
278 	reset->reset_map = desc->resets;
279 
280 	ret = devm_reset_controller_register(dev, &reset->rcdev);
281 	if (ret)
282 		return ret;
283 
284 	if (desc->gdscs && desc->num_gdscs) {
285 		scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL);
286 		if (!scd)
287 			return -ENOMEM;
288 		scd->dev = dev;
289 		scd->scs = desc->gdscs;
290 		scd->num = desc->num_gdscs;
291 		ret = gdsc_register(scd, &reset->rcdev, regmap);
292 		if (ret)
293 			return ret;
294 		ret = devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister,
295 					       scd);
296 		if (ret)
297 			return ret;
298 	}
299 
300 	cc->rclks = rclks;
301 	cc->num_rclks = num_clks;
302 
303 	qcom_cc_drop_protected(dev, cc);
304 
305 	for (i = 0; i < num_clk_hws; i++) {
306 		ret = devm_clk_hw_register(dev, clk_hws[i]);
307 		if (ret)
308 			return ret;
309 	}
310 
311 	for (i = 0; i < num_clks; i++) {
312 		if (!rclks[i])
313 			continue;
314 
315 		ret = devm_clk_register_regmap(dev, rclks[i]);
316 		if (ret)
317 			return ret;
318 	}
319 
320 	ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc);
321 	if (ret)
322 		return ret;
323 
324 	return 0;
325 }
326 EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
327 
328 int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
329 {
330 	struct regmap *regmap;
331 
332 	regmap = qcom_cc_map(pdev, desc);
333 	if (IS_ERR(regmap))
334 		return PTR_ERR(regmap);
335 
336 	return qcom_cc_really_probe(pdev, desc, regmap);
337 }
338 EXPORT_SYMBOL_GPL(qcom_cc_probe);
339 
340 int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
341 			   const struct qcom_cc_desc *desc)
342 {
343 	struct regmap *regmap;
344 	void __iomem *base;
345 
346 	base = devm_platform_ioremap_resource(pdev, index);
347 	if (IS_ERR(base))
348 		return -ENOMEM;
349 
350 	regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config);
351 	if (IS_ERR(regmap))
352 		return PTR_ERR(regmap);
353 
354 	return qcom_cc_really_probe(pdev, desc, regmap);
355 }
356 EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index);
357 
358 MODULE_LICENSE("GPL v2");
359