1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2017, The Linux Foundation. All rights reserved. 3 */ 4 5 #include <linux/bitops.h> 6 #include <linux/cleanup.h> 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/delay.h> 10 #include <linux/err.h> 11 #include <linux/log2.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/regmap.h> 16 #include <linux/slab.h> 17 #include <linux/types.h> 18 19 #define REG_DIV_CTL1 0x43 20 #define DIV_CTL1_DIV_FACTOR_MASK GENMASK(2, 0) 21 22 #define REG_EN_CTL 0x46 23 #define REG_EN_MASK BIT(7) 24 25 struct clkdiv { 26 struct regmap *regmap; 27 u16 base; 28 spinlock_t lock; 29 30 struct clk_hw hw; 31 unsigned int cxo_period_ns; 32 }; 33 34 static inline struct clkdiv *to_clkdiv(struct clk_hw *hw) 35 { 36 return container_of(hw, struct clkdiv, hw); 37 } 38 39 static inline unsigned int div_factor_to_div(unsigned int div_factor) 40 { 41 if (!div_factor) 42 div_factor = 1; 43 44 return 1 << (div_factor - 1); 45 } 46 47 static inline unsigned int div_to_div_factor(unsigned int div) 48 { 49 return min(ilog2(div) + 1, 7); 50 } 51 52 static bool is_spmi_pmic_clkdiv_enabled(struct clkdiv *clkdiv) 53 { 54 unsigned int val = 0; 55 56 regmap_read(clkdiv->regmap, clkdiv->base + REG_EN_CTL, &val); 57 58 return val & REG_EN_MASK; 59 } 60 61 static int 62 __spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable, 63 unsigned int div_factor) 64 { 65 int ret; 66 unsigned int ns = clkdiv->cxo_period_ns; 67 unsigned int div = div_factor_to_div(div_factor); 68 69 ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_EN_CTL, 70 REG_EN_MASK, enable ? REG_EN_MASK : 0); 71 if (ret) 72 return ret; 73 74 if (enable) 75 ndelay((2 + 3 * div) * ns); 76 else 77 ndelay(3 * div * ns); 78 79 return 0; 80 } 81 82 static int spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable) 83 { 84 unsigned int div_factor; 85 86 regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor); 87 div_factor &= DIV_CTL1_DIV_FACTOR_MASK; 88 89 return __spmi_pmic_clkdiv_set_enable_state(clkdiv, enable, div_factor); 90 } 91 92 static int clk_spmi_pmic_div_enable(struct clk_hw *hw) 93 { 94 struct clkdiv *clkdiv = to_clkdiv(hw); 95 unsigned long flags; 96 int ret; 97 98 spin_lock_irqsave(&clkdiv->lock, flags); 99 ret = spmi_pmic_clkdiv_set_enable_state(clkdiv, true); 100 spin_unlock_irqrestore(&clkdiv->lock, flags); 101 102 return ret; 103 } 104 105 static void clk_spmi_pmic_div_disable(struct clk_hw *hw) 106 { 107 struct clkdiv *clkdiv = to_clkdiv(hw); 108 unsigned long flags; 109 110 spin_lock_irqsave(&clkdiv->lock, flags); 111 spmi_pmic_clkdiv_set_enable_state(clkdiv, false); 112 spin_unlock_irqrestore(&clkdiv->lock, flags); 113 } 114 115 static long clk_spmi_pmic_div_round_rate(struct clk_hw *hw, unsigned long rate, 116 unsigned long *parent_rate) 117 { 118 unsigned int div, div_factor; 119 120 div = DIV_ROUND_UP(*parent_rate, rate); 121 div_factor = div_to_div_factor(div); 122 div = div_factor_to_div(div_factor); 123 124 return *parent_rate / div; 125 } 126 127 static unsigned long 128 clk_spmi_pmic_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 129 { 130 struct clkdiv *clkdiv = to_clkdiv(hw); 131 unsigned int div_factor; 132 133 regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor); 134 div_factor &= DIV_CTL1_DIV_FACTOR_MASK; 135 136 return parent_rate / div_factor_to_div(div_factor); 137 } 138 139 static int clk_spmi_pmic_div_set_rate(struct clk_hw *hw, unsigned long rate, 140 unsigned long parent_rate) 141 { 142 struct clkdiv *clkdiv = to_clkdiv(hw); 143 unsigned int div_factor = div_to_div_factor(parent_rate / rate); 144 bool enabled; 145 int ret; 146 147 guard(spinlock_irqsave)(&clkdiv->lock); 148 149 enabled = is_spmi_pmic_clkdiv_enabled(clkdiv); 150 if (enabled) { 151 ret = spmi_pmic_clkdiv_set_enable_state(clkdiv, false); 152 if (ret) 153 return ret; 154 } 155 156 ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, 157 DIV_CTL1_DIV_FACTOR_MASK, div_factor); 158 if (ret) 159 return ret; 160 161 if (enabled) 162 ret = __spmi_pmic_clkdiv_set_enable_state(clkdiv, true, 163 div_factor); 164 return ret; 165 } 166 167 static const struct clk_ops clk_spmi_pmic_div_ops = { 168 .enable = clk_spmi_pmic_div_enable, 169 .disable = clk_spmi_pmic_div_disable, 170 .set_rate = clk_spmi_pmic_div_set_rate, 171 .recalc_rate = clk_spmi_pmic_div_recalc_rate, 172 .round_rate = clk_spmi_pmic_div_round_rate, 173 }; 174 175 struct spmi_pmic_div_clk_cc { 176 int nclks; 177 struct clkdiv clks[] __counted_by(nclks); 178 }; 179 180 static struct clk_hw * 181 spmi_pmic_div_clk_hw_get(struct of_phandle_args *clkspec, void *data) 182 { 183 struct spmi_pmic_div_clk_cc *cc = data; 184 int idx = clkspec->args[0] - 1; /* Start at 1 instead of 0 */ 185 186 if (idx < 0 || idx >= cc->nclks) { 187 pr_err("%s: index value %u is invalid; allowed range [1, %d]\n", 188 __func__, clkspec->args[0], cc->nclks); 189 return ERR_PTR(-EINVAL); 190 } 191 192 return &cc->clks[idx].hw; 193 } 194 195 static int spmi_pmic_clkdiv_probe(struct platform_device *pdev) 196 { 197 struct spmi_pmic_div_clk_cc *cc; 198 struct clk_init_data init = {}; 199 struct clkdiv *clkdiv; 200 struct clk *cxo; 201 struct regmap *regmap; 202 struct device *dev = &pdev->dev; 203 struct device_node *of_node = dev->of_node; 204 struct clk_parent_data parent_data = { .index = 0, }; 205 int nclks, i, ret, cxo_hz; 206 char name[20]; 207 u32 start; 208 209 ret = of_property_read_u32(of_node, "reg", &start); 210 if (ret < 0) { 211 dev_err(dev, "reg property reading failed\n"); 212 return ret; 213 } 214 215 regmap = dev_get_regmap(dev->parent, NULL); 216 if (!regmap) { 217 dev_err(dev, "Couldn't get parent's regmap\n"); 218 return -EINVAL; 219 } 220 221 ret = of_property_read_u32(of_node, "qcom,num-clkdivs", &nclks); 222 if (ret < 0) { 223 dev_err(dev, "qcom,num-clkdivs property reading failed, ret=%d\n", 224 ret); 225 return ret; 226 } 227 228 if (!nclks) 229 return -EINVAL; 230 231 cc = devm_kzalloc(dev, struct_size(cc, clks, nclks), GFP_KERNEL); 232 if (!cc) 233 return -ENOMEM; 234 cc->nclks = nclks; 235 236 cxo = clk_get(dev, "xo"); 237 if (IS_ERR(cxo)) { 238 ret = PTR_ERR(cxo); 239 if (ret != -EPROBE_DEFER) 240 dev_err(dev, "failed to get xo clock\n"); 241 return ret; 242 } 243 cxo_hz = clk_get_rate(cxo); 244 clk_put(cxo); 245 246 init.name = name; 247 init.parent_data = &parent_data; 248 init.num_parents = 1; 249 init.ops = &clk_spmi_pmic_div_ops; 250 251 for (i = 0, clkdiv = cc->clks; i < nclks; i++) { 252 snprintf(name, sizeof(name), "div_clk%d", i + 1); 253 254 spin_lock_init(&clkdiv[i].lock); 255 clkdiv[i].base = start + i * 0x100; 256 clkdiv[i].regmap = regmap; 257 clkdiv[i].cxo_period_ns = NSEC_PER_SEC / cxo_hz; 258 clkdiv[i].hw.init = &init; 259 260 ret = devm_clk_hw_register(dev, &clkdiv[i].hw); 261 if (ret) 262 return ret; 263 } 264 265 return devm_of_clk_add_hw_provider(dev, spmi_pmic_div_clk_hw_get, cc); 266 } 267 268 static const struct of_device_id spmi_pmic_clkdiv_match_table[] = { 269 { .compatible = "qcom,spmi-clkdiv" }, 270 { /* sentinel */ } 271 }; 272 MODULE_DEVICE_TABLE(of, spmi_pmic_clkdiv_match_table); 273 274 static struct platform_driver spmi_pmic_clkdiv_driver = { 275 .driver = { 276 .name = "qcom,spmi-pmic-clkdiv", 277 .of_match_table = spmi_pmic_clkdiv_match_table, 278 }, 279 .probe = spmi_pmic_clkdiv_probe, 280 }; 281 module_platform_driver(spmi_pmic_clkdiv_driver); 282 283 MODULE_DESCRIPTION("QCOM SPMI PMIC clkdiv driver"); 284 MODULE_LICENSE("GPL v2"); 285