1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016, Linaro Limited 4 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/err.h> 9 #include <linux/export.h> 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/platform_device.h> 17 #include <linux/soc/qcom/smd-rpm.h> 18 19 #include <dt-bindings/clock/qcom,rpmcc.h> 20 21 #define QCOM_RPM_KEY_SOFTWARE_ENABLE 0x6e657773 22 #define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY 0x62636370 23 #define QCOM_RPM_SMD_KEY_RATE 0x007a484b 24 #define QCOM_RPM_SMD_KEY_ENABLE 0x62616e45 25 #define QCOM_RPM_SMD_KEY_STATE 0x54415453 26 #define QCOM_RPM_SCALING_ENABLE_ID 0x2 27 28 #define __DEFINE_CLK_SMD_RPM_PREFIX(_prefix, _name, _active, \ 29 type, r_id, key) \ 30 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \ 31 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_name = { \ 32 .rpm_res_type = (type), \ 33 .rpm_clk_id = (r_id), \ 34 .rpm_key = (key), \ 35 .peer = &clk_smd_rpm_##_prefix##_active, \ 36 .rate = INT_MAX, \ 37 .hw.init = &(struct clk_init_data){ \ 38 .ops = &clk_smd_rpm_ops, \ 39 .name = #_name, \ 40 .parent_data = &(const struct clk_parent_data){ \ 41 .fw_name = "xo", \ 42 .name = "xo_board", \ 43 }, \ 44 .num_parents = 1, \ 45 }, \ 46 }; \ 47 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active = { \ 48 .rpm_res_type = (type), \ 49 .rpm_clk_id = (r_id), \ 50 .active_only = true, \ 51 .rpm_key = (key), \ 52 .peer = &clk_smd_rpm_##_prefix##_name, \ 53 .rate = INT_MAX, \ 54 .hw.init = &(struct clk_init_data){ \ 55 .ops = &clk_smd_rpm_ops, \ 56 .name = #_active, \ 57 .parent_data = &(const struct clk_parent_data){ \ 58 .fw_name = "xo", \ 59 .name = "xo_board", \ 60 }, \ 61 .num_parents = 1, \ 62 }, \ 63 } 64 65 #define __DEFINE_CLK_SMD_RPM(_name, _active, type, r_id, key) \ 66 __DEFINE_CLK_SMD_RPM_PREFIX(/* empty */, _name, _active, \ 67 type, r_id, key) 68 69 #define __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, _name, _active,\ 70 type, r_id, r, key, ao_flags) \ 71 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \ 72 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_name = { \ 73 .rpm_res_type = (type), \ 74 .rpm_clk_id = (r_id), \ 75 .rpm_key = (key), \ 76 .branch = true, \ 77 .peer = &clk_smd_rpm_##_prefix##_active, \ 78 .rate = (r), \ 79 .hw.init = &(struct clk_init_data){ \ 80 .ops = &clk_smd_rpm_branch_ops, \ 81 .name = #_name, \ 82 .parent_data = &(const struct clk_parent_data){ \ 83 .fw_name = "xo", \ 84 .name = "xo_board", \ 85 }, \ 86 .num_parents = 1, \ 87 }, \ 88 }; \ 89 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active = { \ 90 .rpm_res_type = (type), \ 91 .rpm_clk_id = (r_id), \ 92 .active_only = true, \ 93 .rpm_key = (key), \ 94 .branch = true, \ 95 .peer = &clk_smd_rpm_##_prefix##_name, \ 96 .rate = (r), \ 97 .hw.init = &(struct clk_init_data){ \ 98 .ops = &clk_smd_rpm_branch_ops, \ 99 .name = #_active, \ 100 .parent_data = &(const struct clk_parent_data){ \ 101 .fw_name = "xo", \ 102 .name = "xo_board", \ 103 }, \ 104 .num_parents = 1, \ 105 .flags = (ao_flags), \ 106 }, \ 107 } 108 109 #define __DEFINE_CLK_SMD_RPM_BRANCH(_name, _active, type, r_id, r, key) \ 110 __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(/* empty */, \ 111 _name, _active, type, r_id, r, key, 0) 112 113 #define DEFINE_CLK_SMD_RPM(_name, type, r_id) \ 114 __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \ 115 type, r_id, QCOM_RPM_SMD_KEY_RATE) 116 117 #define DEFINE_CLK_SMD_RPM_BUS(_name, r_id) \ 118 __DEFINE_CLK_SMD_RPM_PREFIX(bus_##r_id##_, \ 119 _name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \ 120 QCOM_RPM_SMD_KEY_RATE) 121 122 #define DEFINE_CLK_SMD_RPM_CLK_SRC(_name, type, r_id) \ 123 __DEFINE_CLK_SMD_RPM( \ 124 _name##_clk_src, _name##_a_clk_src, \ 125 type, r_id, QCOM_RPM_SMD_KEY_RATE) 126 127 #define DEFINE_CLK_SMD_RPM_BRANCH(_name, type, r_id, r) \ 128 __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \ 129 _name##_clk, _name##_a_clk, \ 130 type, r_id, r, QCOM_RPM_SMD_KEY_ENABLE, 0) 131 132 #define DEFINE_CLK_SMD_RPM_BRANCH_A(_name, type, r_id, r, ao_flags) \ 133 __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \ 134 _name, _name##_a, type, \ 135 r_id, r, QCOM_RPM_SMD_KEY_ENABLE, ao_flags) 136 137 #define DEFINE_CLK_SMD_RPM_QDSS(_name, type, r_id) \ 138 __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \ 139 type, r_id, QCOM_RPM_SMD_KEY_STATE) 140 141 #define DEFINE_CLK_SMD_RPM_XO_BUFFER(_name, r_id, r) \ 142 __DEFINE_CLK_SMD_RPM_BRANCH(_name, _name##_a, \ 143 QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ 144 QCOM_RPM_KEY_SOFTWARE_ENABLE) 145 146 #define DEFINE_CLK_SMD_RPM_XO_BUFFER_PREFIX(_prefix, _name, r_id, r) \ 147 __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, \ 148 _name, _name##_a, \ 149 QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ 150 QCOM_RPM_KEY_SOFTWARE_ENABLE, 0) 151 152 #define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_name, r_id, r) \ 153 DEFINE_CLK_SMD_RPM_XO_BUFFER(_name, r_id, r); \ 154 __DEFINE_CLK_SMD_RPM_BRANCH(_name##_pin, _name##_a##_pin, \ 155 QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ 156 QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY) 157 158 #define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw) 159 160 static struct qcom_smd_rpm *rpmcc_smd_rpm; 161 162 struct clk_smd_rpm { 163 const int rpm_res_type; 164 const int rpm_key; 165 const int rpm_clk_id; 166 const bool active_only; 167 bool enabled; 168 bool branch; 169 struct clk_smd_rpm *peer; 170 struct clk_hw hw; 171 unsigned long rate; 172 }; 173 174 struct clk_smd_rpm_req { 175 __le32 key; 176 __le32 nbytes; 177 __le32 value; 178 }; 179 180 struct rpm_smd_clk_desc { 181 struct clk_smd_rpm **clks; 182 size_t num_clks; 183 bool scaling_before_handover; 184 }; 185 186 static DEFINE_MUTEX(rpm_smd_clk_lock); 187 188 static int clk_smd_rpm_handoff(struct clk_smd_rpm *r) 189 { 190 int ret; 191 struct clk_smd_rpm_req req = { 192 .key = cpu_to_le32(r->rpm_key), 193 .nbytes = cpu_to_le32(sizeof(u32)), 194 .value = cpu_to_le32(r->branch ? 1 : INT_MAX), 195 }; 196 197 ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE, 198 r->rpm_res_type, r->rpm_clk_id, &req, 199 sizeof(req)); 200 if (ret) 201 return ret; 202 ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE, 203 r->rpm_res_type, r->rpm_clk_id, &req, 204 sizeof(req)); 205 if (ret) 206 return ret; 207 208 return 0; 209 } 210 211 static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r, 212 unsigned long rate) 213 { 214 struct clk_smd_rpm_req req = { 215 .key = cpu_to_le32(r->rpm_key), 216 .nbytes = cpu_to_le32(sizeof(u32)), 217 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */ 218 }; 219 220 return qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE, 221 r->rpm_res_type, r->rpm_clk_id, &req, 222 sizeof(req)); 223 } 224 225 static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r, 226 unsigned long rate) 227 { 228 struct clk_smd_rpm_req req = { 229 .key = cpu_to_le32(r->rpm_key), 230 .nbytes = cpu_to_le32(sizeof(u32)), 231 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */ 232 }; 233 234 return qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE, 235 r->rpm_res_type, r->rpm_clk_id, &req, 236 sizeof(req)); 237 } 238 239 static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate, 240 unsigned long *active, unsigned long *sleep) 241 { 242 *active = rate; 243 244 /* 245 * Active-only clocks don't care what the rate is during sleep. So, 246 * they vote for zero. 247 */ 248 if (r->active_only) 249 *sleep = 0; 250 else 251 *sleep = *active; 252 } 253 254 static int clk_smd_rpm_prepare(struct clk_hw *hw) 255 { 256 struct clk_smd_rpm *r = to_clk_smd_rpm(hw); 257 struct clk_smd_rpm *peer = r->peer; 258 unsigned long this_rate = 0, this_sleep_rate = 0; 259 unsigned long peer_rate = 0, peer_sleep_rate = 0; 260 unsigned long active_rate, sleep_rate; 261 int ret = 0; 262 263 mutex_lock(&rpm_smd_clk_lock); 264 265 /* Don't send requests to the RPM if the rate has not been set. */ 266 if (!r->rate) 267 goto out; 268 269 to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate); 270 271 /* Take peer clock's rate into account only if it's enabled. */ 272 if (peer->enabled) 273 to_active_sleep(peer, peer->rate, 274 &peer_rate, &peer_sleep_rate); 275 276 active_rate = max(this_rate, peer_rate); 277 278 if (r->branch) 279 active_rate = !!active_rate; 280 281 ret = clk_smd_rpm_set_rate_active(r, active_rate); 282 if (ret) 283 goto out; 284 285 sleep_rate = max(this_sleep_rate, peer_sleep_rate); 286 if (r->branch) 287 sleep_rate = !!sleep_rate; 288 289 ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate); 290 if (ret) 291 /* Undo the active set vote and restore it */ 292 ret = clk_smd_rpm_set_rate_active(r, peer_rate); 293 294 out: 295 if (!ret) 296 r->enabled = true; 297 298 mutex_unlock(&rpm_smd_clk_lock); 299 300 return ret; 301 } 302 303 static void clk_smd_rpm_unprepare(struct clk_hw *hw) 304 { 305 struct clk_smd_rpm *r = to_clk_smd_rpm(hw); 306 struct clk_smd_rpm *peer = r->peer; 307 unsigned long peer_rate = 0, peer_sleep_rate = 0; 308 unsigned long active_rate, sleep_rate; 309 int ret; 310 311 mutex_lock(&rpm_smd_clk_lock); 312 313 if (!r->rate) 314 goto out; 315 316 /* Take peer clock's rate into account only if it's enabled. */ 317 if (peer->enabled) 318 to_active_sleep(peer, peer->rate, &peer_rate, 319 &peer_sleep_rate); 320 321 active_rate = r->branch ? !!peer_rate : peer_rate; 322 ret = clk_smd_rpm_set_rate_active(r, active_rate); 323 if (ret) 324 goto out; 325 326 sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate; 327 ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate); 328 if (ret) 329 goto out; 330 331 r->enabled = false; 332 333 out: 334 mutex_unlock(&rpm_smd_clk_lock); 335 } 336 337 static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate, 338 unsigned long parent_rate) 339 { 340 struct clk_smd_rpm *r = to_clk_smd_rpm(hw); 341 struct clk_smd_rpm *peer = r->peer; 342 unsigned long active_rate, sleep_rate; 343 unsigned long this_rate = 0, this_sleep_rate = 0; 344 unsigned long peer_rate = 0, peer_sleep_rate = 0; 345 int ret = 0; 346 347 mutex_lock(&rpm_smd_clk_lock); 348 349 if (!r->enabled) 350 goto out; 351 352 to_active_sleep(r, rate, &this_rate, &this_sleep_rate); 353 354 /* Take peer clock's rate into account only if it's enabled. */ 355 if (peer->enabled) 356 to_active_sleep(peer, peer->rate, 357 &peer_rate, &peer_sleep_rate); 358 359 active_rate = max(this_rate, peer_rate); 360 ret = clk_smd_rpm_set_rate_active(r, active_rate); 361 if (ret) 362 goto out; 363 364 sleep_rate = max(this_sleep_rate, peer_sleep_rate); 365 ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate); 366 if (ret) 367 goto out; 368 369 r->rate = rate; 370 371 out: 372 mutex_unlock(&rpm_smd_clk_lock); 373 374 return ret; 375 } 376 377 static long clk_smd_rpm_round_rate(struct clk_hw *hw, unsigned long rate, 378 unsigned long *parent_rate) 379 { 380 /* 381 * RPM handles rate rounding and we don't have a way to 382 * know what the rate will be, so just return whatever 383 * rate is requested. 384 */ 385 return rate; 386 } 387 388 static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw, 389 unsigned long parent_rate) 390 { 391 struct clk_smd_rpm *r = to_clk_smd_rpm(hw); 392 393 /* 394 * RPM handles rate rounding and we don't have a way to 395 * know what the rate will be, so just return whatever 396 * rate was set. 397 */ 398 return r->rate; 399 } 400 401 static int clk_smd_rpm_enable_scaling(void) 402 { 403 int ret; 404 struct clk_smd_rpm_req req = { 405 .key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE), 406 .nbytes = cpu_to_le32(sizeof(u32)), 407 .value = cpu_to_le32(1), 408 }; 409 410 ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE, 411 QCOM_SMD_RPM_MISC_CLK, 412 QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req)); 413 if (ret) { 414 pr_err("RPM clock scaling (sleep set) not enabled!\n"); 415 return ret; 416 } 417 418 ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE, 419 QCOM_SMD_RPM_MISC_CLK, 420 QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req)); 421 if (ret) { 422 pr_err("RPM clock scaling (active set) not enabled!\n"); 423 return ret; 424 } 425 426 pr_debug("%s: RPM clock scaling is enabled\n", __func__); 427 return 0; 428 } 429 430 static const struct clk_ops clk_smd_rpm_ops = { 431 .prepare = clk_smd_rpm_prepare, 432 .unprepare = clk_smd_rpm_unprepare, 433 .set_rate = clk_smd_rpm_set_rate, 434 .round_rate = clk_smd_rpm_round_rate, 435 .recalc_rate = clk_smd_rpm_recalc_rate, 436 }; 437 438 static const struct clk_ops clk_smd_rpm_branch_ops = { 439 .prepare = clk_smd_rpm_prepare, 440 .unprepare = clk_smd_rpm_unprepare, 441 .recalc_rate = clk_smd_rpm_recalc_rate, 442 }; 443 444 /* Disabling BI_TCXO_AO could gate the root clock source of the entire system. */ 445 DEFINE_CLK_SMD_RPM_BRANCH_A(bi_tcxo, QCOM_SMD_RPM_MISC_CLK, 0, 19200000, CLK_IS_CRITICAL); 446 DEFINE_CLK_SMD_RPM_BRANCH(qdss, QCOM_SMD_RPM_MISC_CLK, 1, 19200000); 447 DEFINE_CLK_SMD_RPM_QDSS(qdss, QCOM_SMD_RPM_MISC_CLK, 1); 448 DEFINE_CLK_SMD_RPM_BRANCH_A(bimc_freq_log, QCOM_SMD_RPM_MISC_CLK, 4, 1, 0); 449 450 DEFINE_CLK_SMD_RPM_BRANCH(mss_cfg_ahb, QCOM_SMD_RPM_MCFG_CLK, 0, 19200000); 451 452 DEFINE_CLK_SMD_RPM_BRANCH(aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1, 1000); 453 DEFINE_CLK_SMD_RPM_BRANCH(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2, 1000); 454 DEFINE_CLK_SMD_RPM(aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1); 455 DEFINE_CLK_SMD_RPM(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2); 456 457 DEFINE_CLK_SMD_RPM_BUS(pcnoc, 0); 458 DEFINE_CLK_SMD_RPM_BUS(snoc, 1); 459 DEFINE_CLK_SMD_RPM_BUS(sysmmnoc, 2); 460 DEFINE_CLK_SMD_RPM_BUS(cnoc, 2); 461 DEFINE_CLK_SMD_RPM_BUS(mmssnoc_ahb, 3); 462 DEFINE_CLK_SMD_RPM_BUS(snoc_periph, 0); 463 DEFINE_CLK_SMD_RPM_BUS(cnoc, 1); 464 DEFINE_CLK_SMD_RPM_BUS(snoc, 2); 465 DEFINE_CLK_SMD_RPM_BUS(snoc_lpass, 5); 466 467 DEFINE_CLK_SMD_RPM(bimc, QCOM_SMD_RPM_MEM_CLK, 0); 468 DEFINE_CLK_SMD_RPM(cpuss_gnoc, QCOM_SMD_RPM_MEM_CLK, 1); 469 DEFINE_CLK_SMD_RPM_CLK_SRC(gfx3d, QCOM_SMD_RPM_MEM_CLK, 1); 470 DEFINE_CLK_SMD_RPM(ocmemgx, QCOM_SMD_RPM_MEM_CLK, 2); 471 DEFINE_CLK_SMD_RPM(bimc_gpu, QCOM_SMD_RPM_MEM_CLK, 2); 472 473 DEFINE_CLK_SMD_RPM(ce1, QCOM_SMD_RPM_CE_CLK, 0); 474 DEFINE_CLK_SMD_RPM(ce2, QCOM_SMD_RPM_CE_CLK, 1); 475 DEFINE_CLK_SMD_RPM(ce3, QCOM_SMD_RPM_CE_CLK, 2); 476 477 DEFINE_CLK_SMD_RPM(ipa, QCOM_SMD_RPM_IPA_CLK, 0); 478 479 DEFINE_CLK_SMD_RPM(hwkm, QCOM_SMD_RPM_HWKM_CLK, 0); 480 481 DEFINE_CLK_SMD_RPM(mmssnoc_axi_rpm, QCOM_SMD_RPM_MMAXI_CLK, 0); 482 DEFINE_CLK_SMD_RPM(mmnrt, QCOM_SMD_RPM_MMAXI_CLK, 0); 483 DEFINE_CLK_SMD_RPM(mmrt, QCOM_SMD_RPM_MMAXI_CLK, 1); 484 485 DEFINE_CLK_SMD_RPM(pka, QCOM_SMD_RPM_PKA_CLK, 0); 486 487 DEFINE_CLK_SMD_RPM(qpic, QCOM_SMD_RPM_QPIC_CLK, 0); 488 489 DEFINE_CLK_SMD_RPM(qup, QCOM_SMD_RPM_QUP_CLK, 0); 490 491 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(bb_clk1, 1, 19200000); 492 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(bb_clk2, 2, 19200000); 493 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk1, 1, 19200000); 494 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk2, 2, 19200000); 495 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk3, 3, 19200000); 496 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk1, 4, 19200000); 497 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk2, 5, 19200000); 498 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk3, 6, 19200000); 499 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk, 8, 19200000); 500 501 DEFINE_CLK_SMD_RPM_XO_BUFFER_PREFIX(38m4_, rf_clk3, 6, 38400000); 502 503 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_d0, 1, 19200000); 504 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_d1, 2, 19200000); 505 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a0, 4, 19200000); 506 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a1, 5, 19200000); 507 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a2, 6, 19200000); 508 509 DEFINE_CLK_SMD_RPM_XO_BUFFER(diff_clk, 7, 19200000); 510 DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk1, 11, 19200000); 511 DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk2, 12, 19200000); 512 DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk3, 13, 19200000); 513 514 static struct clk_smd_rpm *msm8909_clks[] = { 515 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 516 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 517 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 518 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 519 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 520 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 521 [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, 522 [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, 523 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 524 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 525 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 526 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 527 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 528 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 529 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 530 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 531 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 532 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 533 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 534 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 535 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 536 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 537 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 538 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 539 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 540 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 541 }; 542 543 static const struct rpm_smd_clk_desc rpm_clk_msm8909 = { 544 .clks = msm8909_clks, 545 .num_clks = ARRAY_SIZE(msm8909_clks), 546 }; 547 548 static struct clk_smd_rpm *msm8916_clks[] = { 549 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 550 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 551 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 552 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 553 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 554 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 555 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 556 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 557 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 558 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 559 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 560 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 561 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 562 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 563 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 564 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 565 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 566 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 567 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 568 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 569 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 570 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 571 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 572 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 573 }; 574 575 static const struct rpm_smd_clk_desc rpm_clk_msm8916 = { 576 .clks = msm8916_clks, 577 .num_clks = ARRAY_SIZE(msm8916_clks), 578 }; 579 580 static struct clk_smd_rpm *msm8917_clks[] = { 581 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 582 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 583 [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 584 [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 585 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 586 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 587 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 588 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 589 [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk, 590 [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk, 591 [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk, 592 [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk, 593 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 594 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 595 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 596 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 597 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 598 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 599 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 600 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 601 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 602 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 603 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 604 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 605 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 606 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 607 }; 608 609 static const struct rpm_smd_clk_desc rpm_clk_msm8917 = { 610 .clks = msm8917_clks, 611 .num_clks = ARRAY_SIZE(msm8917_clks), 612 }; 613 614 static struct clk_smd_rpm *msm8936_clks[] = { 615 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 616 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 617 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 618 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 619 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 620 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 621 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 622 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 623 [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk, 624 [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk, 625 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 626 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 627 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 628 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 629 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 630 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 631 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 632 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 633 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 634 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 635 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 636 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 637 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 638 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 639 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 640 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 641 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 642 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 643 }; 644 645 static const struct rpm_smd_clk_desc rpm_clk_msm8936 = { 646 .clks = msm8936_clks, 647 .num_clks = ARRAY_SIZE(msm8936_clks), 648 }; 649 650 static struct clk_smd_rpm *msm8974_clks[] = { 651 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 652 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 653 [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 654 [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 655 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 656 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 657 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, 658 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, 659 [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk, 660 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk, 661 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 662 [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src, 663 [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src, 664 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 665 [RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk, 666 [RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk, 667 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 668 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 669 [RPM_SMD_CXO_D0] = &clk_smd_rpm_cxo_d0, 670 [RPM_SMD_CXO_D0_A] = &clk_smd_rpm_cxo_d0_a, 671 [RPM_SMD_CXO_D1] = &clk_smd_rpm_cxo_d1, 672 [RPM_SMD_CXO_D1_A] = &clk_smd_rpm_cxo_d1_a, 673 [RPM_SMD_CXO_A0] = &clk_smd_rpm_cxo_a0, 674 [RPM_SMD_CXO_A0_A] = &clk_smd_rpm_cxo_a0_a, 675 [RPM_SMD_CXO_A1] = &clk_smd_rpm_cxo_a1, 676 [RPM_SMD_CXO_A1_A] = &clk_smd_rpm_cxo_a1_a, 677 [RPM_SMD_CXO_A2] = &clk_smd_rpm_cxo_a2, 678 [RPM_SMD_CXO_A2_A] = &clk_smd_rpm_cxo_a2_a, 679 [RPM_SMD_DIFF_CLK] = &clk_smd_rpm_diff_clk, 680 [RPM_SMD_DIFF_A_CLK] = &clk_smd_rpm_diff_clk_a, 681 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, 682 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, 683 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 684 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 685 [RPM_SMD_CXO_D0_PIN] = &clk_smd_rpm_cxo_d0_pin, 686 [RPM_SMD_CXO_D0_A_PIN] = &clk_smd_rpm_cxo_d0_a_pin, 687 [RPM_SMD_CXO_D1_PIN] = &clk_smd_rpm_cxo_d1_pin, 688 [RPM_SMD_CXO_D1_A_PIN] = &clk_smd_rpm_cxo_d1_a_pin, 689 [RPM_SMD_CXO_A0_PIN] = &clk_smd_rpm_cxo_a0_pin, 690 [RPM_SMD_CXO_A0_A_PIN] = &clk_smd_rpm_cxo_a0_a_pin, 691 [RPM_SMD_CXO_A1_PIN] = &clk_smd_rpm_cxo_a1_pin, 692 [RPM_SMD_CXO_A1_A_PIN] = &clk_smd_rpm_cxo_a1_a_pin, 693 [RPM_SMD_CXO_A2_PIN] = &clk_smd_rpm_cxo_a2_pin, 694 [RPM_SMD_CXO_A2_A_PIN] = &clk_smd_rpm_cxo_a2_a_pin, 695 }; 696 697 static const struct rpm_smd_clk_desc rpm_clk_msm8974 = { 698 .clks = msm8974_clks, 699 .num_clks = ARRAY_SIZE(msm8974_clks), 700 .scaling_before_handover = true, 701 }; 702 703 static struct clk_smd_rpm *msm8976_clks[] = { 704 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 705 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 706 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 707 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 708 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 709 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 710 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 711 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 712 [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk, 713 [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk, 714 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 715 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 716 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 717 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 718 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 719 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 720 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 721 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 722 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 723 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 724 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 725 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 726 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 727 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 728 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 729 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 730 }; 731 732 static const struct rpm_smd_clk_desc rpm_clk_msm8976 = { 733 .clks = msm8976_clks, 734 .num_clks = ARRAY_SIZE(msm8976_clks), 735 }; 736 737 static struct clk_smd_rpm *msm8992_clks[] = { 738 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 739 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 740 [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 741 [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 742 [RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk, 743 [RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk, 744 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 745 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 746 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, 747 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, 748 [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src, 749 [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src, 750 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 751 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 752 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 753 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 754 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 755 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 756 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 757 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 758 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 759 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 760 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, 761 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, 762 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 763 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 764 [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3, 765 [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a, 766 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 767 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 768 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk, 769 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a, 770 [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk, 771 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk, 772 [RPM_SMD_MSS_CFG_AHB_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_clk, 773 [RPM_SMD_MSS_CFG_AHB_A_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_a_clk, 774 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 775 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 776 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 777 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 778 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 779 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 780 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 781 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 782 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 783 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 784 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 785 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 786 [RPM_SMD_CE2_CLK] = &clk_smd_rpm_ce2_clk, 787 [RPM_SMD_CE2_A_CLK] = &clk_smd_rpm_ce2_a_clk, 788 }; 789 790 static const struct rpm_smd_clk_desc rpm_clk_msm8992 = { 791 .clks = msm8992_clks, 792 .num_clks = ARRAY_SIZE(msm8992_clks), 793 }; 794 795 static struct clk_smd_rpm *msm8994_clks[] = { 796 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 797 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 798 [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 799 [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 800 [RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk, 801 [RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk, 802 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 803 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 804 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, 805 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, 806 [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src, 807 [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src, 808 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 809 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 810 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 811 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 812 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 813 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 814 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 815 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 816 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 817 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 818 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, 819 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, 820 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 821 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 822 [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3, 823 [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a, 824 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 825 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 826 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk, 827 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a, 828 [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk, 829 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk, 830 [RPM_SMD_MSS_CFG_AHB_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_clk, 831 [RPM_SMD_MSS_CFG_AHB_A_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_a_clk, 832 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 833 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 834 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 835 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 836 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 837 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 838 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 839 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 840 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 841 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 842 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 843 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 844 [RPM_SMD_CE2_CLK] = &clk_smd_rpm_ce2_clk, 845 [RPM_SMD_CE2_A_CLK] = &clk_smd_rpm_ce2_a_clk, 846 [RPM_SMD_CE3_CLK] = &clk_smd_rpm_ce3_clk, 847 [RPM_SMD_CE3_A_CLK] = &clk_smd_rpm_ce3_a_clk, 848 }; 849 850 static const struct rpm_smd_clk_desc rpm_clk_msm8994 = { 851 .clks = msm8994_clks, 852 .num_clks = ARRAY_SIZE(msm8994_clks), 853 }; 854 855 static struct clk_smd_rpm *msm8996_clks[] = { 856 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 857 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 858 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 859 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 860 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 861 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 862 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, 863 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, 864 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 865 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 866 [RPM_SMD_MMAXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk, 867 [RPM_SMD_MMAXI_A_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk, 868 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 869 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 870 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 871 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 872 [RPM_SMD_AGGR1_NOC_CLK] = &clk_smd_rpm_branch_aggre1_noc_clk, 873 [RPM_SMD_AGGR1_NOC_A_CLK] = &clk_smd_rpm_branch_aggre1_noc_a_clk, 874 [RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_branch_aggre2_noc_clk, 875 [RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_branch_aggre2_noc_a_clk, 876 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 877 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 878 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 879 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 880 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 881 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 882 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 883 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 884 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 885 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 886 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk, 887 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a, 888 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, 889 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, 890 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 891 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 892 [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3, 893 [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a, 894 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 895 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 896 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 897 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 898 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 899 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 900 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 901 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 902 }; 903 904 static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { 905 .clks = msm8996_clks, 906 .num_clks = ARRAY_SIZE(msm8996_clks), 907 }; 908 909 static struct clk_smd_rpm *qcs404_clks[] = { 910 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 911 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 912 [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 913 [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 914 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 915 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 916 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 917 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 918 [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk, 919 [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk, 920 [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, 921 [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, 922 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 923 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 924 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 925 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 926 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk, 927 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a, 928 [RPM_SMD_LN_BB_CLK_PIN] = &clk_smd_rpm_ln_bb_clk_pin, 929 [RPM_SMD_LN_BB_A_CLK_PIN] = &clk_smd_rpm_ln_bb_clk_a_pin, 930 }; 931 932 static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { 933 .clks = qcs404_clks, 934 .num_clks = ARRAY_SIZE(qcs404_clks), 935 }; 936 937 static struct clk_smd_rpm *msm8998_clks[] = { 938 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 939 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 940 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 941 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 942 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 943 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 944 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 945 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 946 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, 947 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, 948 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 949 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 950 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, 951 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, 952 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 953 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 954 [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3, 955 [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a, 956 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 957 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 958 [RPM_SMD_LN_BB_CLK1] = &clk_smd_rpm_ln_bb_clk1, 959 [RPM_SMD_LN_BB_CLK1_A] = &clk_smd_rpm_ln_bb_clk1_a, 960 [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, 961 [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, 962 [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3, 963 [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a, 964 [RPM_SMD_LN_BB_CLK1_PIN] = &clk_smd_rpm_ln_bb_clk1_pin, 965 [RPM_SMD_LN_BB_CLK1_A_PIN] = &clk_smd_rpm_ln_bb_clk1_a_pin, 966 [RPM_SMD_LN_BB_CLK2_PIN] = &clk_smd_rpm_ln_bb_clk2_pin, 967 [RPM_SMD_LN_BB_CLK2_A_PIN] = &clk_smd_rpm_ln_bb_clk2_a_pin, 968 [RPM_SMD_LN_BB_CLK3_PIN] = &clk_smd_rpm_ln_bb_clk3_pin, 969 [RPM_SMD_LN_BB_CLK3_A_PIN] = &clk_smd_rpm_ln_bb_clk3_a_pin, 970 [RPM_SMD_MMAXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk, 971 [RPM_SMD_MMAXI_A_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk, 972 [RPM_SMD_AGGR1_NOC_CLK] = &clk_smd_rpm_aggre1_noc_clk, 973 [RPM_SMD_AGGR1_NOC_A_CLK] = &clk_smd_rpm_aggre1_noc_a_clk, 974 [RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_aggre2_noc_clk, 975 [RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_aggre2_noc_a_clk, 976 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 977 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 978 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 979 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 980 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 981 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 982 [RPM_SMD_RF_CLK3] = &clk_smd_rpm_rf_clk3, 983 [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_rf_clk3_a, 984 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 985 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 986 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 987 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 988 [RPM_SMD_RF_CLK3_PIN] = &clk_smd_rpm_rf_clk3_pin, 989 [RPM_SMD_RF_CLK3_A_PIN] = &clk_smd_rpm_rf_clk3_a_pin, 990 }; 991 992 static const struct rpm_smd_clk_desc rpm_clk_msm8998 = { 993 .clks = msm8998_clks, 994 .num_clks = ARRAY_SIZE(msm8998_clks), 995 }; 996 997 static struct clk_smd_rpm *sdm660_clks[] = { 998 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 999 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1000 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 1001 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 1002 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, 1003 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, 1004 [RPM_SMD_CNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 1005 [RPM_SMD_CNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 1006 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 1007 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 1008 [RPM_SMD_MMSSNOC_AXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk, 1009 [RPM_SMD_MMSSNOC_AXI_CLK_A] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk, 1010 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 1011 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 1012 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 1013 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 1014 [RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_aggre2_noc_clk, 1015 [RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_aggre2_noc_a_clk, 1016 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 1017 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 1018 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 1019 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 1020 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, 1021 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, 1022 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk1, 1023 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk1_a, 1024 [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, 1025 [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, 1026 [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3, 1027 [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a, 1028 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 1029 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 1030 [RPM_SMD_LN_BB_CLK1_PIN] = &clk_smd_rpm_ln_bb_clk1_pin, 1031 [RPM_SMD_LN_BB_CLK1_A_PIN] = &clk_smd_rpm_ln_bb_clk1_a_pin, 1032 [RPM_SMD_LN_BB_CLK2_PIN] = &clk_smd_rpm_ln_bb_clk2_pin, 1033 [RPM_SMD_LN_BB_CLK2_A_PIN] = &clk_smd_rpm_ln_bb_clk2_a_pin, 1034 [RPM_SMD_LN_BB_CLK3_PIN] = &clk_smd_rpm_ln_bb_clk3_pin, 1035 [RPM_SMD_LN_BB_CLK3_A_PIN] = &clk_smd_rpm_ln_bb_clk3_a_pin, 1036 }; 1037 1038 static const struct rpm_smd_clk_desc rpm_clk_sdm660 = { 1039 .clks = sdm660_clks, 1040 .num_clks = ARRAY_SIZE(sdm660_clks), 1041 }; 1042 1043 static struct clk_smd_rpm *mdm9607_clks[] = { 1044 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1045 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1046 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 1047 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 1048 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 1049 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 1050 [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, 1051 [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, 1052 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 1053 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 1054 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 1055 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 1056 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 1057 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 1058 }; 1059 1060 static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = { 1061 .clks = mdm9607_clks, 1062 .num_clks = ARRAY_SIZE(mdm9607_clks), 1063 }; 1064 1065 static struct clk_smd_rpm *msm8953_clks[] = { 1066 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1067 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1068 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 1069 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 1070 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 1071 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 1072 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 1073 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 1074 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 1075 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 1076 [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk, 1077 [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk, 1078 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 1079 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 1080 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 1081 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 1082 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 1083 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 1084 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 1085 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 1086 [RPM_SMD_RF_CLK3] = &clk_smd_rpm_ln_bb_clk, 1087 [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_ln_bb_clk_a, 1088 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 1089 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 1090 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 1091 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 1092 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 1093 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 1094 }; 1095 1096 static const struct rpm_smd_clk_desc rpm_clk_msm8953 = { 1097 .clks = msm8953_clks, 1098 .num_clks = ARRAY_SIZE(msm8953_clks), 1099 }; 1100 1101 static struct clk_smd_rpm *sm6125_clks[] = { 1102 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1103 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1104 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk, 1105 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk, 1106 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 1107 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 1108 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, 1109 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, 1110 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 1111 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 1112 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 1113 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 1114 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk, 1115 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk, 1116 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 1117 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 1118 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 1119 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 1120 [RPM_SMD_LN_BB_CLK1] = &clk_smd_rpm_ln_bb_clk1, 1121 [RPM_SMD_LN_BB_CLK1_A] = &clk_smd_rpm_ln_bb_clk1_a, 1122 [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, 1123 [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, 1124 [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3, 1125 [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a, 1126 [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk, 1127 [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk, 1128 [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk, 1129 [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk, 1130 [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk, 1131 [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk, 1132 [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, 1133 [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, 1134 [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, 1135 [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, 1136 }; 1137 1138 static const struct rpm_smd_clk_desc rpm_clk_sm6125 = { 1139 .clks = sm6125_clks, 1140 .num_clks = ARRAY_SIZE(sm6125_clks), 1141 }; 1142 1143 /* SM6115 */ 1144 static struct clk_smd_rpm *sm6115_clks[] = { 1145 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1146 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1147 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk, 1148 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk, 1149 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 1150 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 1151 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, 1152 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, 1153 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 1154 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 1155 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 1156 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 1157 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk, 1158 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk, 1159 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 1160 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 1161 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 1162 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 1163 [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk, 1164 [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk, 1165 [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk, 1166 [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk, 1167 [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk, 1168 [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk, 1169 [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, 1170 [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, 1171 [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, 1172 [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, 1173 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 1174 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 1175 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 1176 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 1177 }; 1178 1179 static const struct rpm_smd_clk_desc rpm_clk_sm6115 = { 1180 .clks = sm6115_clks, 1181 .num_clks = ARRAY_SIZE(sm6115_clks), 1182 }; 1183 1184 static struct clk_smd_rpm *sm6375_clks[] = { 1185 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1186 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1187 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk, 1188 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk, 1189 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 1190 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 1191 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, 1192 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, 1193 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk, 1194 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk, 1195 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 1196 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 1197 [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk, 1198 [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk, 1199 [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk, 1200 [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk, 1201 [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk, 1202 [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk, 1203 [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, 1204 [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, 1205 [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, 1206 [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, 1207 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 1208 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 1209 [RPM_SMD_HWKM_CLK] = &clk_smd_rpm_hwkm_clk, 1210 [RPM_SMD_HWKM_A_CLK] = &clk_smd_rpm_hwkm_a_clk, 1211 [RPM_SMD_PKA_CLK] = &clk_smd_rpm_pka_clk, 1212 [RPM_SMD_PKA_A_CLK] = &clk_smd_rpm_pka_a_clk, 1213 [RPM_SMD_BIMC_FREQ_LOG] = &clk_smd_rpm_branch_bimc_freq_log, 1214 }; 1215 1216 static const struct rpm_smd_clk_desc rpm_clk_sm6375 = { 1217 .clks = sm6375_clks, 1218 .num_clks = ARRAY_SIZE(sm6375_clks), 1219 }; 1220 1221 static struct clk_smd_rpm *qcm2290_clks[] = { 1222 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1223 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1224 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk, 1225 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk, 1226 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 1227 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 1228 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, 1229 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, 1230 [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, 1231 [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, 1232 [RPM_SMD_RF_CLK3] = &clk_smd_rpm_38m4_rf_clk3, 1233 [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_38m4_rf_clk3_a, 1234 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk, 1235 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk, 1236 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 1237 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 1238 [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk, 1239 [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk, 1240 [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk, 1241 [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk, 1242 [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk, 1243 [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk, 1244 [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, 1245 [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, 1246 [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, 1247 [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, 1248 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 1249 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 1250 [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, 1251 [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, 1252 [RPM_SMD_HWKM_CLK] = &clk_smd_rpm_hwkm_clk, 1253 [RPM_SMD_HWKM_A_CLK] = &clk_smd_rpm_hwkm_a_clk, 1254 [RPM_SMD_PKA_CLK] = &clk_smd_rpm_pka_clk, 1255 [RPM_SMD_PKA_A_CLK] = &clk_smd_rpm_pka_a_clk, 1256 [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk, 1257 [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk, 1258 [RPM_SMD_CPUSS_GNOC_CLK] = &clk_smd_rpm_cpuss_gnoc_clk, 1259 [RPM_SMD_CPUSS_GNOC_A_CLK] = &clk_smd_rpm_cpuss_gnoc_a_clk, 1260 }; 1261 1262 static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = { 1263 .clks = qcm2290_clks, 1264 .num_clks = ARRAY_SIZE(qcm2290_clks), 1265 }; 1266 1267 static const struct of_device_id rpm_smd_clk_match_table[] = { 1268 { .compatible = "qcom,rpmcc-mdm9607", .data = &rpm_clk_mdm9607 }, 1269 { .compatible = "qcom,rpmcc-msm8226", .data = &rpm_clk_msm8974 }, 1270 { .compatible = "qcom,rpmcc-msm8909", .data = &rpm_clk_msm8909 }, 1271 { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 }, 1272 { .compatible = "qcom,rpmcc-msm8917", .data = &rpm_clk_msm8917 }, 1273 { .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 }, 1274 { .compatible = "qcom,rpmcc-msm8953", .data = &rpm_clk_msm8953 }, 1275 { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 }, 1276 { .compatible = "qcom,rpmcc-msm8976", .data = &rpm_clk_msm8976 }, 1277 { .compatible = "qcom,rpmcc-msm8992", .data = &rpm_clk_msm8992 }, 1278 { .compatible = "qcom,rpmcc-msm8994", .data = &rpm_clk_msm8994 }, 1279 { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 }, 1280 { .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 }, 1281 { .compatible = "qcom,rpmcc-qcm2290", .data = &rpm_clk_qcm2290 }, 1282 { .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 }, 1283 { .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660 }, 1284 { .compatible = "qcom,rpmcc-sm6115", .data = &rpm_clk_sm6115 }, 1285 { .compatible = "qcom,rpmcc-sm6125", .data = &rpm_clk_sm6125 }, 1286 { .compatible = "qcom,rpmcc-sm6375", .data = &rpm_clk_sm6375 }, 1287 { } 1288 }; 1289 MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table); 1290 1291 static struct clk_hw *qcom_smdrpm_clk_hw_get(struct of_phandle_args *clkspec, 1292 void *data) 1293 { 1294 const struct rpm_smd_clk_desc *desc = data; 1295 unsigned int idx = clkspec->args[0]; 1296 1297 if (idx >= desc->num_clks) { 1298 pr_err("%s: invalid index %u\n", __func__, idx); 1299 return ERR_PTR(-EINVAL); 1300 } 1301 1302 return desc->clks[idx] ? &desc->clks[idx]->hw : ERR_PTR(-ENOENT); 1303 } 1304 1305 static int rpm_smd_clk_probe(struct platform_device *pdev) 1306 { 1307 int ret; 1308 size_t num_clks, i; 1309 struct clk_smd_rpm **rpm_smd_clks; 1310 const struct rpm_smd_clk_desc *desc; 1311 1312 rpmcc_smd_rpm = dev_get_drvdata(pdev->dev.parent); 1313 if (!rpmcc_smd_rpm) { 1314 dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n"); 1315 return -ENODEV; 1316 } 1317 1318 desc = of_device_get_match_data(&pdev->dev); 1319 if (!desc) 1320 return -EINVAL; 1321 1322 rpm_smd_clks = desc->clks; 1323 num_clks = desc->num_clks; 1324 1325 if (desc->scaling_before_handover) { 1326 ret = clk_smd_rpm_enable_scaling(); 1327 if (ret) 1328 goto err; 1329 } 1330 1331 for (i = 0; i < num_clks; i++) { 1332 if (!rpm_smd_clks[i]) 1333 continue; 1334 1335 ret = clk_smd_rpm_handoff(rpm_smd_clks[i]); 1336 if (ret) 1337 goto err; 1338 } 1339 1340 if (!desc->scaling_before_handover) { 1341 ret = clk_smd_rpm_enable_scaling(); 1342 if (ret) 1343 goto err; 1344 } 1345 1346 for (i = 0; i < num_clks; i++) { 1347 if (!rpm_smd_clks[i]) 1348 continue; 1349 1350 ret = devm_clk_hw_register(&pdev->dev, &rpm_smd_clks[i]->hw); 1351 if (ret) 1352 goto err; 1353 } 1354 1355 ret = devm_of_clk_add_hw_provider(&pdev->dev, qcom_smdrpm_clk_hw_get, 1356 (void *)desc); 1357 if (ret) 1358 goto err; 1359 1360 return 0; 1361 err: 1362 dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret); 1363 return ret; 1364 } 1365 1366 static struct platform_driver rpm_smd_clk_driver = { 1367 .driver = { 1368 .name = "qcom-clk-smd-rpm", 1369 .of_match_table = rpm_smd_clk_match_table, 1370 }, 1371 .probe = rpm_smd_clk_probe, 1372 }; 1373 1374 static int __init rpm_smd_clk_init(void) 1375 { 1376 return platform_driver_register(&rpm_smd_clk_driver); 1377 } 1378 core_initcall(rpm_smd_clk_init); 1379 1380 static void __exit rpm_smd_clk_exit(void) 1381 { 1382 platform_driver_unregister(&rpm_smd_clk_driver); 1383 } 1384 module_exit(rpm_smd_clk_exit); 1385 1386 MODULE_DESCRIPTION("Qualcomm RPM over SMD Clock Controller Driver"); 1387 MODULE_LICENSE("GPL v2"); 1388 MODULE_ALIAS("platform:qcom-clk-smd-rpm"); 1389