1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/err.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/platform_device.h> 12 #include <linux/string_choices.h> 13 #include <soc/qcom/cmd-db.h> 14 #include <soc/qcom/rpmh.h> 15 #include <soc/qcom/tcs.h> 16 17 #include <dt-bindings/clock/qcom,rpmh.h> 18 19 #define CLK_RPMH_ARC_EN_OFFSET 0 20 #define CLK_RPMH_VRM_EN_OFFSET 4 21 22 /** 23 * struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager(BCM) 24 * @unit: divisor used to convert Hz value to an RPMh msg 25 * @width: multiplier used to convert Hz value to an RPMh msg 26 * @vcd: virtual clock domain that this bcm belongs to 27 * @reserved: reserved to pad the struct 28 */ 29 struct bcm_db { 30 __le32 unit; 31 __le16 width; 32 u8 vcd; 33 u8 reserved; 34 }; 35 36 /** 37 * struct clk_rpmh - individual rpmh clock data structure 38 * @hw: handle between common and hardware-specific interfaces 39 * @res_name: resource name for the rpmh clock 40 * @div: clock divider to compute the clock rate 41 * @res_addr: base address of the rpmh resource within the RPMh 42 * @res_on_val: rpmh clock enable value 43 * @state: rpmh clock requested state 44 * @aggr_state: rpmh clock aggregated state 45 * @last_sent_aggr_state: rpmh clock last aggr state sent to RPMh 46 * @valid_state_mask: mask to determine the state of the rpmh clock 47 * @unit: divisor to convert rate to rpmh msg in magnitudes of Khz 48 * @dev: device to which it is attached 49 * @peer: pointer to the clock rpmh sibling 50 */ 51 struct clk_rpmh { 52 struct clk_hw hw; 53 const char *res_name; 54 u8 div; 55 u32 res_addr; 56 u32 res_on_val; 57 u32 state; 58 u32 aggr_state; 59 u32 last_sent_aggr_state; 60 u32 valid_state_mask; 61 u32 unit; 62 struct device *dev; 63 struct clk_rpmh *peer; 64 }; 65 66 struct clk_rpmh_desc { 67 struct clk_hw **clks; 68 size_t num_clks; 69 }; 70 71 static DEFINE_MUTEX(rpmh_clk_lock); 72 73 #define __DEFINE_CLK_RPMH(_name, _clk_name, _res_name, \ 74 _res_en_offset, _res_on, _div) \ 75 static struct clk_rpmh clk_rpmh_##_clk_name##_ao; \ 76 static struct clk_rpmh clk_rpmh_##_clk_name = { \ 77 .res_name = _res_name, \ 78 .res_addr = _res_en_offset, \ 79 .res_on_val = _res_on, \ 80 .div = _div, \ 81 .peer = &clk_rpmh_##_clk_name##_ao, \ 82 .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \ 83 BIT(RPMH_ACTIVE_ONLY_STATE) | \ 84 BIT(RPMH_SLEEP_STATE)), \ 85 .hw.init = &(struct clk_init_data){ \ 86 .ops = &clk_rpmh_ops, \ 87 .name = #_name, \ 88 .parent_data = &(const struct clk_parent_data){ \ 89 .fw_name = "xo", \ 90 .name = "xo_board", \ 91 }, \ 92 .num_parents = 1, \ 93 }, \ 94 }; \ 95 static struct clk_rpmh clk_rpmh_##_clk_name##_ao= { \ 96 .res_name = _res_name, \ 97 .res_addr = _res_en_offset, \ 98 .res_on_val = _res_on, \ 99 .div = _div, \ 100 .peer = &clk_rpmh_##_clk_name, \ 101 .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \ 102 BIT(RPMH_ACTIVE_ONLY_STATE)), \ 103 .hw.init = &(struct clk_init_data){ \ 104 .ops = &clk_rpmh_ops, \ 105 .name = #_name "_ao", \ 106 .parent_data = &(const struct clk_parent_data){ \ 107 .fw_name = "xo", \ 108 .name = "xo_board", \ 109 }, \ 110 .num_parents = 1, \ 111 }, \ 112 } 113 114 #define DEFINE_CLK_RPMH_ARC(_name, _res_name, _res_on, _div) \ 115 __DEFINE_CLK_RPMH(_name, _name##_##div##_div, _res_name, \ 116 CLK_RPMH_ARC_EN_OFFSET, _res_on, _div) 117 118 #define DEFINE_CLK_RPMH_VRM(_name, _suffix, _res_name, _div) \ 119 __DEFINE_CLK_RPMH(_name, _name##_suffix, _res_name, \ 120 CLK_RPMH_VRM_EN_OFFSET, 1, _div) 121 122 #define DEFINE_CLK_RPMH_BCM(_name, _res_name) \ 123 static struct clk_rpmh clk_rpmh_##_name = { \ 124 .res_name = _res_name, \ 125 .valid_state_mask = BIT(RPMH_ACTIVE_ONLY_STATE), \ 126 .div = 1, \ 127 .hw.init = &(struct clk_init_data){ \ 128 .ops = &clk_rpmh_bcm_ops, \ 129 .name = #_name, \ 130 }, \ 131 } 132 133 static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw) 134 { 135 return container_of(_hw, struct clk_rpmh, hw); 136 } 137 138 static inline bool has_state_changed(struct clk_rpmh *c, u32 state) 139 { 140 return (c->last_sent_aggr_state & BIT(state)) 141 != (c->aggr_state & BIT(state)); 142 } 143 144 static int clk_rpmh_send(struct clk_rpmh *c, enum rpmh_state state, 145 struct tcs_cmd *cmd, bool wait) 146 { 147 if (wait) 148 return rpmh_write(c->dev, state, cmd, 1); 149 150 return rpmh_write_async(c->dev, state, cmd, 1); 151 } 152 153 static int clk_rpmh_send_aggregate_command(struct clk_rpmh *c) 154 { 155 struct tcs_cmd cmd = { 0 }; 156 u32 cmd_state, on_val; 157 enum rpmh_state state = RPMH_SLEEP_STATE; 158 int ret; 159 bool wait; 160 161 cmd.addr = c->res_addr; 162 cmd_state = c->aggr_state; 163 on_val = c->res_on_val; 164 165 for (; state <= RPMH_ACTIVE_ONLY_STATE; state++) { 166 if (has_state_changed(c, state)) { 167 if (cmd_state & BIT(state)) 168 cmd.data = on_val; 169 170 wait = cmd_state && state == RPMH_ACTIVE_ONLY_STATE; 171 ret = clk_rpmh_send(c, state, &cmd, wait); 172 if (ret) { 173 dev_err(c->dev, "set %s state of %s failed: (%d)\n", 174 !state ? "sleep" : 175 state == RPMH_WAKE_ONLY_STATE ? 176 "wake" : "active", c->res_name, ret); 177 return ret; 178 } 179 } 180 } 181 182 c->last_sent_aggr_state = c->aggr_state; 183 c->peer->last_sent_aggr_state = c->last_sent_aggr_state; 184 185 return 0; 186 } 187 188 /* 189 * Update state and aggregate state values based on enable value. 190 */ 191 static int clk_rpmh_aggregate_state_send_command(struct clk_rpmh *c, 192 bool enable) 193 { 194 int ret; 195 196 c->state = enable ? c->valid_state_mask : 0; 197 c->aggr_state = c->state | c->peer->state; 198 c->peer->aggr_state = c->aggr_state; 199 200 ret = clk_rpmh_send_aggregate_command(c); 201 if (!ret) 202 return 0; 203 204 if (ret && enable) 205 c->state = 0; 206 else if (ret) 207 c->state = c->valid_state_mask; 208 209 WARN(1, "clk: %s failed to %s\n", c->res_name, 210 str_enable_disable(enable)); 211 return ret; 212 } 213 214 static int clk_rpmh_prepare(struct clk_hw *hw) 215 { 216 struct clk_rpmh *c = to_clk_rpmh(hw); 217 int ret = 0; 218 219 mutex_lock(&rpmh_clk_lock); 220 ret = clk_rpmh_aggregate_state_send_command(c, true); 221 mutex_unlock(&rpmh_clk_lock); 222 223 return ret; 224 } 225 226 static void clk_rpmh_unprepare(struct clk_hw *hw) 227 { 228 struct clk_rpmh *c = to_clk_rpmh(hw); 229 230 mutex_lock(&rpmh_clk_lock); 231 clk_rpmh_aggregate_state_send_command(c, false); 232 mutex_unlock(&rpmh_clk_lock); 233 }; 234 235 static unsigned long clk_rpmh_recalc_rate(struct clk_hw *hw, 236 unsigned long prate) 237 { 238 struct clk_rpmh *r = to_clk_rpmh(hw); 239 240 /* 241 * RPMh clocks have a fixed rate. Return static rate. 242 */ 243 return prate / r->div; 244 } 245 246 static const struct clk_ops clk_rpmh_ops = { 247 .prepare = clk_rpmh_prepare, 248 .unprepare = clk_rpmh_unprepare, 249 .recalc_rate = clk_rpmh_recalc_rate, 250 }; 251 252 static int clk_rpmh_bcm_send_cmd(struct clk_rpmh *c, bool enable) 253 { 254 struct tcs_cmd cmd = { 0 }; 255 u32 cmd_state; 256 int ret = 0; 257 258 mutex_lock(&rpmh_clk_lock); 259 if (enable) { 260 cmd_state = 1; 261 if (c->aggr_state) 262 cmd_state = c->aggr_state; 263 } else { 264 cmd_state = 0; 265 } 266 267 cmd_state = min(cmd_state, BCM_TCS_CMD_VOTE_MASK); 268 269 if (c->last_sent_aggr_state != cmd_state) { 270 cmd.addr = c->res_addr; 271 cmd.data = BCM_TCS_CMD(1, enable, 0, cmd_state); 272 273 /* 274 * Send only an active only state request. RPMh continues to 275 * use the active state when we're in sleep/wake state as long 276 * as the sleep/wake state has never been set. 277 */ 278 ret = clk_rpmh_send(c, RPMH_ACTIVE_ONLY_STATE, &cmd, enable); 279 if (ret) { 280 dev_err(c->dev, "set active state of %s failed: (%d)\n", 281 c->res_name, ret); 282 } else { 283 c->last_sent_aggr_state = cmd_state; 284 } 285 } 286 287 mutex_unlock(&rpmh_clk_lock); 288 289 return ret; 290 } 291 292 static int clk_rpmh_bcm_prepare(struct clk_hw *hw) 293 { 294 struct clk_rpmh *c = to_clk_rpmh(hw); 295 296 return clk_rpmh_bcm_send_cmd(c, true); 297 } 298 299 static void clk_rpmh_bcm_unprepare(struct clk_hw *hw) 300 { 301 struct clk_rpmh *c = to_clk_rpmh(hw); 302 303 clk_rpmh_bcm_send_cmd(c, false); 304 } 305 306 static int clk_rpmh_bcm_set_rate(struct clk_hw *hw, unsigned long rate, 307 unsigned long parent_rate) 308 { 309 struct clk_rpmh *c = to_clk_rpmh(hw); 310 311 c->aggr_state = rate / c->unit; 312 /* 313 * Since any non-zero value sent to hw would result in enabling the 314 * clock, only send the value if the clock has already been prepared. 315 */ 316 if (clk_hw_is_prepared(hw)) 317 clk_rpmh_bcm_send_cmd(c, true); 318 319 return 0; 320 } 321 322 static long clk_rpmh_round_rate(struct clk_hw *hw, unsigned long rate, 323 unsigned long *parent_rate) 324 { 325 return rate; 326 } 327 328 static unsigned long clk_rpmh_bcm_recalc_rate(struct clk_hw *hw, 329 unsigned long prate) 330 { 331 struct clk_rpmh *c = to_clk_rpmh(hw); 332 333 return (unsigned long)c->aggr_state * c->unit; 334 } 335 336 static const struct clk_ops clk_rpmh_bcm_ops = { 337 .prepare = clk_rpmh_bcm_prepare, 338 .unprepare = clk_rpmh_bcm_unprepare, 339 .set_rate = clk_rpmh_bcm_set_rate, 340 .round_rate = clk_rpmh_round_rate, 341 .recalc_rate = clk_rpmh_bcm_recalc_rate, 342 }; 343 344 /* Resource name must match resource id present in cmd-db */ 345 DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 1); 346 DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 2); 347 DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 4); 348 DEFINE_CLK_RPMH_ARC(qlink, "qphy.lvl", 0x1, 4); 349 350 DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a2, "lnbclka1", 2); 351 DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a2, "lnbclka2", 2); 352 DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a2, "lnbclka3", 2); 353 354 DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a4, "lnbclka1", 4); 355 DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a4, "lnbclka2", 4); 356 DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a4, "lnbclka3", 4); 357 358 DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _g4, "lnbclkg2", 4); 359 DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _g4, "lnbclkg3", 4); 360 361 DEFINE_CLK_RPMH_VRM(rf_clk1, _a, "rfclka1", 1); 362 DEFINE_CLK_RPMH_VRM(rf_clk2, _a, "rfclka2", 1); 363 DEFINE_CLK_RPMH_VRM(rf_clk3, _a, "rfclka3", 1); 364 DEFINE_CLK_RPMH_VRM(rf_clk4, _a, "rfclka4", 1); 365 DEFINE_CLK_RPMH_VRM(rf_clk5, _a, "rfclka5", 1); 366 367 DEFINE_CLK_RPMH_VRM(rf_clk1, _d, "rfclkd1", 1); 368 DEFINE_CLK_RPMH_VRM(rf_clk2, _d, "rfclkd2", 1); 369 DEFINE_CLK_RPMH_VRM(rf_clk3, _d, "rfclkd3", 1); 370 DEFINE_CLK_RPMH_VRM(rf_clk4, _d, "rfclkd4", 1); 371 372 DEFINE_CLK_RPMH_VRM(rf_clk3, _a2, "rfclka3", 2); 373 374 DEFINE_CLK_RPMH_VRM(clk1, _a1, "clka1", 1); 375 DEFINE_CLK_RPMH_VRM(clk2, _a1, "clka2", 1); 376 DEFINE_CLK_RPMH_VRM(clk3, _a1, "clka3", 1); 377 DEFINE_CLK_RPMH_VRM(clk4, _a1, "clka4", 1); 378 DEFINE_CLK_RPMH_VRM(clk5, _a1, "clka5", 1); 379 380 DEFINE_CLK_RPMH_VRM(clk3, _a2, "clka3", 2); 381 DEFINE_CLK_RPMH_VRM(clk4, _a2, "clka4", 2); 382 DEFINE_CLK_RPMH_VRM(clk5, _a2, "clka5", 2); 383 DEFINE_CLK_RPMH_VRM(clk6, _a2, "clka6", 2); 384 DEFINE_CLK_RPMH_VRM(clk7, _a2, "clka7", 2); 385 DEFINE_CLK_RPMH_VRM(clk8, _a2, "clka8", 2); 386 387 DEFINE_CLK_RPMH_VRM(div_clk1, _div2, "divclka1", 2); 388 389 DEFINE_CLK_RPMH_BCM(ce, "CE0"); 390 DEFINE_CLK_RPMH_BCM(hwkm, "HK0"); 391 DEFINE_CLK_RPMH_BCM(ipa, "IP0"); 392 DEFINE_CLK_RPMH_BCM(pka, "PKA0"); 393 DEFINE_CLK_RPMH_BCM(qpic_clk, "QP0"); 394 395 static struct clk_hw *sar2130p_rpmh_clocks[] = { 396 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div1.hw, 397 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div1_ao.hw, 398 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 399 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 400 }; 401 402 static const struct clk_rpmh_desc clk_rpmh_sar2130p = { 403 .clks = sar2130p_rpmh_clocks, 404 .num_clks = ARRAY_SIZE(sar2130p_rpmh_clocks), 405 }; 406 407 static struct clk_hw *sdm845_rpmh_clocks[] = { 408 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 409 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 410 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 411 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 412 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 413 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 414 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 415 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 416 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 417 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 418 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 419 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 420 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 421 [RPMH_CE_CLK] = &clk_rpmh_ce.hw, 422 }; 423 424 static const struct clk_rpmh_desc clk_rpmh_sdm845 = { 425 .clks = sdm845_rpmh_clocks, 426 .num_clks = ARRAY_SIZE(sdm845_rpmh_clocks), 427 }; 428 429 static struct clk_hw *sa8775p_rpmh_clocks[] = { 430 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 431 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 432 [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2.hw, 433 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 434 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a4_ao.hw, 435 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 436 [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, 437 [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, 438 }; 439 440 static const struct clk_rpmh_desc clk_rpmh_sa8775p = { 441 .clks = sa8775p_rpmh_clocks, 442 .num_clks = ARRAY_SIZE(sa8775p_rpmh_clocks), 443 }; 444 445 static struct clk_hw *sdm670_rpmh_clocks[] = { 446 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 447 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 448 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 449 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 450 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 451 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 452 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 453 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 454 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 455 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 456 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 457 [RPMH_CE_CLK] = &clk_rpmh_ce.hw, 458 }; 459 460 static const struct clk_rpmh_desc clk_rpmh_sdm670 = { 461 .clks = sdm670_rpmh_clocks, 462 .num_clks = ARRAY_SIZE(sdm670_rpmh_clocks), 463 }; 464 465 static struct clk_hw *sdx55_rpmh_clocks[] = { 466 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 467 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 468 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_d.hw, 469 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_d_ao.hw, 470 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_d.hw, 471 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_d_ao.hw, 472 [RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw, 473 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 474 }; 475 476 static const struct clk_rpmh_desc clk_rpmh_sdx55 = { 477 .clks = sdx55_rpmh_clocks, 478 .num_clks = ARRAY_SIZE(sdx55_rpmh_clocks), 479 }; 480 481 static struct clk_hw *sm8150_rpmh_clocks[] = { 482 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 483 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 484 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 485 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 486 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 487 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 488 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 489 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 490 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 491 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 492 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 493 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 494 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 495 }; 496 497 static const struct clk_rpmh_desc clk_rpmh_sm8150 = { 498 .clks = sm8150_rpmh_clocks, 499 .num_clks = ARRAY_SIZE(sm8150_rpmh_clocks), 500 }; 501 502 static struct clk_hw *sc7180_rpmh_clocks[] = { 503 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 504 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 505 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 506 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 507 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 508 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 509 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 510 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 511 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 512 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 513 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 514 }; 515 516 static const struct clk_rpmh_desc clk_rpmh_sc7180 = { 517 .clks = sc7180_rpmh_clocks, 518 .num_clks = ARRAY_SIZE(sc7180_rpmh_clocks), 519 }; 520 521 static struct clk_hw *sc8180x_rpmh_clocks[] = { 522 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 523 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 524 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 525 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 526 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 527 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 528 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_d.hw, 529 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_d_ao.hw, 530 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_d.hw, 531 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_d_ao.hw, 532 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_d.hw, 533 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_d_ao.hw, 534 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 535 }; 536 537 static const struct clk_rpmh_desc clk_rpmh_sc8180x = { 538 .clks = sc8180x_rpmh_clocks, 539 .num_clks = ARRAY_SIZE(sc8180x_rpmh_clocks), 540 }; 541 542 static struct clk_hw *sm8250_rpmh_clocks[] = { 543 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 544 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 545 [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2.hw, 546 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a2_ao.hw, 547 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 548 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 549 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 550 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 551 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 552 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 553 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 554 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 555 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 556 }; 557 558 static const struct clk_rpmh_desc clk_rpmh_sm8250 = { 559 .clks = sm8250_rpmh_clocks, 560 .num_clks = ARRAY_SIZE(sm8250_rpmh_clocks), 561 }; 562 563 static struct clk_hw *sm8350_rpmh_clocks[] = { 564 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 565 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 566 [RPMH_DIV_CLK1] = &clk_rpmh_div_clk1_div2.hw, 567 [RPMH_DIV_CLK1_A] = &clk_rpmh_div_clk1_div2_ao.hw, 568 [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2.hw, 569 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a2_ao.hw, 570 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 571 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 572 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 573 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 574 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 575 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 576 [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw, 577 [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw, 578 [RPMH_RF_CLK5] = &clk_rpmh_rf_clk5_a.hw, 579 [RPMH_RF_CLK5_A] = &clk_rpmh_rf_clk5_a_ao.hw, 580 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 581 [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, 582 [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, 583 }; 584 585 static const struct clk_rpmh_desc clk_rpmh_sm8350 = { 586 .clks = sm8350_rpmh_clocks, 587 .num_clks = ARRAY_SIZE(sm8350_rpmh_clocks), 588 }; 589 590 static struct clk_hw *sc8280xp_rpmh_clocks[] = { 591 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 592 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 593 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 594 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 595 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 596 [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, 597 [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, 598 }; 599 600 static const struct clk_rpmh_desc clk_rpmh_sc8280xp = { 601 .clks = sc8280xp_rpmh_clocks, 602 .num_clks = ARRAY_SIZE(sc8280xp_rpmh_clocks), 603 }; 604 605 static struct clk_hw *sm8450_rpmh_clocks[] = { 606 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, 607 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, 608 [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a4.hw, 609 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a4_ao.hw, 610 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a4.hw, 611 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a4_ao.hw, 612 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 613 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 614 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 615 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 616 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 617 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 618 [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw, 619 [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw, 620 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 621 }; 622 623 static const struct clk_rpmh_desc clk_rpmh_sm8450 = { 624 .clks = sm8450_rpmh_clocks, 625 .num_clks = ARRAY_SIZE(sm8450_rpmh_clocks), 626 }; 627 628 static struct clk_hw *sm8550_rpmh_clocks[] = { 629 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 630 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 631 [RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw, 632 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw, 633 [RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a2.hw, 634 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a2_ao.hw, 635 [RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw, 636 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw, 637 [RPMH_RF_CLK1] = &clk_rpmh_clk1_a1.hw, 638 [RPMH_RF_CLK1_A] = &clk_rpmh_clk1_a1_ao.hw, 639 [RPMH_RF_CLK2] = &clk_rpmh_clk2_a1.hw, 640 [RPMH_RF_CLK2_A] = &clk_rpmh_clk2_a1_ao.hw, 641 [RPMH_RF_CLK3] = &clk_rpmh_clk3_a1.hw, 642 [RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a1_ao.hw, 643 [RPMH_RF_CLK4] = &clk_rpmh_clk4_a1.hw, 644 [RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a1_ao.hw, 645 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 646 }; 647 648 static const struct clk_rpmh_desc clk_rpmh_sm8550 = { 649 .clks = sm8550_rpmh_clocks, 650 .num_clks = ARRAY_SIZE(sm8550_rpmh_clocks), 651 }; 652 653 static struct clk_hw *sm8650_rpmh_clocks[] = { 654 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 655 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 656 [RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw, 657 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw, 658 [RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a2.hw, 659 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a2_ao.hw, 660 [RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw, 661 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw, 662 [RPMH_RF_CLK1] = &clk_rpmh_clk1_a1.hw, 663 [RPMH_RF_CLK1_A] = &clk_rpmh_clk1_a1_ao.hw, 664 [RPMH_RF_CLK2] = &clk_rpmh_clk2_a1.hw, 665 [RPMH_RF_CLK2_A] = &clk_rpmh_clk2_a1_ao.hw, 666 /* 667 * The clka3 RPMh resource is missing in cmd-db 668 * for current platforms, while the clka3 exists 669 * on the PMK8550, the clock is unconnected and 670 * unused. 671 */ 672 [RPMH_RF_CLK4] = &clk_rpmh_clk4_a2.hw, 673 [RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a2_ao.hw, 674 [RPMH_RF_CLK5] = &clk_rpmh_clk5_a2.hw, 675 [RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a2_ao.hw, 676 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 677 }; 678 679 static const struct clk_rpmh_desc clk_rpmh_sm8650 = { 680 .clks = sm8650_rpmh_clocks, 681 .num_clks = ARRAY_SIZE(sm8650_rpmh_clocks), 682 }; 683 684 static struct clk_hw *sc7280_rpmh_clocks[] = { 685 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, 686 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, 687 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 688 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 689 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 690 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 691 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 692 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 693 [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw, 694 [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw, 695 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 696 [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, 697 [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, 698 }; 699 700 static const struct clk_rpmh_desc clk_rpmh_sc7280 = { 701 .clks = sc7280_rpmh_clocks, 702 .num_clks = ARRAY_SIZE(sc7280_rpmh_clocks), 703 }; 704 705 static struct clk_hw *sm6350_rpmh_clocks[] = { 706 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, 707 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, 708 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_g4.hw, 709 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_g4_ao.hw, 710 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_g4.hw, 711 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_g4_ao.hw, 712 [RPMH_QLINK_CLK] = &clk_rpmh_qlink_div4.hw, 713 [RPMH_QLINK_CLK_A] = &clk_rpmh_qlink_div4_ao.hw, 714 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 715 }; 716 717 static const struct clk_rpmh_desc clk_rpmh_sm6350 = { 718 .clks = sm6350_rpmh_clocks, 719 .num_clks = ARRAY_SIZE(sm6350_rpmh_clocks), 720 }; 721 722 static struct clk_hw *sdx65_rpmh_clocks[] = { 723 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, 724 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, 725 [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a4.hw, 726 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a4_ao.hw, 727 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 728 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 729 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 730 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 731 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 732 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 733 [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw, 734 [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw, 735 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 736 [RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw, 737 }; 738 739 static const struct clk_rpmh_desc clk_rpmh_sdx65 = { 740 .clks = sdx65_rpmh_clocks, 741 .num_clks = ARRAY_SIZE(sdx65_rpmh_clocks), 742 }; 743 744 static struct clk_hw *qdu1000_rpmh_clocks[] = { 745 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div1.hw, 746 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div1_ao.hw, 747 }; 748 749 static const struct clk_rpmh_desc clk_rpmh_qdu1000 = { 750 .clks = qdu1000_rpmh_clocks, 751 .num_clks = ARRAY_SIZE(qdu1000_rpmh_clocks), 752 }; 753 754 static struct clk_hw *sdx75_rpmh_clocks[] = { 755 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, 756 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, 757 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 758 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 759 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 760 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 761 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 762 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 763 [RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw, 764 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 765 }; 766 767 static const struct clk_rpmh_desc clk_rpmh_sdx75 = { 768 .clks = sdx75_rpmh_clocks, 769 .num_clks = ARRAY_SIZE(sdx75_rpmh_clocks), 770 }; 771 772 static struct clk_hw *sm4450_rpmh_clocks[] = { 773 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, 774 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, 775 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a4.hw, 776 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a4_ao.hw, 777 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a4.hw, 778 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a4_ao.hw, 779 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 780 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 781 [RPMH_RF_CLK5] = &clk_rpmh_rf_clk5_a.hw, 782 [RPMH_RF_CLK5_A] = &clk_rpmh_rf_clk5_a_ao.hw, 783 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 784 }; 785 786 static const struct clk_rpmh_desc clk_rpmh_sm4450 = { 787 .clks = sm4450_rpmh_clocks, 788 .num_clks = ARRAY_SIZE(sm4450_rpmh_clocks), 789 }; 790 791 static struct clk_hw *x1e80100_rpmh_clocks[] = { 792 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 793 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 794 [RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw, 795 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw, 796 [RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a2.hw, 797 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a2_ao.hw, 798 [RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw, 799 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw, 800 [RPMH_RF_CLK3] = &clk_rpmh_clk3_a2.hw, 801 [RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a2_ao.hw, 802 [RPMH_RF_CLK4] = &clk_rpmh_clk4_a2.hw, 803 [RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a2_ao.hw, 804 [RPMH_RF_CLK5] = &clk_rpmh_clk5_a2.hw, 805 [RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a2_ao.hw, 806 }; 807 808 static const struct clk_rpmh_desc clk_rpmh_x1e80100 = { 809 .clks = x1e80100_rpmh_clocks, 810 .num_clks = ARRAY_SIZE(x1e80100_rpmh_clocks), 811 }; 812 813 static struct clk_hw *qcs615_rpmh_clocks[] = { 814 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 815 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 816 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 817 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 818 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 819 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 820 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 821 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 822 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 823 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 824 }; 825 826 static const struct clk_rpmh_desc clk_rpmh_qcs615 = { 827 .clks = qcs615_rpmh_clocks, 828 .num_clks = ARRAY_SIZE(qcs615_rpmh_clocks), 829 }; 830 831 static struct clk_hw *sm8750_rpmh_clocks[] = { 832 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 833 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 834 [RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw, 835 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw, 836 [RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw, 837 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw, 838 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 839 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 840 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 841 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 842 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a2.hw, 843 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a2_ao.hw, 844 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 845 }; 846 847 static const struct clk_rpmh_desc clk_rpmh_sm8750 = { 848 .clks = sm8750_rpmh_clocks, 849 .num_clks = ARRAY_SIZE(sm8750_rpmh_clocks), 850 }; 851 852 static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, 853 void *data) 854 { 855 struct clk_rpmh_desc *rpmh = data; 856 unsigned int idx = clkspec->args[0]; 857 858 if (idx >= rpmh->num_clks) { 859 pr_err("%s: invalid index %u\n", __func__, idx); 860 return ERR_PTR(-EINVAL); 861 } 862 863 return rpmh->clks[idx]; 864 } 865 866 static int clk_rpmh_probe(struct platform_device *pdev) 867 { 868 struct clk_hw **hw_clks; 869 struct clk_rpmh *rpmh_clk; 870 const struct clk_rpmh_desc *desc; 871 int ret, i; 872 873 desc = of_device_get_match_data(&pdev->dev); 874 if (!desc) 875 return -ENODEV; 876 877 hw_clks = desc->clks; 878 879 for (i = 0; i < desc->num_clks; i++) { 880 const char *name; 881 u32 res_addr; 882 size_t aux_data_len; 883 const struct bcm_db *data; 884 885 if (!hw_clks[i]) 886 continue; 887 888 name = hw_clks[i]->init->name; 889 890 rpmh_clk = to_clk_rpmh(hw_clks[i]); 891 res_addr = cmd_db_read_addr(rpmh_clk->res_name); 892 if (!res_addr) { 893 dev_err(&pdev->dev, "missing RPMh resource address for %s\n", 894 rpmh_clk->res_name); 895 return -ENODEV; 896 } 897 898 data = cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len); 899 if (IS_ERR(data)) { 900 ret = PTR_ERR(data); 901 dev_err(&pdev->dev, 902 "error reading RPMh aux data for %s (%d)\n", 903 rpmh_clk->res_name, ret); 904 return ret; 905 } 906 907 /* Convert unit from Khz to Hz */ 908 if (aux_data_len == sizeof(*data)) 909 rpmh_clk->unit = le32_to_cpu(data->unit) * 1000ULL; 910 911 rpmh_clk->res_addr += res_addr; 912 rpmh_clk->dev = &pdev->dev; 913 914 ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]); 915 if (ret) { 916 dev_err(&pdev->dev, "failed to register %s\n", name); 917 return ret; 918 } 919 } 920 921 /* typecast to silence compiler warning */ 922 ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_rpmh_hw_get, 923 (void *)desc); 924 if (ret) { 925 dev_err(&pdev->dev, "Failed to add clock provider\n"); 926 return ret; 927 } 928 929 dev_dbg(&pdev->dev, "Registered RPMh clocks\n"); 930 931 return 0; 932 } 933 934 static const struct of_device_id clk_rpmh_match_table[] = { 935 { .compatible = "qcom,qcs615-rpmh-clk", .data = &clk_rpmh_qcs615}, 936 { .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000}, 937 { .compatible = "qcom,sa8775p-rpmh-clk", .data = &clk_rpmh_sa8775p}, 938 { .compatible = "qcom,sar2130p-rpmh-clk", .data = &clk_rpmh_sar2130p}, 939 { .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180}, 940 { .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280}, 941 { .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x}, 942 { .compatible = "qcom,sc8280xp-rpmh-clk", .data = &clk_rpmh_sc8280xp}, 943 { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845}, 944 { .compatible = "qcom,sdm670-rpmh-clk", .data = &clk_rpmh_sdm670}, 945 { .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55}, 946 { .compatible = "qcom,sdx65-rpmh-clk", .data = &clk_rpmh_sdx65}, 947 { .compatible = "qcom,sdx75-rpmh-clk", .data = &clk_rpmh_sdx75}, 948 { .compatible = "qcom,sm4450-rpmh-clk", .data = &clk_rpmh_sm4450}, 949 { .compatible = "qcom,sm6350-rpmh-clk", .data = &clk_rpmh_sm6350}, 950 { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150}, 951 { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250}, 952 { .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350}, 953 { .compatible = "qcom,sm8450-rpmh-clk", .data = &clk_rpmh_sm8450}, 954 { .compatible = "qcom,sm8550-rpmh-clk", .data = &clk_rpmh_sm8550}, 955 { .compatible = "qcom,sm8650-rpmh-clk", .data = &clk_rpmh_sm8650}, 956 { .compatible = "qcom,sm8750-rpmh-clk", .data = &clk_rpmh_sm8750}, 957 { .compatible = "qcom,x1e80100-rpmh-clk", .data = &clk_rpmh_x1e80100}, 958 { } 959 }; 960 MODULE_DEVICE_TABLE(of, clk_rpmh_match_table); 961 962 static struct platform_driver clk_rpmh_driver = { 963 .probe = clk_rpmh_probe, 964 .driver = { 965 .name = "clk-rpmh", 966 .of_match_table = clk_rpmh_match_table, 967 }, 968 }; 969 970 static int __init clk_rpmh_init(void) 971 { 972 return platform_driver_register(&clk_rpmh_driver); 973 } 974 core_initcall(clk_rpmh_init); 975 976 static void __exit clk_rpmh_exit(void) 977 { 978 platform_driver_unregister(&clk_rpmh_driver); 979 } 980 module_exit(clk_rpmh_exit); 981 982 MODULE_DESCRIPTION("QCOM RPMh Clock Driver"); 983 MODULE_LICENSE("GPL v2"); 984