1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/err.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 #include <soc/qcom/cmd-db.h> 14 #include <soc/qcom/rpmh.h> 15 16 #include <dt-bindings/clock/qcom,rpmh.h> 17 18 #define CLK_RPMH_ARC_EN_OFFSET 0 19 #define CLK_RPMH_VRM_EN_OFFSET 4 20 21 #define BCM_TCS_CMD_COMMIT_MASK 0x40000000 22 #define BCM_TCS_CMD_VALID_SHIFT 29 23 #define BCM_TCS_CMD_VOTE_MASK 0x3fff 24 #define BCM_TCS_CMD_VOTE_SHIFT 0 25 26 #define BCM_TCS_CMD(valid, vote) \ 27 (BCM_TCS_CMD_COMMIT_MASK | \ 28 ((valid) << BCM_TCS_CMD_VALID_SHIFT) | \ 29 ((vote & BCM_TCS_CMD_VOTE_MASK) \ 30 << BCM_TCS_CMD_VOTE_SHIFT)) 31 32 /** 33 * struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager(BCM) 34 * @unit: divisor used to convert Hz value to an RPMh msg 35 * @width: multiplier used to convert Hz value to an RPMh msg 36 * @vcd: virtual clock domain that this bcm belongs to 37 * @reserved: reserved to pad the struct 38 */ 39 struct bcm_db { 40 __le32 unit; 41 __le16 width; 42 u8 vcd; 43 u8 reserved; 44 }; 45 46 /** 47 * struct clk_rpmh - individual rpmh clock data structure 48 * @hw: handle between common and hardware-specific interfaces 49 * @res_name: resource name for the rpmh clock 50 * @div: clock divider to compute the clock rate 51 * @res_addr: base address of the rpmh resource within the RPMh 52 * @res_on_val: rpmh clock enable value 53 * @state: rpmh clock requested state 54 * @aggr_state: rpmh clock aggregated state 55 * @last_sent_aggr_state: rpmh clock last aggr state sent to RPMh 56 * @valid_state_mask: mask to determine the state of the rpmh clock 57 * @unit: divisor to convert rate to rpmh msg in magnitudes of Khz 58 * @dev: device to which it is attached 59 * @peer: pointer to the clock rpmh sibling 60 */ 61 struct clk_rpmh { 62 struct clk_hw hw; 63 const char *res_name; 64 u8 div; 65 u32 res_addr; 66 u32 res_on_val; 67 u32 state; 68 u32 aggr_state; 69 u32 last_sent_aggr_state; 70 u32 valid_state_mask; 71 u32 unit; 72 struct device *dev; 73 struct clk_rpmh *peer; 74 }; 75 76 struct clk_rpmh_desc { 77 struct clk_hw **clks; 78 size_t num_clks; 79 }; 80 81 static DEFINE_MUTEX(rpmh_clk_lock); 82 83 #define __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \ 84 _res_en_offset, _res_on, _div) \ 85 static struct clk_rpmh _platform##_##_name_active; \ 86 static struct clk_rpmh _platform##_##_name = { \ 87 .res_name = _res_name, \ 88 .res_addr = _res_en_offset, \ 89 .res_on_val = _res_on, \ 90 .div = _div, \ 91 .peer = &_platform##_##_name_active, \ 92 .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \ 93 BIT(RPMH_ACTIVE_ONLY_STATE) | \ 94 BIT(RPMH_SLEEP_STATE)), \ 95 .hw.init = &(struct clk_init_data){ \ 96 .ops = &clk_rpmh_ops, \ 97 .name = #_name, \ 98 .parent_names = (const char *[]){ "xo_board" }, \ 99 .num_parents = 1, \ 100 }, \ 101 }; \ 102 static struct clk_rpmh _platform##_##_name_active = { \ 103 .res_name = _res_name, \ 104 .res_addr = _res_en_offset, \ 105 .res_on_val = _res_on, \ 106 .div = _div, \ 107 .peer = &_platform##_##_name, \ 108 .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \ 109 BIT(RPMH_ACTIVE_ONLY_STATE)), \ 110 .hw.init = &(struct clk_init_data){ \ 111 .ops = &clk_rpmh_ops, \ 112 .name = #_name_active, \ 113 .parent_names = (const char *[]){ "xo_board" }, \ 114 .num_parents = 1, \ 115 }, \ 116 } 117 118 #define DEFINE_CLK_RPMH_ARC(_platform, _name, _name_active, _res_name, \ 119 _res_on, _div) \ 120 __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \ 121 CLK_RPMH_ARC_EN_OFFSET, _res_on, _div) 122 123 #define DEFINE_CLK_RPMH_VRM(_platform, _name, _name_active, _res_name, \ 124 _div) \ 125 __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \ 126 CLK_RPMH_VRM_EN_OFFSET, 1, _div) 127 128 #define DEFINE_CLK_RPMH_BCM(_platform, _name, _res_name) \ 129 static struct clk_rpmh _platform##_##_name = { \ 130 .res_name = _res_name, \ 131 .valid_state_mask = BIT(RPMH_ACTIVE_ONLY_STATE), \ 132 .div = 1, \ 133 .hw.init = &(struct clk_init_data){ \ 134 .ops = &clk_rpmh_bcm_ops, \ 135 .name = #_name, \ 136 }, \ 137 } 138 139 static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw) 140 { 141 return container_of(_hw, struct clk_rpmh, hw); 142 } 143 144 static inline bool has_state_changed(struct clk_rpmh *c, u32 state) 145 { 146 return (c->last_sent_aggr_state & BIT(state)) 147 != (c->aggr_state & BIT(state)); 148 } 149 150 static int clk_rpmh_send_aggregate_command(struct clk_rpmh *c) 151 { 152 struct tcs_cmd cmd = { 0 }; 153 u32 cmd_state, on_val; 154 enum rpmh_state state = RPMH_SLEEP_STATE; 155 int ret; 156 157 cmd.addr = c->res_addr; 158 cmd_state = c->aggr_state; 159 on_val = c->res_on_val; 160 161 for (; state <= RPMH_ACTIVE_ONLY_STATE; state++) { 162 if (has_state_changed(c, state)) { 163 if (cmd_state & BIT(state)) 164 cmd.data = on_val; 165 166 ret = rpmh_write_async(c->dev, state, &cmd, 1); 167 if (ret) { 168 dev_err(c->dev, "set %s state of %s failed: (%d)\n", 169 !state ? "sleep" : 170 state == RPMH_WAKE_ONLY_STATE ? 171 "wake" : "active", c->res_name, ret); 172 return ret; 173 } 174 } 175 } 176 177 c->last_sent_aggr_state = c->aggr_state; 178 c->peer->last_sent_aggr_state = c->last_sent_aggr_state; 179 180 return 0; 181 } 182 183 /* 184 * Update state and aggregate state values based on enable value. 185 */ 186 static int clk_rpmh_aggregate_state_send_command(struct clk_rpmh *c, 187 bool enable) 188 { 189 int ret; 190 191 /* Nothing required to be done if already off or on */ 192 if (enable == c->state) 193 return 0; 194 195 c->state = enable ? c->valid_state_mask : 0; 196 c->aggr_state = c->state | c->peer->state; 197 c->peer->aggr_state = c->aggr_state; 198 199 ret = clk_rpmh_send_aggregate_command(c); 200 if (!ret) 201 return 0; 202 203 if (ret && enable) 204 c->state = 0; 205 else if (ret) 206 c->state = c->valid_state_mask; 207 208 WARN(1, "clk: %s failed to %s\n", c->res_name, 209 enable ? "enable" : "disable"); 210 return ret; 211 } 212 213 static int clk_rpmh_prepare(struct clk_hw *hw) 214 { 215 struct clk_rpmh *c = to_clk_rpmh(hw); 216 int ret = 0; 217 218 mutex_lock(&rpmh_clk_lock); 219 ret = clk_rpmh_aggregate_state_send_command(c, true); 220 mutex_unlock(&rpmh_clk_lock); 221 222 return ret; 223 }; 224 225 static void clk_rpmh_unprepare(struct clk_hw *hw) 226 { 227 struct clk_rpmh *c = to_clk_rpmh(hw); 228 229 mutex_lock(&rpmh_clk_lock); 230 clk_rpmh_aggregate_state_send_command(c, false); 231 mutex_unlock(&rpmh_clk_lock); 232 }; 233 234 static unsigned long clk_rpmh_recalc_rate(struct clk_hw *hw, 235 unsigned long prate) 236 { 237 struct clk_rpmh *r = to_clk_rpmh(hw); 238 239 /* 240 * RPMh clocks have a fixed rate. Return static rate. 241 */ 242 return prate / r->div; 243 } 244 245 static const struct clk_ops clk_rpmh_ops = { 246 .prepare = clk_rpmh_prepare, 247 .unprepare = clk_rpmh_unprepare, 248 .recalc_rate = clk_rpmh_recalc_rate, 249 }; 250 251 static int clk_rpmh_bcm_send_cmd(struct clk_rpmh *c, bool enable) 252 { 253 struct tcs_cmd cmd = { 0 }; 254 u32 cmd_state; 255 int ret; 256 257 mutex_lock(&rpmh_clk_lock); 258 259 cmd_state = 0; 260 if (enable) { 261 cmd_state = 1; 262 if (c->aggr_state) 263 cmd_state = c->aggr_state; 264 } 265 266 if (c->last_sent_aggr_state == cmd_state) { 267 mutex_unlock(&rpmh_clk_lock); 268 return 0; 269 } 270 271 cmd.addr = c->res_addr; 272 cmd.data = BCM_TCS_CMD(enable, cmd_state); 273 274 ret = rpmh_write_async(c->dev, RPMH_ACTIVE_ONLY_STATE, &cmd, 1); 275 if (ret) { 276 dev_err(c->dev, "set active state of %s failed: (%d)\n", 277 c->res_name, ret); 278 mutex_unlock(&rpmh_clk_lock); 279 return ret; 280 } 281 282 c->last_sent_aggr_state = cmd_state; 283 284 mutex_unlock(&rpmh_clk_lock); 285 286 return 0; 287 } 288 289 static int clk_rpmh_bcm_prepare(struct clk_hw *hw) 290 { 291 struct clk_rpmh *c = to_clk_rpmh(hw); 292 293 return clk_rpmh_bcm_send_cmd(c, true); 294 }; 295 296 static void clk_rpmh_bcm_unprepare(struct clk_hw *hw) 297 { 298 struct clk_rpmh *c = to_clk_rpmh(hw); 299 300 clk_rpmh_bcm_send_cmd(c, false); 301 }; 302 303 static int clk_rpmh_bcm_set_rate(struct clk_hw *hw, unsigned long rate, 304 unsigned long parent_rate) 305 { 306 struct clk_rpmh *c = to_clk_rpmh(hw); 307 308 c->aggr_state = rate / c->unit; 309 /* 310 * Since any non-zero value sent to hw would result in enabling the 311 * clock, only send the value if the clock has already been prepared. 312 */ 313 if (clk_hw_is_prepared(hw)) 314 clk_rpmh_bcm_send_cmd(c, true); 315 316 return 0; 317 }; 318 319 static long clk_rpmh_round_rate(struct clk_hw *hw, unsigned long rate, 320 unsigned long *parent_rate) 321 { 322 return rate; 323 } 324 325 static unsigned long clk_rpmh_bcm_recalc_rate(struct clk_hw *hw, 326 unsigned long prate) 327 { 328 struct clk_rpmh *c = to_clk_rpmh(hw); 329 330 return c->aggr_state * c->unit; 331 } 332 333 static const struct clk_ops clk_rpmh_bcm_ops = { 334 .prepare = clk_rpmh_bcm_prepare, 335 .unprepare = clk_rpmh_bcm_unprepare, 336 .set_rate = clk_rpmh_bcm_set_rate, 337 .round_rate = clk_rpmh_round_rate, 338 .recalc_rate = clk_rpmh_bcm_recalc_rate, 339 }; 340 341 /* Resource name must match resource id present in cmd-db. */ 342 DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2); 343 DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2); 344 DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2); 345 DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", 1); 346 DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1); 347 DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1); 348 DEFINE_CLK_RPMH_BCM(sdm845, ipa, "IP0"); 349 350 static struct clk_hw *sdm845_rpmh_clocks[] = { 351 [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, 352 [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, 353 [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, 354 [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, 355 [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, 356 [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, 357 [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, 358 [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, 359 [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, 360 [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, 361 [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, 362 [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, 363 [RPMH_IPA_CLK] = &sdm845_ipa.hw, 364 }; 365 366 static const struct clk_rpmh_desc clk_rpmh_sdm845 = { 367 .clks = sdm845_rpmh_clocks, 368 .num_clks = ARRAY_SIZE(sdm845_rpmh_clocks), 369 }; 370 371 static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, 372 void *data) 373 { 374 struct clk_rpmh_desc *rpmh = data; 375 unsigned int idx = clkspec->args[0]; 376 377 if (idx >= rpmh->num_clks) { 378 pr_err("%s: invalid index %u\n", __func__, idx); 379 return ERR_PTR(-EINVAL); 380 } 381 382 return rpmh->clks[idx]; 383 } 384 385 static int clk_rpmh_probe(struct platform_device *pdev) 386 { 387 struct clk_hw **hw_clks; 388 struct clk_rpmh *rpmh_clk; 389 const struct clk_rpmh_desc *desc; 390 int ret, i; 391 392 desc = of_device_get_match_data(&pdev->dev); 393 if (!desc) 394 return -ENODEV; 395 396 hw_clks = desc->clks; 397 398 for (i = 0; i < desc->num_clks; i++) { 399 u32 res_addr; 400 size_t aux_data_len; 401 const struct bcm_db *data; 402 403 rpmh_clk = to_clk_rpmh(hw_clks[i]); 404 res_addr = cmd_db_read_addr(rpmh_clk->res_name); 405 if (!res_addr) { 406 dev_err(&pdev->dev, "missing RPMh resource address for %s\n", 407 rpmh_clk->res_name); 408 return -ENODEV; 409 } 410 411 data = cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len); 412 if (IS_ERR(data)) { 413 ret = PTR_ERR(data); 414 dev_err(&pdev->dev, 415 "error reading RPMh aux data for %s (%d)\n", 416 rpmh_clk->res_name, ret); 417 return ret; 418 } 419 420 /* Convert unit from Khz to Hz */ 421 if (aux_data_len == sizeof(*data)) 422 rpmh_clk->unit = le32_to_cpu(data->unit) * 1000ULL; 423 424 rpmh_clk->res_addr += res_addr; 425 rpmh_clk->dev = &pdev->dev; 426 427 ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]); 428 if (ret) { 429 dev_err(&pdev->dev, "failed to register %s\n", 430 hw_clks[i]->init->name); 431 return ret; 432 } 433 } 434 435 /* typecast to silence compiler warning */ 436 ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_rpmh_hw_get, 437 (void *)desc); 438 if (ret) { 439 dev_err(&pdev->dev, "Failed to add clock provider\n"); 440 return ret; 441 } 442 443 dev_dbg(&pdev->dev, "Registered RPMh clocks\n"); 444 445 return 0; 446 } 447 448 static const struct of_device_id clk_rpmh_match_table[] = { 449 { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845}, 450 { } 451 }; 452 MODULE_DEVICE_TABLE(of, clk_rpmh_match_table); 453 454 static struct platform_driver clk_rpmh_driver = { 455 .probe = clk_rpmh_probe, 456 .driver = { 457 .name = "clk-rpmh", 458 .of_match_table = clk_rpmh_match_table, 459 }, 460 }; 461 462 static int __init clk_rpmh_init(void) 463 { 464 return platform_driver_register(&clk_rpmh_driver); 465 } 466 subsys_initcall(clk_rpmh_init); 467 468 static void __exit clk_rpmh_exit(void) 469 { 470 platform_driver_unregister(&clk_rpmh_driver); 471 } 472 module_exit(clk_rpmh_exit); 473 474 MODULE_DESCRIPTION("QCOM RPMh Clock Driver"); 475 MODULE_LICENSE("GPL v2"); 476