1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/err.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/platform_device.h> 12 #include <soc/qcom/cmd-db.h> 13 #include <soc/qcom/rpmh.h> 14 #include <soc/qcom/tcs.h> 15 16 #include <dt-bindings/clock/qcom,rpmh.h> 17 18 #define CLK_RPMH_ARC_EN_OFFSET 0 19 #define CLK_RPMH_VRM_EN_OFFSET 4 20 21 /** 22 * struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager(BCM) 23 * @unit: divisor used to convert Hz value to an RPMh msg 24 * @width: multiplier used to convert Hz value to an RPMh msg 25 * @vcd: virtual clock domain that this bcm belongs to 26 * @reserved: reserved to pad the struct 27 */ 28 struct bcm_db { 29 __le32 unit; 30 __le16 width; 31 u8 vcd; 32 u8 reserved; 33 }; 34 35 /** 36 * struct clk_rpmh - individual rpmh clock data structure 37 * @hw: handle between common and hardware-specific interfaces 38 * @res_name: resource name for the rpmh clock 39 * @div: clock divider to compute the clock rate 40 * @res_addr: base address of the rpmh resource within the RPMh 41 * @res_on_val: rpmh clock enable value 42 * @state: rpmh clock requested state 43 * @aggr_state: rpmh clock aggregated state 44 * @last_sent_aggr_state: rpmh clock last aggr state sent to RPMh 45 * @valid_state_mask: mask to determine the state of the rpmh clock 46 * @unit: divisor to convert rate to rpmh msg in magnitudes of Khz 47 * @dev: device to which it is attached 48 * @peer: pointer to the clock rpmh sibling 49 */ 50 struct clk_rpmh { 51 struct clk_hw hw; 52 const char *res_name; 53 u8 div; 54 u32 res_addr; 55 u32 res_on_val; 56 u32 state; 57 u32 aggr_state; 58 u32 last_sent_aggr_state; 59 u32 valid_state_mask; 60 u32 unit; 61 struct device *dev; 62 struct clk_rpmh *peer; 63 }; 64 65 struct clk_rpmh_desc { 66 struct clk_hw **clks; 67 size_t num_clks; 68 }; 69 70 static DEFINE_MUTEX(rpmh_clk_lock); 71 72 #define __DEFINE_CLK_RPMH(_name, _clk_name, _res_name, \ 73 _res_en_offset, _res_on, _div) \ 74 static struct clk_rpmh clk_rpmh_##_clk_name##_ao; \ 75 static struct clk_rpmh clk_rpmh_##_clk_name = { \ 76 .res_name = _res_name, \ 77 .res_addr = _res_en_offset, \ 78 .res_on_val = _res_on, \ 79 .div = _div, \ 80 .peer = &clk_rpmh_##_clk_name##_ao, \ 81 .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \ 82 BIT(RPMH_ACTIVE_ONLY_STATE) | \ 83 BIT(RPMH_SLEEP_STATE)), \ 84 .hw.init = &(struct clk_init_data){ \ 85 .ops = &clk_rpmh_ops, \ 86 .name = #_name, \ 87 .parent_data = &(const struct clk_parent_data){ \ 88 .fw_name = "xo", \ 89 .name = "xo_board", \ 90 }, \ 91 .num_parents = 1, \ 92 }, \ 93 }; \ 94 static struct clk_rpmh clk_rpmh_##_clk_name##_ao= { \ 95 .res_name = _res_name, \ 96 .res_addr = _res_en_offset, \ 97 .res_on_val = _res_on, \ 98 .div = _div, \ 99 .peer = &clk_rpmh_##_clk_name, \ 100 .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \ 101 BIT(RPMH_ACTIVE_ONLY_STATE)), \ 102 .hw.init = &(struct clk_init_data){ \ 103 .ops = &clk_rpmh_ops, \ 104 .name = #_name "_ao", \ 105 .parent_data = &(const struct clk_parent_data){ \ 106 .fw_name = "xo", \ 107 .name = "xo_board", \ 108 }, \ 109 .num_parents = 1, \ 110 }, \ 111 } 112 113 #define DEFINE_CLK_RPMH_ARC(_name, _res_name, _res_on, _div) \ 114 __DEFINE_CLK_RPMH(_name, _name##_##div##_div, _res_name, \ 115 CLK_RPMH_ARC_EN_OFFSET, _res_on, _div) 116 117 #define DEFINE_CLK_RPMH_VRM(_name, _suffix, _res_name, _div) \ 118 __DEFINE_CLK_RPMH(_name, _name##_suffix, _res_name, \ 119 CLK_RPMH_VRM_EN_OFFSET, 1, _div) 120 121 #define DEFINE_CLK_RPMH_BCM(_name, _res_name) \ 122 static struct clk_rpmh clk_rpmh_##_name = { \ 123 .res_name = _res_name, \ 124 .valid_state_mask = BIT(RPMH_ACTIVE_ONLY_STATE), \ 125 .div = 1, \ 126 .hw.init = &(struct clk_init_data){ \ 127 .ops = &clk_rpmh_bcm_ops, \ 128 .name = #_name, \ 129 }, \ 130 } 131 132 static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw) 133 { 134 return container_of(_hw, struct clk_rpmh, hw); 135 } 136 137 static inline bool has_state_changed(struct clk_rpmh *c, u32 state) 138 { 139 return (c->last_sent_aggr_state & BIT(state)) 140 != (c->aggr_state & BIT(state)); 141 } 142 143 static int clk_rpmh_send(struct clk_rpmh *c, enum rpmh_state state, 144 struct tcs_cmd *cmd, bool wait) 145 { 146 if (wait) 147 return rpmh_write(c->dev, state, cmd, 1); 148 149 return rpmh_write_async(c->dev, state, cmd, 1); 150 } 151 152 static int clk_rpmh_send_aggregate_command(struct clk_rpmh *c) 153 { 154 struct tcs_cmd cmd = { 0 }; 155 u32 cmd_state, on_val; 156 enum rpmh_state state = RPMH_SLEEP_STATE; 157 int ret; 158 bool wait; 159 160 cmd.addr = c->res_addr; 161 cmd_state = c->aggr_state; 162 on_val = c->res_on_val; 163 164 for (; state <= RPMH_ACTIVE_ONLY_STATE; state++) { 165 if (has_state_changed(c, state)) { 166 if (cmd_state & BIT(state)) 167 cmd.data = on_val; 168 169 wait = cmd_state && state == RPMH_ACTIVE_ONLY_STATE; 170 ret = clk_rpmh_send(c, state, &cmd, wait); 171 if (ret) { 172 dev_err(c->dev, "set %s state of %s failed: (%d)\n", 173 !state ? "sleep" : 174 state == RPMH_WAKE_ONLY_STATE ? 175 "wake" : "active", c->res_name, ret); 176 return ret; 177 } 178 } 179 } 180 181 c->last_sent_aggr_state = c->aggr_state; 182 c->peer->last_sent_aggr_state = c->last_sent_aggr_state; 183 184 return 0; 185 } 186 187 /* 188 * Update state and aggregate state values based on enable value. 189 */ 190 static int clk_rpmh_aggregate_state_send_command(struct clk_rpmh *c, 191 bool enable) 192 { 193 int ret; 194 195 c->state = enable ? c->valid_state_mask : 0; 196 c->aggr_state = c->state | c->peer->state; 197 c->peer->aggr_state = c->aggr_state; 198 199 ret = clk_rpmh_send_aggregate_command(c); 200 if (!ret) 201 return 0; 202 203 if (ret && enable) 204 c->state = 0; 205 else if (ret) 206 c->state = c->valid_state_mask; 207 208 WARN(1, "clk: %s failed to %s\n", c->res_name, 209 enable ? "enable" : "disable"); 210 return ret; 211 } 212 213 static int clk_rpmh_prepare(struct clk_hw *hw) 214 { 215 struct clk_rpmh *c = to_clk_rpmh(hw); 216 int ret = 0; 217 218 mutex_lock(&rpmh_clk_lock); 219 ret = clk_rpmh_aggregate_state_send_command(c, true); 220 mutex_unlock(&rpmh_clk_lock); 221 222 return ret; 223 } 224 225 static void clk_rpmh_unprepare(struct clk_hw *hw) 226 { 227 struct clk_rpmh *c = to_clk_rpmh(hw); 228 229 mutex_lock(&rpmh_clk_lock); 230 clk_rpmh_aggregate_state_send_command(c, false); 231 mutex_unlock(&rpmh_clk_lock); 232 }; 233 234 static unsigned long clk_rpmh_recalc_rate(struct clk_hw *hw, 235 unsigned long prate) 236 { 237 struct clk_rpmh *r = to_clk_rpmh(hw); 238 239 /* 240 * RPMh clocks have a fixed rate. Return static rate. 241 */ 242 return prate / r->div; 243 } 244 245 static const struct clk_ops clk_rpmh_ops = { 246 .prepare = clk_rpmh_prepare, 247 .unprepare = clk_rpmh_unprepare, 248 .recalc_rate = clk_rpmh_recalc_rate, 249 }; 250 251 static int clk_rpmh_bcm_send_cmd(struct clk_rpmh *c, bool enable) 252 { 253 struct tcs_cmd cmd = { 0 }; 254 u32 cmd_state; 255 int ret = 0; 256 257 mutex_lock(&rpmh_clk_lock); 258 if (enable) { 259 cmd_state = 1; 260 if (c->aggr_state) 261 cmd_state = c->aggr_state; 262 } else { 263 cmd_state = 0; 264 } 265 266 cmd_state = min(cmd_state, BCM_TCS_CMD_VOTE_MASK); 267 268 if (c->last_sent_aggr_state != cmd_state) { 269 cmd.addr = c->res_addr; 270 cmd.data = BCM_TCS_CMD(1, enable, 0, cmd_state); 271 272 /* 273 * Send only an active only state request. RPMh continues to 274 * use the active state when we're in sleep/wake state as long 275 * as the sleep/wake state has never been set. 276 */ 277 ret = clk_rpmh_send(c, RPMH_ACTIVE_ONLY_STATE, &cmd, enable); 278 if (ret) { 279 dev_err(c->dev, "set active state of %s failed: (%d)\n", 280 c->res_name, ret); 281 } else { 282 c->last_sent_aggr_state = cmd_state; 283 } 284 } 285 286 mutex_unlock(&rpmh_clk_lock); 287 288 return ret; 289 } 290 291 static int clk_rpmh_bcm_prepare(struct clk_hw *hw) 292 { 293 struct clk_rpmh *c = to_clk_rpmh(hw); 294 295 return clk_rpmh_bcm_send_cmd(c, true); 296 } 297 298 static void clk_rpmh_bcm_unprepare(struct clk_hw *hw) 299 { 300 struct clk_rpmh *c = to_clk_rpmh(hw); 301 302 clk_rpmh_bcm_send_cmd(c, false); 303 } 304 305 static int clk_rpmh_bcm_set_rate(struct clk_hw *hw, unsigned long rate, 306 unsigned long parent_rate) 307 { 308 struct clk_rpmh *c = to_clk_rpmh(hw); 309 310 c->aggr_state = rate / c->unit; 311 /* 312 * Since any non-zero value sent to hw would result in enabling the 313 * clock, only send the value if the clock has already been prepared. 314 */ 315 if (clk_hw_is_prepared(hw)) 316 clk_rpmh_bcm_send_cmd(c, true); 317 318 return 0; 319 } 320 321 static long clk_rpmh_round_rate(struct clk_hw *hw, unsigned long rate, 322 unsigned long *parent_rate) 323 { 324 return rate; 325 } 326 327 static unsigned long clk_rpmh_bcm_recalc_rate(struct clk_hw *hw, 328 unsigned long prate) 329 { 330 struct clk_rpmh *c = to_clk_rpmh(hw); 331 332 return c->aggr_state * c->unit; 333 } 334 335 static const struct clk_ops clk_rpmh_bcm_ops = { 336 .prepare = clk_rpmh_bcm_prepare, 337 .unprepare = clk_rpmh_bcm_unprepare, 338 .set_rate = clk_rpmh_bcm_set_rate, 339 .round_rate = clk_rpmh_round_rate, 340 .recalc_rate = clk_rpmh_bcm_recalc_rate, 341 }; 342 343 /* Resource name must match resource id present in cmd-db */ 344 DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 1); 345 DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 2); 346 DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 4); 347 DEFINE_CLK_RPMH_ARC(qlink, "qphy.lvl", 0x1, 4); 348 349 DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a2, "lnbclka1", 2); 350 DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a2, "lnbclka2", 2); 351 DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a2, "lnbclka3", 2); 352 353 DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a4, "lnbclka1", 4); 354 DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a4, "lnbclka2", 4); 355 DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a4, "lnbclka3", 4); 356 357 DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _g4, "lnbclkg2", 4); 358 DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _g4, "lnbclkg3", 4); 359 360 DEFINE_CLK_RPMH_VRM(rf_clk1, _a, "rfclka1", 1); 361 DEFINE_CLK_RPMH_VRM(rf_clk2, _a, "rfclka2", 1); 362 DEFINE_CLK_RPMH_VRM(rf_clk3, _a, "rfclka3", 1); 363 DEFINE_CLK_RPMH_VRM(rf_clk4, _a, "rfclka4", 1); 364 DEFINE_CLK_RPMH_VRM(rf_clk5, _a, "rfclka5", 1); 365 366 DEFINE_CLK_RPMH_VRM(rf_clk1, _d, "rfclkd1", 1); 367 DEFINE_CLK_RPMH_VRM(rf_clk2, _d, "rfclkd2", 1); 368 DEFINE_CLK_RPMH_VRM(rf_clk3, _d, "rfclkd3", 1); 369 DEFINE_CLK_RPMH_VRM(rf_clk4, _d, "rfclkd4", 1); 370 371 DEFINE_CLK_RPMH_VRM(clk1, _a1, "clka1", 1); 372 DEFINE_CLK_RPMH_VRM(clk2, _a1, "clka2", 1); 373 DEFINE_CLK_RPMH_VRM(clk3, _a1, "clka3", 1); 374 DEFINE_CLK_RPMH_VRM(clk4, _a1, "clka4", 1); 375 DEFINE_CLK_RPMH_VRM(clk5, _a1, "clka5", 1); 376 377 DEFINE_CLK_RPMH_VRM(clk3, _a2, "clka3", 2); 378 DEFINE_CLK_RPMH_VRM(clk4, _a2, "clka4", 2); 379 DEFINE_CLK_RPMH_VRM(clk5, _a2, "clka5", 2); 380 DEFINE_CLK_RPMH_VRM(clk6, _a2, "clka6", 2); 381 DEFINE_CLK_RPMH_VRM(clk7, _a2, "clka7", 2); 382 DEFINE_CLK_RPMH_VRM(clk8, _a2, "clka8", 2); 383 384 DEFINE_CLK_RPMH_VRM(div_clk1, _div2, "divclka1", 2); 385 386 DEFINE_CLK_RPMH_BCM(ce, "CE0"); 387 DEFINE_CLK_RPMH_BCM(hwkm, "HK0"); 388 DEFINE_CLK_RPMH_BCM(ipa, "IP0"); 389 DEFINE_CLK_RPMH_BCM(pka, "PKA0"); 390 DEFINE_CLK_RPMH_BCM(qpic_clk, "QP0"); 391 392 static struct clk_hw *sdm845_rpmh_clocks[] = { 393 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 394 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 395 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 396 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 397 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 398 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 399 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 400 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 401 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 402 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 403 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 404 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 405 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 406 [RPMH_CE_CLK] = &clk_rpmh_ce.hw, 407 }; 408 409 static const struct clk_rpmh_desc clk_rpmh_sdm845 = { 410 .clks = sdm845_rpmh_clocks, 411 .num_clks = ARRAY_SIZE(sdm845_rpmh_clocks), 412 }; 413 414 static struct clk_hw *sa8775p_rpmh_clocks[] = { 415 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 416 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 417 [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2.hw, 418 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 419 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a4_ao.hw, 420 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 421 [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, 422 [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, 423 }; 424 425 static const struct clk_rpmh_desc clk_rpmh_sa8775p = { 426 .clks = sa8775p_rpmh_clocks, 427 .num_clks = ARRAY_SIZE(sa8775p_rpmh_clocks), 428 }; 429 430 static struct clk_hw *sdm670_rpmh_clocks[] = { 431 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 432 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 433 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 434 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 435 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 436 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 437 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 438 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 439 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 440 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 441 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 442 [RPMH_CE_CLK] = &clk_rpmh_ce.hw, 443 }; 444 445 static const struct clk_rpmh_desc clk_rpmh_sdm670 = { 446 .clks = sdm670_rpmh_clocks, 447 .num_clks = ARRAY_SIZE(sdm670_rpmh_clocks), 448 }; 449 450 static struct clk_hw *sdx55_rpmh_clocks[] = { 451 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 452 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 453 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_d.hw, 454 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_d_ao.hw, 455 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_d.hw, 456 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_d_ao.hw, 457 [RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw, 458 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 459 }; 460 461 static const struct clk_rpmh_desc clk_rpmh_sdx55 = { 462 .clks = sdx55_rpmh_clocks, 463 .num_clks = ARRAY_SIZE(sdx55_rpmh_clocks), 464 }; 465 466 static struct clk_hw *sm8150_rpmh_clocks[] = { 467 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 468 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 469 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 470 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 471 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 472 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 473 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 474 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 475 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 476 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 477 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 478 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 479 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 480 }; 481 482 static const struct clk_rpmh_desc clk_rpmh_sm8150 = { 483 .clks = sm8150_rpmh_clocks, 484 .num_clks = ARRAY_SIZE(sm8150_rpmh_clocks), 485 }; 486 487 static struct clk_hw *sc7180_rpmh_clocks[] = { 488 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 489 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 490 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 491 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 492 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 493 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 494 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 495 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 496 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 497 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 498 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 499 }; 500 501 static const struct clk_rpmh_desc clk_rpmh_sc7180 = { 502 .clks = sc7180_rpmh_clocks, 503 .num_clks = ARRAY_SIZE(sc7180_rpmh_clocks), 504 }; 505 506 static struct clk_hw *sc8180x_rpmh_clocks[] = { 507 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 508 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 509 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 510 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 511 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 512 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 513 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_d.hw, 514 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_d_ao.hw, 515 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_d.hw, 516 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_d_ao.hw, 517 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_d.hw, 518 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_d_ao.hw, 519 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 520 }; 521 522 static const struct clk_rpmh_desc clk_rpmh_sc8180x = { 523 .clks = sc8180x_rpmh_clocks, 524 .num_clks = ARRAY_SIZE(sc8180x_rpmh_clocks), 525 }; 526 527 static struct clk_hw *sm8250_rpmh_clocks[] = { 528 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 529 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 530 [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2.hw, 531 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a2_ao.hw, 532 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 533 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 534 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 535 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 536 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 537 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 538 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 539 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 540 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 541 }; 542 543 static const struct clk_rpmh_desc clk_rpmh_sm8250 = { 544 .clks = sm8250_rpmh_clocks, 545 .num_clks = ARRAY_SIZE(sm8250_rpmh_clocks), 546 }; 547 548 static struct clk_hw *sm8350_rpmh_clocks[] = { 549 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 550 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 551 [RPMH_DIV_CLK1] = &clk_rpmh_div_clk1_div2.hw, 552 [RPMH_DIV_CLK1_A] = &clk_rpmh_div_clk1_div2_ao.hw, 553 [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2.hw, 554 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a2_ao.hw, 555 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 556 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 557 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 558 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 559 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 560 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 561 [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw, 562 [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw, 563 [RPMH_RF_CLK5] = &clk_rpmh_rf_clk5_a.hw, 564 [RPMH_RF_CLK5_A] = &clk_rpmh_rf_clk5_a_ao.hw, 565 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 566 [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, 567 [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, 568 }; 569 570 static const struct clk_rpmh_desc clk_rpmh_sm8350 = { 571 .clks = sm8350_rpmh_clocks, 572 .num_clks = ARRAY_SIZE(sm8350_rpmh_clocks), 573 }; 574 575 static struct clk_hw *sc8280xp_rpmh_clocks[] = { 576 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 577 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 578 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 579 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 580 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 581 [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, 582 [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, 583 }; 584 585 static const struct clk_rpmh_desc clk_rpmh_sc8280xp = { 586 .clks = sc8280xp_rpmh_clocks, 587 .num_clks = ARRAY_SIZE(sc8280xp_rpmh_clocks), 588 }; 589 590 static struct clk_hw *sm8450_rpmh_clocks[] = { 591 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, 592 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, 593 [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a4.hw, 594 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a4_ao.hw, 595 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a4.hw, 596 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a4_ao.hw, 597 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 598 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 599 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 600 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 601 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 602 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 603 [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw, 604 [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw, 605 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 606 }; 607 608 static const struct clk_rpmh_desc clk_rpmh_sm8450 = { 609 .clks = sm8450_rpmh_clocks, 610 .num_clks = ARRAY_SIZE(sm8450_rpmh_clocks), 611 }; 612 613 static struct clk_hw *sm8550_rpmh_clocks[] = { 614 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 615 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 616 [RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw, 617 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw, 618 [RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a2.hw, 619 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a2_ao.hw, 620 [RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw, 621 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw, 622 [RPMH_RF_CLK1] = &clk_rpmh_clk1_a1.hw, 623 [RPMH_RF_CLK1_A] = &clk_rpmh_clk1_a1_ao.hw, 624 [RPMH_RF_CLK2] = &clk_rpmh_clk2_a1.hw, 625 [RPMH_RF_CLK2_A] = &clk_rpmh_clk2_a1_ao.hw, 626 [RPMH_RF_CLK3] = &clk_rpmh_clk3_a1.hw, 627 [RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a1_ao.hw, 628 [RPMH_RF_CLK4] = &clk_rpmh_clk4_a1.hw, 629 [RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a1_ao.hw, 630 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 631 }; 632 633 static const struct clk_rpmh_desc clk_rpmh_sm8550 = { 634 .clks = sm8550_rpmh_clocks, 635 .num_clks = ARRAY_SIZE(sm8550_rpmh_clocks), 636 }; 637 638 static struct clk_hw *sm8650_rpmh_clocks[] = { 639 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 640 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 641 [RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw, 642 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw, 643 [RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a2.hw, 644 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a2_ao.hw, 645 [RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw, 646 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw, 647 [RPMH_RF_CLK1] = &clk_rpmh_clk1_a1.hw, 648 [RPMH_RF_CLK1_A] = &clk_rpmh_clk1_a1_ao.hw, 649 [RPMH_RF_CLK2] = &clk_rpmh_clk2_a1.hw, 650 [RPMH_RF_CLK2_A] = &clk_rpmh_clk2_a1_ao.hw, 651 /* 652 * The clka3 RPMh resource is missing in cmd-db 653 * for current platforms, while the clka3 exists 654 * on the PMK8550, the clock is unconnected and 655 * unused. 656 */ 657 [RPMH_RF_CLK4] = &clk_rpmh_clk4_a2.hw, 658 [RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a2_ao.hw, 659 [RPMH_RF_CLK5] = &clk_rpmh_clk5_a2.hw, 660 [RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a2_ao.hw, 661 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 662 }; 663 664 static const struct clk_rpmh_desc clk_rpmh_sm8650 = { 665 .clks = sm8650_rpmh_clocks, 666 .num_clks = ARRAY_SIZE(sm8650_rpmh_clocks), 667 }; 668 669 static struct clk_hw *sc7280_rpmh_clocks[] = { 670 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, 671 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, 672 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 673 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 674 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 675 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 676 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 677 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 678 [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw, 679 [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw, 680 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 681 [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, 682 [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, 683 }; 684 685 static const struct clk_rpmh_desc clk_rpmh_sc7280 = { 686 .clks = sc7280_rpmh_clocks, 687 .num_clks = ARRAY_SIZE(sc7280_rpmh_clocks), 688 }; 689 690 static struct clk_hw *sm6350_rpmh_clocks[] = { 691 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, 692 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, 693 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_g4.hw, 694 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_g4_ao.hw, 695 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_g4.hw, 696 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_g4_ao.hw, 697 [RPMH_QLINK_CLK] = &clk_rpmh_qlink_div4.hw, 698 [RPMH_QLINK_CLK_A] = &clk_rpmh_qlink_div4_ao.hw, 699 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 700 }; 701 702 static const struct clk_rpmh_desc clk_rpmh_sm6350 = { 703 .clks = sm6350_rpmh_clocks, 704 .num_clks = ARRAY_SIZE(sm6350_rpmh_clocks), 705 }; 706 707 static struct clk_hw *sdx65_rpmh_clocks[] = { 708 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, 709 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, 710 [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a4.hw, 711 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a4_ao.hw, 712 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 713 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 714 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 715 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 716 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 717 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 718 [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw, 719 [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw, 720 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 721 [RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw, 722 }; 723 724 static const struct clk_rpmh_desc clk_rpmh_sdx65 = { 725 .clks = sdx65_rpmh_clocks, 726 .num_clks = ARRAY_SIZE(sdx65_rpmh_clocks), 727 }; 728 729 static struct clk_hw *qdu1000_rpmh_clocks[] = { 730 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div1.hw, 731 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div1_ao.hw, 732 }; 733 734 static const struct clk_rpmh_desc clk_rpmh_qdu1000 = { 735 .clks = qdu1000_rpmh_clocks, 736 .num_clks = ARRAY_SIZE(qdu1000_rpmh_clocks), 737 }; 738 739 static struct clk_hw *sdx75_rpmh_clocks[] = { 740 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, 741 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, 742 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 743 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 744 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 745 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 746 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 747 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 748 [RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw, 749 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 750 }; 751 752 static const struct clk_rpmh_desc clk_rpmh_sdx75 = { 753 .clks = sdx75_rpmh_clocks, 754 .num_clks = ARRAY_SIZE(sdx75_rpmh_clocks), 755 }; 756 757 static struct clk_hw *sm4450_rpmh_clocks[] = { 758 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, 759 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, 760 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a4.hw, 761 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a4_ao.hw, 762 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a4.hw, 763 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a4_ao.hw, 764 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 765 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 766 [RPMH_RF_CLK5] = &clk_rpmh_rf_clk5_a.hw, 767 [RPMH_RF_CLK5_A] = &clk_rpmh_rf_clk5_a_ao.hw, 768 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 769 }; 770 771 static const struct clk_rpmh_desc clk_rpmh_sm4450 = { 772 .clks = sm4450_rpmh_clocks, 773 .num_clks = ARRAY_SIZE(sm4450_rpmh_clocks), 774 }; 775 776 static struct clk_hw *x1e80100_rpmh_clocks[] = { 777 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 778 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 779 [RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw, 780 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw, 781 [RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a2.hw, 782 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a2_ao.hw, 783 [RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw, 784 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw, 785 [RPMH_RF_CLK3] = &clk_rpmh_clk3_a2.hw, 786 [RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a2_ao.hw, 787 [RPMH_RF_CLK4] = &clk_rpmh_clk4_a2.hw, 788 [RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a2_ao.hw, 789 [RPMH_RF_CLK5] = &clk_rpmh_clk5_a2.hw, 790 [RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a2_ao.hw, 791 }; 792 793 static const struct clk_rpmh_desc clk_rpmh_x1e80100 = { 794 .clks = x1e80100_rpmh_clocks, 795 .num_clks = ARRAY_SIZE(x1e80100_rpmh_clocks), 796 }; 797 798 static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, 799 void *data) 800 { 801 struct clk_rpmh_desc *rpmh = data; 802 unsigned int idx = clkspec->args[0]; 803 804 if (idx >= rpmh->num_clks) { 805 pr_err("%s: invalid index %u\n", __func__, idx); 806 return ERR_PTR(-EINVAL); 807 } 808 809 return rpmh->clks[idx]; 810 } 811 812 static int clk_rpmh_probe(struct platform_device *pdev) 813 { 814 struct clk_hw **hw_clks; 815 struct clk_rpmh *rpmh_clk; 816 const struct clk_rpmh_desc *desc; 817 int ret, i; 818 819 desc = of_device_get_match_data(&pdev->dev); 820 if (!desc) 821 return -ENODEV; 822 823 hw_clks = desc->clks; 824 825 for (i = 0; i < desc->num_clks; i++) { 826 const char *name; 827 u32 res_addr; 828 size_t aux_data_len; 829 const struct bcm_db *data; 830 831 if (!hw_clks[i]) 832 continue; 833 834 name = hw_clks[i]->init->name; 835 836 rpmh_clk = to_clk_rpmh(hw_clks[i]); 837 res_addr = cmd_db_read_addr(rpmh_clk->res_name); 838 if (!res_addr) { 839 dev_err(&pdev->dev, "missing RPMh resource address for %s\n", 840 rpmh_clk->res_name); 841 return -ENODEV; 842 } 843 844 data = cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len); 845 if (IS_ERR(data)) { 846 ret = PTR_ERR(data); 847 dev_err(&pdev->dev, 848 "error reading RPMh aux data for %s (%d)\n", 849 rpmh_clk->res_name, ret); 850 return ret; 851 } 852 853 /* Convert unit from Khz to Hz */ 854 if (aux_data_len == sizeof(*data)) 855 rpmh_clk->unit = le32_to_cpu(data->unit) * 1000ULL; 856 857 rpmh_clk->res_addr += res_addr; 858 rpmh_clk->dev = &pdev->dev; 859 860 ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]); 861 if (ret) { 862 dev_err(&pdev->dev, "failed to register %s\n", name); 863 return ret; 864 } 865 } 866 867 /* typecast to silence compiler warning */ 868 ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_rpmh_hw_get, 869 (void *)desc); 870 if (ret) { 871 dev_err(&pdev->dev, "Failed to add clock provider\n"); 872 return ret; 873 } 874 875 dev_dbg(&pdev->dev, "Registered RPMh clocks\n"); 876 877 return 0; 878 } 879 880 static const struct of_device_id clk_rpmh_match_table[] = { 881 { .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000}, 882 { .compatible = "qcom,sa8775p-rpmh-clk", .data = &clk_rpmh_sa8775p}, 883 { .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180}, 884 { .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x}, 885 { .compatible = "qcom,sc8280xp-rpmh-clk", .data = &clk_rpmh_sc8280xp}, 886 { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845}, 887 { .compatible = "qcom,sdm670-rpmh-clk", .data = &clk_rpmh_sdm670}, 888 { .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55}, 889 { .compatible = "qcom,sdx65-rpmh-clk", .data = &clk_rpmh_sdx65}, 890 { .compatible = "qcom,sdx75-rpmh-clk", .data = &clk_rpmh_sdx75}, 891 { .compatible = "qcom,sm4450-rpmh-clk", .data = &clk_rpmh_sm4450}, 892 { .compatible = "qcom,sm6350-rpmh-clk", .data = &clk_rpmh_sm6350}, 893 { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150}, 894 { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250}, 895 { .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350}, 896 { .compatible = "qcom,sm8450-rpmh-clk", .data = &clk_rpmh_sm8450}, 897 { .compatible = "qcom,sm8550-rpmh-clk", .data = &clk_rpmh_sm8550}, 898 { .compatible = "qcom,sm8650-rpmh-clk", .data = &clk_rpmh_sm8650}, 899 { .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280}, 900 { .compatible = "qcom,x1e80100-rpmh-clk", .data = &clk_rpmh_x1e80100}, 901 { } 902 }; 903 MODULE_DEVICE_TABLE(of, clk_rpmh_match_table); 904 905 static struct platform_driver clk_rpmh_driver = { 906 .probe = clk_rpmh_probe, 907 .driver = { 908 .name = "clk-rpmh", 909 .of_match_table = clk_rpmh_match_table, 910 }, 911 }; 912 913 static int __init clk_rpmh_init(void) 914 { 915 return platform_driver_register(&clk_rpmh_driver); 916 } 917 core_initcall(clk_rpmh_init); 918 919 static void __exit clk_rpmh_exit(void) 920 { 921 platform_driver_unregister(&clk_rpmh_driver); 922 } 923 module_exit(clk_rpmh_exit); 924 925 MODULE_DESCRIPTION("QCOM RPMh Clock Driver"); 926 MODULE_LICENSE("GPL v2"); 927