1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2017, Linaro Limited 4 * Author: Georgi Djakov <georgi.djakov@linaro.org> 5 */ 6 7 #ifndef __QCOM_CLK_REGMAP_MUX_DIV_H__ 8 #define __QCOM_CLK_REGMAP_MUX_DIV_H__ 9 10 #include <linux/clk-provider.h> 11 #include "clk-regmap.h" 12 13 /** 14 * struct mux_div_clk - combined mux/divider clock 15 * @reg_offset: offset of the mux/divider register 16 * @hid_width: number of bits in half integer divider 17 * @hid_shift: lowest bit of hid value field 18 * @src_width: number of bits in source select 19 * @src_shift: lowest bit of source select field 20 * @div: the divider raw configuration value 21 * @src: the mux index which will be used if the clock is enabled 22 * @parent_map: map from parent_names index to src_sel field 23 * @clkr: handle between common and hardware-specific interfaces 24 * @pclk: the input PLL clock 25 * @clk_nb: clock notifier for rate changes of the input PLL 26 */ 27 struct clk_regmap_mux_div { 28 u32 reg_offset; 29 u32 hid_width; 30 u32 hid_shift; 31 u32 src_width; 32 u32 src_shift; 33 u32 div; 34 u32 src; 35 const u32 *parent_map; 36 struct clk_regmap clkr; 37 struct clk *pclk; 38 struct notifier_block clk_nb; 39 }; 40 41 extern const struct clk_ops clk_regmap_mux_div_ops; 42 extern int mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div); 43 44 #endif 45