1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/bitops.h> 8 #include <linux/err.h> 9 #include <linux/bug.h> 10 #include <linux/export.h> 11 #include <linux/clk-provider.h> 12 #include <linux/delay.h> 13 #include <linux/rational.h> 14 #include <linux/regmap.h> 15 #include <linux/math64.h> 16 #include <linux/minmax.h> 17 #include <linux/slab.h> 18 19 #include <asm/div64.h> 20 21 #include "clk-rcg.h" 22 #include "common.h" 23 24 #define CMD_REG 0x0 25 #define CMD_UPDATE BIT(0) 26 #define CMD_ROOT_EN BIT(1) 27 #define CMD_DIRTY_CFG BIT(4) 28 #define CMD_DIRTY_N BIT(5) 29 #define CMD_DIRTY_M BIT(6) 30 #define CMD_DIRTY_D BIT(7) 31 #define CMD_ROOT_OFF BIT(31) 32 33 #define CFG_REG 0x4 34 #define CFG_SRC_DIV_SHIFT 0 35 #define CFG_SRC_SEL_SHIFT 8 36 #define CFG_SRC_SEL_MASK (0x7 << CFG_SRC_SEL_SHIFT) 37 #define CFG_MODE_SHIFT 12 38 #define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT) 39 #define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT) 40 #define CFG_HW_CLK_CTRL_MASK BIT(20) 41 42 #define M_REG 0x8 43 #define N_REG 0xc 44 #define D_REG 0x10 45 46 #define RCG_CFG_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + CFG_REG) 47 #define RCG_M_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + M_REG) 48 #define RCG_N_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + N_REG) 49 #define RCG_D_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + D_REG) 50 51 /* Dynamic Frequency Scaling */ 52 #define MAX_PERF_LEVEL 8 53 #define SE_CMD_DFSR_OFFSET 0x14 54 #define SE_CMD_DFS_EN BIT(0) 55 #define SE_PERF_DFSR(level) (0x1c + 0x4 * (level)) 56 #define SE_PERF_M_DFSR(level) (0x5c + 0x4 * (level)) 57 #define SE_PERF_N_DFSR(level) (0x9c + 0x4 * (level)) 58 59 enum freq_policy { 60 FLOOR, 61 CEIL, 62 }; 63 64 static int clk_rcg2_is_enabled(struct clk_hw *hw) 65 { 66 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 67 u32 cmd; 68 int ret; 69 70 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd); 71 if (ret) 72 return ret; 73 74 return (cmd & CMD_ROOT_OFF) == 0; 75 } 76 77 static u8 __clk_rcg2_get_parent(struct clk_hw *hw, u32 cfg) 78 { 79 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 80 int num_parents = clk_hw_get_num_parents(hw); 81 int i; 82 83 cfg &= CFG_SRC_SEL_MASK; 84 cfg >>= CFG_SRC_SEL_SHIFT; 85 86 for (i = 0; i < num_parents; i++) 87 if (cfg == rcg->parent_map[i].cfg) 88 return i; 89 90 pr_debug("%s: Clock %s has invalid parent, using default.\n", 91 __func__, clk_hw_get_name(hw)); 92 return 0; 93 } 94 95 static u8 clk_rcg2_get_parent(struct clk_hw *hw) 96 { 97 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 98 u32 cfg; 99 int ret; 100 101 ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); 102 if (ret) { 103 pr_debug("%s: Unable to read CFG register for %s\n", 104 __func__, clk_hw_get_name(hw)); 105 return 0; 106 } 107 108 return __clk_rcg2_get_parent(hw, cfg); 109 } 110 111 static int update_config(struct clk_rcg2 *rcg) 112 { 113 int count, ret; 114 u32 cmd; 115 struct clk_hw *hw = &rcg->clkr.hw; 116 const char *name = clk_hw_get_name(hw); 117 118 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, 119 CMD_UPDATE, CMD_UPDATE); 120 if (ret) 121 return ret; 122 123 /* Wait for update to take effect */ 124 for (count = 500; count > 0; count--) { 125 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd); 126 if (ret) 127 return ret; 128 if (!(cmd & CMD_UPDATE)) 129 return 0; 130 udelay(1); 131 } 132 133 WARN(1, "%s: rcg didn't update its configuration.", name); 134 return -EBUSY; 135 } 136 137 static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index) 138 { 139 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 140 int ret; 141 u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; 142 143 ret = regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), 144 CFG_SRC_SEL_MASK, cfg); 145 if (ret) 146 return ret; 147 148 return update_config(rcg); 149 } 150 151 /* 152 * Calculate m/n:d rate 153 * 154 * parent_rate m 155 * rate = ----------- x --- 156 * hid_div n 157 */ 158 static unsigned long 159 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div) 160 { 161 if (hid_div) { 162 rate *= 2; 163 rate /= hid_div + 1; 164 } 165 166 if (mode) { 167 u64 tmp = rate; 168 tmp *= m; 169 do_div(tmp, n); 170 rate = tmp; 171 } 172 173 return rate; 174 } 175 176 static unsigned long 177 __clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, u32 cfg) 178 { 179 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 180 u32 hid_div, m = 0, n = 0, mode = 0, mask; 181 182 if (rcg->mnd_width) { 183 mask = BIT(rcg->mnd_width) - 1; 184 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m); 185 m &= mask; 186 regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), &n); 187 n = ~n; 188 n &= mask; 189 n += m; 190 mode = cfg & CFG_MODE_MASK; 191 mode >>= CFG_MODE_SHIFT; 192 } 193 194 mask = BIT(rcg->hid_width) - 1; 195 hid_div = cfg >> CFG_SRC_DIV_SHIFT; 196 hid_div &= mask; 197 198 return calc_rate(parent_rate, m, n, mode, hid_div); 199 } 200 201 static unsigned long 202 clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 203 { 204 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 205 u32 cfg; 206 207 regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); 208 209 return __clk_rcg2_recalc_rate(hw, parent_rate, cfg); 210 } 211 212 static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, 213 struct clk_rate_request *req, 214 enum freq_policy policy) 215 { 216 unsigned long clk_flags, rate = req->rate; 217 struct clk_hw *p; 218 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 219 int index; 220 221 switch (policy) { 222 case FLOOR: 223 f = qcom_find_freq_floor(f, rate); 224 break; 225 case CEIL: 226 f = qcom_find_freq(f, rate); 227 break; 228 default: 229 return -EINVAL; 230 } 231 232 if (!f) 233 return -EINVAL; 234 235 index = qcom_find_src_index(hw, rcg->parent_map, f->src); 236 if (index < 0) 237 return index; 238 239 clk_flags = clk_hw_get_flags(hw); 240 p = clk_hw_get_parent_by_index(hw, index); 241 if (!p) 242 return -EINVAL; 243 244 if (clk_flags & CLK_SET_RATE_PARENT) { 245 rate = f->freq; 246 if (f->pre_div) { 247 if (!rate) 248 rate = req->rate; 249 rate /= 2; 250 rate *= f->pre_div + 1; 251 } 252 253 if (f->n) { 254 u64 tmp = rate; 255 tmp = tmp * f->n; 256 do_div(tmp, f->m); 257 rate = tmp; 258 } 259 } else { 260 rate = clk_hw_get_rate(p); 261 } 262 req->best_parent_hw = p; 263 req->best_parent_rate = rate; 264 req->rate = f->freq; 265 266 return 0; 267 } 268 269 static int clk_rcg2_determine_rate(struct clk_hw *hw, 270 struct clk_rate_request *req) 271 { 272 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 273 274 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, CEIL); 275 } 276 277 static int clk_rcg2_determine_floor_rate(struct clk_hw *hw, 278 struct clk_rate_request *req) 279 { 280 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 281 282 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR); 283 } 284 285 static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f, 286 u32 *_cfg) 287 { 288 u32 cfg, mask, d_val, not2d_val, n_minus_m; 289 struct clk_hw *hw = &rcg->clkr.hw; 290 int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src); 291 292 if (index < 0) 293 return index; 294 295 if (rcg->mnd_width && f->n) { 296 mask = BIT(rcg->mnd_width) - 1; 297 ret = regmap_update_bits(rcg->clkr.regmap, 298 RCG_M_OFFSET(rcg), mask, f->m); 299 if (ret) 300 return ret; 301 302 ret = regmap_update_bits(rcg->clkr.regmap, 303 RCG_N_OFFSET(rcg), mask, ~(f->n - f->m)); 304 if (ret) 305 return ret; 306 307 /* Calculate 2d value */ 308 d_val = f->n; 309 310 n_minus_m = f->n - f->m; 311 n_minus_m *= 2; 312 313 d_val = clamp_t(u32, d_val, f->m, n_minus_m); 314 not2d_val = ~d_val & mask; 315 316 ret = regmap_update_bits(rcg->clkr.regmap, 317 RCG_D_OFFSET(rcg), mask, not2d_val); 318 if (ret) 319 return ret; 320 } 321 322 mask = BIT(rcg->hid_width) - 1; 323 mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK; 324 cfg = f->pre_div << CFG_SRC_DIV_SHIFT; 325 cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; 326 if (rcg->mnd_width && f->n && (f->m != f->n)) 327 cfg |= CFG_MODE_DUAL_EDGE; 328 329 *_cfg &= ~mask; 330 *_cfg |= cfg; 331 332 return 0; 333 } 334 335 static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) 336 { 337 u32 cfg; 338 int ret; 339 340 ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); 341 if (ret) 342 return ret; 343 344 ret = __clk_rcg2_configure(rcg, f, &cfg); 345 if (ret) 346 return ret; 347 348 ret = regmap_write(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), cfg); 349 if (ret) 350 return ret; 351 352 return update_config(rcg); 353 } 354 355 static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate, 356 enum freq_policy policy) 357 { 358 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 359 const struct freq_tbl *f; 360 361 switch (policy) { 362 case FLOOR: 363 f = qcom_find_freq_floor(rcg->freq_tbl, rate); 364 break; 365 case CEIL: 366 f = qcom_find_freq(rcg->freq_tbl, rate); 367 break; 368 default: 369 return -EINVAL; 370 } 371 372 if (!f) 373 return -EINVAL; 374 375 return clk_rcg2_configure(rcg, f); 376 } 377 378 static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate, 379 unsigned long parent_rate) 380 { 381 return __clk_rcg2_set_rate(hw, rate, CEIL); 382 } 383 384 static int clk_rcg2_set_floor_rate(struct clk_hw *hw, unsigned long rate, 385 unsigned long parent_rate) 386 { 387 return __clk_rcg2_set_rate(hw, rate, FLOOR); 388 } 389 390 static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw, 391 unsigned long rate, unsigned long parent_rate, u8 index) 392 { 393 return __clk_rcg2_set_rate(hw, rate, CEIL); 394 } 395 396 static int clk_rcg2_set_floor_rate_and_parent(struct clk_hw *hw, 397 unsigned long rate, unsigned long parent_rate, u8 index) 398 { 399 return __clk_rcg2_set_rate(hw, rate, FLOOR); 400 } 401 402 static int clk_rcg2_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty) 403 { 404 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 405 u32 notn_m, n, m, d, not2d, mask; 406 407 if (!rcg->mnd_width) { 408 /* 50 % duty-cycle for Non-MND RCGs */ 409 duty->num = 1; 410 duty->den = 2; 411 return 0; 412 } 413 414 regmap_read(rcg->clkr.regmap, RCG_D_OFFSET(rcg), ¬2d); 415 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m); 416 regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), ¬n_m); 417 418 if (!not2d && !m && !notn_m) { 419 /* 50 % duty-cycle always */ 420 duty->num = 1; 421 duty->den = 2; 422 return 0; 423 } 424 425 mask = BIT(rcg->mnd_width) - 1; 426 427 d = ~(not2d) & mask; 428 d = DIV_ROUND_CLOSEST(d, 2); 429 430 n = (~(notn_m) + m) & mask; 431 432 duty->num = d; 433 duty->den = n; 434 435 return 0; 436 } 437 438 static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty) 439 { 440 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 441 u32 notn_m, n, m, d, not2d, mask, duty_per, cfg; 442 int ret; 443 444 /* Duty-cycle cannot be modified for non-MND RCGs */ 445 if (!rcg->mnd_width) 446 return -EINVAL; 447 448 mask = BIT(rcg->mnd_width) - 1; 449 450 regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), ¬n_m); 451 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m); 452 regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); 453 454 /* Duty-cycle cannot be modified if MND divider is in bypass mode. */ 455 if (!(cfg & CFG_MODE_MASK)) 456 return -EINVAL; 457 458 n = (~(notn_m) + m) & mask; 459 460 duty_per = (duty->num * 100) / duty->den; 461 462 /* Calculate 2d value */ 463 d = DIV_ROUND_CLOSEST(n * duty_per * 2, 100); 464 465 /* 466 * Check bit widths of 2d. If D is too big reduce duty cycle. 467 * Also make sure it is never zero. 468 */ 469 d = clamp_val(d, 1, mask); 470 471 if ((d / 2) > (n - m)) 472 d = (n - m) * 2; 473 else if ((d / 2) < (m / 2)) 474 d = m; 475 476 not2d = ~d & mask; 477 478 ret = regmap_update_bits(rcg->clkr.regmap, RCG_D_OFFSET(rcg), mask, 479 not2d); 480 if (ret) 481 return ret; 482 483 return update_config(rcg); 484 } 485 486 const struct clk_ops clk_rcg2_ops = { 487 .is_enabled = clk_rcg2_is_enabled, 488 .get_parent = clk_rcg2_get_parent, 489 .set_parent = clk_rcg2_set_parent, 490 .recalc_rate = clk_rcg2_recalc_rate, 491 .determine_rate = clk_rcg2_determine_rate, 492 .set_rate = clk_rcg2_set_rate, 493 .set_rate_and_parent = clk_rcg2_set_rate_and_parent, 494 .get_duty_cycle = clk_rcg2_get_duty_cycle, 495 .set_duty_cycle = clk_rcg2_set_duty_cycle, 496 }; 497 EXPORT_SYMBOL_GPL(clk_rcg2_ops); 498 499 const struct clk_ops clk_rcg2_floor_ops = { 500 .is_enabled = clk_rcg2_is_enabled, 501 .get_parent = clk_rcg2_get_parent, 502 .set_parent = clk_rcg2_set_parent, 503 .recalc_rate = clk_rcg2_recalc_rate, 504 .determine_rate = clk_rcg2_determine_floor_rate, 505 .set_rate = clk_rcg2_set_floor_rate, 506 .set_rate_and_parent = clk_rcg2_set_floor_rate_and_parent, 507 .get_duty_cycle = clk_rcg2_get_duty_cycle, 508 .set_duty_cycle = clk_rcg2_set_duty_cycle, 509 }; 510 EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops); 511 512 const struct clk_ops clk_rcg2_mux_closest_ops = { 513 .determine_rate = __clk_mux_determine_rate_closest, 514 .get_parent = clk_rcg2_get_parent, 515 .set_parent = clk_rcg2_set_parent, 516 }; 517 EXPORT_SYMBOL_GPL(clk_rcg2_mux_closest_ops); 518 519 struct frac_entry { 520 int num; 521 int den; 522 }; 523 524 static const struct frac_entry frac_table_675m[] = { /* link rate of 270M */ 525 { 52, 295 }, /* 119 M */ 526 { 11, 57 }, /* 130.25 M */ 527 { 63, 307 }, /* 138.50 M */ 528 { 11, 50 }, /* 148.50 M */ 529 { 47, 206 }, /* 154 M */ 530 { 31, 100 }, /* 205.25 M */ 531 { 107, 269 }, /* 268.50 M */ 532 { }, 533 }; 534 535 static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */ 536 { 31, 211 }, /* 119 M */ 537 { 32, 199 }, /* 130.25 M */ 538 { 63, 307 }, /* 138.50 M */ 539 { 11, 60 }, /* 148.50 M */ 540 { 50, 263 }, /* 154 M */ 541 { 31, 120 }, /* 205.25 M */ 542 { 119, 359 }, /* 268.50 M */ 543 { }, 544 }; 545 546 static int clk_edp_pixel_set_rate(struct clk_hw *hw, unsigned long rate, 547 unsigned long parent_rate) 548 { 549 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 550 struct freq_tbl f = *rcg->freq_tbl; 551 const struct frac_entry *frac; 552 int delta = 100000; 553 s64 src_rate = parent_rate; 554 s64 request; 555 u32 mask = BIT(rcg->hid_width) - 1; 556 u32 hid_div; 557 558 if (src_rate == 810000000) 559 frac = frac_table_810m; 560 else 561 frac = frac_table_675m; 562 563 for (; frac->num; frac++) { 564 request = rate; 565 request *= frac->den; 566 request = div_s64(request, frac->num); 567 if ((src_rate < (request - delta)) || 568 (src_rate > (request + delta))) 569 continue; 570 571 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, 572 &hid_div); 573 f.pre_div = hid_div; 574 f.pre_div >>= CFG_SRC_DIV_SHIFT; 575 f.pre_div &= mask; 576 f.m = frac->num; 577 f.n = frac->den; 578 579 return clk_rcg2_configure(rcg, &f); 580 } 581 582 return -EINVAL; 583 } 584 585 static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw, 586 unsigned long rate, unsigned long parent_rate, u8 index) 587 { 588 /* Parent index is set statically in frequency table */ 589 return clk_edp_pixel_set_rate(hw, rate, parent_rate); 590 } 591 592 static int clk_edp_pixel_determine_rate(struct clk_hw *hw, 593 struct clk_rate_request *req) 594 { 595 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 596 const struct freq_tbl *f = rcg->freq_tbl; 597 const struct frac_entry *frac; 598 int delta = 100000; 599 s64 request; 600 u32 mask = BIT(rcg->hid_width) - 1; 601 u32 hid_div; 602 int index = qcom_find_src_index(hw, rcg->parent_map, f->src); 603 604 /* Force the correct parent */ 605 req->best_parent_hw = clk_hw_get_parent_by_index(hw, index); 606 req->best_parent_rate = clk_hw_get_rate(req->best_parent_hw); 607 608 if (req->best_parent_rate == 810000000) 609 frac = frac_table_810m; 610 else 611 frac = frac_table_675m; 612 613 for (; frac->num; frac++) { 614 request = req->rate; 615 request *= frac->den; 616 request = div_s64(request, frac->num); 617 if ((req->best_parent_rate < (request - delta)) || 618 (req->best_parent_rate > (request + delta))) 619 continue; 620 621 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, 622 &hid_div); 623 hid_div >>= CFG_SRC_DIV_SHIFT; 624 hid_div &= mask; 625 626 req->rate = calc_rate(req->best_parent_rate, 627 frac->num, frac->den, 628 !!frac->den, hid_div); 629 return 0; 630 } 631 632 return -EINVAL; 633 } 634 635 const struct clk_ops clk_edp_pixel_ops = { 636 .is_enabled = clk_rcg2_is_enabled, 637 .get_parent = clk_rcg2_get_parent, 638 .set_parent = clk_rcg2_set_parent, 639 .recalc_rate = clk_rcg2_recalc_rate, 640 .set_rate = clk_edp_pixel_set_rate, 641 .set_rate_and_parent = clk_edp_pixel_set_rate_and_parent, 642 .determine_rate = clk_edp_pixel_determine_rate, 643 }; 644 EXPORT_SYMBOL_GPL(clk_edp_pixel_ops); 645 646 static int clk_byte_determine_rate(struct clk_hw *hw, 647 struct clk_rate_request *req) 648 { 649 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 650 const struct freq_tbl *f = rcg->freq_tbl; 651 int index = qcom_find_src_index(hw, rcg->parent_map, f->src); 652 unsigned long parent_rate, div; 653 u32 mask = BIT(rcg->hid_width) - 1; 654 struct clk_hw *p; 655 656 if (req->rate == 0) 657 return -EINVAL; 658 659 req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index); 660 req->best_parent_rate = parent_rate = clk_hw_round_rate(p, req->rate); 661 662 div = DIV_ROUND_UP((2 * parent_rate), req->rate) - 1; 663 div = min_t(u32, div, mask); 664 665 req->rate = calc_rate(parent_rate, 0, 0, 0, div); 666 667 return 0; 668 } 669 670 static int clk_byte_set_rate(struct clk_hw *hw, unsigned long rate, 671 unsigned long parent_rate) 672 { 673 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 674 struct freq_tbl f = *rcg->freq_tbl; 675 unsigned long div; 676 u32 mask = BIT(rcg->hid_width) - 1; 677 678 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1; 679 div = min_t(u32, div, mask); 680 681 f.pre_div = div; 682 683 return clk_rcg2_configure(rcg, &f); 684 } 685 686 static int clk_byte_set_rate_and_parent(struct clk_hw *hw, 687 unsigned long rate, unsigned long parent_rate, u8 index) 688 { 689 /* Parent index is set statically in frequency table */ 690 return clk_byte_set_rate(hw, rate, parent_rate); 691 } 692 693 const struct clk_ops clk_byte_ops = { 694 .is_enabled = clk_rcg2_is_enabled, 695 .get_parent = clk_rcg2_get_parent, 696 .set_parent = clk_rcg2_set_parent, 697 .recalc_rate = clk_rcg2_recalc_rate, 698 .set_rate = clk_byte_set_rate, 699 .set_rate_and_parent = clk_byte_set_rate_and_parent, 700 .determine_rate = clk_byte_determine_rate, 701 }; 702 EXPORT_SYMBOL_GPL(clk_byte_ops); 703 704 static int clk_byte2_determine_rate(struct clk_hw *hw, 705 struct clk_rate_request *req) 706 { 707 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 708 unsigned long parent_rate, div; 709 u32 mask = BIT(rcg->hid_width) - 1; 710 struct clk_hw *p; 711 unsigned long rate = req->rate; 712 713 if (rate == 0) 714 return -EINVAL; 715 716 p = req->best_parent_hw; 717 req->best_parent_rate = parent_rate = clk_hw_round_rate(p, rate); 718 719 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1; 720 div = min_t(u32, div, mask); 721 722 req->rate = calc_rate(parent_rate, 0, 0, 0, div); 723 724 return 0; 725 } 726 727 static int clk_byte2_set_rate(struct clk_hw *hw, unsigned long rate, 728 unsigned long parent_rate) 729 { 730 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 731 struct freq_tbl f = { 0 }; 732 unsigned long div; 733 int i, num_parents = clk_hw_get_num_parents(hw); 734 u32 mask = BIT(rcg->hid_width) - 1; 735 u32 cfg; 736 737 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1; 738 div = min_t(u32, div, mask); 739 740 f.pre_div = div; 741 742 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); 743 cfg &= CFG_SRC_SEL_MASK; 744 cfg >>= CFG_SRC_SEL_SHIFT; 745 746 for (i = 0; i < num_parents; i++) { 747 if (cfg == rcg->parent_map[i].cfg) { 748 f.src = rcg->parent_map[i].src; 749 return clk_rcg2_configure(rcg, &f); 750 } 751 } 752 753 return -EINVAL; 754 } 755 756 static int clk_byte2_set_rate_and_parent(struct clk_hw *hw, 757 unsigned long rate, unsigned long parent_rate, u8 index) 758 { 759 /* Read the hardware to determine parent during set_rate */ 760 return clk_byte2_set_rate(hw, rate, parent_rate); 761 } 762 763 const struct clk_ops clk_byte2_ops = { 764 .is_enabled = clk_rcg2_is_enabled, 765 .get_parent = clk_rcg2_get_parent, 766 .set_parent = clk_rcg2_set_parent, 767 .recalc_rate = clk_rcg2_recalc_rate, 768 .set_rate = clk_byte2_set_rate, 769 .set_rate_and_parent = clk_byte2_set_rate_and_parent, 770 .determine_rate = clk_byte2_determine_rate, 771 }; 772 EXPORT_SYMBOL_GPL(clk_byte2_ops); 773 774 static const struct frac_entry frac_table_pixel[] = { 775 { 3, 8 }, 776 { 2, 9 }, 777 { 4, 9 }, 778 { 1, 1 }, 779 { 2, 3 }, 780 { } 781 }; 782 783 static int clk_pixel_determine_rate(struct clk_hw *hw, 784 struct clk_rate_request *req) 785 { 786 unsigned long request, src_rate; 787 int delta = 100000; 788 const struct frac_entry *frac = frac_table_pixel; 789 790 for (; frac->num; frac++) { 791 request = (req->rate * frac->den) / frac->num; 792 793 src_rate = clk_hw_round_rate(req->best_parent_hw, request); 794 if ((src_rate < (request - delta)) || 795 (src_rate > (request + delta))) 796 continue; 797 798 req->best_parent_rate = src_rate; 799 req->rate = (src_rate * frac->num) / frac->den; 800 return 0; 801 } 802 803 return -EINVAL; 804 } 805 806 static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate, 807 unsigned long parent_rate) 808 { 809 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 810 struct freq_tbl f = { 0 }; 811 const struct frac_entry *frac = frac_table_pixel; 812 unsigned long request; 813 int delta = 100000; 814 u32 mask = BIT(rcg->hid_width) - 1; 815 u32 hid_div, cfg; 816 int i, num_parents = clk_hw_get_num_parents(hw); 817 818 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); 819 cfg &= CFG_SRC_SEL_MASK; 820 cfg >>= CFG_SRC_SEL_SHIFT; 821 822 for (i = 0; i < num_parents; i++) 823 if (cfg == rcg->parent_map[i].cfg) { 824 f.src = rcg->parent_map[i].src; 825 break; 826 } 827 828 for (; frac->num; frac++) { 829 request = (rate * frac->den) / frac->num; 830 831 if ((parent_rate < (request - delta)) || 832 (parent_rate > (request + delta))) 833 continue; 834 835 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, 836 &hid_div); 837 f.pre_div = hid_div; 838 f.pre_div >>= CFG_SRC_DIV_SHIFT; 839 f.pre_div &= mask; 840 f.m = frac->num; 841 f.n = frac->den; 842 843 return clk_rcg2_configure(rcg, &f); 844 } 845 return -EINVAL; 846 } 847 848 static int clk_pixel_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, 849 unsigned long parent_rate, u8 index) 850 { 851 return clk_pixel_set_rate(hw, rate, parent_rate); 852 } 853 854 const struct clk_ops clk_pixel_ops = { 855 .is_enabled = clk_rcg2_is_enabled, 856 .get_parent = clk_rcg2_get_parent, 857 .set_parent = clk_rcg2_set_parent, 858 .recalc_rate = clk_rcg2_recalc_rate, 859 .set_rate = clk_pixel_set_rate, 860 .set_rate_and_parent = clk_pixel_set_rate_and_parent, 861 .determine_rate = clk_pixel_determine_rate, 862 }; 863 EXPORT_SYMBOL_GPL(clk_pixel_ops); 864 865 static int clk_gfx3d_determine_rate(struct clk_hw *hw, 866 struct clk_rate_request *req) 867 { 868 struct clk_rate_request parent_req = { .min_rate = 0, .max_rate = ULONG_MAX }; 869 struct clk_rcg2_gfx3d *cgfx = to_clk_rcg2_gfx3d(hw); 870 struct clk_hw *xo, *p0, *p1, *p2; 871 unsigned long p0_rate; 872 u8 mux_div = cgfx->div; 873 int ret; 874 875 p0 = cgfx->hws[0]; 876 p1 = cgfx->hws[1]; 877 p2 = cgfx->hws[2]; 878 /* 879 * This function does ping-pong the RCG between PLLs: if we don't 880 * have at least one fixed PLL and two variable ones, 881 * then it's not going to work correctly. 882 */ 883 if (WARN_ON(!p0 || !p1 || !p2)) 884 return -EINVAL; 885 886 xo = clk_hw_get_parent_by_index(hw, 0); 887 if (req->rate == clk_hw_get_rate(xo)) { 888 req->best_parent_hw = xo; 889 return 0; 890 } 891 892 if (mux_div == 0) 893 mux_div = 1; 894 895 parent_req.rate = req->rate * mux_div; 896 897 /* This has to be a fixed rate PLL */ 898 p0_rate = clk_hw_get_rate(p0); 899 900 if (parent_req.rate == p0_rate) { 901 req->rate = req->best_parent_rate = p0_rate; 902 req->best_parent_hw = p0; 903 return 0; 904 } 905 906 if (req->best_parent_hw == p0) { 907 /* Are we going back to a previously used rate? */ 908 if (clk_hw_get_rate(p2) == parent_req.rate) 909 req->best_parent_hw = p2; 910 else 911 req->best_parent_hw = p1; 912 } else if (req->best_parent_hw == p2) { 913 req->best_parent_hw = p1; 914 } else { 915 req->best_parent_hw = p2; 916 } 917 918 ret = __clk_determine_rate(req->best_parent_hw, &parent_req); 919 if (ret) 920 return ret; 921 922 req->rate = req->best_parent_rate = parent_req.rate; 923 req->rate /= mux_div; 924 925 return 0; 926 } 927 928 static int clk_gfx3d_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, 929 unsigned long parent_rate, u8 index) 930 { 931 struct clk_rcg2_gfx3d *cgfx = to_clk_rcg2_gfx3d(hw); 932 struct clk_rcg2 *rcg = &cgfx->rcg; 933 u32 cfg; 934 int ret; 935 936 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; 937 /* On some targets, the GFX3D RCG may need to divide PLL frequency */ 938 if (cgfx->div > 1) 939 cfg |= ((2 * cgfx->div) - 1) << CFG_SRC_DIV_SHIFT; 940 941 ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg); 942 if (ret) 943 return ret; 944 945 return update_config(rcg); 946 } 947 948 static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate, 949 unsigned long parent_rate) 950 { 951 /* 952 * We should never get here; clk_gfx3d_determine_rate() should always 953 * make us use a different parent than what we're currently using, so 954 * clk_gfx3d_set_rate_and_parent() should always be called. 955 */ 956 return 0; 957 } 958 959 const struct clk_ops clk_gfx3d_ops = { 960 .is_enabled = clk_rcg2_is_enabled, 961 .get_parent = clk_rcg2_get_parent, 962 .set_parent = clk_rcg2_set_parent, 963 .recalc_rate = clk_rcg2_recalc_rate, 964 .set_rate = clk_gfx3d_set_rate, 965 .set_rate_and_parent = clk_gfx3d_set_rate_and_parent, 966 .determine_rate = clk_gfx3d_determine_rate, 967 }; 968 EXPORT_SYMBOL_GPL(clk_gfx3d_ops); 969 970 static int clk_rcg2_set_force_enable(struct clk_hw *hw) 971 { 972 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 973 const char *name = clk_hw_get_name(hw); 974 int ret, count; 975 976 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, 977 CMD_ROOT_EN, CMD_ROOT_EN); 978 if (ret) 979 return ret; 980 981 /* wait for RCG to turn ON */ 982 for (count = 500; count > 0; count--) { 983 if (clk_rcg2_is_enabled(hw)) 984 return 0; 985 986 udelay(1); 987 } 988 989 pr_err("%s: RCG did not turn on\n", name); 990 return -ETIMEDOUT; 991 } 992 993 static int clk_rcg2_clear_force_enable(struct clk_hw *hw) 994 { 995 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 996 997 return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, 998 CMD_ROOT_EN, 0); 999 } 1000 1001 static int 1002 clk_rcg2_shared_force_enable_clear(struct clk_hw *hw, const struct freq_tbl *f) 1003 { 1004 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 1005 int ret; 1006 1007 ret = clk_rcg2_set_force_enable(hw); 1008 if (ret) 1009 return ret; 1010 1011 ret = clk_rcg2_configure(rcg, f); 1012 if (ret) 1013 return ret; 1014 1015 return clk_rcg2_clear_force_enable(hw); 1016 } 1017 1018 static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate, 1019 unsigned long parent_rate) 1020 { 1021 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 1022 const struct freq_tbl *f; 1023 1024 f = qcom_find_freq(rcg->freq_tbl, rate); 1025 if (!f) 1026 return -EINVAL; 1027 1028 /* 1029 * In case clock is disabled, update the M, N and D registers, cache 1030 * the CFG value in parked_cfg and don't hit the update bit of CMD 1031 * register. 1032 */ 1033 if (!clk_hw_is_enabled(hw)) 1034 return __clk_rcg2_configure(rcg, f, &rcg->parked_cfg); 1035 1036 return clk_rcg2_shared_force_enable_clear(hw, f); 1037 } 1038 1039 static int clk_rcg2_shared_set_rate_and_parent(struct clk_hw *hw, 1040 unsigned long rate, unsigned long parent_rate, u8 index) 1041 { 1042 return clk_rcg2_shared_set_rate(hw, rate, parent_rate); 1043 } 1044 1045 static int clk_rcg2_shared_enable(struct clk_hw *hw) 1046 { 1047 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 1048 int ret; 1049 1050 /* 1051 * Set the update bit because required configuration has already 1052 * been written in clk_rcg2_shared_set_rate() 1053 */ 1054 ret = clk_rcg2_set_force_enable(hw); 1055 if (ret) 1056 return ret; 1057 1058 /* Write back the stored configuration corresponding to current rate */ 1059 ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, rcg->parked_cfg); 1060 if (ret) 1061 return ret; 1062 1063 ret = update_config(rcg); 1064 if (ret) 1065 return ret; 1066 1067 return clk_rcg2_clear_force_enable(hw); 1068 } 1069 1070 static void clk_rcg2_shared_disable(struct clk_hw *hw) 1071 { 1072 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 1073 1074 /* 1075 * Store current configuration as switching to safe source would clear 1076 * the SRC and DIV of CFG register 1077 */ 1078 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &rcg->parked_cfg); 1079 1080 /* 1081 * Park the RCG at a safe configuration - sourced off of safe source. 1082 * Force enable and disable the RCG while configuring it to safeguard 1083 * against any update signal coming from the downstream clock. 1084 * The current parent is still prepared and enabled at this point, and 1085 * the safe source is always on while application processor subsystem 1086 * is online. Therefore, the RCG can safely switch its parent. 1087 */ 1088 clk_rcg2_set_force_enable(hw); 1089 1090 regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, 1091 rcg->safe_src_index << CFG_SRC_SEL_SHIFT); 1092 1093 update_config(rcg); 1094 1095 clk_rcg2_clear_force_enable(hw); 1096 } 1097 1098 static u8 clk_rcg2_shared_get_parent(struct clk_hw *hw) 1099 { 1100 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 1101 1102 /* If the shared rcg is parked use the cached cfg instead */ 1103 if (!clk_hw_is_enabled(hw)) 1104 return __clk_rcg2_get_parent(hw, rcg->parked_cfg); 1105 1106 return clk_rcg2_get_parent(hw); 1107 } 1108 1109 static int clk_rcg2_shared_set_parent(struct clk_hw *hw, u8 index) 1110 { 1111 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 1112 1113 /* If the shared rcg is parked only update the cached cfg */ 1114 if (!clk_hw_is_enabled(hw)) { 1115 rcg->parked_cfg &= ~CFG_SRC_SEL_MASK; 1116 rcg->parked_cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; 1117 1118 return 0; 1119 } 1120 1121 return clk_rcg2_set_parent(hw, index); 1122 } 1123 1124 static unsigned long 1125 clk_rcg2_shared_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1126 { 1127 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 1128 1129 /* If the shared rcg is parked use the cached cfg instead */ 1130 if (!clk_hw_is_enabled(hw)) 1131 return __clk_rcg2_recalc_rate(hw, parent_rate, rcg->parked_cfg); 1132 1133 return clk_rcg2_recalc_rate(hw, parent_rate); 1134 } 1135 1136 const struct clk_ops clk_rcg2_shared_ops = { 1137 .enable = clk_rcg2_shared_enable, 1138 .disable = clk_rcg2_shared_disable, 1139 .get_parent = clk_rcg2_shared_get_parent, 1140 .set_parent = clk_rcg2_shared_set_parent, 1141 .recalc_rate = clk_rcg2_shared_recalc_rate, 1142 .determine_rate = clk_rcg2_determine_rate, 1143 .set_rate = clk_rcg2_shared_set_rate, 1144 .set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent, 1145 }; 1146 EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops); 1147 1148 /* Common APIs to be used for DFS based RCGR */ 1149 static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l, 1150 struct freq_tbl *f) 1151 { 1152 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 1153 struct clk_hw *p; 1154 unsigned long prate = 0; 1155 u32 val, mask, cfg, mode, src; 1156 int i, num_parents; 1157 1158 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(l), &cfg); 1159 1160 mask = BIT(rcg->hid_width) - 1; 1161 f->pre_div = 1; 1162 if (cfg & mask) 1163 f->pre_div = cfg & mask; 1164 1165 src = cfg & CFG_SRC_SEL_MASK; 1166 src >>= CFG_SRC_SEL_SHIFT; 1167 1168 num_parents = clk_hw_get_num_parents(hw); 1169 for (i = 0; i < num_parents; i++) { 1170 if (src == rcg->parent_map[i].cfg) { 1171 f->src = rcg->parent_map[i].src; 1172 p = clk_hw_get_parent_by_index(&rcg->clkr.hw, i); 1173 prate = clk_hw_get_rate(p); 1174 } 1175 } 1176 1177 mode = cfg & CFG_MODE_MASK; 1178 mode >>= CFG_MODE_SHIFT; 1179 if (mode) { 1180 mask = BIT(rcg->mnd_width) - 1; 1181 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_M_DFSR(l), 1182 &val); 1183 val &= mask; 1184 f->m = val; 1185 1186 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_N_DFSR(l), 1187 &val); 1188 val = ~val; 1189 val &= mask; 1190 val += f->m; 1191 f->n = val; 1192 } 1193 1194 f->freq = calc_rate(prate, f->m, f->n, mode, f->pre_div); 1195 } 1196 1197 static int clk_rcg2_dfs_populate_freq_table(struct clk_rcg2 *rcg) 1198 { 1199 struct freq_tbl *freq_tbl; 1200 int i; 1201 1202 /* Allocate space for 1 extra since table is NULL terminated */ 1203 freq_tbl = kcalloc(MAX_PERF_LEVEL + 1, sizeof(*freq_tbl), GFP_KERNEL); 1204 if (!freq_tbl) 1205 return -ENOMEM; 1206 rcg->freq_tbl = freq_tbl; 1207 1208 for (i = 0; i < MAX_PERF_LEVEL; i++) 1209 clk_rcg2_dfs_populate_freq(&rcg->clkr.hw, i, freq_tbl + i); 1210 1211 return 0; 1212 } 1213 1214 static int clk_rcg2_dfs_determine_rate(struct clk_hw *hw, 1215 struct clk_rate_request *req) 1216 { 1217 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 1218 int ret; 1219 1220 if (!rcg->freq_tbl) { 1221 ret = clk_rcg2_dfs_populate_freq_table(rcg); 1222 if (ret) { 1223 pr_err("Failed to update DFS tables for %s\n", 1224 clk_hw_get_name(hw)); 1225 return ret; 1226 } 1227 } 1228 1229 return clk_rcg2_determine_rate(hw, req); 1230 } 1231 1232 static unsigned long 1233 clk_rcg2_dfs_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1234 { 1235 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 1236 u32 level, mask, cfg, m = 0, n = 0, mode, pre_div; 1237 1238 regmap_read(rcg->clkr.regmap, 1239 rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &level); 1240 level &= GENMASK(4, 1); 1241 level >>= 1; 1242 1243 if (rcg->freq_tbl) 1244 return rcg->freq_tbl[level].freq; 1245 1246 /* 1247 * Assume that parent_rate is actually the parent because 1248 * we can't do any better at figuring it out when the table 1249 * hasn't been populated yet. We only populate the table 1250 * in determine_rate because we can't guarantee the parents 1251 * will be registered with the framework until then. 1252 */ 1253 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(level), 1254 &cfg); 1255 1256 mask = BIT(rcg->hid_width) - 1; 1257 pre_div = 1; 1258 if (cfg & mask) 1259 pre_div = cfg & mask; 1260 1261 mode = cfg & CFG_MODE_MASK; 1262 mode >>= CFG_MODE_SHIFT; 1263 if (mode) { 1264 mask = BIT(rcg->mnd_width) - 1; 1265 regmap_read(rcg->clkr.regmap, 1266 rcg->cmd_rcgr + SE_PERF_M_DFSR(level), &m); 1267 m &= mask; 1268 1269 regmap_read(rcg->clkr.regmap, 1270 rcg->cmd_rcgr + SE_PERF_N_DFSR(level), &n); 1271 n = ~n; 1272 n &= mask; 1273 n += m; 1274 } 1275 1276 return calc_rate(parent_rate, m, n, mode, pre_div); 1277 } 1278 1279 static const struct clk_ops clk_rcg2_dfs_ops = { 1280 .is_enabled = clk_rcg2_is_enabled, 1281 .get_parent = clk_rcg2_get_parent, 1282 .determine_rate = clk_rcg2_dfs_determine_rate, 1283 .recalc_rate = clk_rcg2_dfs_recalc_rate, 1284 }; 1285 1286 static int clk_rcg2_enable_dfs(const struct clk_rcg_dfs_data *data, 1287 struct regmap *regmap) 1288 { 1289 struct clk_rcg2 *rcg = data->rcg; 1290 struct clk_init_data *init = data->init; 1291 u32 val; 1292 int ret; 1293 1294 ret = regmap_read(regmap, rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &val); 1295 if (ret) 1296 return -EINVAL; 1297 1298 if (!(val & SE_CMD_DFS_EN)) 1299 return 0; 1300 1301 /* 1302 * Rate changes with consumer writing a register in 1303 * their own I/O region 1304 */ 1305 init->flags |= CLK_GET_RATE_NOCACHE; 1306 init->ops = &clk_rcg2_dfs_ops; 1307 1308 rcg->freq_tbl = NULL; 1309 1310 return 0; 1311 } 1312 1313 int qcom_cc_register_rcg_dfs(struct regmap *regmap, 1314 const struct clk_rcg_dfs_data *rcgs, size_t len) 1315 { 1316 int i, ret; 1317 1318 for (i = 0; i < len; i++) { 1319 ret = clk_rcg2_enable_dfs(&rcgs[i], regmap); 1320 if (ret) 1321 return ret; 1322 } 1323 1324 return 0; 1325 } 1326 EXPORT_SYMBOL_GPL(qcom_cc_register_rcg_dfs); 1327 1328 static int clk_rcg2_dp_set_rate(struct clk_hw *hw, unsigned long rate, 1329 unsigned long parent_rate) 1330 { 1331 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 1332 struct freq_tbl f = { 0 }; 1333 u32 mask = BIT(rcg->hid_width) - 1; 1334 u32 hid_div, cfg; 1335 int i, num_parents = clk_hw_get_num_parents(hw); 1336 unsigned long num, den; 1337 1338 rational_best_approximation(parent_rate, rate, 1339 GENMASK(rcg->mnd_width - 1, 0), 1340 GENMASK(rcg->mnd_width - 1, 0), &den, &num); 1341 1342 if (!num || !den) 1343 return -EINVAL; 1344 1345 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); 1346 hid_div = cfg; 1347 cfg &= CFG_SRC_SEL_MASK; 1348 cfg >>= CFG_SRC_SEL_SHIFT; 1349 1350 for (i = 0; i < num_parents; i++) { 1351 if (cfg == rcg->parent_map[i].cfg) { 1352 f.src = rcg->parent_map[i].src; 1353 break; 1354 } 1355 } 1356 1357 f.pre_div = hid_div; 1358 f.pre_div >>= CFG_SRC_DIV_SHIFT; 1359 f.pre_div &= mask; 1360 1361 if (num != den) { 1362 f.m = num; 1363 f.n = den; 1364 } else { 1365 f.m = 0; 1366 f.n = 0; 1367 } 1368 1369 return clk_rcg2_configure(rcg, &f); 1370 } 1371 1372 static int clk_rcg2_dp_set_rate_and_parent(struct clk_hw *hw, 1373 unsigned long rate, unsigned long parent_rate, u8 index) 1374 { 1375 return clk_rcg2_dp_set_rate(hw, rate, parent_rate); 1376 } 1377 1378 static int clk_rcg2_dp_determine_rate(struct clk_hw *hw, 1379 struct clk_rate_request *req) 1380 { 1381 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 1382 unsigned long num, den; 1383 u64 tmp; 1384 1385 /* Parent rate is a fixed phy link rate */ 1386 rational_best_approximation(req->best_parent_rate, req->rate, 1387 GENMASK(rcg->mnd_width - 1, 0), 1388 GENMASK(rcg->mnd_width - 1, 0), &den, &num); 1389 1390 if (!num || !den) 1391 return -EINVAL; 1392 1393 tmp = req->best_parent_rate * num; 1394 do_div(tmp, den); 1395 req->rate = tmp; 1396 1397 return 0; 1398 } 1399 1400 const struct clk_ops clk_dp_ops = { 1401 .is_enabled = clk_rcg2_is_enabled, 1402 .get_parent = clk_rcg2_get_parent, 1403 .set_parent = clk_rcg2_set_parent, 1404 .recalc_rate = clk_rcg2_recalc_rate, 1405 .set_rate = clk_rcg2_dp_set_rate, 1406 .set_rate_and_parent = clk_rcg2_dp_set_rate_and_parent, 1407 .determine_rate = clk_rcg2_dp_determine_rate, 1408 }; 1409 EXPORT_SYMBOL_GPL(clk_dp_ops); 1410