1 /* 2 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #ifndef __QCOM_CLK_RCG_H__ 15 #define __QCOM_CLK_RCG_H__ 16 17 #include <linux/clk-provider.h> 18 #include "clk-regmap.h" 19 20 struct freq_tbl { 21 unsigned long freq; 22 u8 src; 23 u8 pre_div; 24 u16 m; 25 u16 n; 26 }; 27 28 /** 29 * struct parent_map - map table for PLL source select configuration values 30 * @src: source PLL 31 * @cfg: configuration value 32 */ 33 struct parent_map { 34 u8 src; 35 u8 cfg; 36 }; 37 38 /** 39 * struct mn - M/N:D counter 40 * @mnctr_en_bit: bit to enable mn counter 41 * @mnctr_reset_bit: bit to assert mn counter reset 42 * @mnctr_mode_shift: lowest bit of mn counter mode field 43 * @n_val_shift: lowest bit of n value field 44 * @m_val_shift: lowest bit of m value field 45 * @width: number of bits in m/n/d values 46 * @reset_in_cc: true if the mnctr_reset_bit is in the CC register 47 */ 48 struct mn { 49 u8 mnctr_en_bit; 50 u8 mnctr_reset_bit; 51 u8 mnctr_mode_shift; 52 #define MNCTR_MODE_DUAL 0x2 53 #define MNCTR_MODE_MASK 0x3 54 u8 n_val_shift; 55 u8 m_val_shift; 56 u8 width; 57 bool reset_in_cc; 58 }; 59 60 /** 61 * struct pre_div - pre-divider 62 * @pre_div_shift: lowest bit of pre divider field 63 * @pre_div_width: number of bits in predivider 64 */ 65 struct pre_div { 66 u8 pre_div_shift; 67 u8 pre_div_width; 68 }; 69 70 /** 71 * struct src_sel - source selector 72 * @src_sel_shift: lowest bit of source selection field 73 * @parent_map: map from software's parent index to hardware's src_sel field 74 */ 75 struct src_sel { 76 u8 src_sel_shift; 77 #define SRC_SEL_MASK 0x7 78 const struct parent_map *parent_map; 79 }; 80 81 /** 82 * struct clk_rcg - root clock generator 83 * 84 * @ns_reg: NS register 85 * @md_reg: MD register 86 * @mn: mn counter 87 * @p: pre divider 88 * @s: source selector 89 * @freq_tbl: frequency table 90 * @clkr: regmap clock handle 91 * @lock: register lock 92 * 93 */ 94 struct clk_rcg { 95 u32 ns_reg; 96 u32 md_reg; 97 98 struct mn mn; 99 struct pre_div p; 100 struct src_sel s; 101 102 const struct freq_tbl *freq_tbl; 103 104 struct clk_regmap clkr; 105 }; 106 107 extern const struct clk_ops clk_rcg_ops; 108 extern const struct clk_ops clk_rcg_bypass_ops; 109 extern const struct clk_ops clk_rcg_lcc_ops; 110 111 #define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr) 112 113 /** 114 * struct clk_dyn_rcg - root clock generator with glitch free mux 115 * 116 * @mux_sel_bit: bit to switch glitch free mux 117 * @ns_reg: NS0 and NS1 register 118 * @md_reg: MD0 and MD1 register 119 * @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux 120 * @mn: mn counter (banked) 121 * @s: source selector (banked) 122 * @freq_tbl: frequency table 123 * @clkr: regmap clock handle 124 * @lock: register lock 125 * 126 */ 127 struct clk_dyn_rcg { 128 u32 ns_reg[2]; 129 u32 md_reg[2]; 130 u32 bank_reg; 131 132 u8 mux_sel_bit; 133 134 struct mn mn[2]; 135 struct pre_div p[2]; 136 struct src_sel s[2]; 137 138 const struct freq_tbl *freq_tbl; 139 140 struct clk_regmap clkr; 141 }; 142 143 extern const struct clk_ops clk_dyn_rcg_ops; 144 145 #define to_clk_dyn_rcg(_hw) \ 146 container_of(to_clk_regmap(_hw), struct clk_dyn_rcg, clkr) 147 148 /** 149 * struct clk_rcg2 - root clock generator 150 * 151 * @cmd_rcgr: corresponds to *_CMD_RCGR 152 * @mnd_width: number of bits in m/n/d values 153 * @hid_width: number of bits in half integer divider 154 * @parent_map: map from software's parent index to hardware's src_sel field 155 * @freq_tbl: frequency table 156 * @clkr: regmap clock handle 157 * @lock: register lock 158 * 159 */ 160 struct clk_rcg2 { 161 u32 cmd_rcgr; 162 u8 mnd_width; 163 u8 hid_width; 164 const struct parent_map *parent_map; 165 const struct freq_tbl *freq_tbl; 166 struct clk_regmap clkr; 167 }; 168 169 #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr) 170 171 extern const struct clk_ops clk_rcg2_ops; 172 extern const struct clk_ops clk_edp_pixel_ops; 173 extern const struct clk_ops clk_byte_ops; 174 extern const struct clk_ops clk_pixel_ops; 175 176 #endif 177