1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2015, 2018, 2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 8 #ifndef __QCOM_CLK_ALPHA_PLL_H__ 9 #define __QCOM_CLK_ALPHA_PLL_H__ 10 11 #include <linux/clk-provider.h> 12 #include "clk-regmap.h" 13 14 /* Alpha PLL types */ 15 enum { 16 CLK_ALPHA_PLL_TYPE_DEFAULT, 17 CLK_ALPHA_PLL_TYPE_HUAYRA, 18 CLK_ALPHA_PLL_TYPE_BRAMMO, 19 CLK_ALPHA_PLL_TYPE_FABIA, 20 CLK_ALPHA_PLL_TYPE_TRION, 21 CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION, 22 CLK_ALPHA_PLL_TYPE_AGERA, 23 CLK_ALPHA_PLL_TYPE_ZONDA, 24 CLK_ALPHA_PLL_TYPE_ZONDA_OLE, 25 CLK_ALPHA_PLL_TYPE_LUCID_EVO, 26 CLK_ALPHA_PLL_TYPE_LUCID_OLE, 27 CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, 28 CLK_ALPHA_PLL_TYPE_DEFAULT_EVO, 29 CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, 30 CLK_ALPHA_PLL_TYPE_STROMER, 31 CLK_ALPHA_PLL_TYPE_STROMER_PLUS, 32 CLK_ALPHA_PLL_TYPE_MAX, 33 }; 34 35 enum { 36 PLL_OFF_L_VAL, 37 PLL_OFF_CAL_L_VAL, 38 PLL_OFF_ALPHA_VAL, 39 PLL_OFF_ALPHA_VAL_U, 40 PLL_OFF_USER_CTL, 41 PLL_OFF_USER_CTL_U, 42 PLL_OFF_USER_CTL_U1, 43 PLL_OFF_CONFIG_CTL, 44 PLL_OFF_CONFIG_CTL_U, 45 PLL_OFF_CONFIG_CTL_U1, 46 PLL_OFF_CONFIG_CTL_U2, 47 PLL_OFF_TEST_CTL, 48 PLL_OFF_TEST_CTL_U, 49 PLL_OFF_TEST_CTL_U1, 50 PLL_OFF_TEST_CTL_U2, 51 PLL_OFF_STATE, 52 PLL_OFF_STATUS, 53 PLL_OFF_OPMODE, 54 PLL_OFF_FRAC, 55 PLL_OFF_CAL_VAL, 56 PLL_OFF_MAX_REGS 57 }; 58 59 extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS]; 60 61 struct pll_vco { 62 unsigned long min_freq; 63 unsigned long max_freq; 64 u32 val; 65 }; 66 67 #define VCO(a, b, c) { \ 68 .val = a,\ 69 .min_freq = b,\ 70 .max_freq = c,\ 71 } 72 73 /** 74 * struct clk_alpha_pll - phase locked loop (PLL) 75 * @offset: base address of registers 76 * @vco_table: array of VCO settings 77 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 78 * @clkr: regmap clock handle 79 */ 80 struct clk_alpha_pll { 81 u32 offset; 82 const u8 *regs; 83 84 const struct pll_vco *vco_table; 85 size_t num_vco; 86 #define SUPPORTS_OFFLINE_REQ BIT(0) 87 #define SUPPORTS_FSM_MODE BIT(2) 88 #define SUPPORTS_DYNAMIC_UPDATE BIT(3) 89 #define SUPPORTS_FSM_LEGACY_MODE BIT(4) 90 u8 flags; 91 92 struct clk_regmap clkr; 93 }; 94 95 /** 96 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider 97 * @offset: base address of registers 98 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 99 * @width: width of post-divider 100 * @post_div_shift: shift to differentiate between odd & even post-divider 101 * @post_div_table: table with PLL odd and even post-divider settings 102 * @num_post_div: Number of PLL post-divider settings 103 * 104 * @clkr: regmap clock handle 105 */ 106 struct clk_alpha_pll_postdiv { 107 u32 offset; 108 u8 width; 109 const u8 *regs; 110 111 struct clk_regmap clkr; 112 int post_div_shift; 113 const struct clk_div_table *post_div_table; 114 size_t num_post_div; 115 }; 116 117 struct alpha_pll_config { 118 u32 l; 119 u32 alpha; 120 u32 alpha_hi; 121 u32 config_ctl_val; 122 u32 config_ctl_hi_val; 123 u32 config_ctl_hi1_val; 124 u32 config_ctl_hi2_val; 125 u32 user_ctl_val; 126 u32 user_ctl_hi_val; 127 u32 user_ctl_hi1_val; 128 u32 test_ctl_val; 129 u32 test_ctl_mask; 130 u32 test_ctl_hi_val; 131 u32 test_ctl_hi_mask; 132 u32 test_ctl_hi1_val; 133 u32 test_ctl_hi2_val; 134 u32 main_output_mask; 135 u32 aux_output_mask; 136 u32 aux2_output_mask; 137 u32 early_output_mask; 138 u32 alpha_en_mask; 139 u32 alpha_mode_mask; 140 u32 pre_div_val; 141 u32 pre_div_mask; 142 u32 post_div_val; 143 u32 post_div_mask; 144 u32 vco_val; 145 u32 vco_mask; 146 u32 status_val; 147 u32 status_mask; 148 u32 lock_det; 149 }; 150 151 extern const struct clk_ops clk_alpha_pll_ops; 152 extern const struct clk_ops clk_alpha_pll_fixed_ops; 153 extern const struct clk_ops clk_alpha_pll_hwfsm_ops; 154 extern const struct clk_ops clk_alpha_pll_postdiv_ops; 155 extern const struct clk_ops clk_alpha_pll_huayra_ops; 156 extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops; 157 extern const struct clk_ops clk_alpha_pll_stromer_ops; 158 extern const struct clk_ops clk_alpha_pll_stromer_plus_ops; 159 160 extern const struct clk_ops clk_alpha_pll_fabia_ops; 161 extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops; 162 extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops; 163 164 extern const struct clk_ops clk_alpha_pll_trion_ops; 165 extern const struct clk_ops clk_alpha_pll_fixed_trion_ops; 166 extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops; 167 168 extern const struct clk_ops clk_alpha_pll_lucid_ops; 169 #define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops 170 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops; 171 extern const struct clk_ops clk_alpha_pll_agera_ops; 172 173 extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops; 174 extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops; 175 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops; 176 177 extern const struct clk_ops clk_alpha_pll_zonda_ops; 178 #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops 179 #define clk_alpha_pll_zonda_ole_ops clk_alpha_pll_zonda_ops 180 181 extern const struct clk_ops clk_alpha_pll_lucid_evo_ops; 182 extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops; 183 #define clk_alpha_pll_reset_lucid_ole_ops clk_alpha_pll_reset_lucid_evo_ops 184 extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops; 185 #define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops 186 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; 187 #define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops 188 189 extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; 190 #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops 191 192 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 193 const struct alpha_pll_config *config); 194 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 195 const struct alpha_pll_config *config); 196 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 197 const struct alpha_pll_config *config); 198 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 199 const struct alpha_pll_config *config); 200 #define clk_lucid_pll_configure(pll, regmap, config) \ 201 clk_trion_pll_configure(pll, regmap, config) 202 203 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 204 const struct alpha_pll_config *config); 205 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 206 const struct alpha_pll_config *config); 207 void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 208 const struct alpha_pll_config *config); 209 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 210 const struct alpha_pll_config *config); 211 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 212 const struct alpha_pll_config *config); 213 214 #endif 215