1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */ 3 4 #ifndef __QCOM_CLK_ALPHA_PLL_H__ 5 #define __QCOM_CLK_ALPHA_PLL_H__ 6 7 #include <linux/clk-provider.h> 8 #include "clk-regmap.h" 9 10 /* Alpha PLL types */ 11 enum { 12 CLK_ALPHA_PLL_TYPE_DEFAULT, 13 CLK_ALPHA_PLL_TYPE_HUAYRA, 14 CLK_ALPHA_PLL_TYPE_BRAMMO, 15 CLK_ALPHA_PLL_TYPE_FABIA, 16 CLK_ALPHA_PLL_TYPE_TRION, 17 CLK_ALPHA_PLL_TYPE_LUCID, 18 CLK_ALPHA_PLL_TYPE_MAX, 19 }; 20 21 enum { 22 PLL_OFF_L_VAL, 23 PLL_OFF_CAL_L_VAL, 24 PLL_OFF_ALPHA_VAL, 25 PLL_OFF_ALPHA_VAL_U, 26 PLL_OFF_USER_CTL, 27 PLL_OFF_USER_CTL_U, 28 PLL_OFF_USER_CTL_U1, 29 PLL_OFF_CONFIG_CTL, 30 PLL_OFF_CONFIG_CTL_U, 31 PLL_OFF_CONFIG_CTL_U1, 32 PLL_OFF_TEST_CTL, 33 PLL_OFF_TEST_CTL_U, 34 PLL_OFF_TEST_CTL_U1, 35 PLL_OFF_STATUS, 36 PLL_OFF_OPMODE, 37 PLL_OFF_FRAC, 38 PLL_OFF_CAL_VAL, 39 PLL_OFF_MAX_REGS 40 }; 41 42 extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS]; 43 44 struct pll_vco { 45 unsigned long min_freq; 46 unsigned long max_freq; 47 u32 val; 48 }; 49 50 /** 51 * struct clk_alpha_pll - phase locked loop (PLL) 52 * @offset: base address of registers 53 * @vco_table: array of VCO settings 54 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 55 * @clkr: regmap clock handle 56 */ 57 struct clk_alpha_pll { 58 u32 offset; 59 const u8 *regs; 60 61 const struct pll_vco *vco_table; 62 size_t num_vco; 63 #define SUPPORTS_OFFLINE_REQ BIT(0) 64 #define SUPPORTS_FSM_MODE BIT(2) 65 #define SUPPORTS_DYNAMIC_UPDATE BIT(3) 66 u8 flags; 67 68 struct clk_regmap clkr; 69 }; 70 71 /** 72 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider 73 * @offset: base address of registers 74 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 75 * @width: width of post-divider 76 * @post_div_shift: shift to differentiate between odd & even post-divider 77 * @post_div_table: table with PLL odd and even post-divider settings 78 * @num_post_div: Number of PLL post-divider settings 79 * 80 * @clkr: regmap clock handle 81 */ 82 struct clk_alpha_pll_postdiv { 83 u32 offset; 84 u8 width; 85 const u8 *regs; 86 87 struct clk_regmap clkr; 88 int post_div_shift; 89 const struct clk_div_table *post_div_table; 90 size_t num_post_div; 91 }; 92 93 struct alpha_pll_config { 94 u32 l; 95 u32 alpha; 96 u32 alpha_hi; 97 u32 config_ctl_val; 98 u32 config_ctl_hi_val; 99 u32 config_ctl_hi1_val; 100 u32 user_ctl_val; 101 u32 user_ctl_hi_val; 102 u32 user_ctl_hi1_val; 103 u32 test_ctl_val; 104 u32 test_ctl_hi_val; 105 u32 test_ctl_hi1_val; 106 u32 main_output_mask; 107 u32 aux_output_mask; 108 u32 aux2_output_mask; 109 u32 early_output_mask; 110 u32 alpha_en_mask; 111 u32 alpha_mode_mask; 112 u32 pre_div_val; 113 u32 pre_div_mask; 114 u32 post_div_val; 115 u32 post_div_mask; 116 u32 vco_val; 117 u32 vco_mask; 118 }; 119 120 extern const struct clk_ops clk_alpha_pll_ops; 121 extern const struct clk_ops clk_alpha_pll_fixed_ops; 122 extern const struct clk_ops clk_alpha_pll_hwfsm_ops; 123 extern const struct clk_ops clk_alpha_pll_postdiv_ops; 124 extern const struct clk_ops clk_alpha_pll_huayra_ops; 125 extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops; 126 127 extern const struct clk_ops clk_alpha_pll_fabia_ops; 128 extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops; 129 extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops; 130 131 extern const struct clk_ops clk_alpha_pll_lucid_ops; 132 extern const struct clk_ops clk_alpha_pll_fixed_lucid_ops; 133 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops; 134 135 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 136 const struct alpha_pll_config *config); 137 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 138 const struct alpha_pll_config *config); 139 void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 140 const struct alpha_pll_config *config); 141 142 extern const struct clk_ops clk_trion_fixed_pll_ops; 143 extern const struct clk_ops clk_trion_pll_postdiv_ops; 144 145 #endif 146