1 /* 2 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #ifndef __QCOM_CLK_ALPHA_PLL_H__ 15 #define __QCOM_CLK_ALPHA_PLL_H__ 16 17 #include <linux/clk-provider.h> 18 #include "clk-regmap.h" 19 20 struct pll_vco { 21 unsigned long min_freq; 22 unsigned long max_freq; 23 u32 val; 24 }; 25 26 /** 27 * struct clk_alpha_pll - phase locked loop (PLL) 28 * @offset: base address of registers 29 * @vco_table: array of VCO settings 30 * @clkr: regmap clock handle 31 */ 32 struct clk_alpha_pll { 33 u32 offset; 34 35 const struct pll_vco *vco_table; 36 size_t num_vco; 37 38 struct clk_regmap clkr; 39 }; 40 41 /** 42 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider 43 * @offset: base address of registers 44 * @width: width of post-divider 45 * @clkr: regmap clock handle 46 */ 47 struct clk_alpha_pll_postdiv { 48 u32 offset; 49 u8 width; 50 51 struct clk_regmap clkr; 52 }; 53 54 extern const struct clk_ops clk_alpha_pll_ops; 55 extern const struct clk_ops clk_alpha_pll_postdiv_ops; 56 57 #endif 58