1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/export.h> 9 #include <linux/clk-provider.h> 10 #include <linux/regmap.h> 11 #include <linux/delay.h> 12 13 #include "clk-alpha-pll.h" 14 #include "common.h" 15 16 #define PLL_MODE(p) ((p)->offset + 0x0) 17 # define PLL_OUTCTRL BIT(0) 18 # define PLL_BYPASSNL BIT(1) 19 # define PLL_RESET_N BIT(2) 20 # define PLL_OFFLINE_REQ BIT(7) 21 # define PLL_LOCK_COUNT_SHIFT 8 22 # define PLL_LOCK_COUNT_MASK 0x3f 23 # define PLL_BIAS_COUNT_SHIFT 14 24 # define PLL_BIAS_COUNT_MASK 0x3f 25 # define PLL_VOTE_FSM_ENA BIT(20) 26 # define PLL_FSM_ENA BIT(20) 27 # define PLL_VOTE_FSM_RESET BIT(21) 28 # define PLL_UPDATE BIT(22) 29 # define PLL_UPDATE_BYPASS BIT(23) 30 # define PLL_FSM_LEGACY_MODE BIT(24) 31 # define PLL_OFFLINE_ACK BIT(28) 32 # define ALPHA_PLL_ACK_LATCH BIT(29) 33 # define PLL_ACTIVE_FLAG BIT(30) 34 # define PLL_LOCK_DET BIT(31) 35 36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL]) 37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL]) 38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL]) 39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U]) 40 41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) 42 # define PLL_POST_DIV_SHIFT 8 43 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width ? (p)->width - 1 : 3, 0) 44 # define PLL_ALPHA_MSB BIT(15) 45 # define PLL_ALPHA_EN BIT(24) 46 # define PLL_ALPHA_MODE BIT(25) 47 # define PLL_VCO_SHIFT 20 48 # define PLL_VCO_MASK 0x3 49 50 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U]) 51 #define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1]) 52 53 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL]) 54 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U]) 55 #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1]) 56 #define PLL_CONFIG_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U2]) 57 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) 58 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) 59 #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1]) 60 #define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2]) 61 #define PLL_TEST_CTL_U3(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U3]) 62 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) 63 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE]) 64 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC]) 65 66 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 67 [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 68 [PLL_OFF_L_VAL] = 0x04, 69 [PLL_OFF_ALPHA_VAL] = 0x08, 70 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 71 [PLL_OFF_USER_CTL] = 0x10, 72 [PLL_OFF_USER_CTL_U] = 0x14, 73 [PLL_OFF_CONFIG_CTL] = 0x18, 74 [PLL_OFF_TEST_CTL] = 0x1c, 75 [PLL_OFF_TEST_CTL_U] = 0x20, 76 [PLL_OFF_STATUS] = 0x24, 77 }, 78 [CLK_ALPHA_PLL_TYPE_HUAYRA] = { 79 [PLL_OFF_L_VAL] = 0x04, 80 [PLL_OFF_ALPHA_VAL] = 0x08, 81 [PLL_OFF_USER_CTL] = 0x10, 82 [PLL_OFF_CONFIG_CTL] = 0x14, 83 [PLL_OFF_CONFIG_CTL_U] = 0x18, 84 [PLL_OFF_TEST_CTL] = 0x1c, 85 [PLL_OFF_TEST_CTL_U] = 0x20, 86 [PLL_OFF_STATUS] = 0x24, 87 }, 88 [CLK_ALPHA_PLL_TYPE_HUAYRA_APSS] = { 89 [PLL_OFF_L_VAL] = 0x08, 90 [PLL_OFF_ALPHA_VAL] = 0x10, 91 [PLL_OFF_USER_CTL] = 0x18, 92 [PLL_OFF_CONFIG_CTL] = 0x20, 93 [PLL_OFF_CONFIG_CTL_U] = 0x24, 94 [PLL_OFF_STATUS] = 0x28, 95 [PLL_OFF_TEST_CTL] = 0x30, 96 [PLL_OFF_TEST_CTL_U] = 0x34, 97 }, 98 [CLK_ALPHA_PLL_TYPE_HUAYRA_2290] = { 99 [PLL_OFF_L_VAL] = 0x04, 100 [PLL_OFF_ALPHA_VAL] = 0x08, 101 [PLL_OFF_USER_CTL] = 0x0c, 102 [PLL_OFF_CONFIG_CTL] = 0x10, 103 [PLL_OFF_CONFIG_CTL_U] = 0x14, 104 [PLL_OFF_CONFIG_CTL_U1] = 0x18, 105 [PLL_OFF_TEST_CTL] = 0x1c, 106 [PLL_OFF_TEST_CTL_U] = 0x20, 107 [PLL_OFF_TEST_CTL_U1] = 0x24, 108 [PLL_OFF_OPMODE] = 0x28, 109 [PLL_OFF_STATUS] = 0x38, 110 }, 111 [CLK_ALPHA_PLL_TYPE_BRAMMO] = { 112 [PLL_OFF_L_VAL] = 0x04, 113 [PLL_OFF_ALPHA_VAL] = 0x08, 114 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 115 [PLL_OFF_USER_CTL] = 0x10, 116 [PLL_OFF_CONFIG_CTL] = 0x18, 117 [PLL_OFF_TEST_CTL] = 0x1c, 118 [PLL_OFF_STATUS] = 0x24, 119 }, 120 [CLK_ALPHA_PLL_TYPE_FABIA] = { 121 [PLL_OFF_L_VAL] = 0x04, 122 [PLL_OFF_USER_CTL] = 0x0c, 123 [PLL_OFF_USER_CTL_U] = 0x10, 124 [PLL_OFF_CONFIG_CTL] = 0x14, 125 [PLL_OFF_CONFIG_CTL_U] = 0x18, 126 [PLL_OFF_TEST_CTL] = 0x1c, 127 [PLL_OFF_TEST_CTL_U] = 0x20, 128 [PLL_OFF_STATUS] = 0x24, 129 [PLL_OFF_OPMODE] = 0x2c, 130 [PLL_OFF_FRAC] = 0x38, 131 }, 132 [CLK_ALPHA_PLL_TYPE_TRION] = { 133 [PLL_OFF_L_VAL] = 0x04, 134 [PLL_OFF_CAL_L_VAL] = 0x08, 135 [PLL_OFF_USER_CTL] = 0x0c, 136 [PLL_OFF_USER_CTL_U] = 0x10, 137 [PLL_OFF_USER_CTL_U1] = 0x14, 138 [PLL_OFF_CONFIG_CTL] = 0x18, 139 [PLL_OFF_CONFIG_CTL_U] = 0x1c, 140 [PLL_OFF_CONFIG_CTL_U1] = 0x20, 141 [PLL_OFF_TEST_CTL] = 0x24, 142 [PLL_OFF_TEST_CTL_U] = 0x28, 143 [PLL_OFF_TEST_CTL_U1] = 0x2c, 144 [PLL_OFF_STATUS] = 0x30, 145 [PLL_OFF_OPMODE] = 0x38, 146 [PLL_OFF_ALPHA_VAL] = 0x40, 147 }, 148 [CLK_ALPHA_PLL_TYPE_AGERA] = { 149 [PLL_OFF_L_VAL] = 0x04, 150 [PLL_OFF_ALPHA_VAL] = 0x08, 151 [PLL_OFF_USER_CTL] = 0x0c, 152 [PLL_OFF_CONFIG_CTL] = 0x10, 153 [PLL_OFF_CONFIG_CTL_U] = 0x14, 154 [PLL_OFF_TEST_CTL] = 0x18, 155 [PLL_OFF_TEST_CTL_U] = 0x1c, 156 [PLL_OFF_STATUS] = 0x2c, 157 }, 158 [CLK_ALPHA_PLL_TYPE_ZONDA] = { 159 [PLL_OFF_L_VAL] = 0x04, 160 [PLL_OFF_ALPHA_VAL] = 0x08, 161 [PLL_OFF_USER_CTL] = 0x0c, 162 [PLL_OFF_CONFIG_CTL] = 0x10, 163 [PLL_OFF_CONFIG_CTL_U] = 0x14, 164 [PLL_OFF_CONFIG_CTL_U1] = 0x18, 165 [PLL_OFF_TEST_CTL] = 0x1c, 166 [PLL_OFF_TEST_CTL_U] = 0x20, 167 [PLL_OFF_TEST_CTL_U1] = 0x24, 168 [PLL_OFF_OPMODE] = 0x28, 169 [PLL_OFF_STATUS] = 0x38, 170 }, 171 [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = { 172 [PLL_OFF_OPMODE] = 0x04, 173 [PLL_OFF_STATUS] = 0x0c, 174 [PLL_OFF_L_VAL] = 0x10, 175 [PLL_OFF_ALPHA_VAL] = 0x14, 176 [PLL_OFF_USER_CTL] = 0x18, 177 [PLL_OFF_USER_CTL_U] = 0x1c, 178 [PLL_OFF_CONFIG_CTL] = 0x20, 179 [PLL_OFF_CONFIG_CTL_U] = 0x24, 180 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 181 [PLL_OFF_TEST_CTL] = 0x2c, 182 [PLL_OFF_TEST_CTL_U] = 0x30, 183 [PLL_OFF_TEST_CTL_U1] = 0x34, 184 }, 185 [CLK_ALPHA_PLL_TYPE_LUCID_OLE] = { 186 [PLL_OFF_OPMODE] = 0x04, 187 [PLL_OFF_STATE] = 0x08, 188 [PLL_OFF_STATUS] = 0x0c, 189 [PLL_OFF_L_VAL] = 0x10, 190 [PLL_OFF_ALPHA_VAL] = 0x14, 191 [PLL_OFF_USER_CTL] = 0x18, 192 [PLL_OFF_USER_CTL_U] = 0x1c, 193 [PLL_OFF_CONFIG_CTL] = 0x20, 194 [PLL_OFF_CONFIG_CTL_U] = 0x24, 195 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 196 [PLL_OFF_TEST_CTL] = 0x2c, 197 [PLL_OFF_TEST_CTL_U] = 0x30, 198 [PLL_OFF_TEST_CTL_U1] = 0x34, 199 [PLL_OFF_TEST_CTL_U2] = 0x38, 200 }, 201 [CLK_ALPHA_PLL_TYPE_PONGO_ELU] = { 202 [PLL_OFF_OPMODE] = 0x04, 203 [PLL_OFF_STATE] = 0x08, 204 [PLL_OFF_STATUS] = 0x0c, 205 [PLL_OFF_L_VAL] = 0x10, 206 [PLL_OFF_USER_CTL] = 0x14, 207 [PLL_OFF_USER_CTL_U] = 0x18, 208 [PLL_OFF_CONFIG_CTL] = 0x1c, 209 [PLL_OFF_CONFIG_CTL_U] = 0x20, 210 [PLL_OFF_CONFIG_CTL_U1] = 0x24, 211 [PLL_OFF_CONFIG_CTL_U2] = 0x28, 212 [PLL_OFF_TEST_CTL] = 0x2c, 213 [PLL_OFF_TEST_CTL_U] = 0x30, 214 [PLL_OFF_TEST_CTL_U1] = 0x34, 215 [PLL_OFF_TEST_CTL_U2] = 0x38, 216 [PLL_OFF_TEST_CTL_U3] = 0x3c, 217 }, 218 [CLK_ALPHA_PLL_TYPE_TAYCAN_ELU] = { 219 [PLL_OFF_OPMODE] = 0x04, 220 [PLL_OFF_STATE] = 0x08, 221 [PLL_OFF_STATUS] = 0x0c, 222 [PLL_OFF_L_VAL] = 0x10, 223 [PLL_OFF_ALPHA_VAL] = 0x14, 224 [PLL_OFF_USER_CTL] = 0x18, 225 [PLL_OFF_USER_CTL_U] = 0x1c, 226 [PLL_OFF_CONFIG_CTL] = 0x20, 227 [PLL_OFF_CONFIG_CTL_U] = 0x24, 228 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 229 [PLL_OFF_TEST_CTL] = 0x2c, 230 [PLL_OFF_TEST_CTL_U] = 0x30, 231 }, 232 [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = { 233 [PLL_OFF_OPMODE] = 0x04, 234 [PLL_OFF_STATUS] = 0x0c, 235 [PLL_OFF_L_VAL] = 0x10, 236 [PLL_OFF_USER_CTL] = 0x14, 237 [PLL_OFF_USER_CTL_U] = 0x18, 238 [PLL_OFF_CONFIG_CTL] = 0x1c, 239 [PLL_OFF_CONFIG_CTL_U] = 0x20, 240 [PLL_OFF_CONFIG_CTL_U1] = 0x24, 241 [PLL_OFF_TEST_CTL] = 0x28, 242 [PLL_OFF_TEST_CTL_U] = 0x2c, 243 }, 244 [CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = { 245 [PLL_OFF_L_VAL] = 0x04, 246 [PLL_OFF_ALPHA_VAL] = 0x08, 247 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 248 [PLL_OFF_TEST_CTL] = 0x10, 249 [PLL_OFF_TEST_CTL_U] = 0x14, 250 [PLL_OFF_USER_CTL] = 0x18, 251 [PLL_OFF_USER_CTL_U] = 0x1c, 252 [PLL_OFF_CONFIG_CTL] = 0x20, 253 [PLL_OFF_STATUS] = 0x24, 254 }, 255 [CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = { 256 [PLL_OFF_L_VAL] = 0x04, 257 [PLL_OFF_ALPHA_VAL] = 0x08, 258 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 259 [PLL_OFF_TEST_CTL] = 0x10, 260 [PLL_OFF_TEST_CTL_U] = 0x14, 261 [PLL_OFF_USER_CTL] = 0x18, 262 [PLL_OFF_CONFIG_CTL] = 0x1C, 263 [PLL_OFF_STATUS] = 0x20, 264 }, 265 [CLK_ALPHA_PLL_TYPE_STROMER] = { 266 [PLL_OFF_L_VAL] = 0x08, 267 [PLL_OFF_ALPHA_VAL] = 0x10, 268 [PLL_OFF_ALPHA_VAL_U] = 0x14, 269 [PLL_OFF_USER_CTL] = 0x18, 270 [PLL_OFF_USER_CTL_U] = 0x1c, 271 [PLL_OFF_CONFIG_CTL] = 0x20, 272 [PLL_OFF_STATUS] = 0x28, 273 [PLL_OFF_TEST_CTL] = 0x30, 274 [PLL_OFF_TEST_CTL_U] = 0x34, 275 }, 276 [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = { 277 [PLL_OFF_L_VAL] = 0x04, 278 [PLL_OFF_USER_CTL] = 0x08, 279 [PLL_OFF_USER_CTL_U] = 0x0c, 280 [PLL_OFF_CONFIG_CTL] = 0x10, 281 [PLL_OFF_TEST_CTL] = 0x14, 282 [PLL_OFF_TEST_CTL_U] = 0x18, 283 [PLL_OFF_STATUS] = 0x1c, 284 [PLL_OFF_ALPHA_VAL] = 0x24, 285 [PLL_OFF_ALPHA_VAL_U] = 0x28, 286 }, 287 [CLK_ALPHA_PLL_TYPE_ZONDA_OLE] = { 288 [PLL_OFF_L_VAL] = 0x04, 289 [PLL_OFF_ALPHA_VAL] = 0x08, 290 [PLL_OFF_USER_CTL] = 0x0c, 291 [PLL_OFF_USER_CTL_U] = 0x10, 292 [PLL_OFF_CONFIG_CTL] = 0x14, 293 [PLL_OFF_CONFIG_CTL_U] = 0x18, 294 [PLL_OFF_CONFIG_CTL_U1] = 0x1c, 295 [PLL_OFF_CONFIG_CTL_U2] = 0x20, 296 [PLL_OFF_TEST_CTL] = 0x24, 297 [PLL_OFF_TEST_CTL_U] = 0x28, 298 [PLL_OFF_TEST_CTL_U1] = 0x2c, 299 [PLL_OFF_OPMODE] = 0x30, 300 [PLL_OFF_STATUS] = 0x3c, 301 }, 302 [CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] = { 303 [PLL_OFF_L_VAL] = 0x04, 304 [PLL_OFF_ALPHA_VAL] = 0x08, 305 [PLL_OFF_TEST_CTL] = 0x0c, 306 [PLL_OFF_TEST_CTL_U] = 0x10, 307 [PLL_OFF_USER_CTL] = 0x14, 308 [PLL_OFF_CONFIG_CTL] = 0x18, 309 [PLL_OFF_CONFIG_CTL_U] = 0x1c, 310 [PLL_OFF_STATUS] = 0x20, 311 }, 312 313 }; 314 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 315 316 /* 317 * Even though 40 bits are present, use only 32 for ease of calculation. 318 */ 319 #define ALPHA_REG_BITWIDTH 40 320 #define ALPHA_REG_16BIT_WIDTH 16 321 #define ALPHA_BITWIDTH 32U 322 #define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH) 323 324 #define ALPHA_PLL_STATUS_REG_SHIFT 8 325 326 #define PLL_HUAYRA_M_WIDTH 8 327 #define PLL_HUAYRA_M_SHIFT 8 328 #define PLL_HUAYRA_M_MASK 0xff 329 #define PLL_HUAYRA_N_SHIFT 0 330 #define PLL_HUAYRA_N_MASK 0xff 331 #define PLL_HUAYRA_ALPHA_WIDTH 16 332 333 #define PLL_STANDBY 0x0 334 #define PLL_RUN 0x1 335 #define PLL_OUT_MASK 0x7 336 #define PLL_RATE_MARGIN 500 337 338 /* TRION PLL specific settings and offsets */ 339 #define TRION_PLL_CAL_VAL 0x44 340 #define TRION_PCAL_DONE BIT(26) 341 342 /* LUCID PLL specific settings and offsets */ 343 #define LUCID_PCAL_DONE BIT(27) 344 345 /* LUCID 5LPE PLL specific settings and offsets */ 346 #define LUCID_5LPE_PCAL_DONE BIT(11) 347 #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13) 348 #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14) 349 #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) 350 351 /* LUCID EVO PLL specific settings and offsets */ 352 #define LUCID_EVO_PCAL_NOT_DONE BIT(8) 353 #define LUCID_EVO_ENABLE_VOTE_RUN BIT(25) 354 #define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0) 355 #define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16 356 #define LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT 24 357 358 /* PONGO ELU PLL specific setting and offsets */ 359 #define PONGO_PLL_OUT_MASK GENMASK(1, 0) 360 #define PONGO_PLL_L_VAL_MASK GENMASK(11, 0) 361 #define PONGO_XO_PRESENT BIT(10) 362 #define PONGO_CLOCK_SELECT BIT(12) 363 364 /* ZONDA PLL specific */ 365 #define ZONDA_PLL_OUT_MASK 0xf 366 #define ZONDA_STAY_IN_CFA BIT(16) 367 #define ZONDA_PLL_FREQ_LOCK_DET BIT(29) 368 369 #define pll_alpha_width(p) \ 370 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ 371 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) 372 373 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4) 374 375 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ 376 struct clk_alpha_pll, clkr) 377 378 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \ 379 struct clk_alpha_pll_postdiv, clkr) 380 381 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, 382 const char *action) 383 { 384 u32 val; 385 int count; 386 int ret; 387 const char *name = clk_hw_get_name(&pll->clkr.hw); 388 389 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 390 if (ret) 391 return ret; 392 393 /* Pongo PLLs using a 32KHz reference can take upwards of 1500us to lock. */ 394 for (count = 1500; count > 0; count--) { 395 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 396 if (ret) 397 return ret; 398 if (inverse && !(val & mask)) 399 return 0; 400 else if ((val & mask) == mask) 401 return 0; 402 403 udelay(1); 404 } 405 406 WARN(1, "%s failed to %s!\n", name, action); 407 return -ETIMEDOUT; 408 } 409 410 #define wait_for_pll_enable_active(pll) \ 411 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable") 412 413 #define wait_for_pll_enable_lock(pll) \ 414 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable") 415 416 #define wait_for_zonda_pll_freq_lock(pll) \ 417 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable") 418 419 #define wait_for_pll_disable(pll) \ 420 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable") 421 422 #define wait_for_pll_offline(pll) \ 423 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline") 424 425 #define wait_for_pll_update(pll) \ 426 wait_for_pll(pll, PLL_UPDATE, 1, "update") 427 428 #define wait_for_pll_update_ack_set(pll) \ 429 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set") 430 431 #define wait_for_pll_update_ack_clear(pll) \ 432 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear") 433 434 static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg, 435 unsigned int val) 436 { 437 if (val) 438 regmap_write(regmap, reg, val); 439 } 440 441 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 442 const struct alpha_pll_config *config) 443 { 444 u32 val, mask; 445 446 regmap_write(regmap, PLL_L_VAL(pll), config->l); 447 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); 448 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 449 450 if (pll_has_64bit_config(pll)) 451 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), 452 config->config_ctl_hi_val); 453 454 if (pll_alpha_width(pll) > 32) 455 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); 456 457 val = config->main_output_mask; 458 val |= config->aux_output_mask; 459 val |= config->aux2_output_mask; 460 val |= config->early_output_mask; 461 val |= config->pre_div_val; 462 val |= config->post_div_val; 463 val |= config->vco_val; 464 val |= config->alpha_en_mask; 465 val |= config->alpha_mode_mask; 466 467 mask = config->main_output_mask; 468 mask |= config->aux_output_mask; 469 mask |= config->aux2_output_mask; 470 mask |= config->early_output_mask; 471 mask |= config->pre_div_mask; 472 mask |= config->post_div_mask; 473 mask |= config->vco_mask; 474 mask |= config->alpha_en_mask; 475 mask |= config->alpha_mode_mask; 476 477 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 478 479 if (config->test_ctl_mask) 480 regmap_update_bits(regmap, PLL_TEST_CTL(pll), 481 config->test_ctl_mask, 482 config->test_ctl_val); 483 else 484 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 485 config->test_ctl_val); 486 487 if (config->test_ctl_hi_mask) 488 regmap_update_bits(regmap, PLL_TEST_CTL_U(pll), 489 config->test_ctl_hi_mask, 490 config->test_ctl_hi_val); 491 else 492 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 493 config->test_ctl_hi_val); 494 495 if (pll->flags & SUPPORTS_FSM_MODE) 496 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); 497 } 498 EXPORT_SYMBOL_GPL(clk_alpha_pll_configure); 499 500 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) 501 { 502 int ret; 503 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 504 u32 val; 505 506 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 507 if (ret) 508 return ret; 509 510 val |= PLL_FSM_ENA; 511 512 if (pll->flags & SUPPORTS_OFFLINE_REQ) 513 val &= ~PLL_OFFLINE_REQ; 514 515 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); 516 if (ret) 517 return ret; 518 519 /* Make sure enable request goes through before waiting for update */ 520 mb(); 521 522 return wait_for_pll_enable_active(pll); 523 } 524 525 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw) 526 { 527 int ret; 528 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 529 u32 val; 530 531 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 532 if (ret) 533 return; 534 535 if (pll->flags & SUPPORTS_OFFLINE_REQ) { 536 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 537 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ); 538 if (ret) 539 return; 540 541 ret = wait_for_pll_offline(pll); 542 if (ret) 543 return; 544 } 545 546 /* Disable hwfsm */ 547 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 548 PLL_FSM_ENA, 0); 549 if (ret) 550 return; 551 552 wait_for_pll_disable(pll); 553 } 554 555 static int pll_is_enabled(struct clk_hw *hw, u32 mask) 556 { 557 int ret; 558 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 559 u32 val; 560 561 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 562 if (ret) 563 return ret; 564 565 return !!(val & mask); 566 } 567 568 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw) 569 { 570 return pll_is_enabled(hw, PLL_ACTIVE_FLAG); 571 } 572 573 static int clk_alpha_pll_is_enabled(struct clk_hw *hw) 574 { 575 return pll_is_enabled(hw, PLL_LOCK_DET); 576 } 577 578 static int clk_alpha_pll_enable(struct clk_hw *hw) 579 { 580 int ret; 581 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 582 u32 val, mask; 583 584 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; 585 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 586 if (ret) 587 return ret; 588 589 /* If in FSM mode, just vote for it */ 590 if (val & PLL_VOTE_FSM_ENA) { 591 ret = clk_enable_regmap(hw); 592 if (ret) 593 return ret; 594 return wait_for_pll_enable_active(pll); 595 } 596 597 /* Skip if already enabled */ 598 if ((val & mask) == mask) 599 return 0; 600 601 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 602 PLL_BYPASSNL, PLL_BYPASSNL); 603 if (ret) 604 return ret; 605 606 /* 607 * H/W requires a 5us delay between disabling the bypass and 608 * de-asserting the reset. 609 */ 610 mb(); 611 udelay(5); 612 613 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 614 PLL_RESET_N, PLL_RESET_N); 615 if (ret) 616 return ret; 617 618 ret = wait_for_pll_enable_lock(pll); 619 if (ret) 620 return ret; 621 622 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 623 PLL_OUTCTRL, PLL_OUTCTRL); 624 625 /* Ensure that the write above goes through before returning. */ 626 mb(); 627 return ret; 628 } 629 630 static void clk_alpha_pll_disable(struct clk_hw *hw) 631 { 632 int ret; 633 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 634 u32 val, mask; 635 636 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 637 if (ret) 638 return; 639 640 /* If in FSM mode, just unvote it */ 641 if (val & PLL_VOTE_FSM_ENA) { 642 clk_disable_regmap(hw); 643 return; 644 } 645 646 mask = PLL_OUTCTRL; 647 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 648 649 /* Delay of 2 output clock ticks required until output is disabled */ 650 mb(); 651 udelay(1); 652 653 mask = PLL_RESET_N | PLL_BYPASSNL; 654 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 655 } 656 657 static unsigned long 658 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width) 659 { 660 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width)); 661 } 662 663 static unsigned long 664 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a, 665 u32 alpha_width) 666 { 667 u64 remainder; 668 u64 quotient; 669 670 quotient = rate; 671 remainder = do_div(quotient, prate); 672 *l = quotient; 673 674 if (!remainder) { 675 *a = 0; 676 return rate; 677 } 678 679 /* Upper ALPHA_BITWIDTH bits of Alpha */ 680 quotient = remainder << ALPHA_SHIFT(alpha_width); 681 682 remainder = do_div(quotient, prate); 683 684 if (remainder) 685 quotient++; 686 687 *a = quotient; 688 return alpha_pll_calc_rate(prate, *l, *a, alpha_width); 689 } 690 691 static const struct pll_vco * 692 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) 693 { 694 const struct pll_vco *v = pll->vco_table; 695 const struct pll_vco *end = v + pll->num_vco; 696 697 for (; v < end; v++) 698 if (rate >= v->min_freq && rate <= v->max_freq) 699 return v; 700 701 return NULL; 702 } 703 704 static unsigned long 705 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 706 { 707 u32 l, low, high, ctl; 708 u64 a = 0, prate = parent_rate; 709 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 710 u32 alpha_width = pll_alpha_width(pll); 711 712 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 713 714 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 715 if (ctl & PLL_ALPHA_EN) { 716 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); 717 if (alpha_width > 32) { 718 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 719 &high); 720 a = (u64)high << 32 | low; 721 } else { 722 a = low & GENMASK(alpha_width - 1, 0); 723 } 724 725 if (alpha_width > ALPHA_BITWIDTH) 726 a >>= alpha_width - ALPHA_BITWIDTH; 727 } 728 729 return alpha_pll_calc_rate(prate, l, a, alpha_width); 730 } 731 732 733 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) 734 { 735 int ret; 736 u32 mode; 737 738 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); 739 740 /* Latch the input to the PLL */ 741 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 742 PLL_UPDATE); 743 744 /* Wait for 2 reference cycle before checking ACK bit */ 745 udelay(1); 746 747 /* 748 * PLL will latch the new L, Alpha and freq control word. 749 * PLL will respond by raising PLL_ACK_LATCH output when new programming 750 * has been latched in and PLL is being updated. When 751 * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared 752 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. 753 */ 754 if (mode & PLL_UPDATE_BYPASS) { 755 ret = wait_for_pll_update_ack_set(pll); 756 if (ret) 757 return ret; 758 759 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); 760 } else { 761 ret = wait_for_pll_update(pll); 762 if (ret) 763 return ret; 764 } 765 766 ret = wait_for_pll_update_ack_clear(pll); 767 if (ret) 768 return ret; 769 770 /* Wait for PLL output to stabilize */ 771 udelay(10); 772 773 return 0; 774 } 775 776 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, 777 int (*is_enabled)(struct clk_hw *)) 778 { 779 if (!is_enabled(&pll->clkr.hw) || 780 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) 781 return 0; 782 783 return __clk_alpha_pll_update_latch(pll); 784 } 785 786 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 787 unsigned long prate, 788 int (*is_enabled)(struct clk_hw *)) 789 { 790 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 791 const struct pll_vco *vco; 792 u32 l, alpha_width = pll_alpha_width(pll); 793 u64 a; 794 795 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 796 vco = alpha_pll_find_vco(pll, rate); 797 if (pll->vco_table && !vco) { 798 pr_err("%s: alpha pll not in a valid vco range\n", 799 clk_hw_get_name(hw)); 800 return -EINVAL; 801 } 802 803 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 804 805 if (alpha_width > ALPHA_BITWIDTH) 806 a <<= alpha_width - ALPHA_BITWIDTH; 807 808 if (alpha_width > 32) 809 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); 810 811 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 812 813 if (vco) { 814 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 815 PLL_VCO_MASK << PLL_VCO_SHIFT, 816 vco->val << PLL_VCO_SHIFT); 817 } 818 819 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 820 PLL_ALPHA_EN, PLL_ALPHA_EN); 821 822 return clk_alpha_pll_update_latch(pll, is_enabled); 823 } 824 825 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 826 unsigned long prate) 827 { 828 return __clk_alpha_pll_set_rate(hw, rate, prate, 829 clk_alpha_pll_is_enabled); 830 } 831 832 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate, 833 unsigned long prate) 834 { 835 return __clk_alpha_pll_set_rate(hw, rate, prate, 836 clk_alpha_pll_hwfsm_is_enabled); 837 } 838 839 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, 840 unsigned long *prate) 841 { 842 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 843 u32 l, alpha_width = pll_alpha_width(pll); 844 u64 a; 845 unsigned long min_freq, max_freq; 846 847 rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width); 848 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) 849 return rate; 850 851 min_freq = pll->vco_table[0].min_freq; 852 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 853 854 return clamp(rate, min_freq, max_freq); 855 } 856 857 void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 858 const struct alpha_pll_config *config) 859 { 860 u32 val; 861 862 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 863 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 864 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 865 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 866 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 867 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 868 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 869 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 870 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 871 872 /* Set PLL_BYPASSNL */ 873 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); 874 regmap_read(regmap, PLL_MODE(pll), &val); 875 876 /* Wait 5 us between setting BYPASS and deasserting reset */ 877 udelay(5); 878 879 /* Take PLL out from reset state */ 880 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 881 regmap_read(regmap, PLL_MODE(pll), &val); 882 883 /* Wait 50us for PLL_LOCK_DET bit to go high */ 884 usleep_range(50, 55); 885 886 /* Enable PLL output */ 887 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 888 } 889 EXPORT_SYMBOL_GPL(clk_huayra_2290_pll_configure); 890 891 static unsigned long 892 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a) 893 { 894 /* 895 * a contains 16 bit alpha_val in two’s complement number in the range 896 * of [-0.5, 0.5). 897 */ 898 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 899 l -= 1; 900 901 return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH); 902 } 903 904 static unsigned long 905 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate, 906 u32 *l, u32 *a) 907 { 908 u64 remainder; 909 u64 quotient; 910 911 quotient = rate; 912 remainder = do_div(quotient, prate); 913 *l = quotient; 914 915 if (!remainder) { 916 *a = 0; 917 return rate; 918 } 919 920 quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH; 921 remainder = do_div(quotient, prate); 922 923 if (remainder) 924 quotient++; 925 926 /* 927 * alpha_val should be in two’s complement number in the range 928 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value 929 * since alpha value will be subtracted in this case. 930 */ 931 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 932 *l += 1; 933 934 *a = quotient; 935 return alpha_huayra_pll_calc_rate(prate, *l, *a); 936 } 937 938 static unsigned long 939 alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 940 { 941 u64 rate = parent_rate, tmp; 942 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 943 u32 l, alpha = 0, ctl, alpha_m, alpha_n; 944 945 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 946 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 947 948 if (ctl & PLL_ALPHA_EN) { 949 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); 950 /* 951 * Depending upon alpha_mode, it can be treated as M/N value or 952 * as a two’s complement number. When alpha_mode=1, 953 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N 954 * 955 * Fout=FIN*(L+(M/N)) 956 * 957 * M is a signed number (-128 to 127) and N is unsigned 958 * (0 to 255). M/N has to be within +/-0.5. 959 * 960 * When alpha_mode=0, it is a two’s complement number in the 961 * range [-0.5, 0.5). 962 * 963 * Fout=FIN*(L+(alpha_val)/2^16) 964 * 965 * where alpha_val is two’s complement number. 966 */ 967 if (!(ctl & PLL_ALPHA_MODE)) 968 return alpha_huayra_pll_calc_rate(rate, l, alpha); 969 970 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK; 971 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK; 972 973 rate *= l; 974 tmp = parent_rate; 975 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) { 976 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m; 977 tmp *= alpha_m; 978 do_div(tmp, alpha_n); 979 rate -= tmp; 980 } else { 981 tmp *= alpha_m; 982 do_div(tmp, alpha_n); 983 rate += tmp; 984 } 985 986 return rate; 987 } 988 989 return alpha_huayra_pll_calc_rate(rate, l, alpha); 990 } 991 992 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate, 993 unsigned long prate) 994 { 995 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 996 u32 l, a, ctl, cur_alpha = 0; 997 998 rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a); 999 1000 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 1001 1002 if (ctl & PLL_ALPHA_EN) 1003 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); 1004 1005 /* 1006 * Huayra PLL supports PLL dynamic programming. User can change L_VAL, 1007 * without having to go through the power on sequence. 1008 */ 1009 if (clk_alpha_pll_is_enabled(hw)) { 1010 if (cur_alpha != a) { 1011 pr_err("%s: clock needs to be gated\n", 1012 clk_hw_get_name(hw)); 1013 return -EBUSY; 1014 } 1015 1016 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1017 /* Ensure that the write above goes to detect L val change. */ 1018 mb(); 1019 return wait_for_pll_enable_lock(pll); 1020 } 1021 1022 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1023 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1024 1025 if (a == 0) 1026 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1027 PLL_ALPHA_EN, 0x0); 1028 else 1029 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1030 PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN); 1031 1032 return 0; 1033 } 1034 1035 static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate, 1036 unsigned long *prate) 1037 { 1038 u32 l, a; 1039 1040 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a); 1041 } 1042 1043 static int trion_pll_is_enabled(struct clk_alpha_pll *pll, 1044 struct regmap *regmap) 1045 { 1046 u32 mode_val, opmode_val; 1047 int ret; 1048 1049 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); 1050 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 1051 if (ret) 1052 return 0; 1053 1054 return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL)); 1055 } 1056 1057 static int clk_trion_pll_is_enabled(struct clk_hw *hw) 1058 { 1059 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1060 1061 return trion_pll_is_enabled(pll, pll->clkr.regmap); 1062 } 1063 1064 static int clk_trion_pll_enable(struct clk_hw *hw) 1065 { 1066 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1067 struct regmap *regmap = pll->clkr.regmap; 1068 u32 val; 1069 int ret; 1070 1071 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1072 if (ret) 1073 return ret; 1074 1075 /* If in FSM mode, just vote for it */ 1076 if (val & PLL_VOTE_FSM_ENA) { 1077 ret = clk_enable_regmap(hw); 1078 if (ret) 1079 return ret; 1080 return wait_for_pll_enable_active(pll); 1081 } 1082 1083 /* Set operation mode to RUN */ 1084 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 1085 1086 ret = wait_for_pll_enable_lock(pll); 1087 if (ret) 1088 return ret; 1089 1090 /* Enable the PLL outputs */ 1091 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1092 PLL_OUT_MASK, PLL_OUT_MASK); 1093 if (ret) 1094 return ret; 1095 1096 /* Enable the global PLL outputs */ 1097 return regmap_update_bits(regmap, PLL_MODE(pll), 1098 PLL_OUTCTRL, PLL_OUTCTRL); 1099 } 1100 1101 static void clk_trion_pll_disable(struct clk_hw *hw) 1102 { 1103 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1104 struct regmap *regmap = pll->clkr.regmap; 1105 u32 val; 1106 int ret; 1107 1108 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1109 if (ret) 1110 return; 1111 1112 /* If in FSM mode, just unvote it */ 1113 if (val & PLL_VOTE_FSM_ENA) { 1114 clk_disable_regmap(hw); 1115 return; 1116 } 1117 1118 /* Disable the global PLL output */ 1119 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1120 if (ret) 1121 return; 1122 1123 /* Disable the PLL outputs */ 1124 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1125 PLL_OUT_MASK, 0); 1126 if (ret) 1127 return; 1128 1129 /* Place the PLL mode in STANDBY */ 1130 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1131 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1132 } 1133 1134 static unsigned long 1135 clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1136 { 1137 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1138 u32 l, frac, alpha_width = pll_alpha_width(pll); 1139 1140 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 1141 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac); 1142 1143 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 1144 } 1145 1146 const struct clk_ops clk_alpha_pll_fixed_ops = { 1147 .enable = clk_alpha_pll_enable, 1148 .disable = clk_alpha_pll_disable, 1149 .is_enabled = clk_alpha_pll_is_enabled, 1150 .recalc_rate = clk_alpha_pll_recalc_rate, 1151 }; 1152 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops); 1153 1154 const struct clk_ops clk_alpha_pll_ops = { 1155 .enable = clk_alpha_pll_enable, 1156 .disable = clk_alpha_pll_disable, 1157 .is_enabled = clk_alpha_pll_is_enabled, 1158 .recalc_rate = clk_alpha_pll_recalc_rate, 1159 .round_rate = clk_alpha_pll_round_rate, 1160 .set_rate = clk_alpha_pll_set_rate, 1161 }; 1162 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops); 1163 1164 const struct clk_ops clk_alpha_pll_huayra_ops = { 1165 .enable = clk_alpha_pll_enable, 1166 .disable = clk_alpha_pll_disable, 1167 .is_enabled = clk_alpha_pll_is_enabled, 1168 .recalc_rate = alpha_pll_huayra_recalc_rate, 1169 .round_rate = alpha_pll_huayra_round_rate, 1170 .set_rate = alpha_pll_huayra_set_rate, 1171 }; 1172 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops); 1173 1174 const struct clk_ops clk_alpha_pll_hwfsm_ops = { 1175 .enable = clk_alpha_pll_hwfsm_enable, 1176 .disable = clk_alpha_pll_hwfsm_disable, 1177 .is_enabled = clk_alpha_pll_hwfsm_is_enabled, 1178 .recalc_rate = clk_alpha_pll_recalc_rate, 1179 .round_rate = clk_alpha_pll_round_rate, 1180 .set_rate = clk_alpha_pll_hwfsm_set_rate, 1181 }; 1182 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); 1183 1184 const struct clk_ops clk_alpha_pll_fixed_trion_ops = { 1185 .enable = clk_trion_pll_enable, 1186 .disable = clk_trion_pll_disable, 1187 .is_enabled = clk_trion_pll_is_enabled, 1188 .recalc_rate = clk_trion_pll_recalc_rate, 1189 .round_rate = clk_alpha_pll_round_rate, 1190 }; 1191 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops); 1192 1193 static unsigned long 1194 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1195 { 1196 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1197 u32 ctl; 1198 1199 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 1200 1201 ctl >>= PLL_POST_DIV_SHIFT; 1202 ctl &= PLL_POST_DIV_MASK(pll); 1203 1204 return parent_rate >> fls(ctl); 1205 } 1206 1207 static const struct clk_div_table clk_alpha_div_table[] = { 1208 { 0x0, 1 }, 1209 { 0x1, 2 }, 1210 { 0x3, 4 }, 1211 { 0x7, 8 }, 1212 { 0xf, 16 }, 1213 { } 1214 }; 1215 1216 static const struct clk_div_table clk_alpha_2bit_div_table[] = { 1217 { 0x0, 1 }, 1218 { 0x1, 2 }, 1219 { 0x3, 4 }, 1220 { } 1221 }; 1222 1223 static long 1224 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, 1225 unsigned long *prate) 1226 { 1227 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1228 const struct clk_div_table *table; 1229 1230 if (pll->width == 2) 1231 table = clk_alpha_2bit_div_table; 1232 else 1233 table = clk_alpha_div_table; 1234 1235 return divider_round_rate(hw, rate, prate, table, 1236 pll->width, CLK_DIVIDER_POWER_OF_TWO); 1237 } 1238 1239 static long 1240 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate, 1241 unsigned long *prate) 1242 { 1243 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1244 u32 ctl, div; 1245 1246 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 1247 1248 ctl >>= PLL_POST_DIV_SHIFT; 1249 ctl &= BIT(pll->width) - 1; 1250 div = 1 << fls(ctl); 1251 1252 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) 1253 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate); 1254 1255 return DIV_ROUND_UP_ULL((u64)*prate, div); 1256 } 1257 1258 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1259 unsigned long parent_rate) 1260 { 1261 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1262 int div; 1263 1264 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ 1265 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1; 1266 1267 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1268 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 1269 div << PLL_POST_DIV_SHIFT); 1270 } 1271 1272 const struct clk_ops clk_alpha_pll_postdiv_ops = { 1273 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1274 .round_rate = clk_alpha_pll_postdiv_round_rate, 1275 .set_rate = clk_alpha_pll_postdiv_set_rate, 1276 }; 1277 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops); 1278 1279 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = { 1280 .round_rate = clk_alpha_pll_postdiv_round_ro_rate, 1281 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1282 }; 1283 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops); 1284 1285 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1286 const struct alpha_pll_config *config) 1287 { 1288 u32 val, mask; 1289 1290 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1291 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha); 1292 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1293 config->config_ctl_val); 1294 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1295 config->config_ctl_hi_val); 1296 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1297 config->user_ctl_val); 1298 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1299 config->user_ctl_hi_val); 1300 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1301 config->test_ctl_val); 1302 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1303 config->test_ctl_hi_val); 1304 1305 if (config->post_div_mask) { 1306 mask = config->post_div_mask; 1307 val = config->post_div_val; 1308 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 1309 } 1310 1311 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE) 1312 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE, 1313 PLL_FSM_LEGACY_MODE); 1314 1315 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1316 PLL_UPDATE_BYPASS); 1317 1318 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1319 } 1320 EXPORT_SYMBOL_GPL(clk_fabia_pll_configure); 1321 1322 static int alpha_pll_fabia_enable(struct clk_hw *hw) 1323 { 1324 int ret; 1325 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1326 u32 val, opmode_val; 1327 struct regmap *regmap = pll->clkr.regmap; 1328 1329 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1330 if (ret) 1331 return ret; 1332 1333 /* If in FSM mode, just vote for it */ 1334 if (val & PLL_VOTE_FSM_ENA) { 1335 ret = clk_enable_regmap(hw); 1336 if (ret) 1337 return ret; 1338 return wait_for_pll_enable_active(pll); 1339 } 1340 1341 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 1342 if (ret) 1343 return ret; 1344 1345 /* Skip If PLL is already running */ 1346 if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL)) 1347 return 0; 1348 1349 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1350 if (ret) 1351 return ret; 1352 1353 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1354 if (ret) 1355 return ret; 1356 1357 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 1358 PLL_RESET_N); 1359 if (ret) 1360 return ret; 1361 1362 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 1363 if (ret) 1364 return ret; 1365 1366 ret = wait_for_pll_enable_lock(pll); 1367 if (ret) 1368 return ret; 1369 1370 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1371 PLL_OUT_MASK, PLL_OUT_MASK); 1372 if (ret) 1373 return ret; 1374 1375 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 1376 PLL_OUTCTRL); 1377 } 1378 1379 static void alpha_pll_fabia_disable(struct clk_hw *hw) 1380 { 1381 int ret; 1382 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1383 u32 val; 1384 struct regmap *regmap = pll->clkr.regmap; 1385 1386 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1387 if (ret) 1388 return; 1389 1390 /* If in FSM mode, just unvote it */ 1391 if (val & PLL_FSM_ENA) { 1392 clk_disable_regmap(hw); 1393 return; 1394 } 1395 1396 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1397 if (ret) 1398 return; 1399 1400 /* Disable main outputs */ 1401 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 1402 if (ret) 1403 return; 1404 1405 /* Place the PLL in STANDBY */ 1406 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1407 } 1408 1409 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw, 1410 unsigned long parent_rate) 1411 { 1412 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1413 u32 l, frac, alpha_width = pll_alpha_width(pll); 1414 1415 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 1416 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac); 1417 1418 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 1419 } 1420 1421 /* 1422 * Due to limited number of bits for fractional rate programming, the 1423 * rounded up rate could be marginally higher than the requested rate. 1424 */ 1425 static int alpha_pll_check_rate_margin(struct clk_hw *hw, 1426 unsigned long rrate, unsigned long rate) 1427 { 1428 unsigned long rate_margin = rate + PLL_RATE_MARGIN; 1429 1430 if (rrate > rate_margin || rrate < rate) { 1431 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n", 1432 clk_hw_get_name(hw), rrate, rate, rate_margin); 1433 return -EINVAL; 1434 } 1435 1436 return 0; 1437 } 1438 1439 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate, 1440 unsigned long prate) 1441 { 1442 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1443 u32 l, alpha_width = pll_alpha_width(pll); 1444 unsigned long rrate; 1445 int ret; 1446 u64 a; 1447 1448 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1449 1450 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1451 if (ret < 0) 1452 return ret; 1453 1454 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1455 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); 1456 1457 return __clk_alpha_pll_update_latch(pll); 1458 } 1459 1460 static int alpha_pll_fabia_prepare(struct clk_hw *hw) 1461 { 1462 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1463 const struct pll_vco *vco; 1464 struct clk_hw *parent_hw; 1465 unsigned long cal_freq, rrate; 1466 u32 cal_l, val, alpha_width = pll_alpha_width(pll); 1467 const char *name = clk_hw_get_name(hw); 1468 u64 a; 1469 int ret; 1470 1471 /* Check if calibration needs to be done i.e. PLL is in reset */ 1472 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1473 if (ret) 1474 return ret; 1475 1476 /* Return early if calibration is not needed. */ 1477 if (val & PLL_RESET_N) 1478 return 0; 1479 1480 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); 1481 if (!vco) { 1482 pr_err("%s: alpha pll not in a valid vco range\n", name); 1483 return -EINVAL; 1484 } 1485 1486 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq + 1487 pll->vco_table[0].max_freq) * 54, 100); 1488 1489 parent_hw = clk_hw_get_parent(hw); 1490 if (!parent_hw) 1491 return -EINVAL; 1492 1493 rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw), 1494 &cal_l, &a, alpha_width); 1495 1496 ret = alpha_pll_check_rate_margin(hw, rrate, cal_freq); 1497 if (ret < 0) 1498 return ret; 1499 1500 /* Setup PLL for calibration frequency */ 1501 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l); 1502 1503 /* Bringup the PLL at calibration frequency */ 1504 ret = clk_alpha_pll_enable(hw); 1505 if (ret) { 1506 pr_err("%s: alpha pll calibration failed\n", name); 1507 return ret; 1508 } 1509 1510 clk_alpha_pll_disable(hw); 1511 1512 return 0; 1513 } 1514 1515 const struct clk_ops clk_alpha_pll_fabia_ops = { 1516 .prepare = alpha_pll_fabia_prepare, 1517 .enable = alpha_pll_fabia_enable, 1518 .disable = alpha_pll_fabia_disable, 1519 .is_enabled = clk_alpha_pll_is_enabled, 1520 .set_rate = alpha_pll_fabia_set_rate, 1521 .recalc_rate = alpha_pll_fabia_recalc_rate, 1522 .round_rate = clk_alpha_pll_round_rate, 1523 }; 1524 EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops); 1525 1526 const struct clk_ops clk_alpha_pll_fixed_fabia_ops = { 1527 .enable = alpha_pll_fabia_enable, 1528 .disable = alpha_pll_fabia_disable, 1529 .is_enabled = clk_alpha_pll_is_enabled, 1530 .recalc_rate = alpha_pll_fabia_recalc_rate, 1531 .round_rate = clk_alpha_pll_round_rate, 1532 }; 1533 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops); 1534 1535 static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw, 1536 unsigned long parent_rate) 1537 { 1538 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1539 u32 i, div = 1, val; 1540 int ret; 1541 1542 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1543 if (ret) 1544 return ret; 1545 1546 val >>= pll->post_div_shift; 1547 val &= BIT(pll->width) - 1; 1548 1549 for (i = 0; i < pll->num_post_div; i++) { 1550 if (pll->post_div_table[i].val == val) { 1551 div = pll->post_div_table[i].div; 1552 break; 1553 } 1554 } 1555 1556 return (parent_rate / div); 1557 } 1558 1559 static unsigned long 1560 clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1561 { 1562 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1563 struct regmap *regmap = pll->clkr.regmap; 1564 u32 i, div = 1, val; 1565 1566 regmap_read(regmap, PLL_USER_CTL(pll), &val); 1567 1568 val >>= pll->post_div_shift; 1569 val &= PLL_POST_DIV_MASK(pll); 1570 1571 for (i = 0; i < pll->num_post_div; i++) { 1572 if (pll->post_div_table[i].val == val) { 1573 div = pll->post_div_table[i].div; 1574 break; 1575 } 1576 } 1577 1578 return (parent_rate / div); 1579 } 1580 1581 static long 1582 clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, 1583 unsigned long *prate) 1584 { 1585 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1586 1587 return divider_round_rate(hw, rate, prate, pll->post_div_table, 1588 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1589 }; 1590 1591 static int 1592 clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1593 unsigned long parent_rate) 1594 { 1595 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1596 struct regmap *regmap = pll->clkr.regmap; 1597 int i, val = 0, div; 1598 1599 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1600 for (i = 0; i < pll->num_post_div; i++) { 1601 if (pll->post_div_table[i].div == div) { 1602 val = pll->post_div_table[i].val; 1603 break; 1604 } 1605 } 1606 1607 return regmap_update_bits(regmap, PLL_USER_CTL(pll), 1608 PLL_POST_DIV_MASK(pll) << pll->post_div_shift, 1609 val << pll->post_div_shift); 1610 } 1611 1612 const struct clk_ops clk_alpha_pll_postdiv_trion_ops = { 1613 .recalc_rate = clk_trion_pll_postdiv_recalc_rate, 1614 .round_rate = clk_trion_pll_postdiv_round_rate, 1615 .set_rate = clk_trion_pll_postdiv_set_rate, 1616 }; 1617 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops); 1618 1619 static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw, 1620 unsigned long rate, unsigned long *prate) 1621 { 1622 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1623 1624 return divider_round_rate(hw, rate, prate, pll->post_div_table, 1625 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1626 } 1627 1628 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw, 1629 unsigned long rate, unsigned long parent_rate) 1630 { 1631 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1632 int i, val = 0, div, ret; 1633 1634 /* 1635 * If the PLL is in FSM mode, then treat set_rate callback as a 1636 * no-operation. 1637 */ 1638 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1639 if (ret) 1640 return ret; 1641 1642 if (val & PLL_VOTE_FSM_ENA) 1643 return 0; 1644 1645 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1646 for (i = 0; i < pll->num_post_div; i++) { 1647 if (pll->post_div_table[i].div == div) { 1648 val = pll->post_div_table[i].val; 1649 break; 1650 } 1651 } 1652 1653 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1654 (BIT(pll->width) - 1) << pll->post_div_shift, 1655 val << pll->post_div_shift); 1656 } 1657 1658 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = { 1659 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1660 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1661 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1662 }; 1663 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops); 1664 1665 /** 1666 * clk_trion_pll_configure - configure the trion pll 1667 * 1668 * @pll: clk alpha pll 1669 * @regmap: register map 1670 * @config: configuration to apply for pll 1671 */ 1672 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1673 const struct alpha_pll_config *config) 1674 { 1675 /* 1676 * If the bootloader left the PLL enabled it's likely that there are 1677 * RCGs that will lock up if we disable the PLL below. 1678 */ 1679 if (trion_pll_is_enabled(pll, regmap)) { 1680 pr_debug("Trion PLL is already enabled, skipping configuration\n"); 1681 return; 1682 } 1683 1684 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1685 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); 1686 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1687 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1688 config->config_ctl_val); 1689 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1690 config->config_ctl_hi_val); 1691 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), 1692 config->config_ctl_hi1_val); 1693 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1694 config->user_ctl_val); 1695 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1696 config->user_ctl_hi_val); 1697 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), 1698 config->user_ctl_hi1_val); 1699 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1700 config->test_ctl_val); 1701 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1702 config->test_ctl_hi_val); 1703 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), 1704 config->test_ctl_hi1_val); 1705 1706 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1707 PLL_UPDATE_BYPASS); 1708 1709 /* Disable PLL output */ 1710 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1711 1712 /* Set operation mode to OFF */ 1713 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1714 1715 /* Place the PLL in STANDBY mode */ 1716 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1717 } 1718 EXPORT_SYMBOL_GPL(clk_trion_pll_configure); 1719 1720 /* 1721 * The TRION PLL requires a power-on self-calibration which happens when the 1722 * PLL comes out of reset. Calibrate in case it is not completed. 1723 */ 1724 static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done) 1725 { 1726 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1727 u32 val; 1728 int ret; 1729 1730 /* Return early if calibration is not needed. */ 1731 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); 1732 if (val & pcal_done) 1733 return 0; 1734 1735 /* On/off to calibrate */ 1736 ret = clk_trion_pll_enable(hw); 1737 if (!ret) 1738 clk_trion_pll_disable(hw); 1739 1740 return ret; 1741 } 1742 1743 static int alpha_pll_trion_prepare(struct clk_hw *hw) 1744 { 1745 return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE); 1746 } 1747 1748 static int alpha_pll_lucid_prepare(struct clk_hw *hw) 1749 { 1750 return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE); 1751 } 1752 1753 static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1754 unsigned long prate, u32 latch_bit, u32 latch_ack) 1755 { 1756 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1757 unsigned long rrate; 1758 u32 val, l, alpha_width = pll_alpha_width(pll); 1759 u64 a; 1760 int ret; 1761 1762 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1763 1764 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1765 if (ret < 0) 1766 return ret; 1767 1768 regmap_update_bits(pll->clkr.regmap, PLL_L_VAL(pll), LUCID_EVO_PLL_L_VAL_MASK, l); 1769 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1770 1771 /* Latch the PLL input */ 1772 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); 1773 if (ret) 1774 return ret; 1775 1776 /* Wait for 2 reference cycles before checking the ACK bit. */ 1777 udelay(1); 1778 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1779 if (!(val & latch_ack)) { 1780 pr_err("Lucid PLL latch failed. Output may be unstable!\n"); 1781 return -EINVAL; 1782 } 1783 1784 /* Return the latch input to 0 */ 1785 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); 1786 if (ret) 1787 return ret; 1788 1789 if (clk_hw_is_enabled(hw)) { 1790 ret = wait_for_pll_enable_lock(pll); 1791 if (ret) 1792 return ret; 1793 } 1794 1795 /* Wait for PLL output to stabilize */ 1796 udelay(100); 1797 return 0; 1798 } 1799 1800 static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1801 unsigned long prate) 1802 { 1803 return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH); 1804 } 1805 1806 const struct clk_ops clk_alpha_pll_trion_ops = { 1807 .prepare = alpha_pll_trion_prepare, 1808 .enable = clk_trion_pll_enable, 1809 .disable = clk_trion_pll_disable, 1810 .is_enabled = clk_trion_pll_is_enabled, 1811 .recalc_rate = clk_trion_pll_recalc_rate, 1812 .round_rate = clk_alpha_pll_round_rate, 1813 .set_rate = alpha_pll_trion_set_rate, 1814 }; 1815 EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops); 1816 1817 const struct clk_ops clk_alpha_pll_lucid_ops = { 1818 .prepare = alpha_pll_lucid_prepare, 1819 .enable = clk_trion_pll_enable, 1820 .disable = clk_trion_pll_disable, 1821 .is_enabled = clk_trion_pll_is_enabled, 1822 .recalc_rate = clk_trion_pll_recalc_rate, 1823 .round_rate = clk_alpha_pll_round_rate, 1824 .set_rate = alpha_pll_trion_set_rate, 1825 }; 1826 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops); 1827 1828 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { 1829 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1830 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1831 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1832 }; 1833 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops); 1834 1835 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1836 const struct alpha_pll_config *config) 1837 { 1838 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1839 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1840 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1841 config->user_ctl_val); 1842 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1843 config->config_ctl_val); 1844 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1845 config->config_ctl_hi_val); 1846 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1847 config->test_ctl_val); 1848 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1849 config->test_ctl_hi_val); 1850 } 1851 EXPORT_SYMBOL_GPL(clk_agera_pll_configure); 1852 1853 static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate, 1854 unsigned long prate) 1855 { 1856 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1857 u32 l, alpha_width = pll_alpha_width(pll); 1858 int ret; 1859 unsigned long rrate; 1860 u64 a; 1861 1862 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1863 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1864 if (ret < 0) 1865 return ret; 1866 1867 /* change L_VAL without having to go through the power on sequence */ 1868 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1869 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1870 1871 if (clk_hw_is_enabled(hw)) 1872 return wait_for_pll_enable_lock(pll); 1873 1874 return 0; 1875 } 1876 1877 const struct clk_ops clk_alpha_pll_agera_ops = { 1878 .enable = clk_alpha_pll_enable, 1879 .disable = clk_alpha_pll_disable, 1880 .is_enabled = clk_alpha_pll_is_enabled, 1881 .recalc_rate = alpha_pll_fabia_recalc_rate, 1882 .round_rate = clk_alpha_pll_round_rate, 1883 .set_rate = clk_alpha_pll_agera_set_rate, 1884 }; 1885 EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops); 1886 1887 /** 1888 * clk_lucid_5lpe_pll_configure - configure the lucid 5lpe pll 1889 * 1890 * @pll: clk alpha pll 1891 * @regmap: register map 1892 * @config: configuration to apply for pll 1893 */ 1894 void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1895 const struct alpha_pll_config *config) 1896 { 1897 /* 1898 * If the bootloader left the PLL enabled it's likely that there are 1899 * RCGs that will lock up if we disable the PLL below. 1900 */ 1901 if (trion_pll_is_enabled(pll, regmap)) { 1902 pr_debug("Lucid 5LPE PLL is already enabled, skipping configuration\n"); 1903 return; 1904 } 1905 1906 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1907 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); 1908 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1909 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1910 config->config_ctl_val); 1911 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1912 config->config_ctl_hi_val); 1913 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), 1914 config->config_ctl_hi1_val); 1915 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1916 config->user_ctl_val); 1917 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1918 config->user_ctl_hi_val); 1919 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), 1920 config->user_ctl_hi1_val); 1921 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1922 config->test_ctl_val); 1923 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1924 config->test_ctl_hi_val); 1925 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), 1926 config->test_ctl_hi1_val); 1927 1928 /* Disable PLL output */ 1929 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1930 1931 /* Set operation mode to OFF */ 1932 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1933 1934 /* Place the PLL in STANDBY mode */ 1935 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1936 } 1937 EXPORT_SYMBOL_GPL(clk_lucid_5lpe_pll_configure); 1938 1939 static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw) 1940 { 1941 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1942 u32 val; 1943 int ret; 1944 1945 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1946 if (ret) 1947 return ret; 1948 1949 /* If in FSM mode, just vote for it */ 1950 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 1951 ret = clk_enable_regmap(hw); 1952 if (ret) 1953 return ret; 1954 return wait_for_pll_enable_lock(pll); 1955 } 1956 1957 /* Check if PLL is already enabled, return if enabled */ 1958 if (trion_pll_is_enabled(pll, pll->clkr.regmap)) 1959 return 0; 1960 1961 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1962 if (ret) 1963 return ret; 1964 1965 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); 1966 1967 ret = wait_for_pll_enable_lock(pll); 1968 if (ret) 1969 return ret; 1970 1971 /* Enable the PLL outputs */ 1972 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 1973 if (ret) 1974 return ret; 1975 1976 /* Enable the global PLL outputs */ 1977 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 1978 } 1979 1980 static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw) 1981 { 1982 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1983 u32 val; 1984 int ret; 1985 1986 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1987 if (ret) 1988 return; 1989 1990 /* If in FSM mode, just unvote it */ 1991 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 1992 clk_disable_regmap(hw); 1993 return; 1994 } 1995 1996 /* Disable the global PLL output */ 1997 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1998 if (ret) 1999 return; 2000 2001 /* Disable the PLL outputs */ 2002 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 2003 if (ret) 2004 return; 2005 2006 /* Place the PLL mode in STANDBY */ 2007 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY); 2008 } 2009 2010 /* 2011 * The Lucid 5LPE PLL requires a power-on self-calibration which happens 2012 * when the PLL comes out of reset. Calibrate in case it is not completed. 2013 */ 2014 static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw) 2015 { 2016 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2017 struct clk_hw *p; 2018 u32 val = 0; 2019 int ret; 2020 2021 /* Return early if calibration is not needed. */ 2022 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 2023 if (val & LUCID_5LPE_PCAL_DONE) 2024 return 0; 2025 2026 p = clk_hw_get_parent(hw); 2027 if (!p) 2028 return -EINVAL; 2029 2030 ret = alpha_pll_lucid_5lpe_enable(hw); 2031 if (ret) 2032 return ret; 2033 2034 alpha_pll_lucid_5lpe_disable(hw); 2035 2036 return 0; 2037 } 2038 2039 static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate, 2040 unsigned long prate) 2041 { 2042 return __alpha_pll_trion_set_rate(hw, rate, prate, 2043 LUCID_5LPE_PLL_LATCH_INPUT, 2044 LUCID_5LPE_ALPHA_PLL_ACK_LATCH); 2045 } 2046 2047 static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 2048 unsigned long parent_rate, 2049 unsigned long enable_vote_run) 2050 { 2051 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 2052 struct regmap *regmap = pll->clkr.regmap; 2053 int i, val, div, ret; 2054 u32 mask; 2055 2056 /* 2057 * If the PLL is in FSM mode, then treat set_rate callback as a 2058 * no-operation. 2059 */ 2060 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2061 if (ret) 2062 return ret; 2063 2064 if (val & enable_vote_run) 2065 return 0; 2066 2067 if (!pll->post_div_table) { 2068 pr_err("Missing the post_div_table for the %s PLL\n", 2069 clk_hw_get_name(&pll->clkr.hw)); 2070 return -EINVAL; 2071 } 2072 2073 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); 2074 for (i = 0; i < pll->num_post_div; i++) { 2075 if (pll->post_div_table[i].div == div) { 2076 val = pll->post_div_table[i].val; 2077 break; 2078 } 2079 } 2080 2081 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); 2082 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 2083 mask, val << pll->post_div_shift); 2084 } 2085 2086 static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 2087 unsigned long parent_rate) 2088 { 2089 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN); 2090 } 2091 2092 const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = { 2093 .prepare = alpha_pll_lucid_5lpe_prepare, 2094 .enable = alpha_pll_lucid_5lpe_enable, 2095 .disable = alpha_pll_lucid_5lpe_disable, 2096 .is_enabled = clk_trion_pll_is_enabled, 2097 .recalc_rate = clk_trion_pll_recalc_rate, 2098 .round_rate = clk_alpha_pll_round_rate, 2099 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2100 }; 2101 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops); 2102 2103 const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = { 2104 .enable = alpha_pll_lucid_5lpe_enable, 2105 .disable = alpha_pll_lucid_5lpe_disable, 2106 .is_enabled = clk_trion_pll_is_enabled, 2107 .recalc_rate = clk_trion_pll_recalc_rate, 2108 .round_rate = clk_alpha_pll_round_rate, 2109 }; 2110 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops); 2111 2112 const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = { 2113 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 2114 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 2115 .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate, 2116 }; 2117 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops); 2118 2119 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2120 const struct alpha_pll_config *config) 2121 { 2122 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2123 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2124 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2125 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2126 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2127 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2128 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2129 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); 2130 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2131 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2132 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2133 2134 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0); 2135 2136 /* Disable PLL output */ 2137 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2138 2139 /* Set operation mode to OFF */ 2140 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2141 2142 /* Place the PLL in STANDBY mode */ 2143 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2144 } 2145 EXPORT_SYMBOL_GPL(clk_zonda_pll_configure); 2146 2147 static int clk_zonda_pll_enable(struct clk_hw *hw) 2148 { 2149 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2150 struct regmap *regmap = pll->clkr.regmap; 2151 u32 val; 2152 int ret; 2153 2154 regmap_read(regmap, PLL_MODE(pll), &val); 2155 2156 /* If in FSM mode, just vote for it */ 2157 if (val & PLL_VOTE_FSM_ENA) { 2158 ret = clk_enable_regmap(hw); 2159 if (ret) 2160 return ret; 2161 return wait_for_pll_enable_active(pll); 2162 } 2163 2164 /* Get the PLL out of bypass mode */ 2165 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); 2166 2167 /* 2168 * H/W requires a 1us delay between disabling the bypass and 2169 * de-asserting the reset. 2170 */ 2171 udelay(1); 2172 2173 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2174 2175 /* Set operation mode to RUN */ 2176 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2177 2178 regmap_read(regmap, PLL_TEST_CTL(pll), &val); 2179 2180 /* If cfa mode then poll for freq lock */ 2181 if (val & ZONDA_STAY_IN_CFA) 2182 ret = wait_for_zonda_pll_freq_lock(pll); 2183 else 2184 ret = wait_for_pll_enable_lock(pll); 2185 if (ret) 2186 return ret; 2187 2188 /* Enable the PLL outputs */ 2189 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK); 2190 2191 /* Enable the global PLL outputs */ 2192 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2193 2194 return 0; 2195 } 2196 2197 static void clk_zonda_pll_disable(struct clk_hw *hw) 2198 { 2199 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2200 struct regmap *regmap = pll->clkr.regmap; 2201 u32 val; 2202 2203 regmap_read(regmap, PLL_MODE(pll), &val); 2204 2205 /* If in FSM mode, just unvote it */ 2206 if (val & PLL_VOTE_FSM_ENA) { 2207 clk_disable_regmap(hw); 2208 return; 2209 } 2210 2211 /* Disable the global PLL output */ 2212 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2213 2214 /* Disable the PLL outputs */ 2215 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0); 2216 2217 /* Put the PLL in bypass and reset */ 2218 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0); 2219 2220 /* Place the PLL mode in OFF state */ 2221 regmap_write(regmap, PLL_OPMODE(pll), 0x0); 2222 } 2223 2224 static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32 *l) 2225 { 2226 u64 remainder, quotient; 2227 2228 quotient = rate; 2229 remainder = do_div(quotient, prate); 2230 2231 *l = rate + (u32)(remainder * 2 >= prate); 2232 } 2233 2234 static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, 2235 unsigned long prate) 2236 { 2237 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2238 unsigned long rrate; 2239 u32 test_ctl_val; 2240 u32 l, alpha_width = pll_alpha_width(pll); 2241 u64 a; 2242 int ret; 2243 2244 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 2245 2246 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 2247 if (ret < 0) 2248 return ret; 2249 2250 if (a & PLL_ALPHA_MSB) 2251 zonda_pll_adjust_l_val(rate, prate, &l); 2252 2253 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2254 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2255 2256 if (!clk_hw_is_enabled(hw)) 2257 return 0; 2258 2259 /* Wait before polling for the frequency latch */ 2260 udelay(5); 2261 2262 /* Read stay in cfa mode */ 2263 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val); 2264 2265 /* If cfa mode then poll for freq lock */ 2266 if (test_ctl_val & ZONDA_STAY_IN_CFA) 2267 ret = wait_for_zonda_pll_freq_lock(pll); 2268 else 2269 ret = wait_for_pll_enable_lock(pll); 2270 if (ret) 2271 return ret; 2272 2273 /* Wait for PLL output to stabilize */ 2274 udelay(100); 2275 return 0; 2276 } 2277 2278 const struct clk_ops clk_alpha_pll_zonda_ops = { 2279 .enable = clk_zonda_pll_enable, 2280 .disable = clk_zonda_pll_disable, 2281 .is_enabled = clk_trion_pll_is_enabled, 2282 .recalc_rate = clk_trion_pll_recalc_rate, 2283 .round_rate = clk_alpha_pll_round_rate, 2284 .set_rate = clk_zonda_pll_set_rate, 2285 }; 2286 EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops); 2287 2288 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2289 const struct alpha_pll_config *config) 2290 { 2291 u32 lval = config->l; 2292 2293 /* 2294 * If the bootloader left the PLL enabled it's likely that there are 2295 * RCGs that will lock up if we disable the PLL below. 2296 */ 2297 if (trion_pll_is_enabled(pll, regmap)) { 2298 pr_debug("Lucid Evo PLL is already enabled, skipping configuration\n"); 2299 return; 2300 } 2301 2302 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT; 2303 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); 2304 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2305 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2306 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2307 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2308 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2309 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2310 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2311 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2312 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2313 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); 2314 2315 /* Disable PLL output */ 2316 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2317 2318 /* Set operation mode to STANDBY and de-assert the reset */ 2319 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2320 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2321 } 2322 EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure); 2323 2324 void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2325 const struct alpha_pll_config *config) 2326 { 2327 u32 lval = config->l; 2328 2329 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT; 2330 lval |= TRION_PLL_CAL_VAL << LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT; 2331 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); 2332 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2333 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2334 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2335 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2336 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2337 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2338 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2339 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2340 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2341 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); 2342 2343 /* Disable PLL output */ 2344 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2345 2346 /* Set operation mode to STANDBY and de-assert the reset */ 2347 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2348 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2349 } 2350 EXPORT_SYMBOL_GPL(clk_lucid_ole_pll_configure); 2351 2352 static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) 2353 { 2354 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2355 struct regmap *regmap = pll->clkr.regmap; 2356 u32 val; 2357 int ret; 2358 2359 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2360 if (ret) 2361 return ret; 2362 2363 /* If in FSM mode, just vote for it */ 2364 if (val & LUCID_EVO_ENABLE_VOTE_RUN) { 2365 ret = clk_enable_regmap(hw); 2366 if (ret) 2367 return ret; 2368 return wait_for_pll_enable_lock(pll); 2369 } 2370 2371 /* Check if PLL is already enabled */ 2372 if (trion_pll_is_enabled(pll, regmap)) 2373 return 0; 2374 2375 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2376 if (ret) 2377 return ret; 2378 2379 /* Set operation mode to RUN */ 2380 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2381 2382 ret = wait_for_pll_enable_lock(pll); 2383 if (ret) 2384 return ret; 2385 2386 /* Enable the PLL outputs */ 2387 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 2388 if (ret) 2389 return ret; 2390 2391 /* Enable the global PLL outputs */ 2392 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2393 if (ret) 2394 return ret; 2395 2396 /* Ensure that the write above goes through before returning. */ 2397 mb(); 2398 return ret; 2399 } 2400 2401 static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset) 2402 { 2403 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2404 struct regmap *regmap = pll->clkr.regmap; 2405 u32 val; 2406 int ret; 2407 2408 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2409 if (ret) 2410 return; 2411 2412 /* If in FSM mode, just unvote it */ 2413 if (val & LUCID_EVO_ENABLE_VOTE_RUN) { 2414 clk_disable_regmap(hw); 2415 return; 2416 } 2417 2418 /* Disable the global PLL output */ 2419 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2420 if (ret) 2421 return; 2422 2423 /* Disable the PLL outputs */ 2424 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 2425 if (ret) 2426 return; 2427 2428 /* Place the PLL mode in STANDBY */ 2429 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2430 2431 if (reset) 2432 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0); 2433 } 2434 2435 static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset) 2436 { 2437 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2438 struct clk_hw *p; 2439 u32 val = 0; 2440 int ret; 2441 2442 /* Return early if calibration is not needed. */ 2443 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 2444 if (!(val & LUCID_EVO_PCAL_NOT_DONE)) 2445 return 0; 2446 2447 p = clk_hw_get_parent(hw); 2448 if (!p) 2449 return -EINVAL; 2450 2451 ret = alpha_pll_lucid_evo_enable(hw); 2452 if (ret) 2453 return ret; 2454 2455 _alpha_pll_lucid_evo_disable(hw, reset); 2456 2457 return 0; 2458 } 2459 2460 static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) 2461 { 2462 _alpha_pll_lucid_evo_disable(hw, false); 2463 } 2464 2465 static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw) 2466 { 2467 return _alpha_pll_lucid_evo_prepare(hw, false); 2468 } 2469 2470 static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw) 2471 { 2472 _alpha_pll_lucid_evo_disable(hw, true); 2473 } 2474 2475 static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw) 2476 { 2477 return _alpha_pll_lucid_evo_prepare(hw, true); 2478 } 2479 2480 static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, 2481 unsigned long parent_rate) 2482 { 2483 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2484 struct regmap *regmap = pll->clkr.regmap; 2485 u32 l, frac; 2486 2487 regmap_read(regmap, PLL_L_VAL(pll), &l); 2488 l &= LUCID_EVO_PLL_L_VAL_MASK; 2489 regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac); 2490 2491 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); 2492 } 2493 2494 static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 2495 unsigned long parent_rate) 2496 { 2497 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN); 2498 } 2499 2500 const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = { 2501 .enable = alpha_pll_lucid_evo_enable, 2502 .disable = alpha_pll_lucid_evo_disable, 2503 .is_enabled = clk_trion_pll_is_enabled, 2504 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2505 .round_rate = clk_alpha_pll_round_rate, 2506 }; 2507 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops); 2508 2509 const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = { 2510 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 2511 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 2512 .set_rate = clk_lucid_evo_pll_postdiv_set_rate, 2513 }; 2514 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops); 2515 2516 const struct clk_ops clk_alpha_pll_lucid_evo_ops = { 2517 .prepare = alpha_pll_lucid_evo_prepare, 2518 .enable = alpha_pll_lucid_evo_enable, 2519 .disable = alpha_pll_lucid_evo_disable, 2520 .is_enabled = clk_trion_pll_is_enabled, 2521 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2522 .round_rate = clk_alpha_pll_round_rate, 2523 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2524 }; 2525 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops); 2526 2527 const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = { 2528 .prepare = alpha_pll_reset_lucid_evo_prepare, 2529 .enable = alpha_pll_lucid_evo_enable, 2530 .disable = alpha_pll_reset_lucid_evo_disable, 2531 .is_enabled = clk_trion_pll_is_enabled, 2532 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2533 .round_rate = clk_alpha_pll_round_rate, 2534 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2535 }; 2536 EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops); 2537 2538 static int alpha_pll_pongo_elu_prepare(struct clk_hw *hw) 2539 { 2540 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2541 struct regmap *regmap = pll->clkr.regmap; 2542 int ret; 2543 2544 /* Enable PLL intially to one-time calibrate against XO. */ 2545 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2546 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2547 regmap_update_bits(regmap, PLL_MODE(pll), PONGO_XO_PRESENT, PONGO_XO_PRESENT); 2548 2549 /* Set regmap for wait_for_pll() */ 2550 pll->clkr.regmap = regmap; 2551 ret = wait_for_pll_enable_lock(pll); 2552 if (ret) { 2553 /* Reverse calibration - disable PLL output */ 2554 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2555 return ret; 2556 } 2557 2558 /* Disable PLL after one-time calibration. */ 2559 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2560 2561 /* Select internally generated clock. */ 2562 regmap_update_bits(regmap, PLL_MODE(pll), PONGO_CLOCK_SELECT, 2563 PONGO_CLOCK_SELECT); 2564 2565 return 0; 2566 } 2567 2568 static int alpha_pll_pongo_elu_enable(struct clk_hw *hw) 2569 { 2570 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2571 struct regmap *regmap = pll->clkr.regmap; 2572 int ret; 2573 2574 /* Check if PLL is already enabled */ 2575 if (trion_pll_is_enabled(pll, regmap)) 2576 return 0; 2577 2578 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2579 if (ret) 2580 return ret; 2581 2582 /* Set operation mode to RUN */ 2583 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2584 2585 ret = wait_for_pll_enable_lock(pll); 2586 if (ret) 2587 return ret; 2588 2589 /* Enable the global PLL outputs */ 2590 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2591 if (ret) 2592 return ret; 2593 2594 /* Ensure that the write above goes through before returning. */ 2595 mb(); 2596 2597 return ret; 2598 } 2599 2600 static void alpha_pll_pongo_elu_disable(struct clk_hw *hw) 2601 { 2602 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2603 struct regmap *regmap = pll->clkr.regmap; 2604 int ret; 2605 2606 /* Disable the global PLL output */ 2607 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2608 if (ret) 2609 return; 2610 2611 /* Place the PLL mode in STANDBY */ 2612 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2613 } 2614 2615 static unsigned long alpha_pll_pongo_elu_recalc_rate(struct clk_hw *hw, 2616 unsigned long parent_rate) 2617 { 2618 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2619 struct regmap *regmap = pll->clkr.regmap; 2620 u32 l; 2621 2622 if (regmap_read(regmap, PLL_L_VAL(pll), &l)) 2623 return 0; 2624 2625 l &= PONGO_PLL_L_VAL_MASK; 2626 2627 return alpha_pll_calc_rate(parent_rate, l, 0, pll_alpha_width(pll)); 2628 } 2629 2630 const struct clk_ops clk_alpha_pll_pongo_elu_ops = { 2631 .prepare = alpha_pll_pongo_elu_prepare, 2632 .enable = alpha_pll_pongo_elu_enable, 2633 .disable = alpha_pll_pongo_elu_disable, 2634 .recalc_rate = alpha_pll_pongo_elu_recalc_rate, 2635 }; 2636 EXPORT_SYMBOL_GPL(clk_alpha_pll_pongo_elu_ops); 2637 2638 void clk_pongo_elu_pll_configure(struct clk_alpha_pll *pll, 2639 struct regmap *regmap, 2640 const struct alpha_pll_config *config) 2641 { 2642 u32 val; 2643 2644 regmap_update_bits(regmap, PLL_USER_CTL(pll), PONGO_PLL_OUT_MASK, 2645 PONGO_PLL_OUT_MASK); 2646 2647 if (trion_pll_is_enabled(pll, regmap)) 2648 return; 2649 2650 if (regmap_read(regmap, PLL_L_VAL(pll), &val)) 2651 return; 2652 val &= PONGO_PLL_L_VAL_MASK; 2653 if (val) 2654 return; 2655 2656 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2657 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2658 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2659 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2660 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2661 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U2(pll), config->config_ctl_hi2_val); 2662 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 2663 config->user_ctl_val | PONGO_PLL_OUT_MASK); 2664 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2665 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2666 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2667 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2668 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); 2669 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U3(pll), config->test_ctl_hi3_val); 2670 2671 /* Disable PLL output */ 2672 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2673 } 2674 EXPORT_SYMBOL_GPL(clk_pongo_elu_pll_configure); 2675 2676 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2677 const struct alpha_pll_config *config) 2678 { 2679 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2680 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2681 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2682 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2683 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2684 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2685 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2686 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2687 2688 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2689 2690 regmap_update_bits(regmap, PLL_MODE(pll), 2691 PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL, 2692 PLL_RESET_N | PLL_BYPASSNL); 2693 } 2694 EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure); 2695 2696 static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw, 2697 unsigned long parent_rate) 2698 { 2699 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2700 u32 l; 2701 2702 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 2703 2704 return parent_rate * l; 2705 } 2706 2707 static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate, 2708 unsigned long *prate) 2709 { 2710 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2711 unsigned long min_freq, max_freq; 2712 u32 l; 2713 u64 a; 2714 2715 rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0); 2716 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) 2717 return rate; 2718 2719 min_freq = pll->vco_table[0].min_freq; 2720 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 2721 2722 return clamp(rate, min_freq, max_freq); 2723 } 2724 2725 const struct clk_ops clk_alpha_pll_rivian_evo_ops = { 2726 .enable = alpha_pll_lucid_5lpe_enable, 2727 .disable = alpha_pll_lucid_5lpe_disable, 2728 .is_enabled = clk_trion_pll_is_enabled, 2729 .recalc_rate = clk_rivian_evo_pll_recalc_rate, 2730 .round_rate = clk_rivian_evo_pll_round_rate, 2731 }; 2732 EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops); 2733 2734 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2735 const struct alpha_pll_config *config) 2736 { 2737 u32 val, val_u, mask, mask_u; 2738 2739 regmap_write(regmap, PLL_L_VAL(pll), config->l); 2740 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2741 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2742 2743 if (pll_has_64bit_config(pll)) 2744 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), 2745 config->config_ctl_hi_val); 2746 2747 if (pll_alpha_width(pll) > 32) 2748 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); 2749 2750 val = config->main_output_mask; 2751 val |= config->aux_output_mask; 2752 val |= config->aux2_output_mask; 2753 val |= config->early_output_mask; 2754 val |= config->pre_div_val; 2755 val |= config->post_div_val; 2756 val |= config->vco_val; 2757 val |= config->alpha_en_mask; 2758 val |= config->alpha_mode_mask; 2759 2760 mask = config->main_output_mask; 2761 mask |= config->aux_output_mask; 2762 mask |= config->aux2_output_mask; 2763 mask |= config->early_output_mask; 2764 mask |= config->pre_div_mask; 2765 mask |= config->post_div_mask; 2766 mask |= config->vco_mask; 2767 mask |= config->alpha_en_mask; 2768 mask |= config->alpha_mode_mask; 2769 2770 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 2771 2772 /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */ 2773 val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT; 2774 val_u |= config->lock_det; 2775 2776 mask_u = config->status_mask; 2777 mask_u |= config->lock_det; 2778 2779 regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u); 2780 regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2781 regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2782 2783 if (pll->flags & SUPPORTS_FSM_MODE) 2784 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); 2785 } 2786 EXPORT_SYMBOL_GPL(clk_stromer_pll_configure); 2787 2788 static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw, 2789 struct clk_rate_request *req) 2790 { 2791 u32 l; 2792 u64 a; 2793 2794 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, 2795 &l, &a, ALPHA_REG_BITWIDTH); 2796 2797 return 0; 2798 } 2799 2800 static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate, 2801 unsigned long prate) 2802 { 2803 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2804 int ret; 2805 u32 l; 2806 u64 a; 2807 2808 rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH); 2809 2810 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2811 2812 a <<= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH; 2813 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2814 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 2815 a >> ALPHA_BITWIDTH); 2816 2817 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 2818 PLL_ALPHA_EN, PLL_ALPHA_EN); 2819 2820 if (!clk_hw_is_enabled(hw)) 2821 return 0; 2822 2823 /* 2824 * Stromer PLL supports Dynamic programming. 2825 * It allows the PLL frequency to be changed on-the-fly without first 2826 * execution of a shutdown procedure followed by a bring up procedure. 2827 */ 2828 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 2829 PLL_UPDATE); 2830 2831 ret = wait_for_pll_update(pll); 2832 if (ret) 2833 return ret; 2834 2835 return wait_for_pll_enable_lock(pll); 2836 } 2837 2838 const struct clk_ops clk_alpha_pll_stromer_ops = { 2839 .enable = clk_alpha_pll_enable, 2840 .disable = clk_alpha_pll_disable, 2841 .is_enabled = clk_alpha_pll_is_enabled, 2842 .recalc_rate = clk_alpha_pll_recalc_rate, 2843 .determine_rate = clk_alpha_pll_stromer_determine_rate, 2844 .set_rate = clk_alpha_pll_stromer_set_rate, 2845 }; 2846 EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops); 2847 2848 static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw, 2849 unsigned long rate, 2850 unsigned long prate) 2851 { 2852 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2853 u32 l, alpha_width = pll_alpha_width(pll); 2854 int ret, pll_mode; 2855 u64 a; 2856 2857 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 2858 2859 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode); 2860 if (ret) 2861 return ret; 2862 2863 regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0); 2864 2865 /* Delay of 2 output clock ticks required until output is disabled */ 2866 udelay(1); 2867 2868 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2869 2870 if (alpha_width > ALPHA_BITWIDTH) 2871 a <<= alpha_width - ALPHA_BITWIDTH; 2872 2873 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2874 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 2875 a >> ALPHA_BITWIDTH); 2876 2877 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 2878 PLL_ALPHA_EN, PLL_ALPHA_EN); 2879 2880 regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL); 2881 2882 /* Wait five micro seconds or more */ 2883 udelay(5); 2884 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, 2885 PLL_RESET_N); 2886 2887 /* The lock time should be less than 50 micro seconds worst case */ 2888 usleep_range(50, 60); 2889 2890 ret = wait_for_pll_enable_lock(pll); 2891 if (ret) { 2892 pr_err("Wait for PLL enable lock failed [%s] %d\n", 2893 clk_hw_get_name(hw), ret); 2894 return ret; 2895 } 2896 2897 if (pll_mode & PLL_OUTCTRL) 2898 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 2899 PLL_OUTCTRL); 2900 2901 return 0; 2902 } 2903 2904 const struct clk_ops clk_alpha_pll_stromer_plus_ops = { 2905 .prepare = clk_alpha_pll_enable, 2906 .unprepare = clk_alpha_pll_disable, 2907 .is_enabled = clk_alpha_pll_is_enabled, 2908 .recalc_rate = clk_alpha_pll_recalc_rate, 2909 .determine_rate = clk_alpha_pll_stromer_determine_rate, 2910 .set_rate = clk_alpha_pll_stromer_plus_set_rate, 2911 }; 2912 EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops); 2913 2914 void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2915 const struct alpha_pll_config *config) 2916 { 2917 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2918 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2919 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2920 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2921 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2922 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2923 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2924 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); 2925 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2926 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2927 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2928 2929 /* Set operation mode to STANDBY */ 2930 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2931 } 2932 EXPORT_SYMBOL_GPL(clk_regera_pll_configure); 2933 2934 const struct clk_ops clk_alpha_pll_regera_ops = { 2935 .enable = clk_zonda_pll_enable, 2936 .disable = clk_zonda_pll_disable, 2937 .is_enabled = clk_alpha_pll_is_enabled, 2938 .recalc_rate = clk_trion_pll_recalc_rate, 2939 .round_rate = clk_alpha_pll_round_rate, 2940 .set_rate = clk_zonda_pll_set_rate, 2941 }; 2942 EXPORT_SYMBOL_GPL(clk_alpha_pll_regera_ops); 2943